| #============================================================================================================================================================= |
| #----------------------------------------------------------- GF 0.18um MCU DRC RULE DECK (5V SRAM) ----------------------------------------------------------- |
| #============================================================================================================================================================= |
| |
| require 'time' |
| require "logger" |
| |
| exec_start_time = Time.now |
| |
| logger = Logger.new(STDOUT) |
| |
| logger.formatter = proc do |severity, datetime, progname, msg| |
| "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} |
| " |
| end |
| |
| #================================================ |
| #----------------- FILE SETUP ------------------- |
| #================================================ |
| |
| # optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb |
| |
| logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) |
| |
| if $input |
| if $topcell |
| source($input, $topcell) |
| else |
| source($input) |
| end |
| end |
| |
| logger.info("Loading database to memory is complete.") |
| |
| if $report |
| logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) |
| report("DRC Run Report at", $report) |
| else |
| logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) |
| report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) |
| end |
| |
| if $thr |
| logger.info("Number of threads to use %s" % [$thr]) |
| threads($thr) |
| else |
| logger.info("Number of threads to use 16") |
| threads(16) |
| end |
| |
| # === TILING MODE === |
| if $run_mode == "tiling" |
| # use a tile size of 1mm - not used in deep mode- |
| # tiles(500.um) |
| # use a tile border of 10 micron: |
| # tile_borders(10.um) |
| tiles(1000) |
| logger.info("Tiling mode is enabled.") |
| |
| elsif $run_mode == "deep" |
| #=== HIER MODE === |
| deep |
| logger.info("deep mode is enabled.") |
| |
| elsif $run_mode == "flat" |
| #=== FLAT MODE === |
| flat |
| logger.info("flat mode is enabled.") |
| |
| else |
| #=== FLAT MODE === |
| flat |
| logger.info("flat mode is enabled.") |
| |
| end # run_mode |
| |
| #================================================ |
| #------------- LAYERS DEFINITIONS --------------- |
| #================================================ |
| |
| v5_xtor = polygons(112, 1 ) |
| dualgate = polygons(55 , 0 ) |
| poly2 = polygons(30 , 0 ) |
| nplus = polygons(32 , 0 ) |
| pplus = polygons(31 , 0 ) |
| comp = polygons(22 , 0 ) |
| dnwell = polygons(12 , 0 ) |
| nwell = polygons(21 , 0 ) |
| lvpwell = polygons(204, 0 ) |
| contact = polygons(33 , 0 ) |
| sramcore = polygons(108, 5 ) |
| |
| logger.info("Starting deriving base layers.") |
| #================================================ |
| #------------- LAYERS DERIVATIONS --------------- |
| #================================================ |
| |
| ncomp = comp & nplus |
| pcomp = comp & pplus |
| tgate = poly2 & comp |
| ngate = nplus & tgate |
| pgate = pplus & tgate |
| |
| #================================================ |
| #------------------ SWITCHES -------------------- |
| #================================================ |
| logger.info("Evaluate switches.") |
| |
| # FEOL |
| if $feol == "false" |
| FEOL = $feol |
| logger.info("FEOL is disabled.") |
| else |
| FEOL = "true" |
| logger.info("FEOL is enabled.") |
| end # FEOL |
| |
| # BEOL |
| if $beol == "false" |
| BEOL = $beol |
| logger.info("BEOL is disabled.") |
| else |
| BEOL = "true" |
| logger.info("BEOL is enabled.") |
| end # BEOL |
| |
| # connectivity rules |
| if $conn_drc == "true" |
| CONNECTIVITY_RULES = $conn_drc |
| logger.info("connectivity rules are enabled.") |
| else |
| CONNECTIVITY_RULES = false |
| logger.info("connectivity rules are disabled.") |
| end # connectivity rules |
| |
| # METAL_TOP |
| if $metal_top |
| METAL_TOP = $metal_top |
| else |
| METAL_TOP = "9K" |
| end # METAL_TOP |
| |
| logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) |
| |
| # METAL_LEVEL |
| if $metal_level |
| METAL_LEVEL = $metal_level |
| else |
| METAL_LEVEL = "6LM" |
| end # METAL_LEVEL |
| |
| logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) |
| |
| # WEDGE |
| if $wedge == "false" |
| WEDGE = $wedge |
| else |
| WEDGE = "true" |
| end # WEDGE |
| |
| logger.info("Wedge enabled %s" % [WEDGE]) |
| |
| # BALL |
| if $ball == "false" |
| BALL = $ball |
| else |
| BALL = "true" |
| end # BALL |
| |
| logger.info("Ball enabled %s" % [BALL]) |
| |
| # GOLD |
| if $gold == "false" |
| GOLD = $gold |
| else |
| GOLD = "true" |
| end # GOLD |
| |
| logger.info("Gold enabled %s" % [GOLD]) |
| |
| if $mim_option |
| MIM_OPTION = $mim_option |
| else |
| MIM_OPTION = "Nan" |
| end |
| |
| logger.info("MIM Option selected %s" % [MIM_OPTION]) |
| |
| # OFFGRID |
| if $offgrid == "false" |
| OFFGRID = false |
| else |
| OFFGRID = true |
| end # OFFGRID |
| |
| logger.info("Offgrid enabled %s" % [OFFGRID]) |
| |
| #================================================ |
| #--------------------5V SRAM--------------------- |
| #================================================ |
| |
| # Rule S.DF.4c_MV: Min. (Nwell overlap of PCOMP) outside DNWELL. is 0.45µm |
| logger.info("Executing rule S.DF.4c_MV") |
| sdf4c_l1 = nwell.outside(dnwell).inside(sramcore).enclosing(pcomp.outside(dnwell).inside(sramcore), 0.45.um, euclidian).polygons(0.001) |
| sdf4c_l2 = pcomp.outside(dnwell).inside(sramcore).not_outside(nwell.outside(dnwell).inside(sramcore)).not(nwell.outside(dnwell).inside(sramcore)) |
| sdf4c_l = sdf4c_l1.or(sdf4c_l2).overlapping(v5_xtor).overlapping(dualgate) |
| sdf4c_l.output("S.DF.4c_MV", "S.DF.4c_MV : Min. (Nwell overlap of PCOMP) outside DNWELL. : 0.45µm") |
| sdf4c_l1.forget |
| sdf4c_l2.forget |
| sdf4c_l.forget |
| |
| # Rule S.DF.6_MV: Min. COMP extend beyond gate (it also means source/drain overhang). is 0.32µm |
| logger.info("Executing rule S.DF.6_MV") |
| sdf6_l1 = comp.inside(sramcore).enclosing(poly2.inside(sramcore), 0.32.um, euclidian).polygons(0.001).overlapping(v5_xtor).overlapping(dualgate) |
| sdf6_l1.output("S.DF.6_MV", "S.DF.6_MV : Min. COMP extend beyond gate (it also means source/drain overhang). : 0.32µm") |
| sdf6_l1.forget |
| |
| # Rule S.DF.7_MV: Min. (LVPWELL Spacer to PCOMP) inside DNWELL. is 0.45µm |
| logger.info("Executing rule S.DF.7_MV") |
| sdf7_l1 = pcomp.inside(dnwell).inside(sramcore).separation(lvpwell.inside(dnwell).inside(sramcore), 0.45.um, euclidian).polygons(0.001).overlapping(v5_xtor).overlapping(dualgate) |
| sdf7_l1.output("S.DF.7_MV", "S.DF.7_MV : Min. (LVPWELL Spacer to PCOMP) inside DNWELL. : 0.45µm") |
| sdf7_l1.forget |
| |
| # Rule S.DF.8_MV: Min. (LVPWELL overlap of NCOMP) Inside DNWELL. is 0.45µm |
| logger.info("Executing rule S.DF.8_MV") |
| sdf8_l1 = lvpwell.inside(dnwell).inside(sramcore).enclosing(ncomp.inside(dnwell).inside(sramcore), 0.45.um, euclidian).polygons(0.001) |
| sdf8_l2 = ncomp.inside(dnwell).inside(sramcore).not_outside(lvpwell.inside(dnwell).inside(sramcore)).not(lvpwell.inside(dnwell).inside(sramcore)) |
| sdf8_l = sdf8_l1.or(sdf8_l2).overlapping(v5_xtor).overlapping(dualgate) |
| sdf8_l.output("S.DF.8_MV", "S.DF.8_MV : Min. (LVPWELL overlap of NCOMP) Inside DNWELL. : 0.45µm") |
| sdf8_l1.forget |
| sdf8_l2.forget |
| sdf8_l.forget |
| |
| # Rule S.DF.16_MV: Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). is 0.45µm |
| logger.info("Executing rule S.DF.16_MV") |
| sdf16_l1 = ncomp.outside(nwell).outside(dnwell).inside(sramcore).separation(nwell.outside(dnwell).inside(sramcore), 0.45.um, euclidian).polygons(0.001).overlapping(v5_xtor).overlapping(dualgate) |
| sdf16_l1.output("S.DF.16_MV", "S.DF.16_MV : Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). : 0.45µm") |
| sdf16_l1.forget |
| |
| # Rule S.PL.5a_MV: Space from field Poly2 to unrelated COMP Spacer from field Poly2 to Guard-ring. is 0.12µm |
| logger.info("Executing rule S.PL.5a_MV") |
| spl5a_l1 = poly2.inside(sramcore).separation(comp.inside(sramcore), 0.12.um, euclidian).polygons(0.001).overlapping(v5_xtor).overlapping(dualgate) |
| spl5a_l1.output("S.PL.5a_MV", "S.PL.5a_MV : Space from field Poly2 to unrelated COMP Spacer from field Poly2 to Guard-ring. : 0.12µm") |
| spl5a_l1.forget |
| |
| # Rule S.PL.5b_MV: Space from field Poly2 to related COMP. is 0.12µm |
| logger.info("Executing rule S.PL.5b_MV") |
| spl5b_l1 = poly2.inside(sramcore).separation(comp.inside(sramcore), 0.12.um, euclidian).polygons(0.001).overlapping(v5_xtor).overlapping(dualgate) |
| spl5b_l1.output("S.PL.5b_MV", "S.PL.5b_MV : Space from field Poly2 to related COMP. : 0.12µm") |
| spl5b_l1.forget |
| |
| # Rule S.CO.4_MV: COMP overlap of contact. is 0.04µm |
| logger.info("Executing rule S.CO.4_MV") |
| sco4_l1 = comp.inside(sramcore).and(v5_xtor).enclosing(contact.inside(sramcore).and(v5_xtor), 0.04.um, euclidian).polygons(0.001) |
| sco4_l2 = contact.inside(sramcore).and(v5_xtor).not_outside(comp.inside(sramcore).and(v5_xtor)).not(comp.inside(sramcore).and(v5_xtor)) |
| sco4_l = sco4_l1.or(sco4_l2) |
| sco4_l.output("S.CO.4_MV", "S.CO.4_MV : COMP overlap of contact. : 0.04µm") |
| sco4_l1.forget |
| sco4_l2.forget |
| sco4_l.forget |
| |
| |
| exec_end_time = Time.now |
| run_time = exec_end_time - exec_start_time |
| logger.info("DRC Run time %f seconds" % [run_time]) |
| |
