| #============================================================================================================================================================= |
| #------------------------------------------------------------ GF 0.18um MCU DRC RULE DECK (VIA4) ------------------------------------------------------------- |
| #============================================================================================================================================================= |
| |
| require 'time' |
| require "logger" |
| |
| exec_start_time = Time.now |
| |
| logger = Logger.new(STDOUT) |
| |
| logger.formatter = proc do |severity, datetime, progname, msg| |
| "#{datetime}: Memory Usage (" + `pmap #{Process.pid} | tail -1`[10,40].strip + ") : #{msg} |
| " |
| end |
| |
| #================================================ |
| #----------------- FILE SETUP ------------------- |
| #================================================ |
| |
| # optional for a batch launch : klayout -b -r gf180mcu.drc -rd input=design.gds -rd report=gf180mcu_main.lyrdb |
| |
| logger.info("Starting running GF180MCU Klayout DRC runset on %s" % [$input]) |
| |
| if $input |
| if $topcell |
| source($input, $topcell) |
| else |
| source($input) |
| end |
| end |
| |
| logger.info("Loading database to memory is complete.") |
| |
| if $report |
| logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) |
| report("DRC Run Report at", $report) |
| else |
| logger.info("GF180MCU Klayout DRC runset output at default location." % [File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb").path]) |
| report("DRC Run Report at", File.join(File.dirname(RBA::CellView::active.filename), "gf180_drc.lyrdb")) |
| end |
| |
| if $thr |
| logger.info("Number of threads to use %s" % [$thr]) |
| threads($thr) |
| else |
| logger.info("Number of threads to use 16") |
| threads(16) |
| end |
| |
| # === TILING MODE === |
| if $run_mode == "tiling" |
| # use a tile size of 1mm - not used in deep mode- |
| # tiles(500.um) |
| # use a tile border of 10 micron: |
| # tile_borders(10.um) |
| tiles(1000) |
| logger.info("Tiling mode is enabled.") |
| |
| elsif $run_mode == "deep" |
| #=== HIER MODE === |
| deep |
| logger.info("deep mode is enabled.") |
| |
| elsif $run_mode == "flat" |
| #=== FLAT MODE === |
| flat |
| logger.info("flat mode is enabled.") |
| |
| else |
| #=== FLAT MODE === |
| flat |
| logger.info("flat mode is enabled.") |
| |
| end # run_mode |
| |
| #================================================ |
| #------------- LAYERS DEFINITIONS --------------- |
| #================================================ |
| |
| v5_xtor = polygons(112, 1 ) |
| dualgate = polygons(55 , 0 ) |
| poly2 = polygons(30 , 0 ) |
| nplus = polygons(32 , 0 ) |
| pplus = polygons(31 , 0 ) |
| comp = polygons(22 , 0 ) |
| metal4 = polygons(46 , 0 ) |
| via4 = polygons(41 , 0 ) |
| metal5 = polygons(81 , 0 ) |
| |
| logger.info("Starting deriving base layers.") |
| #================================================ |
| #------------- LAYERS DERIVATIONS --------------- |
| #================================================ |
| |
| ncomp = comp & nplus |
| pcomp = comp & pplus |
| tgate = poly2 & comp |
| ngate = nplus & tgate |
| pgate = pplus & tgate |
| |
| #================================================ |
| #------------------ SWITCHES -------------------- |
| #================================================ |
| logger.info("Evaluate switches.") |
| |
| # FEOL |
| if $feol == "false" |
| FEOL = $feol |
| logger.info("FEOL is disabled.") |
| else |
| FEOL = "true" |
| logger.info("FEOL is enabled.") |
| end # FEOL |
| |
| # BEOL |
| if $beol == "false" |
| BEOL = $beol |
| logger.info("BEOL is disabled.") |
| else |
| BEOL = "true" |
| logger.info("BEOL is enabled.") |
| end # BEOL |
| |
| # connectivity rules |
| if $conn_drc == "true" |
| CONNECTIVITY_RULES = $conn_drc |
| logger.info("connectivity rules are enabled.") |
| else |
| CONNECTIVITY_RULES = false |
| logger.info("connectivity rules are disabled.") |
| end # connectivity rules |
| |
| # METAL_TOP |
| if $metal_top |
| METAL_TOP = $metal_top |
| else |
| METAL_TOP = "9K" |
| end # METAL_TOP |
| |
| logger.info("METAL_TOP Selected is %s" % [METAL_TOP]) |
| |
| # METAL_LEVEL |
| if $metal_level |
| METAL_LEVEL = $metal_level |
| else |
| METAL_LEVEL = "6LM" |
| end # METAL_LEVEL |
| |
| logger.info("METAL_STACK Selected is %s" % [METAL_LEVEL]) |
| |
| # WEDGE |
| if $wedge == "false" |
| WEDGE = $wedge |
| else |
| WEDGE = "true" |
| end # WEDGE |
| |
| logger.info("Wedge enabled %s" % [WEDGE]) |
| |
| # BALL |
| if $ball == "false" |
| BALL = $ball |
| else |
| BALL = "true" |
| end # BALL |
| |
| logger.info("Ball enabled %s" % [BALL]) |
| |
| # GOLD |
| if $gold == "false" |
| GOLD = $gold |
| else |
| GOLD = "true" |
| end # GOLD |
| |
| logger.info("Gold enabled %s" % [GOLD]) |
| |
| if $mim_option |
| MIM_OPTION = $mim_option |
| else |
| MIM_OPTION = "Nan" |
| end |
| |
| logger.info("MIM Option selected %s" % [MIM_OPTION]) |
| |
| # OFFGRID |
| if $offgrid == "false" |
| OFFGRID = false |
| else |
| OFFGRID = true |
| end # OFFGRID |
| |
| logger.info("Offgrid enabled %s" % [OFFGRID]) |
| |
| #================================================ |
| #----------------------VIA4---------------------- |
| #================================================ |
| |
| |
| if BEOL |
| logger.info("BEOL section") |
| |
| # Rule V4.1: Min/max Via4 size . is 0.26µm |
| logger.info("Executing rule V4.1") |
| v41_l1 = via4.edges.without_length(0.26.um).extended(0, 0, 0.001, 0.001) |
| v41_l1.output("V4.1", "V4.1 : Min/max Via4 size . : 0.26µm") |
| v41_l1.forget |
| |
| # Rule V4.2a: min. via4 spacing is 0.26µm |
| logger.info("Executing rule V4.2a") |
| v42a_l1 = via4.space(0.26.um, euclidian).polygons(0.001) |
| v42a_l1.output("V4.2a", "V4.2a : min. via4 spacing : 0.26µm") |
| v42a_l1.forget |
| |
| merged_via4 = via4.sized(0.18.um).sized(-0.18.um).with_bbox_min(1.82.um , nil).extents.inside(metal4) |
| via4_mask = merged_via4.size(1).not(via4).with_holes(16, nil) |
| selected_via4 = via4.interacting(via4_mask) |
| # Rule V4.2b: Via4 Space in 4x4 or larger Vian array is 0.36µm |
| logger.info("Executing rule V4.2b") |
| v42b_l1 = selected_via4.space(0.36.um, euclidian).polygons(0.001) |
| v42b_l1.output("V4.2b", "V4.2b : Via4 Space in 4x4 or larger Vian array : 0.36µm") |
| v42b_l1.forget |
| |
| merged_via4.forget |
| via4_mask.forget |
| selected_via4.forget |
| # rule V4.3a is not a DRC check |
| |
| # Rule V4.3b: metal4 overlap of via4. |
| logger.info("Executing rule V4.3b") |
| v43b_l1 = metal4.enclosing(via4, 0.01.um, euclidian).polygons(0.001).or(via4.not(metal4)) |
| v43b_l1.output("V4.3b", "V4.3b : metal4 overlap of via4.") |
| v43b_l1.forget |
| |
| v4p3c_cond = metal4.drc( width <= 0.34.um).with_length(0.28.um,nil,both) |
| v4p3c_eol = metal4.edges.with_length(nil, 0.34.um).interacting(v4p3c_cond.first_edges).interacting(v4p3c_cond.second_edges).not(v4p3c_cond.first_edges).not(v4p3c_cond.second_edges) |
| # Rule V4.3c: metal4 (< 0.34um) end-of-line overlap. is 0.06µm |
| logger.info("Executing rule V4.3c") |
| v43c_l1 = v4p3c_eol.enclosing(via4.edges,0.06.um, projection).polygons(0.001) |
| v43c_l1.output("V4.3c", "V4.3c : metal4 (< 0.34um) end-of-line overlap. : 0.06µm") |
| v43c_l1.forget |
| |
| v4p3c_cond.forget |
| v4p3c_eol.forget |
| v4_3d_1 = via4.edges.interacting(via4.drc(enclosed(metal4, projection) < 0.04.um).edges.centers(0, 0.5)) |
| v4_3d_2 = via4.edges.interacting(via4.drc(0.04.um <= enclosed(metal4, projection) < 0.06.um).centers(0, 0.5)) |
| v4_3d_3 = v4_3d_1.extended(0, 0, 0, 0.001, joined).corners(90) |
| # Rule V4.3d: If metal4 overlap Vian by < 0.04um on one side, adjacent metal4 edges overlap. is 0.06µm |
| logger.info("Executing rule V4.3d") |
| v43d_l1 = v4_3d_2.not_in(v4_3d_1).interacting(v4_3d_1).or(v4_3d_1.interacting(v4_3d_3)).enclosed(metal4.edges, 0.06.um).polygons(0.001) |
| v43d_l1.output("V4.3d", "V4.3d : If metal4 overlap Vian by < 0.04um on one side, adjacent metal4 edges overlap. : 0.06µm") |
| v43d_l1.forget |
| |
| v4_3d_1.forget |
| v4_3d_2.forget |
| v4_3d_3.forget |
| # rule V4.3e is not a DRC check |
| |
| # Rule V4.4a: metal5 overlap of via4. |
| logger.info("Executing rule V4.4a") |
| v44a_l1 = metal5.enclosing(via4, 0.01.um, euclidian).polygons(0.001).or(via4.not(metal5)) |
| v44a_l1.output("V4.4a", "V4.4a : metal5 overlap of via4.") |
| v44a_l1.forget |
| |
| v4p4b_cond = metal5.drc( width <= 0.34.um).with_length(0.28.um,nil,both) |
| v4p4b_eol = metal5.edges.with_length(nil, 0.34.um).interacting(v4p4b_cond.first_edges).interacting(v4p4b_cond.second_edges).not(v4p4b_cond.first_edges).not(v4p4b_cond.second_edges) |
| # Rule V4.4b: metal5 (< 0.34um) end-of-line overlap. is 0.06µm |
| logger.info("Executing rule V4.4b") |
| v44b_l1 = v4p4b_eol.enclosing(via4.edges,0.06.um, projection).polygons(0.001) |
| v44b_l1.output("V4.4b", "V4.4b : metal5 (< 0.34um) end-of-line overlap. : 0.06µm") |
| v44b_l1.forget |
| |
| v4p4b_cond.forget |
| v4p4b_eol.forget |
| v4_4c_1 = via4.edges.interacting(via4.drc(enclosed(metal5, projection) < 0.04.um).edges.centers(0, 0.5)) |
| v4_4c_2 = via4.edges.interacting(via4.drc(0.04.um <= enclosed(metal5, projection) < 0.06.um).centers(0, 0.5)) |
| v4_4c_3 = v4_4c_1.extended(0, 0, 0, 0.001, joined).corners(90) |
| # Rule V4.4c: If metal5 overlap via4 by < 0.04um on one side, adjacent metal5 edges overlap. is 0.06µm |
| logger.info("Executing rule V4.4c") |
| v44c_l1 = v4_4c_2.not_in(v4_4c_1).interacting(v4_4c_1).or(v4_4c_1.interacting(v4_4c_3)).enclosed(metal5.edges, 0.06.um).polygons(0.001) |
| v44c_l1.output("V4.4c", "V4.4c : If metal5 overlap via4 by < 0.04um on one side, adjacent metal5 edges overlap. : 0.06µm") |
| v44c_l1.forget |
| |
| v4_4c_1.forget |
| v4_4c_2.forget |
| v4_4c_3.forget |
| # rule V4.4d is not a DRC check |
| |
| # rule V4.5 is not a DRC check |
| |
| |
| end #BEOL |
| |
| |
| exec_end_time = Time.now |
| run_time = exec_end_time - exec_start_time |
| logger.info("DRC Run time %f seconds" % [run_time]) |
| |
