Google Git
Sign in
foss-eda-tools / third_party / shuttle / sky130 / mpw-008 / slot-005 / 3c8175cc386e54282bc01faeec4cdcee07bce973 / . / verilog / dv / user_i2cm / Makefile
blob: b2bfe321e92cfcd4d2e9c5929d3714e8170a3bf9 [file] [log] [blame]
dineshannayya62e46322022-02-15 14:19:56 +0530[diff] [blame]1# SPDX-FileCopyrightText: 2020 Efabless Corporation
2#
3# Licensed under the Apache License, Version 2.0 (the "License");
4# you may not use this file except in compliance with the License.
5# You may obtain a copy of the License at
6#
7# http://www.apache.org/licenses/LICENSE-2.0
8#
9# Unless required by applicable law or agreed to in writing, software
10# distributed under the License is distributed on an "AS IS" BASIS,
11# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12# See the License for the specific language governing permissions and
13# limitations under the License.
14#
15# SPDX-License-Identifier: Apache-2.0
16
dineshannayya62e46322022-02-15 14:19:56 +0530[diff] [blame]17
dineshannayyad8a093b2022-03-26 08:32:19 +0530[diff] [blame]18# ---- Include Partitioned Makefiles ----
dineshannayya62e46322022-02-15 14:19:56 +0530[diff] [blame]19
dineshannayyad8a093b2022-03-26 08:32:19 +0530[diff] [blame]20CONFIG = caravel_user_project
21
22#######################################################################
23## Caravel Verilog for Integration Tests
24#######################################################################
dineshannayya62e46322022-02-15 14:19:56 +0530[diff] [blame]25
dineshannayyad8a093b2022-03-26 08:32:19 +0530[diff] [blame]26DESIGNS?=../../..
dineshannayyacf0fda02022-07-08 10:53:25 +0530[diff] [blame]27TOOLS?=/opt/riscv32i/
dineshannayyad8a093b2022-03-26 08:32:19 +0530[diff] [blame]28
29export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
dineshannayya7700e3c2022-06-01 11:36:21 +0530[diff] [blame]30## YIFIVE FIRMWARE
31YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
dineshannayyacf0fda02022-07-08 10:53:25 +0530[diff] [blame]32GCC_PREFIX?=riscv32-unknown-elf
dineshannayya62e46322022-02-15 14:19:56 +0530[diff] [blame]33
dineshannayya62e46322022-02-15 14:19:56 +0530[diff] [blame]34
35## Simulation mode: RTL/GL
36SIM?=RTL
37DUMP?=OFF
38
dineshannayyad8a093b2022-03-26 08:32:19 +0530[diff] [blame]39### To Enable IVERILOG FST DUMP
40export IVERILOG_DUMPER = fst
41
42
dineshannayya62e46322022-02-15 14:19:56 +0530[diff] [blame]43.SUFFIXES:
44
45PATTERN = user_i2cm
46
47all: ${PATTERN:=.vcd}
48
dineshannayya62e46322022-02-15 14:19:56 +0530[diff] [blame]49
50vvp: ${PATTERN:=.vvp}
51
52%.vvp: %_tb.v
dineshannayya62e46322022-02-15 14:19:56 +0530[diff] [blame]53ifeq ($(SIM),RTL)
54 ifeq ($(DUMP),OFF)
dineshannayyad8a093b2022-03-26 08:32:19 +0530[diff] [blame]55 iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
56 -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
dineshannayya7700e3c2022-06-01 11:36:21 +0530[diff] [blame]57 -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
dineshannayya62e46322022-02-15 14:19:56 +0530[diff] [blame]58 $< -o $@
59 else
dineshannayyad8a093b2022-03-26 08:32:19 +0530[diff] [blame]60 iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
61 -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
dineshannayya7700e3c2022-06-01 11:36:21 +0530[diff] [blame]62 -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
dineshannayya62e46322022-02-15 14:19:56 +0530[diff] [blame]63 $< -o $@
64 endif
65else
dineshannayya93c82cc2022-04-10 12:40:06 +0530[diff] [blame]66 ifeq ($(DUMP),OFF)
67 iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
68 -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
dineshannayya7700e3c2022-06-01 11:36:21 +0530[diff] [blame]69 -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
dineshannayya62e46322022-02-15 14:19:56 +0530[diff] [blame]70 $< -o $@
dineshannayya93c82cc2022-04-10 12:40:06 +0530[diff] [blame]71 else
72 iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
73 -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
dineshannayya7700e3c2022-06-01 11:36:21 +0530[diff] [blame]74 -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
dineshannayya93c82cc2022-04-10 12:40:06 +0530[diff] [blame]75 $< -o $@
76 endif
dineshannayya62e46322022-02-15 14:19:56 +0530[diff] [blame]77endif
78
79%.vcd: %.vvp
80 vvp $<
81
dineshannayya62e46322022-02-15 14:19:56 +0530[diff] [blame]82
83# ---- Clean ----
84
85clean:
dineshannayya93c82cc2022-04-10 12:40:06 +0530[diff] [blame]86 rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump *.fst
dineshannayya62e46322022-02-15 14:19:56 +0530[diff] [blame]87
88.PHONY: clean hex all