gatesim setup cleanup
diff --git a/verilog/dv/user_i2cm/Makefile b/verilog/dv/user_i2cm/Makefile
index e7d9b13..a801f55 100644
--- a/verilog/dv/user_i2cm/Makefile
+++ b/verilog/dv/user_i2cm/Makefile
@@ -26,9 +26,6 @@
DESIGNS?=../../..
export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
-## YIFIVE FIRMWARE
-YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
-GCC64_PREFIX?=riscv64-unknown-elf
## Simulation mode: RTL/GL
@@ -45,7 +42,6 @@
all: ${PATTERN:=.vcd}
-hex: ${PATTERN:=.hex}
vvp: ${PATTERN:=.vvp}
@@ -61,9 +57,15 @@
$< -o $@
endif
else
- iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
- -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
$< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ $< -o $@
+ endif
endif
%.vcd: %.vvp
@@ -73,6 +75,6 @@
# ---- Clean ----
clean:
- rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump *.fst
.PHONY: clean hex all
