commit cf0fda0d726bc02c1f0927de3fb6ce89ed2acff6
author dineshannayya <dinesh.annayya@gmail.com> Fri Jul 08 10:53:25 2022 +0530
committer dineshannayya <dinesh.annayya@gmail.com> Fri Jul 08 10:53:25 2022 +0530
tree 17f774a062ce33cf650561aa68f5c502f1016deb
parent 040fe6b98809fd4460c4901c9689de0ba44ba83e

arduino test case integration

verilog/dv/user_i2cm/Makefile

diff --git a/verilog/dv/user_i2cm/Makefile b/verilog/dv/user_i2cm/Makefile
index f01c09d..b2bfe32 100644
--- a/verilog/dv/user_i2cm/Makefile
+++ b/verilog/dv/user_i2cm/Makefile
@@ -24,12 +24,12 @@
 #######################################################################
 
 DESIGNS?=../../..
-TOOLS?=/opt/riscv64i/
+TOOLS?=/opt/riscv32i/
 
 export USER_PROJECT_VERILOG ?=  $(DESIGNS)/verilog
 ## YIFIVE FIRMWARE
 YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
-GCC64_PREFIX?=riscv64-unknown-elf
+GCC_PREFIX?=riscv32-unknown-elf
 
 
 ## Simulation mode: RTL/GL