commit	7700e3cc44e2f5bcb2c230210cdc55d48f88235b	[log] [tgz]
author	dineshannayya <dinesh.annayya@gmail.com>	Wed Jun 01 11:36:21 2022 +0530
committer	dineshannayya <dinesh.annayya@gmail.com>	Wed Jun 01 11:36:21 2022 +0530
tree	2a58f863fa7699864d379f02f57ac4643a67d985
parent	eaa0c9009a5e04598b46627d2d449b6d86d77b78 [diff]

tree: 2a58f863fa7699864d379f02f57ac4643a67d985

README.md

  Riscduino Quad Risc Core SOC


Permission to use, copy, modify, and/or distribute this soc for any
purpose with or without fee is hereby granted, provided that the above
copyright notice and this permission notice appear in all copies.

THE SOC IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
WITH REGARD TO THIS SOC INCLUDING ALL IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOC.

Overview
Riscduino Block Diagram
Key Feature
Riscduino derivatives
MPW Shuttle on Riscduino
Sub IP Feature
SOC Memory Map
Pin Mapping
Repository contents
Prerequisites
Tests preparation
- Running Simuation
Tool sets
News
Contacts
How To Contribute
Documentation

Overview

Riscduino is a Quad 32 bit RISC V based SOC design pin compatible to arudino platform and this soc targetted for efabless Shuttle program. This project uses only open source tool set for simulation,synthesis and backend tools. The SOC flow follow the openlane methodology and SOC environment is compatible with efabless/carvel methodology.

Riscduino Block Diagram

Key features

    * Open sourced under Apache-2.0 License (see LICENSE file) - unrestricted commercial use allowed.
    * Quad Core  32 Bit RISC-V core
    * 2KB SRAM for instruction cache 
    * 2KB SRAM for data cache
    * 2KB SRAM for Tightly coupled memory - For Data Memory
    * Quad SPI Master with 4 Chip select, supports both SPI flash and SRAM interface
    * 2 x UART with 16Byte FIFO
    * USB 1.1 Host
    * I2C Master
    * UART Master
    * Simple SPI Master with 4 Chip select
    * 6 Channel ADC (in Progress)
    * 6 x PWM
    * 3 x Timer (16 Bit), 1us/1ms/1second resolution
    * Pin Compatbible to arudino uno
    * Wishbone compatible design
    * Written in System Verilog
    * Open-source tool set
       * simulation - iverilog
       * synthesis  - yosys
       * backend/sta - openlane tool set
    * Verification suite provided.

Riscduino derivatives

MPW Shuttle on Riscduino

SOC Pin Mapping

Carvel SOC provides 38 GPIO pins for user functionality. Riscduino SOC GPIO Pin Mapping as follows vs ATMEGA328 and Arudino

RISC V Core

Riscduino SOC Integrated Quad 32 Bits RISC V core. Initial version of Single core RISC-V core is picked from Syntacore SCR1 (https://github.com/syntacore/scr1)

RISC V core customization for Riscduino SOC

Following Design changes are done on the basic version of syntacore RISC core

   * Some of the sv syntex are changed to standard verilog format to make compatibile with opensource tool iverilog & yosys
   * local Instruction Memory is increased from 4 to 8 location
   * Instruction Request are changed from Single word to 4 Word Burst
   * Multiplication and Divsion are changed to improve timing
   * Additional pipe line stages added to improve the RISC timing closure near to 50Mhz
   * 2KB instruction cache 
   * 2KB data cache
   * Additional router are added towards instruction cache
   * Additional router are added towards data cache
   * Quad core related changes
   * Modified AXI/AHB interface to wishbone interface for instruction and data memory interface

Block Diagram

RISC V Core Key feature

   * RV32I or RV32E ISA base + optional RVM and RVC standard extensions
   * Machine privilege mode only
   * 2 to 5 stage pipeline
   * 2KB icache
   * 2KB dcache
   * Optional Integrated Programmable Interrupt Controller with 16 IRQ lines
   * Optional RISC-V Debug subsystem with JTAG interface
   * Optional on-chip Tightly-Coupled Memory

6 Channel SAR ADC

In Process - Looking for community help ...

SOC Memory Map

SOC Size

Block	Total Cell	Seq	Combo
RISC	20982	3164	17818
PINMUX	5693	1022	4671
SPI	7120	1281	5839
UART_I2C_USB_SPI	11196	2448	8748
WB_HOST	2796	588	2208
WB_INTC	1878	108	1770
SAR_ADC	118	18	100
MBIST	3125	543	2582

TOTAL	52908	9172	43736

SOC Register Map

Register Map: Wishbone HOST

Offset	Name	Description
0x00	GLBL_CTRL	[RW] Global Wishbone Access Control Register
0x04	BANK_CTRL	[RW] Bank Selection, MSB 8 bit Address
0x08	CLK_SKEW_CTRL1	[RW] Clock Skew Control2
0x0c	CLK_SKEW_CTRL2	[RW] Clock Skew Control2

Register: GLBL_CTRL

Bits	Name	Description
31:24	Resevered	Unsused
23:20	RTC_CLK_CTRL	RTC Clock Div Selection
19:16	CPU_CLK_CTRL	CPU Clock Div Selection
15:12	SDARM_CLK_CTRL	SDRAM Clock Div Selection
10:8	WB_CLK_CTRL	Core Wishbone Clock Div Selection
7	UART_I2C_SEL	0 - UART , 1 - I2C Master IO Selection
5	I2C_RST	I2C Reset Control
4	UART_RST	UART Reset Control
3	SDRAM_RST	SDRAM Reset Control
2	SPI_RST	SPI Reset Control
1	CPU_RST	CPU Reset Control
0	WB_RST	Wishbone Core Reset Control

Register: BANK_CTRL

Bits	Name	Description
31:24	Resevered	Unsused
7:0	BANK_SEL	Holds the upper 8 bit address core Wishbone Address

Register: CLK_SKEW_CTRL1

Bits	Name	Description
31:28	Resevered	Unsused
27:24	CLK_SKEW_WB	WishBone Core Clk Skew Control
23:20	CLK_SKEW_GLBL	Glbal Register Clk Skew Control
19:16	CLK_SKEW_SDRAM	SDRAM Clk Skew Control
15:12	CLK_SKEW_SPI	SPI Clk Skew Control
11:8	CLK_SKEW_UART	UART/I2C Clk Skew Control
7:4	CLK_SKEW_RISC	RISC Clk Skew Control
3:0	CLK_SKEW_WI	Wishbone Clk Skew Control

Register Map: SPI MASTER

Offset	Name	Description
0x00	GLBL_CTRL	[RW] Global SPI Access Control Register
0x04	DMEM_CTRL1	[RW] Direct SPI Memory Access Control Register1
0x08	DMEM_CTRL2	[RW] Direct SPI Memory Access Control Register2
0x0c	IMEM_CTRL1	[RW] Indirect SPI Memory Access Control Register1
0x10	IMEM_CTRL2	[RW] Indirect SPI Memory Access Control Register2
0x14	IMEM_ADDR	[RW] Indirect SPI Memory Address
0x18	IMEM_WDATA	[W] Indirect SPI Memory Write Data
0x1c	IMEM_RDATA	[R] Indirect SPI Memory Read Data
0x20	SPI_STATUS	[R] SPI Debug Status

Register: GLBL_CTRL

Bits	Name	Description
31:16	Resevered	Unsused
15:8	SPI_CLK_DIV	SPI Clock Div Rato Selection
7:4	Reserved	Unused
3:2	CS_LATE	CS DE_ASSERTION CONTROL
1:0	CS_EARLY	CS ASSERTION CONTROL

Register: DMEM_CTRL1

Bits	Name	Description
31:9	Resevered	Unsused
8	FSM_RST	Direct Mem State Machine Reset
7:6	SPI_SWITCH	Phase at which SPI Mode need to switch
5:4	SPI_MODE	SPI Mode, 0 - Single, 1 - Dual, 2 - Quad, 3 - QDDR
3:0	CS_SELECT	CHIP SELECT

Register: DMEM_CTRL2

Bits	Name	Description
31:24	DATA_CNT	Total Data Byte Count
23:22	DUMMY_CNT	Total Dummy Byte Count
21:20	ADDR_CNT	Total Address Byte Count
19:16	SPI_SEQ	SPI Access Sequence
15:8	MODE_REG	Mode Register Value
7:0	CMD_REG	Command Register Value

Register: IMEM_CTRL1

Bits	Name	Description
31:9	Resevered	Unsused
8	FSM_RST	InDirect Mem State Machine Reset
7:6	SPI_SWITCH	Phase at which SPI Mode need to switch
5:4	SPI_MODE	SPI Mode, 0 - Single, 1 - Dual, 2 - Quad, 3 - QDDR
3:0	CS_SELECT	CHIP SELECT

Register: IMEM_CTRL2

Bits	Name	Description
31:24	DATA_CNT	Total Data Byte Count
23:22	DUMMY_CNT	Total Dummy Byte Count
21:20	ADDR_CNT	Total Address Byte Count
19:16	SPI_SEQ	SPI Access Sequence
15:8	MODE_REG	Mode Register Value
7:0	CMD_REG	Command Register Value

Register: IMEM_ADDR

Bits	Name	Description
31:0	ADDR	Indirect Memory Address

Register: IMEM_WDATA

Bits	Name	Description
31:0	WDATA	Indirect Memory Write Data

Register: IMEM_RDATA

Bits	Name	Description
31:0	RDATA	Indirect Memory Read Data

Register: SPI_STATUS

Bits	Name	Description
31:0	DEBUG	SPI Debug Status

Register Map: Global Register

Offset	Name	Description
0x00	SOFT_REG0	[RW] Software Register0
0x04	RISC_FUSE	[RW] Risc Fuse Value
0x08	SOFT_REG2	[RW] Software Register2
0x0c	INTR_CTRL	[RW] Interrupt Control
0x10	SDRAM_CTRL1	[RW] Indirect SPI Memory Access Control Register2
0x14	SDRAM_CTRL2	[RW] Indirect SPI Memory Address
0x18	SOFT_REG6	[RW] Software Register6
0x1C	SOFT_REG7	[RW] Software Register7
0x20	SOFT_REG8	[RW] Software Register8
0x24	SOFT_REG9	[RW] Software Register9
0x28	SOFT_REG10	[RW] Software Register10
0x2C	SOFT_REG11	[RW] Software Register11
0x30	SOFT_REG12	[RW] Software Register12
0x34	SOFT_REG13	[RW] Software Register13
0x38	SOFT_REG14	[RW] Software Register14
0x3C	SOFT_REG15	[RW] Software Register15

Register: RISC_FUSE

Bits	Name	Description
31:0	RISC_FUSE	RISC Core Fuse Value

Register: INTR_CTRL

Bits	Name	Description
31:20	Reserved	Unused
19:17	USER_IRQ	User Interrupt generation toward riscv
16	SOFT_IRQ	Software Interrupt generation toward riscv
15:0	EXT_IRQ	External Interrupt generation toward riscv

Repository contents

|verilog
|   ├─  rtl
|   |     |-  syntacore
|   |     |     |─  scr1
|   |     |     |    ├─ **docs**                           | **SCR1 documentation**
|   |     |     |    |      ├─ scr1_eas.pdf                | SCR1 External Architecture Specification
|   |     |     |    |      └─ scr1_um.pdf                 | SCR1 User Manual
|   |     |     |    |─  **src**                           | **SCR1 RTL source and testbench files**
|   |     |     |    |   ├─ includes                       | Header files
|   |     |     |    |   ├─ core                           | Core top source files
|   |     |     |    |   ├─ top                            | Cluster source files
|   |     |     |    |─  **synth**                         | **SCR1 RTL Synthesis files **
|   |     |- Qspi_master
|   |     |     |- src                                     | Qard SPI Master Source files
|   |     |-wb_interconnect
|   |     |     |- src                                     | 3x4 Wishbone Interconnect
|   |     |- digital_core
|   |     |     |- src                                     | Digital core Source files
|   |     |- lib                                           | common library source files
|   |- dv
|   |   |- la_test1                                        | carevel LA test
|   |   |- risc_boot                                       | user core risc boot test
|   |   |- wb_port                                         | user wishbone test
|   |   |- user_risc_boot                                  | user standalone test without carevel soc
|   |- gl                                                  | ** GLS Source files **
|
|- openlane
    |- spi_master                                          | spi_master openlane scripts   
    |- syntacore                                           | Risc Core openlane scripts   
    |- user_project_wrapper                                | carvel user project wrapper

Prerequisites

Docker (ensure docker daemon is running) -- tested with version 19.03.12, but any recent version should suffice.

Step-1: Docker in ubuntu 20.04 version

   sudo apt update
   sudo apt-get install apt-transport-https curl rtificates -agent software-properties-common
   curl -fsSL https://download.docker.com/linux/ubuntu/gpg | sudo apt-key add -
   sudo add-apt-repository "deb [arch=amd64] https://download.docker.com/linux/ubuntu focal stable"
   sudo apt update
   apt-cache policy docker-ce
   sudo apt install docker-ce

   #Add User Name to docker
   sudo usermod -aG docker <your user name>
   # Reboot the system to enable the docker setup

Step-2: Update the Submodule, To to project area

   git submodule init
   git submodule update

Step-3: clone Openlane scripts under workarea

   git clone https://github.com/The-OpenROAD-Project/OpenLane.git

Step-4: add Environment setting

    export CARAVEL_ROOT=<Carvel Installed Path>
    export OPENLANE_ROOT=<OpenLane Installed Path>
    export OPENLANE_IMAGE_NAME=efabless/openlane:latest
    export PDK_ROOT=<PDK Installed PATH>
    export PDK_PATH=<PDK Install Path>/sky130A

Step-5: To install the PDK

   source ~/.bashrc
   cd OpenLane
   make pdk

Tests preparation

The simulation package includes the following tests:

risc_boot - Simple User Risc core boot
wb_port - User Wishbone validation
user_risc_boot - Standalone User Risc core boot
user_mbist_test1 - Standalone MBIST test
user_spi - Standalone SPI test
user_i2c - Standalone I2C test
user_risc_soft_boot - Standalone Risc with SRAM as Boot

Running Simulation

Examples:

    make verify-wb_port  
    make verify-risc_boot
    make verify-uart_master
    make verify-user_basic
    make verify-user_uart
    make verify-user_uart1
    make verify-user_spi
    make verify-user_i2cm
    make verify-user_risc_boot
    make verify-user_pwm
    make verify-user_timer
    make verify-user_sspi
    make verify-user_qspi
    make verify-user_usb
    make verify-user_uart_master
    make verify-wb_port SIM=RTL DUMP=OFF
    make verify-wb_port SIM=RTL DUMP=ON
    make verify-riscv_regress

Tool Sets

Riscduino Soc flow uses Openlane tool sets.

Synthesis
1. yosys - Performs RTL synthesis
2. abc - Performs technology mapping
3. OpenSTA - Pefroms static timing analysis on the resulting netlist to generate timing reports
Floorplan and PDN
1. init_fp - Defines the core area for the macro as well as the rows (used for placement) and the tracks (used for routing)
2. ioplacer - Places the macro input and output ports
3. pdn - Generates the power distribution network
4. tapcell - Inserts welltap and decap cells in the floorplan
Placement
1. RePLace - Performs global placement
2. Resizer - Performs optional optimizations on the design
3. OpenPhySyn - Performs timing optimizations on the design
4. OpenDP - Perfroms detailed placement to legalize the globally placed components
CTS
1. TritonCTS - Synthesizes the clock distribution network (the clock tree)
Routing
1. FastRoute - Performs global routing to generate a guide file for the detailed router
2. CU-GR - Another option for performing global routing.
3. TritonRoute - Performs detailed routing
4. SPEF-Extractor - Performs SPEF extraction
GDSII Generation
1. Magic - Streams out the final GDSII layout file from the routed def
2. Klayout - Streams out the final GDSII layout file from the routed def as a back-up
Checks
1. Magic - Performs DRC Checks & Antenna Checks
2. Klayout - Performs DRC Checks
3. Netgen - Performs LVS Checks
4. CVC - Performs Circuit Validity Checks

News

Riscduino Aim - https://www.youtube.com/watch?v=lFVnicPhTI0

How To Contribute

We are looking for community help in following activity, interested user can ping me in efabless slack platform

Analog Design - ADC, DAC, PLL,
Digital Design - New IP Integration, Encription,DSP, Floating point functions
Verification - Improving the Verification flow
Linux Porting - Build Root integration
Arudino Software Update - Tool Customisation for Riscduino, Adding additional plug-in and Riscv compilation support
Riscv Simulator - integration to Riscduino
Any other ideas

Contacts

Report an issue: https://github.com/dineshannayya/riscduino_qcore/issues

Documentation

Syntacore Link - https://github.com/syntacore/scr1

News on Riscduino

Riscduino Aim - https://www.youtube.com/watch?v=lFVnicPhTI0

Table of contents

Overview

Riscduino Block Diagram

Key features

Riscduino derivatives

MPW Shuttle on Riscduino

SOC Pin Mapping

RISC V Core

RISC V core customization for Riscduino SOC

Block Diagram

RISC V Core Key feature

6 Channel SAR ADC

SOC Memory Map

SOC Size

SOC Register Map

Register Map: Wishbone HOST

Register: GLBL_CTRL

Register: BANK_CTRL

Register: CLK_SKEW_CTRL1

Register Map: SPI MASTER

Register: GLBL_CTRL

Register: DMEM_CTRL1

Register: DMEM_CTRL2

Register: IMEM_CTRL1

Register: IMEM_CTRL2

Register: IMEM_ADDR

Register: IMEM_WDATA

Register: IMEM_RDATA

Register: SPI_STATUS

Register Map: Global Register

Register: RISC_FUSE

Register: INTR_CTRL

Repository contents

Prerequisites

Step-1: Docker in ubuntu 20.04 version

Step-2: Update the Submodule, To to project area

Step-3: clone Openlane scripts under workarea

Step-4: add Environment setting

Step-5: To install the PDK

Tests preparation

Running Simulation

Tool Sets

News

How To Contribute

Contacts

Documentation

News on Riscduino