blob: 212737fe5091118db349051fada916d3839fea8f [file] [log] [blame]
//_\TLV_version 1d: tl-x.org, generated by SandPiper(TM) 1.12-2022/01/27-beta
`include "sp_verilog.vh" //_\SV
// =========================================
// Welcome! Try the tutorials via the menu.
// =========================================
// Default Makerchip TL-Verilog Code Template
// Macro providing required top-level module definition, random
// stimulus support, and Verilator config.
module wb_interface(input wb_clk_i,
input wb_rst_i,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
input [3:0] wbs_sel_i,
input [31:0] wbs_dat_i,
input [31:0] wbs_adr_i,
input dmem_enb,
input [7:0] dmem_addrb,
input [31:0] dmem_doutb,
output clk0,
output csb0,
output web0,
output [3:0] wmask0,
output [31:0] din0,
output [8:0] addr0,
output imem_rd_cs1,
output wbs_ack_o,
output [7:0] dmem_addrb_o,
output [31:0] wbs_dat_o,
output processor_reset);
wire clk;
assign clk = wb_clk_i;
`include "wb_interface_gen.v" //_\TLV
assign wbs_dat_o = dmem_doutb;
assign dmem_addrb_o = dmem_enb ? wbs_adr_i[7:0] : dmem_addrb;
assign L0_valid_addr_a0 = wbs_adr_i[31:11] == 21'b0011_0000_0000_0000_0000_0;
assign processor_reset = ((wbs_adr_i[31:28] == 4'h3) && (wbs_adr_i[11] == 1)) ? wbs_dat_i[0] : '0;
assign L0_valid_a0 = wbs_cyc_i && wbs_stb_i;
assign L0_ready_a0 = L0_valid_a0 && !L0_ready_a1;
assign clk0 = wb_clk_i;
assign csb0 = (L0_valid_addr_a0 && L0_valid_a0) ? '0 : '1;
assign web0 = !wbs_we_i;
assign wmask0 = wbs_sel_i & {4{wbs_we_i}};
assign din0 = wbs_dat_i;
assign addr0 = wbs_adr_i[10:2];
assign wbs_ack_o = L0_ready_a0;
assign imem_rd_cs1 = '0; endgenerate
//_\SV
endmodule