tree: 8b6e0a36bedb838dc2b0fea129cd26fd2439b510 [path history] [tgz]
  1. .github/
  2. def/
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  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
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  14. verilog/
  15. .gitignore
  16. LICENSE
  17. Makefile
  18. README.md
README.md

WARP-V

WARP-V is an open-source CPU core generator written in TL-Verilog with support for RISC-V and MIPS I. It is a demonstration and exploration vehicle for the flexibility that is possible using the emerging “transaction-level design” methodology. It can implement a single-stage, low-power microcontroller or a mid-range 7-stage CPU. Even the instruction-set architectures (ISAs) is configurable. WARP-V is an evolving library of CPU components as well as various compositions of them. It is driven by a community interested in transforming the silicon industry through open-source hardware and revolutionary design methodology.