| commit | 2b2c6e7de1429a142cd6784b5ea4110436f4436f | [log] [tgz] |
|---|---|---|
| author | Ali Imran <ali1120001@outlook.com> | Mon Sep 12 10:11:21 2022 +0500 |
| committer | Ali Imran <ali1120001@outlook.com> | Mon Sep 12 10:11:21 2022 +0500 |
| tree | 8b6e0a36bedb838dc2b0fea129cd26fd2439b510 | |
| parent | ad4570703d6ef48b271529912340c262e9622fc4 [diff] |
Design Updated
WARP-V is an open-source CPU core generator written in TL-Verilog with support for RISC-V and MIPS I. It is a demonstration and exploration vehicle for the flexibility that is possible using the emerging “transaction-level design” methodology. It can implement a single-stage, low-power microcontroller or a mid-range 7-stage CPU. Even the instruction-set architectures (ISAs) is configurable. WARP-V is an evolving library of CPU components as well as various compositions of them. It is driven by a community interested in transforming the silicon industry through open-source hardware and revolutionary design methodology.