docker update
diff --git a/deps/timing-scripts/README.md b/deps/timing-scripts/README.md
new file mode 100644
index 0000000..6e72e68
--- /dev/null
+++ b/deps/timing-scripts/README.md
@@ -0,0 +1,83 @@
+# Timing scripts
+
+A set of scripts for rcx and sta for caravel top level
+
+## Dependencies
+- Docker
+
+## Prerequisites
+
+A set of exports are needed:
+```bash
+export CARAVEL_ROOT=${HOME}/caravel/
+export MCW_ROOT=${HOME}/caravel_mgmt_soc_litex/
+export CUP_ROOT=${HOME}/caravel_user_project/
+export TIMING_ROOT=${HOME}/timing-scripts/
+export PDK_ROOT=${HOME}/pdk/
+export PDK=sky130A
+export OPENLANE_IMAGE_NAME=efabless/openlane:4476a58407d670d251aa0be6a55e5391bb181c4e-amd64
+```
+
+python modules:
+- `pyverilog`
+- `click`
+
+## Usage
+
+### caravel_user_project
+
+1. After exporting the prerequisites, run:
+
+ ```
+ make -f timing.mk list-rcx
+ ```
+ You should get `rcx-user_project_wrapper` amongst others such as:
+
+ ```
+ rcx-buff_flash_clkrst
+ rcx-caravel
+ rcx-caravel_clocking
+ rcx-constant_block
+ rcx-digital_pll
+ rcx-gpio_control_block
+ rcx-gpio_defaults_block
+ rcx-gpio_logic_high
+ rcx-gpio_signal_buffering
+ rcx-gpio_signal_buffering_alt
+ rcx-housekeeping
+ rcx-mgmt_protect
+ rcx-mprj2_logic_high
+ rcx-mprj_logic_high
+ rcx-spare_logic_block
+ rcx-RAM256
+ rcx-mgmt_core_wrapper
+ rcx-user_proj_example
+ rcx-user_project_wrapper
+ ```
+
+2. extract multicorner spefs for `user_project_wrapper` and any other blocks inside:
+
+ ```
+ make -f timing.mk rcx-user_project_wrapper
+ make -f timing.mk rcx-user_proj_example
+ ```
+3. generate spef mapping file for caravel_user_project:
+
+ ```
+ python3 ./scripts/generate_spef_mapping -i ${CUP_ROOT}/verilog/gl/user_project_wrapper.v -o ${CUP_ROOT}/env/spef-mapping.tcl --project-root '$::env(CUP_ROOT)' --pdk-root ${PDK_ROOT} --pdk ${PDK}
+ ```
+
+4. run sta:
+
+ ```
+ make -f timing.mk caravel-timing-typ
+ make -f timing.mk caravel-timing-slow
+ make -f timing.mk caravel-timing-fast
+ ```
+
+## Limitations
+
+- Makefile
+- Makefile
+- Assumes a fixed folder structure for the exported directories
+- Probably a lot of corner cases that weren't considered
diff --git a/deps/timing-scripts/env/caravel_spef_mapping-mpw2-calibre.tcl b/deps/timing-scripts/env/caravel_spef_mapping-mpw2-calibre.tcl
new file mode 100644
index 0000000..87eeb62
--- /dev/null
+++ b/deps/timing-scripts/env/caravel_spef_mapping-mpw2-calibre.tcl
@@ -0,0 +1,101 @@
+set spef_mapping(rstb_level) $::env(CARAVEL_ROOT)/spef/xres_buf.spef
+set spef_mapping(mgmt_buffers/powergood_check) $::env(CARAVEL_ROOT)/spef/mgmt_protect_hv.spef
+set spef_mapping(padframe) $::env(CARAVEL_ROOT)/spef/chip_io.spef
+set spef_mapping(mgmt_buffers/mprj2_logic_high_inst) $::env(CARAVEL_ROOT)/spef/mprj2_logic_high.spef
+set spef_mapping(mgmt_buffers/mprj_logic_high_inst) $::env(CARAVEL_ROOT)/spef/mprj_logic_high.spef
+
+#set spef_mapping(por) $::env(CARAVEL_ROOT)/spef/simple_por.spef
+
+# error in rcx extraction for the section/paragraph below
+# [ERROR ODB-0299] Via via3_320_320 has only 2 shapes and must have at least three.
+
+set spef_mapping(gpio_defaults_block_0) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_1803.spef
+set spef_mapping(gpio_defaults_block_1) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_1803.spef
+set spef_mapping(gpio_defaults_block_2) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_0403.spef
+set spef_mapping(gpio_defaults_block_3) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_0403.spef
+set spef_mapping(gpio_defaults_block_4) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_0403.spef
+
+set spef_mapping(gpio_defaults_block_10) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_11) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_12) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_13) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_14) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_15) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_16) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_17) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_18) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_19) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_20) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_21) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_22) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_23) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_24) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_25) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_26) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_27) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_28) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_29) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_30) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_31) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_32) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_33) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_34) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_35) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_36) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_37) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_5) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_6) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_7) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_8) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_9) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_control_bidir_1[0]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_bidir_1[1]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_bidir_2[0]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_bidir_2[1]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_bidir_2[2]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_1[0]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_1[10]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_1[1]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_1[2]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_1[3]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_1[4]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_1[5]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_1[6]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_1[7]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_1[8]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_1[9]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_1a[0]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_1a[1]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_1a[2]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_1a[3]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_1a[4]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_1a[5]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_2[0]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_2[10]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_2[11]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_2[12]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_2[13]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_2[14]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_2[15]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_2[1]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_2[2]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_2[3]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_2[4]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_2[5]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_2[6]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_2[7]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_2[8]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_2[9]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(housekeeping) $::env(CARAVEL_ROOT)/spef/housekeeping.spef
+set spef_mapping(mgmt_buffers) $::env(CARAVEL_ROOT)/spef/mgmt_protect.spef
+set spef_mapping(pll) $::env(CARAVEL_ROOT)/spef/digital_pll.spef
+set spef_mapping(spare_logic[0]) $::env(CARAVEL_ROOT)/spef/spare_logic_block.spef
+set spef_mapping(spare_logic[1]) $::env(CARAVEL_ROOT)/spef/spare_logic_block.spef
+set spef_mapping(spare_logic[2]) $::env(CARAVEL_ROOT)/spef/spare_logic_block.spef
+set spef_mapping(spare_logic[3]) $::env(CARAVEL_ROOT)/spef/spare_logic_block.spef
+
+set spef_mapping(clocking) $::env(CARAVEL_ROOT)/spef/caravel_clocking.spef
+
+set spef_mapping(soc) $::env(MCW_ROOT)/spef/mgmt_core_wrapper.spef
+set spef_mapping(soc/DFFRAM_0) $::env(MCW_ROOT)/spef/DFFRAM.spef
+set spef_mapping(soc/core) $::env(MCW_ROOT)/spef/mgmt_core.spef
diff --git a/deps/timing-scripts/env/caravel_spef_mapping-mpw2.tcl b/deps/timing-scripts/env/caravel_spef_mapping-mpw2.tcl
new file mode 100644
index 0000000..fade71c
--- /dev/null
+++ b/deps/timing-scripts/env/caravel_spef_mapping-mpw2.tcl
@@ -0,0 +1,99 @@
+set spef_mapping(rstb_level) $::env(CARAVEL_ROOT)/spef/xres_buf.spef
+set spef_mapping(mgmt_buffers/powergood_check) $::env(CARAVEL_ROOT)/spef/mgmt_protect_hv.spef
+set spef_mapping(padframe) $::env(CARAVEL_ROOT)/spef/chip_io.spef
+set spef_mapping(mgmt_buffers/mprj2_logic_high_inst) $::env(CARAVEL_ROOT)/spef/mprj2_logic_high.spef
+set spef_mapping(mgmt_buffers/mprj_logic_high_inst) $::env(CARAVEL_ROOT)/spef/mprj_logic_high.spef
+
+#set spef_mapping(por) $::env(CARAVEL_ROOT)/spef/simple_por.spef
+
+# error in rcx extraction for the section/paragraph below
+# [ERROR ODB-0299] Via via3_320_320 has only 2 shapes and must have at least three.
+
+set spef_mapping(gpio_defaults_block_0) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_1803.spef
+set spef_mapping(gpio_defaults_block_1) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_1803.spef
+set spef_mapping(gpio_defaults_block_2) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_0403.spef
+set spef_mapping(gpio_defaults_block_3) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_0403.spef
+set spef_mapping(gpio_defaults_block_4) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_0403.spef
+
+set spef_mapping(gpio_defaults_block_10) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_11) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_12) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_13) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_14) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_15) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_16) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_17) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_18) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_19) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_20) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_21) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_22) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_23) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_24) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_25) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_26) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_27) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_28) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_29) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_30) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_31) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_32) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_33) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_34) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_35) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_36) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_37) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_5) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_6) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_7) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_8) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_9) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_bidir_1[0]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_bidir_1[1]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_bidir_2[0]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_bidir_2[1]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_bidir_2[2]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_1[0]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_1[10]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_1[1]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_1[2]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_1[3]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_1[4]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_1[5]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_1[6]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_1[7]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_1[8]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_1[9]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_1a[0]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_1a[1]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_1a[2]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_1a[3]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_1a[4]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_1a[5]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_2[0]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_2[10]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_2[11]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_2[12]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_2[13]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_2[14]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_2[15]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_2[1]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_2[2]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_2[3]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_2[4]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_2[5]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_2[6]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_2[7]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_2[8]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_2[9]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(housekeeping) $::env(CARAVEL_ROOT)/spef/housekeeping_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(mgmt_buffers) $::env(CARAVEL_ROOT)/spef/mgmt_protect_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(pll) $::env(CARAVEL_ROOT)/spef/digital_pll_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(spare_logic[0]) $::env(CARAVEL_ROOT)/spef/spare_logic_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(spare_logic[1]) $::env(CARAVEL_ROOT)/spef/spare_logic_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(spare_logic[2]) $::env(CARAVEL_ROOT)/spef/spare_logic_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(spare_logic[3]) $::env(CARAVEL_ROOT)/spef/spare_logic_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+
+set spef_mapping(soc) $::env(MCW_ROOT)/spef/mgmt_core_wrapper_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(soc/DFFRAM_0) $::env(MCW_ROOT)/spef/DFFRAM_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(soc/core) $::env(MCW_ROOT)/spef/mgmt_core_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
diff --git a/deps/timing-scripts/env/caravel_spef_mapping-mpw5-calibre.tcl b/deps/timing-scripts/env/caravel_spef_mapping-mpw5-calibre.tcl
new file mode 100644
index 0000000..c6c8a54
--- /dev/null
+++ b/deps/timing-scripts/env/caravel_spef_mapping-mpw5-calibre.tcl
@@ -0,0 +1,90 @@
+set spef_mapping(rstb_level) $::env(CARAVEL_ROOT)/spef/xres_buf.spef
+set spef_mapping(mgmt_buffers/powergood_check) $::env(CARAVEL_ROOT)/spef/mgmt_protect_hv.spef
+set spef_mapping(padframe) $::env(CARAVEL_ROOT)/spef/chip_io.spef
+
+# should double check this
+set spef_mapping(gpio_defaults_block_0[0]) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_1803.spef
+set spef_mapping(gpio_defaults_block_0[1]) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_1803.spef
+set spef_mapping(gpio_defaults_block_2[0]) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_0403.spef
+set spef_mapping(gpio_defaults_block_2[1]) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_0403.spef
+set spef_mapping(gpio_defaults_block_2[2]) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_0403.spef
+
+set spef_mapping(soc/DFFRAM_0) $::env(MCW_ROOT)/spef/DFFRAM.spef
+set spef_mapping(soc/core) $::env(MCW_ROOT)/spef/mgmt_core.spef
+set spef_mapping(soc) $::env(MCW_ROOT)/spef/mgmt_core_wrapper.spef
+set spef_mapping(pll) $::env(CARAVEL_ROOT)/spef/digital_pll.spef
+set spef_mapping(housekeeping) $::env(CARAVEL_ROOT)/spef/housekeeping.spef
+set spef_mapping(mgmt_buffers/mprj_logic_high_inst) $::env(CARAVEL_ROOT)/spef/mprj_logic_high.spef
+set spef_mapping(mgmt_buffers/mprj2_logic_high_inst) $::env(CARAVEL_ROOT)/spef/mprj2_logic_high.spef
+set spef_mapping(mgmt_buffers) $::env(CARAVEL_ROOT)/spef/mgmt_protect.spef
+set spef_mapping(gpio_control_bidir_1[0]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_bidir_1[1]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_bidir_2[1]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_bidir_2[2]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_1[0]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_1[10]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_1[1]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_1[2]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_1[3]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_1[4]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_1[5]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_1[6]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_1[7]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_1[8]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_1[9]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_1a[0]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_1a[1]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_1a[2]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_1a[3]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_1a[4]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_1a[5]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_2[0]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_2[10]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_2[11]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_2[12]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_2[13]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_2[14]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_2[15]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_2[1]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_2[2]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_2[3]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_2[4]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_2[5]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_2[6]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_2[7]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_2[8]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_control_in_2[9]) $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+set spef_mapping(gpio_defaults_block_5) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_6) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_7) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_8) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_9) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_10) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_11) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_12) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_13) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_14) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_15) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_16) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_17) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_18) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_19) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_20) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_21) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_22) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_23) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_24) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_25) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_26) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_27) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_28) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_29) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_30) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_31) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_32) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_33) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_34) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_35) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_36) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+set spef_mapping(gpio_defaults_block_37) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+
diff --git a/deps/timing-scripts/env/caravel_spef_mapping-mpw7.tcl b/deps/timing-scripts/env/caravel_spef_mapping-mpw7.tcl
new file mode 100644
index 0000000..e12e189
--- /dev/null
+++ b/deps/timing-scripts/env/caravel_spef_mapping-mpw7.tcl
@@ -0,0 +1,136 @@
+set SPEF_MAPPING_POSTFIX ".$::env(RCX_CORNER).spef"
+set SPEF_MAPPING_PREFIX "$::env(CARAVEL_ROOT)/signoff/gpio_control_block/openlane-signoff/spef/"
+set spef_mapping(\gpio_control_bidir_1[0]) ${SPEF_MAPPING_PREFIX}gpio_control_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(\gpio_control_bidir_1[1]) ${SPEF_MAPPING_PREFIX}gpio_control_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(\gpio_control_bidir_2[0]) ${SPEF_MAPPING_PREFIX}gpio_control_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(\gpio_control_bidir_2[1]) ${SPEF_MAPPING_PREFIX}gpio_control_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(\gpio_control_bidir_2[2]) ${SPEF_MAPPING_PREFIX}gpio_control_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(\gpio_control_in_1[0]) ${SPEF_MAPPING_PREFIX}gpio_control_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(\gpio_control_in_1[10]) ${SPEF_MAPPING_PREFIX}gpio_control_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(\gpio_control_in_1[1]) ${SPEF_MAPPING_PREFIX}gpio_control_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(\gpio_control_in_1[2]) ${SPEF_MAPPING_PREFIX}gpio_control_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(\gpio_control_in_1[3]) ${SPEF_MAPPING_PREFIX}gpio_control_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(\gpio_control_in_1[4]) ${SPEF_MAPPING_PREFIX}gpio_control_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(\gpio_control_in_1[5]) ${SPEF_MAPPING_PREFIX}gpio_control_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(\gpio_control_in_1[6]) ${SPEF_MAPPING_PREFIX}gpio_control_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(\gpio_control_in_1[7]) ${SPEF_MAPPING_PREFIX}gpio_control_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(\gpio_control_in_1[8]) ${SPEF_MAPPING_PREFIX}gpio_control_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(\gpio_control_in_1[9]) ${SPEF_MAPPING_PREFIX}gpio_control_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(\gpio_control_in_1a[0]) ${SPEF_MAPPING_PREFIX}gpio_control_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(\gpio_control_in_1a[1]) ${SPEF_MAPPING_PREFIX}gpio_control_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(\gpio_control_in_1a[2]) ${SPEF_MAPPING_PREFIX}gpio_control_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(\gpio_control_in_1a[3]) ${SPEF_MAPPING_PREFIX}gpio_control_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(\gpio_control_in_1a[4]) ${SPEF_MAPPING_PREFIX}gpio_control_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(\gpio_control_in_1a[5]) ${SPEF_MAPPING_PREFIX}gpio_control_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(\gpio_control_in_2[0]) ${SPEF_MAPPING_PREFIX}gpio_control_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(\gpio_control_in_2[10]) ${SPEF_MAPPING_PREFIX}gpio_control_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(\gpio_control_in_2[11]) ${SPEF_MAPPING_PREFIX}gpio_control_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(\gpio_control_in_2[12]) ${SPEF_MAPPING_PREFIX}gpio_control_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(\gpio_control_in_2[13]) ${SPEF_MAPPING_PREFIX}gpio_control_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(\gpio_control_in_2[14]) ${SPEF_MAPPING_PREFIX}gpio_control_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(\gpio_control_in_2[15]) ${SPEF_MAPPING_PREFIX}gpio_control_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(\gpio_control_in_2[1]) ${SPEF_MAPPING_PREFIX}gpio_control_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(\gpio_control_in_2[2]) ${SPEF_MAPPING_PREFIX}gpio_control_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(\gpio_control_in_2[3]) ${SPEF_MAPPING_PREFIX}gpio_control_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(\gpio_control_in_2[4]) ${SPEF_MAPPING_PREFIX}gpio_control_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(\gpio_control_in_2[5]) ${SPEF_MAPPING_PREFIX}gpio_control_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(\gpio_control_in_2[6]) ${SPEF_MAPPING_PREFIX}gpio_control_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(\gpio_control_in_2[7]) ${SPEF_MAPPING_PREFIX}gpio_control_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(\gpio_control_in_2[8]) ${SPEF_MAPPING_PREFIX}gpio_control_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(\gpio_control_in_2[9]) ${SPEF_MAPPING_PREFIX}gpio_control_block${SPEF_MAPPING_POSTFIX}
+
+set SPEF_MAPPING_PREFIX "$::env(CARAVEL_ROOT)/signoff/spare_logic_block/openlane-signoff/spef/"
+set spef_mapping(\spare_logic[0]) ${SPEF_MAPPING_PREFIX}spare_logic_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(\spare_logic[1]) ${SPEF_MAPPING_PREFIX}spare_logic_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(\spare_logic[2]) ${SPEF_MAPPING_PREFIX}spare_logic_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(\spare_logic[3]) ${SPEF_MAPPING_PREFIX}spare_logic_block${SPEF_MAPPING_POSTFIX}
+
+set SPEF_MAPPING_PREFIX "$::env(CARAVEL_ROOT)/signoff/caravel_clocking/openlane-signoff/spef/"
+set spef_mapping(clock_ctrl) ${SPEF_MAPPING_PREFIX}caravel_clocking${SPEF_MAPPING_POSTFIX}
+
+set SPEF_MAPPING_PREFIX "$::env(CARAVEL_ROOT)/signoff/buff_flash_clkrst/openlane-signoff/spef/"
+set spef_mapping(flash_clkrst_buffers) ${SPEF_MAPPING_PREFIX}buff_flash_clkrst${SPEF_MAPPING_POSTFIX}
+
+set SPEF_MAPPING_PREFIX "$::env(CARAVEL_ROOT)/signoff/gpio_defaults_block/openlane-signoff/spef/"
+set spef_mapping(gpio_defaults_block_0) ${SPEF_MAPPING_PREFIX}gpio_defaults_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(gpio_defaults_block_1) ${SPEF_MAPPING_PREFIX}gpio_defaults_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(gpio_defaults_block_2) ${SPEF_MAPPING_PREFIX}gpio_defaults_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(gpio_defaults_block_3) ${SPEF_MAPPING_PREFIX}gpio_defaults_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(gpio_defaults_block_4) ${SPEF_MAPPING_PREFIX}gpio_defaults_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(gpio_defaults_block_5) ${SPEF_MAPPING_PREFIX}gpio_defaults_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(gpio_defaults_block_6) ${SPEF_MAPPING_PREFIX}gpio_defaults_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(gpio_defaults_block_7) ${SPEF_MAPPING_PREFIX}gpio_defaults_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(gpio_defaults_block_8) ${SPEF_MAPPING_PREFIX}gpio_defaults_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(gpio_defaults_block_9) ${SPEF_MAPPING_PREFIX}gpio_defaults_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(gpio_defaults_block_10) ${SPEF_MAPPING_PREFIX}gpio_defaults_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(gpio_defaults_block_11) ${SPEF_MAPPING_PREFIX}gpio_defaults_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(gpio_defaults_block_12) ${SPEF_MAPPING_PREFIX}gpio_defaults_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(gpio_defaults_block_13) ${SPEF_MAPPING_PREFIX}gpio_defaults_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(gpio_defaults_block_14) ${SPEF_MAPPING_PREFIX}gpio_defaults_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(gpio_defaults_block_15) ${SPEF_MAPPING_PREFIX}gpio_defaults_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(gpio_defaults_block_16) ${SPEF_MAPPING_PREFIX}gpio_defaults_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(gpio_defaults_block_17) ${SPEF_MAPPING_PREFIX}gpio_defaults_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(gpio_defaults_block_18) ${SPEF_MAPPING_PREFIX}gpio_defaults_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(gpio_defaults_block_19) ${SPEF_MAPPING_PREFIX}gpio_defaults_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(gpio_defaults_block_20) ${SPEF_MAPPING_PREFIX}gpio_defaults_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(gpio_defaults_block_21) ${SPEF_MAPPING_PREFIX}gpio_defaults_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(gpio_defaults_block_22) ${SPEF_MAPPING_PREFIX}gpio_defaults_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(gpio_defaults_block_23) ${SPEF_MAPPING_PREFIX}gpio_defaults_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(gpio_defaults_block_24) ${SPEF_MAPPING_PREFIX}gpio_defaults_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(gpio_defaults_block_25) ${SPEF_MAPPING_PREFIX}gpio_defaults_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(gpio_defaults_block_26) ${SPEF_MAPPING_PREFIX}gpio_defaults_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(gpio_defaults_block_27) ${SPEF_MAPPING_PREFIX}gpio_defaults_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(gpio_defaults_block_28) ${SPEF_MAPPING_PREFIX}gpio_defaults_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(gpio_defaults_block_29) ${SPEF_MAPPING_PREFIX}gpio_defaults_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(gpio_defaults_block_30) ${SPEF_MAPPING_PREFIX}gpio_defaults_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(gpio_defaults_block_31) ${SPEF_MAPPING_PREFIX}gpio_defaults_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(gpio_defaults_block_32) ${SPEF_MAPPING_PREFIX}gpio_defaults_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(gpio_defaults_block_33) ${SPEF_MAPPING_PREFIX}gpio_defaults_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(gpio_defaults_block_34) ${SPEF_MAPPING_PREFIX}gpio_defaults_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(gpio_defaults_block_35) ${SPEF_MAPPING_PREFIX}gpio_defaults_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(gpio_defaults_block_36) ${SPEF_MAPPING_PREFIX}gpio_defaults_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(gpio_defaults_block_37) ${SPEF_MAPPING_PREFIX}gpio_defaults_block${SPEF_MAPPING_POSTFIX}
+
+set SPEF_MAPPING_PREFIX "$::env(CARAVEL_ROOT)/signoff/housekeeping/openlane-signoff/spef/"
+set spef_mapping(housekeeping) ${SPEF_MAPPING_PREFIX}housekeeping${SPEF_MAPPING_POSTFIX}
+
+set SPEF_MAPPING_PREFIX "$::env(CARAVEL_ROOT)/signoff/mgmt_protect/openlane-signoff/spef/"
+set spef_mapping(mgmt_buffers) ${SPEF_MAPPING_PREFIX}mgmt_protect${SPEF_MAPPING_POSTFIX}
+
+set SPEF_MAPPING_PREFIX "$::env(CUP_ROOT)/signoff/user_project_wrapper/openlane-signoff/spef/"
+set spef_mapping(mprj) ${SPEF_MAPPING_PREFIX}user_project_wrapper${SPEF_MAPPING_POSTFIX}
+
+set SPEF_MAPPING_PREFIX "$::env(CARAVEL_ROOT)/signoff/chip_io/openlane-signoff/spef/"
+set spef_mapping(padframe) ${SPEF_MAPPING_PREFIX}chip_io${SPEF_MAPPING_POSTFIX}
+
+set SPEF_MAPPING_PREFIX "$::env(CARAVEL_ROOT)/signoff/digital_pll/openlane-signoff/spef/"
+set spef_mapping(pll) ${SPEF_MAPPING_PREFIX}digital_pll${SPEF_MAPPING_POSTFIX}
+
+set SPEF_MAPPING_PREFIX "$::env(CARAVEL_ROOT)/signoff/simple_por/openlane-signoff/spef/"
+set spef_mapping(por) ${SPEF_MAPPING_PREFIX}simple_por${SPEF_MAPPING_POSTFIX}
+
+set SPEF_MAPPING_PREFIX "$::env(CARAVEL_ROOT)/signoff/xres_buf/openlane-signoff/spef/"
+set spef_mapping(rstb_level) ${SPEF_MAPPING_PREFIX}xres_buf${SPEF_MAPPING_POSTFIX}
+
+set SPEF_MAPPING_PREFIX "$::env(CARAVEL_ROOT)/signoff/gpio_signal_buffering/openlane-signoff/spef/"
+set spef_mapping(sigbuf) ${SPEF_MAPPING_PREFIX}gpio_signal_buffering${SPEF_MAPPING_POSTFIX}
+
+set SPEF_MAPPING_PREFIX "$::env(CARAVEL_ROOT)/signoff/user_id_programming/openlane-signoff/spef/"
+set spef_mapping(user_id_value) ${SPEF_MAPPING_PREFIX}user_id_programming${SPEF_MAPPING_POSTFIX}
+
+set SPEF_MAPPING_PREFIX "$::env(MCW_ROOT)/signoff/mgmt_core_wrapper/openlane-signoff/spef/"
+set spef_mapping(soc) ${SPEF_MAPPING_PREFIX}mgmt_core_wrapper${SPEF_MAPPING_POSTFIX}
+
+set SPEF_MAPPING_PREFIX "$::env(CARAVEL_ROOT)/signoff/constant_block/openlane-signoff/spef/"
+set spef_mapping(padframe/\constant_value_inst[0]) ${SPEF_MAPPING_PREFIX}constant_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(padframe/\constant_value_inst[1]) ${SPEF_MAPPING_PREFIX}constant_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(padframe/\constant_value_inst[2]) ${SPEF_MAPPING_PREFIX}constant_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(padframe/\constant_value_inst[3]) ${SPEF_MAPPING_PREFIX}constant_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(padframe/\constant_value_inst[4]) ${SPEF_MAPPING_PREFIX}constant_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(padframe/\constant_value_inst[5]) ${SPEF_MAPPING_PREFIX}constant_block${SPEF_MAPPING_POSTFIX}
+set spef_mapping(padframe/\constant_value_inst[6]) ${SPEF_MAPPING_PREFIX}constant_block${SPEF_MAPPING_POSTFIX}
+
+set SPEF_MAPPING_PREFIX "$::env(MCW_ROOT)/signoff/RAM256/openlane-signoff/spef/"
+set spef_mapping(soc/\core.RAM256) ${SPEF_MAPPING_PREFIX}RAM256${SPEF_MAPPING_POSTFIX}
+set SPEF_MAPPING_PREFIX "$::env(MCW_ROOT)/signoff/RAM128/openlane-signoff/spef/"
+set spef_mapping(soc/\core.RAM128) ${SPEF_MAPPING_PREFIX}RAM128${SPEF_MAPPING_POSTFIX}
diff --git a/deps/timing-scripts/env/caravel_spef_mapping.tcl b/deps/timing-scripts/env/caravel_spef_mapping.tcl
new file mode 100644
index 0000000..f287952
--- /dev/null
+++ b/deps/timing-scripts/env/caravel_spef_mapping.tcl
@@ -0,0 +1,90 @@
+set spef_mapping(rstb_level) $::env(CARAVEL_ROOT)/spef/xres_buf.spef
+set spef_mapping(mgmt_buffers/powergood_check) $::env(CARAVEL_ROOT)/spef/mgmt_protect_hv.spef
+set spef_mapping(padframe) $::env(CARAVEL_ROOT)/spef/chip_io.spef
+
+# should double check this
+set spef_mapping(gpio_defaults_block_0[0]) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_1803.spef
+set spef_mapping(gpio_defaults_block_0[1]) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_1803.spef
+set spef_mapping(gpio_defaults_block_2[0]) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_0403.spef
+set spef_mapping(gpio_defaults_block_2[1]) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_0403.spef
+set spef_mapping(gpio_defaults_block_2[2]) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_0403.spef
+
+set spef_mapping(soc/DFFRAM_0) $::env(MCW_ROOT)/spef/DFFRAM_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(soc/core) $::env(MCW_ROOT)/spef/mgmt_core_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(soc) $::env(MCW_ROOT)/spef/mgmt_core_wrapper_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(pll) $::env(CARAVEL_ROOT)/spef/digital_pll_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(housekeeping) $::env(CARAVEL_ROOT)/spef/housekeeping_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(mgmt_buffers/mprj_logic_high_inst) $::env(CARAVEL_ROOT)/spef/mprj_logic_high_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(mgmt_buffers/mprj2_logic_high_inst) $::env(CARAVEL_ROOT)/spef/mprj2_logic_high_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(mgmt_buffers) $::env(CARAVEL_ROOT)/spef/mgmt_protect_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_bidir_1[0]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_bidir_1[1]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_bidir_2[1]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_bidir_2[2]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_1[0]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_1[10]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_1[1]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_1[2]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_1[3]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_1[4]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_1[5]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_1[6]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_1[7]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_1[8]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_1[9]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_1a[0]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_1a[1]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_1a[2]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_1a[3]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_1a[4]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_1a[5]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_2[0]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_2[10]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_2[11]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_2[12]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_2[13]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_2[14]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_2[15]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_2[1]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_2[2]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_2[3]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_2[4]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_2[5]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_2[6]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_2[7]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_2[8]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_control_in_2[9]) $::env(CARAVEL_ROOT)/spef/gpio_control_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_5) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_6) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_7) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_8) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_9) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_10) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_11) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_12) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_13) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_14) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_15) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_16) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_17) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_18) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_19) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_20) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_21) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_22) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_23) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_24) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_25) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_26) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_27) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_28) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_29) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_30) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_31) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_32) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_33) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_34) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_35) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_36) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+set spef_mapping(gpio_defaults_block_37) $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_$::env(RCX_CORNER)_$::env(LIB_CORNER).spef
+
diff --git a/deps/timing-scripts/env/common.tcl b/deps/timing-scripts/env/common.tcl
new file mode 100644
index 0000000..b06a6f7
--- /dev/null
+++ b/deps/timing-scripts/env/common.tcl
@@ -0,0 +1,134 @@
+set std_cell_library "sky130_fd_sc_hd"
+set special_voltage_library "sky130_fd_sc_hvl"
+set io_library "sky130_fd_io"
+set primitives_library "sky130_fd_pr"
+set ef_io_library "sky130_ef_io"
+set ef_cell_library "sky130_ef_sc_hd"
+
+set signal_layer "met2"
+set clock_layer "met5"
+
+set extra_lefs "
+[glob $::env(CARAVEL_ROOT)/lef/*.lef]
+[glob $::env(MCW_ROOT)/lef/*.lef]
+[glob $::env(CUP_ROOT)/lef/*.lef]"
+
+set tech_lef $::env(PDK_REF_PATH)/$std_cell_library/techlef/${std_cell_library}__$::env(RCX_CORNER).tlef
+set cells_lef $::env(PDK_REF_PATH)/$std_cell_library/lef/$std_cell_library.lef
+set io_lef $::env(PDK_REF_PATH)/$io_library/lef/$io_library.lef
+set ef_io_lef $::env(PDK_REF_PATH)/$io_library/lef/$ef_io_library.lef
+set ef_cells_lef $::env(PDK_REF_PATH)/$std_cell_library/lef/$ef_cell_library.lef
+
+set lefs [list \
+ $tech_lef \
+ $cells_lef \
+ $io_lef \
+ $ef_cells_lef \
+ $ef_io_lef
+]
+# search order:
+# cup -> mcw -> caravel
+
+# file mkdir $::env(CUP_ROOT)/spef/
+# file mkdir $::env(CARAVEL_ROOT)/spef/
+# file mkdir $::env(MCW_ROOT)/spef/
+
+set def $::env(CUP_ROOT)/def/$::env(BLOCK).def
+set spef $::env(CUP_ROOT)/signoff/$::env(BLOCK)/openlane-signoff/spef/$::env(BLOCK).$::env(RCX_CORNER).spef
+set sdc $::env(CUP_ROOT)/sdc/$::env(BLOCK).sdc
+set sdf $::env(CUP_ROOT)/signoff/$::env(BLOCK)/openlane-signoff/sdf/$::env(RCX_CORNER)/$::env(BLOCK).$::env(LIB_CORNER)$::env(LIB_CORNER).$::env(RCX_CORNER).sdf
+if { ![file exists $def] } {
+ set def $::env(MCW_ROOT)/def/$::env(BLOCK).def
+ set spef $::env(MCW_ROOT)/signoff/$::env(BLOCK)/openlane-signoff/spef/$::env(BLOCK).$::env(RCX_CORNER).spef
+ set sdc $::env(MCW_ROOT)/sdc/$::env(BLOCK).sdc
+ set sdf $::env(MCW_ROOT)/signoff/$::env(BLOCK)/openlane-signoff/sdf/$::env(RCX_CORNER)/$::env(BLOCK).$::env(LIB_CORNER)$::env(LIB_CORNER).$::env(RCX_CORNER).sdf
+}
+if { ![file exists $def] } {
+ set def $::env(CARAVEL_ROOT)/def/$::env(BLOCK).def
+ set spef $::env(CARAVEL_ROOT)/signoff/$::env(BLOCK)/openlane-signoff/spef/$::env(BLOCK).$::env(RCX_CORNER).spef
+ set sdc $::env(CARAVEL_ROOT)/sdc/$::env(BLOCK).sdc
+ set sdf $::env(CARAVEL_ROOT)/signoff/$::env(BLOCK)/openlane-signoff/sdf/$::env(RCX_CORNER)/$::env(BLOCK).$::env(LIB_CORNER)$::env(LIB_CORNER).$::env(RCX_CORNER).sdf
+}
+
+file mkdir [file dirname $spef]
+file mkdir [file dirname $sdf]
+set block $::env(BLOCK)
+if { $::env(PDK) == "sky130A" } {
+ set rcx_rules_file $::env(PDK_TECH_PATH)/openlane/rules.openrcx.$::env(PDK).$::env(RCX_CORNER).calibre
+} elseif { $::env(PDK) == "sky130B" } {
+ set rcx_rules_file $::env(PDK_TECH_PATH)/openlane/rules.openrcx.$::env(PDK).$::env(RCX_CORNER).spef_extractor
+} else {
+ puts "no extraction rules file set for $::env(PDK) exiting.."
+ exit 1
+}
+set merged_lef $::env(CARAVEL_ROOT)/tmp/merged_lef-$::env(RCX_CORNER).lef
+
+set sram_lef $::env(PDK_REF_PATH)/sky130_sram_macros/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef
+
+# order matter
+set caravel_root "[file normalize $::env(CARAVEL_ROOT)]"
+set mcw_root "[file normalize $::env(MCW_ROOT)]"
+set cup_root "[file normalize $::env(CUP_ROOT)]"
+set verilogs "
+[glob $mcw_root/verilog/gl/*]
+[glob $caravel_root/verilog/gl/*]
+[glob $cup_root/verilog/gl/*]
+"
+
+set verilog_exceptions [list \
+ "$caravel_root/verilog/gl/__user_analog_project_wrapper.v" \
+ "$caravel_root/verilog/gl/caravel-signoff.v" \
+ "$caravel_root/verilog/gl/caravan-signoff.v" \
+ "$caravel_root/verilog/gl/__user_project_wrapper.v" \
+ ]
+
+foreach verilog_exception $verilog_exceptions {
+ puts "verilog exception: $verilog_exception"
+ set verilogs [regsub "$verilog_exception" "$verilogs" " "]
+}
+
+proc puts_list {arg} {
+ foreach element $arg {
+ puts $element
+ }
+}
+
+proc read_libs {arg} {
+ set libs [split [regexp -all -inline {\S+} $arg]]
+ foreach liberty $libs {
+ puts $liberty
+ read_liberty $liberty
+ }
+}
+
+proc read_verilogs {arg} {
+ set verilogs [split [regexp -all -inline {\S+} $arg]]
+ foreach verilog $verilogs {
+ puts $verilog
+ read_verilog $verilog
+ }
+}
+
+proc read_spefs {} {
+ global spef_mapping
+ foreach key [array names spef_mapping] {
+ puts "read_spef -path $key $spef_mapping($key)"
+ read_spef -path $key $spef_mapping($key)
+ }
+}
+
+proc run_puts {arg} {
+ puts "exec> $arg"
+ eval "{*}$arg"
+}
+
+proc run_puts_logs {arg log} {
+ set output [open "$log" w+]
+ puts $output "exec> $arg"
+ puts $output "design: $::env(BLOCK)"
+ set timestr [exec date]
+ puts $output "time: $timestr\n"
+ close $output
+ puts "exec> $arg >> $log"
+ eval "{*}$arg >> $log"
+}
diff --git a/deps/timing-scripts/env/f.tcl b/deps/timing-scripts/env/f.tcl
new file mode 100644
index 0000000..867427b
--- /dev/null
+++ b/deps/timing-scripts/env/f.tcl
@@ -0,0 +1,20 @@
+set libs "
+ $::env(PDK_REF_PATH)/${std_cell_library}/lib/${std_cell_library}__ff_n40C_1v95.lib
+ $::env(PDK_REF_PATH)/${special_voltage_library}/lib/${special_voltage_library}__ff_n40C_5v50.lib
+ $::env(PDK_REF_PATH)/${special_voltage_library}/lib/${special_voltage_library}__ff_n40C_4v40_lv1v95.lib
+ $::env(PDK_REF_PATH)/${io_library}/lib/sky130_fd_io__top_gpiov2_ff_ff_n40C_1v95_5v50.lib
+ $::env(PDK_REF_PATH)/${io_library}/lib/sky130_fd_io__top_ground_hvc_wpad_ff_n40C_1v95_5v50_5v50.lib
+ $::env(PDK_REF_PATH)/${io_library}/lib/sky130_fd_io__top_ground_lvc_wpad_ff_n40C_1v95_5v50.lib
+ $::env(PDK_REF_PATH)/${io_library}/lib/sky130_fd_io__top_power_lvc_wpad_ff_n40C_1v95_5v50_5v50.lib
+ $::env(PDK_REF_PATH)/${io_library}/lib/sky130_fd_io__top_xres4v2_ff_ff_n40C_1v95_5v50.lib
+ $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__gpiov2_pad_wrapped_ff_ff_n40C_1v95_5v50.lib
+ $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vccd_lvc_clamped_pad_ff_n40C_1v95_5v50_5v50.lib
+ $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vdda_hvc_clamped_pad_ff_n40C_1v95_5v50_5v50.lib
+ $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vssa_hvc_clamped_pad_ff_n40C_1v95_5v50_5v50.lib
+ $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vddio_hvc_clamped_pad_ff_n40C_1v95_5v50_5v50.lib
+ $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vssio_hvc_clamped_pad_ff_n40C_1v95_5v50_5v50.lib
+ $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vssd_lvc_clamped3_pad_ff_n40C_1v95_5v50.lib
+ $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vccd_lvc_clamped3_pad_ff_n40C_1v95_5v50_5v50.lib
+ $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vssd_lvc_clamped_pad_ff_n40C_1v95_5v50.lib
+ $::env(PDK_REF_PATH)/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib
+"
diff --git a/deps/timing-scripts/env/s.tcl b/deps/timing-scripts/env/s.tcl
new file mode 100644
index 0000000..9b61eeb
--- /dev/null
+++ b/deps/timing-scripts/env/s.tcl
@@ -0,0 +1,21 @@
+set libs "
+ $::env(PDK_REF_PATH)/${std_cell_library}/lib/${std_cell_library}__ss_100C_1v60.lib
+ $::env(PDK_REF_PATH)/${special_voltage_library}/lib/${special_voltage_library}__ss_100C_1v65.lib
+ $::env(PDK_REF_PATH)/${special_voltage_library}/lib/${special_voltage_library}__ss_100C_1v65_lv1v60.lib
+ $::env(PDK_REF_PATH)/${io_library}/lib/sky130_fd_io__top_gpiov2_ss_ss_100C_1v60_3v00.lib
+ $::env(PDK_REF_PATH)/${io_library}/lib/sky130_fd_io__top_ground_hvc_wpad_ss_100C_1v60_3v00_3v00.lib
+ $::env(PDK_REF_PATH)/${io_library}/lib/sky130_fd_io__top_ground_lvc_wpad_ss_100C_1v60_3v00.lib
+ $::env(PDK_REF_PATH)/${io_library}/lib/sky130_fd_io__top_power_lvc_wpad_ss_100C_1v60_3v00_3v00.lib
+ $::env(PDK_REF_PATH)/${io_library}/lib/sky130_fd_io__top_xres4v2_ss_ss_100C_1v60_3v00.lib
+ $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__gpiov2_pad_wrapped_ss_ss_100C_1v60_3v00.lib
+ $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vccd_lvc_clamped_pad_ss_100C_1v60_3v00_3v00.lib
+ $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vdda_hvc_clamped_pad_ss_100C_1v60_3v00_3v00.lib
+ $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vssa_hvc_clamped_pad_ss_100C_1v60_3v00_3v00.lib
+ $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vddio_hvc_clamped_pad_ss_100C_1v60_3v00_3v00.lib
+ $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vssio_hvc_clamped_pad_ss_100C_1v60_3v00_3v00.lib
+ $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vssd_lvc_clamped3_pad_ss_100C_1v60_3v00.lib
+ $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vccd_lvc_clamped3_pad_ss_100C_1v60_3v00_3v00.lib
+ $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vssd_lvc_clamped_pad_ss_100C_1v60_3v00.lib
+ $::env(PDK_REF_PATH)/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib
+"
+
diff --git a/deps/timing-scripts/env/t.tcl b/deps/timing-scripts/env/t.tcl
new file mode 100644
index 0000000..c9eea15
--- /dev/null
+++ b/deps/timing-scripts/env/t.tcl
@@ -0,0 +1,21 @@
+set libs "
+ $::env(PDK_REF_PATH)/${std_cell_library}/lib/${std_cell_library}__tt_025C_1v80.lib
+ $::env(PDK_REF_PATH)/${special_voltage_library}/lib/${special_voltage_library}__tt_025C_3v30.lib
+ $::env(PDK_REF_PATH)/${special_voltage_library}/lib/${special_voltage_library}__tt_025C_3v30_lv1v80.lib
+ $::env(PDK_REF_PATH)/${io_library}/lib/sky130_fd_io__top_gpiov2_tt_tt_025C_1v80_3v30.lib
+ $::env(PDK_REF_PATH)/${io_library}/lib/sky130_fd_io__top_ground_hvc_wpad_tt_025C_1v80_3v30_3v30.lib
+ $::env(PDK_REF_PATH)/${io_library}/lib/sky130_fd_io__top_ground_lvc_wpad_tt_025C_1v80_3v30.lib
+ $::env(PDK_REF_PATH)/${io_library}/lib/sky130_fd_io__top_power_lvc_wpad_tt_025C_1v80_3v30_3v30.lib
+ $::env(PDK_REF_PATH)/${io_library}/lib/sky130_fd_io__top_xres4v2_tt_tt_025C_1v80_3v30.lib
+ $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__gpiov2_pad_tt_tt_025C_1v80_3v30.lib
+ $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vccd_lvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib
+ $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vdda_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib
+ $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vssa_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib
+ $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vddio_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib
+ $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vssio_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib
+ $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vssd_lvc_clamped3_pad_tt_025C_1v80_3v30.lib
+ $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vccd_lvc_clamped3_pad_tt_025C_1v80_3v30_3v30.lib
+ $::env(PDK_REF_PATH)/${io_library}/lib/sky130_ef_io__vssd_lvc_clamped_pad_tt_025C_1v80_3v30.lib
+ $::env(PDK_REF_PATH)/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib
+"
+
diff --git a/deps/timing-scripts/requirements.txt b/deps/timing-scripts/requirements.txt
new file mode 100644
index 0000000..06df830
--- /dev/null
+++ b/deps/timing-scripts/requirements.txt
@@ -0,0 +1,2 @@
+pyverilog
+click
diff --git a/deps/timing-scripts/scripts/__pycache__/pdk_helpers.cpython-38.pyc b/deps/timing-scripts/scripts/__pycache__/pdk_helpers.cpython-38.pyc
new file mode 100644
index 0000000..fdb2f9c
--- /dev/null
+++ b/deps/timing-scripts/scripts/__pycache__/pdk_helpers.cpython-38.pyc
Binary files differ
diff --git a/deps/timing-scripts/scripts/__pycache__/verilog_parser.cpython-38.pyc b/deps/timing-scripts/scripts/__pycache__/verilog_parser.cpython-38.pyc
new file mode 100644
index 0000000..d75946a
--- /dev/null
+++ b/deps/timing-scripts/scripts/__pycache__/verilog_parser.cpython-38.pyc
Binary files differ
diff --git a/deps/timing-scripts/scripts/compare_reports.py b/deps/timing-scripts/scripts/compare_reports.py
new file mode 100644
index 0000000..1276473
--- /dev/null
+++ b/deps/timing-scripts/scripts/compare_reports.py
@@ -0,0 +1,85 @@
+#!/usr/bin/env python3
+import click
+
+from report import Report
+
+
+@click.command(
+ help="""
+ attempts to compare two sta reports
+ """
+)
+@click.option("--first", "-f", required=True, type=str)
+@click.option("--first-label", default="first", type=str)
+@click.option("--second-label", default="second", type=str)
+@click.option("--second", "-s", required=True, type=str)
+@click.option("--output", "-o", required=True, type=str)
+def main(first, second, output, first_label, second_label):
+ first_report = Report(first)
+ second_report = Report(second)
+
+ print(f"{first_label} {len(first_report.paths)}")
+ print(f"{second_label} {len(second_report.paths)}")
+ f_output = open(output, "w+")
+ f_first_diff = open(f"{first}.diff", "w+")
+ f_second_diff = open(f"{second}.diff", "w+")
+ header = (
+ f"start,end,group,type,{first_label},{second_label},"
+ f"required_first,required_second,first-second,percent"
+ )
+ f_output.write(f"{header}\n")
+
+ matches_count = 0
+ b = 0
+ c = 0
+
+ for first_path in first_report.paths:
+ if first_path in second_report.paths:
+ matches = [
+ element for element in second_report.paths if first_path == element
+ ]
+ if len(matches) == 1:
+ matches_count += 1
+ second_path = matches[0]
+ delta = first_path.slack - second_path.slack
+ percent = delta / first_path.slack * 100.0
+ path_summary = (
+ f"{first_path.start_point},{first_path.end_point},"
+ f"{first_path.path_group},"
+ f"{first_path.path_type},"
+ f"{first_path.slack:.4f},"
+ f"{second_path.slack:.4f},"
+ f"{first_path.required_time:.4f},"
+ f"{second_path.required_time:.4f},"
+ f"{delta:.4f},{percent:.2f}%"
+ )
+ f_output.write(f"{path_summary}\n")
+
+ f_first_diff.write(f"{first_path.start_point}\n")
+ f_first_diff.write(f"{first_path.end_point}\n")
+ f_first_diff.write(f"{first_path.path}\n")
+ f_second_diff.write(f"------------\n")
+
+ f_second_diff.write(f"{second_path.start_point}\n")
+ f_second_diff.write(f"{second_path.end_point}\n")
+ f_second_diff.write(f"{second_path.path}\n")
+ f_second_diff.write(f"------------\n")
+ elif len(matches) > 1:
+ b += 1
+ # print(
+ # f"{path.start_point},{path.end_point},{path.path_group},{path.path_type},{path.slack}"
+ # )
+ else:
+ c += 1
+
+ f_output.close()
+ f_first_diff.close()
+ f_second_diff.close()
+ print("matches:", matches_count)
+ print("non unique matches:", b)
+ print("unmatched:", c)
+ print("done")
+
+
+if __name__ == "__main__":
+ main()
diff --git a/deps/timing-scripts/scripts/generate_spef_mapping.py b/deps/timing-scripts/scripts/generate_spef_mapping.py
new file mode 100644
index 0000000..92c8483
--- /dev/null
+++ b/deps/timing-scripts/scripts/generate_spef_mapping.py
@@ -0,0 +1,120 @@
+from pathlib import Path
+from verilog_parser import VerilogParser
+from pdk_helpers import get_macros, get_pdk_lefs_paths
+import click
+import logging
+
+
+@click.command(
+ help="""parses a verilog gatelevel netlist and creates a
+ spef mapping file for non pdk macros. the file is used
+ along with the other scripts in the repo for proper parasitics annotation
+ during sta"""
+)
+@click.option(
+ "--input",
+ "-i",
+ required=True,
+ type=click.Path(exists=True, dir_okay=False),
+ help="input verilog netlist",
+)
+@click.option(
+ "--project-root",
+ required=True,
+ type=click.Path(exists=True, file_okay=False),
+ help="path of the project that will be used in the output spef mapping file and finding verilog modules",
+)
+@click.option(
+ "--output", "-o", required=True, type=str, help="spef mapping tcl output file"
+)
+@click.option(
+ "--pdk-path", required=True, type=click.Path(exists=True, file_okay=False)
+)
+@click.option(
+ "--macro-parent",
+ required=False,
+ type=str,
+ default="",
+ help="optional name of the parent of the macro",
+)
+@click.option("--debug", is_flag=True)
+def main(input, project_root, output, pdk_path, macro_parent, debug=False):
+ """
+ Parse a verilog netlist
+ """
+ output_path = Path(output)
+ output_path.parents[0].mkdir(parents=True, exist_ok=True)
+ logging.basicConfig(format="%(asctime)s | %(module)s | %(levelname)s | %(message)s")
+ logger = logging.getLogger()
+ if debug:
+ logger.setLevel(logging.DEBUG)
+ else:
+ logger.setLevel(logging.INFO)
+
+ logger.info(f"using project_root {project_root}")
+
+ pdk_macros = []
+ logger.info("getting pdk macros ..")
+ lef_paths = get_pdk_lefs_paths(pdk_path)
+ for lef in lef_paths:
+ pdk_macros = pdk_macros + get_macros(lef)
+ logger.debug(f"pdk has {len(pdk_macros)} macros")
+
+ with open(output_path, "w") as f:
+ for mapping in run(input, project_root, pdk_macros, logger, macro_parent):
+ logging.debug(mapping)
+ f.write(mapping)
+
+ logger.info(f"wrote to {output_path}")
+
+
+def run(input, project_root, pdk_macros, logger, macro_parent=""):
+ logger.info(f"parsing netlist {input} ..")
+ parsed = VerilogParser(input)
+ logger.info("comparing macros against pdk macros ..")
+ postfix = ".$::env(RCX_CORNER).spef"
+
+ mappings = []
+ non_pdk_instance = []
+ for instance in parsed.instances:
+ macro = parsed.instances[instance]
+ if macro not in pdk_macros:
+ logging.debug(f"{macro} not found in pdk_macros")
+ non_pdk_instance.append(instance)
+
+ logging.debug(f"# of non pdk instances {len(non_pdk_instance)}")
+ # recursion will break if above is zero
+ for instance in non_pdk_instance:
+ macro = parsed.instances[instance]
+ mapping_key = instance
+ hier_separator = "/"
+ if macro_parent != "":
+ mapping_key = f"{macro_parent}{hier_separator}{instance}"
+
+ existing_netlist = list(
+ (Path(project_root) / "verilog" / "gl").rglob(f"{macro}.v")
+ )
+ if len(existing_netlist) == 1:
+ logging.info(f"found netlist {str(existing_netlist[0])} for macro {macro}")
+ mappings += run(
+ input=str(existing_netlist[0]),
+ project_root=project_root,
+ pdk_macros=pdk_macros,
+ logger=logger,
+ macro_parent=mapping_key,
+ )
+
+ spef_dir = Path(project_root) / "signoff" / "not-found"
+ for macro_spef_file in (Path(project_root) / "signoff").rglob(f"{macro}*.spef"):
+ spef_dir = macro_spef_file.parent
+ logging.debug(f"found {macro_spef_file} for {macro}")
+ spef_rel_dir = spef_dir.relative_to(project_root)
+ macro_spef = f"$::env(PROJECT_ROOT)/{spef_rel_dir}/{macro}{postfix}"
+ mappings.append(f'set spef_mapping({mapping_key}) "{macro_spef}"\n')
+
+ return mappings
+
+
+# sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.abspath(__file__))))
+if __name__ == "__main__":
+ main()
diff --git a/deps/timing-scripts/scripts/get_macros.py b/deps/timing-scripts/scripts/get_macros.py
new file mode 100644
index 0000000..0448cd1
--- /dev/null
+++ b/deps/timing-scripts/scripts/get_macros.py
@@ -0,0 +1,116 @@
+from __future__ import absolute_import
+from __future__ import print_function
+from pathlib import Path
+from verilog_parser import VerilogParser
+from pdk_helpers import get_pdk_lefs_paths, get_macros
+import click
+import logging
+import os
+import sys
+
+
+@click.command(
+ help="""parses a verilog gatelevel netlist and
+ prints the non scl instance names
+ """
+)
+@click.option(
+ "--input",
+ "-i",
+ required=True,
+ type=click.Path(exists=True, dir_okay=False),
+ help="input verilog netlist",
+)
+@click.option(
+ "--pdk-path", required=True, type=click.Path(exists=True, file_okay=False)
+)
+@click.option(
+ "--output",
+ "-o",
+ required=True,
+ type=str,
+ help="output file in the format each line <instance_name> <instance_type>",
+)
+@click.option(
+ "--project-root",
+ required=True,
+ type=click.Path(exists=True, file_okay=False),
+ help="path of the project that will be used in the finding verilog modules",
+)
+@click.option(
+ "--macro-parent",
+ required=False,
+ type=str,
+ default="",
+ help="optional name of the parent of the macro",
+)
+@click.option("--debug", is_flag=True)
+def main(input, output, pdk_path, project_root, macro_parent, debug=False):
+ """
+ Parse a verilog netlist
+ """
+ logging.basicConfig(format="%(asctime)s | %(module)s | %(levelname)s | %(message)s")
+ logger = logging.getLogger()
+ if debug:
+ logger.setLevel(logging.DEBUG)
+ else:
+ logger.setLevel(logging.INFO)
+
+ output_path = Path(output)
+ output_path.parents[0].mkdir(parents=True, exist_ok=True)
+
+ pdk_macros = []
+ logger.info("getting pdk macros..")
+ lef_paths = get_pdk_lefs_paths(pdk_path)
+ for lef in lef_paths:
+ pdk_macros = pdk_macros + get_macros(lef)
+ logger.debug(pdk_macros)
+
+
+ with open(output_path, "w") as f:
+ for macro in run(input, project_root, pdk_macros, logger, macro_parent):
+ f.write(macro)
+
+def run(input, project_root, pdk_macros, logger, macro_parent=""):
+ logger.info(f"parsing netlist {input} ..")
+ parsed = VerilogParser(input)
+ logger.info("comparing macros against pdk macros ..")
+
+ macros = []
+ non_pdk_instance = []
+ for instance in parsed.instances:
+ macro = parsed.instances[instance]
+ if macro not in pdk_macros:
+ logging.debug(f"{macro} not found in pdk_macros")
+ non_pdk_instance.append(instance)
+
+ logging.debug(f"# of non pdk instances {len(non_pdk_instance)}")
+ # recursion will break if above is zero
+ for instance in non_pdk_instance:
+ macro = parsed.instances[instance]
+ mapping_key = instance
+ hier_separator = "/"
+ if macro_parent != "":
+ mapping_key = f"{macro_parent}{hier_separator}{instance}"
+
+ existing_netlist = list(
+ (Path(project_root) / "verilog" / "gl").rglob(f"{macro}.v")
+ )
+ if len(existing_netlist) == 1:
+ logging.info(f"found netlist {str(existing_netlist[0])} for macro {macro}")
+ macros += run(
+ input=str(existing_netlist[0]),
+ project_root=project_root,
+ pdk_macros=pdk_macros,
+ logger=logger,
+ macro_parent=mapping_key,
+ )
+
+ macros.append(f'{instance} {macro}\n')
+
+ return macros
+
+
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.abspath(__file__))))
+if __name__ == "__main__":
+ main()
diff --git a/deps/timing-scripts/scripts/openroad/rcx.tcl b/deps/timing-scripts/scripts/openroad/rcx.tcl
new file mode 100644
index 0000000..dfe3e9c
--- /dev/null
+++ b/deps/timing-scripts/scripts/openroad/rcx.tcl
@@ -0,0 +1,35 @@
+source $::env(TIMING_ROOT)/env/common.tcl
+source $::env(TIMING_ROOT)/env/$::env(LIB_CORNER).tcl
+
+set libs [split [regexp -all -inline {\S+} $libs]]
+set extra_lefs [split [regexp -all -inline {\S+} $extra_lefs]]
+
+foreach liberty $libs {
+ run_puts "read_liberty $liberty"
+}
+foreach lef $lefs {
+ run_puts "read_lef $lef"
+}
+run_puts "read_lef $sram_lef"
+
+foreach lef_file $extra_lefs {
+ run_puts "read_lef $lef_file"
+}
+
+run_puts "read_def $def"
+# don't think we need to read sdc
+
+run_puts "define_process_corner -ext_model_index 0 X"
+run_puts "extract_parasitics \
+ -ext_model_file $rcx_rules_file \
+ -lef_res"
+
+run_puts "write_spef $spef"
+run_puts "read_spef $spef"
+
+puts "spef: $spef"
+puts "def: $def"
+puts "rcx: $rcx_rules_file"
+puts "rcx-corner: $::env(RCX_CORNER)"
+puts "lib-corner: $::env(TIMING_ROOT)/env/$::env(LIB_CORNER).tcl"
+puts "tech_lef: $tech_lef"
diff --git a/deps/timing-scripts/scripts/openroad/sdf.tcl b/deps/timing-scripts/scripts/openroad/sdf.tcl
new file mode 100644
index 0000000..382ef89
--- /dev/null
+++ b/deps/timing-scripts/scripts/openroad/sdf.tcl
@@ -0,0 +1,60 @@
+source $::env(TIMING_ROOT)/env/common.tcl
+source $::env(TIMING_ROOT)/env/$::env(LIB_CORNER).tcl
+
+set libs [split [regexp -all -inline {\S+} $libs]]
+set verilogs [split [regexp -all -inline {\S+} $verilogs]]
+
+
+foreach lef $lefs {
+ if {[catch {read_lef $lef} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+ }
+}
+
+if {[catch {read_lef $sram_lef} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+}
+
+foreach lef_file $extra_lefs {
+ if {[catch {read_lef $lef_file} errmsg]} {
+ puts stderr $errmsg
+ exit 1
+ }
+}
+
+foreach liberty $libs {
+ read_liberty $liberty
+}
+
+#foreach verilog $verilogs {
+# puts "reading veriolg: $verilog"
+# read_verilog $verilog
+#}
+
+set verilog $::env(CUP_ROOT)/verilog/gl/$::env(BLOCK).v
+if { ![file exists $verilog] } {
+ set verilog $::env(MCW_ROOT)/verilog/gl/$::env(BLOCK).v
+}
+if { ![file exists $verilog] } {
+ set verilog $::env(CARAVEL_ROOT)/verilog/gl/$::env(BLOCK).v
+}
+
+read_verilog $verilog
+
+
+link_design $block
+
+puts "read_spef $spef"
+read_spef $spef
+#read_sdc $sdc
+write_sdf $sdf -divider . -include_typ
+
+puts "block: $block"
+puts "spef: $spef"
+puts "verilog: $verilog"
+puts "sdf: $sdf"
+puts "sdc: $sdc"
+puts "rcx-corner: $::env(RCX_CORNER)"
+puts "lib-corner: $::env(TIMING_ROOT)/env/$::env(LIB_CORNER).tcl"
diff --git a/deps/timing-scripts/scripts/openroad/sta-gpio_control_block.tcl b/deps/timing-scripts/scripts/openroad/sta-gpio_control_block.tcl
new file mode 100644
index 0000000..e224905
--- /dev/null
+++ b/deps/timing-scripts/scripts/openroad/sta-gpio_control_block.tcl
@@ -0,0 +1,42 @@
+source $::env(TIMING_ROOT)/env/common.tcl
+source $::env(TIMING_ROOT)/env/$::env(LIB_CORNER).tcl
+
+set libs [split [regexp -all -inline {\S+} $libs]]
+
+foreach liberty $libs {
+ read_liberty $liberty
+}
+
+
+set verilogs [list \
+ $::env(CARAVEL_ROOT)/verilog/gl/gpio_logic_high.v \
+ $::env(CARAVEL_ROOT)/verilog/gl/gpio_control_block.v \
+]
+foreach verilog $verilogs {
+ puts "read_verilog $verilog"
+ read_verilog $verilog
+}
+
+link_design $block
+
+set spef $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
+puts "read_spef $spef"
+read_spef $spef
+
+puts "read_spef -path gpio_logic_high $::env(CARAVEL_ROOT)/spef/gpio_logic_high.spef"
+read_spef -path gpio_logic_high $::env(CARAVEL_ROOT)/spef/gpio_logic_high.spef
+
+read_sdc -echo $sdc
+
+report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50
+
+report_worst_slack -max
+report_worst_slack -min
+
+puts "block: $block"
+puts "spef: $spef"
+puts "verilog: $verilog"
+puts "sdf: $sdf"
+puts "sdc: $sdc"
+puts "rcx-corner: $::env(RCX_CORNER)"
+puts "lib-corner: $::env(TIMING_ROOT)/env/$::env(LIB_CORNER).tcl"
diff --git a/deps/timing-scripts/scripts/openroad/timing_top.tcl b/deps/timing-scripts/scripts/openroad/timing_top.tcl
new file mode 100644
index 0000000..03082ff
--- /dev/null
+++ b/deps/timing-scripts/scripts/openroad/timing_top.tcl
@@ -0,0 +1,229 @@
+source $::env(TIMING_ROOT)/env/common.tcl
+source $::env(TIMING_ROOT)/env/caravel_spef_mapping-mpw7.tcl
+
+if { [file exists $::env(CUP_ROOT)/env/spef-mapping.tcl] } {
+ source $::env(CUP_ROOT)/env/spef-mapping.tcl
+} else {
+ puts "WARNING no user project spef mapping file found"
+}
+
+source $::env(TIMING_ROOT)/env/$::env(LIB_CORNER).tcl
+
+set libs [split [regexp -all -inline {\S+} $libs]]
+set verilogs [split [regexp -all -inline {\S+} $verilogs]]
+
+
+foreach liberty $libs {
+}
+
+foreach liberty $libs {
+ run_puts "read_liberty $liberty"
+}
+
+foreach verilog $verilogs {
+ run_puts "read_verilog $verilog"
+}
+
+run_puts "link_design caravel"
+
+if { $::env(SPEF_OVERWRITE) ne "" } {
+ puts "overwriting spef from "
+ puts "$spef to"
+ puts "$::env(SPEF_OVERWRITE)"
+ eval set spef $::env(SPEF_OVERWRITE)
+}
+
+set missing_spefs 0
+set missing_spefs_list ""
+run_puts "read_spef $spef"
+foreach key [array names spef_mapping] {
+ set spef_file $spef_mapping($key)
+ if { [file exists $spef_file] } {
+ run_puts "read_spef -path $key $spef_mapping($key)"
+ } else {
+ set missing_spefs 1
+ set missing_spefs_list "$missing_spefs_list $key"
+ puts "$spef_file not found"
+ if { $::env(ALLOW_MISSING_SPEF) } {
+ puts "WARNING ALLOW_MISSING_SPEF set to 1. continuing"
+ } else {
+ exit 1
+ }
+ }
+}
+
+#set sdc $::env(CARAVEL_ROOT)/signoff/caravel/caravel.sdc
+set sdc $::env(CUP_ROOT)/sdc/caravel.sdc
+run_puts "read_sdc -echo $sdc"
+
+set logs_path "$::env(PROJECT_ROOT)/signoff/caravel/openlane-signoff/timing/$::env(RCX_CORNER)/$::env(LIB_CORNER)"
+file mkdir [file dirname $logs_path]
+
+run_puts_logs "report_checks \\
+ -path_delay min \\
+ -format full_clock_expanded \\
+ -fields {slew cap input_pins nets fanout} \\
+ -no_line_splits \\
+ -group_count 100 \\
+ -slack_max 10 \\
+ -digits 4 \\
+ -endpoint_count 10 \\
+ -unique_paths_to_endpoint \\
+ "\
+ "${logs_path}-min.rpt"
+
+run_puts_logs "report_checks \\
+ -path_delay max \\
+ -format full_clock_expanded \\
+ -fields {slew cap input_pins nets fanout} \\
+ -no_line_splits \\
+ -group_count 100 \\
+ -slack_max 10 \\
+ -digits 4 \\
+ -endpoint_count 10 \\
+ -unique_paths_to_endpoint \\
+ "\
+ "${logs_path}-max.rpt"
+
+run_puts_logs "report_checks \\
+ -path_delay min \\
+ -format full_clock_expanded \\
+ -fields {slew cap input_pins nets fanout} \\
+ -no_line_splits \\
+ -path_group hk_serial_clk \\
+ -group_count 100 \\
+ -slack_max 10 \\
+ -digits 4 \\
+ -unique_paths_to_endpoint \\
+ "\
+ "${logs_path}-hk_serial_clk-min.rpt"
+
+
+run_puts_logs "report_checks \\
+ -path_delay max \\
+ -format full_clock_expanded \\
+ -fields {slew cap input_pins nets fanout} \\
+ -no_line_splits \\
+ -path_group hk_serial_clk \\
+ -group_count 100 \\
+ -slack_max 10 \\
+ -digits 4 \\
+ -unique_paths_to_endpoint \\
+ "\
+ "${logs_path}-hk_serial_clk-max.rpt"
+
+run_puts_logs "report_checks \\
+ -path_delay max \\
+ -format full_clock_expanded \\
+ -fields {slew cap input_pins nets fanout} \\
+ -no_line_splits \\
+ -path_group hkspi_clk \\
+ -group_count 100 \\
+ -slack_max 10 \\
+ -digits 4 \\
+ -unique_paths_to_endpoint \\
+ "\
+ "${logs_path}-hkspi_clk-max.rpt"
+
+run_puts_logs "report_checks \\
+ -path_delay min \\
+ -format full_clock_expanded \\
+ -fields {slew cap input_pins nets fanout} \\
+ -no_line_splits \\
+ -path_group hkspi_clk \\
+ -group_count 100 \\
+ -slack_max 10 \\
+ -digits 4 \\
+ -unique_paths_to_endpoint \\
+ "\
+ "${logs_path}-hkspi_clk-min.rpt"
+
+run_puts_logs "report_checks \\
+ -path_delay min \\
+ -format full_clock_expanded \\
+ -fields {slew cap input_pins nets fanout} \\
+ -no_line_splits \\
+ -path_group clk \\
+ -group_count 100 \\
+ -slack_max 10 \\
+ -digits 4 \\
+ -unique_paths_to_endpoint \\
+ "\
+ "${logs_path}-clk-min.rpt"
+
+run_puts_logs "report_checks \\
+ -path_delay max \\
+ -format full_clock_expanded \\
+ -fields {slew cap input_pins nets fanout} \\
+ -no_line_splits \\
+ -path_group clk \\
+ -group_count 100 \\
+ -slack_max 10 \\
+ -digits 4 \\
+ -unique_paths_to_endpoint \\
+ "\
+ "${logs_path}-clk-max.rpt"
+
+run_puts_logs "report_checks \\
+ -path_delay min \\
+ -through [get_cells soc] \\
+ -format full_clock_expanded \\
+ -fields {slew cap input_pins nets fanout} \\
+ -no_line_splits \\
+ -group_count 100 \\
+ -slack_max 10 \\
+ -digits 4 \\
+ -unique_paths_to_endpoint \\
+ "\
+ "${logs_path}-soc-min.rpt"
+
+run_puts_logs "report_checks \\
+ -path_delay max \\
+ -through [get_cells soc] \\
+ -format full_clock_expanded \\
+ -fields {slew cap input_pins nets fanout} \\
+ -no_line_splits \\
+ -group_count 100 \\
+ -slack_max 10 \\
+ -digits 4 \\
+ -unique_paths_to_endpoint \\
+ "\
+ "${logs_path}-soc-max.rpt"
+
+run_puts_logs "report_checks \\
+ -path_delay min \\
+ -through [get_cells mprj] \\
+ -format full_clock_expanded \\
+ -fields {slew cap input_pins nets fanout} \\
+ -no_line_splits \\
+ -group_count 100 \\
+ -slack_max 40 \\
+ -digits 4 \\
+ -unique_paths_to_endpoint \\
+ "\
+ "${logs_path}-mprj-min.rpt"
+
+run_puts_logs "report_checks \\
+ -path_delay max \\
+ -through [get_cells mprj] \\
+ -format full_clock_expanded \\
+ -fields {slew cap input_pins nets fanout} \\
+ -no_line_splits \\
+ -group_count 100 \\
+ -slack_max 40 \\
+ -digits 4 \\
+ -unique_paths_to_endpoint \\
+ "\
+ "${logs_path}-mprj-max.rpt"
+
+run_puts "report_parasitic_annotation -report_unannotated > ${logs_path}-unannotated.log"
+if { $missing_spefs } {
+ puts "there are missing spefs. check the log for ALLOW_MISSING_SPEF"
+ puts "the following macros don't have spefs"
+ foreach spef $missing_spefs_list {
+ puts "$spef"
+ }
+}
+report_parasitic_annotation
+puts "you may want to edit sdc: $sdc to change i/o constraints"
+puts "check $logs_path"
diff --git a/deps/timing-scripts/scripts/pdk_helpers.py b/deps/timing-scripts/scripts/pdk_helpers.py
new file mode 100644
index 0000000..6536e9b
--- /dev/null
+++ b/deps/timing-scripts/scripts/pdk_helpers.py
@@ -0,0 +1,21 @@
+from typing import List
+import os
+
+def get_pdk_lefs_paths(pdk_path: str) -> List[str]:
+ lef_paths = []
+ for root, dirs, files in os.walk(pdk_path):
+ for file in files:
+ filename, file_extension = os.path.splitext(f"{file}")
+ if file_extension == ".lef":
+ lef_paths.append(f"{root}/{file}")
+ return lef_paths
+
+
+def get_macros(lef_file: str) -> List[str]:
+ macros = []
+ with open(lef_file) as f:
+ for line in f.readlines():
+ if "MACRO" in line:
+ macro_name = line.split()[1]
+ macros.append(macro_name)
+ return macros
diff --git a/deps/timing-scripts/scripts/report.py b/deps/timing-scripts/scripts/report.py
new file mode 100644
index 0000000..1b96505
--- /dev/null
+++ b/deps/timing-scripts/scripts/report.py
@@ -0,0 +1,83 @@
+from timing_path import TimingPath
+
+
+class Report:
+ def __init__(self, report_file):
+ self.report_file = report_file
+ self.paths = []
+ self.input_output_paths = []
+ self.input_flipflop_paths = []
+ self.flipflop_flipflop_paths = []
+ self.flipflop_output_paths = []
+ self.build_db()
+ self.classify_paths()
+
+ def classify_paths(self):
+ for path in self.paths:
+ path_category = path.category
+ if path_category == "input-output":
+ self.input_output_paths.append(path)
+ elif path_category == "input-flipflop":
+ self.input_flipflop_paths.append(path)
+ elif path_category == "flipflop-flipflop":
+ self.flipflop_flipflop_paths.append(path)
+ elif path_category == "flipflop-output":
+ self.flipflop_output_paths.append(path)
+
+ def build_db(self):
+ file = open(self.report_file)
+ start_point = end_point = path_group = path_values = ""
+
+ line = file.readline()
+ while line != "":
+ line = line.strip()
+ if "Startpoint" in line:
+ x = file.tell()
+ start_point = " ".join(line.split(" ")[1:])
+ line2 = file.readline()
+ if "Endpoint" not in line2:
+ start_point += line2
+ else:
+ file.seek(x)
+ elif "Endpoint" in line:
+ x = file.tell()
+ end_point = " ".join(line.split(" ")[1:])
+ line2 = file.readline()
+ if "Path Group" not in line2:
+ end_point += line2
+ else:
+ file.seek(x)
+ elif "Path Group" in line:
+ path_group = line.split(" ")[2]
+ elif "Path Type" in line:
+ path_type = line.split(" ")[2]
+
+ path_line = file.readline()
+ while path_line != "":
+ if "Startpoint" in path_line:
+ path_object = TimingPath(
+ start_point=start_point.rstrip(),
+ end_point=end_point.rstrip(),
+ path_group=path_group.rstrip(),
+ path_type=path_type,
+ path=path_values,
+ )
+ self.paths.append(path_object)
+
+ path_line = path_line.strip()
+ start_point = " ".join(path_line.split(" ")[1:])
+ x = file.tell()
+ line2 = file.readline()
+ if "Endpoint" not in line2:
+ start_point += line2
+ else:
+ file.seek(x)
+
+ path_values = ""
+ break
+ else:
+ path_values += path_line
+ path_line = file.readline()
+ line = file.readline()
+
+ file.close()
diff --git a/deps/timing-scripts/scripts/summarize_report.py b/deps/timing-scripts/scripts/summarize_report.py
new file mode 100644
index 0000000..efc0317
--- /dev/null
+++ b/deps/timing-scripts/scripts/summarize_report.py
@@ -0,0 +1,44 @@
+#!/usr/bin/env python3
+
+import argparse
+from report import Report
+from timing_path import TimingPath
+
+parser = argparse.ArgumentParser(
+ description="summarizes sta reports. tested on pt and opensta"
+)
+parser.add_argument("--input", "-i", required=True)
+parser.add_argument("--output", "-o", required=True)
+
+args = parser.parse_args()
+report_file = args.input
+output_file = args.output
+
+report = Report(report_file)
+
+output_files_stream = open(f"{output_file}", "w")
+
+output_files_stream.write(
+ f"--------------input-flipflop_paths#{len(report.input_flipflop_paths)}-------------------\n"
+)
+output_files_stream.write(TimingPath.get_header())
+for path in report.input_flipflop_paths:
+ output_files_stream.write(path.summarize())
+output_files_stream.write(
+ f"--------------input-output_paths#{len(report.input_output_paths)}---------------------\n"
+)
+output_files_stream.write(TimingPath.get_header())
+for path in report.input_output_paths:
+ output_files_stream.write(path.summarize())
+output_files_stream.write(
+ f"--------------flipflop-flipflop_paths#{len(report.flipflop_flipflop_paths)}----------------\n"
+)
+output_files_stream.write(TimingPath.get_header())
+for path in report.flipflop_flipflop_paths:
+ output_files_stream.write(path.summarize())
+output_files_stream.write(
+ f"--------------flipflop-output_paths#{len(report.flipflop_output_paths)}------------------\n"
+)
+output_files_stream.write(TimingPath.get_header())
+for path in report.flipflop_output_paths:
+ output_files_stream.write(path.summarize())
diff --git a/deps/timing-scripts/scripts/timing_path.py b/deps/timing-scripts/scripts/timing_path.py
new file mode 100644
index 0000000..c77a624
--- /dev/null
+++ b/deps/timing-scripts/scripts/timing_path.py
@@ -0,0 +1,112 @@
+import textwrap
+import re
+
+
+class TimingPath:
+ def __init__(self, start_point, end_point, path_group, path_type, path):
+ self.start_point = start_point
+ self.end_point = end_point
+ self.path_group = path_group
+ self.path_type = path_type
+ self.path = path
+ self.category = ""
+ self.slack = None
+ self.edges = ""
+ self.required_time = None
+ self.arrival_time = None
+ self.find_category()
+ self.simplify_points()
+ self.find_slack()
+ self.find_required()
+ self.find_arrival()
+ self.id = self.start_point + self.end_point + self.path_group + self.path_type
+
+ def find_required(self):
+ for line in self.path.split("\n"):
+ if "required time" in line:
+ self.required_time = float(re.findall(
+ r"[+-]? *(?:\d+(?:\.\d*)?|\.\d+)(?:[eE][+-]?\d+)?", line
+ )[0].strip())
+ break
+
+ def find_arrival(self):
+ for line in self.path:
+ if "arrival time" in line:
+ self.arrival_time = float(re.findall(
+ r"[+-]? *(?:\d+(?:\.\d*)?|\.\d+)(?:[eE][+-]?\d+)?", line
+ )[0].strip())
+ break
+
+ def find_edges(self):
+ split_path = self.path.split("\n")
+ edge = "f"
+ for line in split_path:
+ if "^" in line or " r" in line:
+ edge = "r"
+ self.edges = self.edges + edge
+ elif "v" in line or " f" in line:
+ edge = "f"
+ self.edges = self.edges + edge
+ elif "data arrival time" in line:
+ break
+
+ def simplify_points(self):
+ if len(self.start_point.split()) > 1:
+ self.start_point = self.start_point.split()[0]
+ if len(self.end_point.split()) > 1:
+ self.end_point = self.end_point.split()[0]
+
+ @classmethod
+ def get_header(cls):
+ start_point = "start_point"
+ end_point = "end_point"
+ group = "group"
+ type = "type"
+ slack = "slack"
+ return f"{start_point},{end_point},{group},{type},{slack}\n"
+
+ def find_slack(self):
+ slack = ""
+ for line in self.path.splitlines():
+ if "slack" in line:
+ slack = textwrap.dedent(line)
+ break
+ self.slack = re.findall(
+ r"[+-]? *(?:\d+(?:\.\d*)?|\.\d+)(?:[eE][+-]?\d+)?", slack
+ )[0].strip()
+ self.slack = float(self.slack)
+
+ def summarize(self):
+ slack_value = self.slack
+ group = self.path_group
+ type = self.path_type
+ start_point = self.start_point
+ end_point = self.end_point
+ return f"{start_point},{end_point},{group},{type},{slack_value:.4f}\n"
+
+ def find_category(self):
+ start = ""
+ end = ""
+ if "input" in self.start_point:
+ start = "input"
+ else:
+ start = "flipflop"
+ if "output" in self.end_point:
+ end = "output"
+ else:
+ end = "flipflop"
+
+ self.category = f"{start}-{end}"
+
+ def __eq__(self, other):
+ return self.id == other.id
+
+ def __str__(self):
+ return f"""
+Startpoint: {self.start_point}
+Endpoint: {self.end_point}
+Path group: {self.path_group}
+Path type: {self.path_type}
+Path:
+{self.path}
+"""
diff --git a/deps/timing-scripts/scripts/verilog_parser.py b/deps/timing-scripts/scripts/verilog_parser.py
new file mode 100644
index 0000000..0c4e4f1
--- /dev/null
+++ b/deps/timing-scripts/scripts/verilog_parser.py
@@ -0,0 +1,20 @@
+from pyverilog.vparser.parser import parse
+
+class VerilogParser():
+ def __init__(self, verilog_netlist):
+ self.verilog_netlist = [verilog_netlist]
+ ast, _ = parse(self.verilog_netlist)
+ top_definition = None
+ self.instances = {}
+
+ for definition in ast.description.definitions:
+ def_type = type(definition).__name__
+ if def_type == "ModuleDef":
+ top_definition = definition
+
+ # Loop over each node under the top module definition
+ for item in top_definition.items:
+ item_type = type(item).__name__
+ if item_type == "InstanceList": # Module instances
+ instance = item.instances[0]
+ self.instances[instance.name] = instance.module
diff --git a/deps/timing-scripts/timing.mk b/deps/timing-scripts/timing.mk
new file mode 100644
index 0000000..148b384
--- /dev/null
+++ b/deps/timing-scripts/timing.mk
@@ -0,0 +1,307 @@
+OPENLANE_TAG ?= 2022.02.23_02.50.41
+OPENLANE_IMAGE_NAME ?= efabless/openlane:$(OPENLANE_TAG)
+export PDK ?= sky130A
+export RCX_CORNER ?= nom
+export LIB_CORNER ?= t
+export ALLOW_MISSING_SPEF ?= 1
+export PDK_REF_PATH = $(PDK_ROOT)/$(PDK)/libs.ref/
+export PDK_TECH_PATH = $(PDK_ROOT)/$(PDK)/libs.tech/
+export PROJECT_ROOT ?= $(CARAVEL_ROOT)
+
+logs-dir = $(PROJECT_ROOT)/logs
+logs = $(logs-dir)/rcx $(logs-dir)/sdf $(logs-dir)/top $(logs-dir)/sta
+$(logs):
+ mkdir -p $@
+
+SPEF_OVERWRITE ?= ""
+define docker_run_base
+ docker run \
+ --rm \
+ -e PROJECT_ROOT=$(PROJECT_ROOT) \
+ -e BLOCK=$1 \
+ -e PDK=$(PDK) \
+ -e LIB_CORNER=$(LIB_CORNER) \
+ -e RCX_CORNER=$(RCX_CORNER) \
+ -e MCW_ROOT=$(MCW_ROOT) \
+ -e SPEF_OVERWRITE=$(SPEF_OVERWRITE) \
+ -e CUP_ROOT=$(CUP_ROOT) \
+ -e CARAVEL_ROOT=$(CARAVEL_ROOT) \
+ -e TIMING_ROOT=$(TIMING_ROOT) \
+ -e PDK_REF_PATH=$(PDK_ROOT)/$(PDK)/libs.ref/ \
+ -e PDK_TECH_PATH=$(PDK_ROOT)/$(PDK)/libs.tech/ \
+ -e ALLOW_MISSING_SPEF=$(ALLOW_MISSING_SPEF) \
+ -v $(PDK_ROOT):$(PDK_ROOT) \
+ -v $(CUP_ROOT):$(CUP_ROOT) \
+ -v $(MCW_ROOT):$(MCW_ROOT) \
+ -v $(TIMING_ROOT):$(TIMING_ROOT) \
+ -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
+ -v $(HOME):$(HOME) \
+ -u $(shell id -u $(USER)):$(shell id -g $(USER)) \
+ $(OPENLANE_IMAGE_NAME)
+endef
+
+
+define docker_run_sta
+ $(call docker_run_base,$1) \
+ bash -c "set -eo pipefail && sta -exit $(TIMING_ROOT)/scripts/openroad/sta-$*.tcl \
+ |& tee $(logs-dir)/sta/$*-$(RCX_CORNER)-$(LIB_CORNER).log"
+ @echo "logged to $(logs-dir)/sta/$*-$(RCX_CORNER)-$(LIB_CORNER).log"
+endef
+
+define docker_run_sdf
+ $(call docker_run_base,$1) \
+ bash -c "set -eo pipefail && openroad -exit $(TIMING_ROOT)/scripts/openroad/sdf.tcl \
+ |& tee $(logs-dir)/sdf/$*-$(RCX_CORNER)-$(LIB_CORNER).log"
+ @echo "logged to $(logs-dir)/sdf/$*-$(RCX_CORNER)-$(LIB_CORNER).log"
+endef
+
+define docker_run_rcx
+ $(call docker_run_base,$1) \
+ bash -c "set -eo pipefail && openroad -exit $(TIMING_ROOT)/scripts/openroad/rcx.tcl \
+ |& tee $(logs-dir)/rcx/$*-$(RCX_CORNER)-$(LIB_CORNER).log"
+ @echo "logged to $(logs-dir)/rcx/$*-$(RCX_CORNER)-$(LIB_CORNER).log"
+endef
+
+blocks = $(shell cd $(CARAVEL_ROOT)/openlane && find * -maxdepth 0 -type d)
+blocks := $(subst user_project_wrapper,,$(blocks))
+ifneq ($(CARAVEL_ROOT),$(MCW_ROOT))
+blocks += $(shell cd $(MCW_ROOT)/openlane && find * -maxdepth 0 -type d)
+endif
+ifneq ($(CARAVEL_ROOT),$(CUP_ROOT))
+blocks += $(shell cd $(CUP_ROOT)/openlane && find * -maxdepth 0 -type d)
+endif
+
+# we don't have user_id_programming.def)
+# mgmt_protect_hvl use hvl library which we don't handle yet
+blocks := $(subst mgmt_protect_hvl,,$(blocks))
+blocks := $(subst chip_io_alt,,$(blocks))
+blocks := $(subst user_id_programming,,$(blocks))
+blocks := $(subst user_analog_project_wrapper,,$(blocks))
+blocks := $(subst caravan,,$(blocks))
+
+defs = $(shell cd $(CARAVEL_ROOT)/def && find *.def -maxdepth 0 -type f ! -name 'user_project_wrapper.def')
+ifneq ($(CARAVEL_ROOT),$(MCW_ROOT))
+defs += $(shell cd $(MCW_ROOT)/def && find *.def -maxdepth 0 -type f)
+endif
+ifneq ($(CARAVEL_ROOT),$(CUP_ROOT))
+defs += $(shell cd $(CUP_ROOT)/def && find *.def -maxdepth 0 -type f)
+endif
+
+rcx-blocks = $(defs:%.def=rcx-%)
+rcx-blocks-nom = $(blocks:%=rcx-%-nom)
+rcx-blocks-max = $(blocks:%=rcx-%-max)
+rcx-blocks-min = $(blocks:%=rcx-%-min)
+rcx-blocks-t = $(blocks:%=rcx-%-t)
+rcx-blocks-f = $(blocks:%=rcx-%-f)
+rcx-blocks-s = $(blocks:%=rcx-%-s)
+
+sdf-blocks = $(blocks:%=sdf-%)
+sdf-blocks-t = $(blocks:%=sdf-%-t)
+sdf-blocks-f = $(blocks:%=sdf-%-f)
+sdf-blocks-s = $(blocks:%=sdf-%-s)
+sdf-blocks-nom = $(blocks:%=sdf-%-nom)
+sdf-blocks-min = $(blocks:%=sdf-%-min)
+sdf-blocks-max = $(blocks:%=sdf-%-max)
+
+$(sdf-blocks): sdf-%:
+ $(MAKE) -f timing.mk sdf-$*-nom
+ $(MAKE) -f timing.mk sdf-$*-min
+ $(MAKE) -f timing.mk sdf-$*-max
+
+$(sdf-blocks-nom): export RCX_CORNER = nom
+$(sdf-blocks-min): export RCX_CORNER = min
+$(sdf-blocks-max): export RCX_CORNER = max
+$(sdf-blocks-nom): sdf-%-nom: sdf-%-t sdf-%-f sdf-%-s
+$(sdf-blocks-min): sdf-%-min: sdf-%-t sdf-%-f sdf-%-s
+$(sdf-blocks-max): sdf-%-max: sdf-%-t sdf-%-f sdf-%-s
+
+$(sdf-blocks-t): export LIB_CORNER = t
+$(sdf-blocks-s): export LIB_CORNER = s
+$(sdf-blocks-f): export LIB_CORNER = f
+$(sdf-blocks-t): sdf-%-t:
+ $(call docker_run_sdf,$*)
+$(sdf-blocks-s): sdf-%-s:
+ $(call docker_run_sdf,$*)
+$(sdf-blocks-f): sdf-%-f:
+ $(call docker_run_sdf,$*)
+
+
+sta-blocks = $(blocks:%=sta-%)
+sta-blocks-t = $(blocks:%=sta-%-t)
+sta-blocks-f = $(blocks:%=sta-%-f)
+sta-blocks-s = $(blocks:%=sta-%-s)
+sta-blocks-nom = $(blocks:%=sta-%-nom)
+sta-blocks-min = $(blocks:%=sta-%-min)
+sta-blocks-max = $(blocks:%=sta-%-max)
+
+$(sta-blocks): sta-%:
+ $(MAKE) -f timing.mk sta-$*-nom
+ $(MAKE) -f timing.mk sta-$*-min
+ $(MAKE) -f timing.mk sta-$*-max
+
+$(sta-blocks-nom): export RCX_CORNER = nom
+$(sta-blocks-min): export RCX_CORNER = min
+$(sta-blocks-max): export RCX_CORNER = max
+$(sta-blocks-nom): sta-%-nom: sta-%-t sta-%-f sta-%-s
+$(sta-blocks-min): sta-%-min: sta-%-t sta-%-f sta-%-s
+$(sta-blocks-max): sta-%-max: sta-%-t sta-%-f sta-%-s
+
+$(sta-blocks-t): export LIB_CORNER = t
+$(sta-blocks-s): export LIB_CORNER = s
+$(sta-blocks-f): export LIB_CORNER = f
+$(sta-blocks-t): sta-%-t: $(logs-dir)/sta
+ $(call docker_run_sta,$*)
+$(sta-blocks-s): sta-%-s:
+ $(call docker_run_sta,$*)
+$(sta-blocks-f): sta-%-f:
+ $(call docker_run_sta,$*)
+
+
+$(rcx-blocks): rcx-%: $(rcx-requirements)
+ $(MAKE) -f timing.mk rcx-$*-nom &
+ $(MAKE) -f timing.mk rcx-$*-min &
+ $(MAKE) -f timing.mk rcx-$*-max
+
+$(rcx-blocks-nom): export RCX_CORNER = nom
+$(rcx-blocks-min): export RCX_CORNER = min
+$(rcx-blocks-max): export RCX_CORNER = max
+$(rcx-blocks-nom): rcx-%-nom: rcx-%-t
+$(rcx-blocks-min): rcx-%-min: rcx-%-t
+$(rcx-blocks-max): rcx-%-max: rcx-%-t
+
+$(rcx-blocks-t): export LIB_CORNER = t
+$(rcx-blocks-s): export LIB_CORNER = s
+$(rcx-blocks-f): export LIB_CORNER = f
+$(rcx-blocks-t): rcx-%-t: $(logs-dir)/rcx
+ $(call docker_run_rcx,$*)
+$(rcx-blocks-s): rcx-%-s:
+ $(call docker_run_rcx,$*)
+$(rcx-blocks-f): rcx-%-f:
+ $(call docker_run_rcx,$*)
+
+
+define docker_run_caravel_timing
+ $(call docker_run_base,caravel) \
+ bash -c "set -eo pipefail && sta -no_splash -exit $(TIMING_ROOT)/scripts/openroad/timing_top.tcl |& tee \
+ $(logs-dir)/top/caravel-timing-$$(basename $(LIB_CORNER))-$(RCX_CORNER).log"
+ @echo "logged to $(logs-dir)/top/caravel-timing-$$(basename $(LIB_CORNER))-$(RCX_CORNER).log"
+endef
+
+
+caravel-timing-typ-targets = caravel-timing-typ-nom
+caravel-timing-typ-targets += caravel-timing-typ-min
+caravel-timing-typ-targets += caravel-timing-typ-max
+
+caravel-timing-slow-targets = caravel-timing-slow-nom
+caravel-timing-slow-targets += caravel-timing-slow-min
+caravel-timing-slow-targets += caravel-timing-slow-max
+
+caravel-timing-fast-targets = caravel-timing-fast-nom
+caravel-timing-fast-targets += caravel-timing-fast-min
+caravel-timing-fast-targets += caravel-timing-fast-max
+
+caravel-timing-targets = $(caravel-timing-slow-targets)
+caravel-timing-targets += $(caravel-timing-fast-targets)
+caravel-timing-targets += $(caravel-timing-typ-targets)
+
+.PHONY: caravel-timing-typ
+$(caravel-timing-typ-targets): export LIB_CORNER = t
+caravel-timing-typ: caravel-timing-typ-nom caravel-timing-typ-min caravel-timing-typ-max
+
+.PHONY: caravel-timing-typ-nom
+.PHONY: caravel-timing-typ-min
+.PHONY: caravel-timing-typ-max
+caravel-timing-typ-nom: export RCX_CORNER = nom
+caravel-timing-typ-min: export RCX_CORNER = min
+caravel-timing-typ-max: export RCX_CORNER = max
+
+.PHONY: caravel-timing-slow
+$(caravel-timing-slow-targets): export LIB_CORNER = s
+caravel-timing-slow: caravel-timing-slow-nom caravel-timing-slow-min caravel-timing-slow-max
+
+.PHONY: caravel-timing-slow-nom
+.PHONY: caravel-timing-slow-min
+.PHONY: caravel-timing-slow-max
+caravel-timing-slow-nom: export RCX_CORNER = nom
+caravel-timing-slow-min: export RCX_CORNER = min
+caravel-timing-slow-max: export RCX_CORNER = max
+
+.PHONY: caravel-timing-fast
+$(caravel-timing-fast-targets): export LIB_CORNER = f
+caravel-timing-fast: caravel-timing-fast-nom caravel-timing-fast-min caravel-timing-fast-max
+
+.PHONY: caravel-timing-fast-nom
+.PHONY: caravel-timing-fast-min
+.PHONY: caravel-timing-fast-max
+caravel-timing-fast-nom: export RCX_CORNER = nom
+caravel-timing-fast-min: export RCX_CORNER = min
+caravel-timing-fast-max: export RCX_CORNER = max
+
+$(caravel-timing-targets): $(logs-dir)/top
+ $(call docker_run_caravel_timing)
+
+
+# some useful dev double checking
+#
+rcx-requirements = $(CARAVEL_ROOT)/def/%.def
+rcx-requirements += $(CARAVEL_ROOT)/lef/%.lef
+rcx-requirements += $(CARAVEL_ROOT)/sdc/%.sdc
+rcx-requirements += $(CARAVEL_ROOT)/verilog/gl/%.v
+
+exceptions = $(MCW_ROOT)/lef/caravel.lef
+exceptions += $(MCW_ROOT)/lef/caravan.lef
+# lets ignore these for now
+exceptions += $(MCW_ROOT)/sdc/user_analog_project_wrapper.sdc
+exceptions += $(MCW_ROOT)/sdc/user_project_wrapper.sdc
+exceptions += $(MCW_ROOT)/verilog/gl/user_analog_project_wrapper.v
+exceptions += $(MCW_ROOT)/verilog/gl/user_project_wrapper.v
+
+.PHONY: list-rcx
+.PHONY: list-sdf
+.PHONY: rcx-all
+list-rcx:
+ @blocks="$(rcx-blocks)";\
+ for block in $${blocks}; do echo "$$block"; done
+list-sdf:
+ @echo $(sdf-blocks)
+list-sta:
+ @echo $(sta-blocks)
+rcx-all: $(rcx-blocks)
+
+$(exceptions):
+ $(warning we don't need lefs for $@ but take note anyway)
+
+$(CARAVEL_ROOT)/def/%.def: $(MCW_ROOT)/def/%.def ;
+$(MCW_ROOT)/def/%.def: $(CUP_ROOT)/def/%.def ;
+$(CUP_ROOT)/def/%.def:
+ $(error error if you are here it probably means that $@.def is mising from mcw and caravel)
+
+$(CARAVEL_ROOT)/lef/%.lef: $(MCW_ROOT)/lef/%.lef ;
+$(MCW_ROOT)/lef/%.lef: $(CUP_ROOT)/lef/%.lef ;
+$(CUP_ROOT)/lef/%.lef:
+ $(error error if you are here it probably means that $@.lef is mising from mcw and caravel)
+
+$(CARAVEL_ROOT)/sdc/%.sdc: $(MCW_ROOT)/sdc/%.sdc ;
+$(MCW_ROOT)/sdc/%.sdc: $(CUP_ROOT)/sdc/%.sdc ;
+$(CUP_ROOT)/sdc/%.sdc:
+ $(error error if you are here it probably means that $@.sdc is mising from mcw and caravel)
+
+$(CARAVEL_ROOT)/verilog/gl/%.v: $(MCW_ROOT)/verilog/gl/%.v ;
+$(MCW_ROOT)/verilog/gl/%.v: $(CUP_ROOT)/verilog/gl/%.v ;
+$(CUP_ROOT)/verilog/gl/%.v:
+ $(error error if you are here it probably means that gl/$@.v is mising from mcw and caravel)
+
+check_defined = \
+ $(strip $(foreach 1,$1, \
+ $(call __check_defined,$1,$(strip $(value 2)))))
+__check_defined = \
+ $(if $(value $1),, \
+ $(error Undefined $1$(if $2, ($2))))
+
+$(call check_defined, \
+ MCW_ROOT \
+ CUP_ROOT \
+ PDK_ROOT \
+ CARAVEL_ROOT \
+ TIMING_ROOT \
+)
diff --git a/openlane/Makefile b/openlane/Makefile
index c21989a..3c48c94 100644
--- a/openlane/Makefile
+++ b/openlane/Makefile
@@ -43,29 +43,15 @@
@sleep 1
@if [ -f ./$*/interactive.tcl ]; then\
- docker run --rm -v $(OPENLANE_ROOT):/openlane \
- -v $(PDK_ROOT):$(PDK_ROOT) \
+ docker run --rm \
-v $(PWD)/..:$(PWD)/.. \
- -v $(MCW_ROOT):$(MCW_ROOT) \
- -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
- -e MCW_ROOT=$(MCW_ROOT) \
- -e PDK_ROOT=$(PDK_ROOT) \
- -e CARAVEL_ROOT=$(CARAVEL_ROOT) \
- -e PDK=$(PDK) \
-e TEST_MISMATCHES=tools \
-e MISMATCHES_OK=1 \
-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
$(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_INTERACTIVE_COMMAND);\
else\
- docker run --rm -v $(OPENLANE_ROOT):/openlane \
- -v $(PDK_ROOT):$(PDK_ROOT) \
+ docker run --rm \
-v $(PWD)/..:$(PWD)/.. \
- -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
- -v $(MCW_ROOT):$(MCW_ROOT) \
- -e MCW_ROOT=$(MCW_ROOT) \
- -e PDK=$(PDK) \
- -e PDK_ROOT=$(PDK_ROOT) \
- -e CARAVEL_ROOT=$(CARAVEL_ROOT) \
-e TEST_MISMATCHES=tools \
-e MISMATCHES_OK=1 \
-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
diff --git a/sdc/caravel.sdc b/sdc/caravel.sdc
new file mode 100644
index 0000000..70ea73d
--- /dev/null
+++ b/sdc/caravel.sdc
@@ -0,0 +1,346 @@
+### Caravel Signoff SDC
+### Rev 3
+### Date: 28/10/2022
+### Reference SDC: $CARAVEL_ROOT/signoff/caravel/caravel.sdc
+
+## MASTER CLOCKS
+## Reduce the clock speed from 25ns 40ns
+create_clock -name clk -period 40 [get_ports {clock}]
+
+create_clock -name hkspi_clk -period 100 [get_pins {housekeeping/mgmt_gpio_in[4]} ]
+create_clock -name hk_serial_clk -period 50 [get_pins {housekeeping/serial_clock}]
+create_clock -name hk_serial_load -period 1000 [get_pins {housekeeping/serial_load}]
+# hk_serial_clk period is x2 core clock
+
+### User Project Clocks
+create_generated_clock -name wb_clk -add -source [get_ports {clock}] -master_clock [get_clocks clk] -divide_by 1 -comment {Wishbone User Clock} [get_pins mprj/wb_clk_i]
+create_clock -name int_pll_clock -period 5.0000 [get_pins {mprj/u_pinmux/int_pll_clock}]
+
+create_clock -name wbs_ref_clk -period 5.0000 [get_pins {mprj/u_wb_host/u_reg.u_wbs_ref_clkbuf.u_buf/X}]
+create_clock -name wbs_clk_i -period 26.0000 [get_pins {mprj/u_wb_host/wbs_clk_out}]
+
+create_clock -name cpu_ref_clk -period 5.0000 [get_pins {mprj/u_wb_host/u_reg.u_cpu_ref_clkbuf.u_buf/X}]
+create_clock -name cpu_clk -period 40.0000 [get_pins {mprj/u_wb_host/cpu_clk}]
+
+create_clock -name rtc_ref_clk -period 50.0000 [get_pins {mprj/u_pinmux/u_glbl_reg.u_rtc_ref_clkbuf.u_buf/X}]
+create_clock -name rtc_clk -period 50.0000 [get_pins {mprj/u_pinmux/u_glbl_reg.u_clkbuf_rtc.u_buf/X}]
+
+create_clock -name pll_ref_clk -period 20.0000 [get_pins {mprj/u_pinmux/pll_ref_clk}]
+create_clock -name pll_clk_0 -period 12.0000 [get_pins {mprj/u_pll/ringosc.ibufp01/Y}]
+
+create_clock -name usb_ref_clk -period 6.0000 [get_pins {mprj/u_pinmux/u_glbl_reg.u_usb_ref_clkbuf.u_buf/X}]
+create_clock -name usb_clk -period 20.0000 [get_pins {mprj/u_pinmux/u_glbl_reg.u_clkbuf_usb.u_buf/X}]
+create_clock -name uarts0_clk -period 100.0000 [get_pins {mprj/u_uart_i2c_usb_spi/u_uart0_core.u_lineclk_buf.genblk1.u_mux/X}]
+create_clock -name uarts1_clk -period 100.0000 [get_pins {mprj/u_uart_i2c_usb_spi/u_uart1_core.u_lineclk_buf.genblk1.u_mux/X}]
+create_clock -name uartm_clk -period 100.0000 [get_pins {mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X}]
+create_clock -name dbg_ref_clk -period 12.0000 [get_pins {mprj/u_pinmux/u_glbl_reg.u_clkbuf_dbg_ref.u_buf/X}]
+
+set_clock_uncertainty 0.1000 [all_clocks]
+
+set_clock_groups \
+ -name clock_group \
+ -logically_exclusive \
+ -group [get_clocks {wb_clk clk}]\
+ -group [get_clocks {hk_serial_clk}]\
+ -group [get_clocks {hk_serial_load}]\
+ -group [get_clocks {hkspi_clk}]\
+ -group [get_clocks {int_pll_clock}]\
+ -group [get_clocks {wbs_clk_i}]\
+ -group [get_clocks {wbs_ref_clk}]\
+ -group [get_clocks {cpu_clk}]\
+ -group [get_clocks {cpu_ref_clk}]\
+ -group [get_clocks {rtc_clk}]\
+ -group [get_clocks {usb_ref_clk}]\
+ -group [get_clocks {pll_ref_clk}]\
+ -group [get_clocks {pll_clk_0}]\
+ -group [get_clocks {usb_clk}]\
+ -group [get_clocks {uarts0_clk}]\
+ -group [get_clocks {uarts1_clk}]\
+ -group [get_clocks {uartm_clk}]\
+ -group [get_clocks {dbg_ref_clk}]\
+ -group [get_clocks {rtc_ref_clk}]\
+ -comment {Async Clock group}
+
+# clock <-> hk_serial_clk/load no paths
+# future note: CDC stuff
+# clock <-> hkspi_clk no paths with careful methods (clock is off)
+
+set_propagated_clock [all_clocks]
+
+## INPUT/OUTPUT DELAYS
+set input_delay_value 4
+set output_delay_value 4
+puts "\[INFO\]: Setting output delay to: $output_delay_value"
+puts "\[INFO\]: Setting input delay to: $input_delay_value"
+
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {gpio}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[0]}]
+
+#set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[1]}]
+
+set_input_delay $input_delay_value -clock [get_clocks {hkspi_clk}] -add_delay [get_ports {mprj_io[2]}]
+set_input_delay $input_delay_value -clock [get_clocks {hkspi_clk}] -add_delay [get_ports {mprj_io[3]}]
+
+#set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[4]}]
+
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[5]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[6]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[7]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[8]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[9]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[10]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[11]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[12]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[13]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[14]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[15]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[16]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[17]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[18]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[19]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[20]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[21]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[22]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[23]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[24]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[25]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[26]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[27]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[28]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[29]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[30]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[31]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[32]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[33]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[34]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[35]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[36]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[37]}]
+
+set_output_delay $output_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {flash_csb}]
+set_output_delay $output_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {flash_clk}]
+set_output_delay $output_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {flash_io0}]
+set_output_delay $output_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {flash_io1}]
+
+# set_output_delay $output_delay_value -clock [get_clocks {hkspi_clk}] -add_delay [get_ports {mprj_io[1]}]
+
+set_max_fanout 12 [current_design]
+# synthesis max fanout should be less than 12 (7 maybe)
+
+## Set system monitoring mux select to zero so that the clock/user_clk monitoring is disabled
+set_case_analysis 0 [get_pins housekeeping/_3936_/S]
+set_case_analysis 0 [get_pins housekeeping/_3937_/S]
+
+# Add case analysis for pads DM[2]==1'b1 & DM[1]==1'b1 & DM[0]==1'b0 to be outputs
+
+set_case_analysis 1 [get_pins padframe/*_pad*/DM[2]]
+set_case_analysis 1 [get_pins padframe/*_pad*/DM[1]]
+set_case_analysis 0 [get_pins padframe/*_pad*/DM[0]]
+set_case_analysis 0 [get_pins padframe/*_pad*/SLOW]
+set_case_analysis 0 [get_pins padframe/*_pad*/ANALOG_EN]
+
+# the following pads are set as inputs
+set_case_analysis 0 [get_pins padframe/*area1_io_pad[4]/DM[2]]
+set_case_analysis 0 [get_pins padframe/*area1_io_pad[4]/DM[1]]
+set_case_analysis 1 [get_pins padframe/*area1_io_pad[4]/DM[0]]
+
+set_case_analysis 0 [get_pins padframe/*area1_io_pad[2]/DM[2]]
+set_case_analysis 0 [get_pins padframe/*area1_io_pad[2]/DM[1]]
+set_case_analysis 1 [get_pins padframe/*area1_io_pad[2]/DM[0]]
+
+
+set_case_analysis 0 [get_pins padframe/clock_pad/DM[2]]
+set_case_analysis 0 [get_pins padframe/clock_pad/DM[1]]
+set_case_analysis 1 [get_pins padframe/clock_pad/DM[0]]
+
+#################################################################
+## User Case analysis
+#################################################################
+
+set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[3]}]
+set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[2]}]
+set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[1]}]
+set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[0]}]
+
+set_case_analysis 0 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[3]}]
+set_case_analysis 1 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[2]}]
+set_case_analysis 0 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[1]}]
+set_case_analysis 0 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[0]}]
+
+set_case_analysis 1 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[3]}]
+set_case_analysis 1 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[2]}]
+set_case_analysis 0 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[1]}]
+set_case_analysis 1 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[0]}]
+
+set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[3]}]
+set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[2]}]
+set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[1]}]
+set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[0]}]
+
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[3]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[2]}]
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[0]}]
+
+set_case_analysis 1 [get_pins {mprj/u_wb_host/cfg_cska_wh[3]}]
+set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[2]}]
+set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[1]}]
+set_case_analysis 1 [get_pins {mprj/u_wb_host/cfg_cska_wh[0]}]
+
+set_case_analysis 0 [get_pins {mprj/u_intercon/cfg_cska_wi[3]}]
+set_case_analysis 0 [get_pins {mprj/u_intercon/cfg_cska_wi[2]}]
+set_case_analysis 1 [get_pins {mprj/u_intercon/cfg_cska_wi[0]}]
+set_case_analysis 1 [get_pins {mprj/u_intercon/cfg_cska_wi[1]}]
+
+# clock skew cntrl-2
+
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_3/cfg_ccska[3]}]
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.i_core_top_3/cfg_ccska[2]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_3/cfg_ccska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_3/cfg_ccska[0]}]
+
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_2/cfg_ccska[3]}]
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.i_core_top_2/cfg_ccska[2]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_2/cfg_ccska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_2/cfg_ccska[0]}]
+
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_1/cfg_ccska[3]}]
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.i_core_top_1/cfg_ccska[2]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_1/cfg_ccska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_1/cfg_ccska[0]}]
+
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_0/cfg_ccska[3]}]
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.i_core_top_0/cfg_ccska[2]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_0/cfg_ccska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_0/cfg_ccska[0]}]
+
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[3]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[2]}]
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[1]}]
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[0]}]
+
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[3]}]
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[2]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[1]}]
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[0]}]
+
+#Keept the SRAM clock driving edge at pos edge
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_sram_lphase[0]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_sram_lphase[1]}]
+
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_sram_lphase[0]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_sram_lphase[1]}]
+
+set_case_analysis 1 [get_pins {mprj/u_aes/cfg_cska[3]}]
+set_case_analysis 0 [get_pins {mprj/u_aes/cfg_cska[2]}]
+set_case_analysis 0 [get_pins {mprj/u_aes/cfg_cska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_aes/cfg_cska[0]}]
+
+set_case_analysis 1 [get_pins {mprj/u_fpu/cfg_cska[3]}]
+set_case_analysis 0 [get_pins {mprj/u_fpu/cfg_cska[2]}]
+set_case_analysis 0 [get_pins {mprj/u_fpu/cfg_cska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_fpu/cfg_cska[0]}]
+
+## FALSE PATHS (ASYNCHRONOUS INPUTS)
+set_false_path -from [get_ports {resetb}]
+
+## Async USB/I2C Interrupt, Double Sync added inside glbl block
+set_false_path -through [get_pins {mprj/u_pinmux/usb_intr}]
+set_false_path -through [get_pins {mprj/u_pinmux/i2cm_intr}]
+
+## UART RXD is async signal
+set_false_path -through [get_pins {mprj/u_wb_host/uartm_rxd}]
+
+##SPI Slave Interface Signal (SCLK/SSN) are double sync with wb_clk
+set_false_path -through [get_pins {mprj/u_wb_host/sclk}]
+set_false_path -through [get_pins {mprj/u_wb_host/ssn}]
+## SDIN sampled on negedge SCLK
+set_false_path -through [get_pins {mprj/u_wb_host/sdin}]
+
+
+# set_false_path -from [get_ports mprj_io[*]] -through [get_pins housekeeping/mgmt_gpio_in[*]]
+# reset_path -from [get_ports mprj_io[4]]
+# reset_path -from [get_ports mprj_io[2]]
+#reset_path is not supported in PT read_sdc ^
+
+set_false_path -from [get_ports mprj_io[0]] -through [get_pins housekeeping/mgmt_gpio_in[0]]
+set_false_path -from [get_ports mprj_io[1]] -through [get_pins housekeeping/mgmt_gpio_in[1]]
+set_false_path -from [get_ports mprj_io[3]] -through [get_pins housekeeping/mgmt_gpio_in[3]]
+set_false_path -from [get_ports mprj_io[5]] -through [get_pins housekeeping/mgmt_gpio_in[5]]
+set_false_path -from [get_ports mprj_io[6]] -through [get_pins housekeeping/mgmt_gpio_in[6]]
+set_false_path -from [get_ports mprj_io[7]] -through [get_pins housekeeping/mgmt_gpio_in[7]]
+set_false_path -from [get_ports mprj_io[8]] -through [get_pins housekeeping/mgmt_gpio_in[8]]
+set_false_path -from [get_ports mprj_io[9]] -through [get_pins housekeeping/mgmt_gpio_in[9]]
+set_false_path -from [get_ports mprj_io[10]] -through [get_pins housekeeping/mgmt_gpio_in[10]]
+set_false_path -from [get_ports mprj_io[11]] -through [get_pins housekeeping/mgmt_gpio_in[11]]
+set_false_path -from [get_ports mprj_io[12]] -through [get_pins housekeeping/mgmt_gpio_in[12]]
+set_false_path -from [get_ports mprj_io[13]] -through [get_pins housekeeping/mgmt_gpio_in[13]]
+set_false_path -from [get_ports mprj_io[14]] -through [get_pins housekeeping/mgmt_gpio_in[14]]
+set_false_path -from [get_ports mprj_io[15]] -through [get_pins housekeeping/mgmt_gpio_in[15]]
+set_false_path -from [get_ports mprj_io[16]] -through [get_pins housekeeping/mgmt_gpio_in[16]]
+set_false_path -from [get_ports mprj_io[17]] -through [get_pins housekeeping/mgmt_gpio_in[17]]
+set_false_path -from [get_ports mprj_io[18]] -through [get_pins housekeeping/mgmt_gpio_in[18]]
+set_false_path -from [get_ports mprj_io[19]] -through [get_pins housekeeping/mgmt_gpio_in[19]]
+set_false_path -from [get_ports mprj_io[20]] -through [get_pins housekeeping/mgmt_gpio_in[20]]
+set_false_path -from [get_ports mprj_io[21]] -through [get_pins housekeeping/mgmt_gpio_in[21]]
+set_false_path -from [get_ports mprj_io[22]] -through [get_pins housekeeping/mgmt_gpio_in[22]]
+set_false_path -from [get_ports mprj_io[23]] -through [get_pins housekeeping/mgmt_gpio_in[23]]
+set_false_path -from [get_ports mprj_io[24]] -through [get_pins housekeeping/mgmt_gpio_in[24]]
+set_false_path -from [get_ports mprj_io[25]] -through [get_pins housekeeping/mgmt_gpio_in[25]]
+set_false_path -from [get_ports mprj_io[26]] -through [get_pins housekeeping/mgmt_gpio_in[26]]
+set_false_path -from [get_ports mprj_io[27]] -through [get_pins housekeeping/mgmt_gpio_in[27]]
+set_false_path -from [get_ports mprj_io[28]] -through [get_pins housekeeping/mgmt_gpio_in[28]]
+set_false_path -from [get_ports mprj_io[29]] -through [get_pins housekeeping/mgmt_gpio_in[29]]
+set_false_path -from [get_ports mprj_io[30]] -through [get_pins housekeeping/mgmt_gpio_in[30]]
+set_false_path -from [get_ports mprj_io[31]] -through [get_pins housekeeping/mgmt_gpio_in[31]]
+set_false_path -from [get_ports mprj_io[32]] -through [get_pins housekeeping/mgmt_gpio_in[32]]
+set_false_path -from [get_ports mprj_io[33]] -through [get_pins housekeeping/mgmt_gpio_in[33]]
+set_false_path -from [get_ports mprj_io[34]] -through [get_pins housekeeping/mgmt_gpio_in[34]]
+set_false_path -from [get_ports mprj_io[35]] -through [get_pins housekeeping/mgmt_gpio_in[35]]
+set_false_path -from [get_ports mprj_io[36]] -through [get_pins housekeeping/mgmt_gpio_in[36]]
+set_false_path -from [get_ports mprj_io[37]] -through [get_pins housekeeping/mgmt_gpio_in[37]]
+
+set_false_path -from [get_ports mprj_io[*]] -through [get_pins housekeeping/mgmt_gpio_out[*]]
+set_false_path -from [get_ports mprj_io[*]] -through [get_pins housekeeping/mgmt_gpio_oeb[*]]
+set_false_path -from [get_ports gpio]
+
+# add loads for output ports (pads)
+set min_cap 5
+set max_cap 10
+puts "\[INFO\]: Cap load range: $min_cap : $max_cap"
+# set_load 10 [all_outputs]
+set_load -min $min_cap [all_outputs]
+set_load -max $max_cap [all_outputs]
+
+#add input transition for the inputs ports (pads)
+# set_input_transition 2 [all_inputs]
+#add exception for power pads as 2ns on them results in max_tran violations (false viol)
+# set_input_transition 2 [remove_from_collection [all_inputs] [get_ports v*]]
+# remove_from_collection is not supported in PT read_sdc ^
+# set_input_transition 2 [all_inputs]
+# set_input_transition 0 [get_ports v*]
+
+set min_in_tran 1
+set max_in_tran 4
+puts "\[INFO\]: Input transition range: $min_in_tran : $max_in_tran"
+set_input_transition -min $min_in_tran [all_inputs]
+set_input_transition -min 0 [get_ports v*]
+set_input_transition -max $max_in_tran [all_inputs]
+set_input_transition -max 0 [get_ports v*]
+
+# check ocv table (not provided) -- maybe try 8%
+set derate 0.0375
+puts "\[INFO\]: Setting derate factor to: [expr $derate * 100] %"
+set_timing_derate -early [expr 1-$derate]
+set_timing_derate -late [expr 1+$derate]
+
+# add max_tran constraint as the default max_tran of the ss hd SCL is 10 so the violations are not caught in ss corners
+# apply the constraint to hd cells at the ss corner only
+# if {$::env(PROC_CORNER) == "s"} {
+# set max_tran 1.5
+# set_max_transition $max_tran [get_pins -of_objects [get_cells -filter {ref_name=~sky130_fd_sc_hd*}]]
+# set_max_transition $max_tran [get_pins -of_objects [get_cells */* -filter {ref_name=~sky130_fd_sc_hd*}]]
+# set_max_transition $max_tran [get_pins -of_objects [get_cells */*/* -filter {ref_name=~sky130_fd_sc_hd*}]]
+# puts "\[INFO\]: Setting maximum transition of HD cells in slow process corner to: $max_tran"
+# }
+# -filter not supported in PT read_sdc ^
diff --git a/sdc/dg_pll.sdc b/sdc/dg_pll.sdc
new file mode 100644
index 0000000..d8bbcf5
--- /dev/null
+++ b/sdc/dg_pll.sdc
@@ -0,0 +1,61 @@
+###############################################################################
+# Created by write_sdc
+# Thu Nov 24 13:10:05 2022
+###############################################################################
+current_design dg_pll
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name pll_control_clock -period 6.6667 [get_pins {ringosc.ibufp01/Y}]
+set_clock_transition 0.1500 [get_clocks {pll_control_clock}]
+set_clock_uncertainty -setup 0.5000 pll_control_clock
+set_clock_uncertainty -hold 0.2500 pll_control_clock
+set_propagated_clock [get_clocks {pll_control_clock}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {clockp[1]}]
+set_load -pin_load 0.0334 [get_ports {clockp[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dco}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {enable}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {osc}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {resetb}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[0]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_transition 1.0000 [current_design]
+set_max_capacitance 0.2000 [current_design]
+set_max_fanout 10.0000 [current_design]
diff --git a/sdc/digital_pll.sdc b/sdc/digital_pll.sdc
new file mode 100644
index 0000000..81a7abe
--- /dev/null
+++ b/sdc/digital_pll.sdc
@@ -0,0 +1,97 @@
+###############################################################################
+# Created by write_sdc
+# Sun Sep 18 14:49:47 2022
+###############################################################################
+current_design digital_pll
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name pll_control_clock -period 6.6667 [get_pins {ringosc.ibufp01/Y}]
+set_clock_transition 0.1500 [get_clocks {pll_control_clock}]
+set_clock_uncertainty 0.2500 pll_control_clock
+set_propagated_clock [get_clocks {pll_control_clock}]
+set_input_delay 2.0000 -add_delay [get_ports {dco}]
+set_input_delay 2.0000 -add_delay [get_ports {div[0]}]
+set_input_delay 2.0000 -add_delay [get_ports {div[1]}]
+set_input_delay 2.0000 -add_delay [get_ports {div[2]}]
+set_input_delay 2.0000 -add_delay [get_ports {div[3]}]
+set_input_delay 2.0000 -add_delay [get_ports {div[4]}]
+set_input_delay 2.0000 -add_delay [get_ports {enable}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[0]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[10]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[11]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[12]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[13]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[14]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[15]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[16]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[17]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[18]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[19]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[1]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[20]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[21]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[22]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[23]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[24]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[25]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[2]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[3]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[4]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[5]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[6]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[7]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[8]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[9]}]
+set_input_delay 2.0000 -add_delay [get_ports {osc}]
+set_input_delay 2.0000 -add_delay [get_ports {resetb}]
+set_output_delay 2.0000 -add_delay [get_ports {clockp[0]}]
+set_output_delay 2.0000 -add_delay [get_ports {clockp[1]}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {clockp[1]}]
+set_load -pin_load 0.0334 [get_ports {clockp[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dco}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {enable}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {osc}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {resetb}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[0]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_transition 1.0000 [current_design]
+set_max_capacitance 0.2000 [current_design]
+set_max_fanout 10.0000 [current_design]
diff --git a/sdc/pinmux.sdc b/sdc/pinmux.sdc
new file mode 100644
index 0000000..9bd9f68
--- /dev/null
+++ b/sdc/pinmux.sdc
@@ -0,0 +1,521 @@
+###############################################################################
+# Created by write_sdc
+# Sun Jul 31 10:27:51 2022
+###############################################################################
+current_design pinmux
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name mclk -period 10.0000 [get_ports {mclk}]
+set_clock_transition 0.1500 [get_clocks {mclk}]
+set_clock_uncertainty 0.2500 mclk
+set_propagated_clock [get_clocks {mclk}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {h_reset_n}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[0]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[0]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[1]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[1]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[2]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[2]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[3]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[3]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[4]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[4]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[5]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[5]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[6]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[6]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[7]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[7]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[0]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[0]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[1]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[1]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[2]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[2]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[3]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[3]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_cs}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_cs}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[0]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[0]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[10]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[10]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[11]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[11]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[12]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[12]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[13]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[13]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[14]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[14]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[15]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[15]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[16]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[16]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[17]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[17]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[18]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[18]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[19]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[19]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[1]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[1]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[20]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[20]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[21]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[21]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[22]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[22]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[23]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[23]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[24]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[24]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[25]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[25]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[26]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[26]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[27]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[27]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[28]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[28]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[29]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[29]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[2]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[2]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[30]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[30]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[31]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[31]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[3]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[3]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[4]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[4]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[5]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[5]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[6]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[6]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[7]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[7]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[8]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[8]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[9]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[9]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wr}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wr}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {qspim_rst_n}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {qspim_rst_n}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_ack}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_ack}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[0]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[0]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[10]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[10]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[11]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[11]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[12]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[12]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[13]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[13]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[14]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[14]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[15]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[15]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[16]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[16]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[17]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[17]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[18]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[18]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[19]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[19]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[1]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[1]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[20]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[20]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[21]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[21]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[22]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[22]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[23]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[23]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[24]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[24]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[25]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[25]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[26]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[26]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[27]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[27]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[28]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[28]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[29]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[29]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[2]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[2]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[30]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[30]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[31]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[31]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[3]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[3]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[4]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[4]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[5]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[5]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[6]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[6]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[7]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[7]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[8]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[8]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[9]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[9]}]
+set_max_delay\
+ -from [get_ports {wbd_clk_int}] 3.5000
+set_max_delay\
+ -from [get_ports {wbd_clk_int}]\
+ -to [get_ports {wbd_clk_pinmux}] 3.5000
+set_max_delay\
+ -to [get_ports {wbd_clk_pinmux}] 2.0000
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {cpu_intf_rst_n}]
+set_load -pin_load 0.0334 [get_ports {i2cm_clk_i}]
+set_load -pin_load 0.0334 [get_ports {i2cm_data_i}]
+set_load -pin_load 0.0334 [get_ports {i2cm_rst_n}]
+set_load -pin_load 0.0334 [get_ports {pulse1m_mclk}]
+set_load -pin_load 0.0334 [get_ports {qspim_rst_n}]
+set_load -pin_load 0.0334 [get_ports {reg_ack}]
+set_load -pin_load 0.0334 [get_ports {soft_irq}]
+set_load -pin_load 0.0334 [get_ports {spim_mosi}]
+set_load -pin_load 0.0334 [get_ports {spis_mosi}]
+set_load -pin_load 0.0334 [get_ports {spis_sck}]
+set_load -pin_load 0.0334 [get_ports {spis_ssn}]
+set_load -pin_load 0.0334 [get_ports {sspim_rst_n}]
+set_load -pin_load 0.0334 [get_ports {uartm_rxd}]
+set_load -pin_load 0.0334 [get_ports {usb_dn_i}]
+set_load -pin_load 0.0334 [get_ports {usb_dp_i}]
+set_load -pin_load 0.0334 [get_ports {usb_rst_n}]
+set_load -pin_load 0.0334 [get_ports {wbd_clk_pinmux}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[15]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[14]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[13]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[12]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[11]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[10]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[9]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[8]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[0]}]
+set_load -pin_load 0.0334 [get_ports {cpu_core_rst_n[3]}]
+set_load -pin_load 0.0334 [get_ports {cpu_core_rst_n[2]}]
+set_load -pin_load 0.0334 [get_ports {cpu_core_rst_n[1]}]
+set_load -pin_load 0.0334 [get_ports {cpu_core_rst_n[0]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[37]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[36]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[35]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[34]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[33]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[32]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[31]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[30]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[29]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[28]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[27]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[26]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[25]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[24]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[23]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[22]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[21]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[20]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[19]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[18]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[17]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[16]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[15]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[14]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[13]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[12]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[11]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[10]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[9]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[8]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[7]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[6]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[5]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[4]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[3]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[2]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[1]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[0]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[37]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[36]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[35]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[34]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[33]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[32]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[31]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[30]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[29]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[28]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[27]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[26]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[25]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[24]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[23]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[22]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[21]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[20]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[19]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[18]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[17]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[16]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[15]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[14]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[13]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[12]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[11]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[10]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[9]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[8]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[7]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[6]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[5]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[4]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[3]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[2]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[1]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[0]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[15]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[14]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[13]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[12]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[11]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[10]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[9]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[8]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[7]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[6]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[5]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[4]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[3]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[2]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[1]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[0]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[31]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[30]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[29]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[28]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[27]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[26]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[25]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[24]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[23]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[22]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[21]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[20]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[19]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[18]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[17]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[16]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[15]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[14]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[13]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[12]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[11]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[10]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[9]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[8]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[7]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[6]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[5]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[4]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[3]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[2]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[1]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[0]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[31]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[30]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[29]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[28]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[27]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[26]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[25]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[24]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[23]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[22]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[21]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[20]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[19]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[18]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[17]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[16]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[15]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[14]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[13]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[12]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[11]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[10]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[9]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[8]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[7]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[6]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[5]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[4]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[3]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[2]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[1]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[0]}]
+set_load -pin_load 0.0334 [get_ports {sflash_di[3]}]
+set_load -pin_load 0.0334 [get_ports {sflash_di[2]}]
+set_load -pin_load 0.0334 [get_ports {sflash_di[1]}]
+set_load -pin_load 0.0334 [get_ports {sflash_di[0]}]
+set_load -pin_load 0.0334 [get_ports {uart_rst_n[1]}]
+set_load -pin_load 0.0334 [get_ports {uart_rst_n[0]}]
+set_load -pin_load 0.0334 [get_ports {uart_rxd[1]}]
+set_load -pin_load 0.0334 [get_ports {uart_rxd[0]}]
+set_load -pin_load 0.0334 [get_ports {user_irq[2]}]
+set_load -pin_load 0.0334 [get_ports {user_irq[1]}]
+set_load -pin_load 0.0334 [get_ports {user_irq[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_clk_mon}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {h_reset_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i2cm_clk_o}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i2cm_clk_oen}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i2cm_data_o}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i2cm_data_oen}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i2cm_intr}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mclk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_cs}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wr}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_sck}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spim_miso}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spim_sck}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spis_miso}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uartm_txd}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usb_dn_o}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usb_dp_o}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usb_intr}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usb_oen}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_pinmux[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_pinmux[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_pinmux[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_pinmux[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_do[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_do[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_do[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_do[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_oen[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_oen[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_oen[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_oen[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_ss[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_ss[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_ss[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_ss[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spim_ssn[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spim_ssn[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spim_ssn[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spim_ssn[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uart_txd[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uart_txd[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_pinmux[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_pinmux[1]}]
+set_case_analysis 0 [get_ports {cfg_cska_pinmux[2]}]
+set_case_analysis 0 [get_ports {cfg_cska_pinmux[3]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
diff --git a/sdc/pinmux_top.sdc b/sdc/pinmux_top.sdc
new file mode 100644
index 0000000..897365d
--- /dev/null
+++ b/sdc/pinmux_top.sdc
@@ -0,0 +1,729 @@
+###############################################################################
+# Created by write_sdc
+# Wed Nov 30 08:04:48 2022
+###############################################################################
+current_design pinmux_top
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name mclk -period 10.0000 [get_ports {mclk}]
+set_clock_transition 0.1500 [get_clocks {mclk}]
+set_clock_uncertainty -setup 0.5000 mclk
+set_clock_uncertainty -hold 0.2500 mclk
+set_propagated_clock [get_clocks {mclk}]
+create_clock -name user_clock1 -period 10.0000 [get_ports {user_clock1}]
+set_clock_transition 0.1500 [get_clocks {user_clock1}]
+set_clock_uncertainty -setup 0.5000 user_clock1
+set_clock_uncertainty -hold 0.2500 user_clock1
+set_propagated_clock [get_clocks {user_clock1}]
+create_clock -name user_clock2 -period 10.0000 [get_ports {user_clock2}]
+set_clock_transition 0.1500 [get_clocks {user_clock2}]
+set_clock_uncertainty -setup 0.5000 user_clock2
+set_clock_uncertainty -hold 0.2500 user_clock2
+set_propagated_clock [get_clocks {user_clock2}]
+create_clock -name int_pll_clock -period 5.0000
+set_clock_uncertainty -setup 0.5000 int_pll_clock
+set_clock_uncertainty -hold 0.2500 int_pll_clock
+create_clock -name rtc_ref_clk -period 50.0000 [get_pins {u_glbl_reg.u_rtc_ref_clkbuf.u_buf/X}]
+set_clock_transition 0.1500 [get_clocks {rtc_ref_clk}]
+set_clock_uncertainty -setup 0.5000 rtc_ref_clk
+set_clock_uncertainty -hold 0.2500 rtc_ref_clk
+set_propagated_clock [get_clocks {rtc_ref_clk}]
+create_clock -name rtc_clk -period 50.0000 [get_pins {u_glbl_reg.u_clkbuf_rtc.u_buf/X}]
+set_clock_transition 0.1500 [get_clocks {rtc_clk}]
+set_clock_uncertainty -setup 0.5000 rtc_clk
+set_clock_uncertainty -hold 0.2500 rtc_clk
+set_propagated_clock [get_clocks {rtc_clk}]
+create_clock -name usb_ref_clk -period 5.0000 [get_pins {u_glbl_reg.u_usb_ref_clkbuf.u_buf/X}]
+set_clock_transition 0.1500 [get_clocks {usb_ref_clk}]
+set_clock_uncertainty -setup 0.5000 usb_ref_clk
+set_clock_uncertainty -hold 0.2500 usb_ref_clk
+set_propagated_clock [get_clocks {usb_ref_clk}]
+create_clock -name dbg_ref_clk -period 10.0000 [get_pins {u_glbl_reg.u_clkbuf_dbg_ref.u_buf/X}]
+set_clock_transition 0.1500 [get_clocks {dbg_ref_clk}]
+set_clock_uncertainty -setup 0.5000 dbg_ref_clk
+set_clock_uncertainty -hold 0.2500 dbg_ref_clk
+set_propagated_clock [get_clocks {dbg_ref_clk}]
+set_clock_groups -name clock_group -logically_exclusive \
+ -group [get_clocks {dbg_ref_clk}]\
+ -group [get_clocks {int_pll_clock}]\
+ -group [get_clocks {mclk}]\
+ -group [get_clocks {rtc_clk}]\
+ -group [get_clocks {rtc_ref_clk}]\
+ -group [get_clocks {usb_ref_clk}]\
+ -group [get_clocks {user_clock1}]\
+ -group [get_clocks {user_clock2}] -comment {Async Clock group}
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[0]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[0]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[1]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[1]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[2]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[2]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[3]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[3]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[4]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[4]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[5]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[5]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[6]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[6]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[7]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[7]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[8]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[8]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[9]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[9]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[0]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[0]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[1]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[1]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[2]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[2]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[3]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[3]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_cs}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_cs}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[0]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[0]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[10]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[10]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[11]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[11]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[12]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[12]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[13]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[13]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[14]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[14]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[15]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[15]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[16]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[16]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[17]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[17]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[18]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[18]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[19]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[19]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[1]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[1]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[20]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[20]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[21]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[21]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[22]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[22]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[23]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[23]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[24]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[24]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[25]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[25]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[26]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[26]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[27]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[27]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[28]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[28]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[29]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[29]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[2]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[2]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[30]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[30]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[31]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[31]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[3]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[3]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[4]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[4]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[5]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[5]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[6]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[6]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[7]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[7]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[8]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[8]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[9]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[9]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wr}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wr}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {qspim_rst_n}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {qspim_rst_n}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_ack}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_ack}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[0]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[0]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[10]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[10]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[11]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[11]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[12]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[12]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[13]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[13]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[14]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[14]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[15]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[15]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[16]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[16]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[17]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[17]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[18]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[18]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[19]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[19]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[1]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[1]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[20]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[20]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[21]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[21]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[22]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[22]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[23]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[23]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[24]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[24]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[25]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[25]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[26]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[26]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[27]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[27]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[28]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[28]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[29]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[29]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[2]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[2]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[30]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[30]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[31]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[31]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[3]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[3]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[4]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[4]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[5]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[5]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[6]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[6]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[7]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[7]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[8]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[8]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[9]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[9]}]
+set_max_delay\
+ -from [get_ports {wbd_clk_int}] 3.5000
+set_max_delay\
+ -from [get_ports {wbd_clk_int}]\
+ -to [get_ports {wbd_clk_pinmux}] 3.5000
+set_max_delay\
+ -to [get_ports {wbd_clk_pinmux}] 2.0000
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {cfg_dco_mode}]
+set_load -pin_load 0.0334 [get_ports {cfg_pll_enb}]
+set_load -pin_load 0.0334 [get_ports {cpu_intf_rst_n}]
+set_load -pin_load 0.0334 [get_ports {i2cm_clk_i}]
+set_load -pin_load 0.0334 [get_ports {i2cm_data_i}]
+set_load -pin_load 0.0334 [get_ports {i2cm_rst_n}]
+set_load -pin_load 0.0334 [get_ports {pll_ref_clk}]
+set_load -pin_load 0.0334 [get_ports {pulse1m_mclk}]
+set_load -pin_load 0.0334 [get_ports {qspim_rst_n}]
+set_load -pin_load 0.0334 [get_ports {reg_ack}]
+set_load -pin_load 0.0334 [get_ports {rtc_clk}]
+set_load -pin_load 0.0334 [get_ports {soft_irq}]
+set_load -pin_load 0.0334 [get_ports {spim_mosi}]
+set_load -pin_load 0.0334 [get_ports {spis_mosi}]
+set_load -pin_load 0.0334 [get_ports {spis_sck}]
+set_load -pin_load 0.0334 [get_ports {spis_ssn}]
+set_load -pin_load 0.0334 [get_ports {sspim_rst_n}]
+set_load -pin_load 0.0334 [get_ports {uartm_rxd}]
+set_load -pin_load 0.0334 [get_ports {usb_clk}]
+set_load -pin_load 0.0334 [get_ports {usb_dn_i}]
+set_load -pin_load 0.0334 [get_ports {usb_dp_i}]
+set_load -pin_load 0.0334 [get_ports {usb_rst_n}]
+set_load -pin_load 0.0334 [get_ports {wbd_clk_pinmux}]
+set_load -pin_load 0.0334 [get_ports {xtal_clk}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[25]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[24]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[23]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[22]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[21]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[20]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[19]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[18]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[17]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[16]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[15]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[14]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[13]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[12]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[11]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[10]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[9]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[8]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_pll_fed_div[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_pll_fed_div[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_pll_fed_div[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_pll_fed_div[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_pll_fed_div[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[15]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[14]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[13]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[12]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[11]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[10]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[9]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[8]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[0]}]
+set_load -pin_load 0.0334 [get_ports {cpu_core_rst_n[3]}]
+set_load -pin_load 0.0334 [get_ports {cpu_core_rst_n[2]}]
+set_load -pin_load 0.0334 [get_ports {cpu_core_rst_n[1]}]
+set_load -pin_load 0.0334 [get_ports {cpu_core_rst_n[0]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[37]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[36]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[35]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[34]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[33]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[32]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[31]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[30]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[29]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[28]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[27]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[26]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[25]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[24]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[23]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[22]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[21]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[20]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[19]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[18]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[17]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[16]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[15]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[14]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[13]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[12]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[11]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[10]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[9]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[8]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[7]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[6]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[5]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[4]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[3]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[2]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[1]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[0]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[37]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[36]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[35]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[34]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[33]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[32]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[31]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[30]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[29]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[28]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[27]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[26]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[25]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[24]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[23]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[22]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[21]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[20]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[19]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[18]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[17]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[16]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[15]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[14]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[13]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[12]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[11]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[10]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[9]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[8]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[7]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[6]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[5]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[4]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[3]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[2]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[1]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[0]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[31]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[30]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[29]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[28]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[27]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[26]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[25]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[24]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[23]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[22]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[21]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[20]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[19]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[18]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[17]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[16]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[15]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[14]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[13]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[12]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[11]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[10]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[9]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[8]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[7]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[6]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[5]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[4]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[3]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[2]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[1]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[0]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[31]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[30]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[29]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[28]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[27]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[26]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[25]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[24]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[23]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[22]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[21]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[20]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[19]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[18]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[17]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[16]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[15]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[14]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[13]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[12]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[11]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[10]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[9]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[8]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[7]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[6]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[5]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[4]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[3]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[2]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[1]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[0]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[31]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[30]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[29]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[28]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[27]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[26]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[25]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[24]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[23]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[22]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[21]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[20]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[19]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[18]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[17]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[16]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[15]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[14]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[13]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[12]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[11]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[10]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[9]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[8]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[7]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[6]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[5]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[4]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[3]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[2]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[1]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[0]}]
+set_load -pin_load 0.0334 [get_ports {sflash_di[3]}]
+set_load -pin_load 0.0334 [get_ports {sflash_di[2]}]
+set_load -pin_load 0.0334 [get_ports {sflash_di[1]}]
+set_load -pin_load 0.0334 [get_ports {sflash_di[0]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[31]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[30]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[29]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[28]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[27]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[26]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[25]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[24]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[23]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[22]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[21]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[20]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[19]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[18]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[17]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[16]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[15]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[14]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[13]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[12]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[11]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[10]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[9]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[8]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[7]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[6]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[5]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[4]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[3]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[2]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[1]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[0]}]
+set_load -pin_load 0.0334 [get_ports {strap_uartm[1]}]
+set_load -pin_load 0.0334 [get_ports {strap_uartm[0]}]
+set_load -pin_load 0.0334 [get_ports {uart_rst_n[1]}]
+set_load -pin_load 0.0334 [get_ports {uart_rst_n[0]}]
+set_load -pin_load 0.0334 [get_ports {uart_rxd[1]}]
+set_load -pin_load 0.0334 [get_ports {uart_rxd[0]}]
+set_load -pin_load 0.0334 [get_ports {user_irq[2]}]
+set_load -pin_load 0.0334 [get_ports {user_irq[1]}]
+set_load -pin_load 0.0334 [get_ports {user_irq[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_strap_pad_ctrl}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cpu_clk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {e_reset_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i2cm_clk_o}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i2cm_clk_oen}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i2cm_data_o}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i2cm_data_oen}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i2cm_intr}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {int_pll_clock}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mclk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {p_reset_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_cs}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wr}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s_reset_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_sck}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spim_miso}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spim_sck}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spis_miso}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uartm_txd}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usb_dn_o}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usb_dp_o}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usb_intr}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usb_oen}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {user_clock1}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {user_clock2}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_pinmux[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_pinmux[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_pinmux[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_pinmux[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_do[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_do[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_do[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_do[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_oen[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_oen[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_oen[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_oen[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_ss[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_ss[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_ss[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_ss[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spim_ssn[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spim_ssn[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spim_ssn[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spim_ssn[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uart_txd[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uart_txd[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_pinmux[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_pinmux[1]}]
+set_case_analysis 0 [get_ports {cfg_cska_pinmux[2]}]
+set_case_analysis 0 [get_ports {cfg_cska_pinmux[3]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_transition 1.0000 [current_design]
+set_max_capacitance 0.2000 [current_design]
+set_max_fanout 10.0000 [current_design]
diff --git a/sdc/qspim_top.sdc b/sdc/qspim_top.sdc
new file mode 100644
index 0000000..fccd211
--- /dev/null
+++ b/sdc/qspim_top.sdc
@@ -0,0 +1,532 @@
+###############################################################################
+# Created by write_sdc
+# Mon Nov 28 03:20:00 2022
+###############################################################################
+current_design qspim_top
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name mclk -period 10.0000 [get_ports {mclk}]
+set_clock_transition 0.1500 [get_clocks {mclk}]
+set_clock_uncertainty -setup 0.5000 mclk
+set_clock_uncertainty -hold 0.2500 mclk
+set_propagated_clock [get_clocks {mclk}]
+create_generated_clock -name spiclk -add -source [get_ports {mclk}] -master_clock [get_clocks {mclk}] -divide_by 2 -comment {SPI Clock Out} [get_ports {spi_clk}]
+set_clock_transition 0.1500 [get_clocks {spiclk}]
+set_clock_uncertainty -setup 0.5000 spiclk
+set_clock_uncertainty -hold 0.2500 spiclk
+set_propagated_clock [get_clocks {spiclk}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {rst_n}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {rst_n}]
+set_input_delay 0.0000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdi[0]}]
+set_input_delay 5.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdi[0]}]
+set_input_delay 0.0000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdi[1]}]
+set_input_delay 5.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdi[1]}]
+set_input_delay 0.0000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdi[2]}]
+set_input_delay 5.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdi[2]}]
+set_input_delay 0.0000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdi[3]}]
+set_input_delay 5.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdi[3]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[0]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[0]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[10]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[10]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[11]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[11]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[12]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[12]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[13]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[13]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[14]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[14]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[15]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[15]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[16]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[16]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[17]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[17]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[18]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[18]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[19]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[19]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[1]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[1]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[20]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[20]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[21]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[21]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[22]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[22]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[23]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[23]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[24]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[24]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[25]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[25]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[26]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[26]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[27]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[27]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[28]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[28]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[29]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[29]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[2]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[2]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[30]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[30]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[31]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[31]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[3]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[3]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[4]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[4]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[5]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[5]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[6]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[6]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[7]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[7]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[8]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[8]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[9]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[9]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[0]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[0]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[10]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[10]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[11]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[11]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[12]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[12]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[13]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[13]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[14]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[14]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[15]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[15]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[16]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[16]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[17]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[17]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[18]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[18]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[19]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[19]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[1]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[1]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[20]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[20]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[21]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[21]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[22]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[22]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[23]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[23]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[24]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[24]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[25]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[25]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[26]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[26]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[27]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[27]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[28]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[28]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[29]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[29]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[2]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[2]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[30]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[30]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[31]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[31]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[3]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[3]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[4]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[4]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[5]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[5]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[6]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[6]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[7]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[7]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[8]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[8]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[9]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[9]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_sel_i[0]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_sel_i[0]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_sel_i[1]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_sel_i[1]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_sel_i[2]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_sel_i[2]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_sel_i[3]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_sel_i[3]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_stb_i}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_stb_i}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_we_i}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_we_i}]
+set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_csn[0]}]
+set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_csn[0]}]
+set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_csn[1]}]
+set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_csn[1]}]
+set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_csn[2]}]
+set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_csn[2]}]
+set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_csn[3]}]
+set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_csn[3]}]
+set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_oen[0]}]
+set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_oen[0]}]
+set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_oen[1]}]
+set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_oen[1]}]
+set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_oen[2]}]
+set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_oen[2]}]
+set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_oen[3]}]
+set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_oen[3]}]
+set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdo[0]}]
+set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdo[0]}]
+set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdo[1]}]
+set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdo[1]}]
+set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdo[2]}]
+set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdo[2]}]
+set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdo[3]}]
+set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdo[3]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_ack_o}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_ack_o}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[0]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[0]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[10]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[10]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[11]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[11]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[12]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[12]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[13]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[13]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[14]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[14]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[15]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[15]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[16]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[16]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[17]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[17]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[18]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[18]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[19]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[19]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[1]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[1]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[20]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[20]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[21]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[21]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[22]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[22]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[23]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[23]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[24]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[24]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[25]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[25]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[26]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[26]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[27]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[27]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[28]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[28]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[29]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[29]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[2]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[2]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[30]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[30]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[31]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[31]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[3]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[3]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[4]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[4]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[5]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[5]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[6]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[6]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[7]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[7]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[8]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[8]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[9]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[9]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_err_o}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_err_o}]
+set_max_delay\
+ -from [get_ports {wbd_clk_int}] 3.5000
+set_max_delay\
+ -from [get_ports {wbd_clk_int}]\
+ -to [get_ports {wbd_clk_spi}] 3.5000
+set_max_delay\
+ -to [get_ports {spi_debug[0]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[10]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[11]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[12]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[13]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[14]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[15]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[16]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[17]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[18]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[19]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[1]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[20]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[21]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[22]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[23]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[24]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[25]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[26]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[27]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[28]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[29]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[2]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[30]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[31]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[3]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[4]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[5]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[6]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[7]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[8]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[9]}] 10.0000
+set_max_delay\
+ -to [get_ports {wbd_clk_spi}] 2.0000
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {spi_clk}]
+set_load -pin_load 0.0334 [get_ports {wbd_ack_o}]
+set_load -pin_load 0.0334 [get_ports {wbd_clk_spi}]
+set_load -pin_load 0.0334 [get_ports {wbd_err_o}]
+set_load -pin_load 0.0334 [get_ports {wbd_lack_o}]
+set_load -pin_load 0.0334 [get_ports {spi_csn[3]}]
+set_load -pin_load 0.0334 [get_ports {spi_csn[2]}]
+set_load -pin_load 0.0334 [get_ports {spi_csn[1]}]
+set_load -pin_load 0.0334 [get_ports {spi_csn[0]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[31]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[30]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[29]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[28]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[27]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[26]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[25]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[24]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[23]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[22]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[21]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[20]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[19]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[18]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[17]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[16]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[15]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[14]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[13]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[12]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[11]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[10]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[9]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[8]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[7]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[6]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[5]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[4]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[3]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[2]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[1]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[0]}]
+set_load -pin_load 0.0334 [get_ports {spi_oen[3]}]
+set_load -pin_load 0.0334 [get_ports {spi_oen[2]}]
+set_load -pin_load 0.0334 [get_ports {spi_oen[1]}]
+set_load -pin_load 0.0334 [get_ports {spi_oen[0]}]
+set_load -pin_load 0.0334 [get_ports {spi_sdo[3]}]
+set_load -pin_load 0.0334 [get_ports {spi_sdo[2]}]
+set_load -pin_load 0.0334 [get_ports {spi_sdo[1]}]
+set_load -pin_load 0.0334 [get_ports {spi_sdo[0]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[31]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[30]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[29]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[28]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[27]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[26]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[25]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[24]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[23]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[22]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[21]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[20]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[19]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[18]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[17]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[16]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[15]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[14]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[13]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[12]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[11]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[10]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[9]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[8]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[7]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[6]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[5]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[4]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_init_bypass}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mclk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_pre_sram}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sram}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_bry_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_stb_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_we_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_sp_co[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_sp_co[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_sp_co[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_sp_co[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_spi[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_spi[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_spi[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_spi[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spi_sdi[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spi_sdi[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spi_sdi[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spi_sdi[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_flash[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_flash[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_bl_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_bl_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_bl_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_bl_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_bl_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_bl_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_bl_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_bl_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_bl_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_bl_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_sel_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_sel_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_sel_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_sel_i[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_sp_co[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_sp_co[1]}]
+set_case_analysis 0 [get_ports {cfg_cska_sp_co[2]}]
+set_case_analysis 0 [get_ports {cfg_cska_sp_co[3]}]
+set_case_analysis 0 [get_ports {cfg_cska_spi[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_spi[1]}]
+set_case_analysis 0 [get_ports {cfg_cska_spi[2]}]
+set_case_analysis 0 [get_ports {cfg_cska_spi[3]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_transition 1.0000 [current_design]
+set_max_capacitance 0.2000 [current_design]
+set_max_fanout 10.0000 [current_design]
diff --git a/sdc/uart_i2c_usb_spi_top.sdc b/sdc/uart_i2c_usb_spi_top.sdc
new file mode 100644
index 0000000..f1f6df4
--- /dev/null
+++ b/sdc/uart_i2c_usb_spi_top.sdc
@@ -0,0 +1,425 @@
+###############################################################################
+# Created by write_sdc
+# Mon Nov 28 03:22:27 2022
+###############################################################################
+current_design uart_i2c_usb_spi_top
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name app_clk -period 10.0000 [get_ports {app_clk}]
+set_clock_transition 0.1500 [get_clocks {app_clk}]
+set_clock_uncertainty -setup 0.5000 app_clk
+set_clock_uncertainty -hold 0.2500 app_clk
+set_propagated_clock [get_clocks {app_clk}]
+create_clock -name uart0_baud_clk -period 100.0000 [get_pins {u_uart0_core.u_lineclk_buf.genblk1.u_mux/X}]
+set_clock_transition 0.1500 [get_clocks {uart0_baud_clk}]
+set_clock_uncertainty -setup 0.5000 uart0_baud_clk
+set_clock_uncertainty -hold 0.2500 uart0_baud_clk
+set_propagated_clock [get_clocks {uart0_baud_clk}]
+create_clock -name uart1_baud_clk -period 100.0000 [get_pins {u_uart1_core.u_lineclk_buf.genblk1.u_mux/X}]
+set_clock_transition 0.1500 [get_clocks {uart1_baud_clk}]
+set_clock_uncertainty -setup 0.5000 uart1_baud_clk
+set_clock_uncertainty -hold 0.2500 uart1_baud_clk
+set_propagated_clock [get_clocks {uart1_baud_clk}]
+create_clock -name usb_clk -period 100.0000 [get_ports {usb_clk}]
+set_clock_transition 0.1500 [get_clocks {usb_clk}]
+set_clock_uncertainty -setup 0.5000 usb_clk
+set_clock_uncertainty -hold 0.2500 usb_clk
+set_propagated_clock [get_clocks {usb_clk}]
+set_clock_groups -name async_clock -asynchronous \
+ -group [get_clocks {app_clk}]\
+ -group [get_clocks {uart0_baud_clk}]\
+ -group [get_clocks {uart1_baud_clk}]\
+ -group [get_clocks {usb_clk}] -comment {Async Clock group}
+set_input_delay 1.5000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {i2c_rstn}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {i2c_rstn}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_addr[0]}]
+set_input_delay 5.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_addr[0]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_addr[1]}]
+set_input_delay 5.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_addr[1]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_addr[2]}]
+set_input_delay 5.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_addr[2]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_addr[3]}]
+set_input_delay 5.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_addr[3]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_addr[4]}]
+set_input_delay 5.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_addr[4]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_addr[5]}]
+set_input_delay 5.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_addr[5]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_addr[6]}]
+set_input_delay 5.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_addr[6]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_addr[7]}]
+set_input_delay 5.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_addr[7]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_addr[8]}]
+set_input_delay 5.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_addr[8]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_be[0]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_be[0]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_be[1]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_be[1]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_be[2]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_be[2]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_be[3]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_be[3]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_cs}]
+set_input_delay 5.7500 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_cs}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[0]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[0]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[10]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[10]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[11]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[11]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[12]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[12]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[13]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[13]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[14]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[14]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[15]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[15]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[16]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[16]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[17]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[17]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[18]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[18]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[19]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[19]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[1]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[1]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[20]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[20]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[21]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[21]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[22]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[22]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[23]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[23]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[24]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[24]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[25]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[25]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[26]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[26]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[27]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[27]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[28]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[28]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[29]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[29]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[2]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[2]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[30]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[30]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[31]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[31]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[3]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[3]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[4]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[4]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[5]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[5]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[6]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[6]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[7]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[7]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[8]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[8]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[9]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[9]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wr}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wr}]
+set_input_delay 1.5000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {uart_rstn[0]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {uart_rstn[0]}]
+set_input_delay 1.5000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {uart_rstn[1]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {uart_rstn[1]}]
+set_input_delay 1.5000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {usb_rstn}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {usb_rstn}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_ack}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[0]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[0]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[10]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[10]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[11]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[11]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[12]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[12]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[13]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[13]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[14]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[14]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[15]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[15]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[16]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[16]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[17]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[17]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[18]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[18]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[19]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[19]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[1]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[1]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[20]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[20]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[21]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[21]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[22]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[22]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[23]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[23]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[24]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[24]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[25]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[25]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[26]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[26]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[27]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[27]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[28]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[28]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[29]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[29]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[2]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[2]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[30]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[30]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[31]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[31]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[3]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[3]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[4]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[4]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[5]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[5]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[6]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[6]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[7]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[7]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[8]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[8]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[9]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[9]}]
+set_multicycle_path -hold\
+ -from [list [get_ports {reg_addr[0]}]\
+ [get_ports {reg_addr[1]}]\
+ [get_ports {reg_addr[2]}]\
+ [get_ports {reg_addr[3]}]\
+ [get_ports {reg_addr[4]}]\
+ [get_ports {reg_addr[5]}]\
+ [get_ports {reg_addr[6]}]\
+ [get_ports {reg_addr[7]}]\
+ [get_ports {reg_addr[8]}]]\
+ -to [list [get_ports {reg_ack}]\
+ [get_ports {reg_rdata[0]}]\
+ [get_ports {reg_rdata[10]}]\
+ [get_ports {reg_rdata[11]}]\
+ [get_ports {reg_rdata[12]}]\
+ [get_ports {reg_rdata[13]}]\
+ [get_ports {reg_rdata[14]}]\
+ [get_ports {reg_rdata[15]}]\
+ [get_ports {reg_rdata[16]}]\
+ [get_ports {reg_rdata[17]}]\
+ [get_ports {reg_rdata[18]}]\
+ [get_ports {reg_rdata[19]}]\
+ [get_ports {reg_rdata[1]}]\
+ [get_ports {reg_rdata[20]}]\
+ [get_ports {reg_rdata[21]}]\
+ [get_ports {reg_rdata[22]}]\
+ [get_ports {reg_rdata[23]}]\
+ [get_ports {reg_rdata[24]}]\
+ [get_ports {reg_rdata[25]}]\
+ [get_ports {reg_rdata[26]}]\
+ [get_ports {reg_rdata[27]}]\
+ [get_ports {reg_rdata[28]}]\
+ [get_ports {reg_rdata[29]}]\
+ [get_ports {reg_rdata[2]}]\
+ [get_ports {reg_rdata[30]}]\
+ [get_ports {reg_rdata[31]}]\
+ [get_ports {reg_rdata[3]}]\
+ [get_ports {reg_rdata[4]}]\
+ [get_ports {reg_rdata[5]}]\
+ [get_ports {reg_rdata[6]}]\
+ [get_ports {reg_rdata[7]}]\
+ [get_ports {reg_rdata[8]}]\
+ [get_ports {reg_rdata[9]}]] 1
+set_multicycle_path -setup\
+ -from [list [get_ports {reg_addr[0]}]\
+ [get_ports {reg_addr[1]}]\
+ [get_ports {reg_addr[2]}]\
+ [get_ports {reg_addr[3]}]\
+ [get_ports {reg_addr[4]}]\
+ [get_ports {reg_addr[5]}]\
+ [get_ports {reg_addr[6]}]\
+ [get_ports {reg_addr[7]}]\
+ [get_ports {reg_addr[8]}]]\
+ -to [list [get_ports {reg_ack}]\
+ [get_ports {reg_rdata[0]}]\
+ [get_ports {reg_rdata[10]}]\
+ [get_ports {reg_rdata[11]}]\
+ [get_ports {reg_rdata[12]}]\
+ [get_ports {reg_rdata[13]}]\
+ [get_ports {reg_rdata[14]}]\
+ [get_ports {reg_rdata[15]}]\
+ [get_ports {reg_rdata[16]}]\
+ [get_ports {reg_rdata[17]}]\
+ [get_ports {reg_rdata[18]}]\
+ [get_ports {reg_rdata[19]}]\
+ [get_ports {reg_rdata[1]}]\
+ [get_ports {reg_rdata[20]}]\
+ [get_ports {reg_rdata[21]}]\
+ [get_ports {reg_rdata[22]}]\
+ [get_ports {reg_rdata[23]}]\
+ [get_ports {reg_rdata[24]}]\
+ [get_ports {reg_rdata[25]}]\
+ [get_ports {reg_rdata[26]}]\
+ [get_ports {reg_rdata[27]}]\
+ [get_ports {reg_rdata[28]}]\
+ [get_ports {reg_rdata[29]}]\
+ [get_ports {reg_rdata[2]}]\
+ [get_ports {reg_rdata[30]}]\
+ [get_ports {reg_rdata[31]}]\
+ [get_ports {reg_rdata[3]}]\
+ [get_ports {reg_rdata[4]}]\
+ [get_ports {reg_rdata[5]}]\
+ [get_ports {reg_rdata[6]}]\
+ [get_ports {reg_rdata[7]}]\
+ [get_ports {reg_rdata[8]}]\
+ [get_ports {reg_rdata[9]}]] 2
+set_max_delay\
+ -from [get_ports {wbd_clk_int}] 5.0000
+set_max_delay\
+ -from [get_ports {wbd_clk_int}]\
+ -to [get_ports {wbd_clk_uart}] 5.0000
+set_max_delay\
+ -to [get_ports {wbd_clk_uart}] 5.0000
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {i2cm_intr_o}]
+set_load -pin_load 0.0334 [get_ports {reg_ack}]
+set_load -pin_load 0.0334 [get_ports {scl_pad_o}]
+set_load -pin_load 0.0334 [get_ports {scl_pad_oen_o}]
+set_load -pin_load 0.0334 [get_ports {sda_pad_o}]
+set_load -pin_load 0.0334 [get_ports {sda_padoen_o}]
+set_load -pin_load 0.0334 [get_ports {sspim_sck}]
+set_load -pin_load 0.0334 [get_ports {sspim_so}]
+set_load -pin_load 0.0334 [get_ports {usb_intr_o}]
+set_load -pin_load 0.0334 [get_ports {usb_out_dn}]
+set_load -pin_load 0.0334 [get_ports {usb_out_dp}]
+set_load -pin_load 0.0334 [get_ports {usb_out_tx_oen}]
+set_load -pin_load 0.0334 [get_ports {wbd_clk_uart}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[31]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[30]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[29]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[28]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[27]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[26]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[25]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[24]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[23]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[22]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[21]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[20]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[19]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[18]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[17]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[16]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[15]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[14]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[13]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[12]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[11]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[10]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[9]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[8]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[7]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[6]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[5]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[4]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[3]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[2]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[1]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[0]}]
+set_load -pin_load 0.0334 [get_ports {sspim_ssn[3]}]
+set_load -pin_load 0.0334 [get_ports {sspim_ssn[2]}]
+set_load -pin_load 0.0334 [get_ports {sspim_ssn[1]}]
+set_load -pin_load 0.0334 [get_ports {sspim_ssn[0]}]
+set_load -pin_load 0.0334 [get_ports {uart_txd[1]}]
+set_load -pin_load 0.0334 [get_ports {uart_txd[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {app_clk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i2c_rstn}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_cs}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wr}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {scl_pad_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sda_pad_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spi_rstn}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sspim_si}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usb_clk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usb_in_dn}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usb_in_dp}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usb_rstn}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_uart[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_uart[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_uart[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_uart[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uart_rstn[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uart_rstn[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uart_rxd[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uart_rxd[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_uart[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_uart[1]}]
+set_case_analysis 0 [get_ports {cfg_cska_uart[2]}]
+set_case_analysis 0 [get_ports {cfg_cska_uart[3]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_transition 1.0000 [current_design]
+set_max_capacitance 0.2000 [current_design]
+set_max_fanout 10.0000 [current_design]
diff --git a/sdc/user_project_wrapper.sdc b/sdc/user_project_wrapper.sdc
new file mode 100644
index 0000000..8f2415b
--- /dev/null
+++ b/sdc/user_project_wrapper.sdc
@@ -0,0 +1,987 @@
+###############################################################################
+# Created by write_sdc
+# Thu Dec 1 05:35:24 2022
+###############################################################################
+current_design user_project_wrapper
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name user_clock2 -period 100.0000 [get_ports {user_clock2}]
+set_propagated_clock [get_clocks {user_clock2}]
+create_clock -name wbm_clk_i -period 10.0000 [get_ports {wb_clk_i}]
+set_propagated_clock [get_clocks {wbm_clk_i}]
+create_clock -name wbs_clk_i -period 10.0000 [get_pins {u_wb_host/wbs_clk_out}]
+set_propagated_clock [get_clocks {wbs_clk_i}]
+create_clock -name cpu_clk -period 20.0000 [get_pins {u_wb_host/cpu_clk}]
+set_propagated_clock [get_clocks {cpu_clk}]
+create_clock -name rtc_clk -period 50.0000
+create_clock -name usb_clk -period 20.0000
+create_clock -name line_clk -period 100.0000
+set_clock_uncertainty -rise_from [get_clocks {user_clock2}] -rise_to [get_clocks {user_clock2}] -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {user_clock2}] -rise_to [get_clocks {user_clock2}] -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {user_clock2}] -fall_to [get_clocks {user_clock2}] -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {user_clock2}] -fall_to [get_clocks {user_clock2}] -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {user_clock2}] -rise_to [get_clocks {user_clock2}] -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {user_clock2}] -rise_to [get_clocks {user_clock2}] -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {user_clock2}] -fall_to [get_clocks {user_clock2}] -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {user_clock2}] -fall_to [get_clocks {user_clock2}] -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {wbm_clk_i}] -rise_to [get_clocks {wbm_clk_i}] -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {wbm_clk_i}] -rise_to [get_clocks {wbm_clk_i}] -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {wbm_clk_i}] -fall_to [get_clocks {wbm_clk_i}] -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {wbm_clk_i}] -fall_to [get_clocks {wbm_clk_i}] -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {wbm_clk_i}] -rise_to [get_clocks {wbm_clk_i}] -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {wbm_clk_i}] -rise_to [get_clocks {wbm_clk_i}] -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {wbm_clk_i}] -fall_to [get_clocks {wbm_clk_i}] -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {wbm_clk_i}] -fall_to [get_clocks {wbm_clk_i}] -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {wbs_clk_i}] -rise_to [get_clocks {wbs_clk_i}] -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {wbs_clk_i}] -rise_to [get_clocks {wbs_clk_i}] -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {wbs_clk_i}] -fall_to [get_clocks {wbs_clk_i}] -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {wbs_clk_i}] -fall_to [get_clocks {wbs_clk_i}] -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {wbs_clk_i}] -rise_to [get_clocks {wbs_clk_i}] -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {wbs_clk_i}] -rise_to [get_clocks {wbs_clk_i}] -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {wbs_clk_i}] -fall_to [get_clocks {wbs_clk_i}] -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {wbs_clk_i}] -fall_to [get_clocks {wbs_clk_i}] -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {cpu_clk}] -rise_to [get_clocks {cpu_clk}] -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {cpu_clk}] -rise_to [get_clocks {cpu_clk}] -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {cpu_clk}] -fall_to [get_clocks {cpu_clk}] -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {cpu_clk}] -fall_to [get_clocks {cpu_clk}] -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {cpu_clk}] -rise_to [get_clocks {cpu_clk}] -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {cpu_clk}] -rise_to [get_clocks {cpu_clk}] -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {cpu_clk}] -fall_to [get_clocks {cpu_clk}] -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {cpu_clk}] -fall_to [get_clocks {cpu_clk}] -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}] -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}] -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}] -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}] -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}] -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}] -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}] -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}] -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {usb_clk}] -rise_to [get_clocks {usb_clk}] -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {usb_clk}] -rise_to [get_clocks {usb_clk}] -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {usb_clk}] -fall_to [get_clocks {usb_clk}] -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {usb_clk}] -fall_to [get_clocks {usb_clk}] -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {usb_clk}] -rise_to [get_clocks {usb_clk}] -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {usb_clk}] -rise_to [get_clocks {usb_clk}] -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {usb_clk}] -fall_to [get_clocks {usb_clk}] -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {usb_clk}] -fall_to [get_clocks {usb_clk}] -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {line_clk}] -rise_to [get_clocks {line_clk}] -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {line_clk}] -rise_to [get_clocks {line_clk}] -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {line_clk}] -fall_to [get_clocks {line_clk}] -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {line_clk}] -fall_to [get_clocks {line_clk}] -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {line_clk}] -rise_to [get_clocks {line_clk}] -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {line_clk}] -rise_to [get_clocks {line_clk}] -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {line_clk}] -fall_to [get_clocks {line_clk}] -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {line_clk}] -fall_to [get_clocks {line_clk}] -setup 0.2000
+set_clock_groups -name async_clock -asynchronous \
+ -group [get_clocks {cpu_clk}]\
+ -group [get_clocks {line_clk}]\
+ -group [get_clocks {rtc_clk}]\
+ -group [get_clocks {usb_clk}]\
+ -group [get_clocks {wbm_clk_i}]\
+ -group [get_clocks {wbs_clk_i}] -comment {Async Clock group}
+set_input_delay 2.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wb_rst_i}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[0]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[0]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[10]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[10]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[11]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[11]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[12]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[12]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[13]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[13]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[14]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[14]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[15]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[15]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[16]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[16]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[17]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[17]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[18]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[18]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[19]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[19]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[1]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[1]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[20]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[20]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[21]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[21]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[22]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[22]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[23]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[23]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[24]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[24]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[25]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[25]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[26]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[26]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[27]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[27]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[28]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[28]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[29]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[29]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[2]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[2]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[30]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[30]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[31]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[31]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[3]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[3]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[4]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[4]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[5]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[5]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[6]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[6]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[7]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[7]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[8]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[8]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[9]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[9]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_cyc_i}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_cyc_i}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[0]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[0]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[10]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[10]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[11]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[11]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[12]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[12]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[13]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[13]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[14]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[14]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[15]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[15]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[16]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[16]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[17]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[17]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[18]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[18]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[19]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[19]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[1]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[1]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[20]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[20]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[21]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[21]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[22]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[22]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[23]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[23]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[24]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[24]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[25]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[25]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[26]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[26]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[27]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[27]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[28]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[28]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[29]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[29]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[2]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[2]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[30]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[30]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[31]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[31]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[3]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[3]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[4]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[4]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[5]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[5]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[6]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[6]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[7]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[7]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[8]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[8]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[9]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[9]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_sel_i[0]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_sel_i[0]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_sel_i[1]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_sel_i[1]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_sel_i[2]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_sel_i[2]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_sel_i[3]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_sel_i[3]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_stb_i}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_stb_i}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_we_i}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_we_i}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_ack_o}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_ack_o}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[0]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[0]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[10]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[10]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[11]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[11]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[12]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[12]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[13]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[13]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[14]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[14]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[15]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[15]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[16]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[16]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[17]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[17]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[18]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[18]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[19]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[19]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[1]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[1]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[20]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[20]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[21]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[21]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[22]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[22]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[23]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[23]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[24]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[24]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[25]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[25]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[26]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[26]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[27]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[27]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[28]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[28]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[29]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[29]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[2]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[2]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[30]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[30]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[31]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[31]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[3]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[3]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[4]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[4]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[5]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[5]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[6]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[6]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[7]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[7]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[8]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[8]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[9]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[9]}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {wbs_ack_o}]
+set_load -pin_load 0.0334 [get_ports {analog_io[28]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[27]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[26]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[25]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[24]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[23]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[22]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[21]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[20]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[19]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[18]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[17]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[16]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[15]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[14]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[13]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[12]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[11]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[10]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[9]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[8]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[7]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[6]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[5]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[4]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[3]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[2]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[1]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[0]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[37]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[36]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[35]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[34]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[33]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[32]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[31]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[30]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[29]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[28]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[27]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[26]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[25]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[24]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[23]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[22]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[21]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[20]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[19]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[18]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[17]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[16]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[15]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[14]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[13]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[12]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[11]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[10]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[9]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[8]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[7]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[6]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[5]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[4]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[3]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[2]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[1]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[0]}]
+set_load -pin_load 0.0334 [get_ports {io_out[37]}]
+set_load -pin_load 0.0334 [get_ports {io_out[36]}]
+set_load -pin_load 0.0334 [get_ports {io_out[35]}]
+set_load -pin_load 0.0334 [get_ports {io_out[34]}]
+set_load -pin_load 0.0334 [get_ports {io_out[33]}]
+set_load -pin_load 0.0334 [get_ports {io_out[32]}]
+set_load -pin_load 0.0334 [get_ports {io_out[31]}]
+set_load -pin_load 0.0334 [get_ports {io_out[30]}]
+set_load -pin_load 0.0334 [get_ports {io_out[29]}]
+set_load -pin_load 0.0334 [get_ports {io_out[28]}]
+set_load -pin_load 0.0334 [get_ports {io_out[27]}]
+set_load -pin_load 0.0334 [get_ports {io_out[26]}]
+set_load -pin_load 0.0334 [get_ports {io_out[25]}]
+set_load -pin_load 0.0334 [get_ports {io_out[24]}]
+set_load -pin_load 0.0334 [get_ports {io_out[23]}]
+set_load -pin_load 0.0334 [get_ports {io_out[22]}]
+set_load -pin_load 0.0334 [get_ports {io_out[21]}]
+set_load -pin_load 0.0334 [get_ports {io_out[20]}]
+set_load -pin_load 0.0334 [get_ports {io_out[19]}]
+set_load -pin_load 0.0334 [get_ports {io_out[18]}]
+set_load -pin_load 0.0334 [get_ports {io_out[17]}]
+set_load -pin_load 0.0334 [get_ports {io_out[16]}]
+set_load -pin_load 0.0334 [get_ports {io_out[15]}]
+set_load -pin_load 0.0334 [get_ports {io_out[14]}]
+set_load -pin_load 0.0334 [get_ports {io_out[13]}]
+set_load -pin_load 0.0334 [get_ports {io_out[12]}]
+set_load -pin_load 0.0334 [get_ports {io_out[11]}]
+set_load -pin_load 0.0334 [get_ports {io_out[10]}]
+set_load -pin_load 0.0334 [get_ports {io_out[9]}]
+set_load -pin_load 0.0334 [get_ports {io_out[8]}]
+set_load -pin_load 0.0334 [get_ports {io_out[7]}]
+set_load -pin_load 0.0334 [get_ports {io_out[6]}]
+set_load -pin_load 0.0334 [get_ports {io_out[5]}]
+set_load -pin_load 0.0334 [get_ports {io_out[4]}]
+set_load -pin_load 0.0334 [get_ports {io_out[3]}]
+set_load -pin_load 0.0334 [get_ports {io_out[2]}]
+set_load -pin_load 0.0334 [get_ports {io_out[1]}]
+set_load -pin_load 0.0334 [get_ports {io_out[0]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[127]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[126]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[125]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[124]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[123]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[122]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[121]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[120]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[119]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[118]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[117]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[116]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[115]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[114]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[113]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[112]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[111]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[110]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[109]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[108]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[107]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[106]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[105]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[104]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[103]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[102]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[101]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[100]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[99]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[98]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[97]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[96]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[95]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[94]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[93]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[92]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[91]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[90]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[89]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[88]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[87]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[86]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[85]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[84]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[83]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[82]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[81]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[80]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[79]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[78]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[77]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[76]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[75]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[74]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[73]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[72]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[71]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[70]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[69]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[68]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[67]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[66]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[65]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[64]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[63]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[62]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[61]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[60]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[59]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[58]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[57]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[56]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[55]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[54]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[53]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[52]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[51]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[50]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[49]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[48]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[47]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[46]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[45]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[44]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[43]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[42]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[41]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[40]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[39]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[38]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[37]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[36]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[35]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[34]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[33]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[32]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[31]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[30]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[29]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[28]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[27]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[26]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[25]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[24]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[23]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[22]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[21]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[20]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[19]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[18]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[17]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[16]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[15]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[14]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[13]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[12]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[11]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[10]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[9]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[8]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[7]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[6]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[5]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[4]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[3]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[2]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[1]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[0]}]
+set_load -pin_load 0.0334 [get_ports {user_irq[2]}]
+set_load -pin_load 0.0334 [get_ports {user_irq[1]}]
+set_load -pin_load 0.0334 [get_ports {user_irq[0]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[31]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[30]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[29]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[28]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[27]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[26]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[25]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[24]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[23]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[22]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[21]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[20]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[19]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[18]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[17]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[16]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[15]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[14]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[13]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[12]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[11]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[10]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[9]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[8]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[7]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[6]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[5]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[4]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {user_clock2}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_clk_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_rst_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_cyc_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_stb_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_we_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[127]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[126]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[125]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[124]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[123]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[20]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[127]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[126]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[125]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[124]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[122]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[121]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[119]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[5]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[31]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[0]}]
+set_case_analysis 0 [get_pins {u_intercon/cfg_cska_wi[0]}]
+set_case_analysis 0 [get_pins {u_intercon/cfg_cska_wi[1]}]
+set_case_analysis 0 [get_pins {u_intercon/cfg_cska_wi[2]}]
+set_case_analysis 1 [get_pins {u_intercon/cfg_cska_wi[3]}]
+set_case_analysis 0 [get_pins {u_pinmux/cfg_cska_pinmux[0]}]
+set_case_analysis 1 [get_pins {u_pinmux/cfg_cska_pinmux[1]}]
+set_case_analysis 1 [get_pins {u_pinmux/cfg_cska_pinmux[2]}]
+set_case_analysis 0 [get_pins {u_pinmux/cfg_cska_pinmux[3]}]
+set_case_analysis 0 [get_pins {u_qspi_master/cfg_cska_sp_co[0]}]
+set_case_analysis 0 [get_pins {u_qspi_master/cfg_cska_sp_co[1]}]
+set_case_analysis 0 [get_pins {u_qspi_master/cfg_cska_sp_co[2]}]
+set_case_analysis 0 [get_pins {u_qspi_master/cfg_cska_sp_co[3]}]
+set_case_analysis 0 [get_pins {u_qspi_master/cfg_cska_spi[0]}]
+set_case_analysis 0 [get_pins {u_qspi_master/cfg_cska_spi[1]}]
+set_case_analysis 0 [get_pins {u_qspi_master/cfg_cska_spi[2]}]
+set_case_analysis 1 [get_pins {u_qspi_master/cfg_cska_spi[3]}]
+set_case_analysis 0 [get_pins {u_uart_i2c_usb_spi/cfg_cska_uart[0]}]
+set_case_analysis 0 [get_pins {u_uart_i2c_usb_spi/cfg_cska_uart[1]}]
+set_case_analysis 0 [get_pins {u_uart_i2c_usb_spi/cfg_cska_uart[2]}]
+set_case_analysis 1 [get_pins {u_uart_i2c_usb_spi/cfg_cska_uart[3]}]
+set_case_analysis 0 [get_pins {u_wb_host/cfg_cska_wh[0]}]
+set_case_analysis 0 [get_pins {u_wb_host/cfg_cska_wh[1]}]
+set_case_analysis 0 [get_pins {u_wb_host/cfg_cska_wh[2]}]
+set_case_analysis 1 [get_pins {u_wb_host/cfg_cska_wh[3]}]
+###############################################################################
+# Design Rules
+###############################################################################
diff --git a/sdc/wb_host.sdc b/sdc/wb_host.sdc
new file mode 100644
index 0000000..1176297
--- /dev/null
+++ b/sdc/wb_host.sdc
@@ -0,0 +1,873 @@
+###############################################################################
+# Created by write_sdc
+# Thu Dec 1 02:40:04 2022
+###############################################################################
+current_design wb_host
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name wbm_clk_i -period 10.0000 [get_ports {wbm_clk_i}]
+set_clock_transition 0.1500 [get_clocks {wbm_clk_i}]
+set_clock_uncertainty -setup 0.5000 wbm_clk_i
+set_clock_uncertainty -hold 0.2500 wbm_clk_i
+set_propagated_clock [get_clocks {wbm_clk_i}]
+create_clock -name wbs_clk_i -period 10.0000 [get_ports {wbs_clk_i}]
+set_clock_transition 0.1500 [get_clocks {wbs_clk_i}]
+set_clock_uncertainty -setup 0.5000 wbs_clk_i
+set_clock_uncertainty -hold 0.2500 wbs_clk_i
+set_propagated_clock [get_clocks {wbs_clk_i}]
+create_clock -name uart_clk -period 100.0000 [get_pins {u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X}]
+set_clock_transition 0.1500 [get_clocks {uart_clk}]
+set_clock_uncertainty -setup 0.5000 uart_clk
+set_clock_uncertainty -hold 0.2500 uart_clk
+set_propagated_clock [get_clocks {uart_clk}]
+create_clock -name int_pll_clock -period 10.0000
+set_clock_uncertainty -setup 0.5000 int_pll_clock
+set_clock_uncertainty -hold 0.2500 int_pll_clock
+create_clock -name wbs_ref_clk -period 10.0000
+set_clock_uncertainty -setup 0.5000 wbs_ref_clk
+set_clock_uncertainty -hold 0.2500 wbs_ref_clk
+create_clock -name cpu_ref_clk -period 10.0000
+set_clock_uncertainty -setup 0.5000 cpu_ref_clk
+set_clock_uncertainty -hold 0.2500 cpu_ref_clk
+create_clock -name usb_ref_clk -period 10.0000
+set_clock_uncertainty -setup 0.5000 usb_ref_clk
+set_clock_uncertainty -hold 0.2500 usb_ref_clk
+set_clock_groups -name async_clock -asynchronous \
+ -group [get_clocks {cpu_ref_clk}]\
+ -group [get_clocks {int_pll_clock}]\
+ -group [get_clocks {uart_clk}]\
+ -group [get_clocks {usb_ref_clk}]\
+ -group [get_clocks {wbm_clk_i}]\
+ -group [get_clocks {wbs_clk_i}]\
+ -group [get_clocks {wbs_ref_clk}] -comment {Async Clock group}
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_rst_i}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_rst_i}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_stb_i}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_stb_i}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_ack_i}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_ack_i}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[0]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[10]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[10]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[11]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[11]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[12]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[12]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[13]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[13]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[14]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[14]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[15]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[15]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[16]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[16]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[17]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[17]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[18]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[18]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[19]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[19]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[1]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[20]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[20]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[21]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[21]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[22]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[22]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[23]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[23]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[24]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[24]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[25]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[25]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[26]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[26]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[27]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[27]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[28]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[28]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[29]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[29]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[2]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[30]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[30]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[31]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[31]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[3]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[4]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[4]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[5]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[5]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[6]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[6]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[7]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[7]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[8]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[8]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[9]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[9]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_ack_o}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_ack_o}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[0]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[0]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[10]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[10]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[11]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[11]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[12]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[12]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[13]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[13]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[14]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[14]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[15]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[15]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[16]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[16]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[17]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[17]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[18]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[18]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[19]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[19]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[1]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[1]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[20]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[20]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[21]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[21]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[22]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[22]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[23]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[23]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[24]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[24]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[25]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[25]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[26]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[26]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[27]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[27]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[28]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[28]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[29]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[29]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[2]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[2]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[30]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[30]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[31]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[31]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[3]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[3]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[4]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[4]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[5]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[5]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[6]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[6]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[7]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[7]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[8]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[8]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[9]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[9]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_err_o}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_err_o}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[0]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[0]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[10]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[10]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[11]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[11]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[12]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[12]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[13]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[13]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[14]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[14]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[15]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[15]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[16]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[16]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[17]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[17]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[18]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[18]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[19]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[19]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[1]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[1]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[20]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[20]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[21]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[21]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[22]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[22]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[23]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[23]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[24]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[24]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[25]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[25]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[26]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[26]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[27]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[27]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[28]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[28]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[29]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[29]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[2]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[2]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[30]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[30]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[31]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[31]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[3]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[3]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[4]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[4]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[5]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[5]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[6]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[6]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[7]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[7]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[8]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[8]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[9]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[9]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_cyc_o}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_cyc_o}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[0]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[0]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[10]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[10]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[11]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[11]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[12]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[12]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[13]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[13]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[14]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[14]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[15]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[15]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[16]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[16]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[17]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[17]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[18]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[18]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[19]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[19]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[1]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[1]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[20]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[20]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[21]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[21]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[22]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[22]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[23]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[23]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[24]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[24]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[25]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[25]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[26]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[26]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[27]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[27]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[28]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[28]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[29]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[29]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[2]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[2]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[30]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[30]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[31]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[31]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[3]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[3]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[4]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[4]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[5]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[5]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[6]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[6]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[7]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[7]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[8]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[8]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[9]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[9]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_sel_o[0]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_sel_o[0]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_sel_o[1]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_sel_o[1]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_sel_o[2]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_sel_o[2]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_sel_o[3]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_sel_o[3]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_stb_o}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_stb_o}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_we_o}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_we_o}]
+set_multicycle_path -hold\
+ -from [list [get_ports {wbm_adr_i[0]}]\
+ [get_ports {wbm_adr_i[10]}]\
+ [get_ports {wbm_adr_i[11]}]\
+ [get_ports {wbm_adr_i[12]}]\
+ [get_ports {wbm_adr_i[13]}]\
+ [get_ports {wbm_adr_i[14]}]\
+ [get_ports {wbm_adr_i[15]}]\
+ [get_ports {wbm_adr_i[16]}]\
+ [get_ports {wbm_adr_i[17]}]\
+ [get_ports {wbm_adr_i[18]}]\
+ [get_ports {wbm_adr_i[19]}]\
+ [get_ports {wbm_adr_i[1]}]\
+ [get_ports {wbm_adr_i[20]}]\
+ [get_ports {wbm_adr_i[21]}]\
+ [get_ports {wbm_adr_i[22]}]\
+ [get_ports {wbm_adr_i[23]}]\
+ [get_ports {wbm_adr_i[24]}]\
+ [get_ports {wbm_adr_i[25]}]\
+ [get_ports {wbm_adr_i[26]}]\
+ [get_ports {wbm_adr_i[27]}]\
+ [get_ports {wbm_adr_i[28]}]\
+ [get_ports {wbm_adr_i[29]}]\
+ [get_ports {wbm_adr_i[2]}]\
+ [get_ports {wbm_adr_i[30]}]\
+ [get_ports {wbm_adr_i[31]}]\
+ [get_ports {wbm_adr_i[3]}]\
+ [get_ports {wbm_adr_i[4]}]\
+ [get_ports {wbm_adr_i[5]}]\
+ [get_ports {wbm_adr_i[6]}]\
+ [get_ports {wbm_adr_i[7]}]\
+ [get_ports {wbm_adr_i[8]}]\
+ [get_ports {wbm_adr_i[9]}]\
+ [get_ports {wbm_cyc_i}]\
+ [get_ports {wbm_dat_i[0]}]\
+ [get_ports {wbm_dat_i[10]}]\
+ [get_ports {wbm_dat_i[11]}]\
+ [get_ports {wbm_dat_i[12]}]\
+ [get_ports {wbm_dat_i[13]}]\
+ [get_ports {wbm_dat_i[14]}]\
+ [get_ports {wbm_dat_i[15]}]\
+ [get_ports {wbm_dat_i[16]}]\
+ [get_ports {wbm_dat_i[17]}]\
+ [get_ports {wbm_dat_i[18]}]\
+ [get_ports {wbm_dat_i[19]}]\
+ [get_ports {wbm_dat_i[1]}]\
+ [get_ports {wbm_dat_i[20]}]\
+ [get_ports {wbm_dat_i[21]}]\
+ [get_ports {wbm_dat_i[22]}]\
+ [get_ports {wbm_dat_i[23]}]\
+ [get_ports {wbm_dat_i[24]}]\
+ [get_ports {wbm_dat_i[25]}]\
+ [get_ports {wbm_dat_i[26]}]\
+ [get_ports {wbm_dat_i[27]}]\
+ [get_ports {wbm_dat_i[28]}]\
+ [get_ports {wbm_dat_i[29]}]\
+ [get_ports {wbm_dat_i[2]}]\
+ [get_ports {wbm_dat_i[30]}]\
+ [get_ports {wbm_dat_i[31]}]\
+ [get_ports {wbm_dat_i[3]}]\
+ [get_ports {wbm_dat_i[4]}]\
+ [get_ports {wbm_dat_i[5]}]\
+ [get_ports {wbm_dat_i[6]}]\
+ [get_ports {wbm_dat_i[7]}]\
+ [get_ports {wbm_dat_i[8]}]\
+ [get_ports {wbm_dat_i[9]}]\
+ [get_ports {wbm_sel_i[0]}]\
+ [get_ports {wbm_sel_i[1]}]\
+ [get_ports {wbm_sel_i[2]}]\
+ [get_ports {wbm_sel_i[3]}]\
+ [get_ports {wbm_we_i}]] 2
+set_multicycle_path -setup\
+ -from [list [get_ports {wbm_adr_i[0]}]\
+ [get_ports {wbm_adr_i[10]}]\
+ [get_ports {wbm_adr_i[11]}]\
+ [get_ports {wbm_adr_i[12]}]\
+ [get_ports {wbm_adr_i[13]}]\
+ [get_ports {wbm_adr_i[14]}]\
+ [get_ports {wbm_adr_i[15]}]\
+ [get_ports {wbm_adr_i[16]}]\
+ [get_ports {wbm_adr_i[17]}]\
+ [get_ports {wbm_adr_i[18]}]\
+ [get_ports {wbm_adr_i[19]}]\
+ [get_ports {wbm_adr_i[1]}]\
+ [get_ports {wbm_adr_i[20]}]\
+ [get_ports {wbm_adr_i[21]}]\
+ [get_ports {wbm_adr_i[22]}]\
+ [get_ports {wbm_adr_i[23]}]\
+ [get_ports {wbm_adr_i[24]}]\
+ [get_ports {wbm_adr_i[25]}]\
+ [get_ports {wbm_adr_i[26]}]\
+ [get_ports {wbm_adr_i[27]}]\
+ [get_ports {wbm_adr_i[28]}]\
+ [get_ports {wbm_adr_i[29]}]\
+ [get_ports {wbm_adr_i[2]}]\
+ [get_ports {wbm_adr_i[30]}]\
+ [get_ports {wbm_adr_i[31]}]\
+ [get_ports {wbm_adr_i[3]}]\
+ [get_ports {wbm_adr_i[4]}]\
+ [get_ports {wbm_adr_i[5]}]\
+ [get_ports {wbm_adr_i[6]}]\
+ [get_ports {wbm_adr_i[7]}]\
+ [get_ports {wbm_adr_i[8]}]\
+ [get_ports {wbm_adr_i[9]}]\
+ [get_ports {wbm_cyc_i}]\
+ [get_ports {wbm_dat_i[0]}]\
+ [get_ports {wbm_dat_i[10]}]\
+ [get_ports {wbm_dat_i[11]}]\
+ [get_ports {wbm_dat_i[12]}]\
+ [get_ports {wbm_dat_i[13]}]\
+ [get_ports {wbm_dat_i[14]}]\
+ [get_ports {wbm_dat_i[15]}]\
+ [get_ports {wbm_dat_i[16]}]\
+ [get_ports {wbm_dat_i[17]}]\
+ [get_ports {wbm_dat_i[18]}]\
+ [get_ports {wbm_dat_i[19]}]\
+ [get_ports {wbm_dat_i[1]}]\
+ [get_ports {wbm_dat_i[20]}]\
+ [get_ports {wbm_dat_i[21]}]\
+ [get_ports {wbm_dat_i[22]}]\
+ [get_ports {wbm_dat_i[23]}]\
+ [get_ports {wbm_dat_i[24]}]\
+ [get_ports {wbm_dat_i[25]}]\
+ [get_ports {wbm_dat_i[26]}]\
+ [get_ports {wbm_dat_i[27]}]\
+ [get_ports {wbm_dat_i[28]}]\
+ [get_ports {wbm_dat_i[29]}]\
+ [get_ports {wbm_dat_i[2]}]\
+ [get_ports {wbm_dat_i[30]}]\
+ [get_ports {wbm_dat_i[31]}]\
+ [get_ports {wbm_dat_i[3]}]\
+ [get_ports {wbm_dat_i[4]}]\
+ [get_ports {wbm_dat_i[5]}]\
+ [get_ports {wbm_dat_i[6]}]\
+ [get_ports {wbm_dat_i[7]}]\
+ [get_ports {wbm_dat_i[8]}]\
+ [get_ports {wbm_dat_i[9]}]\
+ [get_ports {wbm_sel_i[0]}]\
+ [get_ports {wbm_sel_i[1]}]\
+ [get_ports {wbm_sel_i[2]}]\
+ [get_ports {wbm_sel_i[3]}]\
+ [get_ports {wbm_we_i}]] 2
+set_max_delay\
+ -from [get_ports {wbd_clk_int}] 3.5000
+set_max_delay\
+ -from [get_ports {wbd_clk_int}]\
+ -to [get_ports {wbd_clk_wh}] 3.5000
+set_max_delay\
+ -to [get_ports {wbd_clk_wh}] 2.0000
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {cfg_strap_pad_ctrl}]
+set_load -pin_load 0.0334 [get_ports {cpu_clk}]
+set_load -pin_load 0.0334 [get_ports {e_reset_n}]
+set_load -pin_load 0.0334 [get_ports {p_reset_n}]
+set_load -pin_load 0.0334 [get_ports {s_reset_n}]
+set_load -pin_load 0.0334 [get_ports {sdout}]
+set_load -pin_load 0.0334 [get_ports {sdout_oen}]
+set_load -pin_load 0.0334 [get_ports {uartm_txd}]
+set_load -pin_load 0.0334 [get_ports {wbd_clk_wh}]
+set_load -pin_load 0.0334 [get_ports {wbd_int_rst_n}]
+set_load -pin_load 0.0334 [get_ports {wbd_pll_rst_n}]
+set_load -pin_load 0.0334 [get_ports {wbm_ack_o}]
+set_load -pin_load 0.0334 [get_ports {wbm_err_o}]
+set_load -pin_load 0.0334 [get_ports {wbs_clk_out}]
+set_load -pin_load 0.0334 [get_ports {wbs_cyc_o}]
+set_load -pin_load 0.0334 [get_ports {wbs_stb_o}]
+set_load -pin_load 0.0334 [get_ports {wbs_we_o}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[31]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[30]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[29]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[28]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[27]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[26]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[25]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[24]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[23]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[22]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[21]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[20]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[19]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[18]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[17]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[16]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[15]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[14]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[13]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[12]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[11]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[10]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[9]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[8]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[31]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[30]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[29]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[28]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[27]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[26]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[25]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[24]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[23]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[22]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[21]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[20]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[19]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[18]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[17]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[16]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[15]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[14]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[13]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[12]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[11]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[10]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[9]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[8]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[0]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[31]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[30]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[29]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[28]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[27]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[26]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[25]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[24]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[23]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[22]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[21]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[20]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[19]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[18]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[17]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[16]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[15]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[14]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[13]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[12]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[11]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[10]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[9]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[8]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[7]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[6]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[5]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[4]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[3]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[2]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[1]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[0]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[31]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[30]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[29]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[28]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[27]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[26]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[25]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[24]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[23]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[22]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[21]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[20]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[19]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[18]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[17]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[16]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[15]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[14]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[13]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[12]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[11]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[10]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[9]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[8]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[7]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[6]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[5]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[4]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[0]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[31]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[30]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[29]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[28]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[27]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[26]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[25]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[24]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[23]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[22]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[21]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[20]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[19]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[18]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[17]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[16]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[15]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[14]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[13]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[12]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[11]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[10]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[9]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[8]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[7]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[6]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[5]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[4]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[0]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[31]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[30]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[29]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[28]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[27]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[26]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[25]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[24]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[23]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[22]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[21]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[20]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[19]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[18]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[17]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[16]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[15]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[14]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[13]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[12]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[11]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[10]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[9]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[8]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[7]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[6]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[5]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[4]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[0]}]
+set_load -pin_load 0.0334 [get_ports {wbs_sel_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wbs_sel_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wbs_sel_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wbs_sel_o[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {int_pll_clock}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sclk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sdin}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ssn}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uartm_rxd}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {user_clock1}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {user_clock2}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_clk_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_cyc_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_rst_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_stb_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_we_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_ack_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_clk_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_err_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {xtal_clk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wh[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wh[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wh[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wh[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_uartm[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_uartm[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_sel_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_sel_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_sel_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_sel_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_wh[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_wh[1]}]
+set_case_analysis 0 [get_ports {cfg_cska_wh[2]}]
+set_case_analysis 0 [get_ports {cfg_cska_wh[3]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_transition 1.0000 [current_design]
+set_max_capacitance 0.2000 [current_design]
+set_max_fanout 10.0000 [current_design]
diff --git a/sdc/wb_interconnect.sdc b/sdc/wb_interconnect.sdc
new file mode 100644
index 0000000..16bb907
--- /dev/null
+++ b/sdc/wb_interconnect.sdc
@@ -0,0 +1,2210 @@
+###############################################################################
+# Created by write_sdc
+# Wed Nov 30 08:02:57 2022
+###############################################################################
+current_design wb_interconnect
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name clk_i -period 10.0000 [get_ports {clk_i}]
+set_clock_transition 0.1500 [get_clocks {clk_i}]
+set_clock_uncertainty -setup 0.5000 clk_i
+set_clock_uncertainty -hold 0.2500 clk_i
+set_propagated_clock [get_clocks {clk_i}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[0]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[10]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[10]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[11]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[11]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[12]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[12]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[13]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[13]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[14]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[14]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[15]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[15]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[16]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[16]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[17]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[17]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[18]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[18]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[19]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[19]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[1]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[20]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[20]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[21]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[21]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[22]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[22]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[23]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[23]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[24]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[24]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[25]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[25]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[26]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[26]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[27]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[27]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[28]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[28]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[29]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[29]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[2]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[30]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[30]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[31]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[31]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[3]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[4]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[4]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[5]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[5]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[6]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[6]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[7]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[7]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[8]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[8]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[9]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[9]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[0]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[10]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[10]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[11]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[11]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[12]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[12]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[13]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[13]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[14]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[14]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[15]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[15]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[16]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[16]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[17]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[17]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[18]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[18]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[19]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[19]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[1]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[20]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[20]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[21]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[21]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[22]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[22]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[23]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[23]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[24]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[24]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[25]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[25]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[26]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[26]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[27]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[27]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[28]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[28]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[29]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[29]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[2]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[30]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[30]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[31]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[31]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[3]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[4]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[4]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[5]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[5]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[6]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[6]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[7]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[7]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[8]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[8]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[9]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[9]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m0_wbd_sel_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m0_wbd_sel_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m0_wbd_sel_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m0_wbd_sel_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m0_wbd_sel_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m0_wbd_sel_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m0_wbd_sel_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m0_wbd_sel_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[0]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[10]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[10]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[11]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[11]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[12]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[12]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[13]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[13]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[14]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[14]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[15]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[15]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[16]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[16]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[17]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[17]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[18]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[18]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[19]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[19]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[1]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[20]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[20]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[21]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[21]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[22]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[22]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[23]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[23]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[24]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[24]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[25]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[25]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[26]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[26]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[27]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[27]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[28]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[28]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[29]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[29]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[2]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[30]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[30]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[31]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[31]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[3]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[4]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[4]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[5]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[5]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[6]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[6]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[7]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[7]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[8]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[8]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[9]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[9]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[10]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[10]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[11]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[11]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[12]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[12]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[13]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[13]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[14]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[14]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[15]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[15]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[16]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[16]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[17]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[17]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[18]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[18]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[19]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[19]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[20]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[20]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[21]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[21]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[22]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[22]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[23]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[23]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[24]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[24]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[25]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[25]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[26]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[26]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[27]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[27]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[28]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[28]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[29]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[29]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[30]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[30]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[31]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[31]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[4]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[4]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[5]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[5]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[6]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[6]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[7]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[7]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[8]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[8]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[9]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[9]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_sel_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_sel_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_sel_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_sel_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_sel_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_sel_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_sel_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_sel_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[0]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[10]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[10]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[11]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[11]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[12]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[12]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[13]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[13]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[14]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[14]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[15]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[15]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[16]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[16]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[17]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[17]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[18]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[18]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[19]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[19]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[1]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[20]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[20]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[21]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[21]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[22]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[22]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[23]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[23]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[24]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[24]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[25]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[25]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[26]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[26]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[27]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[27]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[28]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[28]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[29]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[29]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[2]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[30]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[30]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[31]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[31]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[3]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[4]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[4]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[5]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[5]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[6]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[6]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[7]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[7]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[8]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[8]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[9]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[9]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[10]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[10]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[11]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[11]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[12]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[12]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[13]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[13]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[14]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[14]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[15]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[15]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[16]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[16]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[17]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[17]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[18]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[18]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[19]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[19]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[20]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[20]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[21]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[21]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[22]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[22]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[23]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[23]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[24]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[24]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[25]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[25]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[26]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[26]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[27]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[27]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[28]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[28]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[29]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[29]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[30]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[30]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[31]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[31]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[4]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[4]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[5]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[5]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[6]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[6]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[7]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[7]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[8]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[8]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[9]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[9]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_sel_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_sel_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_sel_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_sel_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_sel_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_sel_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_sel_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_sel_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -max -add_delay [get_ports {rst_n}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -max -add_delay [get_ports {rst_n}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_ack_i}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_ack_i}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[0]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[10]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[10]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[11]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[11]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[12]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[12]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[13]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[13]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[14]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[14]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[15]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[15]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[16]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[16]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[17]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[17]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[18]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[18]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[19]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[19]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[1]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[20]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[20]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[21]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[21]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[22]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[22]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[23]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[23]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[24]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[24]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[25]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[25]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[26]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[26]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[27]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[27]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[28]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[28]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[29]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[29]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[2]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[30]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[30]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[31]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[31]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[3]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[4]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[4]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[5]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[5]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[6]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[6]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[7]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[7]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[8]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[8]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[9]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[9]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_ack_i}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_ack_i}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[0]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[10]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[10]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[11]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[11]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[12]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[12]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[13]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[13]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[14]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[14]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[15]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[15]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[16]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[16]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[17]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[17]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[18]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[18]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[19]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[19]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[1]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[20]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[20]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[21]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[21]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[22]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[22]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[23]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[23]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[24]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[24]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[25]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[25]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[26]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[26]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[27]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[27]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[28]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[28]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[29]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[29]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[2]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[30]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[30]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[31]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[31]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[3]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[4]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[4]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[5]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[5]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[6]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[6]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[7]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[7]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[8]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[8]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[9]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[9]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_ack_i}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_ack_i}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[0]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[10]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[10]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[11]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[11]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[12]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[12]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[13]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[13]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[14]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[14]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[15]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[15]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[16]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[16]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[17]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[17]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[18]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[18]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[19]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[19]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[1]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[20]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[20]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[21]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[21]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[22]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[22]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[23]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[23]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[24]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[24]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[25]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[25]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[26]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[26]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[27]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[27]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[28]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[28]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[29]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[29]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[2]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[30]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[30]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[31]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[31]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[3]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[4]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[4]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[5]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[5]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[6]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[6]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[7]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[7]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[8]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[8]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[9]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[9]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_ack_o}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_ack_o}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[0]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[10]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[10]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[11]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[11]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[12]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[12]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[13]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[13]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[14]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[14]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[15]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[15]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[16]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[16]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[17]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[17]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[18]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[18]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[19]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[19]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[1]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[20]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[20]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[21]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[21]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[22]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[22]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[23]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[23]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[24]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[24]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[25]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[25]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[26]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[26]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[27]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[27]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[28]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[28]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[29]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[29]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[2]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[30]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[30]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[31]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[31]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[3]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[4]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[4]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[5]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[5]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[6]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[6]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[7]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[7]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[8]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[8]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[9]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[9]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_err_o}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_err_o}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_ack_o}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_ack_o}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[0]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[10]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[10]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[11]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[11]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[12]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[12]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[13]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[13]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[14]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[14]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[15]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[15]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[16]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[16]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[17]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[17]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[18]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[18]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[19]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[19]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[1]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[20]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[20]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[21]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[21]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[22]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[22]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[23]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[23]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[24]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[24]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[25]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[25]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[26]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[26]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[27]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[27]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[28]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[28]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[29]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[29]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[2]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[30]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[30]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[31]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[31]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[3]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[4]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[4]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[5]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[5]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[6]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[6]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[7]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[7]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[8]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[8]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[9]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[9]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_err_o}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_err_o}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_ack_o}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_ack_o}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[0]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[10]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[10]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[11]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[11]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[12]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[12]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[13]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[13]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[14]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[14]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[15]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[15]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[16]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[16]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[17]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[17]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[18]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[18]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[19]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[19]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[1]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[20]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[20]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[21]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[21]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[22]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[22]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[23]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[23]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[24]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[24]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[25]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[25]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[26]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[26]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[27]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[27]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[28]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[28]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[29]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[29]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[2]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[30]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[30]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[31]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[31]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[3]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[4]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[4]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[5]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[5]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[6]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[6]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[7]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[7]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[8]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[8]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[9]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[9]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_err_o}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_err_o}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[0]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[10]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[10]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[11]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[11]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[12]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[12]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[13]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[13]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[14]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[14]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[15]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[15]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[16]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[16]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[17]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[17]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[18]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[18]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[19]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[19]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[1]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[20]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[20]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[21]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[21]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[22]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[22]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[23]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[23]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[24]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[24]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[25]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[25]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[26]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[26]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[27]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[27]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[28]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[28]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[29]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[29]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[2]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[30]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[30]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[31]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[31]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[3]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[4]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[4]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[5]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[5]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[6]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[6]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[7]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[7]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[8]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[8]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[9]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[9]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_cyc_o}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_cyc_o}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[0]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[10]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[10]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[11]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[11]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[12]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[12]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[13]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[13]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[14]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[14]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[15]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[15]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[16]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[16]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[17]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[17]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[18]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[18]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[19]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[19]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[1]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[20]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[20]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[21]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[21]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[22]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[22]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[23]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[23]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[24]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[24]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[25]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[25]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[26]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[26]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[27]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[27]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[28]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[28]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[29]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[29]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[2]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[30]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[30]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[31]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[31]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[3]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[4]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[4]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[5]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[5]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[6]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[6]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[7]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[7]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[8]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[8]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[9]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[9]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_sel_o[0]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_sel_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_sel_o[1]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_sel_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_sel_o[2]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_sel_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_sel_o[3]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_sel_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_stb_o}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_stb_o}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_we_o}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_we_o}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_adr_o[0]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_adr_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_adr_o[1]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_adr_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_adr_o[2]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_adr_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_adr_o[3]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_adr_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_adr_o[4]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_adr_o[4]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_adr_o[5]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_adr_o[5]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_adr_o[6]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_adr_o[6]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_adr_o[7]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_adr_o[7]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_adr_o[8]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_adr_o[8]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_cyc_o}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_cyc_o}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[0]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[10]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[10]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[11]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[11]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[12]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[12]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[13]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[13]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[14]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[14]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[15]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[15]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[16]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[16]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[17]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[17]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[18]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[18]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[19]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[19]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[1]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[20]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[20]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[21]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[21]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[22]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[22]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[23]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[23]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[24]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[24]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[25]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[25]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[26]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[26]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[27]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[27]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[28]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[28]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[29]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[29]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[2]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[30]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[30]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[31]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[31]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[3]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[4]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[4]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[5]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[5]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[6]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[6]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[7]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[7]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[8]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[8]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[9]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[9]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_sel_o[0]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_sel_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_sel_o[1]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_sel_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_sel_o[2]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_sel_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_sel_o[3]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_sel_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_stb_o}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_stb_o}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_we_o}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_we_o}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[0]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[1]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[2]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[3]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[4]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[4]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[5]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[5]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[6]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[6]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[7]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[7]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[8]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[8]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[9]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[9]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_cyc_o}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_cyc_o}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[0]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[10]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[10]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[11]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[11]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[12]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[12]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[13]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[13]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[14]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[14]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[15]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[15]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[16]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[16]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[17]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[17]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[18]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[18]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[19]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[19]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[1]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[20]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[20]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[21]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[21]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[22]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[22]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[23]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[23]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[24]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[24]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[25]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[25]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[26]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[26]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[27]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[27]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[28]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[28]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[29]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[29]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[2]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[30]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[30]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[31]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[31]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[3]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[4]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[4]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[5]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[5]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[6]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[6]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[7]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[7]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[8]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[8]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[9]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[9]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_sel_o[0]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_sel_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_sel_o[1]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_sel_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_sel_o[2]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_sel_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_sel_o[3]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_sel_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_stb_o}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_stb_o}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_we_o}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_we_o}]
+set_max_delay\
+ -from [get_ports {wbd_clk_int}] 4.0000
+set_max_delay\
+ -from [get_ports {wbd_clk_int}]\
+ -to [get_ports {wbd_clk_wi}] 4.0000
+set_max_delay\
+ -to [get_ports {wbd_clk_wi}] 2.0000
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {m0_wbd_ack_o}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_err_o}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_lack_o}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_ack_o}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_err_o}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_lack_o}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_ack_o}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_err_o}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_lack_o}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_ack_o}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_err_o}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_lack_o}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_bry_o}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_cyc_o}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_stb_o}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_we_o}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_cyc_o}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_stb_o}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_we_o}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_cyc_o}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_stb_o}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_we_o}]
+set_load -pin_load 0.0334 [get_ports {wbd_clk_wi}]
+set_load -pin_load 0.0334 [get_ports {ch_clk_out[6]}]
+set_load -pin_load 0.0334 [get_ports {ch_clk_out[5]}]
+set_load -pin_load 0.0334 [get_ports {ch_clk_out[4]}]
+set_load -pin_load 0.0334 [get_ports {ch_clk_out[3]}]
+set_load -pin_load 0.0334 [get_ports {ch_clk_out[2]}]
+set_load -pin_load 0.0334 [get_ports {ch_clk_out[1]}]
+set_load -pin_load 0.0334 [get_ports {ch_clk_out[0]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[153]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[152]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[151]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[150]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[149]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[148]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[147]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[146]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[145]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[144]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[143]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[142]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[141]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[140]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[139]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[138]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[137]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[136]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[135]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[134]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[133]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[132]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[131]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[130]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[129]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[128]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[127]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[126]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[125]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[124]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[123]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[122]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[121]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[120]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[119]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[118]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[117]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[116]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[115]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[114]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[113]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[112]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[111]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[110]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[109]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[108]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[107]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[106]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[105]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[104]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[103]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[102]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[101]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[100]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[99]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[98]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[97]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[96]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[95]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[94]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[93]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[92]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[91]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[90]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[89]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[88]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[87]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[86]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[85]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[84]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[83]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[82]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[81]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[80]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[79]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[78]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[77]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[76]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[75]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[74]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[73]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[72]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[71]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[70]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[69]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[68]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[67]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[66]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[65]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[64]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[63]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[62]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[61]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[60]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[59]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[58]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[57]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[56]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[55]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[54]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[53]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[52]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[51]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[50]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[49]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[48]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[47]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[46]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[45]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[44]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[43]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[42]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[41]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[40]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[39]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[38]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[37]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[36]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[35]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[34]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[33]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[32]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[31]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[30]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[29]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[28]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[27]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[26]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[25]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[24]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[23]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[22]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[21]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[20]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[19]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[18]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[17]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[16]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[15]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[14]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[13]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[12]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[11]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[10]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[9]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[8]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[7]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[6]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[5]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[4]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[3]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[2]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[1]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[0]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[31]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[30]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[29]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[28]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[27]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[26]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[25]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[24]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[23]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[22]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[21]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[20]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[19]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[18]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[17]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[16]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[15]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[14]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[13]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[12]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[11]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[10]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[9]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[8]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[7]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[6]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[5]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[4]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[3]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[2]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[1]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[0]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[31]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[30]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[29]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[28]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[27]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[26]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[25]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[24]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[23]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[22]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[21]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[20]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[19]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[18]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[17]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[16]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[15]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[14]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[13]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[12]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[11]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[10]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[9]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[8]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[7]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[6]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[5]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[4]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[3]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[2]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[1]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[0]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[31]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[30]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[29]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[28]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[27]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[26]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[25]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[24]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[23]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[22]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[21]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[20]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[19]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[18]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[17]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[16]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[15]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[14]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[13]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[12]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[11]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[10]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[9]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[8]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[7]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[6]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[5]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[4]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[3]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[2]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[1]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[0]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[31]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[30]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[29]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[28]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[27]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[26]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[25]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[24]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[23]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[22]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[21]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[20]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[19]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[18]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[17]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[16]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[15]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[14]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[13]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[12]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[11]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[10]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[9]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[8]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[7]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[6]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[5]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[4]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[3]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[2]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[1]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[0]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[31]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[30]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[29]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[28]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[27]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[26]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[25]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[24]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[23]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[22]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[21]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[20]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[19]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[18]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[17]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[16]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[15]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[14]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[13]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[12]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[11]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[10]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[9]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[8]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[7]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[6]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[5]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[4]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[3]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[2]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[1]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[0]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_bl_o[9]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_bl_o[8]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_bl_o[7]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_bl_o[6]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_bl_o[5]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_bl_o[4]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_bl_o[3]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_bl_o[2]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_bl_o[1]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_bl_o[0]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[31]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[30]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[29]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[28]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[27]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[26]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[25]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[24]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[23]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[22]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[21]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[20]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[19]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[18]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[17]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[16]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[15]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[14]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[13]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[12]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[11]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[10]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[9]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[8]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[7]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[6]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[5]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[4]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[3]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[2]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[1]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[0]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_sel_o[3]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_sel_o[2]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_sel_o[1]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_sel_o[0]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[8]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[7]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[6]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[5]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[4]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[3]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[2]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[1]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[0]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[31]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[30]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[29]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[28]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[27]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[26]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[25]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[24]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[23]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[22]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[21]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[20]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[19]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[18]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[17]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[16]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[15]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[14]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[13]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[12]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[11]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[10]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[9]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[8]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[7]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[6]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[5]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[4]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[3]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[2]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[1]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[0]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_sel_o[3]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_sel_o[2]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_sel_o[1]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_sel_o[0]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[9]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[8]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[7]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[6]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[5]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[4]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[3]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[2]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[1]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[0]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[31]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[30]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[29]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[28]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[27]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[26]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[25]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[24]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[23]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[22]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[21]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[20]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[19]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[18]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[17]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[16]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[15]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[14]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[13]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[12]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[11]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[10]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[9]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[8]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[7]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[6]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[5]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[4]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[3]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[2]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[1]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[0]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_sel_o[3]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_sel_o[2]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_sel_o[1]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_sel_o[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {clk_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_cyc_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_stb_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_we_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_bry_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_cyc_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_stb_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_we_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_bry_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_cyc_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_stb_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_we_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_bry_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_cyc_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_stb_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_we_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_ack_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_lack_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_ack_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_ack_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wi[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wi[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wi[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wi[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_clk_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_clk_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_clk_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_clk_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_clk_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_clk_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_clk_in[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[153]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[152]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[151]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[150]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[149]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[148]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[147]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[146]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[145]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[144]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[143]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[142]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[141]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[140]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[139]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[138]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[137]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[136]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[135]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[134]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[133]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[132]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[131]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[130]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[129]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[128]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[127]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[126]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[125]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[124]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[123]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[122]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[121]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[120]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[119]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[118]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[117]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[116]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[115]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[114]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[113]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[112]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[111]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[110]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[109]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[108]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[107]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[106]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[105]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[104]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[103]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[102]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[101]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[100]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[99]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[98]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[97]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[96]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[95]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[94]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[93]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[92]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[91]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[90]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[89]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[88]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[87]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[86]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[85]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[84]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[83]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[82]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[81]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[80]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[79]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[78]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[77]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[76]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[75]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[74]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[73]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[72]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[71]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[70]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[69]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[68]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[67]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[66]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[65]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[64]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[63]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[62]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[61]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[60]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[59]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[58]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[57]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[56]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[55]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[54]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[53]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[52]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[51]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[50]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[49]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[48]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[47]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[46]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[45]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[44]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[43]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[42]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[41]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[40]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[39]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[38]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_sel_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_sel_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_sel_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_sel_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_bl_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_bl_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_bl_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_sel_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_sel_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_sel_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_sel_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_bl_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_bl_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_bl_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_bl_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_bl_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_bl_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_bl_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_bl_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_bl_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_bl_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_sel_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_sel_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_sel_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_sel_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_bl_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_bl_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_bl_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_bl_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_bl_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_bl_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_bl_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_bl_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_bl_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_bl_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_sel_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_sel_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_sel_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_sel_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_wi[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_wi[1]}]
+set_case_analysis 0 [get_ports {cfg_cska_wi[2]}]
+set_case_analysis 0 [get_ports {cfg_cska_wi[3]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_transition 1.0000 [current_design]
+set_max_capacitance 0.2000 [current_design]
+set_max_fanout 10.0000 [current_design]
diff --git a/sdc/ycr4_iconnect.sdc b/sdc/ycr4_iconnect.sdc
new file mode 100644
index 0000000..fccebd8
--- /dev/null
+++ b/sdc/ycr4_iconnect.sdc
@@ -0,0 +1,4422 @@
+###############################################################################
+# Created by write_sdc
+# Wed Nov 30 11:46:32 2022
+###############################################################################
+current_design ycr4_iconnect
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name core_clk -period 10.0000 [get_ports {core_clk}]
+set_clock_transition 0.1500 [get_clocks {core_clk}]
+set_clock_uncertainty -setup 0.5000 core_clk
+set_clock_uncertainty -hold 0.3000 core_clk
+set_propagated_clock [get_clocks {core_clk}]
+create_generated_clock -name sram0_clk0 -add -source [get_ports {core_clk}] -master_clock [get_clocks {core_clk}] -divide_by 1 -comment {sram0 clock-0} [get_ports {sram0_clk0}]
+set_clock_transition 0.1500 [get_clocks {sram0_clk0}]
+set_clock_uncertainty -setup 0.5000 sram0_clk0
+set_clock_uncertainty -hold 0.3000 sram0_clk0
+set_propagated_clock [get_clocks {sram0_clk0}]
+create_generated_clock -name sram0_clk1 -add -source [get_ports {core_clk}] -master_clock [get_clocks {core_clk}] -divide_by 1 -comment {sram0 clock-0} [get_ports {sram0_clk1}]
+set_clock_transition 0.1500 [get_clocks {sram0_clk1}]
+set_clock_uncertainty -setup 0.5000 sram0_clk1
+set_clock_uncertainty -hold 0.3000 sram0_clk1
+set_propagated_clock [get_clocks {sram0_clk1}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[0]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[0]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[10]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[10]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[11]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[11]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[12]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[12]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[13]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[13]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[14]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[14]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[15]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[15]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[16]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[16]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[17]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[17]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[18]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[18]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[19]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[19]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[1]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[1]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[20]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[20]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[21]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[21]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[22]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[22]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[23]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[23]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[24]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[24]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[25]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[25]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[26]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[26]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[27]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[27]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[28]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[28]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[29]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[29]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[2]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[2]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[30]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[30]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[31]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[31]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[32]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[32]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[33]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[33]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[34]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[34]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[35]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[35]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[36]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[36]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[37]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[37]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[38]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[38]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[39]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[39]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[3]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[3]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[40]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[40]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[41]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[41]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[42]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[42]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[43]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[43]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[44]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[44]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[45]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[45]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[46]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[46]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[47]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[47]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[48]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[48]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[4]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[4]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[5]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[5]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[6]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[6]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[7]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[7]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[8]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[8]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[9]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[9]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[0]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[0]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[10]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[10]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[11]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[11]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[12]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[12]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[13]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[13]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[14]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[14]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[15]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[15]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[16]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[16]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[17]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[17]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[18]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[18]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[19]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[19]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[1]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[1]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[20]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[20]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[21]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[21]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[22]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[22]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[23]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[23]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[24]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[24]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[25]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[25]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[26]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[26]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[27]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[27]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[28]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[28]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[29]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[29]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[2]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[2]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[30]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[30]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[31]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[31]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[3]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[3]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[4]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[4]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[5]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[5]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[6]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[6]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[7]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[7]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[8]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[8]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[9]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[9]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_cmd}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_cmd}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_req}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_req}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[0]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[0]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[10]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[10]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[11]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[11]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[12]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[12]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[13]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[13]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[14]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[14]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[15]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[15]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[16]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[16]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[17]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[17]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[18]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[18]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[19]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[19]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[1]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[1]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[20]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[20]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[21]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[21]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[22]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[22]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[23]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[23]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[24]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[24]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[25]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[25]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[26]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[26]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[27]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[27]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[28]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[28]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[29]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[29]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[2]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[2]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[30]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[30]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[31]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[31]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[3]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[3]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[4]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[4]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[5]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[5]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[6]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[6]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[7]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[7]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[8]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[8]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[9]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[9]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_width[0]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_width[0]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_width[1]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_width[1]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[0]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[0]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[10]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[10]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[11]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[11]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[12]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[12]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[13]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[13]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[14]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[14]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[15]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[15]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[16]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[16]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[17]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[17]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[18]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[18]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[19]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[19]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[1]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[1]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[20]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[20]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[21]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[21]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[22]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[22]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[23]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[23]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[24]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[24]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[25]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[25]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[26]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[26]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[27]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[27]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[28]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[28]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[29]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[29]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[2]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[2]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[30]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[30]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[31]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[31]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[3]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[3]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[4]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[4]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[5]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[5]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[6]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[6]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[7]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[7]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[8]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[8]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[9]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[9]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_bl[0]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_bl[0]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_bl[1]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_bl[1]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_bl[2]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_bl[2]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_cmd}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_cmd}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_req}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_req}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[0]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[0]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[10]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[10]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[11]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[11]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[12]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[12]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[13]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[13]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[14]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[14]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[15]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[15]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[16]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[16]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[17]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[17]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[18]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[18]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[19]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[19]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[1]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[1]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[20]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[20]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[21]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[21]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[22]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[22]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[23]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[23]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[24]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[24]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[25]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[25]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[26]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[26]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[27]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[27]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[28]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[28]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[29]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[29]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[2]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[2]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[30]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[30]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[31]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[31]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[32]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[32]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[33]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[33]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[34]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[34]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[35]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[35]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[36]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[36]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[37]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[37]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[38]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[38]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[39]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[39]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[3]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[3]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[40]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[40]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[41]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[41]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[42]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[42]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[43]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[43]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[44]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[44]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[45]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[45]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[46]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[46]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[47]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[47]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[48]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[48]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[4]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[4]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[5]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[5]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[6]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[6]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[7]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[7]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[8]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[8]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[9]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[9]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[0]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[0]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[10]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[10]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[11]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[11]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[12]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[12]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[13]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[13]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[14]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[14]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[15]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[15]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[16]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[16]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[17]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[17]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[18]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[18]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[19]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[19]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[1]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[1]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[20]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[20]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[21]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[21]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[22]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[22]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[23]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[23]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[24]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[24]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[25]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[25]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[26]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[26]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[27]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[27]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[28]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[28]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[29]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[29]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[2]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[2]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[30]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[30]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[31]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[31]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[3]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[3]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[4]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[4]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[5]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[5]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[6]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[6]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[7]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[7]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[8]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[8]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[9]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[9]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_cmd}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_cmd}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_req}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_req}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[0]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[0]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[10]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[10]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[11]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[11]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[12]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[12]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[13]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[13]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[14]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[14]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[15]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[15]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[16]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[16]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[17]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[17]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[18]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[18]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[19]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[19]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[1]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[1]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[20]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[20]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[21]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[21]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[22]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[22]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[23]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[23]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[24]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[24]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[25]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[25]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[26]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[26]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[27]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[27]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[28]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[28]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[29]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[29]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[2]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[2]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[30]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[30]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[31]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[31]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[3]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[3]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[4]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[4]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[5]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[5]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[6]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[6]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[7]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[7]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[8]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[8]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[9]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[9]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_width[0]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_width[0]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_width[1]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_width[1]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[0]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[0]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[10]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[10]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[11]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[11]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[12]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[12]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[13]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[13]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[14]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[14]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[15]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[15]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[16]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[16]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[17]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[17]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[18]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[18]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[19]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[19]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[1]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[1]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[20]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[20]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[21]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[21]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[22]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[22]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[23]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[23]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[24]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[24]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[25]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[25]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[26]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[26]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[27]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[27]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[28]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[28]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[29]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[29]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[2]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[2]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[30]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[30]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[31]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[31]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[3]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[3]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[4]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[4]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[5]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[5]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[6]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[6]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[7]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[7]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[8]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[8]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[9]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[9]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_bl[0]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_bl[0]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_bl[1]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_bl[1]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_bl[2]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_bl[2]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_cmd}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_cmd}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_req}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_req}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[0]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[0]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[10]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[10]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[11]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[11]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[12]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[12]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[13]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[13]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[14]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[14]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[15]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[15]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[16]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[16]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[17]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[17]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[18]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[18]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[19]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[19]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[1]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[1]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[20]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[20]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[21]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[21]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[22]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[22]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[23]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[23]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[24]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[24]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[25]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[25]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[26]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[26]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[27]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[27]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[28]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[28]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[29]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[29]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[2]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[2]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[30]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[30]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[31]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[31]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[32]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[32]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[33]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[33]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[34]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[34]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[35]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[35]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[36]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[36]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[37]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[37]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[38]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[38]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[39]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[39]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[3]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[3]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[40]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[40]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[41]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[41]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[42]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[42]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[43]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[43]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[44]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[44]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[45]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[45]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[46]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[46]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[47]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[47]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[48]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[48]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[4]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[4]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[5]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[5]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[6]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[6]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[7]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[7]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[8]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[8]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[9]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[9]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[0]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[0]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[10]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[10]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[11]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[11]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[12]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[12]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[13]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[13]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[14]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[14]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[15]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[15]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[16]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[16]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[17]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[17]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[18]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[18]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[19]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[19]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[1]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[1]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[20]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[20]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[21]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[21]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[22]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[22]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[23]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[23]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[24]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[24]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[25]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[25]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[26]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[26]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[27]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[27]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[28]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[28]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[29]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[29]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[2]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[2]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[30]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[30]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[31]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[31]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[3]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[3]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[4]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[4]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[5]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[5]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[6]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[6]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[7]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[7]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[8]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[8]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[9]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[9]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_cmd}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_cmd}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_req}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_req}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[0]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[0]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[10]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[10]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[11]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[11]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[12]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[12]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[13]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[13]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[14]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[14]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[15]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[15]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[16]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[16]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[17]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[17]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[18]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[18]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[19]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[19]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[1]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[1]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[20]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[20]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[21]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[21]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[22]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[22]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[23]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[23]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[24]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[24]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[25]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[25]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[26]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[26]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[27]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[27]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[28]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[28]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[29]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[29]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[2]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[2]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[30]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[30]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[31]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[31]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[3]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[3]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[4]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[4]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[5]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[5]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[6]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[6]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[7]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[7]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[8]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[8]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[9]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[9]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_width[0]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_width[0]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_width[1]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_width[1]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[0]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[0]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[10]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[10]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[11]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[11]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[12]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[12]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[13]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[13]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[14]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[14]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[15]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[15]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[16]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[16]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[17]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[17]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[18]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[18]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[19]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[19]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[1]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[1]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[20]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[20]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[21]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[21]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[22]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[22]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[23]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[23]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[24]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[24]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[25]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[25]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[26]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[26]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[27]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[27]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[28]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[28]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[29]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[29]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[2]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[2]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[30]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[30]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[31]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[31]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[3]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[3]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[4]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[4]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[5]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[5]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[6]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[6]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[7]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[7]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[8]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[8]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[9]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[9]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_bl[0]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_bl[0]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_bl[1]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_bl[1]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_bl[2]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_bl[2]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_cmd}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_cmd}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_req}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_req}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[0]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[0]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[10]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[10]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[11]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[11]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[12]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[12]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[13]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[13]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[14]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[14]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[15]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[15]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[16]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[16]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[17]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[17]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[18]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[18]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[19]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[19]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[1]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[1]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[20]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[20]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[21]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[21]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[22]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[22]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[23]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[23]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[24]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[24]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[25]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[25]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[26]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[26]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[27]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[27]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[28]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[28]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[29]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[29]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[2]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[2]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[30]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[30]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[31]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[31]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[32]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[32]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[33]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[33]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[34]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[34]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[35]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[35]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[36]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[36]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[37]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[37]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[38]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[38]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[39]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[39]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[3]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[3]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[40]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[40]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[41]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[41]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[42]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[42]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[43]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[43]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[44]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[44]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[45]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[45]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[46]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[46]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[47]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[47]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[48]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[48]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[4]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[4]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[5]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[5]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[6]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[6]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[7]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[7]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[8]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[8]}]
+set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[9]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[9]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[0]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[0]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[10]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[10]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[11]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[11]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[12]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[12]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[13]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[13]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[14]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[14]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[15]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[15]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[16]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[16]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[17]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[17]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[18]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[18]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[19]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[19]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[1]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[1]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[20]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[20]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[21]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[21]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[22]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[22]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[23]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[23]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[24]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[24]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[25]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[25]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[26]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[26]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[27]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[27]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[28]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[28]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[29]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[29]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[2]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[2]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[30]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[30]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[31]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[31]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[3]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[3]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[4]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[4]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[5]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[5]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[6]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[6]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[7]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[7]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[8]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[8]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[9]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[9]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_cmd}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_cmd}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_req}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_req}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[0]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[0]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[10]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[10]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[11]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[11]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[12]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[12]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[13]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[13]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[14]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[14]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[15]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[15]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[16]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[16]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[17]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[17]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[18]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[18]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[19]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[19]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[1]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[1]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[20]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[20]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[21]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[21]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[22]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[22]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[23]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[23]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[24]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[24]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[25]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[25]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[26]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[26]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[27]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[27]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[28]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[28]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[29]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[29]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[2]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[2]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[30]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[30]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[31]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[31]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[3]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[3]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[4]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[4]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[5]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[5]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[6]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[6]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[7]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[7]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[8]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[8]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[9]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[9]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_width[0]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_width[0]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_width[1]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_width[1]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[0]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[0]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[10]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[10]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[11]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[11]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[12]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[12]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[13]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[13]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[14]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[14]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[15]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[15]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[16]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[16]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[17]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[17]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[18]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[18]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[19]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[19]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[1]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[1]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[20]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[20]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[21]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[21]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[22]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[22]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[23]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[23]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[24]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[24]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[25]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[25]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[26]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[26]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[27]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[27]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[28]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[28]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[29]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[29]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[2]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[2]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[30]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[30]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[31]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[31]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[3]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[3]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[4]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[4]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[5]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[5]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[6]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[6]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[7]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[7]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[8]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[8]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[9]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[9]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_bl[0]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_bl[0]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_bl[1]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_bl[1]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_bl[2]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_bl[2]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_cmd}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_cmd}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_req}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_req}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[0]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[0]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[10]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[10]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[11]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[11]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[12]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[12]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[13]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[13]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[14]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[14]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[15]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[15]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[16]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[16]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[17]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[17]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[18]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[18]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[19]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[19]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[1]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[1]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[20]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[20]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[21]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[21]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[22]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[22]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[23]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[23]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[24]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[24]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[25]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[25]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[26]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[26]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[27]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[27]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[28]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[28]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[29]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[29]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[2]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[2]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[30]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[30]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[31]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[31]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[3]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[3]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[4]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[4]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[5]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[5]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[6]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[6]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[7]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[7]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[8]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[8]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[9]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[9]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_req_ack}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_req_ack}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_resp[0]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_resp[0]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_resp[1]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_resp[1]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[0]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[0]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[10]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[10]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[11]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[11]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[12]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[12]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[13]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[13]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[14]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[14]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[15]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[15]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[16]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[16]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[17]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[17]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[18]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[18]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[19]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[19]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[1]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[1]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[20]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[20]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[21]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[21]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[22]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[22]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[23]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[23]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[24]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[24]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[25]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[25]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[26]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[26]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[27]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[27]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[28]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[28]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[29]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[29]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[2]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[2]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[30]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[30]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[31]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[31]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[3]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[3]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[4]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[4]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[5]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[5]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[6]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[6]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[7]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[7]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[8]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[8]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[9]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[9]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_req_ack}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_req_ack}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_resp[0]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_resp[0]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_resp[1]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_resp[1]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[0]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[0]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[10]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[10]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[11]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[11]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[12]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[12]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[13]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[13]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[14]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[14]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[15]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[15]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[16]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[16]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[17]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[17]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[18]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[18]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[19]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[19]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[1]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[1]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[20]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[20]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[21]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[21]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[22]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[22]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[23]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[23]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[24]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[24]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[25]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[25]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[26]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[26]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[27]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[27]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[28]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[28]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[29]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[29]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[2]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[2]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[30]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[30]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[31]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[31]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[3]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[3]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[4]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[4]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[5]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[5]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[6]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[6]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[7]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[7]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[8]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[8]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[9]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[9]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_req_ack}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_req_ack}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_resp[0]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_resp[0]}]
+set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_resp[1]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_resp[1]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[0]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[0]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[10]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[10]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[11]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[11]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[12]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[12]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[13]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[13]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[14]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[14]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[15]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[15]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[16]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[16]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[17]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[17]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[18]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[18]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[19]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[19]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[1]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[1]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[20]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[20]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[21]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[21]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[22]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[22]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[23]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[23]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[24]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[24]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[25]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[25]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[26]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[26]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[27]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[27]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[28]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[28]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[29]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[29]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[2]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[2]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[30]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[30]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[31]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[31]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[3]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[3]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[4]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[4]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[5]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[5]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[6]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[6]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[7]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[7]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[8]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[8]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[9]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[9]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[0]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[0]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[10]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[10]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[11]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[11]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[12]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[12]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[13]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[13]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[14]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[14]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[15]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[15]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[16]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[16]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[17]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[17]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[18]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[18]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[19]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[19]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[1]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[1]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[20]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[20]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[21]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[21]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[22]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[22]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[23]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[23]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[24]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[24]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[25]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[25]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[26]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[26]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[27]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[27]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[28]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[28]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[29]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[29]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[2]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[2]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[30]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[30]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[31]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[31]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[3]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[3]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[4]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[4]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[5]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[5]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[6]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[6]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[7]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[7]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[8]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[8]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[9]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[9]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[0]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[0]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[10]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[10]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[11]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[11]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[12]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[12]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[13]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[13]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[14]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[14]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[15]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[15]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[16]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[16]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[17]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[17]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[18]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[18]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[19]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[19]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[1]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[1]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[20]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[20]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[21]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[21]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[22]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[22]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[23]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[23]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[24]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[24]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[25]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[25]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[26]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[26]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[27]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[27]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[28]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[28]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[29]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[29]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[2]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[2]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[30]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[30]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[31]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[31]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[3]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[3]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[4]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[4]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[5]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[5]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[6]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[6]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[7]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[7]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[8]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[8]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[9]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[9]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_req_ack}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_req_ack}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[0]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[0]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[10]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[10]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[11]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[11]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[12]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[12]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[13]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[13]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[14]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[14]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[15]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[15]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[16]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[16]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[17]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[17]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[18]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[18]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[19]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[19]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[1]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[1]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[20]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[20]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[21]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[21]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[22]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[22]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[23]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[23]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[24]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[24]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[25]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[25]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[26]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[26]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[27]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[27]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[28]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[28]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[29]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[29]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[2]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[2]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[30]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[30]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[31]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[31]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[3]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[3]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[4]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[4]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[5]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[5]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[6]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[6]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[7]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[7]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[8]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[8]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[9]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[9]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_req_ack}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_req_ack}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[0]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[0]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[10]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[10]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[11]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[11]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[12]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[12]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[13]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[13]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[14]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[14]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[15]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[15]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[16]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[16]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[17]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[17]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[18]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[18]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[19]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[19]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[1]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[1]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[20]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[20]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[21]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[21]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[22]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[22]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[23]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[23]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[24]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[24]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[25]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[25]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[26]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[26]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[27]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[27]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[28]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[28]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[29]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[29]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[2]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[2]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[30]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[30]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[31]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[31]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[3]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[3]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[4]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[4]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[5]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[5]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[6]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[6]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[7]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[7]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[8]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[8]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[9]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[9]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_req_ack}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_req_ack}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[0]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[0]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[10]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[10]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[11]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[11]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[12]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[12]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[13]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[13]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[14]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[14]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[15]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[15]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[16]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[16]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[17]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[17]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[18]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[18]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[19]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[19]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[1]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[1]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[20]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[20]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[21]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[21]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[22]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[22]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[23]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[23]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[24]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[24]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[25]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[25]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[26]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[26]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[27]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[27]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[28]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[28]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[29]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[29]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[2]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[2]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[30]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[30]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[31]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[31]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[3]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[3]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[4]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[4]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[5]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[5]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[6]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[6]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[7]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[7]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[8]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[8]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[9]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[9]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_req_ack}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_req_ack}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_rdata[0]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_rdata[0]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_rdata[10]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_rdata[10]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_rdata[11]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_rdata[11]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_rdata[12]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_rdata[12]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_rdata[13]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_rdata[13]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_rdata[14]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_rdata[14]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_rdata[15]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_rdata[15]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_rdata[16]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_rdata[16]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_rdata[17]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_rdata[17]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_rdata[18]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_rdata[18]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_rdata[19]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_rdata[19]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_rdata[1]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_rdata[1]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_rdata[20]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_rdata[20]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_rdata[21]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_rdata[21]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_rdata[22]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_rdata[22]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_rdata[23]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_rdata[23]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_rdata[24]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_rdata[24]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_rdata[25]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_rdata[25]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_rdata[26]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_rdata[26]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_rdata[27]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_rdata[27]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_rdata[28]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_rdata[28]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_rdata[29]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_rdata[29]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_rdata[2]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_rdata[2]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_rdata[30]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_rdata[30]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_rdata[31]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_rdata[31]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_rdata[3]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_rdata[3]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_rdata[4]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_rdata[4]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_rdata[5]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_rdata[5]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_rdata[6]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_rdata[6]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_rdata[7]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_rdata[7]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_rdata[8]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_rdata[8]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_rdata[9]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_rdata[9]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_req_ack}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_req_ack}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_rdata[0]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_rdata[0]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_rdata[10]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_rdata[10]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_rdata[11]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_rdata[11]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_rdata[12]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_rdata[12]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_rdata[13]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_rdata[13]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_rdata[14]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_rdata[14]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_rdata[15]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_rdata[15]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_rdata[16]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_rdata[16]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_rdata[17]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_rdata[17]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_rdata[18]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_rdata[18]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_rdata[19]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_rdata[19]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_rdata[1]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_rdata[1]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_rdata[20]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_rdata[20]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_rdata[21]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_rdata[21]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_rdata[22]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_rdata[22]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_rdata[23]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_rdata[23]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_rdata[24]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_rdata[24]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_rdata[25]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_rdata[25]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_rdata[26]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_rdata[26]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_rdata[27]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_rdata[27]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_rdata[28]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_rdata[28]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_rdata[29]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_rdata[29]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_rdata[2]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_rdata[2]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_rdata[30]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_rdata[30]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_rdata[31]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_rdata[31]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_rdata[3]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_rdata[3]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_rdata[4]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_rdata[4]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_rdata[5]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_rdata[5]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_rdata[6]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_rdata[6]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_rdata[7]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_rdata[7]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_rdata[8]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_rdata[8]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_rdata[9]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_rdata[9]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_req_ack}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_req_ack}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_rdata[0]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_rdata[0]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_rdata[10]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_rdata[10]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_rdata[11]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_rdata[11]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_rdata[12]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_rdata[12]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_rdata[13]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_rdata[13]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_rdata[14]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_rdata[14]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_rdata[15]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_rdata[15]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_rdata[16]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_rdata[16]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_rdata[17]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_rdata[17]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_rdata[18]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_rdata[18]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_rdata[19]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_rdata[19]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_rdata[1]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_rdata[1]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_rdata[20]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_rdata[20]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_rdata[21]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_rdata[21]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_rdata[22]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_rdata[22]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_rdata[23]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_rdata[23]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_rdata[24]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_rdata[24]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_rdata[25]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_rdata[25]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_rdata[26]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_rdata[26]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_rdata[27]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_rdata[27]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_rdata[28]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_rdata[28]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_rdata[29]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_rdata[29]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_rdata[2]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_rdata[2]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_rdata[30]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_rdata[30]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_rdata[31]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_rdata[31]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_rdata[3]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_rdata[3]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_rdata[4]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_rdata[4]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_rdata[5]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_rdata[5]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_rdata[6]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_rdata[6]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_rdata[7]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_rdata[7]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_rdata[8]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_rdata[8]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_rdata[9]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_rdata[9]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_req_ack}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_req_ack}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_rdata[0]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_rdata[0]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_rdata[10]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_rdata[10]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_rdata[11]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_rdata[11]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_rdata[12]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_rdata[12]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_rdata[13]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_rdata[13]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_rdata[14]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_rdata[14]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_rdata[15]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_rdata[15]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_rdata[16]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_rdata[16]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_rdata[17]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_rdata[17]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_rdata[18]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_rdata[18]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_rdata[19]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_rdata[19]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_rdata[1]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_rdata[1]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_rdata[20]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_rdata[20]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_rdata[21]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_rdata[21]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_rdata[22]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_rdata[22]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_rdata[23]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_rdata[23]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_rdata[24]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_rdata[24]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_rdata[25]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_rdata[25]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_rdata[26]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_rdata[26]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_rdata[27]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_rdata[27]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_rdata[28]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_rdata[28]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_rdata[29]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_rdata[29]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_rdata[2]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_rdata[2]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_rdata[30]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_rdata[30]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_rdata[31]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_rdata[31]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_rdata[3]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_rdata[3]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_rdata[4]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_rdata[4]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_rdata[5]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_rdata[5]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_rdata[6]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_rdata[6]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_rdata[7]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_rdata[7]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_rdata[8]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_rdata[8]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_rdata[9]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_rdata[9]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_req_ack}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_req_ack}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[0]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[0]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[10]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[10]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[11]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[11]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[12]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[12]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[13]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[13]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[14]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[14]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[15]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[15]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[16]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[16]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[17]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[17]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[18]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[18]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[19]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[19]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[1]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[1]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[20]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[20]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[21]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[21]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[22]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[22]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[23]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[23]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[24]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[24]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[25]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[25]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[26]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[26]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[27]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[27]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[28]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[28]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[29]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[29]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[2]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[2]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[30]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[30]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[31]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[31]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[3]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[3]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[4]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[4]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[5]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[5]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[6]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[6]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[7]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[7]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[8]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[8]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[9]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[9]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_cmd}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_cmd}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_req}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_req}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[0]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[0]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[10]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[10]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[11]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[11]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[12]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[12]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[13]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[13]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[14]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[14]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[15]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[15]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[16]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[16]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[17]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[17]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[18]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[18]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[19]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[19]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[1]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[1]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[20]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[20]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[21]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[21]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[22]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[22]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[23]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[23]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[24]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[24]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[25]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[25]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[26]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[26]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[27]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[27]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[28]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[28]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[29]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[29]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[2]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[2]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[30]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[30]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[31]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[31]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[3]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[3]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[4]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[4]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[5]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[5]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[6]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[6]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[7]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[7]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[8]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[8]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[9]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[9]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_width[0]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_width[0]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_width[1]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_width[1]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[0]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[0]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[10]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[10]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[11]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[11]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[12]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[12]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[13]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[13]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[14]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[14]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[15]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[15]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[16]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[16]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[17]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[17]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[18]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[18]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[19]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[19]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[1]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[1]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[20]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[20]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[21]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[21]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[22]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[22]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[23]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[23]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[24]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[24]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[25]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[25]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[26]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[26]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[27]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[27]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[28]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[28]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[29]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[29]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[2]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[2]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[30]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[30]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[31]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[31]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[3]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[3]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[4]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[4]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[5]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[5]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[6]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[6]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[7]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[7]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[8]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[8]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[9]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[9]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_bl[0]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_bl[0]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_bl[1]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_bl[1]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_bl[2]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_bl[2]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_cmd}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_cmd}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_req}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_req}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[0]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[0]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[10]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[10]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[11]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[11]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[12]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[12]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[13]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[13]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[14]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[14]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[15]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[15]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[16]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[16]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[17]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[17]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[18]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[18]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[19]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[19]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[1]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[1]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[20]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[20]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[21]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[21]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[22]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[22]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[23]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[23]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[24]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[24]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[25]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[25]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[26]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[26]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[27]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[27]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[28]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[28]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[29]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[29]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[2]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[2]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[30]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[30]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[31]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[31]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[3]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[3]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[4]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[4]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[5]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[5]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[6]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[6]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[7]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[7]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[8]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[8]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[9]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[9]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_width[0]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_width[0]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_width[1]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_width[1]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[0]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[0]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[10]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[10]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[11]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[11]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[12]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[12]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[13]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[13]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[14]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[14]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[15]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[15]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[16]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[16]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[17]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[17]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[18]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[18]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[19]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[19]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[1]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[1]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[20]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[20]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[21]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[21]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[22]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[22]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[23]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[23]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[24]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[24]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[25]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[25]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[26]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[26]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[27]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[27]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[28]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[28]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[29]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[29]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[2]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[2]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[30]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[30]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[31]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[31]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[3]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[3]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[4]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[4]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[5]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[5]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[6]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[6]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[7]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[7]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[8]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[8]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[9]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[9]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_bl[0]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_bl[0]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_bl[1]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_bl[1]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_bl[2]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_bl[2]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_cmd}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_cmd}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_req}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_req}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_width[0]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_width[0]}]
+set_output_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_width[1]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_width[1]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_addr0[0]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_addr0[0]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_addr0[1]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_addr0[1]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_addr0[2]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_addr0[2]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_addr0[3]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_addr0[3]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_addr0[4]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_addr0[4]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_addr0[5]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_addr0[5]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_addr0[6]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_addr0[6]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_addr0[7]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_addr0[7]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_addr0[8]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_addr0[8]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_addr1[0]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_addr1[0]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_addr1[1]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_addr1[1]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_addr1[2]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_addr1[2]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_addr1[3]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_addr1[3]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_addr1[4]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_addr1[4]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_addr1[5]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_addr1[5]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_addr1[6]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_addr1[6]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_addr1[7]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_addr1[7]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_addr1[8]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_addr1[8]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_csb0}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_csb0}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_csb1}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_csb1}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[0]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[0]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[10]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[10]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[11]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[11]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[12]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[12]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[13]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[13]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[14]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[14]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[15]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[15]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[16]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[16]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[17]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[17]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[18]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[18]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[19]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[19]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[1]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[1]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[20]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[20]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[21]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[21]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[22]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[22]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[23]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[23]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[24]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[24]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[25]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[25]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[26]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[26]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[27]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[27]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[28]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[28]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[29]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[29]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[2]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[2]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[30]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[30]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[31]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[31]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[3]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[3]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[4]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[4]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[5]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[5]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[6]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[6]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[7]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[7]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[8]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[8]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[9]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[9]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_web0}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_web0}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_wmask0[0]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_wmask0[0]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_wmask0[1]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_wmask0[1]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_wmask0[2]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_wmask0[2]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_wmask0[3]}]
+set_output_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_wmask0[3]}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {cfg_dcache_force_flush}]
+set_load -pin_load 0.0334 [get_ports {core0_clk}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_req_ack}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_req_ack}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_soft}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_irq}]
+set_load -pin_load 0.0334 [get_ports {core1_clk}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_req_ack}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_req_ack}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_soft}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_irq}]
+set_load -pin_load 0.0334 [get_ports {core2_clk}]
+set_load -pin_load 0.0334 [get_ports {core2_dmem_req_ack}]
+set_load -pin_load 0.0334 [get_ports {core2_imem_req_ack}]
+set_load -pin_load 0.0334 [get_ports {core2_irq_soft}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_irq}]
+set_load -pin_load 0.0334 [get_ports {core3_clk}]
+set_load -pin_load 0.0334 [get_ports {core3_dmem_req_ack}]
+set_load -pin_load 0.0334 [get_ports {core3_imem_req_ack}]
+set_load -pin_load 0.0334 [get_ports {core3_irq_soft}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_irq}]
+set_load -pin_load 0.0334 [get_ports {core_clk_skew}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_cmd}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_req}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_cmd}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_req}]
+set_load -pin_load 0.0334 [get_ports {core_icache_cmd}]
+set_load -pin_load 0.0334 [get_ports {core_icache_req}]
+set_load -pin_load 0.0334 [get_ports {sram0_clk0}]
+set_load -pin_load 0.0334 [get_ports {sram0_clk1}]
+set_load -pin_load 0.0334 [get_ports {sram0_csb0}]
+set_load -pin_load 0.0334 [get_ports {sram0_csb1}]
+set_load -pin_load 0.0334 [get_ports {sram0_web0}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[31]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[30]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[29]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[28]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[27]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[26]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[25]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[24]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[23]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[22]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[21]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[20]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[19]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[18]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[17]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[16]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[15]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[14]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[13]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[12]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[11]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[10]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[9]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[8]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[7]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[6]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[5]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[4]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[3]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[2]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[1]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[0]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_resp[1]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_resp[0]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[31]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[30]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[29]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[28]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[27]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[26]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[25]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[24]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[23]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[22]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[21]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[20]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[19]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[18]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[17]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[16]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[15]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[14]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[13]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[12]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[11]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[10]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[9]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[8]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[7]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[6]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[5]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[4]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[3]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[2]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[1]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[0]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_resp[1]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_resp[0]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[31]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[30]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[29]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[28]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[27]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[26]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[25]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[24]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[23]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[22]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[21]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[20]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[19]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[18]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[17]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[16]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[15]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[14]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[13]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[12]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[11]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[10]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[9]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[8]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[7]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[6]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[5]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[4]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[3]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[2]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[1]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[0]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[63]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[62]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[61]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[60]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[59]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[58]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[57]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[56]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[55]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[54]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[53]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[52]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[51]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[50]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[49]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[48]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[47]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[46]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[45]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[44]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[43]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[42]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[41]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[40]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[39]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[38]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[37]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[36]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[35]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[34]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[33]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[32]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[31]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[30]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[29]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[28]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[27]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[26]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[25]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[24]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[23]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[22]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[21]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[20]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[19]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[18]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[17]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[16]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[15]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[14]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[13]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[12]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[11]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[10]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[9]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[8]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[7]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[6]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[5]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[4]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[3]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[2]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[1]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[0]}]
+set_load -pin_load 0.0334 [get_ports {core0_uid[1]}]
+set_load -pin_load 0.0334 [get_ports {core0_uid[0]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[31]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[30]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[29]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[28]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[27]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[26]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[25]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[24]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[23]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[22]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[21]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[20]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[19]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[18]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[17]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[16]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[15]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[14]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[13]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[12]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[11]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[10]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[9]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[8]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[7]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[6]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[5]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[4]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[3]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[2]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[1]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[0]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_resp[1]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_resp[0]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[31]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[30]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[29]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[28]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[27]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[26]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[25]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[24]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[23]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[22]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[21]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[20]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[19]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[18]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[17]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[16]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[15]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[14]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[13]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[12]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[11]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[10]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[9]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[8]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[7]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[6]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[5]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[4]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[3]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[2]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[1]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[0]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_resp[1]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_resp[0]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[31]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[30]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[29]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[28]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[27]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[26]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[25]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[24]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[23]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[22]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[21]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[20]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[19]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[18]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[17]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[16]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[15]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[14]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[13]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[12]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[11]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[10]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[9]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[8]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[7]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[6]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[5]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[4]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[3]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[2]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[1]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[0]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[63]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[62]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[61]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[60]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[59]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[58]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[57]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[56]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[55]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[54]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[53]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[52]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[51]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[50]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[49]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[48]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[47]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[46]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[45]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[44]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[43]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[42]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[41]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[40]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[39]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[38]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[37]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[36]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[35]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[34]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[33]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[32]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[31]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[30]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[29]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[28]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[27]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[26]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[25]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[24]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[23]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[22]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[21]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[20]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[19]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[18]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[17]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[16]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[15]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[14]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[13]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[12]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[11]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[10]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[9]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[8]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[7]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[6]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[5]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[4]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[3]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[2]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[1]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[0]}]
+set_load -pin_load 0.0334 [get_ports {core1_uid[1]}]
+set_load -pin_load 0.0334 [get_ports {core1_uid[0]}]
+set_load -pin_load 0.0334 [get_ports {core2_dmem_rdata[31]}]
+set_load -pin_load 0.0334 [get_ports {core2_dmem_rdata[30]}]
+set_load -pin_load 0.0334 [get_ports {core2_dmem_rdata[29]}]
+set_load -pin_load 0.0334 [get_ports {core2_dmem_rdata[28]}]
+set_load -pin_load 0.0334 [get_ports {core2_dmem_rdata[27]}]
+set_load -pin_load 0.0334 [get_ports {core2_dmem_rdata[26]}]
+set_load -pin_load 0.0334 [get_ports {core2_dmem_rdata[25]}]
+set_load -pin_load 0.0334 [get_ports {core2_dmem_rdata[24]}]
+set_load -pin_load 0.0334 [get_ports {core2_dmem_rdata[23]}]
+set_load -pin_load 0.0334 [get_ports {core2_dmem_rdata[22]}]
+set_load -pin_load 0.0334 [get_ports {core2_dmem_rdata[21]}]
+set_load -pin_load 0.0334 [get_ports {core2_dmem_rdata[20]}]
+set_load -pin_load 0.0334 [get_ports {core2_dmem_rdata[19]}]
+set_load -pin_load 0.0334 [get_ports {core2_dmem_rdata[18]}]
+set_load -pin_load 0.0334 [get_ports {core2_dmem_rdata[17]}]
+set_load -pin_load 0.0334 [get_ports {core2_dmem_rdata[16]}]
+set_load -pin_load 0.0334 [get_ports {core2_dmem_rdata[15]}]
+set_load -pin_load 0.0334 [get_ports {core2_dmem_rdata[14]}]
+set_load -pin_load 0.0334 [get_ports {core2_dmem_rdata[13]}]
+set_load -pin_load 0.0334 [get_ports {core2_dmem_rdata[12]}]
+set_load -pin_load 0.0334 [get_ports {core2_dmem_rdata[11]}]
+set_load -pin_load 0.0334 [get_ports {core2_dmem_rdata[10]}]
+set_load -pin_load 0.0334 [get_ports {core2_dmem_rdata[9]}]
+set_load -pin_load 0.0334 [get_ports {core2_dmem_rdata[8]}]
+set_load -pin_load 0.0334 [get_ports {core2_dmem_rdata[7]}]
+set_load -pin_load 0.0334 [get_ports {core2_dmem_rdata[6]}]
+set_load -pin_load 0.0334 [get_ports {core2_dmem_rdata[5]}]
+set_load -pin_load 0.0334 [get_ports {core2_dmem_rdata[4]}]
+set_load -pin_load 0.0334 [get_ports {core2_dmem_rdata[3]}]
+set_load -pin_load 0.0334 [get_ports {core2_dmem_rdata[2]}]
+set_load -pin_load 0.0334 [get_ports {core2_dmem_rdata[1]}]
+set_load -pin_load 0.0334 [get_ports {core2_dmem_rdata[0]}]
+set_load -pin_load 0.0334 [get_ports {core2_dmem_resp[1]}]
+set_load -pin_load 0.0334 [get_ports {core2_dmem_resp[0]}]
+set_load -pin_load 0.0334 [get_ports {core2_imem_rdata[31]}]
+set_load -pin_load 0.0334 [get_ports {core2_imem_rdata[30]}]
+set_load -pin_load 0.0334 [get_ports {core2_imem_rdata[29]}]
+set_load -pin_load 0.0334 [get_ports {core2_imem_rdata[28]}]
+set_load -pin_load 0.0334 [get_ports {core2_imem_rdata[27]}]
+set_load -pin_load 0.0334 [get_ports {core2_imem_rdata[26]}]
+set_load -pin_load 0.0334 [get_ports {core2_imem_rdata[25]}]
+set_load -pin_load 0.0334 [get_ports {core2_imem_rdata[24]}]
+set_load -pin_load 0.0334 [get_ports {core2_imem_rdata[23]}]
+set_load -pin_load 0.0334 [get_ports {core2_imem_rdata[22]}]
+set_load -pin_load 0.0334 [get_ports {core2_imem_rdata[21]}]
+set_load -pin_load 0.0334 [get_ports {core2_imem_rdata[20]}]
+set_load -pin_load 0.0334 [get_ports {core2_imem_rdata[19]}]
+set_load -pin_load 0.0334 [get_ports {core2_imem_rdata[18]}]
+set_load -pin_load 0.0334 [get_ports {core2_imem_rdata[17]}]
+set_load -pin_load 0.0334 [get_ports {core2_imem_rdata[16]}]
+set_load -pin_load 0.0334 [get_ports {core2_imem_rdata[15]}]
+set_load -pin_load 0.0334 [get_ports {core2_imem_rdata[14]}]
+set_load -pin_load 0.0334 [get_ports {core2_imem_rdata[13]}]
+set_load -pin_load 0.0334 [get_ports {core2_imem_rdata[12]}]
+set_load -pin_load 0.0334 [get_ports {core2_imem_rdata[11]}]
+set_load -pin_load 0.0334 [get_ports {core2_imem_rdata[10]}]
+set_load -pin_load 0.0334 [get_ports {core2_imem_rdata[9]}]
+set_load -pin_load 0.0334 [get_ports {core2_imem_rdata[8]}]
+set_load -pin_load 0.0334 [get_ports {core2_imem_rdata[7]}]
+set_load -pin_load 0.0334 [get_ports {core2_imem_rdata[6]}]
+set_load -pin_load 0.0334 [get_ports {core2_imem_rdata[5]}]
+set_load -pin_load 0.0334 [get_ports {core2_imem_rdata[4]}]
+set_load -pin_load 0.0334 [get_ports {core2_imem_rdata[3]}]
+set_load -pin_load 0.0334 [get_ports {core2_imem_rdata[2]}]
+set_load -pin_load 0.0334 [get_ports {core2_imem_rdata[1]}]
+set_load -pin_load 0.0334 [get_ports {core2_imem_rdata[0]}]
+set_load -pin_load 0.0334 [get_ports {core2_imem_resp[1]}]
+set_load -pin_load 0.0334 [get_ports {core2_imem_resp[0]}]
+set_load -pin_load 0.0334 [get_ports {core2_irq_lines[31]}]
+set_load -pin_load 0.0334 [get_ports {core2_irq_lines[30]}]
+set_load -pin_load 0.0334 [get_ports {core2_irq_lines[29]}]
+set_load -pin_load 0.0334 [get_ports {core2_irq_lines[28]}]
+set_load -pin_load 0.0334 [get_ports {core2_irq_lines[27]}]
+set_load -pin_load 0.0334 [get_ports {core2_irq_lines[26]}]
+set_load -pin_load 0.0334 [get_ports {core2_irq_lines[25]}]
+set_load -pin_load 0.0334 [get_ports {core2_irq_lines[24]}]
+set_load -pin_load 0.0334 [get_ports {core2_irq_lines[23]}]
+set_load -pin_load 0.0334 [get_ports {core2_irq_lines[22]}]
+set_load -pin_load 0.0334 [get_ports {core2_irq_lines[21]}]
+set_load -pin_load 0.0334 [get_ports {core2_irq_lines[20]}]
+set_load -pin_load 0.0334 [get_ports {core2_irq_lines[19]}]
+set_load -pin_load 0.0334 [get_ports {core2_irq_lines[18]}]
+set_load -pin_load 0.0334 [get_ports {core2_irq_lines[17]}]
+set_load -pin_load 0.0334 [get_ports {core2_irq_lines[16]}]
+set_load -pin_load 0.0334 [get_ports {core2_irq_lines[15]}]
+set_load -pin_load 0.0334 [get_ports {core2_irq_lines[14]}]
+set_load -pin_load 0.0334 [get_ports {core2_irq_lines[13]}]
+set_load -pin_load 0.0334 [get_ports {core2_irq_lines[12]}]
+set_load -pin_load 0.0334 [get_ports {core2_irq_lines[11]}]
+set_load -pin_load 0.0334 [get_ports {core2_irq_lines[10]}]
+set_load -pin_load 0.0334 [get_ports {core2_irq_lines[9]}]
+set_load -pin_load 0.0334 [get_ports {core2_irq_lines[8]}]
+set_load -pin_load 0.0334 [get_ports {core2_irq_lines[7]}]
+set_load -pin_load 0.0334 [get_ports {core2_irq_lines[6]}]
+set_load -pin_load 0.0334 [get_ports {core2_irq_lines[5]}]
+set_load -pin_load 0.0334 [get_ports {core2_irq_lines[4]}]
+set_load -pin_load 0.0334 [get_ports {core2_irq_lines[3]}]
+set_load -pin_load 0.0334 [get_ports {core2_irq_lines[2]}]
+set_load -pin_load 0.0334 [get_ports {core2_irq_lines[1]}]
+set_load -pin_load 0.0334 [get_ports {core2_irq_lines[0]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[63]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[62]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[61]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[60]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[59]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[58]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[57]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[56]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[55]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[54]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[53]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[52]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[51]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[50]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[49]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[48]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[47]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[46]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[45]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[44]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[43]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[42]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[41]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[40]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[39]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[38]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[37]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[36]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[35]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[34]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[33]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[32]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[31]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[30]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[29]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[28]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[27]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[26]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[25]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[24]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[23]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[22]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[21]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[20]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[19]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[18]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[17]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[16]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[15]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[14]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[13]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[12]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[11]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[10]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[9]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[8]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[7]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[6]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[5]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[4]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[3]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[2]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[1]}]
+set_load -pin_load 0.0334 [get_ports {core2_timer_val[0]}]
+set_load -pin_load 0.0334 [get_ports {core2_uid[1]}]
+set_load -pin_load 0.0334 [get_ports {core2_uid[0]}]
+set_load -pin_load 0.0334 [get_ports {core3_dmem_rdata[31]}]
+set_load -pin_load 0.0334 [get_ports {core3_dmem_rdata[30]}]
+set_load -pin_load 0.0334 [get_ports {core3_dmem_rdata[29]}]
+set_load -pin_load 0.0334 [get_ports {core3_dmem_rdata[28]}]
+set_load -pin_load 0.0334 [get_ports {core3_dmem_rdata[27]}]
+set_load -pin_load 0.0334 [get_ports {core3_dmem_rdata[26]}]
+set_load -pin_load 0.0334 [get_ports {core3_dmem_rdata[25]}]
+set_load -pin_load 0.0334 [get_ports {core3_dmem_rdata[24]}]
+set_load -pin_load 0.0334 [get_ports {core3_dmem_rdata[23]}]
+set_load -pin_load 0.0334 [get_ports {core3_dmem_rdata[22]}]
+set_load -pin_load 0.0334 [get_ports {core3_dmem_rdata[21]}]
+set_load -pin_load 0.0334 [get_ports {core3_dmem_rdata[20]}]
+set_load -pin_load 0.0334 [get_ports {core3_dmem_rdata[19]}]
+set_load -pin_load 0.0334 [get_ports {core3_dmem_rdata[18]}]
+set_load -pin_load 0.0334 [get_ports {core3_dmem_rdata[17]}]
+set_load -pin_load 0.0334 [get_ports {core3_dmem_rdata[16]}]
+set_load -pin_load 0.0334 [get_ports {core3_dmem_rdata[15]}]
+set_load -pin_load 0.0334 [get_ports {core3_dmem_rdata[14]}]
+set_load -pin_load 0.0334 [get_ports {core3_dmem_rdata[13]}]
+set_load -pin_load 0.0334 [get_ports {core3_dmem_rdata[12]}]
+set_load -pin_load 0.0334 [get_ports {core3_dmem_rdata[11]}]
+set_load -pin_load 0.0334 [get_ports {core3_dmem_rdata[10]}]
+set_load -pin_load 0.0334 [get_ports {core3_dmem_rdata[9]}]
+set_load -pin_load 0.0334 [get_ports {core3_dmem_rdata[8]}]
+set_load -pin_load 0.0334 [get_ports {core3_dmem_rdata[7]}]
+set_load -pin_load 0.0334 [get_ports {core3_dmem_rdata[6]}]
+set_load -pin_load 0.0334 [get_ports {core3_dmem_rdata[5]}]
+set_load -pin_load 0.0334 [get_ports {core3_dmem_rdata[4]}]
+set_load -pin_load 0.0334 [get_ports {core3_dmem_rdata[3]}]
+set_load -pin_load 0.0334 [get_ports {core3_dmem_rdata[2]}]
+set_load -pin_load 0.0334 [get_ports {core3_dmem_rdata[1]}]
+set_load -pin_load 0.0334 [get_ports {core3_dmem_rdata[0]}]
+set_load -pin_load 0.0334 [get_ports {core3_dmem_resp[1]}]
+set_load -pin_load 0.0334 [get_ports {core3_dmem_resp[0]}]
+set_load -pin_load 0.0334 [get_ports {core3_imem_rdata[31]}]
+set_load -pin_load 0.0334 [get_ports {core3_imem_rdata[30]}]
+set_load -pin_load 0.0334 [get_ports {core3_imem_rdata[29]}]
+set_load -pin_load 0.0334 [get_ports {core3_imem_rdata[28]}]
+set_load -pin_load 0.0334 [get_ports {core3_imem_rdata[27]}]
+set_load -pin_load 0.0334 [get_ports {core3_imem_rdata[26]}]
+set_load -pin_load 0.0334 [get_ports {core3_imem_rdata[25]}]
+set_load -pin_load 0.0334 [get_ports {core3_imem_rdata[24]}]
+set_load -pin_load 0.0334 [get_ports {core3_imem_rdata[23]}]
+set_load -pin_load 0.0334 [get_ports {core3_imem_rdata[22]}]
+set_load -pin_load 0.0334 [get_ports {core3_imem_rdata[21]}]
+set_load -pin_load 0.0334 [get_ports {core3_imem_rdata[20]}]
+set_load -pin_load 0.0334 [get_ports {core3_imem_rdata[19]}]
+set_load -pin_load 0.0334 [get_ports {core3_imem_rdata[18]}]
+set_load -pin_load 0.0334 [get_ports {core3_imem_rdata[17]}]
+set_load -pin_load 0.0334 [get_ports {core3_imem_rdata[16]}]
+set_load -pin_load 0.0334 [get_ports {core3_imem_rdata[15]}]
+set_load -pin_load 0.0334 [get_ports {core3_imem_rdata[14]}]
+set_load -pin_load 0.0334 [get_ports {core3_imem_rdata[13]}]
+set_load -pin_load 0.0334 [get_ports {core3_imem_rdata[12]}]
+set_load -pin_load 0.0334 [get_ports {core3_imem_rdata[11]}]
+set_load -pin_load 0.0334 [get_ports {core3_imem_rdata[10]}]
+set_load -pin_load 0.0334 [get_ports {core3_imem_rdata[9]}]
+set_load -pin_load 0.0334 [get_ports {core3_imem_rdata[8]}]
+set_load -pin_load 0.0334 [get_ports {core3_imem_rdata[7]}]
+set_load -pin_load 0.0334 [get_ports {core3_imem_rdata[6]}]
+set_load -pin_load 0.0334 [get_ports {core3_imem_rdata[5]}]
+set_load -pin_load 0.0334 [get_ports {core3_imem_rdata[4]}]
+set_load -pin_load 0.0334 [get_ports {core3_imem_rdata[3]}]
+set_load -pin_load 0.0334 [get_ports {core3_imem_rdata[2]}]
+set_load -pin_load 0.0334 [get_ports {core3_imem_rdata[1]}]
+set_load -pin_load 0.0334 [get_ports {core3_imem_rdata[0]}]
+set_load -pin_load 0.0334 [get_ports {core3_imem_resp[1]}]
+set_load -pin_load 0.0334 [get_ports {core3_imem_resp[0]}]
+set_load -pin_load 0.0334 [get_ports {core3_irq_lines[31]}]
+set_load -pin_load 0.0334 [get_ports {core3_irq_lines[30]}]
+set_load -pin_load 0.0334 [get_ports {core3_irq_lines[29]}]
+set_load -pin_load 0.0334 [get_ports {core3_irq_lines[28]}]
+set_load -pin_load 0.0334 [get_ports {core3_irq_lines[27]}]
+set_load -pin_load 0.0334 [get_ports {core3_irq_lines[26]}]
+set_load -pin_load 0.0334 [get_ports {core3_irq_lines[25]}]
+set_load -pin_load 0.0334 [get_ports {core3_irq_lines[24]}]
+set_load -pin_load 0.0334 [get_ports {core3_irq_lines[23]}]
+set_load -pin_load 0.0334 [get_ports {core3_irq_lines[22]}]
+set_load -pin_load 0.0334 [get_ports {core3_irq_lines[21]}]
+set_load -pin_load 0.0334 [get_ports {core3_irq_lines[20]}]
+set_load -pin_load 0.0334 [get_ports {core3_irq_lines[19]}]
+set_load -pin_load 0.0334 [get_ports {core3_irq_lines[18]}]
+set_load -pin_load 0.0334 [get_ports {core3_irq_lines[17]}]
+set_load -pin_load 0.0334 [get_ports {core3_irq_lines[16]}]
+set_load -pin_load 0.0334 [get_ports {core3_irq_lines[15]}]
+set_load -pin_load 0.0334 [get_ports {core3_irq_lines[14]}]
+set_load -pin_load 0.0334 [get_ports {core3_irq_lines[13]}]
+set_load -pin_load 0.0334 [get_ports {core3_irq_lines[12]}]
+set_load -pin_load 0.0334 [get_ports {core3_irq_lines[11]}]
+set_load -pin_load 0.0334 [get_ports {core3_irq_lines[10]}]
+set_load -pin_load 0.0334 [get_ports {core3_irq_lines[9]}]
+set_load -pin_load 0.0334 [get_ports {core3_irq_lines[8]}]
+set_load -pin_load 0.0334 [get_ports {core3_irq_lines[7]}]
+set_load -pin_load 0.0334 [get_ports {core3_irq_lines[6]}]
+set_load -pin_load 0.0334 [get_ports {core3_irq_lines[5]}]
+set_load -pin_load 0.0334 [get_ports {core3_irq_lines[4]}]
+set_load -pin_load 0.0334 [get_ports {core3_irq_lines[3]}]
+set_load -pin_load 0.0334 [get_ports {core3_irq_lines[2]}]
+set_load -pin_load 0.0334 [get_ports {core3_irq_lines[1]}]
+set_load -pin_load 0.0334 [get_ports {core3_irq_lines[0]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[63]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[62]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[61]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[60]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[59]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[58]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[57]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[56]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[55]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[54]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[53]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[52]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[51]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[50]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[49]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[48]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[47]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[46]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[45]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[44]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[43]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[42]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[41]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[40]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[39]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[38]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[37]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[36]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[35]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[34]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[33]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[32]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[31]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[30]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[29]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[28]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[27]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[26]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[25]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[24]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[23]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[22]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[21]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[20]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[19]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[18]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[17]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[16]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[15]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[14]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[13]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[12]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[11]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[10]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[9]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[8]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[7]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[6]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[5]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[4]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[3]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[2]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[1]}]
+set_load -pin_load 0.0334 [get_ports {core3_timer_val[0]}]
+set_load -pin_load 0.0334 [get_ports {core3_uid[1]}]
+set_load -pin_load 0.0334 [get_ports {core3_uid[0]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[31]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[30]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[29]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[28]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[27]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[26]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[25]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[24]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[23]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[22]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[21]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[20]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[19]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[18]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[17]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[16]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[15]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[14]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[13]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[12]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[11]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[10]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[9]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[8]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[7]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[6]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[5]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[4]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[3]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[2]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[1]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[0]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[31]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[30]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[29]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[28]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[27]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[26]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[25]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[24]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[23]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[22]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[21]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[20]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[19]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[18]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[17]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[16]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[15]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[14]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[13]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[12]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[11]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[10]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[9]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[8]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[7]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[6]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[5]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[4]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[3]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[2]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[1]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[0]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_width[1]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_width[0]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[31]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[30]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[29]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[28]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[27]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[26]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[25]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[24]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[23]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[22]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[21]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[20]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[19]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[18]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[17]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[16]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[15]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[14]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[13]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[12]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[11]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[10]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[9]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[8]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[7]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[6]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[5]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[4]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[3]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[2]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[1]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[0]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_bl[2]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_bl[1]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_bl[0]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[31]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[30]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[29]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[28]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[27]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[26]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[25]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[24]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[23]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[22]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[21]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[20]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[19]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[18]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[17]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[16]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[15]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[14]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[13]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[12]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[11]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[10]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[9]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[8]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[7]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[6]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[5]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[4]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[3]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[2]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[1]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[0]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_width[1]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_width[0]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[31]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[30]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[29]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[28]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[27]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[26]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[25]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[24]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[23]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[22]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[21]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[20]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[19]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[18]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[17]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[16]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[15]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[14]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[13]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[12]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[11]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[10]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[9]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[8]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[7]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[6]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[5]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[4]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[3]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[2]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[1]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[0]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_bl[2]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_bl[1]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_bl[0]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_width[1]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_width[0]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[63]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[62]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[61]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[60]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[59]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[58]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[57]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[56]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[55]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[54]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[53]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[52]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[51]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[50]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[49]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[48]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[47]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[46]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[45]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[44]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[43]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[42]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[41]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[40]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[39]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[38]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[37]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[36]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[35]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[34]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[33]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[32]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[31]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[30]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[29]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[28]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[27]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[26]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[25]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[24]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[23]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[22]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[21]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[20]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[19]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[18]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[17]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[16]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[15]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[14]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[13]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[12]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[11]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[10]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[9]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[8]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[7]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[6]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[5]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[4]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[3]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[2]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[1]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[0]}]
+set_load -pin_load 0.0334 [get_ports {sram0_addr0[8]}]
+set_load -pin_load 0.0334 [get_ports {sram0_addr0[7]}]
+set_load -pin_load 0.0334 [get_ports {sram0_addr0[6]}]
+set_load -pin_load 0.0334 [get_ports {sram0_addr0[5]}]
+set_load -pin_load 0.0334 [get_ports {sram0_addr0[4]}]
+set_load -pin_load 0.0334 [get_ports {sram0_addr0[3]}]
+set_load -pin_load 0.0334 [get_ports {sram0_addr0[2]}]
+set_load -pin_load 0.0334 [get_ports {sram0_addr0[1]}]
+set_load -pin_load 0.0334 [get_ports {sram0_addr0[0]}]
+set_load -pin_load 0.0334 [get_ports {sram0_addr1[8]}]
+set_load -pin_load 0.0334 [get_ports {sram0_addr1[7]}]
+set_load -pin_load 0.0334 [get_ports {sram0_addr1[6]}]
+set_load -pin_load 0.0334 [get_ports {sram0_addr1[5]}]
+set_load -pin_load 0.0334 [get_ports {sram0_addr1[4]}]
+set_load -pin_load 0.0334 [get_ports {sram0_addr1[3]}]
+set_load -pin_load 0.0334 [get_ports {sram0_addr1[2]}]
+set_load -pin_load 0.0334 [get_ports {sram0_addr1[1]}]
+set_load -pin_load 0.0334 [get_ports {sram0_addr1[0]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[31]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[30]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[29]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[28]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[27]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[26]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[25]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[24]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[23]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[22]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[21]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[20]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[19]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[18]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[17]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[16]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[15]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[14]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[13]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[12]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[11]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[10]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[9]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[8]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[7]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[6]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[5]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[4]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[3]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[2]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[1]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[0]}]
+set_load -pin_load 0.0334 [get_ports {sram0_wmask0[3]}]
+set_load -pin_load 0.0334 [get_ports {sram0_wmask0[2]}]
+set_load -pin_load 0.0334 [get_ports {sram0_wmask0[1]}]
+set_load -pin_load 0.0334 [get_ports {sram0_wmask0[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_bypass_dcache}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_bypass_icache}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_cmd}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_req}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_cmd}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_req}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_cmd}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_req}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_cmd}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_req}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_cmd}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_req}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_imem_cmd}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_imem_req}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_cmd}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_req}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_imem_cmd}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_imem_req}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_clk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_req_ack}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_req_ack}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_req_ack}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_soft_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cpu_intf_rst_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {pwrup_rst_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rtc_clk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_ccska[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_ccska[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_ccska[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_ccska[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sram_lphase[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sram_lphase[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[48]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[47]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[46]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[45]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[44]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[43]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[42]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[41]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[40]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[39]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[38]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_width[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_width[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_bl[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_bl[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_bl[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[48]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[47]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[46]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[45]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[44]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[43]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[42]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[41]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[40]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[39]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[38]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_width[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_width[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_bl[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_bl[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_bl[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[48]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[47]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[46]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[45]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[44]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[43]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[42]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[41]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[40]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[39]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[38]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_debug[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_addr[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_addr[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_addr[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_addr[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_addr[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_addr[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_addr[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_addr[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_addr[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_addr[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_addr[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_addr[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_addr[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_addr[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_addr[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_addr[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_addr[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_addr[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_addr[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_addr[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_addr[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_addr[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_addr[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_addr[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_addr[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_addr[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_addr[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_addr[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_addr[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_addr[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_addr[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_addr[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_wdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_wdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_wdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_wdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_wdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_wdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_wdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_wdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_wdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_wdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_wdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_wdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_wdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_wdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_wdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_wdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_wdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_wdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_wdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_wdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_wdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_wdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_wdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_wdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_wdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_wdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_wdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_wdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_wdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_wdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_wdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_wdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_width[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_dmem_width[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_imem_addr[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_imem_addr[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_imem_addr[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_imem_addr[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_imem_addr[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_imem_addr[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_imem_addr[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_imem_addr[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_imem_addr[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_imem_addr[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_imem_addr[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_imem_addr[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_imem_addr[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_imem_addr[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_imem_addr[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_imem_addr[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_imem_addr[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_imem_addr[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_imem_addr[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_imem_addr[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_imem_addr[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_imem_addr[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_imem_addr[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_imem_addr[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_imem_addr[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_imem_addr[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_imem_addr[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_imem_addr[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_imem_addr[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_imem_addr[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_imem_addr[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_imem_addr[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_imem_bl[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_imem_bl[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core2_imem_bl[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[48]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[47]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[46]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[45]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[44]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[43]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[42]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[41]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[40]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[39]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[38]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_debug[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_addr[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_addr[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_addr[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_addr[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_addr[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_addr[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_addr[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_addr[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_addr[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_addr[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_addr[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_addr[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_addr[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_addr[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_addr[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_addr[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_addr[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_addr[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_addr[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_addr[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_addr[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_addr[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_addr[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_addr[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_addr[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_addr[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_addr[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_addr[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_addr[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_addr[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_addr[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_addr[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_wdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_wdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_wdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_wdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_wdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_wdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_wdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_wdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_wdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_wdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_wdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_wdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_wdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_wdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_wdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_wdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_wdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_wdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_wdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_wdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_wdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_wdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_wdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_wdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_wdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_wdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_wdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_wdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_wdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_wdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_wdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_wdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_width[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_dmem_width[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_imem_addr[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_imem_addr[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_imem_addr[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_imem_addr[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_imem_addr[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_imem_addr[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_imem_addr[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_imem_addr[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_imem_addr[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_imem_addr[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_imem_addr[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_imem_addr[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_imem_addr[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_imem_addr[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_imem_addr[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_imem_addr[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_imem_addr[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_imem_addr[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_imem_addr[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_imem_addr[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_imem_addr[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_imem_addr[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_imem_addr[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_imem_addr[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_imem_addr[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_imem_addr[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_imem_addr[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_imem_addr[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_imem_addr[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_imem_addr[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_imem_addr[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_imem_addr[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_imem_bl[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_imem_bl[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core3_imem_bl[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_resp[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_resp[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_debug_sel[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_debug_sel[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_resp[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_resp[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_resp[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_resp[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[0]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_transition 1.0000 [current_design]
+set_max_capacitance 0.2000 [current_design]
+set_max_fanout 10.0000 [current_design]
diff --git a/sdc/ycr_core_top.sdc b/sdc/ycr_core_top.sdc
new file mode 100644
index 0000000..8de6607
--- /dev/null
+++ b/sdc/ycr_core_top.sdc
@@ -0,0 +1,711 @@
+###############################################################################
+# Created by write_sdc
+# Wed Nov 30 14:16:33 2022
+###############################################################################
+current_design ycr_core_top
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name core_clk -period 10.0000 [get_ports {clk}]
+set_clock_transition 0.1500 [get_clocks {core_clk}]
+set_clock_uncertainty -setup 0.5000 core_clk
+set_clock_uncertainty -hold 0.2500 core_clk
+set_propagated_clock [get_clocks {core_clk}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[0]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[10]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[10]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[11]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[11]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[12]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[12]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[13]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[13]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[14]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[14]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[15]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[15]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[16]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[16]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[17]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[17]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[18]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[18]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[19]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[19]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[1]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[20]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[20]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[21]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[21]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[22]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[22]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[23]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[23]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[24]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[24]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[25]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[25]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[26]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[26]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[27]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[27]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[28]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[28]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[29]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[29]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[2]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[30]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[30]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[31]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[31]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[3]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[4]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[4]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[5]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[5]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[6]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[6]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[7]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[7]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[8]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[8]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[9]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[9]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_req_ack_i}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_req_ack_i}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_resp_i[0]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_resp_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_resp_i[1]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_resp_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[0]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[10]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[10]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[11]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[11]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[12]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[12]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[13]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[13]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[14]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[14]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[15]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[15]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[16]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[16]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[17]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[17]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[18]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[18]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[19]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[19]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[1]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[20]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[20]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[21]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[21]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[22]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[22]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[23]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[23]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[24]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[24]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[25]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[25]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[26]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[26]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[27]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[27]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[28]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[28]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[29]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[29]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[2]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[30]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[30]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[31]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[31]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[3]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[4]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[4]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[5]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[5]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[6]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[6]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[7]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[7]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[8]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[8]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[9]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[9]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_req_ack_i}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_req_ack_i}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_resp_i[0]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_resp_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_resp_i[1]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_resp_i[1]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[0]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[10]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[10]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[11]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[11]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[12]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[12]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[13]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[13]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[14]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[14]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[15]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[15]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[16]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[16]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[17]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[17]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[18]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[18]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[19]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[19]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[1]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[20]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[20]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[21]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[21]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[22]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[22]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[23]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[23]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[24]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[24]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[25]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[25]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[26]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[26]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[27]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[27]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[28]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[28]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[29]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[29]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[2]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[30]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[30]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[31]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[31]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[3]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[4]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[4]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[5]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[5]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[6]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[6]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[7]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[7]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[8]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[8]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[9]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[9]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_cmd_o}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_cmd_o}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_req_o}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_req_o}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[0]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[10]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[10]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[11]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[11]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[12]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[12]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[13]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[13]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[14]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[14]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[15]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[15]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[16]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[16]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[17]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[17]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[18]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[18]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[19]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[19]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[1]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[20]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[20]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[21]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[21]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[22]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[22]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[23]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[23]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[24]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[24]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[25]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[25]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[26]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[26]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[27]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[27]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[28]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[28]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[29]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[29]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[2]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[30]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[30]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[31]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[31]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[3]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[4]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[4]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[5]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[5]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[6]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[6]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[7]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[7]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[8]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[8]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[9]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[9]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_width_o[0]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_width_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_width_o[1]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_width_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[0]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[10]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[10]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[11]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[11]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[12]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[12]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[13]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[13]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[14]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[14]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[15]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[15]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[16]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[16]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[17]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[17]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[18]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[18]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[19]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[19]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[1]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[20]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[20]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[21]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[21]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[22]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[22]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[23]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[23]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[24]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[24]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[25]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[25]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[26]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[26]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[27]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[27]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[28]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[28]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[29]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[29]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[2]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[30]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[30]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[31]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[31]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[3]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[4]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[4]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[5]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[5]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[6]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[6]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[7]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[7]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[8]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[8]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[9]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[9]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_bl_o[0]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_bl_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_bl_o[1]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_bl_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_bl_o[2]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_bl_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_cmd_o}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_cmd_o}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_req_o}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_req_o}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {clk_o}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_cmd_o}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_req_o}]
+set_load -pin_load 0.0334 [get_ports {core2imem_cmd_o}]
+set_load -pin_load 0.0334 [get_ports {core2imem_req_o}]
+set_load -pin_load 0.0334 [get_ports {core_clk_skew}]
+set_load -pin_load 0.0334 [get_ports {core_rdc_qlfy_o}]
+set_load -pin_load 0.0334 [get_ports {core_rst_n_o}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[31]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[30]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[29]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[28]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[27]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[26]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[25]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[24]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[23]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[22]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[21]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[20]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[19]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[18]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[17]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[16]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[15]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[14]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[13]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[12]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[11]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[10]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[9]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[8]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[7]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[6]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[5]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[4]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[3]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[2]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[1]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[0]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[31]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[30]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[29]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[28]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[27]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[26]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[25]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[24]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[23]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[22]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[21]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[20]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[19]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[18]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[17]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[16]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[15]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[14]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[13]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[12]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[11]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[10]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[9]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[8]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[7]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[6]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[5]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[4]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[3]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[2]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[1]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[0]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_width_o[1]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_width_o[0]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[31]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[30]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[29]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[28]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[27]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[26]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[25]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[24]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[23]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[22]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[21]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[20]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[19]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[18]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[17]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[16]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[15]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[14]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[13]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[12]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[11]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[10]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[9]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[8]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[7]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[6]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[5]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[4]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[3]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[2]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[1]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[0]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_bl_o[2]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_bl_o[1]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_bl_o[0]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[48]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[47]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[46]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[45]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[44]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[43]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[42]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[41]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[40]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[39]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[38]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[37]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[36]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[35]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[34]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[33]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[32]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[31]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[30]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[29]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[28]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[27]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[26]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[25]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[24]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[23]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[22]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[21]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[20]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[19]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[18]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[17]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[16]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[15]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[14]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[13]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[12]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[11]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[10]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[9]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[8]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[7]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[6]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[5]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[4]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[3]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[2]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[1]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {clk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_mtimer_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_soft_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cpu_rst_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_req_ack_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_req_ack_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {pwrup_rst_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_ccska[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_ccska[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_ccska[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_ccska[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[63]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[62]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[61]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[60]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[59]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[58]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[57]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[56]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[55]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[54]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[53]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[52]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[51]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[50]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[49]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[48]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[47]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[46]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[45]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[44]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[43]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[42]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[41]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[40]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[39]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[38]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_uid[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_uid[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_resp_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_resp_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_resp_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_resp_i[0]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_transition 1.0000 [current_design]
+set_max_capacitance 0.2000 [current_design]
+set_max_fanout 10.0000 [current_design]
diff --git a/sdc/ycr_intf.sdc b/sdc/ycr_intf.sdc
new file mode 100644
index 0000000..1decbbe
--- /dev/null
+++ b/sdc/ycr_intf.sdc
@@ -0,0 +1,2494 @@
+###############################################################################
+# Created by write_sdc
+# Thu Dec 1 02:18:56 2022
+###############################################################################
+current_design ycr_intf
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name core_clk -period 10.0000 [get_ports {core_clk}]
+set_clock_transition 0.1500 [get_clocks {core_clk}]
+set_clock_uncertainty -setup 0.5000 core_clk
+set_clock_uncertainty -hold 0.2500 core_clk
+set_propagated_clock [get_clocks {core_clk}]
+create_clock -name rtc_clk -period 40.0000
+set_clock_uncertainty -setup 0.5000 rtc_clk
+set_clock_uncertainty -hold 0.2500 rtc_clk
+create_clock -name wb_clk -period 10.0000 [get_ports {wb_clk}]
+set_clock_transition 0.1500 [get_clocks {wb_clk}]
+set_clock_uncertainty -setup 0.5000 wb_clk
+set_clock_uncertainty -hold 0.2500 wb_clk
+set_propagated_clock [get_clocks {wb_clk}]
+create_generated_clock -name dcache_mem_clk0 -add -source [get_ports {core_clk}] -master_clock [get_clocks {core_clk}] -divide_by 1 -comment {dcache mem clock0} [get_ports {dcache_mem_clk0}]
+set_clock_transition 0.1500 [get_clocks {dcache_mem_clk0}]
+set_clock_uncertainty -setup 0.5000 dcache_mem_clk0
+set_clock_uncertainty -hold 0.2500 dcache_mem_clk0
+set_propagated_clock [get_clocks {dcache_mem_clk0}]
+create_generated_clock -name dcache_mem_clk1 -add -source [get_ports {core_clk}] -master_clock [get_clocks {core_clk}] -divide_by 1 -comment {dcache mem clock1} [get_ports {dcache_mem_clk1}]
+set_clock_transition 0.1500 [get_clocks {dcache_mem_clk1}]
+set_clock_uncertainty -setup 0.5000 dcache_mem_clk1
+set_clock_uncertainty -hold 0.2500 dcache_mem_clk1
+set_propagated_clock [get_clocks {dcache_mem_clk1}]
+create_generated_clock -name icache_mem_clk0 -add -source [get_ports {core_clk}] -master_clock [get_clocks {core_clk}] -divide_by 1 -comment {icache mem clock0} [get_ports {icache_mem_clk0}]
+set_clock_transition 0.1500 [get_clocks {icache_mem_clk0}]
+set_clock_uncertainty -setup 0.5000 icache_mem_clk0
+set_clock_uncertainty -hold 0.2500 icache_mem_clk0
+set_propagated_clock [get_clocks {icache_mem_clk0}]
+create_generated_clock -name icache_mem_clk1 -add -source [get_ports {core_clk}] -master_clock [get_clocks {core_clk}] -divide_by 1 -comment {icache mem clock1} [get_ports {icache_mem_clk1}]
+set_clock_transition 0.1500 [get_clocks {icache_mem_clk1}]
+set_clock_uncertainty -setup 0.5000 icache_mem_clk1
+set_clock_uncertainty -hold 0.2500 icache_mem_clk1
+set_propagated_clock [get_clocks {icache_mem_clk1}]
+set_clock_groups -name async_clock -asynchronous \
+ -group [get_clocks {rtc_clk}]\
+ -group [get_clocks {wb_clk}]\
+ -group [list [get_clocks {core_clk}]\
+ [get_clocks {dcache_mem_clk0}]\
+ [get_clocks {dcache_mem_clk1}]\
+ [get_clocks {icache_mem_clk0}]\
+ [get_clocks {icache_mem_clk1}]] -comment {Async Clock group}
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[0]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[0]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[10]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[10]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[11]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[11]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[12]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[12]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[13]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[13]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[14]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[14]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[15]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[15]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[16]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[16]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[17]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[17]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[18]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[18]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[19]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[19]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[1]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[1]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[20]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[20]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[21]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[21]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[22]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[22]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[23]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[23]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[24]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[24]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[25]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[25]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[26]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[26]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[27]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[27]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[28]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[28]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[29]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[29]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[2]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[2]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[30]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[30]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[31]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[31]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[3]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[3]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[4]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[4]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[5]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[5]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[6]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[6]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[7]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[7]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[8]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[8]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[9]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[9]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_cmd}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_cmd}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_req}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_req}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[0]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[0]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[10]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[10]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[11]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[11]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[12]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[12]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[13]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[13]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[14]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[14]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[15]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[15]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[16]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[16]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[17]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[17]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[18]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[18]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[19]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[19]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[1]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[1]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[20]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[20]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[21]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[21]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[22]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[22]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[23]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[23]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[24]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[24]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[25]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[25]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[26]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[26]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[27]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[27]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[28]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[28]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[29]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[29]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[2]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[2]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[30]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[30]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[31]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[31]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[3]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[3]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[4]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[4]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[5]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[5]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[6]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[6]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[7]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[7]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[8]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[8]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[9]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[9]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_width[0]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_width[0]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_width[1]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_width[1]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[0]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[0]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[10]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[10]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[11]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[11]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[12]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[12]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[13]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[13]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[14]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[14]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[15]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[15]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[16]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[16]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[17]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[17]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[18]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[18]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[19]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[19]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[1]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[1]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[20]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[20]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[21]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[21]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[22]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[22]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[23]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[23]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[24]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[24]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[25]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[25]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[26]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[26]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[27]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[27]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[28]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[28]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[29]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[29]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[2]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[2]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[30]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[30]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[31]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[31]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[3]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[3]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[4]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[4]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[5]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[5]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[6]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[6]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[7]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[7]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[8]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[8]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[9]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[9]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_cmd}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_cmd}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_req}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_req}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[0]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[0]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[10]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[10]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[11]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[11]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[12]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[12]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[13]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[13]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[14]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[14]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[15]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[15]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[16]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[16]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[17]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[17]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[18]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[18]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[19]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[19]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[1]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[1]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[20]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[20]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[21]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[21]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[22]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[22]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[23]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[23]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[24]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[24]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[25]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[25]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[26]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[26]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[27]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[27]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[28]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[28]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[29]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[29]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[2]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[2]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[30]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[30]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[31]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[31]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[3]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[3]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[4]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[4]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[5]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[5]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[6]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[6]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[7]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[7]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[8]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[8]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[9]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[9]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_width[0]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_width[0]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_width[1]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_width[1]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[0]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[0]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[10]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[10]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[11]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[11]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[12]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[12]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[13]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[13]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[14]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[14]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[15]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[15]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[16]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[16]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[17]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[17]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[18]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[18]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[19]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[19]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[1]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[1]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[20]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[20]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[21]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[21]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[22]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[22]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[23]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[23]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[24]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[24]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[25]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[25]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[26]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[26]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[27]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[27]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[28]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[28]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[29]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[29]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[2]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[2]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[30]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[30]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[31]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[31]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[3]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[3]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[4]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[4]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[5]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[5]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[6]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[6]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[7]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[7]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[8]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[8]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[9]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[9]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_bl[0]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_bl[0]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_bl[1]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_bl[1]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_bl[2]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_bl[2]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_cmd}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_cmd}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_req}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_req}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_width[0]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_width[0]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_width[1]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_width[1]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[0]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[0]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[10]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[10]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[11]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[11]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[12]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[12]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[13]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[13]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[14]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[14]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[15]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[15]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[16]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[16]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[17]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[17]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[18]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[18]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[19]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[19]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[1]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[1]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[20]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[20]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[21]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[21]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[22]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[22]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[23]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[23]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[24]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[24]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[25]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[25]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[26]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[26]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[27]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[27]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[28]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[28]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[29]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[29]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[2]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[2]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[30]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[30]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[31]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[31]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[3]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[3]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[4]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[4]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[5]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[5]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[6]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[6]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[7]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[7]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[8]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[8]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[9]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[9]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[0]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[0]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[10]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[10]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[11]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[11]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[12]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[12]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[13]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[13]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[14]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[14]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[15]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[15]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[16]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[16]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[17]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[17]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[18]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[18]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[19]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[19]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[1]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[1]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[20]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[20]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[21]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[21]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[22]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[22]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[23]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[23]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[24]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[24]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[25]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[25]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[26]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[26]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[27]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[27]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[28]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[28]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[29]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[29]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[2]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[2]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[30]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[30]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[31]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[31]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[3]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[3]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[4]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[4]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[5]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[5]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[6]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[6]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[7]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[7]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[8]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[8]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[9]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[9]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[0]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[0]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[10]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[10]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[11]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[11]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[12]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[12]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[13]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[13]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[14]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[14]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[15]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[15]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[16]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[16]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[17]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[17]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[18]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[18]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[19]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[19]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[1]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[1]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[20]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[20]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[21]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[21]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[22]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[22]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[23]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[23]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[24]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[24]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[25]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[25]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[26]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[26]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[27]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[27]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[28]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[28]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[29]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[29]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[2]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[2]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[30]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[30]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[31]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[31]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[3]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[3]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[4]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[4]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[5]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[5]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[6]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[6]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[7]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[7]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[8]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[8]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[9]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[9]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_ack_i}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_ack_i}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[0]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[10]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[10]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[11]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[11]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[12]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[12]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[13]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[13]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[14]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[14]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[15]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[15]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[16]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[16]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[17]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[17]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[18]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[18]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[19]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[19]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[1]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[20]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[20]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[21]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[21]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[22]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[22]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[23]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[23]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[24]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[24]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[25]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[25]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[26]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[26]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[27]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[27]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[28]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[28]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[29]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[29]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[2]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[30]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[30]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[31]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[31]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[3]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[4]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[4]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[5]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[5]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[6]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[6]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[7]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[7]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[8]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[8]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[9]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[9]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_err_i}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_err_i}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_lack_i}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_lack_i}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_ack_i}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_ack_i}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[0]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[10]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[10]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[11]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[11]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[12]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[12]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[13]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[13]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[14]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[14]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[15]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[15]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[16]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[16]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[17]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[17]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[18]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[18]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[19]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[19]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[1]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[20]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[20]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[21]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[21]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[22]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[22]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[23]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[23]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[24]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[24]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[25]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[25]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[26]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[26]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[27]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[27]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[28]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[28]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[29]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[29]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[2]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[30]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[30]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[31]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[31]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[3]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[4]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[4]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[5]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[5]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[6]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[6]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[7]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[7]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[8]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[8]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[9]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[9]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_err_i}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_err_i}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_lack_i}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_lack_i}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_ack_i}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_ack_i}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[0]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[10]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[10]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[11]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[11]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[12]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[12]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[13]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[13]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[14]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[14]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[15]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[15]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[16]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[16]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[17]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[17]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[18]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[18]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[19]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[19]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[1]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[20]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[20]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[21]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[21]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[22]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[22]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[23]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[23]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[24]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[24]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[25]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[25]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[26]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[26]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[27]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[27]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[28]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[28]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[29]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[29]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[2]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[30]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[30]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[31]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[31]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[3]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[4]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[4]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[5]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[5]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[6]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[6]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[7]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[7]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[8]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[8]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[9]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[9]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_err_i}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_err_i}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[0]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[0]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[10]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[10]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[11]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[11]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[12]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[12]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[13]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[13]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[14]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[14]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[15]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[15]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[16]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[16]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[17]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[17]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[18]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[18]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[19]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[19]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[1]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[1]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[20]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[20]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[21]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[21]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[22]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[22]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[23]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[23]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[24]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[24]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[25]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[25]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[26]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[26]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[27]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[27]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[28]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[28]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[29]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[29]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[2]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[2]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[30]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[30]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[31]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[31]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[3]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[3]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[4]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[4]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[5]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[5]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[6]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[6]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[7]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[7]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[8]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[8]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[9]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[9]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_req_ack}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_req_ack}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_resp[0]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_resp[0]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_resp[1]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_resp[1]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[0]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[0]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[10]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[10]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[11]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[11]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[12]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[12]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[13]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[13]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[14]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[14]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[15]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[15]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[16]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[16]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[17]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[17]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[18]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[18]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[19]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[19]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[1]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[1]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[20]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[20]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[21]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[21]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[22]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[22]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[23]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[23]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[24]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[24]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[25]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[25]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[26]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[26]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[27]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[27]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[28]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[28]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[29]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[29]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[2]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[2]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[30]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[30]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[31]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[31]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[3]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[3]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[4]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[4]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[5]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[5]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[6]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[6]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[7]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[7]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[8]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[8]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[9]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[9]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_req_ack}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_req_ack}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_resp[0]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_resp[0]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_resp[1]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_resp[1]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[0]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[0]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[10]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[10]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[11]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[11]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[12]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[12]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[13]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[13]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[14]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[14]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[15]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[15]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[16]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[16]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[17]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[17]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[18]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[18]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[19]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[19]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[1]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[1]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[20]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[20]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[21]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[21]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[22]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[22]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[23]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[23]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[24]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[24]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[25]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[25]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[26]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[26]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[27]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[27]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[28]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[28]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[29]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[29]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[2]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[2]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[30]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[30]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[31]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[31]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[3]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[3]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[4]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[4]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[5]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[5]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[6]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[6]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[7]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[7]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[8]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[8]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[9]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[9]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_req_ack}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_req_ack}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_resp[0]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_resp[0]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_resp[1]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_resp[1]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_addr0[0]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_addr0[0]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_addr0[1]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_addr0[1]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_addr0[2]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_addr0[2]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_addr0[3]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_addr0[3]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_addr0[4]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_addr0[4]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_addr0[5]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_addr0[5]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_addr0[6]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_addr0[6]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_addr0[7]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_addr0[7]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_addr0[8]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_addr0[8]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_addr1[0]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_addr1[0]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_addr1[1]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_addr1[1]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_addr1[2]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_addr1[2]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_addr1[3]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_addr1[3]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_addr1[4]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_addr1[4]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_addr1[5]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_addr1[5]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_addr1[6]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_addr1[6]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_addr1[7]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_addr1[7]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_addr1[8]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_addr1[8]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_csb0}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_csb0}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_csb1}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_csb1}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[0]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[0]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[10]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[10]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[11]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[11]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[12]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[12]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[13]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[13]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[14]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[14]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[15]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[15]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[16]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[16]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[17]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[17]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[18]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[18]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[19]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[19]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[1]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[1]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[20]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[20]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[21]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[21]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[22]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[22]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[23]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[23]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[24]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[24]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[25]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[25]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[26]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[26]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[27]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[27]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[28]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[28]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[29]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[29]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[2]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[2]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[30]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[30]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[31]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[31]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[3]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[3]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[4]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[4]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[5]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[5]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[6]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[6]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[7]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[7]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[8]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[8]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[9]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[9]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_web0}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_web0}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_wmask0[0]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_wmask0[0]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_wmask0[1]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_wmask0[1]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_wmask0[2]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_wmask0[2]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_wmask0[3]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_wmask0[3]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_addr0[0]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_addr0[0]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_addr0[1]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_addr0[1]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_addr0[2]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_addr0[2]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_addr0[3]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_addr0[3]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_addr0[4]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_addr0[4]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_addr0[5]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_addr0[5]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_addr0[6]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_addr0[6]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_addr0[7]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_addr0[7]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_addr0[8]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_addr0[8]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_addr1[0]}]
+set_output_delay 3.5000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_addr1[0]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_addr1[1]}]
+set_output_delay 3.5000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_addr1[1]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_addr1[2]}]
+set_output_delay 3.5000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_addr1[2]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_addr1[3]}]
+set_output_delay 3.5000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_addr1[3]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_addr1[4]}]
+set_output_delay 3.5000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_addr1[4]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_addr1[5]}]
+set_output_delay 3.5000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_addr1[5]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_addr1[6]}]
+set_output_delay 3.5000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_addr1[6]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_addr1[7]}]
+set_output_delay 3.5000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_addr1[7]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_addr1[8]}]
+set_output_delay 3.5000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_addr1[8]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_csb0}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_csb0}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_csb1}]
+set_output_delay 3.5000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_csb1}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[0]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[0]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[10]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[10]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[11]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[11]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[12]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[12]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[13]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[13]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[14]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[14]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[15]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[15]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[16]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[16]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[17]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[17]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[18]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[18]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[19]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[19]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[1]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[1]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[20]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[20]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[21]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[21]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[22]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[22]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[23]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[23]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[24]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[24]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[25]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[25]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[26]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[26]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[27]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[27]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[28]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[28]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[29]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[29]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[2]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[2]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[30]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[30]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[31]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[31]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[3]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[3]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[4]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[4]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[5]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[5]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[6]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[6]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[7]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[7]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[8]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[8]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[9]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[9]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_web0}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_web0}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_wmask0[0]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_wmask0[0]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_wmask0[1]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_wmask0[1]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_wmask0[2]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_wmask0[2]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_wmask0[3]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_wmask0[3]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[0]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[10]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[10]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[11]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[11]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[12]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[12]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[13]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[13]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[14]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[14]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[15]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[15]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[16]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[16]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[17]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[17]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[18]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[18]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[19]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[19]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[1]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[20]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[20]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[21]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[21]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[22]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[22]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[23]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[23]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[24]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[24]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[25]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[25]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[26]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[26]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[27]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[27]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[28]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[28]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[29]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[29]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[2]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[30]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[30]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[31]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[31]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[3]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[4]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[4]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[5]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[5]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[6]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[6]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[7]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[7]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[8]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[8]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[9]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[9]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_bl_o[0]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_bl_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_bl_o[1]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_bl_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_bl_o[2]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_bl_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_bl_o[3]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_bl_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_bl_o[4]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_bl_o[4]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_bl_o[5]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_bl_o[5]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_bl_o[6]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_bl_o[6]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_bl_o[7]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_bl_o[7]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_bl_o[8]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_bl_o[8]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_bl_o[9]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_bl_o[9]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_bry_o}]
+set_output_delay 5.5000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_bry_o}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_cyc_o}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_cyc_o}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[0]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[10]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[10]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[11]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[11]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[12]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[12]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[13]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[13]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[14]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[14]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[15]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[15]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[16]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[16]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[17]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[17]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[18]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[18]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[19]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[19]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[1]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[20]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[20]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[21]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[21]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[22]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[22]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[23]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[23]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[24]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[24]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[25]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[25]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[26]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[26]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[27]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[27]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[28]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[28]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[29]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[29]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[2]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[30]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[30]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[31]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[31]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[3]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[4]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[4]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[5]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[5]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[6]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[6]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[7]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[7]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[8]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[8]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[9]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[9]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_stb_o}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_stb_o}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_we_o}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_we_o}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[0]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[10]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[10]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[11]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[11]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[12]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[12]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[13]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[13]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[14]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[14]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[15]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[15]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[16]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[16]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[17]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[17]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[18]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[18]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[19]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[19]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[1]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[20]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[20]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[21]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[21]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[22]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[22]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[23]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[23]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[24]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[24]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[25]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[25]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[26]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[26]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[27]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[27]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[28]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[28]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[29]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[29]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[2]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[30]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[30]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[31]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[31]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[3]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[4]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[4]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[5]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[5]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[6]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[6]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[7]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[7]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[8]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[8]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[9]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[9]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_bl_o[0]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_bl_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_bl_o[1]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_bl_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_bl_o[2]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_bl_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_bl_o[3]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_bl_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_bl_o[4]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_bl_o[4]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_bl_o[5]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_bl_o[5]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_bl_o[6]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_bl_o[6]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_bl_o[7]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_bl_o[7]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_bl_o[8]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_bl_o[8]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_bl_o[9]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_bl_o[9]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_bry_o}]
+set_output_delay 2.5000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_bry_o}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_sel_o[0]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_sel_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_sel_o[1]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_sel_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_sel_o[2]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_sel_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_sel_o[3]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_sel_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_stb_o}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_stb_o}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_we_o}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_we_o}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[0]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[10]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[10]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[11]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[11]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[12]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[12]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[13]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[13]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[14]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[14]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[15]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[15]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[16]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[16]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[17]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[17]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[18]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[18]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[19]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[19]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[1]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[20]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[20]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[21]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[21]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[22]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[22]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[23]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[23]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[24]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[24]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[25]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[25]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[26]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[26]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[27]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[27]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[28]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[28]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[29]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[29]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[2]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[30]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[30]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[31]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[31]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[3]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[4]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[4]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[5]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[5]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[6]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[6]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[7]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[7]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[8]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[8]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[9]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[9]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[0]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[10]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[10]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[11]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[11]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[12]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[12]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[13]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[13]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[14]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[14]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[15]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[15]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[16]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[16]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[17]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[17]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[18]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[18]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[19]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[19]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[1]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[20]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[20]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[21]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[21]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[22]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[22]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[23]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[23]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[24]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[24]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[25]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[25]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[26]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[26]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[27]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[27]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[28]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[28]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[29]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[29]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[2]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[30]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[30]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[31]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[31]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[3]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[4]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[4]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[5]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[5]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[6]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[6]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[7]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[7]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[8]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[8]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[9]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[9]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_sel_o[0]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_sel_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_sel_o[1]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_sel_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_sel_o[2]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_sel_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_sel_o[3]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_sel_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_stb_o}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_stb_o}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_we_o}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_we_o}]
+set_false_path\
+ -from [list [get_ports {cfg_dcache_force_flush}]\
+ [get_ports {cfg_dcache_pfet_dis}]\
+ [get_ports {cfg_icache_ntag_pfet_dis}]\
+ [get_ports {cfg_icache_pfet_dis}]\
+ [get_ports {cfg_sram_lphase[0]}]\
+ [get_ports {cfg_sram_lphase[1]}]\
+ [get_ports {cpu_intf_rst_n}]\
+ [get_ports {pwrup_rst_n}]\
+ [get_ports {wb_rst_n}]]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {core_clk_skew}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_req_ack}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_req_ack}]
+set_load -pin_load 0.0334 [get_ports {core_icache_req_ack}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_clk0}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_clk1}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_csb0}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_csb1}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_web0}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_clk0}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_clk1}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_csb0}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_csb1}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_web0}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_bry_o}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_cyc_o}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_stb_o}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_we_o}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_bry_o}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_cyc_o}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_stb_o}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_we_o}]
+set_load -pin_load 0.0334 [get_ports {wbd_clk_skew}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_bry_o}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_cyc_o}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_stb_o}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_we_o}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[31]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[30]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[29]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[28]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[27]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[26]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[25]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[24]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[23]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[22]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[21]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[20]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[19]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[18]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[17]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[16]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[15]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[14]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[13]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[12]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[11]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[10]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[9]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[8]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[7]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[6]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[5]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[4]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[3]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[2]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[1]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[0]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_resp[1]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_resp[0]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[31]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[30]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[29]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[28]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[27]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[26]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[25]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[24]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[23]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[22]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[21]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[20]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[19]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[18]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[17]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[16]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[15]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[14]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[13]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[12]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[11]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[10]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[9]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[8]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[7]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[6]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[5]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[4]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[3]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[2]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[1]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[0]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_resp[1]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_resp[0]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[31]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[30]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[29]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[28]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[27]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[26]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[25]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[24]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[23]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[22]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[21]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[20]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[19]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[18]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[17]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[16]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[15]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[14]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[13]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[12]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[11]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[10]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[9]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[8]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[7]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[6]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[5]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[4]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[3]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[2]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[1]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[0]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_resp[1]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_resp[0]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_addr0[8]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_addr0[7]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_addr0[6]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_addr0[5]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_addr0[4]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_addr0[3]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_addr0[2]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_addr0[1]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_addr0[0]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_addr1[8]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_addr1[7]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_addr1[6]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_addr1[5]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_addr1[4]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_addr1[3]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_addr1[2]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_addr1[1]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_addr1[0]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[31]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[30]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[29]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[28]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[27]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[26]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[25]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[24]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[23]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[22]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[21]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[20]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[19]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[18]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[17]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[16]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[15]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[14]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[13]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[12]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[11]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[10]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[9]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[8]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[7]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[6]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[5]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[4]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[3]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[2]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[1]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[0]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_wmask0[3]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_wmask0[2]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_wmask0[1]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_wmask0[0]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_addr0[8]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_addr0[7]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_addr0[6]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_addr0[5]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_addr0[4]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_addr0[3]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_addr0[2]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_addr0[1]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_addr0[0]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_addr1[8]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_addr1[7]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_addr1[6]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_addr1[5]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_addr1[4]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_addr1[3]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_addr1[2]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_addr1[1]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_addr1[0]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[31]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[30]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[29]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[28]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[27]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[26]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[25]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[24]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[23]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[22]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[21]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[20]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[19]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[18]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[17]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[16]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[15]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[14]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[13]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[12]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[11]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[10]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[9]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[8]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[7]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[6]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[5]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[4]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[3]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[2]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[1]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[0]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_wmask0[3]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_wmask0[2]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_wmask0[1]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_wmask0[0]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[31]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[30]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[29]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[28]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[27]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[26]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[25]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[24]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[23]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[22]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[21]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[20]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[19]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[18]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[17]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[16]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[15]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[14]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[13]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[12]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[11]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[10]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[9]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[8]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[7]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[6]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[5]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[4]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[0]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_bl_o[9]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_bl_o[8]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_bl_o[7]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_bl_o[6]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_bl_o[5]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_bl_o[4]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_bl_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_bl_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_bl_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_bl_o[0]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[31]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[30]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[29]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[28]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[27]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[26]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[25]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[24]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[23]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[22]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[21]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[20]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[19]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[18]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[17]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[16]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[15]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[14]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[13]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[12]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[11]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[10]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[9]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[8]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[7]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[6]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[5]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[4]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[0]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_sel_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_sel_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_sel_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_sel_o[0]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[31]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[30]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[29]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[28]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[27]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[26]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[25]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[24]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[23]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[22]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[21]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[20]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[19]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[18]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[17]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[16]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[15]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[14]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[13]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[12]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[11]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[10]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[9]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[8]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[7]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[6]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[5]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[4]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[0]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_bl_o[9]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_bl_o[8]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_bl_o[7]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_bl_o[6]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_bl_o[5]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_bl_o[4]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_bl_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_bl_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_bl_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_bl_o[0]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_sel_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_sel_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_sel_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_sel_o[0]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[31]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[30]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[29]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[28]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[27]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[26]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[25]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[24]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[23]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[22]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[21]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[20]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[19]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[18]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[17]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[16]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[15]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[14]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[13]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[12]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[11]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[10]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[9]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[8]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[7]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[6]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[5]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[4]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[0]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_bl_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_bl_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_bl_o[0]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[31]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[30]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[29]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[28]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[27]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[26]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[25]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[24]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[23]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[22]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[21]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[20]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[19]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[18]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[17]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[16]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[15]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[14]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[13]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[12]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[11]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[10]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[9]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[8]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[7]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[6]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[5]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[4]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[0]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_sel_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_sel_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_sel_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_sel_o[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_bypass_dcache}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_bypass_icache}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_dcache_force_flush}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_dcache_pfet_dis}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_icache_ntag_pfet_dis}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_icache_pfet_dis}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_clk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_cmd}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_req}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_cmd}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_req}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_cmd}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_req}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cpu_intf_rst_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {pwrup_rst_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_clk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_ack_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_err_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_lack_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_ack_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_err_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_lack_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_rst_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_ack_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_err_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_lack_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_ccska[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_ccska[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_ccska[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_ccska[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sram_lphase[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sram_lphase[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_wcska[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_wcska[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_wcska[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_wcska[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_width[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_width[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_bl[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_bl[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_bl[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_width[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_width[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_bl[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_bl[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_bl[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_width[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_width[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[0]}]
+set_case_analysis 0 [get_ports {cfg_ccska[0]}]
+set_case_analysis 0 [get_ports {cfg_ccska[1]}]
+set_case_analysis 0 [get_ports {cfg_ccska[2]}]
+set_case_analysis 0 [get_ports {cfg_ccska[3]}]
+set_case_analysis 0 [get_ports {cfg_wcska[0]}]
+set_case_analysis 0 [get_ports {cfg_wcska[1]}]
+set_case_analysis 0 [get_ports {cfg_wcska[2]}]
+set_case_analysis 0 [get_ports {cfg_wcska[3]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_transition 1.0000 [current_design]
+set_max_capacitance 0.2000 [current_design]
+set_max_fanout 10.0000 [current_design]
