sdc/ycr_core_top.sdc

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# Created by write_sdc
# Wed Nov 30 14:16:33 2022
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current_design ycr_core_top
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# Timing Constraints
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create_clock -name core_clk -period 10.0000 [get_ports {clk}]
set_clock_transition 0.1500 [get_clocks {core_clk}]
set_clock_uncertainty -setup 0.5000 core_clk
set_clock_uncertainty -hold 0.2500 core_clk
set_propagated_clock [get_clocks {core_clk}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[0]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[10]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[10]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[11]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[11]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[12]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[12]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[13]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[13]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[14]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[14]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[15]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[15]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[16]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[16]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[17]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[17]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[18]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[18]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[19]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[19]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[1]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[20]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[20]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[21]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[21]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[22]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[22]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[23]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[23]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[24]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[24]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[25]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[25]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[26]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[26]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[27]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[27]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[28]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[28]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[29]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[29]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[2]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[2]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[30]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[30]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[31]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[31]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[3]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[3]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[4]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[4]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[5]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[5]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[6]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[6]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[7]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[7]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[8]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[8]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[9]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[9]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_req_ack_i}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_req_ack_i}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_resp_i[0]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_resp_i[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_resp_i[1]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_resp_i[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[0]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[10]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[10]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[11]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[11]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[12]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[12]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[13]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[13]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[14]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[14]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[15]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[15]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[16]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[16]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[17]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[17]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[18]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[18]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[19]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[19]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[1]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[20]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[20]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[21]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[21]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[22]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[22]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[23]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[23]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[24]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[24]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[25]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[25]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[26]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[26]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[27]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[27]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[28]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[28]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[29]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[29]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[2]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[2]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[30]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[30]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[31]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[31]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[3]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[3]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[4]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[4]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[5]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[5]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[6]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[6]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[7]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[7]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[8]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[8]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[9]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[9]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_req_ack_i}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_req_ack_i}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_resp_i[0]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_resp_i[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_resp_i[1]}]
set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_resp_i[1]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[0]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[0]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[10]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[10]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[11]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[11]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[12]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[12]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[13]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[13]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[14]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[14]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[15]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[15]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[16]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[16]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[17]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[17]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[18]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[18]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[19]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[19]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[1]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[1]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[20]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[20]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[21]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[21]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[22]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[22]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[23]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[23]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[24]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[24]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[25]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[25]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[26]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[26]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[27]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[27]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[28]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[28]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[29]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[29]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[2]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[2]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[30]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[30]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[31]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[31]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[3]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[3]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[4]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[4]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[5]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[5]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[6]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[6]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[7]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[7]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[8]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[8]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[9]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[9]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_cmd_o}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_cmd_o}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_req_o}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_req_o}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[0]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[0]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[10]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[10]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[11]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[11]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[12]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[12]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[13]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[13]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[14]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[14]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[15]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[15]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[16]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[16]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[17]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[17]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[18]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[18]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[19]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[19]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[1]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[1]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[20]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[20]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[21]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[21]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[22]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[22]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[23]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[23]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[24]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[24]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[25]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[25]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[26]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[26]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[27]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[27]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[28]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[28]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[29]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[29]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[2]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[2]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[30]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[30]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[31]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[31]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[3]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[3]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[4]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[4]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[5]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[5]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[6]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[6]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[7]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[7]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[8]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[8]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[9]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[9]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_width_o[0]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_width_o[0]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_width_o[1]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_width_o[1]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[0]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[0]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[10]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[10]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[11]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[11]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[12]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[12]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[13]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[13]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[14]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[14]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[15]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[15]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[16]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[16]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[17]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[17]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[18]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[18]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[19]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[19]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[1]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[1]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[20]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[20]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[21]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[21]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[22]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[22]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[23]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[23]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[24]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[24]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[25]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[25]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[26]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[26]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[27]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[27]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[28]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[28]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[29]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[29]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[2]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[2]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[30]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[30]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[31]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[31]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[3]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[3]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[4]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[4]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[5]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[5]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[6]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[6]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[7]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[7]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[8]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[8]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[9]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[9]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_bl_o[0]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_bl_o[0]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_bl_o[1]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_bl_o[1]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_bl_o[2]}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_bl_o[2]}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_cmd_o}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_cmd_o}]
set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_req_o}]
set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_req_o}]
###############################################################################
# Environment
###############################################################################
set_load -pin_load 0.0334 [get_ports {clk_o}]
set_load -pin_load 0.0334 [get_ports {core2dmem_cmd_o}]
set_load -pin_load 0.0334 [get_ports {core2dmem_req_o}]
set_load -pin_load 0.0334 [get_ports {core2imem_cmd_o}]
set_load -pin_load 0.0334 [get_ports {core2imem_req_o}]
set_load -pin_load 0.0334 [get_ports {core_clk_skew}]
set_load -pin_load 0.0334 [get_ports {core_rdc_qlfy_o}]
set_load -pin_load 0.0334 [get_ports {core_rst_n_o}]
set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[31]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[30]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[29]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[28]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[27]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[26]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[25]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[24]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[23]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[22]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[21]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[20]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[19]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[18]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[17]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[16]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[15]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[14]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[13]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[12]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[11]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[10]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[9]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[8]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[7]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[6]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[5]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[4]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[3]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[2]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[1]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[0]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[31]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[30]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[29]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[28]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[27]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[26]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[25]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[24]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[23]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[22]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[21]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[20]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[19]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[18]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[17]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[16]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[15]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[14]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[13]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[12]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[11]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[10]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[9]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[8]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[7]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[6]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[5]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[4]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[3]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[2]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[1]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[0]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_width_o[1]}]
set_load -pin_load 0.0334 [get_ports {core2dmem_width_o[0]}]
set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[31]}]
set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[30]}]
set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[29]}]
set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[28]}]
set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[27]}]
set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[26]}]
set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[25]}]
set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[24]}]
set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[23]}]
set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[22]}]
set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[21]}]
set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[20]}]
set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[19]}]
set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[18]}]
set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[17]}]
set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[16]}]
set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[15]}]
set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[14]}]
set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[13]}]
set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[12]}]
set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[11]}]
set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[10]}]
set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[9]}]
set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[8]}]
set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[7]}]
set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[6]}]
set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[5]}]
set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[4]}]
set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[3]}]
set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[2]}]
set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[1]}]
set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[0]}]
set_load -pin_load 0.0334 [get_ports {core2imem_bl_o[2]}]
set_load -pin_load 0.0334 [get_ports {core2imem_bl_o[1]}]
set_load -pin_load 0.0334 [get_ports {core2imem_bl_o[0]}]
set_load -pin_load 0.0334 [get_ports {core_debug[48]}]
set_load -pin_load 0.0334 [get_ports {core_debug[47]}]
set_load -pin_load 0.0334 [get_ports {core_debug[46]}]
set_load -pin_load 0.0334 [get_ports {core_debug[45]}]
set_load -pin_load 0.0334 [get_ports {core_debug[44]}]
set_load -pin_load 0.0334 [get_ports {core_debug[43]}]
set_load -pin_load 0.0334 [get_ports {core_debug[42]}]
set_load -pin_load 0.0334 [get_ports {core_debug[41]}]
set_load -pin_load 0.0334 [get_ports {core_debug[40]}]
set_load -pin_load 0.0334 [get_ports {core_debug[39]}]
set_load -pin_load 0.0334 [get_ports {core_debug[38]}]
set_load -pin_load 0.0334 [get_ports {core_debug[37]}]
set_load -pin_load 0.0334 [get_ports {core_debug[36]}]
set_load -pin_load 0.0334 [get_ports {core_debug[35]}]
set_load -pin_load 0.0334 [get_ports {core_debug[34]}]
set_load -pin_load 0.0334 [get_ports {core_debug[33]}]
set_load -pin_load 0.0334 [get_ports {core_debug[32]}]
set_load -pin_load 0.0334 [get_ports {core_debug[31]}]
set_load -pin_load 0.0334 [get_ports {core_debug[30]}]
set_load -pin_load 0.0334 [get_ports {core_debug[29]}]
set_load -pin_load 0.0334 [get_ports {core_debug[28]}]
set_load -pin_load 0.0334 [get_ports {core_debug[27]}]
set_load -pin_load 0.0334 [get_ports {core_debug[26]}]
set_load -pin_load 0.0334 [get_ports {core_debug[25]}]
set_load -pin_load 0.0334 [get_ports {core_debug[24]}]
set_load -pin_load 0.0334 [get_ports {core_debug[23]}]
set_load -pin_load 0.0334 [get_ports {core_debug[22]}]
set_load -pin_load 0.0334 [get_ports {core_debug[21]}]
set_load -pin_load 0.0334 [get_ports {core_debug[20]}]
set_load -pin_load 0.0334 [get_ports {core_debug[19]}]
set_load -pin_load 0.0334 [get_ports {core_debug[18]}]
set_load -pin_load 0.0334 [get_ports {core_debug[17]}]
set_load -pin_load 0.0334 [get_ports {core_debug[16]}]
set_load -pin_load 0.0334 [get_ports {core_debug[15]}]
set_load -pin_load 0.0334 [get_ports {core_debug[14]}]
set_load -pin_load 0.0334 [get_ports {core_debug[13]}]
set_load -pin_load 0.0334 [get_ports {core_debug[12]}]
set_load -pin_load 0.0334 [get_ports {core_debug[11]}]
set_load -pin_load 0.0334 [get_ports {core_debug[10]}]
set_load -pin_load 0.0334 [get_ports {core_debug[9]}]
set_load -pin_load 0.0334 [get_ports {core_debug[8]}]
set_load -pin_load 0.0334 [get_ports {core_debug[7]}]
set_load -pin_load 0.0334 [get_ports {core_debug[6]}]
set_load -pin_load 0.0334 [get_ports {core_debug[5]}]
set_load -pin_load 0.0334 [get_ports {core_debug[4]}]
set_load -pin_load 0.0334 [get_ports {core_debug[3]}]
set_load -pin_load 0.0334 [get_ports {core_debug[2]}]
set_load -pin_load 0.0334 [get_ports {core_debug[1]}]
set_load -pin_load 0.0334 [get_ports {core_debug[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {clk}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_clk_int}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_mtimer_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_soft_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cpu_rst_n}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_req_ack_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_req_ack_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {pwrup_rst_n}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst_n}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_ccska[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_ccska[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_ccska[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_ccska[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[63]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[62]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[61]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[60]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[59]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[58]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[57]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[56]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[55]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[54]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[53]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[52]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[51]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[50]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[49]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[48]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[47]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[46]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[45]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[44]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[43]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[42]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[41]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[40]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[39]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[38]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[37]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[36]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[35]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[34]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[33]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[32]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_uid[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_uid[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_resp_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_resp_i[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_resp_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_resp_i[0]}]
set_timing_derate -early 0.9500
set_timing_derate -late 1.0500
###############################################################################
# Design Rules
###############################################################################
set_max_transition 1.0000 [current_design]
set_max_capacitance 0.2000 [current_design]
set_max_fanout 10.0000 [current_design]