sdc/ycr4_iconnect.sdc

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# Created by write_sdc
# Wed Nov 30 11:46:32 2022
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current_design ycr4_iconnect
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# Timing Constraints
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create_clock -name core_clk -period 10.0000 [get_ports {core_clk}]
set_clock_transition 0.1500 [get_clocks {core_clk}]
set_clock_uncertainty -setup 0.5000 core_clk
set_clock_uncertainty -hold 0.3000 core_clk
set_propagated_clock [get_clocks {core_clk}]
create_generated_clock -name sram0_clk0 -add -source [get_ports {core_clk}] -master_clock [get_clocks {core_clk}] -divide_by 1 -comment {sram0 clock-0} [get_ports {sram0_clk0}]
set_clock_transition 0.1500 [get_clocks {sram0_clk0}]
set_clock_uncertainty -setup 0.5000 sram0_clk0
set_clock_uncertainty -hold 0.3000 sram0_clk0
set_propagated_clock [get_clocks {sram0_clk0}]
create_generated_clock -name sram0_clk1 -add -source [get_ports {core_clk}] -master_clock [get_clocks {core_clk}] -divide_by 1 -comment {sram0 clock-0} [get_ports {sram0_clk1}]
set_clock_transition 0.1500 [get_clocks {sram0_clk1}]
set_clock_uncertainty -setup 0.5000 sram0_clk1
set_clock_uncertainty -hold 0.3000 sram0_clk1
set_propagated_clock [get_clocks {sram0_clk1}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[0]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[0]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[10]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[10]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[11]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[11]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[12]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[12]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[13]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[13]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[14]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[14]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[15]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[15]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[16]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[16]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[17]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[17]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[18]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[18]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[19]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[19]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[1]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[1]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[20]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[20]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[21]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[21]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[22]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[22]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[23]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[23]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[24]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[24]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[25]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[25]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[26]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[26]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[27]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[27]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[28]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[28]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[29]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[29]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[2]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[2]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[30]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[30]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[31]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[31]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[32]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[32]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[33]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[33]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[34]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[34]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[35]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[35]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[36]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[36]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[37]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[37]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[38]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[38]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[39]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[39]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[3]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[3]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[40]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[40]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[41]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[41]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[42]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[42]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[43]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[43]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[44]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[44]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[45]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[45]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[46]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[46]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[47]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[47]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[48]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[48]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[4]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[4]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[5]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[5]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[6]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[6]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[7]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[7]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[8]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[8]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_debug[9]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_debug[9]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[0]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[10]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[10]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[11]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[11]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[12]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[12]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[13]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[13]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[14]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[14]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[15]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[15]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[16]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[16]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[17]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[17]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[18]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[18]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[19]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[19]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[1]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[20]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[20]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[21]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[21]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[22]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[22]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[23]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[23]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[24]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[24]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[25]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[25]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[26]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[26]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[27]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[27]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[28]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[28]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[29]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[29]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[2]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[2]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[30]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[30]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[31]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[31]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[3]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[3]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[4]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[4]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[5]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[5]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[6]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[6]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[7]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[7]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[8]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[8]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[9]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[9]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_cmd}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_cmd}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_req}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_req}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[0]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[10]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[10]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[11]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[11]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[12]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[12]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[13]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[13]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[14]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[14]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[15]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[15]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[16]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[16]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[17]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[17]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[18]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[18]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[19]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[19]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[1]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[20]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[20]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[21]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[21]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[22]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[22]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[23]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[23]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[24]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[24]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[25]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[25]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[26]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[26]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[27]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[27]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[28]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[28]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[29]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[29]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[2]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[2]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[30]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[30]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[31]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[31]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[3]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[3]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[4]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[4]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[5]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[5]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[6]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[6]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[7]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[7]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[8]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[8]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[9]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[9]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_width[0]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_width[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_width[1]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_width[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[0]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[10]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[10]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[11]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[11]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[12]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[12]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[13]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[13]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[14]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[14]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[15]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[15]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[16]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[16]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[17]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[17]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[18]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[18]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[19]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[19]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[1]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[20]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[20]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[21]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[21]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[22]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[22]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[23]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[23]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[24]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[24]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[25]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[25]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[26]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[26]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[27]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[27]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[28]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[28]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[29]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[29]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[2]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[2]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[30]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[30]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[31]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[31]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[3]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[3]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[4]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[4]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[5]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[5]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[6]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[6]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[7]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[7]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[8]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[8]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[9]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[9]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_bl[0]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_bl[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_bl[1]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_bl[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_bl[2]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_bl[2]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_cmd}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_cmd}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_req}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_req}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[0]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[0]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[10]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[10]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[11]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[11]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[12]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[12]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[13]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[13]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[14]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[14]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[15]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[15]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[16]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[16]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[17]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[17]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[18]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[18]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[19]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[19]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[1]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[1]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[20]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[20]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[21]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[21]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[22]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[22]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[23]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[23]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[24]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[24]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[25]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[25]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[26]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[26]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[27]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[27]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[28]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[28]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[29]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[29]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[2]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[2]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[30]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[30]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[31]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[31]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[32]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[32]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[33]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[33]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[34]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[34]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[35]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[35]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[36]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[36]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[37]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[37]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[38]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[38]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[39]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[39]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[3]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[3]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[40]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[40]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[41]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[41]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[42]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[42]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[43]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[43]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[44]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[44]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[45]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[45]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[46]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[46]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[47]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[47]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[48]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[48]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[4]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[4]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[5]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[5]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[6]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[6]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[7]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[7]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[8]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[8]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_debug[9]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_debug[9]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[0]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[10]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[10]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[11]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[11]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[12]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[12]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[13]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[13]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[14]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[14]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[15]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[15]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[16]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[16]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[17]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[17]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[18]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[18]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[19]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[19]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[1]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[20]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[20]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[21]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[21]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[22]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[22]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[23]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[23]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[24]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[24]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[25]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[25]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[26]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[26]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[27]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[27]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[28]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[28]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[29]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[29]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[2]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[2]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[30]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[30]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[31]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[31]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[3]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[3]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[4]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[4]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[5]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[5]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[6]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[6]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[7]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[7]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[8]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[8]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[9]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[9]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_cmd}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_cmd}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_req}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_req}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[0]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[10]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[10]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[11]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[11]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[12]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[12]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[13]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[13]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[14]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[14]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[15]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[15]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[16]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[16]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[17]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[17]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[18]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[18]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[19]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[19]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[1]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[20]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[20]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[21]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[21]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[22]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[22]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[23]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[23]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[24]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[24]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[25]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[25]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[26]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[26]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[27]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[27]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[28]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[28]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[29]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[29]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[2]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[2]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[30]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[30]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[31]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[31]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[3]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[3]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[4]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[4]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[5]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[5]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[6]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[6]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[7]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[7]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[8]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[8]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[9]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[9]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_width[0]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_width[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_width[1]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_width[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[0]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[10]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[10]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[11]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[11]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[12]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[12]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[13]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[13]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[14]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[14]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[15]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[15]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[16]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[16]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[17]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[17]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[18]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[18]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[19]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[19]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[1]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[20]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[20]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[21]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[21]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[22]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[22]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[23]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[23]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[24]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[24]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[25]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[25]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[26]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[26]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[27]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[27]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[28]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[28]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[29]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[29]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[2]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[2]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[30]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[30]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[31]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[31]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[3]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[3]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[4]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[4]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[5]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[5]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[6]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[6]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[7]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[7]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[8]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[8]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[9]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[9]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_bl[0]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_bl[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_bl[1]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_bl[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_bl[2]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_bl[2]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_cmd}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_cmd}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_req}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_req}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[0]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[0]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[10]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[10]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[11]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[11]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[12]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[12]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[13]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[13]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[14]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[14]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[15]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[15]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[16]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[16]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[17]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[17]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[18]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[18]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[19]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[19]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[1]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[1]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[20]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[20]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[21]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[21]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[22]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[22]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[23]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[23]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[24]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[24]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[25]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[25]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[26]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[26]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[27]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[27]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[28]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[28]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[29]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[29]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[2]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[2]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[30]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[30]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[31]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[31]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[32]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[32]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[33]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[33]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[34]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[34]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[35]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[35]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[36]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[36]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[37]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[37]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[38]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[38]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[39]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[39]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[3]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[3]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[40]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[40]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[41]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[41]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[42]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[42]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[43]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[43]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[44]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[44]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[45]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[45]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[46]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[46]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[47]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[47]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[48]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[48]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[4]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[4]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[5]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[5]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[6]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[6]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[7]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[7]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[8]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[8]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_debug[9]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_debug[9]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[0]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[10]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[10]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[11]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[11]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[12]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[12]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[13]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[13]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[14]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[14]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[15]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[15]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[16]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[16]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[17]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[17]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[18]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[18]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[19]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[19]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[1]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[20]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[20]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[21]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[21]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[22]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[22]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[23]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[23]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[24]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[24]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[25]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[25]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[26]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[26]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[27]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[27]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[28]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[28]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[29]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[29]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[2]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[2]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[30]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[30]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[31]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[31]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[3]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[3]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[4]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[4]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[5]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[5]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[6]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[6]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[7]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[7]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[8]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[8]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_addr[9]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_addr[9]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_cmd}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_cmd}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_req}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_req}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[0]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[10]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[10]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[11]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[11]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[12]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[12]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[13]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[13]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[14]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[14]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[15]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[15]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[16]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[16]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[17]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[17]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[18]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[18]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[19]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[19]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[1]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[20]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[20]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[21]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[21]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[22]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[22]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[23]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[23]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[24]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[24]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[25]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[25]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[26]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[26]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[27]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[27]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[28]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[28]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[29]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[29]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[2]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[2]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[30]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[30]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[31]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[31]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[3]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[3]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[4]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[4]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[5]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[5]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[6]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[6]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[7]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[7]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[8]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[8]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_wdata[9]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_wdata[9]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_width[0]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_width[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_dmem_width[1]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_dmem_width[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[0]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[10]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[10]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[11]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[11]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[12]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[12]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[13]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[13]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[14]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[14]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[15]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[15]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[16]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[16]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[17]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[17]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[18]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[18]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[19]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[19]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[1]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[20]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[20]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[21]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[21]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[22]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[22]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[23]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[23]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[24]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[24]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[25]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[25]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[26]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[26]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[27]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[27]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[28]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[28]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[29]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[29]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[2]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[2]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[30]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[30]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[31]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[31]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[3]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[3]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[4]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[4]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[5]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[5]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[6]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[6]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[7]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[7]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[8]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[8]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_addr[9]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_addr[9]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_bl[0]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_bl[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_bl[1]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_bl[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_bl[2]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_bl[2]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_cmd}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_cmd}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2_imem_req}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2_imem_req}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[0]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[0]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[10]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[10]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[11]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[11]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[12]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[12]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[13]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[13]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[14]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[14]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[15]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[15]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[16]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[16]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[17]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[17]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[18]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[18]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[19]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[19]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[1]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[1]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[20]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[20]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[21]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[21]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[22]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[22]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[23]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[23]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[24]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[24]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[25]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[25]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[26]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[26]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[27]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[27]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[28]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[28]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[29]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[29]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[2]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[2]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[30]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[30]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[31]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[31]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[32]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[32]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[33]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[33]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[34]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[34]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[35]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[35]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[36]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[36]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[37]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[37]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[38]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[38]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[39]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[39]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[3]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[3]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[40]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[40]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[41]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[41]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[42]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[42]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[43]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[43]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[44]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[44]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[45]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[45]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[46]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[46]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[47]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[47]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[48]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[48]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[4]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[4]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[5]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[5]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[6]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[6]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[7]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[7]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[8]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[8]}]
set_input_delay 1.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_debug[9]}]
set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_debug[9]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[0]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[10]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[10]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[11]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[11]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[12]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[12]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[13]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[13]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[14]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[14]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[15]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[15]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[16]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[16]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[17]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[17]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[18]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[18]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[19]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[19]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[1]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[20]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[20]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[21]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[21]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[22]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[22]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[23]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[23]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[24]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[24]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[25]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[25]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[26]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[26]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[27]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[27]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[28]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[28]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[29]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[29]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[2]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[2]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[30]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[30]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[31]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[31]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[3]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[3]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[4]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[4]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[5]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[5]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[6]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[6]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[7]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[7]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[8]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[8]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_addr[9]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_addr[9]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_cmd}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_cmd}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_req}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_req}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[0]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[10]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[10]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[11]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[11]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[12]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[12]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[13]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[13]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[14]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[14]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[15]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[15]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[16]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[16]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[17]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[17]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[18]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[18]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[19]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[19]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[1]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[20]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[20]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[21]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[21]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[22]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[22]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[23]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[23]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[24]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[24]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[25]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[25]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[26]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[26]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[27]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[27]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[28]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[28]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[29]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[29]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[2]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[2]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[30]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[30]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[31]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[31]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[3]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[3]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[4]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[4]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[5]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[5]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[6]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[6]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[7]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[7]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[8]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[8]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_wdata[9]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_wdata[9]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_width[0]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_width[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_dmem_width[1]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_dmem_width[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[0]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[10]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[10]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[11]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[11]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[12]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[12]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[13]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[13]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[14]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[14]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[15]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[15]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[16]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[16]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[17]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[17]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[18]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[18]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[19]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[19]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[1]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[20]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[20]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[21]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[21]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[22]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[22]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[23]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[23]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[24]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[24]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[25]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[25]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[26]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[26]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[27]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[27]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[28]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[28]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[29]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[29]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[2]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[2]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[30]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[30]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[31]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[31]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[3]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[3]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[4]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[4]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[5]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[5]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[6]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[6]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[7]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[7]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[8]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[8]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_addr[9]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_addr[9]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_bl[0]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_bl[0]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_bl[1]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_bl[1]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_bl[2]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_bl[2]}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_cmd}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_cmd}]
set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core3_imem_req}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core3_imem_req}]
set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[0]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[0]}]
set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[10]}]
set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[10]}]
set_input_delay 3.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[11]}]
set