| ############################################################################### |
| # Created by write_sdc |
| # Mon Nov 28 03:20:00 2022 |
| ############################################################################### |
| current_design qspim_top |
| ############################################################################### |
| # Timing Constraints |
| ############################################################################### |
| create_clock -name mclk -period 10.0000 [get_ports {mclk}] |
| set_clock_transition 0.1500 [get_clocks {mclk}] |
| set_clock_uncertainty -setup 0.5000 mclk |
| set_clock_uncertainty -hold 0.2500 mclk |
| set_propagated_clock [get_clocks {mclk}] |
| create_generated_clock -name spiclk -add -source [get_ports {mclk}] -master_clock [get_clocks {mclk}] -divide_by 2 -comment {SPI Clock Out} [get_ports {spi_clk}] |
| set_clock_transition 0.1500 [get_clocks {spiclk}] |
| set_clock_uncertainty -setup 0.5000 spiclk |
| set_clock_uncertainty -hold 0.2500 spiclk |
| set_propagated_clock [get_clocks {spiclk}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {rst_n}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {rst_n}] |
| set_input_delay 0.0000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdi[0]}] |
| set_input_delay 5.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdi[0]}] |
| set_input_delay 0.0000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdi[1]}] |
| set_input_delay 5.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdi[1]}] |
| set_input_delay 0.0000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdi[2]}] |
| set_input_delay 5.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdi[2]}] |
| set_input_delay 0.0000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdi[3]}] |
| set_input_delay 5.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdi[3]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[0]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[0]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[10]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[10]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[11]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[11]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[12]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[12]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[13]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[13]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[14]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[14]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[15]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[15]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[16]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[16]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[17]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[17]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[18]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[18]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[19]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[19]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[1]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[1]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[20]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[20]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[21]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[21]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[22]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[22]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[23]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[23]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[24]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[24]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[25]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[25]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[26]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[26]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[27]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[27]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[28]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[28]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[29]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[29]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[2]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[2]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[30]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[30]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[31]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[31]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[3]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[3]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[4]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[4]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[5]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[5]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[6]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[6]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[7]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[7]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[8]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[8]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[9]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[9]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[0]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[0]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[10]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[10]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[11]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[11]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[12]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[12]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[13]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[13]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[14]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[14]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[15]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[15]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[16]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[16]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[17]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[17]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[18]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[18]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[19]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[19]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[1]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[1]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[20]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[20]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[21]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[21]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[22]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[22]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[23]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[23]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[24]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[24]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[25]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[25]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[26]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[26]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[27]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[27]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[28]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[28]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[29]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[29]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[2]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[2]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[30]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[30]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[31]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[31]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[3]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[3]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[4]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[4]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[5]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[5]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[6]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[6]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[7]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[7]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[8]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[8]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[9]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[9]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_sel_i[0]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_sel_i[0]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_sel_i[1]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_sel_i[1]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_sel_i[2]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_sel_i[2]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_sel_i[3]}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_sel_i[3]}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_stb_i}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_stb_i}] |
| set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_we_i}] |
| set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_we_i}] |
| set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_csn[0]}] |
| set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_csn[0]}] |
| set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_csn[1]}] |
| set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_csn[1]}] |
| set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_csn[2]}] |
| set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_csn[2]}] |
| set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_csn[3]}] |
| set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_csn[3]}] |
| set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_oen[0]}] |
| set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_oen[0]}] |
| set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_oen[1]}] |
| set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_oen[1]}] |
| set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_oen[2]}] |
| set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_oen[2]}] |
| set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_oen[3]}] |
| set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_oen[3]}] |
| set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdo[0]}] |
| set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdo[0]}] |
| set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdo[1]}] |
| set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdo[1]}] |
| set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdo[2]}] |
| set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdo[2]}] |
| set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdo[3]}] |
| set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdo[3]}] |
| set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_ack_o}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_ack_o}] |
| set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[0]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[0]}] |
| set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[10]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[10]}] |
| set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[11]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[11]}] |
| set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[12]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[12]}] |
| set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[13]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[13]}] |
| set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[14]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[14]}] |
| set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[15]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[15]}] |
| set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[16]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[16]}] |
| set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[17]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[17]}] |
| set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[18]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[18]}] |
| set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[19]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[19]}] |
| set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[1]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[1]}] |
| set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[20]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[20]}] |
| set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[21]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[21]}] |
| set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[22]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[22]}] |
| set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[23]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[23]}] |
| set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[24]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[24]}] |
| set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[25]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[25]}] |
| set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[26]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[26]}] |
| set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[27]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[27]}] |
| set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[28]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[28]}] |
| set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[29]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[29]}] |
| set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[2]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[2]}] |
| set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[30]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[30]}] |
| set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[31]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[31]}] |
| set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[3]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[3]}] |
| set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[4]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[4]}] |
| set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[5]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[5]}] |
| set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[6]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[6]}] |
| set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[7]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[7]}] |
| set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[8]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[8]}] |
| set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[9]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[9]}] |
| set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_err_o}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_err_o}] |
| set_max_delay\ |
| -from [get_ports {wbd_clk_int}] 3.5000 |
| set_max_delay\ |
| -from [get_ports {wbd_clk_int}]\ |
| -to [get_ports {wbd_clk_spi}] 3.5000 |
| set_max_delay\ |
| -to [get_ports {spi_debug[0]}] 10.0000 |
| set_max_delay\ |
| -to [get_ports {spi_debug[10]}] 10.0000 |
| set_max_delay\ |
| -to [get_ports {spi_debug[11]}] 10.0000 |
| set_max_delay\ |
| -to [get_ports {spi_debug[12]}] 10.0000 |
| set_max_delay\ |
| -to [get_ports {spi_debug[13]}] 10.0000 |
| set_max_delay\ |
| -to [get_ports {spi_debug[14]}] 10.0000 |
| set_max_delay\ |
| -to [get_ports {spi_debug[15]}] 10.0000 |
| set_max_delay\ |
| -to [get_ports {spi_debug[16]}] 10.0000 |
| set_max_delay\ |
| -to [get_ports {spi_debug[17]}] 10.0000 |
| set_max_delay\ |
| -to [get_ports {spi_debug[18]}] 10.0000 |
| set_max_delay\ |
| -to [get_ports {spi_debug[19]}] 10.0000 |
| set_max_delay\ |
| -to [get_ports {spi_debug[1]}] 10.0000 |
| set_max_delay\ |
| -to [get_ports {spi_debug[20]}] 10.0000 |
| set_max_delay\ |
| -to [get_ports {spi_debug[21]}] 10.0000 |
| set_max_delay\ |
| -to [get_ports {spi_debug[22]}] 10.0000 |
| set_max_delay\ |
| -to [get_ports {spi_debug[23]}] 10.0000 |
| set_max_delay\ |
| -to [get_ports {spi_debug[24]}] 10.0000 |
| set_max_delay\ |
| -to [get_ports {spi_debug[25]}] 10.0000 |
| set_max_delay\ |
| -to [get_ports {spi_debug[26]}] 10.0000 |
| set_max_delay\ |
| -to [get_ports {spi_debug[27]}] 10.0000 |
| set_max_delay\ |
| -to [get_ports {spi_debug[28]}] 10.0000 |
| set_max_delay\ |
| -to [get_ports {spi_debug[29]}] 10.0000 |
| set_max_delay\ |
| -to [get_ports {spi_debug[2]}] 10.0000 |
| set_max_delay\ |
| -to [get_ports {spi_debug[30]}] 10.0000 |
| set_max_delay\ |
| -to [get_ports {spi_debug[31]}] 10.0000 |
| set_max_delay\ |
| -to [get_ports {spi_debug[3]}] 10.0000 |
| set_max_delay\ |
| -to [get_ports {spi_debug[4]}] 10.0000 |
| set_max_delay\ |
| -to [get_ports {spi_debug[5]}] 10.0000 |
| set_max_delay\ |
| -to [get_ports {spi_debug[6]}] 10.0000 |
| set_max_delay\ |
| -to [get_ports {spi_debug[7]}] 10.0000 |
| set_max_delay\ |
| -to [get_ports {spi_debug[8]}] 10.0000 |
| set_max_delay\ |
| -to [get_ports {spi_debug[9]}] 10.0000 |
| set_max_delay\ |
| -to [get_ports {wbd_clk_spi}] 2.0000 |
| ############################################################################### |
| # Environment |
| ############################################################################### |
| set_load -pin_load 0.0334 [get_ports {spi_clk}] |
| set_load -pin_load 0.0334 [get_ports {wbd_ack_o}] |
| set_load -pin_load 0.0334 [get_ports {wbd_clk_spi}] |
| set_load -pin_load 0.0334 [get_ports {wbd_err_o}] |
| set_load -pin_load 0.0334 [get_ports {wbd_lack_o}] |
| set_load -pin_load 0.0334 [get_ports {spi_csn[3]}] |
| set_load -pin_load 0.0334 [get_ports {spi_csn[2]}] |
| set_load -pin_load 0.0334 [get_ports {spi_csn[1]}] |
| set_load -pin_load 0.0334 [get_ports {spi_csn[0]}] |
| set_load -pin_load 0.0334 [get_ports {spi_debug[31]}] |
| set_load -pin_load 0.0334 [get_ports {spi_debug[30]}] |
| set_load -pin_load 0.0334 [get_ports {spi_debug[29]}] |
| set_load -pin_load 0.0334 [get_ports {spi_debug[28]}] |
| set_load -pin_load 0.0334 [get_ports {spi_debug[27]}] |
| set_load -pin_load 0.0334 [get_ports {spi_debug[26]}] |
| set_load -pin_load 0.0334 [get_ports {spi_debug[25]}] |
| set_load -pin_load 0.0334 [get_ports {spi_debug[24]}] |
| set_load -pin_load 0.0334 [get_ports {spi_debug[23]}] |
| set_load -pin_load 0.0334 [get_ports {spi_debug[22]}] |
| set_load -pin_load 0.0334 [get_ports {spi_debug[21]}] |
| set_load -pin_load 0.0334 [get_ports {spi_debug[20]}] |
| set_load -pin_load 0.0334 [get_ports {spi_debug[19]}] |
| set_load -pin_load 0.0334 [get_ports {spi_debug[18]}] |
| set_load -pin_load 0.0334 [get_ports {spi_debug[17]}] |
| set_load -pin_load 0.0334 [get_ports {spi_debug[16]}] |
| set_load -pin_load 0.0334 [get_ports {spi_debug[15]}] |
| set_load -pin_load 0.0334 [get_ports {spi_debug[14]}] |
| set_load -pin_load 0.0334 [get_ports {spi_debug[13]}] |
| set_load -pin_load 0.0334 [get_ports {spi_debug[12]}] |
| set_load -pin_load 0.0334 [get_ports {spi_debug[11]}] |
| set_load -pin_load 0.0334 [get_ports {spi_debug[10]}] |
| set_load -pin_load 0.0334 [get_ports {spi_debug[9]}] |
| set_load -pin_load 0.0334 [get_ports {spi_debug[8]}] |
| set_load -pin_load 0.0334 [get_ports {spi_debug[7]}] |
| set_load -pin_load 0.0334 [get_ports {spi_debug[6]}] |
| set_load -pin_load 0.0334 [get_ports {spi_debug[5]}] |
| set_load -pin_load 0.0334 [get_ports {spi_debug[4]}] |
| set_load -pin_load 0.0334 [get_ports {spi_debug[3]}] |
| set_load -pin_load 0.0334 [get_ports {spi_debug[2]}] |
| set_load -pin_load 0.0334 [get_ports {spi_debug[1]}] |
| set_load -pin_load 0.0334 [get_ports {spi_debug[0]}] |
| set_load -pin_load 0.0334 [get_ports {spi_oen[3]}] |
| set_load -pin_load 0.0334 [get_ports {spi_oen[2]}] |
| set_load -pin_load 0.0334 [get_ports {spi_oen[1]}] |
| set_load -pin_load 0.0334 [get_ports {spi_oen[0]}] |
| set_load -pin_load 0.0334 [get_ports {spi_sdo[3]}] |
| set_load -pin_load 0.0334 [get_ports {spi_sdo[2]}] |
| set_load -pin_load 0.0334 [get_ports {spi_sdo[1]}] |
| set_load -pin_load 0.0334 [get_ports {spi_sdo[0]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dat_o[31]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dat_o[30]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dat_o[29]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dat_o[28]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dat_o[27]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dat_o[26]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dat_o[25]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dat_o[24]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dat_o[23]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dat_o[22]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dat_o[21]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dat_o[20]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dat_o[19]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dat_o[18]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dat_o[17]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dat_o[16]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dat_o[15]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dat_o[14]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dat_o[13]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dat_o[12]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dat_o[11]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dat_o[10]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dat_o[9]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dat_o[8]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dat_o[7]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dat_o[6]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dat_o[5]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dat_o[4]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dat_o[3]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dat_o[2]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dat_o[1]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dat_o[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_init_bypass}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mclk}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst_n}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_pre_sram}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sram}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_bry_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_stb_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_we_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_sp_co[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_sp_co[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_sp_co[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_sp_co[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_spi[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_spi[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_spi[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_spi[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spi_sdi[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spi_sdi[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spi_sdi[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spi_sdi[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_flash[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_flash[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_bl_i[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_bl_i[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_bl_i[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_bl_i[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_bl_i[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_bl_i[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_bl_i[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_bl_i[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_bl_i[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_bl_i[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_sel_i[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_sel_i[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_sel_i[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_sel_i[0]}] |
| set_case_analysis 0 [get_ports {cfg_cska_sp_co[0]}] |
| set_case_analysis 0 [get_ports {cfg_cska_sp_co[1]}] |
| set_case_analysis 0 [get_ports {cfg_cska_sp_co[2]}] |
| set_case_analysis 0 [get_ports {cfg_cska_sp_co[3]}] |
| set_case_analysis 0 [get_ports {cfg_cska_spi[0]}] |
| set_case_analysis 0 [get_ports {cfg_cska_spi[1]}] |
| set_case_analysis 0 [get_ports {cfg_cska_spi[2]}] |
| set_case_analysis 0 [get_ports {cfg_cska_spi[3]}] |
| set_timing_derate -early 0.9500 |
| set_timing_derate -late 1.0500 |
| ############################################################################### |
| # Design Rules |
| ############################################################################### |
| set_max_transition 1.0000 [current_design] |
| set_max_capacitance 0.2000 [current_design] |
| set_max_fanout 10.0000 [current_design] |