final gds oasis
diff --git a/mpw_precheck/logs/gds.info b/mpw_precheck/logs/gds.info
new file mode 100644
index 0000000..3d11973
--- /dev/null
+++ b/mpw_precheck/logs/gds.info
@@ -0,0 +1 @@
+user_project_wrapper.gds: 0507457456d10a63886f8f85f5ef273429ebec32
\ No newline at end of file
diff --git a/mpw_precheck/logs/git.info b/mpw_precheck/logs/git.info
new file mode 100644
index 0000000..5ac120c
--- /dev/null
+++ b/mpw_precheck/logs/git.info
@@ -0,0 +1,3 @@
+Repository: https://github.com/gitercn/riscduino_qcore_folk.git
+Branch: main
+Commit: aa75e446fa7757dd79717f376e848a4d369a48b5
diff --git a/mpw_precheck/logs/klayout_beol_check.log b/mpw_precheck/logs/klayout_beol_check.log
new file mode 100644
index 0000000..4533063
--- /dev/null
+++ b/mpw_precheck/logs/klayout_beol_check.log
@@ -0,0 +1,992 @@
+/opt/checks/tech-files/sky130A_mr.drc:38: warning: already initialized constant DRC::DRCEngine::FEOL
+/opt/checks/tech-files/sky130A_mr.drc:28: warning: previous definition of FEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:42: warning: already initialized constant DRC::DRCEngine::BEOL
+/opt/checks/tech-files/sky130A_mr.drc:29: warning: previous definition of BEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:50: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/opt/checks/tech-files/sky130A_mr.drc:30: warning: previous definition of OFFGRID was here
+/opt/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::SEAL
+/opt/checks/tech-files/sky130A_mr.drc:31: warning: previous definition of SEAL was here
+/opt/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/opt/checks/tech-files/sky130A_mr.drc:32: warning: previous definition of FLOATING_MET was here
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+DRC section
+BEOL section
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+START: 67/44 (mcon)
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+END: 76/20 (pad)
+Writing report database: /mnt/uffs/user/u7829_giters/design/riscduino_qcore_folk/jobs/mpw_precheck/41322373-5695-4474-8666-baf2b4c97e4c/outputs/reports/klayout_beol_check.xml ..
+Total elapsed: 1920.690s Memory: 6221.00M
diff --git a/mpw_precheck/logs/klayout_beol_check.total b/mpw_precheck/logs/klayout_beol_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_beol_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/klayout_feol_check.log b/mpw_precheck/logs/klayout_feol_check.log
new file mode 100644
index 0000000..e95d703
--- /dev/null
+++ b/mpw_precheck/logs/klayout_feol_check.log
@@ -0,0 +1,789 @@
+/opt/checks/tech-files/sky130A_mr.drc:36: warning: already initialized constant DRC::DRCEngine::FEOL
+/opt/checks/tech-files/sky130A_mr.drc:28: warning: previous definition of FEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:44: warning: already initialized constant DRC::DRCEngine::BEOL
+/opt/checks/tech-files/sky130A_mr.drc:29: warning: previous definition of BEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:50: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/opt/checks/tech-files/sky130A_mr.drc:30: warning: previous definition of OFFGRID was here
+/opt/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::SEAL
+/opt/checks/tech-files/sky130A_mr.drc:31: warning: previous definition of SEAL was here
+/opt/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/opt/checks/tech-files/sky130A_mr.drc:32: warning: previous definition of FLOATING_MET was here
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+DRC section
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+Writing report database: /mnt/uffs/user/u7829_giters/design/riscduino_qcore_folk/jobs/mpw_precheck/41322373-5695-4474-8666-baf2b4c97e4c/outputs/reports/klayout_feol_check.xml ..
+Total elapsed: 168.080s Memory: 1735.00M
diff --git a/mpw_precheck/logs/klayout_feol_check.total b/mpw_precheck/logs/klayout_feol_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_feol_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/klayout_met_min_ca_density_check.log b/mpw_precheck/logs/klayout_met_min_ca_density_check.log
new file mode 100644
index 0000000..126efc5
--- /dev/null
+++ b/mpw_precheck/logs/klayout_met_min_ca_density_check.log
@@ -0,0 +1,79 @@
+"polygons" in: met_min_ca_density.lydrc:35
+ Polygons (raw): 7559230 (flat) 330585 (hierarchical)
+ Elapsed: 0.370s Memory: 910.00M
+"polygons" in: met_min_ca_density.lydrc:36
+ Polygons (raw): 9291091 (flat) 325008 (hierarchical)
+ Elapsed: 0.300s Memory: 917.00M
+"polygons" in: met_min_ca_density.lydrc:38
+ Polygons (raw): 7983902 (flat) 1787984 (hierarchical)
+ Elapsed: 1.180s Memory: 965.00M
+"polygons" in: met_min_ca_density.lydrc:39
+ Polygons (raw): 1425250 (flat) 496733 (hierarchical)
+ Elapsed: 0.420s Memory: 973.00M
+"polygons" in: met_min_ca_density.lydrc:41
+ Polygons (raw): 3055030 (flat) 879858 (hierarchical)
+ Elapsed: 0.690s Memory: 997.00M
+"polygons" in: met_min_ca_density.lydrc:42
+ Polygons (raw): 198913 (flat) 125805 (hierarchical)
+ Elapsed: 0.210s Memory: 998.00M
+"polygons" in: met_min_ca_density.lydrc:44
+ Polygons (raw): 518904 (flat) 277712 (hierarchical)
+ Elapsed: 0.310s Memory: 1004.00M
+"polygons" in: met_min_ca_density.lydrc:45
+ Polygons (raw): 128022 (flat) 86696 (hierarchical)
+ Elapsed: 0.190s Memory: 1006.00M
+"polygons" in: met_min_ca_density.lydrc:47
+ Polygons (raw): 89862 (flat) 45956 (hierarchical)
+ Elapsed: 0.170s Memory: 1007.00M
+"polygons" in: met_min_ca_density.lydrc:48
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 1007.00M
+"polygons" in: met_min_ca_density.lydrc:49
+ Polygons (raw): 5138 (flat) 5138 (hierarchical)
+ Elapsed: 0.020s Memory: 1007.00M
+"polygons" in: met_min_ca_density.lydrc:51
+ Polygons (raw): 357 (flat) 357 (hierarchical)
+ Elapsed: 0.010s Memory: 1007.00M
+"input" in: met_min_ca_density.lydrc:53
+ Polygons (raw): 172747 (flat) 210 (hierarchical)
+ Elapsed: 0.140s Memory: 1008.00M
+"area" in: met_min_ca_density.lydrc:55
+ Elapsed: 3.680s Memory: 1026.00M
+"polygons" in: met_min_ca_density.lydrc:59
+ Polygons (raw): 7559230 (flat) 330585 (hierarchical)
+ Elapsed: 0.320s Memory: 1026.00M
+"area" in: met_min_ca_density.lydrc:59
+ Elapsed: 30.500s Memory: 1469.00M
+li1_ca_density is 0.7387596520664694
+"polygons" in: met_min_ca_density.lydrc:69
+ Polygons (raw): 7983902 (flat) 1787984 (hierarchical)
+ Elapsed: 1.180s Memory: 1469.00M
+"area" in: met_min_ca_density.lydrc:69
+ Elapsed: 32.660s Memory: 1529.00M
+m1_ca_density is 0.8384307137492217
+"polygons" in: met_min_ca_density.lydrc:79
+ Polygons (raw): 3055030 (flat) 879858 (hierarchical)
+ Elapsed: 0.700s Memory: 1529.00M
+"area" in: met_min_ca_density.lydrc:79
+ Elapsed: 6.780s Memory: 1532.00M
+m2_ca_density is 0.8970580263294871
+"polygons" in: met_min_ca_density.lydrc:89
+ Polygons (raw): 518904 (flat) 277712 (hierarchical)
+ Elapsed: 0.330s Memory: 1532.00M
+"area" in: met_min_ca_density.lydrc:89
+ Elapsed: 2.200s Memory: 1532.00M
+m3_ca_density is 0.9644124229087212
+"polygons" in: met_min_ca_density.lydrc:99
+ Polygons (raw): 89862 (flat) 45956 (hierarchical)
+ Elapsed: 0.170s Memory: 1532.00M
+"area" in: met_min_ca_density.lydrc:99
+ Elapsed: 0.520s Memory: 1532.00M
+m4_ca_density is 0.9074337862045649
+"polygons" in: met_min_ca_density.lydrc:109
+ Polygons (raw): 357 (flat) 357 (hierarchical)
+ Elapsed: 0.010s Memory: 1532.00M
+"area" in: met_min_ca_density.lydrc:109
+ Elapsed: 0.220s Memory: 1532.00M
+m5_ca_density is 0.9594726140255293
+Writing report database: /mnt/uffs/user/u7829_giters/design/riscduino_qcore_folk/jobs/mpw_precheck/41322373-5695-4474-8666-baf2b4c97e4c/outputs/reports/klayout_met_min_ca_density_check.xml ..
+Total elapsed: 88.400s Memory: 1508.00M
diff --git a/mpw_precheck/logs/klayout_met_min_ca_density_check.total b/mpw_precheck/logs/klayout_met_min_ca_density_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_met_min_ca_density_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/klayout_offgrid_check.log b/mpw_precheck/logs/klayout_offgrid_check.log
new file mode 100644
index 0000000..40257f9
--- /dev/null
+++ b/mpw_precheck/logs/klayout_offgrid_check.log
@@ -0,0 +1,755 @@
+/opt/checks/tech-files/sky130A_mr.drc:38: warning: already initialized constant DRC::DRCEngine::FEOL
+/opt/checks/tech-files/sky130A_mr.drc:28: warning: previous definition of FEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:44: warning: already initialized constant DRC::DRCEngine::BEOL
+/opt/checks/tech-files/sky130A_mr.drc:29: warning: previous definition of BEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:48: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/opt/checks/tech-files/sky130A_mr.drc:30: warning: previous definition of OFFGRID was here
+/opt/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::SEAL
+/opt/checks/tech-files/sky130A_mr.drc:31: warning: previous definition of SEAL was here
+/opt/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/opt/checks/tech-files/sky130A_mr.drc:32: warning: previous definition of FLOATING_MET was here
+"input" in: sky130A_mr.drc:112
+ Polygons (raw): 1521004 (flat) 849 (hierarchical)
+ Elapsed: 0.200s Memory: 902.00M
+"polygons" in: sky130A_mr.drc:113
+ Polygons (raw): 293834 (flat) 31 (hierarchical)
+ Elapsed: 0.140s Memory: 902.00M
+"polygons" in: sky130A_mr.drc:114
+ Polygons (raw): 720316 (flat) 318 (hierarchical)
+ Elapsed: 0.120s Memory: 902.00M
+"polygons" in: sky130A_mr.drc:115
+ Polygons (raw): 3 (flat) 1 (hierarchical)
+ Elapsed: 0.010s Memory: 902.00M
+"polygons" in: sky130A_mr.drc:116
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 902.00M
+"polygons" in: sky130A_mr.drc:117
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 902.00M
+"polygons" in: sky130A_mr.drc:118
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 902.00M
+"polygons" in: sky130A_mr.drc:119
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 902.00M
+"polygons" in: sky130A_mr.drc:120
+ Polygons (raw): 716159 (flat) 254 (hierarchical)
+ Elapsed: 0.110s Memory: 902.00M
+"polygons" in: sky130A_mr.drc:121
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 902.00M
+"polygons" in: sky130A_mr.drc:122
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 902.00M
+"polygons" in: sky130A_mr.drc:123
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 902.00M
+"polygons" in: sky130A_mr.drc:124
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 902.00M
+"polygons" in: sky130A_mr.drc:125
+ Polygons (raw): 2571855 (flat) 2769 (hierarchical)
+ Elapsed: 0.140s Memory: 902.00M
+"polygons" in: sky130A_mr.drc:126
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 902.00M
+"polygons" in: sky130A_mr.drc:127
+ Polygons (raw): 987830 (flat) 352 (hierarchical)
+ Elapsed: 0.120s Memory: 902.00M
+"polygons" in: sky130A_mr.drc:128
+ Polygons (raw): 885860 (flat) 342 (hierarchical)
+ Elapsed: 0.120s Memory: 902.00M
+"polygons" in: sky130A_mr.drc:129
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 902.00M
+"polygons" in: sky130A_mr.drc:130
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 902.00M
+"polygons" in: sky130A_mr.drc:131
+ Polygons (raw): 774121 (flat) 354 (hierarchical)
+ Elapsed: 0.140s Memory: 903.00M
+"polygons" in: sky130A_mr.drc:132
+ Polygons (raw): 8450751 (flat) 8631 (hierarchical)
+ Elapsed: 0.130s Memory: 903.00M
+"polygons" in: sky130A_mr.drc:134
+ Polygons (raw): 6113313 (flat) 328485 (hierarchical)
+ Elapsed: 0.320s Memory: 912.00M
+"polygons" in: sky130A_mr.drc:135
+ Polygons (raw): 9291091 (flat) 325008 (hierarchical)
+ Elapsed: 0.300s Memory: 919.00M
+"polygons" in: sky130A_mr.drc:137
+ Polygons (raw): 6369188 (flat) 1787459 (hierarchical)
+ Elapsed: 1.180s Memory: 967.00M
+"polygons" in: sky130A_mr.drc:138
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+ Elapsed: 0.430s Memory: 975.00M
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+ Elapsed: 0.680s Memory: 998.00M
+"polygons" in: sky130A_mr.drc:141
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+ Elapsed: 0.220s Memory: 999.00M
+"polygons" in: sky130A_mr.drc:143
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+ Elapsed: 0.310s Memory: 1006.00M
+"polygons" in: sky130A_mr.drc:144
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+ Elapsed: 0.190s Memory: 1008.00M
+"polygons" in: sky130A_mr.drc:146
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+ Elapsed: 0.170s Memory: 1009.00M
+"polygons" in: sky130A_mr.drc:147
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+ Elapsed: 0.010s Memory: 1009.00M
+"polygons" in: sky130A_mr.drc:149
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+ Elapsed: 0.010s Memory: 1009.00M
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+ Elapsed: 0.010s Memory: 1009.00M
+"polygons" in: sky130A_mr.drc:157
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+ Elapsed: 0.000s Memory: 1009.00M
+"polygons" in: sky130A_mr.drc:158
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+"polygons" in: sky130A_mr.drc:160
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+ Elapsed: 0.010s Memory: 1009.00M
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+"polygons" in: sky130A_mr.drc:168
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+ Elapsed: 0.130s Memory: 1010.00M
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+"polygons" in: sky130A_mr.drc:176
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+"polygons" in: sky130A_mr.drc:177
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+ Elapsed: 0.010s Memory: 1010.00M
+"polygons" in: sky130A_mr.drc:178
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+"polygons" in: sky130A_mr.drc:179
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+ Elapsed: 0.010s Memory: 1010.00M
+"polygons" in: sky130A_mr.drc:180
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+ Elapsed: 0.000s Memory: 1010.00M
+"polygons" in: sky130A_mr.drc:181
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+ Elapsed: 0.130s Memory: 1010.00M
+"polygons" in: sky130A_mr.drc:182
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+ Elapsed: 0.010s Memory: 1010.00M
+"polygons" in: sky130A_mr.drc:183
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+ Elapsed: 0.010s Memory: 1010.00M
+"polygons" in: sky130A_mr.drc:184
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+ Elapsed: 0.000s Memory: 1010.00M
+"polygons" in: sky130A_mr.drc:185
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+"polygons" in: sky130A_mr.drc:186
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+ Elapsed: 0.010s Memory: 1010.00M
+"polygons" in: sky130A_mr.drc:187
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+"polygons" in: sky130A_mr.drc:188
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+"polygons" in: sky130A_mr.drc:189
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+"polygons" in: sky130A_mr.drc:190
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+"polygons" in: sky130A_mr.drc:191
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+"polygons" in: sky130A_mr.drc:192
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+"polygons" in: sky130A_mr.drc:196
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+"polygons" in: sky130A_mr.drc:197
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+"polygons" in: sky130A_mr.drc:198
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+"polygons" in: sky130A_mr.drc:199
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+"polygons" in: sky130A_mr.drc:200
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+ Elapsed: 0.010s Memory: 1010.00M
+"polygons" in: sky130A_mr.drc:201
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+"polygons" in: sky130A_mr.drc:202
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+ Elapsed: 0.010s Memory: 1010.00M
+"polygons" in: sky130A_mr.drc:203
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+DRC section
+OFFGRID-ANGLES section
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+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.280s Memory: 1016.00M
+"output" in: sky130A_mr.drc:690
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+ Elapsed: 0.010s Memory: 1016.00M
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+ Elapsed: 0.010s Memory: 1016.00M
+"output" in: sky130A_mr.drc:691
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+"ongrid" in: sky130A_mr.drc:692
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 7.990s Memory: 1141.00M
+"output" in: sky130A_mr.drc:692
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 1141.00M
+"with_angle" in: sky130A_mr.drc:693
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+"output" in: sky130A_mr.drc:693
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+"ongrid" in: sky130A_mr.drc:694
+ Edge pairs: 0 (flat) 0 (hierarchical)
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+"output" in: sky130A_mr.drc:695
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+"ongrid" in: sky130A_mr.drc:696
+ Edge pairs: 0 (flat) 0 (hierarchical)
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+"output" in: sky130A_mr.drc:696
+ Edge pairs: 0 (flat) 0 (hierarchical)
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new file mode 100644
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diff --git a/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.log b/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
new file mode 100644
index 0000000..5ae177e
--- /dev/null
+++ b/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
@@ -0,0 +1,29 @@
+Running pin_label_purposes_overlapping_drawing.rb.drc on file=/root/riscduino_qcore_folk/gds/user_project_wrapper.gds, topcell=user_project_wrapper, output to /mnt/uffs/user/u7829_giters/design/riscduino_qcore_folk/jobs/mpw_precheck/41322373-5695-4474-8666-baf2b4c97e4c/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
+ deep:true tiled:false threads:8
+--- #err|description, table for cell: user_project_wrapper
+NO-Check ---- pwell:64/44/EMP 122/16/dat 64/59/EMP 44/16/EMP 44/5/EMP
+ ---- nwell:64/20/dat 64/16/dat 64/5/EMP
+ ---- diff:65/20/dat 65/16/EMP 65/6/EMP
+ ---- tap:65/44/dat 65/48/EMP 65/5/EMP
+ ---- poly:66/20/dat 66/16/EMP 66/5/EMP
+ ---- licon1:66/44/dat 66/58/EMP
+ ---- li1:67/20/dat 67/16/dat 67/5/EMP
+ ---- mcon:67/44/dat 67/48/EMP
+ ---- met1:68/20/dat 68/16/dat 68/5/dat
+ ---- via:68/44/dat 68/58/EMP
+ ---- met2:69/20/dat 69/16/dat 69/5/dat
+ ---- via2:69/44/dat 69/58/EMP
+ ---- met3:70/20/dat 70/16/dat 70/5/dat
+ ---- via3:70/44/dat 70/48/EMP
+ ---- met4:71/20/dat 71/16/dat 71/5/dat
+ ---- via4:71/44/dat 71/48/EMP
+ ---- met5:72/20/dat 72/16/dat 72/5/EMP
+ ---- pad:76/20/EMP 76/5/EMP 76/16/EMP
+ ---- pnp:82/44/EMP 82/59/EMP
+ ---- npn:82/20/EMP 82/5/EMP
+ ---- rdl:74/20/EMP 74/16/EMP 74/5/EMP
+ ---- inductor:82/24/EMP 82/25/EMP
+ 0 total error(s) among 0 error type(s), 33 checks, cell: user_project_wrapper
+Writing report...
+VmPeak: 2531348 kB
+VmHWM: 1202836 kB
diff --git a/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.total b/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/klayout_zeroarea_check.log b/mpw_precheck/logs/klayout_zeroarea_check.log
new file mode 100644
index 0000000..1777859
--- /dev/null
+++ b/mpw_precheck/logs/klayout_zeroarea_check.log
@@ -0,0 +1,4 @@
+0 zero-area shapes
+writing to /mnt/uffs/user/u7829_giters/design/riscduino_qcore_folk/jobs/mpw_precheck/41322373-5695-4474-8666-baf2b4c97e4c/outputs/user_project_wrapper_no_zero_areas.gds
+VmPeak: 1836676 kB
+VmHWM: 1431108 kB
diff --git a/mpw_precheck/logs/klayout_zeroarea_check.total b/mpw_precheck/logs/klayout_zeroarea_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_zeroarea_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/magic_drc_check.log b/mpw_precheck/logs/magic_drc_check.log
new file mode 100644
index 0000000..020b743
--- /dev/null
+++ b/mpw_precheck/logs/magic_drc_check.log
@@ -0,0 +1,552 @@
+
+Magic 8.3 revision 274 - Compiled on Fri Mar 4 22:53:06 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+ mvobsactive ubm
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/checks/drc_checks/magic/magic_drc_check.tcl" from command line.
+Detected an SRAM module
+Pre-loading a maglef of the SRAM block: sky130_sram_2kbyte_1rw1r_32x512_8
+Scaled magic input cell sky130_sram_2kbyte_1rw1r_32x512_8 geometry by factor of 2
+Warning: Calma reading is not undoable! I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: user_project_wrapper
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_39".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_19".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_14".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_13".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_7".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_38".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_33".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_32".
+Reading "sky130_fd_bd_sram__openram_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_addr_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wmask_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_addr_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_data_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_16".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_29".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_28".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_11".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_360_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_12".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sli_dactive".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w0_740_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w1_260_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m7_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m7_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m24_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m24_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_14".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m8_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m8_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_13".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_12".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_11".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_17".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_delay_chain".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m18_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m18_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_16".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_5".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dactive".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand3_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m22_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m22_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_15".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m42_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m42_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_10".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m15_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m15_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_9".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m5_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_8".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w1_260_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_7".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_rw".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_5".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m41_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m41_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_20".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m14_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m14_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_19".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_18".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_6".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_r".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_20".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_17".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_15".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w7_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w7_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec_0".
+CIF file read warning: CIF style sky130(vendor): units rescaled by factor of 5 / 1
+Reading "sky130_fd_bd_sram__openram_dp_nand2_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec".
+Reading "sky130_fd_bd_sram__openram_dp_nand3_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and3_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode3x8".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_decoder".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_address_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_address".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_27".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_26".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_25".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_24".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w2_880_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array_0".
+Reading "sky130_fd_bd_sram__openram_sense_amp".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_sense_amp_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_23".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_21".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_22".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w0_550_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_data_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_write_mask_and_array".
+Reading "sky130_fd_bd_sram__openram_write_driver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_write_driver_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_data".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_9".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_8".
+Reading "sky130_fd_bd_sram__openram_dp_cell_cap_row".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_cap_row" (byte position 2620068): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_cap_row" (byte position 2620772): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_cap_row" (byte position 2621732): Unknown layer/datatype in boundary, layer=22 type=21
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array".
+Reading "sky130_fd_bd_sram__openram_dp_cell_cap_col".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array_0".
+Reading "sky130_fd_bd_sram__openram_dp_cell_dummy".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3113978): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3117754): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3121946): Unknown layer/datatype in boundary, layer=22 type=21
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3126746): Unknown layer/datatype in boundary, layer=22 type=22
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3128794): Unknown layer/datatype in boundary, layer=235 type=0
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dummy_array".
+Reading "sky130_fd_bd_sram__openram_dp_cell_replica".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3308236): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3312012): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3316204): Unknown layer/datatype in boundary, layer=22 type=21
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3322668): Unknown layer/datatype in boundary, layer=22 type=22
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3324844): Unknown layer/datatype in boundary, layer=235 type=0
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_column_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_column".
+Reading "sky130_fd_bd_sram__openram_dp_cell".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3565294): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3569070): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3573262): Unknown layer/datatype in boundary, layer=22 type=21
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3579726): Unknown layer/datatype in boundary, layer=22 type=22
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3581902): Unknown layer/datatype in boundary, layer=235 type=0
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_bitcell_array".
+ 5000 uses
+ 10000 uses
+ 15000 uses
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_bitcell_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_bank".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8".
+Warning: cell sky130_sram_2kbyte_1rw1r_32x512_8 already existed before reading GDS!
+Using pre-existing cell definition
+Reading "sky130_fd_sc_hd__and2_2".
+Reading "sky130_fd_sc_hd__or4_2".
+Reading "sky130_fd_sc_hd__o41a_2".
+Reading "sky130_fd_sc_hd__o311a_2".
+Reading "sky130_fd_sc_hd__and3_2".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__clkbuf_2".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__clkinv_2".
+Reading "sky130_fd_sc_hd__mux2_1".
+Reading "sky130_fd_sc_hd__o32a_2".
+Reading "sky130_fd_sc_hd__clkinv_8".
+Reading "sky130_fd_sc_hd__a221o_2".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_fd_sc_hd__o31a_2".
+Reading "sky130_fd_sc_hd__a22oi_2".
+Reading "sky130_fd_sc_hd__a21bo_2".
+Reading "sky130_fd_sc_hd__a21o_2".
+Reading "sky130_fd_sc_hd__o22a_2".
+Reading "sky130_fd_sc_hd__o211a_2".
+Reading "sky130_fd_sc_hd__and4_2".
+Reading "sky130_fd_sc_hd__a31o_2".
+Reading "sky130_fd_sc_hd__nand2_2".
+Reading "sky130_fd_sc_hd__o2bb2ai_2".
+Reading "sky130_fd_sc_hd__o21ai_2".
+Reading "sky130_fd_sc_hd__o221a_2".
+Reading "sky130_fd_sc_hd__a2bb2o_2".
+Reading "sky130_fd_sc_hd__or2_2".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__or3_2".
+Reading "sky130_fd_sc_hd__a21oi_2".
+Reading "sky130_fd_sc_hd__nor2_2".
+Reading "sky130_fd_sc_hd__a22o_2".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "sky130_fd_sc_hd__dfrtp_2".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__buf_1".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_ef_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__dfrtp_4".
+Reading "sky130_fd_sc_hd__dfrtp_1".
+Reading "sky130_fd_sc_hd__dfstp_2".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__xnor2_1".
+Reading "sky130_fd_sc_hd__xor2_1".
+Reading "sky130_fd_sc_hd__o21ai_1".
+Reading "sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "sky130_fd_sc_hd__or2b_1".
+Reading "sky130_fd_sc_hd__o211a_1".
+Reading "sky130_fd_sc_hd__or2_1".
+Reading "sky130_fd_sc_hd__dfstp_1".
+Reading "sky130_fd_sc_hd__a21oi_1".
+Reading "sky130_fd_sc_hd__a221o_1".
+Reading "sky130_fd_sc_hd__a31o_1".
+Reading "sky130_fd_sc_hd__nand2_1".
+Reading "sky130_fd_sc_hd__o21a_1".
+Reading "sky130_fd_sc_hd__o2bb2a_1".
+Reading "sky130_fd_sc_hd__nor2_1".
+Reading "sky130_fd_sc_hd__o21ai_4".
+Reading "sky130_fd_sc_hd__clkbuf_4".
+Reading "sky130_fd_sc_hd__and3_1".
+Reading "sky130_fd_sc_hd__nand3_2".
+Reading "sky130_fd_sc_hd__and2_1".
+Reading "sky130_fd_sc_hd__a21o_1".
+Reading "sky130_fd_sc_hd__a311o_1".
+Reading "sky130_fd_sc_hd__a21bo_1".
+Reading "sky130_fd_sc_hd__a2bb2o_1".
+Reading "sky130_fd_sc_hd__o22a_1".
+Reading "sky130_fd_sc_hd__a211o_1".
+Reading "sky130_fd_sc_hd__a22oi_1".
+Reading "sky130_fd_sc_hd__a22o_1".
+Reading "sky130_fd_sc_hd__and4bb_2".
+Reading "sky130_fd_sc_hd__or2_4".
+Reading "sky130_fd_sc_hd__or4b_1".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "sky130_fd_sc_hd__mux2_2".
+Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hd__a32o_1".
+Reading "sky130_fd_sc_hd__and2b_1".
+Reading "sky130_fd_sc_hd__a22o_4".
+Reading "sky130_fd_sc_hd__or3_1".
+Reading "sky130_fd_sc_hd__buf_12".
+Reading "sky130_fd_sc_hd__o221a_1".
+Reading "sky130_fd_sc_hd__xor2_2".
+Reading "sky130_fd_sc_hd__nand3_1".
+Reading "sky130_fd_sc_hd__or4b_4".
+Reading "sky130_fd_sc_hd__o211ai_4".
+Reading "sky130_fd_sc_hd__mux4_1".
+Reading "sky130_fd_sc_hd__or3b_1".
+Reading "sky130_fd_sc_hd__mux4_2".
+Reading "sky130_fd_sc_hd__or2b_4".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__nand2_8".
+Reading "sky130_fd_sc_hd__or4_1".
+Reading "sky130_fd_sc_hd__clkbuf_8".
+Reading "sky130_fd_sc_hd__buf_6".
+Reading "sky130_fd_sc_hd__a221o_4".
+Reading "sky130_fd_sc_hd__mux2_8".
+Reading "sky130_fd_sc_hd__a22oi_4".
+Reading "sky130_fd_sc_hd__a221oi_4".
+Reading "sky130_fd_sc_hd__a21o_4".
+Reading "sky130_fd_sc_hd__o221ai_4".
+Reading "sky130_fd_sc_hd__a41o_4".
+Reading "sky130_fd_sc_hd__a211o_4".
+Reading "sky130_fd_sc_hd__o31a_1".
+Reading "sky130_fd_sc_hd__nor4_4".
+Reading "sky130_fd_sc_hd__or4_4".
+Reading "sky130_fd_sc_hd__o211ai_1".
+Reading "sky130_fd_sc_hd__o221a_4".
+Reading "sky130_fd_sc_hd__o31a_4".
+Reading "sky130_fd_sc_hd__o311a_1".
+Reading "sky130_fd_sc_hd__nand4_1".
+Reading "sky130_fd_sc_hd__o211ai_2".
+Reading "sky130_fd_sc_hd__nand4b_1".
+Reading "sky130_fd_sc_hd__and4_1".
+Reading "sky130_fd_sc_hd__or3_4".
+Reading "sky130_fd_sc_hd__and4_4".
+Reading "sky130_fd_sc_hd__o31ai_1".
+Reading "sky130_fd_sc_hd__or4bb_1".
+Reading "sky130_fd_sc_hd__o21ba_1".
+Reading "sky130_fd_sc_hd__and4b_2".
+Reading "sky130_fd_sc_hd__a221oi_1".
+Reading "sky130_fd_sc_hd__nand4_4".
+Reading "sky130_fd_sc_hd__and4b_4".
+Reading "sky130_fd_sc_hd__and4bb_4".
+Reading "sky130_fd_sc_hd__nand2_4".
+Reading "sky130_fd_sc_hd__or4bb_4".
+Reading "sky130_fd_sc_hd__and4b_1".
+Reading "sky130_fd_sc_hd__a32o_4".
+Reading "sky130_fd_sc_hd__dlygate4sd1_1".
+Reading "sky130_fd_sc_hd__o32a_1".
+Reading "sky130_fd_sc_hd__nor4b_4".
+Reading "sky130_fd_sc_hd__nor3_4".
+Reading "sky130_fd_sc_hd__o31ai_4".
+Reading "sky130_fd_sc_hd__and3b_4".
+Reading "sky130_fd_sc_hd__and3_4".
+Reading "sky130_fd_sc_hd__o31ai_2".
+Reading "sky130_fd_sc_hd__a211oi_4".
+Reading "sky130_fd_sc_hd__o22a_4".
+Reading "sky130_fd_sc_hd__nor4_2".
+Reading "sky130_fd_sc_hd__a41o_2".
+Reading "sky130_fd_sc_hd__inv_6".
+Reading "sky130_fd_sc_hd__nand3_4".
+Reading "sky130_fd_sc_hd__o2bb2ai_1".
+Reading "sky130_fd_sc_hd__clkinv_4".
+Reading "sky130_fd_sc_hd__a2111o_4".
+Reading "sky130_fd_sc_hd__and2b_4".
+Reading "sky130_fd_sc_hd__a2bb2o_4".
+Reading "sky130_fd_sc_hd__o21a_4".
+Reading "sky130_fd_sc_hd__o211a_4".
+Reading "sky130_fd_sc_hd__a21oi_4".
+Reading "sky130_fd_sc_hd__o311a_4".
+Reading "sky130_fd_sc_hd__a211o_2".
+Reading "sky130_fd_sc_hd__a32oi_4".
+Reading "sky130_fd_sc_hd__and3b_2".
+Reading "sky130_fd_sc_hd__and3b_1".
+Reading "sky130_fd_sc_hd__nor4_1".
+Reading "sky130_fd_sc_hd__and4bb_1".
+Reading "sky130_fd_sc_hd__a211oi_1".
+Reading "sky130_fd_sc_hd__mux2_4".
+Reading "sky130_fd_sc_hd__nor3_2".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "sky130_fd_sc_hd__or4b_2".
+Reading "ycr4_iconnect".
+ 5000 uses
+ 10000 uses
+ 15000 uses
+ 20000 uses
+ 25000 uses
+ 30000 uses
+ 35000 uses
+ 40000 uses
+ 45000 uses
+ 50000 uses
+ 55000 uses
+ 60000 uses
+ 65000 uses
+ 70000 uses
+ 75000 uses
+Reading "sky130_fd_sc_hd__o21a_2".
+Reading "sky130_fd_sc_hd__a32o_2".
+Reading "sky130_fd_sc_hd__o22ai_2".
+Reading "sky130_fd_sc_hd__a311o_2".
+Reading "sky130_fd_sc_hd__a41o_1".
+Reading "sky130_fd_sc_hd__o21bai_2".
+Reading "sky130_fd_sc_hd__nor3_1".
+Reading "sky130_fd_sc_hd__a21boi_1".
+Reading "sky130_fd_sc_hd__xnor2_2".
+Reading "sky130_fd_sc_hd__a2111o_2".
+Reading "sky130_fd_sc_hd__o21bai_1".
+Reading "sky130_fd_sc_hd__o2111a_1".
+Reading "sky130_fd_sc_hd__a31oi_4".
+Reading "sky130_fd_sc_hd__a2111oi_4".
+Reading "sky130_fd_sc_hd__nand4_2".
+Reading "sky130_fd_sc_hd__o22ai_1".
+Reading "sky130_fd_sc_hd__a31oi_1".
+Reading "sky130_fd_sc_hd__a311oi_1".
+Reading "sky130_fd_sc_hd__or2b_2".
+Reading "sky130_fd_sc_hd__xnor2_4".
+Reading "sky130_fd_sc_hd__or3b_2".
+Reading "sky130_fd_sc_hd__o41a_1".
+Reading "sky130_fd_sc_hd__nor3b_2".
+Reading "sky130_fd_sc_hd__nand2b_2".
+Reading "sky130_fd_sc_hd__nor4b_2".
+Reading "sky130_fd_sc_hd__nand3b_1".
+Reading "sky130_fd_sc_hd__a211oi_2".
+Reading "sky130_fd_sc_hd__o21ba_2".
+Reading "sky130_fd_sc_hd__nand3b_2".
+Reading "sky130_fd_sc_hd__o22ai_4".
+Reading "sky130_fd_sc_hd__a2111o_1".
+Reading "sky130_fd_sc_hd__a31oi_2".
+Reading "sky130_fd_sc_hd__nor2b_1".
+Reading "sky130_fd_sc_hd__nor3b_1".
+Reading "sky130_fd_sc_hd__a2111oi_1".
+CIF file read warning: Input off lambda grid by 2/5; snapped to grid.
+Reading "sky130_fd_sc_hd__and2b_2".
+Reading "sky130_fd_sc_hd__dfxtp_1".
+Reading "sky130_fd_sc_hd__nor4b_1".
+Reading "sky130_fd_sc_hd__a311oi_2".
+Reading "sky130_fd_sc_hd__xor2_4".
+Reading "sky130_fd_sc_hd__dfxtp_2".
+Reading "sky130_fd_sc_hd__a21bo_4".
+Reading "sky130_fd_sc_hd__or3b_4".
+Reading "sky130_fd_sc_hd__or4bb_2".
+Reading "sky130_fd_sc_hd__nor2_8".
+Reading "sky130_fd_sc_hd__inv_4".
+Reading "sky130_fd_sc_hd__o2111ai_4".
+Reading "ycr_core_top".
+ 5000 uses
+ 10000 uses
+ 15000 uses
+ 20000 uses
+ 25000 uses
+ 30000 uses
+ 35000 uses
+ 40000 uses
+ 45000 uses
+ 50000 uses
+ 55000 uses
+ 60000 uses
+ 65000 uses
+ 70000 uses
+Reading "sky130_fd_sc_hd__o221ai_2".
+Reading "sky130_fd_sc_hd__o2111ai_2".
+Reading "sky130_fd_sc_hd__o2bb2a_2".
+Reading "sky130_fd_sc_hd__o2111ai_1".
+Reading "sky130_fd_sc_hd__a2111oi_2".
+Reading "sky130_fd_sc_hd__a221oi_2".
+Reading "sky130_fd_sc_hd__o221ai_1".
+Reading "sky130_fd_sc_hd__o21bai_4".
+Reading "sky130_fd_sc_hd__o32ai_1".
+Reading "sky130_fd_sc_hd__dfstp_4".
+Reading "sky130_fd_sc_hd__o41a_4".
+Reading "sky130_fd_sc_hd__o2bb2a_4".
+Reading "sky130_fd_sc_hd__a21boi_2".
+Reading "sky130_fd_sc_hd__nand2b_1".
+Reading "sky130_fd_sc_hd__o2111a_2".
+Reading "sky130_fd_sc_hd__clkdlybuf4s15_2".
+Reading "ycr_intf".
+ 5000 uses
+ 10000 uses
+ 15000 uses
+ 20000 uses
+ 25000 uses
+ 30000 uses
+ 35000 uses
+ 40000 uses
+ 45000 uses
+ 50000 uses
+ 55000 uses
+ 60000 uses
+Reading "sky130_fd_sc_hd__einvp_2".
+Reading "sky130_fd_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__clkinv_1".
+Reading "sky130_fd_sc_hd__einvn_8".
+Reading "sky130_fd_sc_hd__einvn_4".
+Reading "sky130_fd_sc_hd__einvp_1".
+Reading "digital_pll".
+Reading "sky130_fd_sc_hd__clkdlybuf4s25_1".
+Reading "sky130_fd_sc_hd__nand4b_2".
+Reading "wb_host".
+ 5000 uses
+ 10000 uses
+ 15000 uses
+ 20000 uses
+Reading "sky130_fd_sc_hd__a31o_4".
+Reading "sky130_fd_sc_hd__nor2b_2".
+Reading "sky130_fd_sc_hd__nor3b_4".
+Reading "uart_i2c_usb_spi_top".
+ 5000 uses
+ 10000 uses
+ 15000 uses
+ 20000 uses
+ 25000 uses
+ 30000 uses
+ 35000 uses
+ 40000 uses
+ 45000 uses
+ 50000 uses
+ 55000 uses
+Reading "sky130_fd_sc_hd__a41oi_1".
+Reading "sky130_fd_sc_hd__a2bb2oi_4".
+Reading "wb_interconnect".
+ 5000 uses
+ 10000 uses
+ 15000 uses
+ 20000 uses
+ 25000 uses
+ 30000 uses
+ 35000 uses
+ 40000 uses
+ 45000 uses
+ 50000 uses
+ 55000 uses
+ 60000 uses
+Reading "pinmux".
+ 5000 uses
+ 10000 uses
+ 15000 uses
+ 20000 uses
+ 25000 uses
+ 30000 uses
+Reading "qspim_top".
+ 5000 uses
+ 10000 uses
+ 15000 uses
+ 20000 uses
+ 25000 uses
+ 30000 uses
+ 35000 uses
+Reading "user_project_wrapper".
+[INFO]: Loading user_project_wrapper
+
+DRC style is now "drc(full)"
+Loading DRC CIF style.
+No errors found.
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+[INFO]: DRC Checking DONE (/mnt/uffs/user/u7829_giters/design/riscduino_qcore_folk/jobs/mpw_precheck/41322373-5695-4474-8666-baf2b4c97e4c/outputs/reports/magic_drc_check.drc.report)
+[INFO]: Saving mag view with DRC errors(/mnt/uffs/user/u7829_giters/design/riscduino_qcore_folk/jobs/mpw_precheck/41322373-5695-4474-8666-baf2b4c97e4c/outputs/user_project_wrapper.magic.drc.mag)
+[INFO]: Saved
diff --git a/mpw_precheck/logs/magic_drc_check.total b/mpw_precheck/logs/magic_drc_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/magic_drc_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/pdks.info b/mpw_precheck/logs/pdks.info
new file mode 100644
index 0000000..19f87e1
--- /dev/null
+++ b/mpw_precheck/logs/pdks.info
@@ -0,0 +1,2 @@
+Open PDKs 27ecf1c16911f7dd4428ffab96f62c1fb876ea70
+Skywater PDK c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
\ No newline at end of file
diff --git a/mpw_precheck/logs/precheck.log b/mpw_precheck/logs/precheck.log
new file mode 100644
index 0000000..ed79574
--- /dev/null
+++ b/mpw_precheck/logs/precheck.log
@@ -0,0 +1,67 @@
+2022-06-03 12:16:39 - [INFO] - {{Project Git Info}} Repository: https://github.com/gitercn/riscduino_qcore_folk.git | Branch: main | Commit: aa75e446fa7757dd79717f376e848a4d369a48b5
+2022-06-03 12:16:39 - [INFO] - {{EXTRACTING FILES}} Extracting compressed files in: riscduino_qcore_folk
+2022-06-03 12:16:44 - [INFO] - {{Project Type Info}} digital
+2022-06-03 12:16:44 - [INFO] - {{Project GDS Info}} user_project_wrapper: 0507457456d10a63886f8f85f5ef273429ebec32
+2022-06-03 12:16:44 - [INFO] - {{Tools Info}} KLayout: v0.27.8 | Magic: v8.3.274
+2022-06-03 12:16:44 - [INFO] - {{PDKs Info}} Open PDKs: 27ecf1c16911f7dd4428ffab96f62c1fb876ea70 | Skywater PDK: c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
+2022-06-03 12:16:44 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in 'riscduino_qcore_folk/jobs/mpw_precheck/41322373-5695-4474-8666-baf2b4c97e4c/logs'
+2022-06-03 12:16:44 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: [License, Makefile, Default, Documentation, Consistency, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea]
+2022-06-03 12:16:44 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 13: License
+2022-06-03 12:16:45 - [INFO] - An approved LICENSE (Apache-2.0) was found in riscduino_qcore_folk.
+2022-06-03 12:16:45 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
+2022-06-03 12:16:46 - [INFO] - An approved LICENSE (Apache-2.0) was found in riscduino_qcore_folk.
+2022-06-03 12:16:46 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
+2022-06-03 12:16:48 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino_qcore_folk/verilog/dv/bfm/usb_device/core/usb1d_ctrl.v): 'utf-8' codec can't decode byte 0x96 in position 5130: invalid start byte
+2022-06-03 12:16:48 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino_qcore_folk/verilog/dv/model/mt48lc8m8a2.v): 'utf-8' codec can't decode byte 0xa9 in position 1830: invalid start byte
+2022-06-03 12:16:48 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino_qcore_folk/verilog/dv/user_uart/.user_uart.c.un~): 'utf-8' codec can't decode byte 0x9f in position 3: invalid start byte
+2022-06-03 12:16:48 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 483 non-compliant file(s) with the SPDX Standard.
+2022-06-03 12:16:48 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['riscduino_qcore_folk/Makefile', 'riscduino_qcore_folk/run_regress', 'riscduino_qcore_folk/gds/.magicrc', 'riscduino_qcore_folk/hacks/patch/pdngen.patch', 'riscduino_qcore_folk/hacks/patch/resizer.patch', 'riscduino_qcore_folk/hacks/src/OpenROAD/PdnGen.tcl', 'riscduino_qcore_folk/hacks/src/OpenROAD/Resizer.cc', 'riscduino_qcore_folk/hacks/src/OpenSTA/network/ConcreteNetwork.cc', 'riscduino_qcore_folk/hacks/src/OpenSTA/tcl/NetworkEdit.tcl', 'riscduino_qcore_folk/hacks/src/OpenSTA/tcl/Sta.tcl', 'riscduino_qcore_folk/hacks/src/openlane/io_place.py', 'riscduino_qcore_folk/hacks/src/openlane/synth.tcl', 'riscduino_qcore_folk/hacks/src/openlane/synth_top.tcl', 'riscduino_qcore_folk/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib', 'riscduino_qcore_folk/openlane/Makefile']
+2022-06-03 12:16:48 - [INFO] - For the full SPDX compliance report check: riscduino_qcore_folk/jobs/mpw_precheck/41322373-5695-4474-8666-baf2b4c97e4c/logs/spdx_compliance_report.log
+2022-06-03 12:16:48 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 13: Makefile
+2022-06-03 12:16:48 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
+2022-06-03 12:16:48 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 13: Default
+2022-06-03 12:16:48 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
+2022-06-03 12:16:52 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
+2022-06-03 12:16:52 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 13: Documentation
+2022-06-03 12:16:52 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
+2022-06-03 12:16:52 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 13: Consistency
+2022-06-03 12:16:59 - [INFO] - HIERARCHY CHECK PASSED: Module user_project_wrapper is instantiated in caravel.
+2022-06-03 12:16:59 - [INFO] - COMPLEXITY CHECK PASSED: Netlist caravel contains at least 8 instances (90 instances).
+2022-06-03 12:16:59 - [INFO] - MODELING CHECK PASSED: Netlist caravel is structural.
+2022-06-03 12:16:59 - [INFO] - SUBMODULE HOOKS CHECK PASSED: All module ports for user_project_wrapper are correctly connected in the top level netlist caravel.
+2022-06-03 12:16:59 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in caravel are connected to power
+2022-06-03 12:16:59 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravel netlist passed all consistency checks.
+2022-06-03 12:16:59 - [INFO] - PORTS CHECK PASSED: Netlist user_project_wrapper ports match the golden wrapper ports
+2022-06-03 12:16:59 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_project_wrapper contains at least 1 instances (15 instances).
+2022-06-03 12:16:59 - [INFO] - MODELING CHECK PASSED: Netlist user_project_wrapper is structural.
+2022-06-03 12:16:59 - [INFO] - LAYOUT CHECK PASSED: The GDS layout for user_project_wrapper matches the provided structural netlist.
+2022-06-03 12:16:59 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in user_project_wrapper are connected to power
+2022-06-03 12:16:59 - [INFO] - PORT TYPES CHECK PASSED: Netlist user_project_wrapper port types match the golden wrapper port types.
+2022-06-03 12:16:59 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} user_project_wrapper netlist passed all consistency checks.
+2022-06-03 12:16:59 - [INFO] - {{CONSISTENCY CHECK PASSED}} The user netlist and the top netlist are valid.
+2022-06-03 12:16:59 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 13: XOR
+2022-06-03 12:19:47 - [INFO] - {{XOR CHECK UPDATE}} Total XOR differences: 0, for more details view riscduino_qcore_folk/jobs/mpw_precheck/41322373-5695-4474-8666-baf2b4c97e4c/outputs/user_project_wrapper.xor.gds
+2022-06-03 12:19:47 - [INFO] - {{XOR CHECK PASSED}} The GDS file has no XOR violations.
+2022-06-03 12:19:47 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 13: Magic DRC
+2022-06-03 12:30:34 - [INFO] - 0 DRC violations
+2022-06-03 12:30:34 - [INFO] - {{MAGIC DRC CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-06-03 12:30:34 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 13: Klayout FEOL
+2022-06-03 12:32:58 - [INFO] - No DRC Violations found
+2022-06-03 12:32:58 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-06-03 12:32:58 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 13: Klayout BEOL
+2022-06-03 12:52:17 - [INFO] - No DRC Violations found
+2022-06-03 12:52:17 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-06-03 12:52:17 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 13: Klayout Offgrid
+2022-06-03 12:55:54 - [INFO] - No DRC Violations found
+2022-06-03 12:55:54 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-06-03 12:55:54 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 13: Klayout Metal Minimum Clear Area Density
+2022-06-03 12:57:24 - [INFO] - No DRC Violations found
+2022-06-03 12:57:24 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-06-03 12:57:24 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 13: Klayout Pin Label Purposes Overlapping Drawing
+2022-06-03 12:57:57 - [INFO] - No DRC Violations found
+2022-06-03 12:57:57 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-06-03 12:57:57 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 13: Klayout ZeroArea
+2022-06-03 12:58:12 - [INFO] - No DRC Violations found
+2022-06-03 12:58:12 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-06-03 12:58:12 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in 'riscduino_qcore_folk/jobs/mpw_precheck/41322373-5695-4474-8666-baf2b4c97e4c/logs'
+2022-06-03 12:58:12 - [INFO] - {{SUCCESS}} All Checks Passed !!!
diff --git a/mpw_precheck/logs/spdx_compliance_report.log b/mpw_precheck/logs/spdx_compliance_report.log
new file mode 100644
index 0000000..a77b263
--- /dev/null
+++ b/mpw_precheck/logs/spdx_compliance_report.log
@@ -0,0 +1,483 @@
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+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/src/lib/async_fifo.sv
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/src/lib/clk_skew_adjust.gv
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/src/lib/ctech_cells.sv
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/src/lib/sync_fifo.sv
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/src/lib/sync_fifo2.sv
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/src/lib/ycr_arb.sv
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/src/lib/ycr_async_wbb.sv
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/src/top/ycr2_top_ahb.sv
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/src/top/ycr2_top_axi.sv
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/src/top/ycr4_cross_bar.sv
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/src/top/ycr4_iconnect.sv
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/src/top/ycr4_router.sv
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/src/top/ycr4_top_wb.sv
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/src/top/ycr_cache_top.sv
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/src/top/ycr_dcache_router.sv
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/src/top/ycr_dmem_ahb.sv
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/src/top/ycr_dmem_router.sv
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/src/top/ycr_dmem_wb.sv
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/src/top/ycr_dp_memory.sv
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/src/top/ycr_icache_router.sv
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/src/top/ycr_imem_ahb.sv
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/src/top/ycr_imem_router.sv
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/src/top/ycr_imem_wb.sv
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/src/top/ycr_intf.sv
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/src/top/ycr_mem_axi.sv
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/src/top/ycr_req_retiming.sv
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/src/top/ycr_sram_mux.sv
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/src/top/ycr_tcm.sv
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/src/top/ycr_timer.sv
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/synth/Makefile
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/synth/base.sdc
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/synth/run_synth
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/synth/sta.tcl
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/synth/synth.tcl
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/synth/scripts/libtrim.pl
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/tb/ahb_tb.files
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/tb/axi_tb.files
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/tb/sky130_sram_2kbyte_1rw1r_32x512_8.v
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/tb/uprj_netlists.v
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/tb/wb_tb.files
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/tb/ycr2_top_tb_ahb.sv
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/tb/ycr2_top_tb_axi.sv
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/tb/ycr4_top_tb_wb.sv
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/tb/ycr_dmem_tb_wb.sv
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/tb/ycr_memory_tb_ahb.sv
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/tb/ycr_memory_tb_axi.sv
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/tb/ycr_memory_tb_wb.sv
+/root/riscduino_qcore_folk/verilog/rtl/yifive/ycr4c/tb/ycr_top_tb_runtests.sv
diff --git a/mpw_precheck/logs/tools.info b/mpw_precheck/logs/tools.info
new file mode 100644
index 0000000..9b2230a
--- /dev/null
+++ b/mpw_precheck/logs/tools.info
@@ -0,0 +1,2 @@
+KLayout: 0.27.8
+Magic: 8.3.274
\ No newline at end of file
diff --git a/mpw_precheck/logs/xor_check.log b/mpw_precheck/logs/xor_check.log
new file mode 100644
index 0000000..bff6a82
--- /dev/null
+++ b/mpw_precheck/logs/xor_check.log
@@ -0,0 +1,704 @@
+Reading file /root/riscduino_qcore_folk/gds/user_project_wrapper.gds for cell user_project_wrapper
+dbu=0.001
+cell user_project_wrapper dbu-bbox(ll;ur)=(-43630,-38270;2963250,3557950)
+cell user_project_wrapper dbu-bbox(left,bottom,right,top)=(-43630,-38270,2963250,3557950)
+cell user_project_wrapper dbu-size(width,height)=(3006880,3596220)
+cell user_project_wrapper micron-bbox(left,bottom,right,top)=(-43.63,-38.27,2963.25,3557.9500000000003)
+cell user_project_wrapper micron-size(width,height)=(3006.88,3596.2200000000003)
+Done.
+
+Magic 8.3 revision 274 - Compiled on Fri Mar 4 22:53:06 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+ mvobsactive ubm
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/checks/xor_check/erase_box.tcl" from command line.
+CIF input style is now "sky130(vendor)"
+Warning: Calma reading is not undoable! I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: user_project_wrapper
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_39".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_19".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_14".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_13".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_7".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_38".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_33".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_32".
+Reading "sky130_fd_bd_sram__openram_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_addr_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wmask_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_addr_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_data_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_16".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_29".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_28".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_11".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_360_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_12".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sli_dactive".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w0_740_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w1_260_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m7_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m7_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m24_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m24_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_14".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m8_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m8_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_13".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_12".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_11".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_17".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_delay_chain".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m18_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m18_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_16".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_5".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dactive".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand3_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m22_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m22_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_15".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m42_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m42_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_10".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m15_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m15_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_9".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m5_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_8".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w1_260_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_7".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_rw".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_5".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m41_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m41_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_20".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m14_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m14_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_19".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_18".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_6".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_r".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_20".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_17".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_15".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w7_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w7_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec_0".
+CIF file read warning: CIF style sky130(vendor): units rescaled by factor of 5 / 1
+Reading "sky130_fd_bd_sram__openram_dp_nand2_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec".
+Reading "sky130_fd_bd_sram__openram_dp_nand3_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and3_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode3x8".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_decoder".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_address_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_address".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_27".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_26".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_25".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_24".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w2_880_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array_0".
+Reading "sky130_fd_bd_sram__openram_sense_amp".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_sense_amp_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_23".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_21".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_22".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w0_550_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_data_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_write_mask_and_array".
+Reading "sky130_fd_bd_sram__openram_write_driver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_write_driver_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_data".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_9".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_8".
+Reading "sky130_fd_bd_sram__openram_dp_cell_cap_row".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_cap_row" (byte position 2620068): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_cap_row" (byte position 2620772): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_cap_row" (byte position 2621732): Unknown layer/datatype in boundary, layer=22 type=21
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array".
+Reading "sky130_fd_bd_sram__openram_dp_cell_cap_col".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array_0".
+Reading "sky130_fd_bd_sram__openram_dp_cell_dummy".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3113978): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3117754): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3121946): Unknown layer/datatype in boundary, layer=22 type=21
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3126746): Unknown layer/datatype in boundary, layer=22 type=22
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 3128794): Unknown layer/datatype in boundary, layer=235 type=0
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dummy_array".
+Reading "sky130_fd_bd_sram__openram_dp_cell_replica".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3308236): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3312012): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3316204): Unknown layer/datatype in boundary, layer=22 type=21
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3322668): Unknown layer/datatype in boundary, layer=22 type=22
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 3324844): Unknown layer/datatype in boundary, layer=235 type=0
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_column_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_column".
+Reading "sky130_fd_bd_sram__openram_dp_cell".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3565294): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3569070): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3573262): Unknown layer/datatype in boundary, layer=22 type=21
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3579726): Unknown layer/datatype in boundary, layer=22 type=22
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 3581902): Unknown layer/datatype in boundary, layer=235 type=0
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_bitcell_array".
+ 5000 uses
+ 10000 uses
+ 15000 uses
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_bitcell_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_bank".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8".
+ 5000 uses
+Reading "sky130_fd_sc_hd__and2_2".
+Reading "sky130_fd_sc_hd__or4_2".
+Reading "sky130_fd_sc_hd__o41a_2".
+Reading "sky130_fd_sc_hd__o311a_2".
+Reading "sky130_fd_sc_hd__and3_2".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__clkbuf_2".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__clkinv_2".
+Reading "sky130_fd_sc_hd__mux2_1".
+Reading "sky130_fd_sc_hd__o32a_2".
+Reading "sky130_fd_sc_hd__clkinv_8".
+Reading "sky130_fd_sc_hd__a221o_2".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_fd_sc_hd__o31a_2".
+Reading "sky130_fd_sc_hd__a22oi_2".
+Reading "sky130_fd_sc_hd__a21bo_2".
+Reading "sky130_fd_sc_hd__a21o_2".
+Reading "sky130_fd_sc_hd__o22a_2".
+Reading "sky130_fd_sc_hd__o211a_2".
+Reading "sky130_fd_sc_hd__and4_2".
+Reading "sky130_fd_sc_hd__a31o_2".
+Reading "sky130_fd_sc_hd__nand2_2".
+Reading "sky130_fd_sc_hd__o2bb2ai_2".
+Reading "sky130_fd_sc_hd__o21ai_2".
+Reading "sky130_fd_sc_hd__o221a_2".
+Reading "sky130_fd_sc_hd__a2bb2o_2".
+Reading "sky130_fd_sc_hd__or2_2".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__or3_2".
+Reading "sky130_fd_sc_hd__a21oi_2".
+Reading "sky130_fd_sc_hd__nor2_2".
+Reading "sky130_fd_sc_hd__a22o_2".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "sky130_fd_sc_hd__dfrtp_2".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__buf_1".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_ef_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__dfrtp_4".
+Reading "sky130_fd_sc_hd__dfrtp_1".
+Reading "sky130_fd_sc_hd__dfstp_2".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__xnor2_1".
+Reading "sky130_fd_sc_hd__xor2_1".
+Reading "sky130_fd_sc_hd__o21ai_1".
+Reading "sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "sky130_fd_sc_hd__or2b_1".
+Reading "sky130_fd_sc_hd__o211a_1".
+Reading "sky130_fd_sc_hd__or2_1".
+Reading "sky130_fd_sc_hd__dfstp_1".
+Reading "sky130_fd_sc_hd__a21oi_1".
+Reading "sky130_fd_sc_hd__a221o_1".
+Reading "sky130_fd_sc_hd__a31o_1".
+Reading "sky130_fd_sc_hd__nand2_1".
+Reading "sky130_fd_sc_hd__o21a_1".
+Reading "sky130_fd_sc_hd__o2bb2a_1".
+Reading "sky130_fd_sc_hd__nor2_1".
+Reading "sky130_fd_sc_hd__o21ai_4".
+Reading "sky130_fd_sc_hd__clkbuf_4".
+Reading "sky130_fd_sc_hd__and3_1".
+Reading "sky130_fd_sc_hd__nand3_2".
+Reading "sky130_fd_sc_hd__and2_1".
+Reading "sky130_fd_sc_hd__a21o_1".
+Reading "sky130_fd_sc_hd__a311o_1".
+Reading "sky130_fd_sc_hd__a21bo_1".
+Reading "sky130_fd_sc_hd__a2bb2o_1".
+Reading "sky130_fd_sc_hd__o22a_1".
+Reading "sky130_fd_sc_hd__a211o_1".
+Reading "sky130_fd_sc_hd__a22oi_1".
+Reading "sky130_fd_sc_hd__a22o_1".
+Reading "sky130_fd_sc_hd__and4bb_2".
+Reading "sky130_fd_sc_hd__or2_4".
+Reading "sky130_fd_sc_hd__or4b_1".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "sky130_fd_sc_hd__mux2_2".
+Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hd__a32o_1".
+Reading "sky130_fd_sc_hd__and2b_1".
+Reading "sky130_fd_sc_hd__a22o_4".
+Reading "sky130_fd_sc_hd__or3_1".
+Reading "sky130_fd_sc_hd__buf_12".
+Reading "sky130_fd_sc_hd__o221a_1".
+Reading "sky130_fd_sc_hd__xor2_2".
+Reading "sky130_fd_sc_hd__nand3_1".
+Reading "sky130_fd_sc_hd__or4b_4".
+Reading "sky130_fd_sc_hd__o211ai_4".
+Reading "sky130_fd_sc_hd__mux4_1".
+Reading "sky130_fd_sc_hd__or3b_1".
+Reading "sky130_fd_sc_hd__mux4_2".
+Reading "sky130_fd_sc_hd__or2b_4".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__nand2_8".
+Reading "sky130_fd_sc_hd__or4_1".
+Reading "sky130_fd_sc_hd__clkbuf_8".
+Reading "sky130_fd_sc_hd__buf_6".
+Reading "sky130_fd_sc_hd__a221o_4".
+Reading "sky130_fd_sc_hd__mux2_8".
+Reading "sky130_fd_sc_hd__a22oi_4".
+Reading "sky130_fd_sc_hd__a221oi_4".
+Reading "sky130_fd_sc_hd__a21o_4".
+Reading "sky130_fd_sc_hd__o221ai_4".
+Reading "sky130_fd_sc_hd__a41o_4".
+Reading "sky130_fd_sc_hd__a211o_4".
+Reading "sky130_fd_sc_hd__o31a_1".
+Reading "sky130_fd_sc_hd__nor4_4".
+Reading "sky130_fd_sc_hd__or4_4".
+Reading "sky130_fd_sc_hd__o211ai_1".
+Reading "sky130_fd_sc_hd__o221a_4".
+Reading "sky130_fd_sc_hd__o31a_4".
+Reading "sky130_fd_sc_hd__o311a_1".
+Reading "sky130_fd_sc_hd__nand4_1".
+Reading "sky130_fd_sc_hd__o211ai_2".
+Reading "sky130_fd_sc_hd__nand4b_1".
+Reading "sky130_fd_sc_hd__and4_1".
+Reading "sky130_fd_sc_hd__or3_4".
+Reading "sky130_fd_sc_hd__and4_4".
+Reading "sky130_fd_sc_hd__o31ai_1".
+Reading "sky130_fd_sc_hd__or4bb_1".
+Reading "sky130_fd_sc_hd__o21ba_1".
+Reading "sky130_fd_sc_hd__and4b_2".
+Reading "sky130_fd_sc_hd__a221oi_1".
+Reading "sky130_fd_sc_hd__nand4_4".
+Reading "sky130_fd_sc_hd__and4b_4".
+Reading "sky130_fd_sc_hd__and4bb_4".
+Reading "sky130_fd_sc_hd__nand2_4".
+Reading "sky130_fd_sc_hd__or4bb_4".
+Reading "sky130_fd_sc_hd__and4b_1".
+Reading "sky130_fd_sc_hd__a32o_4".
+Reading "sky130_fd_sc_hd__dlygate4sd1_1".
+Reading "sky130_fd_sc_hd__o32a_1".
+Reading "sky130_fd_sc_hd__nor4b_4".
+Reading "sky130_fd_sc_hd__nor3_4".
+Reading "sky130_fd_sc_hd__o31ai_4".
+Reading "sky130_fd_sc_hd__and3b_4".
+Reading "sky130_fd_sc_hd__and3_4".
+Reading "sky130_fd_sc_hd__o31ai_2".
+Reading "sky130_fd_sc_hd__a211oi_4".
+Reading "sky130_fd_sc_hd__o22a_4".
+Reading "sky130_fd_sc_hd__nor4_2".
+Reading "sky130_fd_sc_hd__a41o_2".
+Reading "sky130_fd_sc_hd__inv_6".
+Reading "sky130_fd_sc_hd__nand3_4".
+Reading "sky130_fd_sc_hd__o2bb2ai_1".
+Reading "sky130_fd_sc_hd__clkinv_4".
+Reading "sky130_fd_sc_hd__a2111o_4".
+Reading "sky130_fd_sc_hd__and2b_4".
+Reading "sky130_fd_sc_hd__a2bb2o_4".
+Reading "sky130_fd_sc_hd__o21a_4".
+Reading "sky130_fd_sc_hd__o211a_4".
+Reading "sky130_fd_sc_hd__a21oi_4".
+Reading "sky130_fd_sc_hd__o311a_4".
+Reading "sky130_fd_sc_hd__a211o_2".
+Reading "sky130_fd_sc_hd__a32oi_4".
+Reading "sky130_fd_sc_hd__and3b_2".
+Reading "sky130_fd_sc_hd__and3b_1".
+Reading "sky130_fd_sc_hd__nor4_1".
+Reading "sky130_fd_sc_hd__and4bb_1".
+Reading "sky130_fd_sc_hd__a211oi_1".
+Reading "sky130_fd_sc_hd__mux2_4".
+Reading "sky130_fd_sc_hd__nor3_2".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "sky130_fd_sc_hd__or4b_2".
+Reading "ycr4_iconnect".
+ 5000 uses
+ 10000 uses
+ 15000 uses
+ 20000 uses
+ 25000 uses
+ 30000 uses
+ 35000 uses
+ 40000 uses
+ 45000 uses
+ 50000 uses
+ 55000 uses
+ 60000 uses
+ 65000 uses
+ 70000 uses
+ 75000 uses
+Reading "sky130_fd_sc_hd__o21a_2".
+Reading "sky130_fd_sc_hd__a32o_2".
+Reading "sky130_fd_sc_hd__o22ai_2".
+Reading "sky130_fd_sc_hd__a311o_2".
+Reading "sky130_fd_sc_hd__a41o_1".
+Reading "sky130_fd_sc_hd__o21bai_2".
+Reading "sky130_fd_sc_hd__nor3_1".
+Reading "sky130_fd_sc_hd__a21boi_1".
+Reading "sky130_fd_sc_hd__xnor2_2".
+Reading "sky130_fd_sc_hd__a2111o_2".
+Reading "sky130_fd_sc_hd__o21bai_1".
+Reading "sky130_fd_sc_hd__o2111a_1".
+Reading "sky130_fd_sc_hd__a31oi_4".
+Reading "sky130_fd_sc_hd__a2111oi_4".
+Reading "sky130_fd_sc_hd__nand4_2".
+Reading "sky130_fd_sc_hd__o22ai_1".
+Reading "sky130_fd_sc_hd__a31oi_1".
+Reading "sky130_fd_sc_hd__a311oi_1".
+Reading "sky130_fd_sc_hd__or2b_2".
+Reading "sky130_fd_sc_hd__xnor2_4".
+Reading "sky130_fd_sc_hd__or3b_2".
+Reading "sky130_fd_sc_hd__o41a_1".
+Reading "sky130_fd_sc_hd__nor3b_2".
+Reading "sky130_fd_sc_hd__nand2b_2".
+Reading "sky130_fd_sc_hd__nor4b_2".
+Reading "sky130_fd_sc_hd__nand3b_1".
+Reading "sky130_fd_sc_hd__a211oi_2".
+Reading "sky130_fd_sc_hd__o21ba_2".
+Reading "sky130_fd_sc_hd__nand3b_2".
+Reading "sky130_fd_sc_hd__o22ai_4".
+Reading "sky130_fd_sc_hd__a2111o_1".
+Reading "sky130_fd_sc_hd__a31oi_2".
+Reading "sky130_fd_sc_hd__nor2b_1".
+Reading "sky130_fd_sc_hd__nor3b_1".
+Reading "sky130_fd_sc_hd__a2111oi_1".
+CIF file read warning: Input off lambda grid by 2/5; snapped to grid.
+Reading "sky130_fd_sc_hd__and2b_2".
+Reading "sky130_fd_sc_hd__dfxtp_1".
+Reading "sky130_fd_sc_hd__nor4b_1".
+Reading "sky130_fd_sc_hd__a311oi_2".
+Reading "sky130_fd_sc_hd__xor2_4".
+Reading "sky130_fd_sc_hd__dfxtp_2".
+Reading "sky130_fd_sc_hd__a21bo_4".
+Reading "sky130_fd_sc_hd__or3b_4".
+Reading "sky130_fd_sc_hd__or4bb_2".
+Reading "sky130_fd_sc_hd__nor2_8".
+Reading "sky130_fd_sc_hd__inv_4".
+Reading "sky130_fd_sc_hd__o2111ai_4".
+Reading "ycr_core_top".
+ 5000 uses
+ 10000 uses
+ 15000 uses
+ 20000 uses
+ 25000 uses
+ 30000 uses
+ 35000 uses
+ 40000 uses
+ 45000 uses
+ 50000 uses
+ 55000 uses
+ 60000 uses
+ 65000 uses
+ 70000 uses
+Reading "sky130_fd_sc_hd__o221ai_2".
+Reading "sky130_fd_sc_hd__o2111ai_2".
+Reading "sky130_fd_sc_hd__o2bb2a_2".
+Reading "sky130_fd_sc_hd__o2111ai_1".
+Reading "sky130_fd_sc_hd__a2111oi_2".
+Reading "sky130_fd_sc_hd__a221oi_2".
+Reading "sky130_fd_sc_hd__o221ai_1".
+Reading "sky130_fd_sc_hd__o21bai_4".
+Reading "sky130_fd_sc_hd__o32ai_1".
+Reading "sky130_fd_sc_hd__dfstp_4".
+Reading "sky130_fd_sc_hd__o41a_4".
+Reading "sky130_fd_sc_hd__o2bb2a_4".
+Reading "sky130_fd_sc_hd__a21boi_2".
+Reading "sky130_fd_sc_hd__nand2b_1".
+Reading "sky130_fd_sc_hd__o2111a_2".
+Reading "sky130_fd_sc_hd__clkdlybuf4s15_2".
+Reading "ycr_intf".
+ 5000 uses
+ 10000 uses
+ 15000 uses
+ 20000 uses
+ 25000 uses
+ 30000 uses
+ 35000 uses
+ 40000 uses
+ 45000 uses
+ 50000 uses
+ 55000 uses
+ 60000 uses
+Reading "sky130_fd_sc_hd__einvp_2".
+Reading "sky130_fd_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__clkinv_1".
+Reading "sky130_fd_sc_hd__einvn_8".
+Reading "sky130_fd_sc_hd__einvn_4".
+Reading "sky130_fd_sc_hd__einvp_1".
+Reading "digital_pll".
+Reading "sky130_fd_sc_hd__clkdlybuf4s25_1".
+Reading "sky130_fd_sc_hd__nand4b_2".
+Reading "wb_host".
+ 5000 uses
+ 10000 uses
+ 15000 uses
+ 20000 uses
+Reading "sky130_fd_sc_hd__a31o_4".
+Reading "sky130_fd_sc_hd__nor2b_2".
+Reading "sky130_fd_sc_hd__nor3b_4".
+Reading "uart_i2c_usb_spi_top".
+ 5000 uses
+ 10000 uses
+ 15000 uses
+ 20000 uses
+ 25000 uses
+ 30000 uses
+ 35000 uses
+ 40000 uses
+ 45000 uses
+ 50000 uses
+ 55000 uses
+Reading "sky130_fd_sc_hd__a41oi_1".
+Reading "sky130_fd_sc_hd__a2bb2oi_4".
+Reading "wb_interconnect".
+ 5000 uses
+ 10000 uses
+ 15000 uses
+ 20000 uses
+ 25000 uses
+ 30000 uses
+ 35000 uses
+ 40000 uses
+ 45000 uses
+ 50000 uses
+ 55000 uses
+ 60000 uses
+Reading "pinmux".
+ 5000 uses
+ 10000 uses
+ 15000 uses
+ 20000 uses
+ 25000 uses
+ 30000 uses
+Reading "qspim_top".
+ 5000 uses
+ 10000 uses
+ 15000 uses
+ 20000 uses
+ 25000 uses
+ 30000 uses
+ 35000 uses
+Reading "user_project_wrapper".
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 42.880 x 3520.000 (-42.880, 0.000), ( 0.000, 3520.000) 150937.594
+lambda: 4288.00 x 352000.00 (-4288.00, 0.00 ), ( 0.00, 352000.00) 1509376000.00
+internal: 8576 x 704000 ( -8576, 0 ), ( 0, 704000) 6037504000
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 42.500 x 3520.000 ( 2920.000, 0.000), ( 2962.500, 3520.000) 149600.000
+lambda: 4250.00 x 352000.00 ( 292000.00, 0.00 ), ( 296250.00, 352000.00) 1496000000.00
+internal: 8500 x 704000 ( 584000, 0 ), ( 592500, 704000) 5984000000
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 3005.380 x 37.530 (-42.880, -37.530), ( 2962.500, 0.000) 112791.906
+lambda: 300538.00 x 3753.00 (-4288.00, -3753.00), ( 296250.00, 0.00 ) 1127919104.00
+internal: 601076 x 7506 ( -8576, -7506 ), ( 592500, 0 ) 4511676456
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 3005.380 x 37.210 (-42.880, 3520.000), ( 2962.500, 3557.210) 111830.188
+lambda: 300538.00 x 3721.00 (-4288.00, 352000.00), ( 296250.00, 355721.00) 1118301952.00
+internal: 601076 x 7442 ( -8576, 704000), ( 592500, 711442) 4473207592
+ Generating output for cell xor_target
+
+Magic 8.3 revision 274 - Compiled on Fri Mar 4 22:53:06 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+ mvobsactive ubm
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/checks/xor_check/erase_box.tcl" from command line.
+CIF input style is now "sky130(vendor)"
+Warning: Calma reading is not undoable! I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: user_project_wrapper
+Reading "user_project_wrapper".
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 42.880 x 3520.000 (-42.880, 0.000), ( 0.000, 3520.000) 150937.594
+lambda: 4288.00 x 352000.00 (-4288.00, 0.00 ), ( 0.00, 352000.00) 1509376000.00
+internal: 8576 x 704000 ( -8576, 0 ), ( 0, 704000) 6037504000
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 42.500 x 3520.000 ( 2920.000, 0.000), ( 2962.500, 3520.000) 149600.000
+lambda: 4250.00 x 352000.00 ( 292000.00, 0.00 ), ( 296250.00, 352000.00) 1496000000.00
+internal: 8500 x 704000 ( 584000, 0 ), ( 592500, 704000) 5984000000
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 3005.380 x 37.530 (-42.880, -37.530), ( 2962.500, 0.000) 112791.906
+lambda: 300538.00 x 3753.00 (-4288.00, -3753.00), ( 296250.00, 0.00 ) 1127919104.00
+internal: 601076 x 7506 ( -8576, -7506 ), ( 592500, 0 ) 4511676456
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 3005.380 x 37.210 (-42.880, 3520.000), ( 2962.500, 3557.210) 111830.188
+lambda: 300538.00 x 3721.00 (-4288.00, 352000.00), ( 296250.00, 355721.00) 1118301952.00
+internal: 601076 x 7442 ( -8576, 704000), ( 592500, 711442) 4473207592
+ Generating output for cell xor_target
+Reading /mnt/uffs/user/u7829_giters/design/riscduino_qcore_folk/jobs/mpw_precheck/41322373-5695-4474-8666-baf2b4c97e4c/outputs/user_project_wrapper_erased.gds ..
+Reading /mnt/uffs/user/u7829_giters/design/riscduino_qcore_folk/jobs/mpw_precheck/41322373-5695-4474-8666-baf2b4c97e4c/outputs/user_project_wrapper_empty_erased.gds ..
+--- Running XOR for 69/20 ---
+"input" in: xor.rb.drc:39
+ Polygons (raw): 530 (flat) 530 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
+"input" in: xor.rb.drc:39
+ Polygons (raw): 530 (flat) 530 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
+"^" in: xor.rb.drc:39
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
+--- Running XOR for 70/20 ---
+"input" in: xor.rb.drc:39
+ Polygons (raw): 107 (flat) 107 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
+"input" in: xor.rb.drc:39
+ Polygons (raw): 107 (flat) 107 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
+"^" in: xor.rb.drc:39
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
+--- Running XOR for 71/20 ---
+"input" in: xor.rb.drc:39
+ Polygons (raw): 16 (flat) 16 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
+"input" in: xor.rb.drc:39
+ Polygons (raw): 16 (flat) 16 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
+"^" in: xor.rb.drc:39
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
+--- Running XOR for 71/44 ---
+"input" in: xor.rb.drc:39
+ Polygons (raw): 116 (flat) 116 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
+"input" in: xor.rb.drc:39
+ Polygons (raw): 116 (flat) 116 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
+"^" in: xor.rb.drc:39
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
+--- Running XOR for 72/20 ---
+"input" in: xor.rb.drc:39
+ Polygons (raw): 16 (flat) 16 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
+"input" in: xor.rb.drc:39
+ Polygons (raw): 16 (flat) 16 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
+"^" in: xor.rb.drc:39
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
+--- Running XOR for 81/14 ---
+"input" in: xor.rb.drc:39
+ Polygons (raw): 1 (flat) 1 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
+"input" in: xor.rb.drc:39
+ Polygons (raw): 1 (flat) 1 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
+"^" in: xor.rb.drc:39
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
+Writing layout file: /mnt/uffs/user/u7829_giters/design/riscduino_qcore_folk/jobs/mpw_precheck/41322373-5695-4474-8666-baf2b4c97e4c/outputs/user_project_wrapper.xor.gds ..
+Total elapsed: 0.120s Memory: 523.00M
diff --git a/mpw_precheck/logs/xor_check.total b/mpw_precheck/logs/xor_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/xor_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/outputs/reports/klayout_beol_check.xml b/mpw_precheck/outputs/reports/klayout_beol_check.xml
new file mode 100644
index 0000000..5ffd971
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_beol_check.xml
@@ -0,0 +1,447 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ <category>
+ <name>li.1</name>
+ <description>li.1 : min. li width : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li.3</name>
+ <description>li.3 : min. li spacing : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li.5</name>
+ <description>li.5 : min. li enclosure of licon of 2 adjacent edges : 0.08um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li.6</name>
+ <description>li.6 : min. li area : 0.0561um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.1</name>
+ <description>ct.1: non-ring mcon should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.1_a</name>
+ <description>ct.1_a : minimum width of mcon : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.1_b</name>
+ <description>ct.1_b : maximum length of mcon : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.2</name>
+ <description>ct.2 : min. mcon spacing : 0.19um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.4</name>
+ <description>ct.4 : mcon should covered by li</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.1</name>
+ <description>m1.1 : min. m1 width : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.2</name>
+ <description>m1.2 : min. m1 spacing : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.3ab</name>
+ <description>m1.3ab : min. 3um.m1 spacing m1 : 0.28um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>791_m1.4</name>
+ <description>791_m1.4 : min. m1 enclosure of mcon : 0.03um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.4</name>
+ <description>m1.4 : mcon periphery must be enclosed by m1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.4a</name>
+ <description>m1.4a : min. m1 enclosure of mcon for specific cells : 0.005um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.4a_a</name>
+ <description>m1.4a_a : mcon periph must be enclosed by met1 for specific cells</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.6</name>
+ <description>m1.6 : min. m1 area : 0.083um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.7</name>
+ <description>m1.7 : min. m1 with holes area : 0.14um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.5</name>
+ <description>m1.5 : min. m1 enclosure of mcon of 2 adjacent edges : 0.06um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.1a</name>
+ <description>via.1a : via outside of moduleCut should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.1a_a</name>
+ <description>via.1a_a : min. width of via outside of moduleCut : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.1a_b</name>
+ <description>via.1a_b : maximum length of via : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.2</name>
+ <description>via.2 : min. via spacing : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.4a</name>
+ <description>via.4a : min. m1 enclosure of 0.15um via : 0.055um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.4a_a</name>
+ <description>via.4a_a : 0.15um via must be enclosed by met1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.5a</name>
+ <description>via.5a : min. m1 enclosure of 0.15um via of 2 adjacent edges : 0.085um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.1</name>
+ <description>m2.1 : min. m2 width : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.2</name>
+ <description>m2.2 : min. m2 spacing : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.3ab</name>
+ <description>m2.3ab : min. 3um.m2 spacing m2 : 0.28um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.6</name>
+ <description>m2.6 : min. m2 area : 0.0676um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.7</name>
+ <description>m2.7 : min. m2 holes area : 0.14um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.4</name>
+ <description>m2.4 : min. m2 enclosure of via : 0.055um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.4_a</name>
+ <description>m2.4_a : via in periphery must be enclosed by met2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.5</name>
+ <description>m2.5 : min. m2 enclosure of via of 2 adjacent edges : 0.085um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.1a</name>
+ <description>via2.1a : via2 outside of moduleCut should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.1a_a</name>
+ <description>via2.1a_a : min. width of via2 outside of moduleCut : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.1a_b</name>
+ <description>via2.1a_b : maximum length of via2 : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.2</name>
+ <description>via2.2 : min. via2 spacing : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.4</name>
+ <description>via2.4 : min. m2 enclosure of via2 : 0.04um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.4_a</name>
+ <description>via2.4_a : via must be enclosed by met2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.5</name>
+ <description>via2.5 : min. m3 enclosure of via2 of 2 adjacent edges : 0.085um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.1</name>
+ <description>m3.1 : min. m3 width : 0.3um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.2</name>
+ <description>m3.2 : min. m3 spacing : 0.3um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.3cd</name>
+ <description>m3.3cd : min. 3um.m3 spacing m3 : 0.4um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.4</name>
+ <description>m3.4 : min. m3 enclosure of via2 : 0.065um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.4_a</name>
+ <description>m3.4_a : via2 must be enclosed by met3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.1</name>
+ <description>via3.1 : via3 outside of moduleCut should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.1_a</name>
+ <description>via3.1_a : min. width of via3 outside of moduleCut : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.1_b</name>
+ <description>via3.1_b : maximum length of via3 : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.2</name>
+ <description>via3.2 : min. via3 spacing : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.4</name>
+ <description>via3.4 : min. m3 enclosure of via3 : 0.06um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.4_a</name>
+ <description>via3.4_a : non-ring via3 must be enclosed by met3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.5</name>
+ <description>via3.5 : min. m3 enclosure of via3 of 2 adjacent edges : 0.09um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.1</name>
+ <description>m4.1 : min. m4 width : 0.3um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.2</name>
+ <description>m4.2 : min. m4 spacing : 0.3um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.4a</name>
+ <description>m4.4a : min. m4 area : 0.240um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.5ab</name>
+ <description>m4.5ab : min. 3um.m4 spacing m4 : 0.4um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.3</name>
+ <description>m4.3 : min. m4 enclosure of via3 : 0.065um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.3_a</name>
+ <description>m4.3_a : via3 must be enclosed by met4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.1</name>
+ <description>via4.1 : via4 outside of moduleCut should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.1_a</name>
+ <description>via4.1_a : min. width of via4 outside of moduleCut : 0.8um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.1_b</name>
+ <description>via4.1_b : maximum length of via4 : 0.8um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.2</name>
+ <description>via4.2 : min. via4 spacing : 0.8um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.4</name>
+ <description>via4.4 : min. m4 enclosure of via4 : 0.19um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.4_a</name>
+ <description>via4.4_a : m4 must enclose all via4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.1</name>
+ <description>m5.1 : min. m5 width : 1.6um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.2</name>
+ <description>m5.2 : min. m5 spacing : 1.6um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.3</name>
+ <description>m5.3 : min. m5 enclosure of via4 : 0.31um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.3_a</name>
+ <description>m5.3_a : via must be enclosed by m5</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.4</name>
+ <description>m5.4 : min. m5 area : 4.0um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pad.2</name>
+ <description>pad.2 : min. pad spacing : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/reports/klayout_feol_check.xml b/mpw_precheck/outputs/reports/klayout_feol_check.xml
new file mode 100644
index 0000000..987027f
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_feol_check.xml
@@ -0,0 +1,363 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ <category>
+ <name>dnwell.2</name>
+ <description>dnwell.2 : min. dnwell width : 3.0um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell.1</name>
+ <description>nwell.1 : min. nwell width : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell.2a</name>
+ <description>nwell.2a : min. nwell spacing (merged if less) : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell.6</name>
+ <description>nwell.6 : min enclosure of nwellHole by dnwell : 1.03um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp.1</name>
+ <description>hvtp.1 : min. hvtp width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp.2</name>
+ <description>hvtp.2 : min. hvtp spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr.1</name>
+ <description>hvtr.1 : min. hvtr width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr.2</name>
+ <description>hvtr.2 : min. hvtr spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr.2_a</name>
+ <description>hvtr.2_a : hvtr must not overlap hvtp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn.1a</name>
+ <description>lvtn.1a : min. lvtn width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn.2</name>
+ <description>lvtn.2 : min. lvtn spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm.1</name>
+ <description>ncm.1 : min. ncm width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm.2a</name>
+ <description>ncm.2a : min. ncm spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1</name>
+ <description>difftap.1 : min. diff width across areaid:ce : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1_a</name>
+ <description>difftap.1_a : min. diff width in periphery : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1_b</name>
+ <description>difftap.1_b : min. tap width across areaid:ce : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1_c</name>
+ <description>difftap.1_c : min. tap width in periphery : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.3</name>
+ <description>difftap.3 : min. difftap spacing : 0.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm.1</name>
+ <description>tunm.1 : min. tunm width : 0.41um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm.2</name>
+ <description>tunm.2 : min. tunm spacing : 0.5um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly.1a</name>
+ <description>poly.1a : min. poly width : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly.2</name>
+ <description>poly.2 : min. poly spacing : 0.21um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm.1a</name>
+ <description>rpm.1a : min. rpm width : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm.2</name>
+ <description>rpm.2 : min. rpm spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>urpm.1a</name>
+ <description>urpm.1a : min. rpm width : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>urpm.2</name>
+ <description>urpm.2 : min. rpm spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc.1</name>
+ <description>npc.1 : min. npc width : 0.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc.2</name>
+ <description>npc.2 : min. npc spacing, should be manually merged if less than : 0.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsd.1</name>
+ <description>nsd.1 : min. nsdm width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsd.2</name>
+ <description>nsd.2 : min. nsdm spacing, should be manually merged if less than : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psd.1</name>
+ <description>psd.1 : min. psdm width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psd.2</name>
+ <description>psd.2 : min. psdm spacing, should be manually merged if less than : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.1</name>
+ <description>licon.1 : licon should be rectangle</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.1_a/b</name>
+ <description>licon.1_a/b : minimum/maximum width of licon : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.13</name>
+ <description>licon.13 : min. difftap licon spacing to npc : 0.09um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.13_a</name>
+ <description>licon.13_a : licon of diffTap in periphery must not overlap npc</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.17</name>
+ <description>licon.17 : Licons may not overlap both poly and (diff or tap)</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.1</name>
+ <description>capm.1 : min. capm width : 1.0um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.2a</name>
+ <description>capm.2a : min. capm spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.2b</name>
+ <description>capm.2b : min. capm spacing : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.2b_a</name>
+ <description>capm.2b_a : min. spacing of m3_bot_plate : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.3</name>
+ <description>capm.3 : min. capm and m3 enclosure of m3 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.3_a</name>
+ <description>capm.3_a : min. m3 enclosure of capm : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.4</name>
+ <description>capm.4 : min. capm enclosure of via3 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.5</name>
+ <description>capm.5 : min. capm spacing to via3 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.1</name>
+ <description>cap2m.1 : min. cap2m width : 1.0um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.2a</name>
+ <description>cap2m.2a : min. cap2m spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.2b</name>
+ <description>cap2m.2b : min. cap2m spacing : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.2b_a</name>
+ <description>cap2m.2b_a : min. spacing of m4_bot_plate : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.3</name>
+ <description>cap2m.3 : min. m4 enclosure of cap2m : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.3_a</name>
+ <description>cap2m.3_a : min. m4 enclosure of cap2m : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.4</name>
+ <description>cap2m.4 : min. cap2m enclosure of via4 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.5</name>
+ <description>cap2m.5 : min. cap2m spacing to via4 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi.1</name>
+ <description>hvi.1 : min. hvi width : 0.6um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi.2a</name>
+ <description>hvi.2a : min. hvi spacing : 0.7um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm.1</name>
+ <description>hvntm.1 : min. hvntm width : 0.7um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm.2</name>
+ <description>hvntm.2 : min. hvntm spacing : 0.7um</description>
+ <categories>
+ </categories>
+ </category>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/reports/klayout_met_min_ca_density_check.xml b/mpw_precheck/outputs/reports/klayout_met_min_ca_density_check.xml
new file mode 100644
index 0000000..698a39a
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_met_min_ca_density_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>Density Checks</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/drc_checks/klayout/met_min_ca_density.lydrc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/reports/klayout_offgrid_check.xml b/mpw_precheck/outputs/reports/klayout_offgrid_check.xml
new file mode 100644
index 0000000..95ebbc9
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_offgrid_check.xml
@@ -0,0 +1,483 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ <category>
+ <name>dnwell_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on dnwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>dnwell_angle</name>
+ <description>x.3a : non 45 degree angle dnwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on nwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell_angle</name>
+ <description>x.3a : non 45 degree angle nwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwbm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pwbm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwbm_angle</name>
+ <description>x.3a : non 45 degree angle pwbm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwde_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pwde</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwde_angle</name>
+ <description>x.3a : non 45 degree angle pwde</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvtp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp_angle</name>
+ <description>x.3a : non 45 degree angle hvtp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvtr</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr_angle</name>
+ <description>x.3a : non 45 degree angle hvtr</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on lvtn</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn_angle</name>
+ <description>x.3a : non 45 degree angle lvtn</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on ncm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm_angle</name>
+ <description>x.3a : non 45 degree angle ncm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>diff_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on diff</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tap_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on tap</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>diff_angle</name>
+ <description>x.2 : non 90 degree angle diff</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>diff_angle</name>
+ <description>x.2c : non 45 degree angle diff</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tap_angle</name>
+ <description>x.2 : non 90 degree angle tap</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tap_angle</name>
+ <description>x.2c : non 45 degree angle tap</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on tunm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm_angle</name>
+ <description>x.3a : non 45 degree angle tunm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on poly</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly_angle</name>
+ <description>x.2 : non 90 degree angle poly</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on rpm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm_angle</name>
+ <description>x.3a : non 45 degree angle rpm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on npc</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc_angle</name>
+ <description>x.3a : non 45 degree angle npc</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsdm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on nsdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsdm_angle</name>
+ <description>x.3a : non 45 degree angle nsdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psdm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on psdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psdm_angle</name>
+ <description>x.3a : non 45 degree angle psdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on licon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon_angle</name>
+ <description>x.2 : non 90 degree angle licon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on li</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li_angle</name>
+ <description>x.3a : non 45 degree angle li</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on mcon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct_angle</name>
+ <description>x.2 : non 90 degree angle mcon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vpp_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on vpp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vpp_angle</name>
+ <description>x.3a : non 45 degree angle vpp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1_angle</name>
+ <description>x.3a : non 45 degree angle m1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via_angle</name>
+ <description>x.2 : non 90 degree angle via</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2_angle</name>
+ <description>x.3a : non 45 degree angle m2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2_angle</name>
+ <description>x.2 : non 90 degree angle via2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3_angle</name>
+ <description>x.3a : non 45 degree angle m3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3_angle</name>
+ <description>x.2 : non 90 degree angle via3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on nsm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsm_angle</name>
+ <description>x.3a : non 45 degree angle nsm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4_angle</name>
+ <description>x.3a : non 45 degree angle m4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4_angle</name>
+ <description>x.2 : non 90 degree angle via4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m5</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5_angle</name>
+ <description>x.3a : non 45 degree angle m5</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pad_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pad</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pad_angle</name>
+ <description>x.3a : non 45 degree angle pad</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mf_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on mf</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mf_angle</name>
+ <description>x.2 : non 90 degree angle mf</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi_angle</name>
+ <description>x.3a : non 45 degree angle hvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvntm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm_angle</name>
+ <description>x.3a : non 45 degree angle hvntm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vhvi_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on vhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vhvi_angle</name>
+ <description>x.3a : non 45 degree angle vhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>uhvi_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on uhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>uhvi_angle</name>
+ <description>x.3a : non 45 degree angle uhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwell_rs_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pwell_rs</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwell_rs_angle</name>
+ <description>x.3a : non 45 degree angle pwell_rs</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>areaid_re_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on areaid.re</description>
+ <categories>
+ </categories>
+ </category>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml b/mpw_precheck/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
new file mode 100644
index 0000000..85714f3
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>pin_label_purposes_overlapping_drawing.rb.drc, input=/root/riscduino_qcore_folk/gds/user_project_wrapper.gds, topcell=user_project_wrapper</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/drc_checks/klayout/pin_label_purposes_overlapping_drawing.rb.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/reports/klayout_zeroarea_check.xml b/mpw_precheck/outputs/reports/klayout_zeroarea_check.xml
new file mode 100644
index 0000000..7f95f69
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_zeroarea_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>zero area check</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/drc_checks/klayout/zeroarea.rb.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/reports/magic_drc_check.drc.report b/mpw_precheck/outputs/reports/magic_drc_check.drc.report
new file mode 100644
index 0000000..46ca7f3
--- /dev/null
+++ b/mpw_precheck/outputs/reports/magic_drc_check.drc.report
@@ -0,0 +1,5 @@
+user_project_wrapper
+----------------------------------------
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+
diff --git a/mpw_precheck/outputs/reports/magic_drc_check.rdb b/mpw_precheck/outputs/reports/magic_drc_check.rdb
new file mode 100644
index 0000000..ac5b3c4
--- /dev/null
+++ b/mpw_precheck/outputs/reports/magic_drc_check.rdb
@@ -0,0 +1,2 @@
+$user_project_wrapper
+ 100
diff --git a/mpw_precheck/outputs/reports/magic_drc_check.tcl b/mpw_precheck/outputs/reports/magic_drc_check.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/mpw_precheck/outputs/reports/magic_drc_check.tcl
diff --git a/mpw_precheck/outputs/reports/magic_drc_check.tr b/mpw_precheck/outputs/reports/magic_drc_check.tr
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/mpw_precheck/outputs/reports/magic_drc_check.tr
diff --git a/mpw_precheck/outputs/reports/magic_drc_check.xml b/mpw_precheck/outputs/reports/magic_drc_check.xml
new file mode 100644
index 0000000..0eff265
--- /dev/null
+++ b/mpw_precheck/outputs/reports/magic_drc_check.xml
@@ -0,0 +1,10 @@
+<?xml version="1.0" ?>
+<report-database>
+ <categories/>
+ <cells>
+ <cell>
+ <name>user_project_wrapper</name>
+ </cell>
+ </cells>
+ <items/>
+</report-database>
diff --git a/mpw_precheck/outputs/user_project_wrapper.filtered.v b/mpw_precheck/outputs/user_project_wrapper.filtered.v
new file mode 100644
index 0000000..ee9213a
--- /dev/null
+++ b/mpw_precheck/outputs/user_project_wrapper.filtered.v
@@ -0,0 +1,8753 @@
+module user_project_wrapper (user_clock2,
+ vccd1,
+ vccd2,
+ vdda1,
+ vdda2,
+ vssa1,
+ vssa2,
+ vssd1,
+ vssd2,
+ wb_clk_i,
+ wb_rst_i,
+ wbs_ack_o,
+ wbs_cyc_i,
+ wbs_stb_i,
+ wbs_we_i,
+ analog_io,
+ io_in,
+ io_oeb,
+ io_out,
+ la_data_in,
+ la_data_out,
+ la_oenb,
+ user_irq,
+ wbs_adr_i,
+ wbs_dat_i,
+ wbs_dat_o,
+ wbs_sel_i);
+ input user_clock2;
+ input vccd1;
+ input vccd2;
+ input vdda1;
+ input vdda2;
+ input vssa1;
+ input vssa2;
+ input vssd1;
+ input vssd2;
+ input wb_clk_i;
+ input wb_rst_i;
+ output wbs_ack_o;
+ input wbs_cyc_i;
+ input wbs_stb_i;
+ input wbs_we_i;
+ inout [28:0] analog_io;
+ input [37:0] io_in;
+ output [37:0] io_oeb;
+ output [37:0] io_out;
+ input [127:0] la_data_in;
+ output [127:0] la_data_out;
+ input [127:0] la_oenb;
+ output [2:0] user_irq;
+ input [31:0] wbs_adr_i;
+ input [31:0] wbs_dat_i;
+ output [31:0] wbs_dat_o;
+ input [3:0] wbs_sel_i;
+
+ wire \cfg_clk_ctrl1[0] ;
+ wire \cfg_clk_ctrl1[10] ;
+ wire \cfg_clk_ctrl1[11] ;
+ wire \cfg_clk_ctrl1[12] ;
+ wire \cfg_clk_ctrl1[13] ;
+ wire \cfg_clk_ctrl1[14] ;
+ wire \cfg_clk_ctrl1[15] ;
+ wire \cfg_clk_ctrl1[16] ;
+ wire \cfg_clk_ctrl1[17] ;
+ wire \cfg_clk_ctrl1[18] ;
+ wire \cfg_clk_ctrl1[19] ;
+ wire \cfg_clk_ctrl1[1] ;
+ wire \cfg_clk_ctrl1[20] ;
+ wire \cfg_clk_ctrl1[21] ;
+ wire \cfg_clk_ctrl1[22] ;
+ wire \cfg_clk_ctrl1[23] ;
+ wire \cfg_clk_ctrl1[24] ;
+ wire \cfg_clk_ctrl1[25] ;
+ wire \cfg_clk_ctrl1[26] ;
+ wire \cfg_clk_ctrl1[27] ;
+ wire \cfg_clk_ctrl1[28] ;
+ wire \cfg_clk_ctrl1[29] ;
+ wire \cfg_clk_ctrl1[2] ;
+ wire \cfg_clk_ctrl1[30] ;
+ wire \cfg_clk_ctrl1[31] ;
+ wire \cfg_clk_ctrl1[3] ;
+ wire \cfg_clk_ctrl1[4] ;
+ wire \cfg_clk_ctrl1[5] ;
+ wire \cfg_clk_ctrl1[6] ;
+ wire \cfg_clk_ctrl1[7] ;
+ wire \cfg_clk_ctrl1[8] ;
+ wire \cfg_clk_ctrl1[9] ;
+ wire \cfg_cska_pinmux_rp[0] ;
+ wire \cfg_cska_pinmux_rp[1] ;
+ wire \cfg_cska_pinmux_rp[2] ;
+ wire \cfg_cska_pinmux_rp[3] ;
+ wire \cfg_cska_qspi_co_rp[0] ;
+ wire \cfg_cska_qspi_co_rp[1] ;
+ wire \cfg_cska_qspi_co_rp[2] ;
+ wire \cfg_cska_qspi_co_rp[3] ;
+ wire \cfg_cska_qspi_rp[0] ;
+ wire \cfg_cska_qspi_rp[1] ;
+ wire \cfg_cska_qspi_rp[2] ;
+ wire \cfg_cska_qspi_rp[3] ;
+ wire \cfg_cska_uart_rp[0] ;
+ wire \cfg_cska_uart_rp[1] ;
+ wire \cfg_cska_uart_rp[2] ;
+ wire \cfg_cska_uart_rp[3] ;
+ wire \cfg_dc_trim[0] ;
+ wire \cfg_dc_trim[10] ;
+ wire \cfg_dc_trim[11] ;
+ wire \cfg_dc_trim[12] ;
+ wire \cfg_dc_trim[13] ;
+ wire \cfg_dc_trim[14] ;
+ wire \cfg_dc_trim[15] ;
+ wire \cfg_dc_trim[16] ;
+ wire \cfg_dc_trim[17] ;
+ wire \cfg_dc_trim[18] ;
+ wire \cfg_dc_trim[19] ;
+ wire \cfg_dc_trim[1] ;
+ wire \cfg_dc_trim[20] ;
+ wire \cfg_dc_trim[21] ;
+ wire \cfg_dc_trim[22] ;
+ wire \cfg_dc_trim[23] ;
+ wire \cfg_dc_trim[24] ;
+ wire \cfg_dc_trim[25] ;
+ wire \cfg_dc_trim[2] ;
+ wire \cfg_dc_trim[3] ;
+ wire \cfg_dc_trim[4] ;
+ wire \cfg_dc_trim[5] ;
+ wire \cfg_dc_trim[6] ;
+ wire \cfg_dc_trim[7] ;
+ wire \cfg_dc_trim[8] ;
+ wire \cfg_dc_trim[9] ;
+ wire cfg_dco_mode;
+ wire cfg_pll_enb;
+ wire \cfg_pll_fed_div[0] ;
+ wire \cfg_pll_fed_div[1] ;
+ wire \cfg_pll_fed_div[2] ;
+ wire \cfg_pll_fed_div[3] ;
+ wire \cfg_pll_fed_div[4] ;
+ wire \cfg_riscv_ctrl[0] ;
+ wire \cfg_riscv_ctrl[10] ;
+ wire \cfg_riscv_ctrl[11] ;
+ wire \cfg_riscv_ctrl[12] ;
+ wire \cfg_riscv_ctrl[13] ;
+ wire \cfg_riscv_ctrl[14] ;
+ wire \cfg_riscv_ctrl[15] ;
+ wire \cfg_riscv_ctrl[1] ;
+ wire \cfg_riscv_ctrl[2] ;
+ wire \cfg_riscv_ctrl[3] ;
+ wire \cfg_riscv_ctrl[4] ;
+ wire \cfg_riscv_ctrl[5] ;
+ wire \cfg_riscv_ctrl[6] ;
+ wire \cfg_riscv_ctrl[7] ;
+ wire \cfg_riscv_ctrl[8] ;
+ wire \cfg_riscv_ctrl[9] ;
+ wire dbg_clk_mon;
+ wire i2c_rst_n;
+ wire i2cm_clk_i;
+ wire i2cm_clk_o;
+ wire i2cm_clk_oen;
+ wire i2cm_data_i;
+ wire i2cm_data_o;
+ wire i2cm_data_oen;
+ wire i2cm_intr_o;
+ wire \irq_lines[0] ;
+ wire \irq_lines[10] ;
+ wire \irq_lines[11] ;
+ wire \irq_lines[12] ;
+ wire \irq_lines[13] ;
+ wire \irq_lines[14] ;
+ wire \irq_lines[15] ;
+ wire \irq_lines[1] ;
+ wire \irq_lines[2] ;
+ wire \irq_lines[3] ;
+ wire \irq_lines[4] ;
+ wire \irq_lines[5] ;
+ wire \irq_lines[6] ;
+ wire \irq_lines[7] ;
+ wire \irq_lines[8] ;
+ wire \irq_lines[9] ;
+ wire \pll_clk_out[0] ;
+ wire \pll_clk_out[1] ;
+ wire pll_ref_clk;
+ wire pulse1m_mclk;
+ wire qspim_rst_n;
+ wire \sflash_di[0] ;
+ wire \sflash_di[1] ;
+ wire \sflash_di[2] ;
+ wire \sflash_di[3] ;
+ wire \sflash_do[0] ;
+ wire \sflash_do[1] ;
+ wire \sflash_do[2] ;
+ wire \sflash_do[3] ;
+ wire \sflash_oen[0] ;
+ wire \sflash_oen[1] ;
+ wire \sflash_oen[2] ;
+ wire \sflash_oen[3] ;
+ wire sflash_sck;
+ wire soft_irq;
+ wire \spi_csn[0] ;
+ wire \spi_csn[1] ;
+ wire \spi_csn[2] ;
+ wire \spi_csn[3] ;
+ wire sspim_rst_n;
+ wire sspim_sck;
+ wire sspim_si;
+ wire sspim_so;
+ wire \sspim_ssn[0] ;
+ wire \sspim_ssn[1] ;
+ wire \sspim_ssn[2] ;
+ wire \sspim_ssn[3] ;
+ wire \u_riscv_top.cfg_cska_riscv[0] ;
+ wire \u_riscv_top.cfg_cska_riscv[1] ;
+ wire \u_riscv_top.cfg_cska_riscv[2] ;
+ wire \u_riscv_top.cfg_cska_riscv[3] ;
+ wire \u_riscv_top.cfg_dcache_force_flush ;
+ wire \u_riscv_top.core0_debug[0] ;
+ wire \u_riscv_top.core0_debug[10] ;
+ wire \u_riscv_top.core0_debug[11] ;
+ wire \u_riscv_top.core0_debug[12] ;
+ wire \u_riscv_top.core0_debug[13] ;
+ wire \u_riscv_top.core0_debug[14] ;
+ wire \u_riscv_top.core0_debug[15] ;
+ wire \u_riscv_top.core0_debug[16] ;
+ wire \u_riscv_top.core0_debug[17] ;
+ wire \u_riscv_top.core0_debug[18] ;
+ wire \u_riscv_top.core0_debug[19] ;
+ wire \u_riscv_top.core0_debug[1] ;
+ wire \u_riscv_top.core0_debug[20] ;
+ wire \u_riscv_top.core0_debug[21] ;
+ wire \u_riscv_top.core0_debug[22] ;
+ wire \u_riscv_top.core0_debug[23] ;
+ wire \u_riscv_top.core0_debug[24] ;
+ wire \u_riscv_top.core0_debug[25] ;
+ wire \u_riscv_top.core0_debug[26] ;
+ wire \u_riscv_top.core0_debug[27] ;
+ wire \u_riscv_top.core0_debug[28] ;
+ wire \u_riscv_top.core0_debug[29] ;
+ wire \u_riscv_top.core0_debug[2] ;
+ wire \u_riscv_top.core0_debug[30] ;
+ wire \u_riscv_top.core0_debug[31] ;
+ wire \u_riscv_top.core0_debug[32] ;
+ wire \u_riscv_top.core0_debug[33] ;
+ wire \u_riscv_top.core0_debug[34] ;
+ wire \u_riscv_top.core0_debug[35] ;
+ wire \u_riscv_top.core0_debug[36] ;
+ wire \u_riscv_top.core0_debug[37] ;
+ wire \u_riscv_top.core0_debug[38] ;
+ wire \u_riscv_top.core0_debug[39] ;
+ wire \u_riscv_top.core0_debug[3] ;
+ wire \u_riscv_top.core0_debug[40] ;
+ wire \u_riscv_top.core0_debug[41] ;
+ wire \u_riscv_top.core0_debug[42] ;
+ wire \u_riscv_top.core0_debug[43] ;
+ wire \u_riscv_top.core0_debug[44] ;
+ wire \u_riscv_top.core0_debug[45] ;
+ wire \u_riscv_top.core0_debug[46] ;
+ wire \u_riscv_top.core0_debug[47] ;
+ wire \u_riscv_top.core0_debug[48] ;
+ wire \u_riscv_top.core0_debug[4] ;
+ wire \u_riscv_top.core0_debug[5] ;
+ wire \u_riscv_top.core0_debug[6] ;
+ wire \u_riscv_top.core0_debug[7] ;
+ wire \u_riscv_top.core0_debug[8] ;
+ wire \u_riscv_top.core0_debug[9] ;
+ wire \u_riscv_top.core0_dmem_addr[0] ;
+ wire \u_riscv_top.core0_dmem_addr[10] ;
+ wire \u_riscv_top.core0_dmem_addr[11] ;
+ wire \u_riscv_top.core0_dmem_addr[12] ;
+ wire \u_riscv_top.core0_dmem_addr[13] ;
+ wire \u_riscv_top.core0_dmem_addr[14] ;
+ wire \u_riscv_top.core0_dmem_addr[15] ;
+ wire \u_riscv_top.core0_dmem_addr[16] ;
+ wire \u_riscv_top.core0_dmem_addr[17] ;
+ wire \u_riscv_top.core0_dmem_addr[18] ;
+ wire \u_riscv_top.core0_dmem_addr[19] ;
+ wire \u_riscv_top.core0_dmem_addr[1] ;
+ wire \u_riscv_top.core0_dmem_addr[20] ;
+ wire \u_riscv_top.core0_dmem_addr[21] ;
+ wire \u_riscv_top.core0_dmem_addr[22] ;
+ wire \u_riscv_top.core0_dmem_addr[23] ;
+ wire \u_riscv_top.core0_dmem_addr[24] ;
+ wire \u_riscv_top.core0_dmem_addr[25] ;
+ wire \u_riscv_top.core0_dmem_addr[26] ;
+ wire \u_riscv_top.core0_dmem_addr[27] ;
+ wire \u_riscv_top.core0_dmem_addr[28] ;
+ wire \u_riscv_top.core0_dmem_addr[29] ;
+ wire \u_riscv_top.core0_dmem_addr[2] ;
+ wire \u_riscv_top.core0_dmem_addr[30] ;
+ wire \u_riscv_top.core0_dmem_addr[31] ;
+ wire \u_riscv_top.core0_dmem_addr[3] ;
+ wire \u_riscv_top.core0_dmem_addr[4] ;
+ wire \u_riscv_top.core0_dmem_addr[5] ;
+ wire \u_riscv_top.core0_dmem_addr[6] ;
+ wire \u_riscv_top.core0_dmem_addr[7] ;
+ wire \u_riscv_top.core0_dmem_addr[8] ;
+ wire \u_riscv_top.core0_dmem_addr[9] ;
+ wire \u_riscv_top.core0_dmem_cmd ;
+ wire \u_riscv_top.core0_dmem_rdata[0] ;
+ wire \u_riscv_top.core0_dmem_rdata[10] ;
+ wire \u_riscv_top.core0_dmem_rdata[11] ;
+ wire \u_riscv_top.core0_dmem_rdata[12] ;
+ wire \u_riscv_top.core0_dmem_rdata[13] ;
+ wire \u_riscv_top.core0_dmem_rdata[14] ;
+ wire \u_riscv_top.core0_dmem_rdata[15] ;
+ wire \u_riscv_top.core0_dmem_rdata[16] ;
+ wire \u_riscv_top.core0_dmem_rdata[17] ;
+ wire \u_riscv_top.core0_dmem_rdata[18] ;
+ wire \u_riscv_top.core0_dmem_rdata[19] ;
+ wire \u_riscv_top.core0_dmem_rdata[1] ;
+ wire \u_riscv_top.core0_dmem_rdata[20] ;
+ wire \u_riscv_top.core0_dmem_rdata[21] ;
+ wire \u_riscv_top.core0_dmem_rdata[22] ;
+ wire \u_riscv_top.core0_dmem_rdata[23] ;
+ wire \u_riscv_top.core0_dmem_rdata[24] ;
+ wire \u_riscv_top.core0_dmem_rdata[25] ;
+ wire \u_riscv_top.core0_dmem_rdata[26] ;
+ wire \u_riscv_top.core0_dmem_rdata[27] ;
+ wire \u_riscv_top.core0_dmem_rdata[28] ;
+ wire \u_riscv_top.core0_dmem_rdata[29] ;
+ wire \u_riscv_top.core0_dmem_rdata[2] ;
+ wire \u_riscv_top.core0_dmem_rdata[30] ;
+ wire \u_riscv_top.core0_dmem_rdata[31] ;
+ wire \u_riscv_top.core0_dmem_rdata[3] ;
+ wire \u_riscv_top.core0_dmem_rdata[4] ;
+ wire \u_riscv_top.core0_dmem_rdata[5] ;
+ wire \u_riscv_top.core0_dmem_rdata[6] ;
+ wire \u_riscv_top.core0_dmem_rdata[7] ;
+ wire \u_riscv_top.core0_dmem_rdata[8] ;
+ wire \u_riscv_top.core0_dmem_rdata[9] ;
+ wire \u_riscv_top.core0_dmem_req ;
+ wire \u_riscv_top.core0_dmem_req_ack ;
+ wire \u_riscv_top.core0_dmem_resp[0] ;
+ wire \u_riscv_top.core0_dmem_resp[1] ;
+ wire \u_riscv_top.core0_dmem_wdata[0] ;
+ wire \u_riscv_top.core0_dmem_wdata[10] ;
+ wire \u_riscv_top.core0_dmem_wdata[11] ;
+ wire \u_riscv_top.core0_dmem_wdata[12] ;
+ wire \u_riscv_top.core0_dmem_wdata[13] ;
+ wire \u_riscv_top.core0_dmem_wdata[14] ;
+ wire \u_riscv_top.core0_dmem_wdata[15] ;
+ wire \u_riscv_top.core0_dmem_wdata[16] ;
+ wire \u_riscv_top.core0_dmem_wdata[17] ;
+ wire \u_riscv_top.core0_dmem_wdata[18] ;
+ wire \u_riscv_top.core0_dmem_wdata[19] ;
+ wire \u_riscv_top.core0_dmem_wdata[1] ;
+ wire \u_riscv_top.core0_dmem_wdata[20] ;
+ wire \u_riscv_top.core0_dmem_wdata[21] ;
+ wire \u_riscv_top.core0_dmem_wdata[22] ;
+ wire \u_riscv_top.core0_dmem_wdata[23] ;
+ wire \u_riscv_top.core0_dmem_wdata[24] ;
+ wire \u_riscv_top.core0_dmem_wdata[25] ;
+ wire \u_riscv_top.core0_dmem_wdata[26] ;
+ wire \u_riscv_top.core0_dmem_wdata[27] ;
+ wire \u_riscv_top.core0_dmem_wdata[28] ;
+ wire \u_riscv_top.core0_dmem_wdata[29] ;
+ wire \u_riscv_top.core0_dmem_wdata[2] ;
+ wire \u_riscv_top.core0_dmem_wdata[30] ;
+ wire \u_riscv_top.core0_dmem_wdata[31] ;
+ wire \u_riscv_top.core0_dmem_wdata[3] ;
+ wire \u_riscv_top.core0_dmem_wdata[4] ;
+ wire \u_riscv_top.core0_dmem_wdata[5] ;
+ wire \u_riscv_top.core0_dmem_wdata[6] ;
+ wire \u_riscv_top.core0_dmem_wdata[7] ;
+ wire \u_riscv_top.core0_dmem_wdata[8] ;
+ wire \u_riscv_top.core0_dmem_wdata[9] ;
+ wire \u_riscv_top.core0_dmem_width[0] ;
+ wire \u_riscv_top.core0_dmem_width[1] ;
+ wire \u_riscv_top.core0_imem_addr[0] ;
+ wire \u_riscv_top.core0_imem_addr[10] ;
+ wire \u_riscv_top.core0_imem_addr[11] ;
+ wire \u_riscv_top.core0_imem_addr[12] ;
+ wire \u_riscv_top.core0_imem_addr[13] ;
+ wire \u_riscv_top.core0_imem_addr[14] ;
+ wire \u_riscv_top.core0_imem_addr[15] ;
+ wire \u_riscv_top.core0_imem_addr[16] ;
+ wire \u_riscv_top.core0_imem_addr[17] ;
+ wire \u_riscv_top.core0_imem_addr[18] ;
+ wire \u_riscv_top.core0_imem_addr[19] ;
+ wire \u_riscv_top.core0_imem_addr[1] ;
+ wire \u_riscv_top.core0_imem_addr[20] ;
+ wire \u_riscv_top.core0_imem_addr[21] ;
+ wire \u_riscv_top.core0_imem_addr[22] ;
+ wire \u_riscv_top.core0_imem_addr[23] ;
+ wire \u_riscv_top.core0_imem_addr[24] ;
+ wire \u_riscv_top.core0_imem_addr[25] ;
+ wire \u_riscv_top.core0_imem_addr[26] ;
+ wire \u_riscv_top.core0_imem_addr[27] ;
+ wire \u_riscv_top.core0_imem_addr[28] ;
+ wire \u_riscv_top.core0_imem_addr[29] ;
+ wire \u_riscv_top.core0_imem_addr[2] ;
+ wire \u_riscv_top.core0_imem_addr[30] ;
+ wire \u_riscv_top.core0_imem_addr[31] ;
+ wire \u_riscv_top.core0_imem_addr[3] ;
+ wire \u_riscv_top.core0_imem_addr[4] ;
+ wire \u_riscv_top.core0_imem_addr[5] ;
+ wire \u_riscv_top.core0_imem_addr[6] ;
+ wire \u_riscv_top.core0_imem_addr[7] ;
+ wire \u_riscv_top.core0_imem_addr[8] ;
+ wire \u_riscv_top.core0_imem_addr[9] ;
+ wire \u_riscv_top.core0_imem_bl[0] ;
+ wire \u_riscv_top.core0_imem_bl[1] ;
+ wire \u_riscv_top.core0_imem_bl[2] ;
+ wire \u_riscv_top.core0_imem_cmd ;
+ wire \u_riscv_top.core0_imem_rdata[0] ;
+ wire \u_riscv_top.core0_imem_rdata[10] ;
+ wire \u_riscv_top.core0_imem_rdata[11] ;
+ wire \u_riscv_top.core0_imem_rdata[12] ;
+ wire \u_riscv_top.core0_imem_rdata[13] ;
+ wire \u_riscv_top.core0_imem_rdata[14] ;
+ wire \u_riscv_top.core0_imem_rdata[15] ;
+ wire \u_riscv_top.core0_imem_rdata[16] ;
+ wire \u_riscv_top.core0_imem_rdata[17] ;
+ wire \u_riscv_top.core0_imem_rdata[18] ;
+ wire \u_riscv_top.core0_imem_rdata[19] ;
+ wire \u_riscv_top.core0_imem_rdata[1] ;
+ wire \u_riscv_top.core0_imem_rdata[20] ;
+ wire \u_riscv_top.core0_imem_rdata[21] ;
+ wire \u_riscv_top.core0_imem_rdata[22] ;
+ wire \u_riscv_top.core0_imem_rdata[23] ;
+ wire \u_riscv_top.core0_imem_rdata[24] ;
+ wire \u_riscv_top.core0_imem_rdata[25] ;
+ wire \u_riscv_top.core0_imem_rdata[26] ;
+ wire \u_riscv_top.core0_imem_rdata[27] ;
+ wire \u_riscv_top.core0_imem_rdata[28] ;
+ wire \u_riscv_top.core0_imem_rdata[29] ;
+ wire \u_riscv_top.core0_imem_rdata[2] ;
+ wire \u_riscv_top.core0_imem_rdata[30] ;
+ wire \u_riscv_top.core0_imem_rdata[31] ;
+ wire \u_riscv_top.core0_imem_rdata[3] ;
+ wire \u_riscv_top.core0_imem_rdata[4] ;
+ wire \u_riscv_top.core0_imem_rdata[5] ;
+ wire \u_riscv_top.core0_imem_rdata[6] ;
+ wire \u_riscv_top.core0_imem_rdata[7] ;
+ wire \u_riscv_top.core0_imem_rdata[8] ;
+ wire \u_riscv_top.core0_imem_rdata[9] ;
+ wire \u_riscv_top.core0_imem_req ;
+ wire \u_riscv_top.core0_imem_req_ack ;
+ wire \u_riscv_top.core0_imem_resp[0] ;
+ wire \u_riscv_top.core0_imem_resp[1] ;
+ wire \u_riscv_top.core0_irq_lines[0] ;
+ wire \u_riscv_top.core0_irq_lines[10] ;
+ wire \u_riscv_top.core0_irq_lines[11] ;
+ wire \u_riscv_top.core0_irq_lines[12] ;
+ wire \u_riscv_top.core0_irq_lines[13] ;
+ wire \u_riscv_top.core0_irq_lines[14] ;
+ wire \u_riscv_top.core0_irq_lines[15] ;
+ wire \u_riscv_top.core0_irq_lines[1] ;
+ wire \u_riscv_top.core0_irq_lines[2] ;
+ wire \u_riscv_top.core0_irq_lines[3] ;
+ wire \u_riscv_top.core0_irq_lines[4] ;
+ wire \u_riscv_top.core0_irq_lines[5] ;
+ wire \u_riscv_top.core0_irq_lines[6] ;
+ wire \u_riscv_top.core0_irq_lines[7] ;
+ wire \u_riscv_top.core0_irq_lines[8] ;
+ wire \u_riscv_top.core0_irq_lines[9] ;
+ wire \u_riscv_top.core0_soft_irq ;
+ wire \u_riscv_top.core0_timer_irq ;
+ wire \u_riscv_top.core0_timer_val[0] ;
+ wire \u_riscv_top.core0_timer_val[10] ;
+ wire \u_riscv_top.core0_timer_val[11] ;
+ wire \u_riscv_top.core0_timer_val[12] ;
+ wire \u_riscv_top.core0_timer_val[13] ;
+ wire \u_riscv_top.core0_timer_val[14] ;
+ wire \u_riscv_top.core0_timer_val[15] ;
+ wire \u_riscv_top.core0_timer_val[16] ;
+ wire \u_riscv_top.core0_timer_val[17] ;
+ wire \u_riscv_top.core0_timer_val[18] ;
+ wire \u_riscv_top.core0_timer_val[19] ;
+ wire \u_riscv_top.core0_timer_val[1] ;
+ wire \u_riscv_top.core0_timer_val[20] ;
+ wire \u_riscv_top.core0_timer_val[21] ;
+ wire \u_riscv_top.core0_timer_val[22] ;
+ wire \u_riscv_top.core0_timer_val[23] ;
+ wire \u_riscv_top.core0_timer_val[24] ;
+ wire \u_riscv_top.core0_timer_val[25] ;
+ wire \u_riscv_top.core0_timer_val[26] ;
+ wire \u_riscv_top.core0_timer_val[27] ;
+ wire \u_riscv_top.core0_timer_val[28] ;
+ wire \u_riscv_top.core0_timer_val[29] ;
+ wire \u_riscv_top.core0_timer_val[2] ;
+ wire \u_riscv_top.core0_timer_val[30] ;
+ wire \u_riscv_top.core0_timer_val[31] ;
+ wire \u_riscv_top.core0_timer_val[32] ;
+ wire \u_riscv_top.core0_timer_val[33] ;
+ wire \u_riscv_top.core0_timer_val[34] ;
+ wire \u_riscv_top.core0_timer_val[35] ;
+ wire \u_riscv_top.core0_timer_val[36] ;
+ wire \u_riscv_top.core0_timer_val[37] ;
+ wire \u_riscv_top.core0_timer_val[38] ;
+ wire \u_riscv_top.core0_timer_val[39] ;
+ wire \u_riscv_top.core0_timer_val[3] ;
+ wire \u_riscv_top.core0_timer_val[40] ;
+ wire \u_riscv_top.core0_timer_val[41] ;
+ wire \u_riscv_top.core0_timer_val[42] ;
+ wire \u_riscv_top.core0_timer_val[43] ;
+ wire \u_riscv_top.core0_timer_val[44] ;
+ wire \u_riscv_top.core0_timer_val[45] ;
+ wire \u_riscv_top.core0_timer_val[46] ;
+ wire \u_riscv_top.core0_timer_val[47] ;
+ wire \u_riscv_top.core0_timer_val[48] ;
+ wire \u_riscv_top.core0_timer_val[49] ;
+ wire \u_riscv_top.core0_timer_val[4] ;
+ wire \u_riscv_top.core0_timer_val[50] ;
+ wire \u_riscv_top.core0_timer_val[51] ;
+ wire \u_riscv_top.core0_timer_val[52] ;
+ wire \u_riscv_top.core0_timer_val[53] ;
+ wire \u_riscv_top.core0_timer_val[54] ;
+ wire \u_riscv_top.core0_timer_val[55] ;
+ wire \u_riscv_top.core0_timer_val[56] ;
+ wire \u_riscv_top.core0_timer_val[57] ;
+ wire \u_riscv_top.core0_timer_val[58] ;
+ wire \u_riscv_top.core0_timer_val[59] ;
+ wire \u_riscv_top.core0_timer_val[5] ;
+ wire \u_riscv_top.core0_timer_val[60] ;
+ wire \u_riscv_top.core0_timer_val[61] ;
+ wire \u_riscv_top.core0_timer_val[62] ;
+ wire \u_riscv_top.core0_timer_val[63] ;
+ wire \u_riscv_top.core0_timer_val[6] ;
+ wire \u_riscv_top.core0_timer_val[7] ;
+ wire \u_riscv_top.core0_timer_val[8] ;
+ wire \u_riscv_top.core0_timer_val[9] ;
+ wire \u_riscv_top.core0_uid[0] ;
+ wire \u_riscv_top.core0_uid[1] ;
+ wire \u_riscv_top.core1_debug[0] ;
+ wire \u_riscv_top.core1_debug[10] ;
+ wire \u_riscv_top.core1_debug[11] ;
+ wire \u_riscv_top.core1_debug[12] ;
+ wire \u_riscv_top.core1_debug[13] ;
+ wire \u_riscv_top.core1_debug[14] ;
+ wire \u_riscv_top.core1_debug[15] ;
+ wire \u_riscv_top.core1_debug[16] ;
+ wire \u_riscv_top.core1_debug[17] ;
+ wire \u_riscv_top.core1_debug[18] ;
+ wire \u_riscv_top.core1_debug[19] ;
+ wire \u_riscv_top.core1_debug[1] ;
+ wire \u_riscv_top.core1_debug[20] ;
+ wire \u_riscv_top.core1_debug[21] ;
+ wire \u_riscv_top.core1_debug[22] ;
+ wire \u_riscv_top.core1_debug[23] ;
+ wire \u_riscv_top.core1_debug[24] ;
+ wire \u_riscv_top.core1_debug[25] ;
+ wire \u_riscv_top.core1_debug[26] ;
+ wire \u_riscv_top.core1_debug[27] ;
+ wire \u_riscv_top.core1_debug[28] ;
+ wire \u_riscv_top.core1_debug[29] ;
+ wire \u_riscv_top.core1_debug[2] ;
+ wire \u_riscv_top.core1_debug[30] ;
+ wire \u_riscv_top.core1_debug[31] ;
+ wire \u_riscv_top.core1_debug[32] ;
+ wire \u_riscv_top.core1_debug[33] ;
+ wire \u_riscv_top.core1_debug[34] ;
+ wire \u_riscv_top.core1_debug[35] ;
+ wire \u_riscv_top.core1_debug[36] ;
+ wire \u_riscv_top.core1_debug[37] ;
+ wire \u_riscv_top.core1_debug[38] ;
+ wire \u_riscv_top.core1_debug[39] ;
+ wire \u_riscv_top.core1_debug[3] ;
+ wire \u_riscv_top.core1_debug[40] ;
+ wire \u_riscv_top.core1_debug[41] ;
+ wire \u_riscv_top.core1_debug[42] ;
+ wire \u_riscv_top.core1_debug[43] ;
+ wire \u_riscv_top.core1_debug[44] ;
+ wire \u_riscv_top.core1_debug[45] ;
+ wire \u_riscv_top.core1_debug[46] ;
+ wire \u_riscv_top.core1_debug[47] ;
+ wire \u_riscv_top.core1_debug[48] ;
+ wire \u_riscv_top.core1_debug[4] ;
+ wire \u_riscv_top.core1_debug[5] ;
+ wire \u_riscv_top.core1_debug[6] ;
+ wire \u_riscv_top.core1_debug[7] ;
+ wire \u_riscv_top.core1_debug[8] ;
+ wire \u_riscv_top.core1_debug[9] ;
+ wire \u_riscv_top.core1_dmem_addr[0] ;
+ wire \u_riscv_top.core1_dmem_addr[10] ;
+ wire \u_riscv_top.core1_dmem_addr[11] ;
+ wire \u_riscv_top.core1_dmem_addr[12] ;
+ wire \u_riscv_top.core1_dmem_addr[13] ;
+ wire \u_riscv_top.core1_dmem_addr[14] ;
+ wire \u_riscv_top.core1_dmem_addr[15] ;
+ wire \u_riscv_top.core1_dmem_addr[16] ;
+ wire \u_riscv_top.core1_dmem_addr[17] ;
+ wire \u_riscv_top.core1_dmem_addr[18] ;
+ wire \u_riscv_top.core1_dmem_addr[19] ;
+ wire \u_riscv_top.core1_dmem_addr[1] ;
+ wire \u_riscv_top.core1_dmem_addr[20] ;
+ wire \u_riscv_top.core1_dmem_addr[21] ;
+ wire \u_riscv_top.core1_dmem_addr[22] ;
+ wire \u_riscv_top.core1_dmem_addr[23] ;
+ wire \u_riscv_top.core1_dmem_addr[24] ;
+ wire \u_riscv_top.core1_dmem_addr[25] ;
+ wire \u_riscv_top.core1_dmem_addr[26] ;
+ wire \u_riscv_top.core1_dmem_addr[27] ;
+ wire \u_riscv_top.core1_dmem_addr[28] ;
+ wire \u_riscv_top.core1_dmem_addr[29] ;
+ wire \u_riscv_top.core1_dmem_addr[2] ;
+ wire \u_riscv_top.core1_dmem_addr[30] ;
+ wire \u_riscv_top.core1_dmem_addr[31] ;
+ wire \u_riscv_top.core1_dmem_addr[3] ;
+ wire \u_riscv_top.core1_dmem_addr[4] ;
+ wire \u_riscv_top.core1_dmem_addr[5] ;
+ wire \u_riscv_top.core1_dmem_addr[6] ;
+ wire \u_riscv_top.core1_dmem_addr[7] ;
+ wire \u_riscv_top.core1_dmem_addr[8] ;
+ wire \u_riscv_top.core1_dmem_addr[9] ;
+ wire \u_riscv_top.core1_dmem_cmd ;
+ wire \u_riscv_top.core1_dmem_rdata[0] ;
+ wire \u_riscv_top.core1_dmem_rdata[10] ;
+ wire \u_riscv_top.core1_dmem_rdata[11] ;
+ wire \u_riscv_top.core1_dmem_rdata[12] ;
+ wire \u_riscv_top.core1_dmem_rdata[13] ;
+ wire \u_riscv_top.core1_dmem_rdata[14] ;
+ wire \u_riscv_top.core1_dmem_rdata[15] ;
+ wire \u_riscv_top.core1_dmem_rdata[16] ;
+ wire \u_riscv_top.core1_dmem_rdata[17] ;
+ wire \u_riscv_top.core1_dmem_rdata[18] ;
+ wire \u_riscv_top.core1_dmem_rdata[19] ;
+ wire \u_riscv_top.core1_dmem_rdata[1] ;
+ wire \u_riscv_top.core1_dmem_rdata[20] ;
+ wire \u_riscv_top.core1_dmem_rdata[21] ;
+ wire \u_riscv_top.core1_dmem_rdata[22] ;
+ wire \u_riscv_top.core1_dmem_rdata[23] ;
+ wire \u_riscv_top.core1_dmem_rdata[24] ;
+ wire \u_riscv_top.core1_dmem_rdata[25] ;
+ wire \u_riscv_top.core1_dmem_rdata[26] ;
+ wire \u_riscv_top.core1_dmem_rdata[27] ;
+ wire \u_riscv_top.core1_dmem_rdata[28] ;
+ wire \u_riscv_top.core1_dmem_rdata[29] ;
+ wire \u_riscv_top.core1_dmem_rdata[2] ;
+ wire \u_riscv_top.core1_dmem_rdata[30] ;
+ wire \u_riscv_top.core1_dmem_rdata[31] ;
+ wire \u_riscv_top.core1_dmem_rdata[3] ;
+ wire \u_riscv_top.core1_dmem_rdata[4] ;
+ wire \u_riscv_top.core1_dmem_rdata[5] ;
+ wire \u_riscv_top.core1_dmem_rdata[6] ;
+ wire \u_riscv_top.core1_dmem_rdata[7] ;
+ wire \u_riscv_top.core1_dmem_rdata[8] ;
+ wire \u_riscv_top.core1_dmem_rdata[9] ;
+ wire \u_riscv_top.core1_dmem_req ;
+ wire \u_riscv_top.core1_dmem_req_ack ;
+ wire \u_riscv_top.core1_dmem_resp[0] ;
+ wire \u_riscv_top.core1_dmem_resp[1] ;
+ wire \u_riscv_top.core1_dmem_wdata[0] ;
+ wire \u_riscv_top.core1_dmem_wdata[10] ;
+ wire \u_riscv_top.core1_dmem_wdata[11] ;
+ wire \u_riscv_top.core1_dmem_wdata[12] ;
+ wire \u_riscv_top.core1_dmem_wdata[13] ;
+ wire \u_riscv_top.core1_dmem_wdata[14] ;
+ wire \u_riscv_top.core1_dmem_wdata[15] ;
+ wire \u_riscv_top.core1_dmem_wdata[16] ;
+ wire \u_riscv_top.core1_dmem_wdata[17] ;
+ wire \u_riscv_top.core1_dmem_wdata[18] ;
+ wire \u_riscv_top.core1_dmem_wdata[19] ;
+ wire \u_riscv_top.core1_dmem_wdata[1] ;
+ wire \u_riscv_top.core1_dmem_wdata[20] ;
+ wire \u_riscv_top.core1_dmem_wdata[21] ;
+ wire \u_riscv_top.core1_dmem_wdata[22] ;
+ wire \u_riscv_top.core1_dmem_wdata[23] ;
+ wire \u_riscv_top.core1_dmem_wdata[24] ;
+ wire \u_riscv_top.core1_dmem_wdata[25] ;
+ wire \u_riscv_top.core1_dmem_wdata[26] ;
+ wire \u_riscv_top.core1_dmem_wdata[27] ;
+ wire \u_riscv_top.core1_dmem_wdata[28] ;
+ wire \u_riscv_top.core1_dmem_wdata[29] ;
+ wire \u_riscv_top.core1_dmem_wdata[2] ;
+ wire \u_riscv_top.core1_dmem_wdata[30] ;
+ wire \u_riscv_top.core1_dmem_wdata[31] ;
+ wire \u_riscv_top.core1_dmem_wdata[3] ;
+ wire \u_riscv_top.core1_dmem_wdata[4] ;
+ wire \u_riscv_top.core1_dmem_wdata[5] ;
+ wire \u_riscv_top.core1_dmem_wdata[6] ;
+ wire \u_riscv_top.core1_dmem_wdata[7] ;
+ wire \u_riscv_top.core1_dmem_wdata[8] ;
+ wire \u_riscv_top.core1_dmem_wdata[9] ;
+ wire \u_riscv_top.core1_dmem_width[0] ;
+ wire \u_riscv_top.core1_dmem_width[1] ;
+ wire \u_riscv_top.core1_imem_addr[0] ;
+ wire \u_riscv_top.core1_imem_addr[10] ;
+ wire \u_riscv_top.core1_imem_addr[11] ;
+ wire \u_riscv_top.core1_imem_addr[12] ;
+ wire \u_riscv_top.core1_imem_addr[13] ;
+ wire \u_riscv_top.core1_imem_addr[14] ;
+ wire \u_riscv_top.core1_imem_addr[15] ;
+ wire \u_riscv_top.core1_imem_addr[16] ;
+ wire \u_riscv_top.core1_imem_addr[17] ;
+ wire \u_riscv_top.core1_imem_addr[18] ;
+ wire \u_riscv_top.core1_imem_addr[19] ;
+ wire \u_riscv_top.core1_imem_addr[1] ;
+ wire \u_riscv_top.core1_imem_addr[20] ;
+ wire \u_riscv_top.core1_imem_addr[21] ;
+ wire \u_riscv_top.core1_imem_addr[22] ;
+ wire \u_riscv_top.core1_imem_addr[23] ;
+ wire \u_riscv_top.core1_imem_addr[24] ;
+ wire \u_riscv_top.core1_imem_addr[25] ;
+ wire \u_riscv_top.core1_imem_addr[26] ;
+ wire \u_riscv_top.core1_imem_addr[27] ;
+ wire \u_riscv_top.core1_imem_addr[28] ;
+ wire \u_riscv_top.core1_imem_addr[29] ;
+ wire \u_riscv_top.core1_imem_addr[2] ;
+ wire \u_riscv_top.core1_imem_addr[30] ;
+ wire \u_riscv_top.core1_imem_addr[31] ;
+ wire \u_riscv_top.core1_imem_addr[3] ;
+ wire \u_riscv_top.core1_imem_addr[4] ;
+ wire \u_riscv_top.core1_imem_addr[5] ;
+ wire \u_riscv_top.core1_imem_addr[6] ;
+ wire \u_riscv_top.core1_imem_addr[7] ;
+ wire \u_riscv_top.core1_imem_addr[8] ;
+ wire \u_riscv_top.core1_imem_addr[9] ;
+ wire \u_riscv_top.core1_imem_bl[0] ;
+ wire \u_riscv_top.core1_imem_bl[1] ;
+ wire \u_riscv_top.core1_imem_bl[2] ;
+ wire \u_riscv_top.core1_imem_cmd ;
+ wire \u_riscv_top.core1_imem_rdata[0] ;
+ wire \u_riscv_top.core1_imem_rdata[10] ;
+ wire \u_riscv_top.core1_imem_rdata[11] ;
+ wire \u_riscv_top.core1_imem_rdata[12] ;
+ wire \u_riscv_top.core1_imem_rdata[13] ;
+ wire \u_riscv_top.core1_imem_rdata[14] ;
+ wire \u_riscv_top.core1_imem_rdata[15] ;
+ wire \u_riscv_top.core1_imem_rdata[16] ;
+ wire \u_riscv_top.core1_imem_rdata[17] ;
+ wire \u_riscv_top.core1_imem_rdata[18] ;
+ wire \u_riscv_top.core1_imem_rdata[19] ;
+ wire \u_riscv_top.core1_imem_rdata[1] ;
+ wire \u_riscv_top.core1_imem_rdata[20] ;
+ wire \u_riscv_top.core1_imem_rdata[21] ;
+ wire \u_riscv_top.core1_imem_rdata[22] ;
+ wire \u_riscv_top.core1_imem_rdata[23] ;
+ wire \u_riscv_top.core1_imem_rdata[24] ;
+ wire \u_riscv_top.core1_imem_rdata[25] ;
+ wire \u_riscv_top.core1_imem_rdata[26] ;
+ wire \u_riscv_top.core1_imem_rdata[27] ;
+ wire \u_riscv_top.core1_imem_rdata[28] ;
+ wire \u_riscv_top.core1_imem_rdata[29] ;
+ wire \u_riscv_top.core1_imem_rdata[2] ;
+ wire \u_riscv_top.core1_imem_rdata[30] ;
+ wire \u_riscv_top.core1_imem_rdata[31] ;
+ wire \u_riscv_top.core1_imem_rdata[3] ;
+ wire \u_riscv_top.core1_imem_rdata[4] ;
+ wire \u_riscv_top.core1_imem_rdata[5] ;
+ wire \u_riscv_top.core1_imem_rdata[6] ;
+ wire \u_riscv_top.core1_imem_rdata[7] ;
+ wire \u_riscv_top.core1_imem_rdata[8] ;
+ wire \u_riscv_top.core1_imem_rdata[9] ;
+ wire \u_riscv_top.core1_imem_req ;
+ wire \u_riscv_top.core1_imem_req_ack ;
+ wire \u_riscv_top.core1_imem_resp[0] ;
+ wire \u_riscv_top.core1_imem_resp[1] ;
+ wire \u_riscv_top.core1_irq_lines[0] ;
+ wire \u_riscv_top.core1_irq_lines[10] ;
+ wire \u_riscv_top.core1_irq_lines[11] ;
+ wire \u_riscv_top.core1_irq_lines[12] ;
+ wire \u_riscv_top.core1_irq_lines[13] ;
+ wire \u_riscv_top.core1_irq_lines[14] ;
+ wire \u_riscv_top.core1_irq_lines[15] ;
+ wire \u_riscv_top.core1_irq_lines[1] ;
+ wire \u_riscv_top.core1_irq_lines[2] ;
+ wire \u_riscv_top.core1_irq_lines[3] ;
+ wire \u_riscv_top.core1_irq_lines[4] ;
+ wire \u_riscv_top.core1_irq_lines[5] ;
+ wire \u_riscv_top.core1_irq_lines[6] ;
+ wire \u_riscv_top.core1_irq_lines[7] ;
+ wire \u_riscv_top.core1_irq_lines[8] ;
+ wire \u_riscv_top.core1_irq_lines[9] ;
+ wire \u_riscv_top.core1_soft_irq ;
+ wire \u_riscv_top.core1_timer_irq ;
+ wire \u_riscv_top.core1_timer_val[0] ;
+ wire \u_riscv_top.core1_timer_val[10] ;
+ wire \u_riscv_top.core1_timer_val[11] ;
+ wire \u_riscv_top.core1_timer_val[12] ;
+ wire \u_riscv_top.core1_timer_val[13] ;
+ wire \u_riscv_top.core1_timer_val[14] ;
+ wire \u_riscv_top.core1_timer_val[15] ;
+ wire \u_riscv_top.core1_timer_val[16] ;
+ wire \u_riscv_top.core1_timer_val[17] ;
+ wire \u_riscv_top.core1_timer_val[18] ;
+ wire \u_riscv_top.core1_timer_val[19] ;
+ wire \u_riscv_top.core1_timer_val[1] ;
+ wire \u_riscv_top.core1_timer_val[20] ;
+ wire \u_riscv_top.core1_timer_val[21] ;
+ wire \u_riscv_top.core1_timer_val[22] ;
+ wire \u_riscv_top.core1_timer_val[23] ;
+ wire \u_riscv_top.core1_timer_val[24] ;
+ wire \u_riscv_top.core1_timer_val[25] ;
+ wire \u_riscv_top.core1_timer_val[26] ;
+ wire \u_riscv_top.core1_timer_val[27] ;
+ wire \u_riscv_top.core1_timer_val[28] ;
+ wire \u_riscv_top.core1_timer_val[29] ;
+ wire \u_riscv_top.core1_timer_val[2] ;
+ wire \u_riscv_top.core1_timer_val[30] ;
+ wire \u_riscv_top.core1_timer_val[31] ;
+ wire \u_riscv_top.core1_timer_val[32] ;
+ wire \u_riscv_top.core1_timer_val[33] ;
+ wire \u_riscv_top.core1_timer_val[34] ;
+ wire \u_riscv_top.core1_timer_val[35] ;
+ wire \u_riscv_top.core1_timer_val[36] ;
+ wire \u_riscv_top.core1_timer_val[37] ;
+ wire \u_riscv_top.core1_timer_val[38] ;
+ wire \u_riscv_top.core1_timer_val[39] ;
+ wire \u_riscv_top.core1_timer_val[3] ;
+ wire \u_riscv_top.core1_timer_val[40] ;
+ wire \u_riscv_top.core1_timer_val[41] ;
+ wire \u_riscv_top.core1_timer_val[42] ;
+ wire \u_riscv_top.core1_timer_val[43] ;
+ wire \u_riscv_top.core1_timer_val[44] ;
+ wire \u_riscv_top.core1_timer_val[45] ;
+ wire \u_riscv_top.core1_timer_val[46] ;
+ wire \u_riscv_top.core1_timer_val[47] ;
+ wire \u_riscv_top.core1_timer_val[48] ;
+ wire \u_riscv_top.core1_timer_val[49] ;
+ wire \u_riscv_top.core1_timer_val[4] ;
+ wire \u_riscv_top.core1_timer_val[50] ;
+ wire \u_riscv_top.core1_timer_val[51] ;
+ wire \u_riscv_top.core1_timer_val[52] ;
+ wire \u_riscv_top.core1_timer_val[53] ;
+ wire \u_riscv_top.core1_timer_val[54] ;
+ wire \u_riscv_top.core1_timer_val[55] ;
+ wire \u_riscv_top.core1_timer_val[56] ;
+ wire \u_riscv_top.core1_timer_val[57] ;
+ wire \u_riscv_top.core1_timer_val[58] ;
+ wire \u_riscv_top.core1_timer_val[59] ;
+ wire \u_riscv_top.core1_timer_val[5] ;
+ wire \u_riscv_top.core1_timer_val[60] ;
+ wire \u_riscv_top.core1_timer_val[61] ;
+ wire \u_riscv_top.core1_timer_val[62] ;
+ wire \u_riscv_top.core1_timer_val[63] ;
+ wire \u_riscv_top.core1_timer_val[6] ;
+ wire \u_riscv_top.core1_timer_val[7] ;
+ wire \u_riscv_top.core1_timer_val[8] ;
+ wire \u_riscv_top.core1_timer_val[9] ;
+ wire \u_riscv_top.core1_uid[0] ;
+ wire \u_riscv_top.core1_uid[1] ;
+ wire \u_riscv_top.core2_debug[0] ;
+ wire \u_riscv_top.core2_debug[10] ;
+ wire \u_riscv_top.core2_debug[11] ;
+ wire \u_riscv_top.core2_debug[12] ;
+ wire \u_riscv_top.core2_debug[13] ;
+ wire \u_riscv_top.core2_debug[14] ;
+ wire \u_riscv_top.core2_debug[15] ;
+ wire \u_riscv_top.core2_debug[16] ;
+ wire \u_riscv_top.core2_debug[17] ;
+ wire \u_riscv_top.core2_debug[18] ;
+ wire \u_riscv_top.core2_debug[19] ;
+ wire \u_riscv_top.core2_debug[1] ;
+ wire \u_riscv_top.core2_debug[20] ;
+ wire \u_riscv_top.core2_debug[21] ;
+ wire \u_riscv_top.core2_debug[22] ;
+ wire \u_riscv_top.core2_debug[23] ;
+ wire \u_riscv_top.core2_debug[24] ;
+ wire \u_riscv_top.core2_debug[25] ;
+ wire \u_riscv_top.core2_debug[26] ;
+ wire \u_riscv_top.core2_debug[27] ;
+ wire \u_riscv_top.core2_debug[28] ;
+ wire \u_riscv_top.core2_debug[29] ;
+ wire \u_riscv_top.core2_debug[2] ;
+ wire \u_riscv_top.core2_debug[30] ;
+ wire \u_riscv_top.core2_debug[31] ;
+ wire \u_riscv_top.core2_debug[32] ;
+ wire \u_riscv_top.core2_debug[33] ;
+ wire \u_riscv_top.core2_debug[34] ;
+ wire \u_riscv_top.core2_debug[35] ;
+ wire \u_riscv_top.core2_debug[36] ;
+ wire \u_riscv_top.core2_debug[37] ;
+ wire \u_riscv_top.core2_debug[38] ;
+ wire \u_riscv_top.core2_debug[39] ;
+ wire \u_riscv_top.core2_debug[3] ;
+ wire \u_riscv_top.core2_debug[40] ;
+ wire \u_riscv_top.core2_debug[41] ;
+ wire \u_riscv_top.core2_debug[42] ;
+ wire \u_riscv_top.core2_debug[43] ;
+ wire \u_riscv_top.core2_debug[44] ;
+ wire \u_riscv_top.core2_debug[45] ;
+ wire \u_riscv_top.core2_debug[46] ;
+ wire \u_riscv_top.core2_debug[47] ;
+ wire \u_riscv_top.core2_debug[48] ;
+ wire \u_riscv_top.core2_debug[4] ;
+ wire \u_riscv_top.core2_debug[5] ;
+ wire \u_riscv_top.core2_debug[6] ;
+ wire \u_riscv_top.core2_debug[7] ;
+ wire \u_riscv_top.core2_debug[8] ;
+ wire \u_riscv_top.core2_debug[9] ;
+ wire \u_riscv_top.core2_dmem_addr[0] ;
+ wire \u_riscv_top.core2_dmem_addr[10] ;
+ wire \u_riscv_top.core2_dmem_addr[11] ;
+ wire \u_riscv_top.core2_dmem_addr[12] ;
+ wire \u_riscv_top.core2_dmem_addr[13] ;
+ wire \u_riscv_top.core2_dmem_addr[14] ;
+ wire \u_riscv_top.core2_dmem_addr[15] ;
+ wire \u_riscv_top.core2_dmem_addr[16] ;
+ wire \u_riscv_top.core2_dmem_addr[17] ;
+ wire \u_riscv_top.core2_dmem_addr[18] ;
+ wire \u_riscv_top.core2_dmem_addr[19] ;
+ wire \u_riscv_top.core2_dmem_addr[1] ;
+ wire \u_riscv_top.core2_dmem_addr[20] ;
+ wire \u_riscv_top.core2_dmem_addr[21] ;
+ wire \u_riscv_top.core2_dmem_addr[22] ;
+ wire \u_riscv_top.core2_dmem_addr[23] ;
+ wire \u_riscv_top.core2_dmem_addr[24] ;
+ wire \u_riscv_top.core2_dmem_addr[25] ;
+ wire \u_riscv_top.core2_dmem_addr[26] ;
+ wire \u_riscv_top.core2_dmem_addr[27] ;
+ wire \u_riscv_top.core2_dmem_addr[28] ;
+ wire \u_riscv_top.core2_dmem_addr[29] ;
+ wire \u_riscv_top.core2_dmem_addr[2] ;
+ wire \u_riscv_top.core2_dmem_addr[30] ;
+ wire \u_riscv_top.core2_dmem_addr[31] ;
+ wire \u_riscv_top.core2_dmem_addr[3] ;
+ wire \u_riscv_top.core2_dmem_addr[4] ;
+ wire \u_riscv_top.core2_dmem_addr[5] ;
+ wire \u_riscv_top.core2_dmem_addr[6] ;
+ wire \u_riscv_top.core2_dmem_addr[7] ;
+ wire \u_riscv_top.core2_dmem_addr[8] ;
+ wire \u_riscv_top.core2_dmem_addr[9] ;
+ wire \u_riscv_top.core2_dmem_cmd ;
+ wire \u_riscv_top.core2_dmem_rdata[0] ;
+ wire \u_riscv_top.core2_dmem_rdata[10] ;
+ wire \u_riscv_top.core2_dmem_rdata[11] ;
+ wire \u_riscv_top.core2_dmem_rdata[12] ;
+ wire \u_riscv_top.core2_dmem_rdata[13] ;
+ wire \u_riscv_top.core2_dmem_rdata[14] ;
+ wire \u_riscv_top.core2_dmem_rdata[15] ;
+ wire \u_riscv_top.core2_dmem_rdata[16] ;
+ wire \u_riscv_top.core2_dmem_rdata[17] ;
+ wire \u_riscv_top.core2_dmem_rdata[18] ;
+ wire \u_riscv_top.core2_dmem_rdata[19] ;
+ wire \u_riscv_top.core2_dmem_rdata[1] ;
+ wire \u_riscv_top.core2_dmem_rdata[20] ;
+ wire \u_riscv_top.core2_dmem_rdata[21] ;
+ wire \u_riscv_top.core2_dmem_rdata[22] ;
+ wire \u_riscv_top.core2_dmem_rdata[23] ;
+ wire \u_riscv_top.core2_dmem_rdata[24] ;
+ wire \u_riscv_top.core2_dmem_rdata[25] ;
+ wire \u_riscv_top.core2_dmem_rdata[26] ;
+ wire \u_riscv_top.core2_dmem_rdata[27] ;
+ wire \u_riscv_top.core2_dmem_rdata[28] ;
+ wire \u_riscv_top.core2_dmem_rdata[29] ;
+ wire \u_riscv_top.core2_dmem_rdata[2] ;
+ wire \u_riscv_top.core2_dmem_rdata[30] ;
+ wire \u_riscv_top.core2_dmem_rdata[31] ;
+ wire \u_riscv_top.core2_dmem_rdata[3] ;
+ wire \u_riscv_top.core2_dmem_rdata[4] ;
+ wire \u_riscv_top.core2_dmem_rdata[5] ;
+ wire \u_riscv_top.core2_dmem_rdata[6] ;
+ wire \u_riscv_top.core2_dmem_rdata[7] ;
+ wire \u_riscv_top.core2_dmem_rdata[8] ;
+ wire \u_riscv_top.core2_dmem_rdata[9] ;
+ wire \u_riscv_top.core2_dmem_req ;
+ wire \u_riscv_top.core2_dmem_req_ack ;
+ wire \u_riscv_top.core2_dmem_resp[0] ;
+ wire \u_riscv_top.core2_dmem_resp[1] ;
+ wire \u_riscv_top.core2_dmem_wdata[0] ;
+ wire \u_riscv_top.core2_dmem_wdata[10] ;
+ wire \u_riscv_top.core2_dmem_wdata[11] ;
+ wire \u_riscv_top.core2_dmem_wdata[12] ;
+ wire \u_riscv_top.core2_dmem_wdata[13] ;
+ wire \u_riscv_top.core2_dmem_wdata[14] ;
+ wire \u_riscv_top.core2_dmem_wdata[15] ;
+ wire \u_riscv_top.core2_dmem_wdata[16] ;
+ wire \u_riscv_top.core2_dmem_wdata[17] ;
+ wire \u_riscv_top.core2_dmem_wdata[18] ;
+ wire \u_riscv_top.core2_dmem_wdata[19] ;
+ wire \u_riscv_top.core2_dmem_wdata[1] ;
+ wire \u_riscv_top.core2_dmem_wdata[20] ;
+ wire \u_riscv_top.core2_dmem_wdata[21] ;
+ wire \u_riscv_top.core2_dmem_wdata[22] ;
+ wire \u_riscv_top.core2_dmem_wdata[23] ;
+ wire \u_riscv_top.core2_dmem_wdata[24] ;
+ wire \u_riscv_top.core2_dmem_wdata[25] ;
+ wire \u_riscv_top.core2_dmem_wdata[26] ;
+ wire \u_riscv_top.core2_dmem_wdata[27] ;
+ wire \u_riscv_top.core2_dmem_wdata[28] ;
+ wire \u_riscv_top.core2_dmem_wdata[29] ;
+ wire \u_riscv_top.core2_dmem_wdata[2] ;
+ wire \u_riscv_top.core2_dmem_wdata[30] ;
+ wire \u_riscv_top.core2_dmem_wdata[31] ;
+ wire \u_riscv_top.core2_dmem_wdata[3] ;
+ wire \u_riscv_top.core2_dmem_wdata[4] ;
+ wire \u_riscv_top.core2_dmem_wdata[5] ;
+ wire \u_riscv_top.core2_dmem_wdata[6] ;
+ wire \u_riscv_top.core2_dmem_wdata[7] ;
+ wire \u_riscv_top.core2_dmem_wdata[8] ;
+ wire \u_riscv_top.core2_dmem_wdata[9] ;
+ wire \u_riscv_top.core2_dmem_width[0] ;
+ wire \u_riscv_top.core2_dmem_width[1] ;
+ wire \u_riscv_top.core2_imem_addr[0] ;
+ wire \u_riscv_top.core2_imem_addr[10] ;
+ wire \u_riscv_top.core2_imem_addr[11] ;
+ wire \u_riscv_top.core2_imem_addr[12] ;
+ wire \u_riscv_top.core2_imem_addr[13] ;
+ wire \u_riscv_top.core2_imem_addr[14] ;
+ wire \u_riscv_top.core2_imem_addr[15] ;
+ wire \u_riscv_top.core2_imem_addr[16] ;
+ wire \u_riscv_top.core2_imem_addr[17] ;
+ wire \u_riscv_top.core2_imem_addr[18] ;
+ wire \u_riscv_top.core2_imem_addr[19] ;
+ wire \u_riscv_top.core2_imem_addr[1] ;
+ wire \u_riscv_top.core2_imem_addr[20] ;
+ wire \u_riscv_top.core2_imem_addr[21] ;
+ wire \u_riscv_top.core2_imem_addr[22] ;
+ wire \u_riscv_top.core2_imem_addr[23] ;
+ wire \u_riscv_top.core2_imem_addr[24] ;
+ wire \u_riscv_top.core2_imem_addr[25] ;
+ wire \u_riscv_top.core2_imem_addr[26] ;
+ wire \u_riscv_top.core2_imem_addr[27] ;
+ wire \u_riscv_top.core2_imem_addr[28] ;
+ wire \u_riscv_top.core2_imem_addr[29] ;
+ wire \u_riscv_top.core2_imem_addr[2] ;
+ wire \u_riscv_top.core2_imem_addr[30] ;
+ wire \u_riscv_top.core2_imem_addr[31] ;
+ wire \u_riscv_top.core2_imem_addr[3] ;
+ wire \u_riscv_top.core2_imem_addr[4] ;
+ wire \u_riscv_top.core2_imem_addr[5] ;
+ wire \u_riscv_top.core2_imem_addr[6] ;
+ wire \u_riscv_top.core2_imem_addr[7] ;
+ wire \u_riscv_top.core2_imem_addr[8] ;
+ wire \u_riscv_top.core2_imem_addr[9] ;
+ wire \u_riscv_top.core2_imem_bl[0] ;
+ wire \u_riscv_top.core2_imem_bl[1] ;
+ wire \u_riscv_top.core2_imem_bl[2] ;
+ wire \u_riscv_top.core2_imem_cmd ;
+ wire \u_riscv_top.core2_imem_rdata[0] ;
+ wire \u_riscv_top.core2_imem_rdata[10] ;
+ wire \u_riscv_top.core2_imem_rdata[11] ;
+ wire \u_riscv_top.core2_imem_rdata[12] ;
+ wire \u_riscv_top.core2_imem_rdata[13] ;
+ wire \u_riscv_top.core2_imem_rdata[14] ;
+ wire \u_riscv_top.core2_imem_rdata[15] ;
+ wire \u_riscv_top.core2_imem_rdata[16] ;
+ wire \u_riscv_top.core2_imem_rdata[17] ;
+ wire \u_riscv_top.core2_imem_rdata[18] ;
+ wire \u_riscv_top.core2_imem_rdata[19] ;
+ wire \u_riscv_top.core2_imem_rdata[1] ;
+ wire \u_riscv_top.core2_imem_rdata[20] ;
+ wire \u_riscv_top.core2_imem_rdata[21] ;
+ wire \u_riscv_top.core2_imem_rdata[22] ;
+ wire \u_riscv_top.core2_imem_rdata[23] ;
+ wire \u_riscv_top.core2_imem_rdata[24] ;
+ wire \u_riscv_top.core2_imem_rdata[25] ;
+ wire \u_riscv_top.core2_imem_rdata[26] ;
+ wire \u_riscv_top.core2_imem_rdata[27] ;
+ wire \u_riscv_top.core2_imem_rdata[28] ;
+ wire \u_riscv_top.core2_imem_rdata[29] ;
+ wire \u_riscv_top.core2_imem_rdata[2] ;
+ wire \u_riscv_top.core2_imem_rdata[30] ;
+ wire \u_riscv_top.core2_imem_rdata[31] ;
+ wire \u_riscv_top.core2_imem_rdata[3] ;
+ wire \u_riscv_top.core2_imem_rdata[4] ;
+ wire \u_riscv_top.core2_imem_rdata[5] ;
+ wire \u_riscv_top.core2_imem_rdata[6] ;
+ wire \u_riscv_top.core2_imem_rdata[7] ;
+ wire \u_riscv_top.core2_imem_rdata[8] ;
+ wire \u_riscv_top.core2_imem_rdata[9] ;
+ wire \u_riscv_top.core2_imem_req ;
+ wire \u_riscv_top.core2_imem_req_ack ;
+ wire \u_riscv_top.core2_imem_resp[0] ;
+ wire \u_riscv_top.core2_imem_resp[1] ;
+ wire \u_riscv_top.core2_irq_lines[0] ;
+ wire \u_riscv_top.core2_irq_lines[10] ;
+ wire \u_riscv_top.core2_irq_lines[11] ;
+ wire \u_riscv_top.core2_irq_lines[12] ;
+ wire \u_riscv_top.core2_irq_lines[13] ;
+ wire \u_riscv_top.core2_irq_lines[14] ;
+ wire \u_riscv_top.core2_irq_lines[15] ;
+ wire \u_riscv_top.core2_irq_lines[1] ;
+ wire \u_riscv_top.core2_irq_lines[2] ;
+ wire \u_riscv_top.core2_irq_lines[3] ;
+ wire \u_riscv_top.core2_irq_lines[4] ;
+ wire \u_riscv_top.core2_irq_lines[5] ;
+ wire \u_riscv_top.core2_irq_lines[6] ;
+ wire \u_riscv_top.core2_irq_lines[7] ;
+ wire \u_riscv_top.core2_irq_lines[8] ;
+ wire \u_riscv_top.core2_irq_lines[9] ;
+ wire \u_riscv_top.core2_soft_irq ;
+ wire \u_riscv_top.core2_timer_irq ;
+ wire \u_riscv_top.core2_timer_val[0] ;
+ wire \u_riscv_top.core2_timer_val[10] ;
+ wire \u_riscv_top.core2_timer_val[11] ;
+ wire \u_riscv_top.core2_timer_val[12] ;
+ wire \u_riscv_top.core2_timer_val[13] ;
+ wire \u_riscv_top.core2_timer_val[14] ;
+ wire \u_riscv_top.core2_timer_val[15] ;
+ wire \u_riscv_top.core2_timer_val[16] ;
+ wire \u_riscv_top.core2_timer_val[17] ;
+ wire \u_riscv_top.core2_timer_val[18] ;
+ wire \u_riscv_top.core2_timer_val[19] ;
+ wire \u_riscv_top.core2_timer_val[1] ;
+ wire \u_riscv_top.core2_timer_val[20] ;
+ wire \u_riscv_top.core2_timer_val[21] ;
+ wire \u_riscv_top.core2_timer_val[22] ;
+ wire \u_riscv_top.core2_timer_val[23] ;
+ wire \u_riscv_top.core2_timer_val[24] ;
+ wire \u_riscv_top.core2_timer_val[25] ;
+ wire \u_riscv_top.core2_timer_val[26] ;
+ wire \u_riscv_top.core2_timer_val[27] ;
+ wire \u_riscv_top.core2_timer_val[28] ;
+ wire \u_riscv_top.core2_timer_val[29] ;
+ wire \u_riscv_top.core2_timer_val[2] ;
+ wire \u_riscv_top.core2_timer_val[30] ;
+ wire \u_riscv_top.core2_timer_val[31] ;
+ wire \u_riscv_top.core2_timer_val[32] ;
+ wire \u_riscv_top.core2_timer_val[33] ;
+ wire \u_riscv_top.core2_timer_val[34] ;
+ wire \u_riscv_top.core2_timer_val[35] ;
+ wire \u_riscv_top.core2_timer_val[36] ;
+ wire \u_riscv_top.core2_timer_val[37] ;
+ wire \u_riscv_top.core2_timer_val[38] ;
+ wire \u_riscv_top.core2_timer_val[39] ;
+ wire \u_riscv_top.core2_timer_val[3] ;
+ wire \u_riscv_top.core2_timer_val[40] ;
+ wire \u_riscv_top.core2_timer_val[41] ;
+ wire \u_riscv_top.core2_timer_val[42] ;
+ wire \u_riscv_top.core2_timer_val[43] ;
+ wire \u_riscv_top.core2_timer_val[44] ;
+ wire \u_riscv_top.core2_timer_val[45] ;
+ wire \u_riscv_top.core2_timer_val[46] ;
+ wire \u_riscv_top.core2_timer_val[47] ;
+ wire \u_riscv_top.core2_timer_val[48] ;
+ wire \u_riscv_top.core2_timer_val[49] ;
+ wire \u_riscv_top.core2_timer_val[4] ;
+ wire \u_riscv_top.core2_timer_val[50] ;
+ wire \u_riscv_top.core2_timer_val[51] ;
+ wire \u_riscv_top.core2_timer_val[52] ;
+ wire \u_riscv_top.core2_timer_val[53] ;
+ wire \u_riscv_top.core2_timer_val[54] ;
+ wire \u_riscv_top.core2_timer_val[55] ;
+ wire \u_riscv_top.core2_timer_val[56] ;
+ wire \u_riscv_top.core2_timer_val[57] ;
+ wire \u_riscv_top.core2_timer_val[58] ;
+ wire \u_riscv_top.core2_timer_val[59] ;
+ wire \u_riscv_top.core2_timer_val[5] ;
+ wire \u_riscv_top.core2_timer_val[60] ;
+ wire \u_riscv_top.core2_timer_val[61] ;
+ wire \u_riscv_top.core2_timer_val[62] ;
+ wire \u_riscv_top.core2_timer_val[63] ;
+ wire \u_riscv_top.core2_timer_val[6] ;
+ wire \u_riscv_top.core2_timer_val[7] ;
+ wire \u_riscv_top.core2_timer_val[8] ;
+ wire \u_riscv_top.core2_timer_val[9] ;
+ wire \u_riscv_top.core2_uid[0] ;
+ wire \u_riscv_top.core2_uid[1] ;
+ wire \u_riscv_top.core3_debug[0] ;
+ wire \u_riscv_top.core3_debug[10] ;
+ wire \u_riscv_top.core3_debug[11] ;
+ wire \u_riscv_top.core3_debug[12] ;
+ wire \u_riscv_top.core3_debug[13] ;
+ wire \u_riscv_top.core3_debug[14] ;
+ wire \u_riscv_top.core3_debug[15] ;
+ wire \u_riscv_top.core3_debug[16] ;
+ wire \u_riscv_top.core3_debug[17] ;
+ wire \u_riscv_top.core3_debug[18] ;
+ wire \u_riscv_top.core3_debug[19] ;
+ wire \u_riscv_top.core3_debug[1] ;
+ wire \u_riscv_top.core3_debug[20] ;
+ wire \u_riscv_top.core3_debug[21] ;
+ wire \u_riscv_top.core3_debug[22] ;
+ wire \u_riscv_top.core3_debug[23] ;
+ wire \u_riscv_top.core3_debug[24] ;
+ wire \u_riscv_top.core3_debug[25] ;
+ wire \u_riscv_top.core3_debug[26] ;
+ wire \u_riscv_top.core3_debug[27] ;
+ wire \u_riscv_top.core3_debug[28] ;
+ wire \u_riscv_top.core3_debug[29] ;
+ wire \u_riscv_top.core3_debug[2] ;
+ wire \u_riscv_top.core3_debug[30] ;
+ wire \u_riscv_top.core3_debug[31] ;
+ wire \u_riscv_top.core3_debug[32] ;
+ wire \u_riscv_top.core3_debug[33] ;
+ wire \u_riscv_top.core3_debug[34] ;
+ wire \u_riscv_top.core3_debug[35] ;
+ wire \u_riscv_top.core3_debug[36] ;
+ wire \u_riscv_top.core3_debug[37] ;
+ wire \u_riscv_top.core3_debug[38] ;
+ wire \u_riscv_top.core3_debug[39] ;
+ wire \u_riscv_top.core3_debug[3] ;
+ wire \u_riscv_top.core3_debug[40] ;
+ wire \u_riscv_top.core3_debug[41] ;
+ wire \u_riscv_top.core3_debug[42] ;
+ wire \u_riscv_top.core3_debug[43] ;
+ wire \u_riscv_top.core3_debug[44] ;
+ wire \u_riscv_top.core3_debug[45] ;
+ wire \u_riscv_top.core3_debug[46] ;
+ wire \u_riscv_top.core3_debug[47] ;
+ wire \u_riscv_top.core3_debug[48] ;
+ wire \u_riscv_top.core3_debug[4] ;
+ wire \u_riscv_top.core3_debug[5] ;
+ wire \u_riscv_top.core3_debug[6] ;
+ wire \u_riscv_top.core3_debug[7] ;
+ wire \u_riscv_top.core3_debug[8] ;
+ wire \u_riscv_top.core3_debug[9] ;
+ wire \u_riscv_top.core3_dmem_addr[0] ;
+ wire \u_riscv_top.core3_dmem_addr[10] ;
+ wire \u_riscv_top.core3_dmem_addr[11] ;
+ wire \u_riscv_top.core3_dmem_addr[12] ;
+ wire \u_riscv_top.core3_dmem_addr[13] ;
+ wire \u_riscv_top.core3_dmem_addr[14] ;
+ wire \u_riscv_top.core3_dmem_addr[15] ;
+ wire \u_riscv_top.core3_dmem_addr[16] ;
+ wire \u_riscv_top.core3_dmem_addr[17] ;
+ wire \u_riscv_top.core3_dmem_addr[18] ;
+ wire \u_riscv_top.core3_dmem_addr[19] ;
+ wire \u_riscv_top.core3_dmem_addr[1] ;
+ wire \u_riscv_top.core3_dmem_addr[20] ;
+ wire \u_riscv_top.core3_dmem_addr[21] ;
+ wire \u_riscv_top.core3_dmem_addr[22] ;
+ wire \u_riscv_top.core3_dmem_addr[23] ;
+ wire \u_riscv_top.core3_dmem_addr[24] ;
+ wire \u_riscv_top.core3_dmem_addr[25] ;
+ wire \u_riscv_top.core3_dmem_addr[26] ;
+ wire \u_riscv_top.core3_dmem_addr[27] ;
+ wire \u_riscv_top.core3_dmem_addr[28] ;
+ wire \u_riscv_top.core3_dmem_addr[29] ;
+ wire \u_riscv_top.core3_dmem_addr[2] ;
+ wire \u_riscv_top.core3_dmem_addr[30] ;
+ wire \u_riscv_top.core3_dmem_addr[31] ;
+ wire \u_riscv_top.core3_dmem_addr[3] ;
+ wire \u_riscv_top.core3_dmem_addr[4] ;
+ wire \u_riscv_top.core3_dmem_addr[5] ;
+ wire \u_riscv_top.core3_dmem_addr[6] ;
+ wire \u_riscv_top.core3_dmem_addr[7] ;
+ wire \u_riscv_top.core3_dmem_addr[8] ;
+ wire \u_riscv_top.core3_dmem_addr[9] ;
+ wire \u_riscv_top.core3_dmem_cmd ;
+ wire \u_riscv_top.core3_dmem_rdata[0] ;
+ wire \u_riscv_top.core3_dmem_rdata[10] ;
+ wire \u_riscv_top.core3_dmem_rdata[11] ;
+ wire \u_riscv_top.core3_dmem_rdata[12] ;
+ wire \u_riscv_top.core3_dmem_rdata[13] ;
+ wire \u_riscv_top.core3_dmem_rdata[14] ;
+ wire \u_riscv_top.core3_dmem_rdata[15] ;
+ wire \u_riscv_top.core3_dmem_rdata[16] ;
+ wire \u_riscv_top.core3_dmem_rdata[17] ;
+ wire \u_riscv_top.core3_dmem_rdata[18] ;
+ wire \u_riscv_top.core3_dmem_rdata[19] ;
+ wire \u_riscv_top.core3_dmem_rdata[1] ;
+ wire \u_riscv_top.core3_dmem_rdata[20] ;
+ wire \u_riscv_top.core3_dmem_rdata[21] ;
+ wire \u_riscv_top.core3_dmem_rdata[22] ;
+ wire \u_riscv_top.core3_dmem_rdata[23] ;
+ wire \u_riscv_top.core3_dmem_rdata[24] ;
+ wire \u_riscv_top.core3_dmem_rdata[25] ;
+ wire \u_riscv_top.core3_dmem_rdata[26] ;
+ wire \u_riscv_top.core3_dmem_rdata[27] ;
+ wire \u_riscv_top.core3_dmem_rdata[28] ;
+ wire \u_riscv_top.core3_dmem_rdata[29] ;
+ wire \u_riscv_top.core3_dmem_rdata[2] ;
+ wire \u_riscv_top.core3_dmem_rdata[30] ;
+ wire \u_riscv_top.core3_dmem_rdata[31] ;
+ wire \u_riscv_top.core3_dmem_rdata[3] ;
+ wire \u_riscv_top.core3_dmem_rdata[4] ;
+ wire \u_riscv_top.core3_dmem_rdata[5] ;
+ wire \u_riscv_top.core3_dmem_rdata[6] ;
+ wire \u_riscv_top.core3_dmem_rdata[7] ;
+ wire \u_riscv_top.core3_dmem_rdata[8] ;
+ wire \u_riscv_top.core3_dmem_rdata[9] ;
+ wire \u_riscv_top.core3_dmem_req ;
+ wire \u_riscv_top.core3_dmem_req_ack ;
+ wire \u_riscv_top.core3_dmem_resp[0] ;
+ wire \u_riscv_top.core3_dmem_resp[1] ;
+ wire \u_riscv_top.core3_dmem_wdata[0] ;
+ wire \u_riscv_top.core3_dmem_wdata[10] ;
+ wire \u_riscv_top.core3_dmem_wdata[11] ;
+ wire \u_riscv_top.core3_dmem_wdata[12] ;
+ wire \u_riscv_top.core3_dmem_wdata[13] ;
+ wire \u_riscv_top.core3_dmem_wdata[14] ;
+ wire \u_riscv_top.core3_dmem_wdata[15] ;
+ wire \u_riscv_top.core3_dmem_wdata[16] ;
+ wire \u_riscv_top.core3_dmem_wdata[17] ;
+ wire \u_riscv_top.core3_dmem_wdata[18] ;
+ wire \u_riscv_top.core3_dmem_wdata[19] ;
+ wire \u_riscv_top.core3_dmem_wdata[1] ;
+ wire \u_riscv_top.core3_dmem_wdata[20] ;
+ wire \u_riscv_top.core3_dmem_wdata[21] ;
+ wire \u_riscv_top.core3_dmem_wdata[22] ;
+ wire \u_riscv_top.core3_dmem_wdata[23] ;
+ wire \u_riscv_top.core3_dmem_wdata[24] ;
+ wire \u_riscv_top.core3_dmem_wdata[25] ;
+ wire \u_riscv_top.core3_dmem_wdata[26] ;
+ wire \u_riscv_top.core3_dmem_wdata[27] ;
+ wire \u_riscv_top.core3_dmem_wdata[28] ;
+ wire \u_riscv_top.core3_dmem_wdata[29] ;
+ wire \u_riscv_top.core3_dmem_wdata[2] ;
+ wire \u_riscv_top.core3_dmem_wdata[30] ;
+ wire \u_riscv_top.core3_dmem_wdata[31] ;
+ wire \u_riscv_top.core3_dmem_wdata[3] ;
+ wire \u_riscv_top.core3_dmem_wdata[4] ;
+ wire \u_riscv_top.core3_dmem_wdata[5] ;
+ wire \u_riscv_top.core3_dmem_wdata[6] ;
+ wire \u_riscv_top.core3_dmem_wdata[7] ;
+ wire \u_riscv_top.core3_dmem_wdata[8] ;
+ wire \u_riscv_top.core3_dmem_wdata[9] ;
+ wire \u_riscv_top.core3_dmem_width[0] ;
+ wire \u_riscv_top.core3_dmem_width[1] ;
+ wire \u_riscv_top.core3_imem_addr[0] ;
+ wire \u_riscv_top.core3_imem_addr[10] ;
+ wire \u_riscv_top.core3_imem_addr[11] ;
+ wire \u_riscv_top.core3_imem_addr[12] ;
+ wire \u_riscv_top.core3_imem_addr[13] ;
+ wire \u_riscv_top.core3_imem_addr[14] ;
+ wire \u_riscv_top.core3_imem_addr[15] ;
+ wire \u_riscv_top.core3_imem_addr[16] ;
+ wire \u_riscv_top.core3_imem_addr[17] ;
+ wire \u_riscv_top.core3_imem_addr[18] ;
+ wire \u_riscv_top.core3_imem_addr[19] ;
+ wire \u_riscv_top.core3_imem_addr[1] ;
+ wire \u_riscv_top.core3_imem_addr[20] ;
+ wire \u_riscv_top.core3_imem_addr[21] ;
+ wire \u_riscv_top.core3_imem_addr[22] ;
+ wire \u_riscv_top.core3_imem_addr[23] ;
+ wire \u_riscv_top.core3_imem_addr[24] ;
+ wire \u_riscv_top.core3_imem_addr[25] ;
+ wire \u_riscv_top.core3_imem_addr[26] ;
+ wire \u_riscv_top.core3_imem_addr[27] ;
+ wire \u_riscv_top.core3_imem_addr[28] ;
+ wire \u_riscv_top.core3_imem_addr[29] ;
+ wire \u_riscv_top.core3_imem_addr[2] ;
+ wire \u_riscv_top.core3_imem_addr[30] ;
+ wire \u_riscv_top.core3_imem_addr[31] ;
+ wire \u_riscv_top.core3_imem_addr[3] ;
+ wire \u_riscv_top.core3_imem_addr[4] ;
+ wire \u_riscv_top.core3_imem_addr[5] ;
+ wire \u_riscv_top.core3_imem_addr[6] ;
+ wire \u_riscv_top.core3_imem_addr[7] ;
+ wire \u_riscv_top.core3_imem_addr[8] ;
+ wire \u_riscv_top.core3_imem_addr[9] ;
+ wire \u_riscv_top.core3_imem_bl[0] ;
+ wire \u_riscv_top.core3_imem_bl[1] ;
+ wire \u_riscv_top.core3_imem_bl[2] ;
+ wire \u_riscv_top.core3_imem_cmd ;
+ wire \u_riscv_top.core3_imem_rdata[0] ;
+ wire \u_riscv_top.core3_imem_rdata[10] ;
+ wire \u_riscv_top.core3_imem_rdata[11] ;
+ wire \u_riscv_top.core3_imem_rdata[12] ;
+ wire \u_riscv_top.core3_imem_rdata[13] ;
+ wire \u_riscv_top.core3_imem_rdata[14] ;
+ wire \u_riscv_top.core3_imem_rdata[15] ;
+ wire \u_riscv_top.core3_imem_rdata[16] ;
+ wire \u_riscv_top.core3_imem_rdata[17] ;
+ wire \u_riscv_top.core3_imem_rdata[18] ;
+ wire \u_riscv_top.core3_imem_rdata[19] ;
+ wire \u_riscv_top.core3_imem_rdata[1] ;
+ wire \u_riscv_top.core3_imem_rdata[20] ;
+ wire \u_riscv_top.core3_imem_rdata[21] ;
+ wire \u_riscv_top.core3_imem_rdata[22] ;
+ wire \u_riscv_top.core3_imem_rdata[23] ;
+ wire \u_riscv_top.core3_imem_rdata[24] ;
+ wire \u_riscv_top.core3_imem_rdata[25] ;
+ wire \u_riscv_top.core3_imem_rdata[26] ;
+ wire \u_riscv_top.core3_imem_rdata[27] ;
+ wire \u_riscv_top.core3_imem_rdata[28] ;
+ wire \u_riscv_top.core3_imem_rdata[29] ;
+ wire \u_riscv_top.core3_imem_rdata[2] ;
+ wire \u_riscv_top.core3_imem_rdata[30] ;
+ wire \u_riscv_top.core3_imem_rdata[31] ;
+ wire \u_riscv_top.core3_imem_rdata[3] ;
+ wire \u_riscv_top.core3_imem_rdata[4] ;
+ wire \u_riscv_top.core3_imem_rdata[5] ;
+ wire \u_riscv_top.core3_imem_rdata[6] ;
+ wire \u_riscv_top.core3_imem_rdata[7] ;
+ wire \u_riscv_top.core3_imem_rdata[8] ;
+ wire \u_riscv_top.core3_imem_rdata[9] ;
+ wire \u_riscv_top.core3_imem_req ;
+ wire \u_riscv_top.core3_imem_req_ack ;
+ wire \u_riscv_top.core3_imem_resp[0] ;
+ wire \u_riscv_top.core3_imem_resp[1] ;
+ wire \u_riscv_top.core3_irq_lines[0] ;
+ wire \u_riscv_top.core3_irq_lines[10] ;
+ wire \u_riscv_top.core3_irq_lines[11] ;
+ wire \u_riscv_top.core3_irq_lines[12] ;
+ wire \u_riscv_top.core3_irq_lines[13] ;
+ wire \u_riscv_top.core3_irq_lines[14] ;
+ wire \u_riscv_top.core3_irq_lines[15] ;
+ wire \u_riscv_top.core3_irq_lines[1] ;
+ wire \u_riscv_top.core3_irq_lines[2] ;
+ wire \u_riscv_top.core3_irq_lines[3] ;
+ wire \u_riscv_top.core3_irq_lines[4] ;
+ wire \u_riscv_top.core3_irq_lines[5] ;
+ wire \u_riscv_top.core3_irq_lines[6] ;
+ wire \u_riscv_top.core3_irq_lines[7] ;
+ wire \u_riscv_top.core3_irq_lines[8] ;
+ wire \u_riscv_top.core3_irq_lines[9] ;
+ wire \u_riscv_top.core3_soft_irq ;
+ wire \u_riscv_top.core3_timer_irq ;
+ wire \u_riscv_top.core3_timer_val[0] ;
+ wire \u_riscv_top.core3_timer_val[10] ;
+ wire \u_riscv_top.core3_timer_val[11] ;
+ wire \u_riscv_top.core3_timer_val[12] ;
+ wire \u_riscv_top.core3_timer_val[13] ;
+ wire \u_riscv_top.core3_timer_val[14] ;
+ wire \u_riscv_top.core3_timer_val[15] ;
+ wire \u_riscv_top.core3_timer_val[16] ;
+ wire \u_riscv_top.core3_timer_val[17] ;
+ wire \u_riscv_top.core3_timer_val[18] ;
+ wire \u_riscv_top.core3_timer_val[19] ;
+ wire \u_riscv_top.core3_timer_val[1] ;
+ wire \u_riscv_top.core3_timer_val[20] ;
+ wire \u_riscv_top.core3_timer_val[21] ;
+ wire \u_riscv_top.core3_timer_val[22] ;
+ wire \u_riscv_top.core3_timer_val[23] ;
+ wire \u_riscv_top.core3_timer_val[24] ;
+ wire \u_riscv_top.core3_timer_val[25] ;
+ wire \u_riscv_top.core3_timer_val[26] ;
+ wire \u_riscv_top.core3_timer_val[27] ;
+ wire \u_riscv_top.core3_timer_val[28] ;
+ wire \u_riscv_top.core3_timer_val[29] ;
+ wire \u_riscv_top.core3_timer_val[2] ;
+ wire \u_riscv_top.core3_timer_val[30] ;
+ wire \u_riscv_top.core3_timer_val[31] ;
+ wire \u_riscv_top.core3_timer_val[32] ;
+ wire \u_riscv_top.core3_timer_val[33] ;
+ wire \u_riscv_top.core3_timer_val[34] ;
+ wire \u_riscv_top.core3_timer_val[35] ;
+ wire \u_riscv_top.core3_timer_val[36] ;
+ wire \u_riscv_top.core3_timer_val[37] ;
+ wire \u_riscv_top.core3_timer_val[38] ;
+ wire \u_riscv_top.core3_timer_val[39] ;
+ wire \u_riscv_top.core3_timer_val[3] ;
+ wire \u_riscv_top.core3_timer_val[40] ;
+ wire \u_riscv_top.core3_timer_val[41] ;
+ wire \u_riscv_top.core3_timer_val[42] ;
+ wire \u_riscv_top.core3_timer_val[43] ;
+ wire \u_riscv_top.core3_timer_val[44] ;
+ wire \u_riscv_top.core3_timer_val[45] ;
+ wire \u_riscv_top.core3_timer_val[46] ;
+ wire \u_riscv_top.core3_timer_val[47] ;
+ wire \u_riscv_top.core3_timer_val[48] ;
+ wire \u_riscv_top.core3_timer_val[49] ;
+ wire \u_riscv_top.core3_timer_val[4] ;
+ wire \u_riscv_top.core3_timer_val[50] ;
+ wire \u_riscv_top.core3_timer_val[51] ;
+ wire \u_riscv_top.core3_timer_val[52] ;
+ wire \u_riscv_top.core3_timer_val[53] ;
+ wire \u_riscv_top.core3_timer_val[54] ;
+ wire \u_riscv_top.core3_timer_val[55] ;
+ wire \u_riscv_top.core3_timer_val[56] ;
+ wire \u_riscv_top.core3_timer_val[57] ;
+ wire \u_riscv_top.core3_timer_val[58] ;
+ wire \u_riscv_top.core3_timer_val[59] ;
+ wire \u_riscv_top.core3_timer_val[5] ;
+ wire \u_riscv_top.core3_timer_val[60] ;
+ wire \u_riscv_top.core3_timer_val[61] ;
+ wire \u_riscv_top.core3_timer_val[62] ;
+ wire \u_riscv_top.core3_timer_val[63] ;
+ wire \u_riscv_top.core3_timer_val[6] ;
+ wire \u_riscv_top.core3_timer_val[7] ;
+ wire \u_riscv_top.core3_timer_val[8] ;
+ wire \u_riscv_top.core3_timer_val[9] ;
+ wire \u_riscv_top.core3_uid[0] ;
+ wire \u_riscv_top.core3_uid[1] ;
+ wire \u_riscv_top.core_clk ;
+ wire \u_riscv_top.core_clk_out[0] ;
+ wire \u_riscv_top.core_clk_out[1] ;
+ wire \u_riscv_top.core_clk_out[2] ;
+ wire \u_riscv_top.core_clk_out[3] ;
+ wire \u_riscv_top.core_dcache_addr[0] ;
+ wire \u_riscv_top.core_dcache_addr[10] ;
+ wire \u_riscv_top.core_dcache_addr[11] ;
+ wire \u_riscv_top.core_dcache_addr[12] ;
+ wire \u_riscv_top.core_dcache_addr[13] ;
+ wire \u_riscv_top.core_dcache_addr[14] ;
+ wire \u_riscv_top.core_dcache_addr[15] ;
+ wire \u_riscv_top.core_dcache_addr[16] ;
+ wire \u_riscv_top.core_dcache_addr[17] ;
+ wire \u_riscv_top.core_dcache_addr[18] ;
+ wire \u_riscv_top.core_dcache_addr[19] ;
+ wire \u_riscv_top.core_dcache_addr[1] ;
+ wire \u_riscv_top.core_dcache_addr[20] ;
+ wire \u_riscv_top.core_dcache_addr[21] ;
+ wire \u_riscv_top.core_dcache_addr[22] ;
+ wire \u_riscv_top.core_dcache_addr[23] ;
+ wire \u_riscv_top.core_dcache_addr[24] ;
+ wire \u_riscv_top.core_dcache_addr[25] ;
+ wire \u_riscv_top.core_dcache_addr[26] ;
+ wire \u_riscv_top.core_dcache_addr[27] ;
+ wire \u_riscv_top.core_dcache_addr[28] ;
+ wire \u_riscv_top.core_dcache_addr[29] ;
+ wire \u_riscv_top.core_dcache_addr[2] ;
+ wire \u_riscv_top.core_dcache_addr[30] ;
+ wire \u_riscv_top.core_dcache_addr[31] ;
+ wire \u_riscv_top.core_dcache_addr[3] ;
+ wire \u_riscv_top.core_dcache_addr[4] ;
+ wire \u_riscv_top.core_dcache_addr[5] ;
+ wire \u_riscv_top.core_dcache_addr[6] ;
+ wire \u_riscv_top.core_dcache_addr[7] ;
+ wire \u_riscv_top.core_dcache_addr[8] ;
+ wire \u_riscv_top.core_dcache_addr[9] ;
+ wire \u_riscv_top.core_dcache_cmd ;
+ wire \u_riscv_top.core_dcache_rdata[0] ;
+ wire \u_riscv_top.core_dcache_rdata[10] ;
+ wire \u_riscv_top.core_dcache_rdata[11] ;
+ wire \u_riscv_top.core_dcache_rdata[12] ;
+ wire \u_riscv_top.core_dcache_rdata[13] ;
+ wire \u_riscv_top.core_dcache_rdata[14] ;
+ wire \u_riscv_top.core_dcache_rdata[15] ;
+ wire \u_riscv_top.core_dcache_rdata[16] ;
+ wire \u_riscv_top.core_dcache_rdata[17] ;
+ wire \u_riscv_top.core_dcache_rdata[18] ;
+ wire \u_riscv_top.core_dcache_rdata[19] ;
+ wire \u_riscv_top.core_dcache_rdata[1] ;
+ wire \u_riscv_top.core_dcache_rdata[20] ;
+ wire \u_riscv_top.core_dcache_rdata[21] ;
+ wire \u_riscv_top.core_dcache_rdata[22] ;
+ wire \u_riscv_top.core_dcache_rdata[23] ;
+ wire \u_riscv_top.core_dcache_rdata[24] ;
+ wire \u_riscv_top.core_dcache_rdata[25] ;
+ wire \u_riscv_top.core_dcache_rdata[26] ;
+ wire \u_riscv_top.core_dcache_rdata[27] ;
+ wire \u_riscv_top.core_dcache_rdata[28] ;
+ wire \u_riscv_top.core_dcache_rdata[29] ;
+ wire \u_riscv_top.core_dcache_rdata[2] ;
+ wire \u_riscv_top.core_dcache_rdata[30] ;
+ wire \u_riscv_top.core_dcache_rdata[31] ;
+ wire \u_riscv_top.core_dcache_rdata[3] ;
+ wire \u_riscv_top.core_dcache_rdata[4] ;
+ wire \u_riscv_top.core_dcache_rdata[5] ;
+ wire \u_riscv_top.core_dcache_rdata[6] ;
+ wire \u_riscv_top.core_dcache_rdata[7] ;
+ wire \u_riscv_top.core_dcache_rdata[8] ;
+ wire \u_riscv_top.core_dcache_rdata[9] ;
+ wire \u_riscv_top.core_dcache_req ;
+ wire \u_riscv_top.core_dcache_req_ack ;
+ wire \u_riscv_top.core_dcache_resp[0] ;
+ wire \u_riscv_top.core_dcache_resp[1] ;
+ wire \u_riscv_top.core_dcache_wdata[0] ;
+ wire \u_riscv_top.core_dcache_wdata[10] ;
+ wire \u_riscv_top.core_dcache_wdata[11] ;
+ wire \u_riscv_top.core_dcache_wdata[12] ;
+ wire \u_riscv_top.core_dcache_wdata[13] ;
+ wire \u_riscv_top.core_dcache_wdata[14] ;
+ wire \u_riscv_top.core_dcache_wdata[15] ;
+ wire \u_riscv_top.core_dcache_wdata[16] ;
+ wire \u_riscv_top.core_dcache_wdata[17] ;
+ wire \u_riscv_top.core_dcache_wdata[18] ;
+ wire \u_riscv_top.core_dcache_wdata[19] ;
+ wire \u_riscv_top.core_dcache_wdata[1] ;
+ wire \u_riscv_top.core_dcache_wdata[20] ;
+ wire \u_riscv_top.core_dcache_wdata[21] ;
+ wire \u_riscv_top.core_dcache_wdata[22] ;
+ wire \u_riscv_top.core_dcache_wdata[23] ;
+ wire \u_riscv_top.core_dcache_wdata[24] ;
+ wire \u_riscv_top.core_dcache_wdata[25] ;
+ wire \u_riscv_top.core_dcache_wdata[26] ;
+ wire \u_riscv_top.core_dcache_wdata[27] ;
+ wire \u_riscv_top.core_dcache_wdata[28] ;
+ wire \u_riscv_top.core_dcache_wdata[29] ;
+ wire \u_riscv_top.core_dcache_wdata[2] ;
+ wire \u_riscv_top.core_dcache_wdata[30] ;
+ wire \u_riscv_top.core_dcache_wdata[31] ;
+ wire \u_riscv_top.core_dcache_wdata[3] ;
+ wire \u_riscv_top.core_dcache_wdata[4] ;
+ wire \u_riscv_top.core_dcache_wdata[5] ;
+ wire \u_riscv_top.core_dcache_wdata[6] ;
+ wire \u_riscv_top.core_dcache_wdata[7] ;
+ wire \u_riscv_top.core_dcache_wdata[8] ;
+ wire \u_riscv_top.core_dcache_wdata[9] ;
+ wire \u_riscv_top.core_dcache_width[0] ;
+ wire \u_riscv_top.core_dcache_width[1] ;
+ wire \u_riscv_top.core_dmem_addr[0] ;
+ wire \u_riscv_top.core_dmem_addr[10] ;
+ wire \u_riscv_top.core_dmem_addr[11] ;
+ wire \u_riscv_top.core_dmem_addr[12] ;
+ wire \u_riscv_top.core_dmem_addr[13] ;
+ wire \u_riscv_top.core_dmem_addr[14] ;
+ wire \u_riscv_top.core_dmem_addr[15] ;
+ wire \u_riscv_top.core_dmem_addr[16] ;
+ wire \u_riscv_top.core_dmem_addr[17] ;
+ wire \u_riscv_top.core_dmem_addr[18] ;
+ wire \u_riscv_top.core_dmem_addr[19] ;
+ wire \u_riscv_top.core_dmem_addr[1] ;
+ wire \u_riscv_top.core_dmem_addr[20] ;
+ wire \u_riscv_top.core_dmem_addr[21] ;
+ wire \u_riscv_top.core_dmem_addr[22] ;
+ wire \u_riscv_top.core_dmem_addr[23] ;
+ wire \u_riscv_top.core_dmem_addr[24] ;
+ wire \u_riscv_top.core_dmem_addr[25] ;
+ wire \u_riscv_top.core_dmem_addr[26] ;
+ wire \u_riscv_top.core_dmem_addr[27] ;
+ wire \u_riscv_top.core_dmem_addr[28] ;
+ wire \u_riscv_top.core_dmem_addr[29] ;
+ wire \u_riscv_top.core_dmem_addr[2] ;
+ wire \u_riscv_top.core_dmem_addr[30] ;
+ wire \u_riscv_top.core_dmem_addr[31] ;
+ wire \u_riscv_top.core_dmem_addr[3] ;
+ wire \u_riscv_top.core_dmem_addr[4] ;
+ wire \u_riscv_top.core_dmem_addr[5] ;
+ wire \u_riscv_top.core_dmem_addr[6] ;
+ wire \u_riscv_top.core_dmem_addr[7] ;
+ wire \u_riscv_top.core_dmem_addr[8] ;
+ wire \u_riscv_top.core_dmem_addr[9] ;
+ wire \u_riscv_top.core_dmem_cmd ;
+ wire \u_riscv_top.core_dmem_rdata[0] ;
+ wire \u_riscv_top.core_dmem_rdata[10] ;
+ wire \u_riscv_top.core_dmem_rdata[11] ;
+ wire \u_riscv_top.core_dmem_rdata[12] ;
+ wire \u_riscv_top.core_dmem_rdata[13] ;
+ wire \u_riscv_top.core_dmem_rdata[14] ;
+ wire \u_riscv_top.core_dmem_rdata[15] ;
+ wire \u_riscv_top.core_dmem_rdata[16] ;
+ wire \u_riscv_top.core_dmem_rdata[17] ;
+ wire \u_riscv_top.core_dmem_rdata[18] ;
+ wire \u_riscv_top.core_dmem_rdata[19] ;
+ wire \u_riscv_top.core_dmem_rdata[1] ;
+ wire \u_riscv_top.core_dmem_rdata[20] ;
+ wire \u_riscv_top.core_dmem_rdata[21] ;
+ wire \u_riscv_top.core_dmem_rdata[22] ;
+ wire \u_riscv_top.core_dmem_rdata[23] ;
+ wire \u_riscv_top.core_dmem_rdata[24] ;
+ wire \u_riscv_top.core_dmem_rdata[25] ;
+ wire \u_riscv_top.core_dmem_rdata[26] ;
+ wire \u_riscv_top.core_dmem_rdata[27] ;
+ wire \u_riscv_top.core_dmem_rdata[28] ;
+ wire \u_riscv_top.core_dmem_rdata[29] ;
+ wire \u_riscv_top.core_dmem_rdata[2] ;
+ wire \u_riscv_top.core_dmem_rdata[30] ;
+ wire \u_riscv_top.core_dmem_rdata[31] ;
+ wire \u_riscv_top.core_dmem_rdata[3] ;
+ wire \u_riscv_top.core_dmem_rdata[4] ;
+ wire \u_riscv_top.core_dmem_rdata[5] ;
+ wire \u_riscv_top.core_dmem_rdata[6] ;
+ wire \u_riscv_top.core_dmem_rdata[7] ;
+ wire \u_riscv_top.core_dmem_rdata[8] ;
+ wire \u_riscv_top.core_dmem_rdata[9] ;
+ wire \u_riscv_top.core_dmem_req ;
+ wire \u_riscv_top.core_dmem_req_ack ;
+ wire \u_riscv_top.core_dmem_resp[0] ;
+ wire \u_riscv_top.core_dmem_resp[1] ;
+ wire \u_riscv_top.core_dmem_wdata[0] ;
+ wire \u_riscv_top.core_dmem_wdata[10] ;
+ wire \u_riscv_top.core_dmem_wdata[11] ;
+ wire \u_riscv_top.core_dmem_wdata[12] ;
+ wire \u_riscv_top.core_dmem_wdata[13] ;
+ wire \u_riscv_top.core_dmem_wdata[14] ;
+ wire \u_riscv_top.core_dmem_wdata[15] ;
+ wire \u_riscv_top.core_dmem_wdata[16] ;
+ wire \u_riscv_top.core_dmem_wdata[17] ;
+ wire \u_riscv_top.core_dmem_wdata[18] ;
+ wire \u_riscv_top.core_dmem_wdata[19] ;
+ wire \u_riscv_top.core_dmem_wdata[1] ;
+ wire \u_riscv_top.core_dmem_wdata[20] ;
+ wire \u_riscv_top.core_dmem_wdata[21] ;
+ wire \u_riscv_top.core_dmem_wdata[22] ;
+ wire \u_riscv_top.core_dmem_wdata[23] ;
+ wire \u_riscv_top.core_dmem_wdata[24] ;
+ wire \u_riscv_top.core_dmem_wdata[25] ;
+ wire \u_riscv_top.core_dmem_wdata[26] ;
+ wire \u_riscv_top.core_dmem_wdata[27] ;
+ wire \u_riscv_top.core_dmem_wdata[28] ;
+ wire \u_riscv_top.core_dmem_wdata[29] ;
+ wire \u_riscv_top.core_dmem_wdata[2] ;
+ wire \u_riscv_top.core_dmem_wdata[30] ;
+ wire \u_riscv_top.core_dmem_wdata[31] ;
+ wire \u_riscv_top.core_dmem_wdata[3] ;
+ wire \u_riscv_top.core_dmem_wdata[4] ;
+ wire \u_riscv_top.core_dmem_wdata[5] ;
+ wire \u_riscv_top.core_dmem_wdata[6] ;
+ wire \u_riscv_top.core_dmem_wdata[7] ;
+ wire \u_riscv_top.core_dmem_wdata[8] ;
+ wire \u_riscv_top.core_dmem_wdata[9] ;
+ wire \u_riscv_top.core_dmem_width[0] ;
+ wire \u_riscv_top.core_dmem_width[1] ;
+ wire \u_riscv_top.core_icache_addr[0] ;
+ wire \u_riscv_top.core_icache_addr[10] ;
+ wire \u_riscv_top.core_icache_addr[11] ;
+ wire \u_riscv_top.core_icache_addr[12] ;
+ wire \u_riscv_top.core_icache_addr[13] ;
+ wire \u_riscv_top.core_icache_addr[14] ;
+ wire \u_riscv_top.core_icache_addr[15] ;
+ wire \u_riscv_top.core_icache_addr[16] ;
+ wire \u_riscv_top.core_icache_addr[17] ;
+ wire \u_riscv_top.core_icache_addr[18] ;
+ wire \u_riscv_top.core_icache_addr[19] ;
+ wire \u_riscv_top.core_icache_addr[1] ;
+ wire \u_riscv_top.core_icache_addr[20] ;
+ wire \u_riscv_top.core_icache_addr[21] ;
+ wire \u_riscv_top.core_icache_addr[22] ;
+ wire \u_riscv_top.core_icache_addr[23] ;
+ wire \u_riscv_top.core_icache_addr[24] ;
+ wire \u_riscv_top.core_icache_addr[25] ;
+ wire \u_riscv_top.core_icache_addr[26] ;
+ wire \u_riscv_top.core_icache_addr[27] ;
+ wire \u_riscv_top.core_icache_addr[28] ;
+ wire \u_riscv_top.core_icache_addr[29] ;
+ wire \u_riscv_top.core_icache_addr[2] ;
+ wire \u_riscv_top.core_icache_addr[30] ;
+ wire \u_riscv_top.core_icache_addr[31] ;
+ wire \u_riscv_top.core_icache_addr[3] ;
+ wire \u_riscv_top.core_icache_addr[4] ;
+ wire \u_riscv_top.core_icache_addr[5] ;
+ wire \u_riscv_top.core_icache_addr[6] ;
+ wire \u_riscv_top.core_icache_addr[7] ;
+ wire \u_riscv_top.core_icache_addr[8] ;
+ wire \u_riscv_top.core_icache_addr[9] ;
+ wire \u_riscv_top.core_icache_bl[0] ;
+ wire \u_riscv_top.core_icache_bl[1] ;
+ wire \u_riscv_top.core_icache_bl[2] ;
+ wire \u_riscv_top.core_icache_cmd ;
+ wire \u_riscv_top.core_icache_rdata[0] ;
+ wire \u_riscv_top.core_icache_rdata[10] ;
+ wire \u_riscv_top.core_icache_rdata[11] ;
+ wire \u_riscv_top.core_icache_rdata[12] ;
+ wire \u_riscv_top.core_icache_rdata[13] ;
+ wire \u_riscv_top.core_icache_rdata[14] ;
+ wire \u_riscv_top.core_icache_rdata[15] ;
+ wire \u_riscv_top.core_icache_rdata[16] ;
+ wire \u_riscv_top.core_icache_rdata[17] ;
+ wire \u_riscv_top.core_icache_rdata[18] ;
+ wire \u_riscv_top.core_icache_rdata[19] ;
+ wire \u_riscv_top.core_icache_rdata[1] ;
+ wire \u_riscv_top.core_icache_rdata[20] ;
+ wire \u_riscv_top.core_icache_rdata[21] ;
+ wire \u_riscv_top.core_icache_rdata[22] ;
+ wire \u_riscv_top.core_icache_rdata[23] ;
+ wire \u_riscv_top.core_icache_rdata[24] ;
+ wire \u_riscv_top.core_icache_rdata[25] ;
+ wire \u_riscv_top.core_icache_rdata[26] ;
+ wire \u_riscv_top.core_icache_rdata[27] ;
+ wire \u_riscv_top.core_icache_rdata[28] ;
+ wire \u_riscv_top.core_icache_rdata[29] ;
+ wire \u_riscv_top.core_icache_rdata[2] ;
+ wire \u_riscv_top.core_icache_rdata[30] ;
+ wire \u_riscv_top.core_icache_rdata[31] ;
+ wire \u_riscv_top.core_icache_rdata[3] ;
+ wire \u_riscv_top.core_icache_rdata[4] ;
+ wire \u_riscv_top.core_icache_rdata[5] ;
+ wire \u_riscv_top.core_icache_rdata[6] ;
+ wire \u_riscv_top.core_icache_rdata[7] ;
+ wire \u_riscv_top.core_icache_rdata[8] ;
+ wire \u_riscv_top.core_icache_rdata[9] ;
+ wire \u_riscv_top.core_icache_req ;
+ wire \u_riscv_top.core_icache_req_ack ;
+ wire \u_riscv_top.core_icache_resp[0] ;
+ wire \u_riscv_top.core_icache_resp[1] ;
+ wire \u_riscv_top.core_icache_width[0] ;
+ wire \u_riscv_top.core_icache_width[1] ;
+ wire \u_riscv_top.cpu_core_rst_n[0] ;
+ wire \u_riscv_top.cpu_core_rst_n[1] ;
+ wire \u_riscv_top.cpu_core_rst_n[2] ;
+ wire \u_riscv_top.cpu_core_rst_n[3] ;
+ wire \u_riscv_top.cpu_intf_rst_n ;
+ wire \u_riscv_top.dcache_mem_addr0[0] ;
+ wire \u_riscv_top.dcache_mem_addr0[1] ;
+ wire \u_riscv_top.dcache_mem_addr0[2] ;
+ wire \u_riscv_top.dcache_mem_addr0[3] ;
+ wire \u_riscv_top.dcache_mem_addr0[4] ;
+ wire \u_riscv_top.dcache_mem_addr0[5] ;
+ wire \u_riscv_top.dcache_mem_addr0[6] ;
+ wire \u_riscv_top.dcache_mem_addr0[7] ;
+ wire \u_riscv_top.dcache_mem_addr0[8] ;
+ wire \u_riscv_top.dcache_mem_addr1[0] ;
+ wire \u_riscv_top.dcache_mem_addr1[1] ;
+ wire \u_riscv_top.dcache_mem_addr1[2] ;
+ wire \u_riscv_top.dcache_mem_addr1[3] ;
+ wire \u_riscv_top.dcache_mem_addr1[4] ;
+ wire \u_riscv_top.dcache_mem_addr1[5] ;
+ wire \u_riscv_top.dcache_mem_addr1[6] ;
+ wire \u_riscv_top.dcache_mem_addr1[7] ;
+ wire \u_riscv_top.dcache_mem_addr1[8] ;
+ wire \u_riscv_top.dcache_mem_clk0 ;
+ wire \u_riscv_top.dcache_mem_clk1 ;
+ wire \u_riscv_top.dcache_mem_csb0 ;
+ wire \u_riscv_top.dcache_mem_csb1 ;
+ wire \u_riscv_top.dcache_mem_din0[0] ;
+ wire \u_riscv_top.dcache_mem_din0[10] ;
+ wire \u_riscv_top.dcache_mem_din0[11] ;
+ wire \u_riscv_top.dcache_mem_din0[12] ;
+ wire \u_riscv_top.dcache_mem_din0[13] ;
+ wire \u_riscv_top.dcache_mem_din0[14] ;
+ wire \u_riscv_top.dcache_mem_din0[15] ;
+ wire \u_riscv_top.dcache_mem_din0[16] ;
+ wire \u_riscv_top.dcache_mem_din0[17] ;
+ wire \u_riscv_top.dcache_mem_din0[18] ;
+ wire \u_riscv_top.dcache_mem_din0[19] ;
+ wire \u_riscv_top.dcache_mem_din0[1] ;
+ wire \u_riscv_top.dcache_mem_din0[20] ;
+ wire \u_riscv_top.dcache_mem_din0[21] ;
+ wire \u_riscv_top.dcache_mem_din0[22] ;
+ wire \u_riscv_top.dcache_mem_din0[23] ;
+ wire \u_riscv_top.dcache_mem_din0[24] ;
+ wire \u_riscv_top.dcache_mem_din0[25] ;
+ wire \u_riscv_top.dcache_mem_din0[26] ;
+ wire \u_riscv_top.dcache_mem_din0[27] ;
+ wire \u_riscv_top.dcache_mem_din0[28] ;
+ wire \u_riscv_top.dcache_mem_din0[29] ;
+ wire \u_riscv_top.dcache_mem_din0[2] ;
+ wire \u_riscv_top.dcache_mem_din0[30] ;
+ wire \u_riscv_top.dcache_mem_din0[31] ;
+ wire \u_riscv_top.dcache_mem_din0[3] ;
+ wire \u_riscv_top.dcache_mem_din0[4] ;
+ wire \u_riscv_top.dcache_mem_din0[5] ;
+ wire \u_riscv_top.dcache_mem_din0[6] ;
+ wire \u_riscv_top.dcache_mem_din0[7] ;
+ wire \u_riscv_top.dcache_mem_din0[8] ;
+ wire \u_riscv_top.dcache_mem_din0[9] ;
+ wire \u_riscv_top.dcache_mem_dout0[0] ;
+ wire \u_riscv_top.dcache_mem_dout0[10] ;
+ wire \u_riscv_top.dcache_mem_dout0[11] ;
+ wire \u_riscv_top.dcache_mem_dout0[12] ;
+ wire \u_riscv_top.dcache_mem_dout0[13] ;
+ wire \u_riscv_top.dcache_mem_dout0[14] ;
+ wire \u_riscv_top.dcache_mem_dout0[15] ;
+ wire \u_riscv_top.dcache_mem_dout0[16] ;
+ wire \u_riscv_top.dcache_mem_dout0[17] ;
+ wire \u_riscv_top.dcache_mem_dout0[18] ;
+ wire \u_riscv_top.dcache_mem_dout0[19] ;
+ wire \u_riscv_top.dcache_mem_dout0[1] ;
+ wire \u_riscv_top.dcache_mem_dout0[20] ;
+ wire \u_riscv_top.dcache_mem_dout0[21] ;
+ wire \u_riscv_top.dcache_mem_dout0[22] ;
+ wire \u_riscv_top.dcache_mem_dout0[23] ;
+ wire \u_riscv_top.dcache_mem_dout0[24] ;
+ wire \u_riscv_top.dcache_mem_dout0[25] ;
+ wire \u_riscv_top.dcache_mem_dout0[26] ;
+ wire \u_riscv_top.dcache_mem_dout0[27] ;
+ wire \u_riscv_top.dcache_mem_dout0[28] ;
+ wire \u_riscv_top.dcache_mem_dout0[29] ;
+ wire \u_riscv_top.dcache_mem_dout0[2] ;
+ wire \u_riscv_top.dcache_mem_dout0[30] ;
+ wire \u_riscv_top.dcache_mem_dout0[31] ;
+ wire \u_riscv_top.dcache_mem_dout0[3] ;
+ wire \u_riscv_top.dcache_mem_dout0[4] ;
+ wire \u_riscv_top.dcache_mem_dout0[5] ;
+ wire \u_riscv_top.dcache_mem_dout0[6] ;
+ wire \u_riscv_top.dcache_mem_dout0[7] ;
+ wire \u_riscv_top.dcache_mem_dout0[8] ;
+ wire \u_riscv_top.dcache_mem_dout0[9] ;
+ wire \u_riscv_top.dcache_mem_dout1[0] ;
+ wire \u_riscv_top.dcache_mem_dout1[10] ;
+ wire \u_riscv_top.dcache_mem_dout1[11] ;
+ wire \u_riscv_top.dcache_mem_dout1[12] ;
+ wire \u_riscv_top.dcache_mem_dout1[13] ;
+ wire \u_riscv_top.dcache_mem_dout1[14] ;
+ wire \u_riscv_top.dcache_mem_dout1[15] ;
+ wire \u_riscv_top.dcache_mem_dout1[16] ;
+ wire \u_riscv_top.dcache_mem_dout1[17] ;
+ wire \u_riscv_top.dcache_mem_dout1[18] ;
+ wire \u_riscv_top.dcache_mem_dout1[19] ;
+ wire \u_riscv_top.dcache_mem_dout1[1] ;
+ wire \u_riscv_top.dcache_mem_dout1[20] ;
+ wire \u_riscv_top.dcache_mem_dout1[21] ;
+ wire \u_riscv_top.dcache_mem_dout1[22] ;
+ wire \u_riscv_top.dcache_mem_dout1[23] ;
+ wire \u_riscv_top.dcache_mem_dout1[24] ;
+ wire \u_riscv_top.dcache_mem_dout1[25] ;
+ wire \u_riscv_top.dcache_mem_dout1[26] ;
+ wire \u_riscv_top.dcache_mem_dout1[27] ;
+ wire \u_riscv_top.dcache_mem_dout1[28] ;
+ wire \u_riscv_top.dcache_mem_dout1[29] ;
+ wire \u_riscv_top.dcache_mem_dout1[2] ;
+ wire \u_riscv_top.dcache_mem_dout1[30] ;
+ wire \u_riscv_top.dcache_mem_dout1[31] ;
+ wire \u_riscv_top.dcache_mem_dout1[3] ;
+ wire \u_riscv_top.dcache_mem_dout1[4] ;
+ wire \u_riscv_top.dcache_mem_dout1[5] ;
+ wire \u_riscv_top.dcache_mem_dout1[6] ;
+ wire \u_riscv_top.dcache_mem_dout1[7] ;
+ wire \u_riscv_top.dcache_mem_dout1[8] ;
+ wire \u_riscv_top.dcache_mem_dout1[9] ;
+ wire \u_riscv_top.dcache_mem_web0 ;
+ wire \u_riscv_top.dcache_mem_wmask0[0] ;
+ wire \u_riscv_top.dcache_mem_wmask0[1] ;
+ wire \u_riscv_top.dcache_mem_wmask0[2] ;
+ wire \u_riscv_top.dcache_mem_wmask0[3] ;
+ wire \u_riscv_top.icache_mem_addr0[0] ;
+ wire \u_riscv_top.icache_mem_addr0[1] ;
+ wire \u_riscv_top.icache_mem_addr0[2] ;
+ wire \u_riscv_top.icache_mem_addr0[3] ;
+ wire \u_riscv_top.icache_mem_addr0[4] ;
+ wire \u_riscv_top.icache_mem_addr0[5] ;
+ wire \u_riscv_top.icache_mem_addr0[6] ;
+ wire \u_riscv_top.icache_mem_addr0[7] ;
+ wire \u_riscv_top.icache_mem_addr0[8] ;
+ wire \u_riscv_top.icache_mem_addr1[0] ;
+ wire \u_riscv_top.icache_mem_addr1[1] ;
+ wire \u_riscv_top.icache_mem_addr1[2] ;
+ wire \u_riscv_top.icache_mem_addr1[3] ;
+ wire \u_riscv_top.icache_mem_addr1[4] ;
+ wire \u_riscv_top.icache_mem_addr1[5] ;
+ wire \u_riscv_top.icache_mem_addr1[6] ;
+ wire \u_riscv_top.icache_mem_addr1[7] ;
+ wire \u_riscv_top.icache_mem_addr1[8] ;
+ wire \u_riscv_top.icache_mem_clk0 ;
+ wire \u_riscv_top.icache_mem_clk1 ;
+ wire \u_riscv_top.icache_mem_csb0 ;
+ wire \u_riscv_top.icache_mem_csb1 ;
+ wire \u_riscv_top.icache_mem_din0[0] ;
+ wire \u_riscv_top.icache_mem_din0[10] ;
+ wire \u_riscv_top.icache_mem_din0[11] ;
+ wire \u_riscv_top.icache_mem_din0[12] ;
+ wire \u_riscv_top.icache_mem_din0[13] ;
+ wire \u_riscv_top.icache_mem_din0[14] ;
+ wire \u_riscv_top.icache_mem_din0[15] ;
+ wire \u_riscv_top.icache_mem_din0[16] ;
+ wire \u_riscv_top.icache_mem_din0[17] ;
+ wire \u_riscv_top.icache_mem_din0[18] ;
+ wire \u_riscv_top.icache_mem_din0[19] ;
+ wire \u_riscv_top.icache_mem_din0[1] ;
+ wire \u_riscv_top.icache_mem_din0[20] ;
+ wire \u_riscv_top.icache_mem_din0[21] ;
+ wire \u_riscv_top.icache_mem_din0[22] ;
+ wire \u_riscv_top.icache_mem_din0[23] ;
+ wire \u_riscv_top.icache_mem_din0[24] ;
+ wire \u_riscv_top.icache_mem_din0[25] ;
+ wire \u_riscv_top.icache_mem_din0[26] ;
+ wire \u_riscv_top.icache_mem_din0[27] ;
+ wire \u_riscv_top.icache_mem_din0[28] ;
+ wire \u_riscv_top.icache_mem_din0[29] ;
+ wire \u_riscv_top.icache_mem_din0[2] ;
+ wire \u_riscv_top.icache_mem_din0[30] ;
+ wire \u_riscv_top.icache_mem_din0[31] ;
+ wire \u_riscv_top.icache_mem_din0[3] ;
+ wire \u_riscv_top.icache_mem_din0[4] ;
+ wire \u_riscv_top.icache_mem_din0[5] ;
+ wire \u_riscv_top.icache_mem_din0[6] ;
+ wire \u_riscv_top.icache_mem_din0[7] ;
+ wire \u_riscv_top.icache_mem_din0[8] ;
+ wire \u_riscv_top.icache_mem_din0[9] ;
+ wire \u_riscv_top.icache_mem_dout1[0] ;
+ wire \u_riscv_top.icache_mem_dout1[10] ;
+ wire \u_riscv_top.icache_mem_dout1[11] ;
+ wire \u_riscv_top.icache_mem_dout1[12] ;
+ wire \u_riscv_top.icache_mem_dout1[13] ;
+ wire \u_riscv_top.icache_mem_dout1[14] ;
+ wire \u_riscv_top.icache_mem_dout1[15] ;
+ wire \u_riscv_top.icache_mem_dout1[16] ;
+ wire \u_riscv_top.icache_mem_dout1[17] ;
+ wire \u_riscv_top.icache_mem_dout1[18] ;
+ wire \u_riscv_top.icache_mem_dout1[19] ;
+ wire \u_riscv_top.icache_mem_dout1[1] ;
+ wire \u_riscv_top.icache_mem_dout1[20] ;
+ wire \u_riscv_top.icache_mem_dout1[21] ;
+ wire \u_riscv_top.icache_mem_dout1[22] ;
+ wire \u_riscv_top.icache_mem_dout1[23] ;
+ wire \u_riscv_top.icache_mem_dout1[24] ;
+ wire \u_riscv_top.icache_mem_dout1[25] ;
+ wire \u_riscv_top.icache_mem_dout1[26] ;
+ wire \u_riscv_top.icache_mem_dout1[27] ;
+ wire \u_riscv_top.icache_mem_dout1[28] ;
+ wire \u_riscv_top.icache_mem_dout1[29] ;
+ wire \u_riscv_top.icache_mem_dout1[2] ;
+ wire \u_riscv_top.icache_mem_dout1[30] ;
+ wire \u_riscv_top.icache_mem_dout1[31] ;
+ wire \u_riscv_top.icache_mem_dout1[3] ;
+ wire \u_riscv_top.icache_mem_dout1[4] ;
+ wire \u_riscv_top.icache_mem_dout1[5] ;
+ wire \u_riscv_top.icache_mem_dout1[6] ;
+ wire \u_riscv_top.icache_mem_dout1[7] ;
+ wire \u_riscv_top.icache_mem_dout1[8] ;
+ wire \u_riscv_top.icache_mem_dout1[9] ;
+ wire \u_riscv_top.icache_mem_web0 ;
+ wire \u_riscv_top.icache_mem_wmask0[0] ;
+ wire \u_riscv_top.icache_mem_wmask0[1] ;
+ wire \u_riscv_top.icache_mem_wmask0[2] ;
+ wire \u_riscv_top.icache_mem_wmask0[3] ;
+ wire \u_riscv_top.irq_lines[0] ;
+ wire \u_riscv_top.irq_lines[10] ;
+ wire \u_riscv_top.irq_lines[11] ;
+ wire \u_riscv_top.irq_lines[12] ;
+ wire \u_riscv_top.irq_lines[13] ;
+ wire \u_riscv_top.irq_lines[14] ;
+ wire \u_riscv_top.irq_lines[15] ;
+ wire \u_riscv_top.irq_lines[1] ;
+ wire \u_riscv_top.irq_lines[2] ;
+ wire \u_riscv_top.irq_lines[3] ;
+ wire \u_riscv_top.irq_lines[4] ;
+ wire \u_riscv_top.irq_lines[5] ;
+ wire \u_riscv_top.irq_lines[6] ;
+ wire \u_riscv_top.irq_lines[7] ;
+ wire \u_riscv_top.irq_lines[8] ;
+ wire \u_riscv_top.irq_lines[9] ;
+ wire \u_riscv_top.pwrup_rst_n ;
+ wire \u_riscv_top.rtc_clk ;
+ wire \u_riscv_top.soft_irq ;
+ wire \u_riscv_top.sram0_addr0[0] ;
+ wire \u_riscv_top.sram0_addr0[1] ;
+ wire \u_riscv_top.sram0_addr0[2] ;
+ wire \u_riscv_top.sram0_addr0[3] ;
+ wire \u_riscv_top.sram0_addr0[4] ;
+ wire \u_riscv_top.sram0_addr0[5] ;
+ wire \u_riscv_top.sram0_addr0[6] ;
+ wire \u_riscv_top.sram0_addr0[7] ;
+ wire \u_riscv_top.sram0_addr0[8] ;
+ wire \u_riscv_top.sram0_addr1[0] ;
+ wire \u_riscv_top.sram0_addr1[1] ;
+ wire \u_riscv_top.sram0_addr1[2] ;
+ wire \u_riscv_top.sram0_addr1[3] ;
+ wire \u_riscv_top.sram0_addr1[4] ;
+ wire \u_riscv_top.sram0_addr1[5] ;
+ wire \u_riscv_top.sram0_addr1[6] ;
+ wire \u_riscv_top.sram0_addr1[7] ;
+ wire \u_riscv_top.sram0_addr1[8] ;
+ wire \u_riscv_top.sram0_clk0 ;
+ wire \u_riscv_top.sram0_clk1 ;
+ wire \u_riscv_top.sram0_csb0 ;
+ wire \u_riscv_top.sram0_csb1 ;
+ wire \u_riscv_top.sram0_din0[0] ;
+ wire \u_riscv_top.sram0_din0[10] ;
+ wire \u_riscv_top.sram0_din0[11] ;
+ wire \u_riscv_top.sram0_din0[12] ;
+ wire \u_riscv_top.sram0_din0[13] ;
+ wire \u_riscv_top.sram0_din0[14] ;
+ wire \u_riscv_top.sram0_din0[15] ;
+ wire \u_riscv_top.sram0_din0[16] ;
+ wire \u_riscv_top.sram0_din0[17] ;
+ wire \u_riscv_top.sram0_din0[18] ;
+ wire \u_riscv_top.sram0_din0[19] ;
+ wire \u_riscv_top.sram0_din0[1] ;
+ wire \u_riscv_top.sram0_din0[20] ;
+ wire \u_riscv_top.sram0_din0[21] ;
+ wire \u_riscv_top.sram0_din0[22] ;
+ wire \u_riscv_top.sram0_din0[23] ;
+ wire \u_riscv_top.sram0_din0[24] ;
+ wire \u_riscv_top.sram0_din0[25] ;
+ wire \u_riscv_top.sram0_din0[26] ;
+ wire \u_riscv_top.sram0_din0[27] ;
+ wire \u_riscv_top.sram0_din0[28] ;
+ wire \u_riscv_top.sram0_din0[29] ;
+ wire \u_riscv_top.sram0_din0[2] ;
+ wire \u_riscv_top.sram0_din0[30] ;
+ wire \u_riscv_top.sram0_din0[31] ;
+ wire \u_riscv_top.sram0_din0[3] ;
+ wire \u_riscv_top.sram0_din0[4] ;
+ wire \u_riscv_top.sram0_din0[5] ;
+ wire \u_riscv_top.sram0_din0[6] ;
+ wire \u_riscv_top.sram0_din0[7] ;
+ wire \u_riscv_top.sram0_din0[8] ;
+ wire \u_riscv_top.sram0_din0[9] ;
+ wire \u_riscv_top.sram0_dout0[0] ;
+ wire \u_riscv_top.sram0_dout0[10] ;
+ wire \u_riscv_top.sram0_dout0[11] ;
+ wire \u_riscv_top.sram0_dout0[12] ;
+ wire \u_riscv_top.sram0_dout0[13] ;
+ wire \u_riscv_top.sram0_dout0[14] ;
+ wire \u_riscv_top.sram0_dout0[15] ;
+ wire \u_riscv_top.sram0_dout0[16] ;
+ wire \u_riscv_top.sram0_dout0[17] ;
+ wire \u_riscv_top.sram0_dout0[18] ;
+ wire \u_riscv_top.sram0_dout0[19] ;
+ wire \u_riscv_top.sram0_dout0[1] ;
+ wire \u_riscv_top.sram0_dout0[20] ;
+ wire \u_riscv_top.sram0_dout0[21] ;
+ wire \u_riscv_top.sram0_dout0[22] ;
+ wire \u_riscv_top.sram0_dout0[23] ;
+ wire \u_riscv_top.sram0_dout0[24] ;
+ wire \u_riscv_top.sram0_dout0[25] ;
+ wire \u_riscv_top.sram0_dout0[26] ;
+ wire \u_riscv_top.sram0_dout0[27] ;
+ wire \u_riscv_top.sram0_dout0[28] ;
+ wire \u_riscv_top.sram0_dout0[29] ;
+ wire \u_riscv_top.sram0_dout0[2] ;
+ wire \u_riscv_top.sram0_dout0[30] ;
+ wire \u_riscv_top.sram0_dout0[31] ;
+ wire \u_riscv_top.sram0_dout0[3] ;
+ wire \u_riscv_top.sram0_dout0[4] ;
+ wire \u_riscv_top.sram0_dout0[5] ;
+ wire \u_riscv_top.sram0_dout0[6] ;
+ wire \u_riscv_top.sram0_dout0[7] ;
+ wire \u_riscv_top.sram0_dout0[8] ;
+ wire \u_riscv_top.sram0_dout0[9] ;
+ wire \u_riscv_top.sram0_dout1[0] ;
+ wire \u_riscv_top.sram0_dout1[10] ;
+ wire \u_riscv_top.sram0_dout1[11] ;
+ wire \u_riscv_top.sram0_dout1[12] ;
+ wire \u_riscv_top.sram0_dout1[13] ;
+ wire \u_riscv_top.sram0_dout1[14] ;
+ wire \u_riscv_top.sram0_dout1[15] ;
+ wire \u_riscv_top.sram0_dout1[16] ;
+ wire \u_riscv_top.sram0_dout1[17] ;
+ wire \u_riscv_top.sram0_dout1[18] ;
+ wire \u_riscv_top.sram0_dout1[19] ;
+ wire \u_riscv_top.sram0_dout1[1] ;
+ wire \u_riscv_top.sram0_dout1[20] ;
+ wire \u_riscv_top.sram0_dout1[21] ;
+ wire \u_riscv_top.sram0_dout1[22] ;
+ wire \u_riscv_top.sram0_dout1[23] ;
+ wire \u_riscv_top.sram0_dout1[24] ;
+ wire \u_riscv_top.sram0_dout1[25] ;
+ wire \u_riscv_top.sram0_dout1[26] ;
+ wire \u_riscv_top.sram0_dout1[27] ;
+ wire \u_riscv_top.sram0_dout1[28] ;
+ wire \u_riscv_top.sram0_dout1[29] ;
+ wire \u_riscv_top.sram0_dout1[2] ;
+ wire \u_riscv_top.sram0_dout1[30] ;
+ wire \u_riscv_top.sram0_dout1[31] ;
+ wire \u_riscv_top.sram0_dout1[3] ;
+ wire \u_riscv_top.sram0_dout1[4] ;
+ wire \u_riscv_top.sram0_dout1[5] ;
+ wire \u_riscv_top.sram0_dout1[6] ;
+ wire \u_riscv_top.sram0_dout1[7] ;
+ wire \u_riscv_top.sram0_dout1[8] ;
+ wire \u_riscv_top.sram0_dout1[9] ;
+ wire \u_riscv_top.sram0_web0 ;
+ wire \u_riscv_top.sram0_wmask0[0] ;
+ wire \u_riscv_top.sram0_wmask0[1] ;
+ wire \u_riscv_top.sram0_wmask0[2] ;
+ wire \u_riscv_top.sram0_wmask0[3] ;
+ wire \u_riscv_top.wb_clk ;
+ wire \u_riscv_top.wb_dcache_ack_i ;
+ wire \u_riscv_top.wb_dcache_adr_o[0] ;
+ wire \u_riscv_top.wb_dcache_adr_o[10] ;
+ wire \u_riscv_top.wb_dcache_adr_o[11] ;
+ wire \u_riscv_top.wb_dcache_adr_o[12] ;
+ wire \u_riscv_top.wb_dcache_adr_o[13] ;
+ wire \u_riscv_top.wb_dcache_adr_o[14] ;
+ wire \u_riscv_top.wb_dcache_adr_o[15] ;
+ wire \u_riscv_top.wb_dcache_adr_o[16] ;
+ wire \u_riscv_top.wb_dcache_adr_o[17] ;
+ wire \u_riscv_top.wb_dcache_adr_o[18] ;
+ wire \u_riscv_top.wb_dcache_adr_o[19] ;
+ wire \u_riscv_top.wb_dcache_adr_o[1] ;
+ wire \u_riscv_top.wb_dcache_adr_o[20] ;
+ wire \u_riscv_top.wb_dcache_adr_o[21] ;
+ wire \u_riscv_top.wb_dcache_adr_o[22] ;
+ wire \u_riscv_top.wb_dcache_adr_o[23] ;
+ wire \u_riscv_top.wb_dcache_adr_o[24] ;
+ wire \u_riscv_top.wb_dcache_adr_o[25] ;
+ wire \u_riscv_top.wb_dcache_adr_o[26] ;
+ wire \u_riscv_top.wb_dcache_adr_o[27] ;
+ wire \u_riscv_top.wb_dcache_adr_o[28] ;
+ wire \u_riscv_top.wb_dcache_adr_o[29] ;
+ wire \u_riscv_top.wb_dcache_adr_o[2] ;
+ wire \u_riscv_top.wb_dcache_adr_o[30] ;
+ wire \u_riscv_top.wb_dcache_adr_o[31] ;
+ wire \u_riscv_top.wb_dcache_adr_o[3] ;
+ wire \u_riscv_top.wb_dcache_adr_o[4] ;
+ wire \u_riscv_top.wb_dcache_adr_o[5] ;
+ wire \u_riscv_top.wb_dcache_adr_o[6] ;
+ wire \u_riscv_top.wb_dcache_adr_o[7] ;
+ wire \u_riscv_top.wb_dcache_adr_o[8] ;
+ wire \u_riscv_top.wb_dcache_adr_o[9] ;
+ wire \u_riscv_top.wb_dcache_bl_o[0] ;
+ wire \u_riscv_top.wb_dcache_bl_o[1] ;
+ wire \u_riscv_top.wb_dcache_bl_o[2] ;
+ wire \u_riscv_top.wb_dcache_bl_o[3] ;
+ wire \u_riscv_top.wb_dcache_bl_o[4] ;
+ wire \u_riscv_top.wb_dcache_bl_o[5] ;
+ wire \u_riscv_top.wb_dcache_bl_o[6] ;
+ wire \u_riscv_top.wb_dcache_bl_o[7] ;
+ wire \u_riscv_top.wb_dcache_bl_o[8] ;
+ wire \u_riscv_top.wb_dcache_bl_o[9] ;
+ wire \u_riscv_top.wb_dcache_bry_o ;
+ wire \u_riscv_top.wb_dcache_cyc_o ;
+ wire \u_riscv_top.wb_dcache_dat_i[0] ;
+ wire \u_riscv_top.wb_dcache_dat_i[10] ;
+ wire \u_riscv_top.wb_dcache_dat_i[11] ;
+ wire \u_riscv_top.wb_dcache_dat_i[12] ;
+ wire \u_riscv_top.wb_dcache_dat_i[13] ;
+ wire \u_riscv_top.wb_dcache_dat_i[14] ;
+ wire \u_riscv_top.wb_dcache_dat_i[15] ;
+ wire \u_riscv_top.wb_dcache_dat_i[16] ;
+ wire \u_riscv_top.wb_dcache_dat_i[17] ;
+ wire \u_riscv_top.wb_dcache_dat_i[18] ;
+ wire \u_riscv_top.wb_dcache_dat_i[19] ;
+ wire \u_riscv_top.wb_dcache_dat_i[1] ;
+ wire \u_riscv_top.wb_dcache_dat_i[20] ;
+ wire \u_riscv_top.wb_dcache_dat_i[21] ;
+ wire \u_riscv_top.wb_dcache_dat_i[22] ;
+ wire \u_riscv_top.wb_dcache_dat_i[23] ;
+ wire \u_riscv_top.wb_dcache_dat_i[24] ;
+ wire \u_riscv_top.wb_dcache_dat_i[25] ;
+ wire \u_riscv_top.wb_dcache_dat_i[26] ;
+ wire \u_riscv_top.wb_dcache_dat_i[27] ;
+ wire \u_riscv_top.wb_dcache_dat_i[28] ;
+ wire \u_riscv_top.wb_dcache_dat_i[29] ;
+ wire \u_riscv_top.wb_dcache_dat_i[2] ;
+ wire \u_riscv_top.wb_dcache_dat_i[30] ;
+ wire \u_riscv_top.wb_dcache_dat_i[31] ;
+ wire \u_riscv_top.wb_dcache_dat_i[3] ;
+ wire \u_riscv_top.wb_dcache_dat_i[4] ;
+ wire \u_riscv_top.wb_dcache_dat_i[5] ;
+ wire \u_riscv_top.wb_dcache_dat_i[6] ;
+ wire \u_riscv_top.wb_dcache_dat_i[7] ;
+ wire \u_riscv_top.wb_dcache_dat_i[8] ;
+ wire \u_riscv_top.wb_dcache_dat_i[9] ;
+ wire \u_riscv_top.wb_dcache_dat_o[0] ;
+ wire \u_riscv_top.wb_dcache_dat_o[10] ;
+ wire \u_riscv_top.wb_dcache_dat_o[11] ;
+ wire \u_riscv_top.wb_dcache_dat_o[12] ;
+ wire \u_riscv_top.wb_dcache_dat_o[13] ;
+ wire \u_riscv_top.wb_dcache_dat_o[14] ;
+ wire \u_riscv_top.wb_dcache_dat_o[15] ;
+ wire \u_riscv_top.wb_dcache_dat_o[16] ;
+ wire \u_riscv_top.wb_dcache_dat_o[17] ;
+ wire \u_riscv_top.wb_dcache_dat_o[18] ;
+ wire \u_riscv_top.wb_dcache_dat_o[19] ;
+ wire \u_riscv_top.wb_dcache_dat_o[1] ;
+ wire \u_riscv_top.wb_dcache_dat_o[20] ;
+ wire \u_riscv_top.wb_dcache_dat_o[21] ;
+ wire \u_riscv_top.wb_dcache_dat_o[22] ;
+ wire \u_riscv_top.wb_dcache_dat_o[23] ;
+ wire \u_riscv_top.wb_dcache_dat_o[24] ;
+ wire \u_riscv_top.wb_dcache_dat_o[25] ;
+ wire \u_riscv_top.wb_dcache_dat_o[26] ;
+ wire \u_riscv_top.wb_dcache_dat_o[27] ;
+ wire \u_riscv_top.wb_dcache_dat_o[28] ;
+ wire \u_riscv_top.wb_dcache_dat_o[29] ;
+ wire \u_riscv_top.wb_dcache_dat_o[2] ;
+ wire \u_riscv_top.wb_dcache_dat_o[30] ;
+ wire \u_riscv_top.wb_dcache_dat_o[31] ;
+ wire \u_riscv_top.wb_dcache_dat_o[3] ;
+ wire \u_riscv_top.wb_dcache_dat_o[4] ;
+ wire \u_riscv_top.wb_dcache_dat_o[5] ;
+ wire \u_riscv_top.wb_dcache_dat_o[6] ;
+ wire \u_riscv_top.wb_dcache_dat_o[7] ;
+ wire \u_riscv_top.wb_dcache_dat_o[8] ;
+ wire \u_riscv_top.wb_dcache_dat_o[9] ;
+ wire \u_riscv_top.wb_dcache_err_i ;
+ wire \u_riscv_top.wb_dcache_lack_i ;
+ wire \u_riscv_top.wb_dcache_sel_o[0] ;
+ wire \u_riscv_top.wb_dcache_sel_o[1] ;
+ wire \u_riscv_top.wb_dcache_sel_o[2] ;
+ wire \u_riscv_top.wb_dcache_sel_o[3] ;
+ wire \u_riscv_top.wb_dcache_stb_o ;
+ wire \u_riscv_top.wb_dcache_we_o ;
+ wire \u_riscv_top.wb_icache_ack_i ;
+ wire \u_riscv_top.wb_icache_adr_o[0] ;
+ wire \u_riscv_top.wb_icache_adr_o[10] ;
+ wire \u_riscv_top.wb_icache_adr_o[11] ;
+ wire \u_riscv_top.wb_icache_adr_o[12] ;
+ wire \u_riscv_top.wb_icache_adr_o[13] ;
+ wire \u_riscv_top.wb_icache_adr_o[14] ;
+ wire \u_riscv_top.wb_icache_adr_o[15] ;
+ wire \u_riscv_top.wb_icache_adr_o[16] ;
+ wire \u_riscv_top.wb_icache_adr_o[17] ;
+ wire \u_riscv_top.wb_icache_adr_o[18] ;
+ wire \u_riscv_top.wb_icache_adr_o[19] ;
+ wire \u_riscv_top.wb_icache_adr_o[1] ;
+ wire \u_riscv_top.wb_icache_adr_o[20] ;
+ wire \u_riscv_top.wb_icache_adr_o[21] ;
+ wire \u_riscv_top.wb_icache_adr_o[22] ;
+ wire \u_riscv_top.wb_icache_adr_o[23] ;
+ wire \u_riscv_top.wb_icache_adr_o[24] ;
+ wire \u_riscv_top.wb_icache_adr_o[25] ;
+ wire \u_riscv_top.wb_icache_adr_o[26] ;
+ wire \u_riscv_top.wb_icache_adr_o[27] ;
+ wire \u_riscv_top.wb_icache_adr_o[28] ;
+ wire \u_riscv_top.wb_icache_adr_o[29] ;
+ wire \u_riscv_top.wb_icache_adr_o[2] ;
+ wire \u_riscv_top.wb_icache_adr_o[30] ;
+ wire \u_riscv_top.wb_icache_adr_o[31] ;
+ wire \u_riscv_top.wb_icache_adr_o[3] ;
+ wire \u_riscv_top.wb_icache_adr_o[4] ;
+ wire \u_riscv_top.wb_icache_adr_o[5] ;
+ wire \u_riscv_top.wb_icache_adr_o[6] ;
+ wire \u_riscv_top.wb_icache_adr_o[7] ;
+ wire \u_riscv_top.wb_icache_adr_o[8] ;
+ wire \u_riscv_top.wb_icache_adr_o[9] ;
+ wire \u_riscv_top.wb_icache_bl_o[0] ;
+ wire \u_riscv_top.wb_icache_bl_o[1] ;
+ wire \u_riscv_top.wb_icache_bl_o[2] ;
+ wire \u_riscv_top.wb_icache_bl_o[3] ;
+ wire \u_riscv_top.wb_icache_bl_o[4] ;
+ wire \u_riscv_top.wb_icache_bl_o[5] ;
+ wire \u_riscv_top.wb_icache_bl_o[6] ;
+ wire \u_riscv_top.wb_icache_bl_o[7] ;
+ wire \u_riscv_top.wb_icache_bl_o[8] ;
+ wire \u_riscv_top.wb_icache_bl_o[9] ;
+ wire \u_riscv_top.wb_icache_bry_o ;
+ wire \u_riscv_top.wb_icache_cyc_o ;
+ wire \u_riscv_top.wb_icache_dat_i[0] ;
+ wire \u_riscv_top.wb_icache_dat_i[10] ;
+ wire \u_riscv_top.wb_icache_dat_i[11] ;
+ wire \u_riscv_top.wb_icache_dat_i[12] ;
+ wire \u_riscv_top.wb_icache_dat_i[13] ;
+ wire \u_riscv_top.wb_icache_dat_i[14] ;
+ wire \u_riscv_top.wb_icache_dat_i[15] ;
+ wire \u_riscv_top.wb_icache_dat_i[16] ;
+ wire \u_riscv_top.wb_icache_dat_i[17] ;
+ wire \u_riscv_top.wb_icache_dat_i[18] ;
+ wire \u_riscv_top.wb_icache_dat_i[19] ;
+ wire \u_riscv_top.wb_icache_dat_i[1] ;
+ wire \u_riscv_top.wb_icache_dat_i[20] ;
+ wire \u_riscv_top.wb_icache_dat_i[21] ;
+ wire \u_riscv_top.wb_icache_dat_i[22] ;
+ wire \u_riscv_top.wb_icache_dat_i[23] ;
+ wire \u_riscv_top.wb_icache_dat_i[24] ;
+ wire \u_riscv_top.wb_icache_dat_i[25] ;
+ wire \u_riscv_top.wb_icache_dat_i[26] ;
+ wire \u_riscv_top.wb_icache_dat_i[27] ;
+ wire \u_riscv_top.wb_icache_dat_i[28] ;
+ wire \u_riscv_top.wb_icache_dat_i[29] ;
+ wire \u_riscv_top.wb_icache_dat_i[2] ;
+ wire \u_riscv_top.wb_icache_dat_i[30] ;
+ wire \u_riscv_top.wb_icache_dat_i[31] ;
+ wire \u_riscv_top.wb_icache_dat_i[3] ;
+ wire \u_riscv_top.wb_icache_dat_i[4] ;
+ wire \u_riscv_top.wb_icache_dat_i[5] ;
+ wire \u_riscv_top.wb_icache_dat_i[6] ;
+ wire \u_riscv_top.wb_icache_dat_i[7] ;
+ wire \u_riscv_top.wb_icache_dat_i[8] ;
+ wire \u_riscv_top.wb_icache_dat_i[9] ;
+ wire \u_riscv_top.wb_icache_err_i ;
+ wire \u_riscv_top.wb_icache_lack_i ;
+ wire \u_riscv_top.wb_icache_sel_o[0] ;
+ wire \u_riscv_top.wb_icache_sel_o[1] ;
+ wire \u_riscv_top.wb_icache_sel_o[2] ;
+ wire \u_riscv_top.wb_icache_sel_o[3] ;
+ wire \u_riscv_top.wb_icache_stb_o ;
+ wire \u_riscv_top.wb_icache_we_o ;
+ wire \u_riscv_top.wbd_clk_int ;
+ wire \u_riscv_top.wbd_dmem_ack_i ;
+ wire \u_riscv_top.wbd_dmem_adr_o[0] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[10] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[11] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[12] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[13] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[14] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[15] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[16] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[17] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[18] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[19] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[1] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[20] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[21] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[22] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[23] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[24] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[25] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[26] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[27] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[28] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[29] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[2] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[30] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[31] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[3] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[4] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[5] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[6] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[7] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[8] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[9] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[0] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[10] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[11] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[12] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[13] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[14] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[15] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[16] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[17] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[18] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[19] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[1] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[20] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[21] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[22] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[23] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[24] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[25] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[26] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[27] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[28] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[29] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[2] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[30] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[31] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[3] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[4] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[5] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[6] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[7] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[8] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[9] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[0] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[10] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[11] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[12] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[13] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[14] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[15] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[16] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[17] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[18] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[19] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[1] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[20] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[21] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[22] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[23] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[24] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[25] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[26] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[27] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[28] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[29] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[2] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[30] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[31] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[3] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[4] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[5] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[6] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[7] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[8] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[9] ;
+ wire \u_riscv_top.wbd_dmem_err_i ;
+ wire \u_riscv_top.wbd_dmem_sel_o[0] ;
+ wire \u_riscv_top.wbd_dmem_sel_o[1] ;
+ wire \u_riscv_top.wbd_dmem_sel_o[2] ;
+ wire \u_riscv_top.wbd_dmem_sel_o[3] ;
+ wire \u_riscv_top.wbd_dmem_stb_o ;
+ wire \u_riscv_top.wbd_dmem_we_o ;
+ wire \uart_rst_n[0] ;
+ wire \uart_rst_n[1] ;
+ wire \uart_rxd[0] ;
+ wire \uart_rxd[1] ;
+ wire \uart_txd[0] ;
+ wire \uart_txd[1] ;
+ wire uartm_rxd;
+ wire uartm_txd;
+ wire usb_clk;
+ wire usb_dn_i;
+ wire usb_dn_o;
+ wire usb_dp_i;
+ wire usb_dp_o;
+ wire usb_intr_o;
+ wire usb_oen;
+ wire usb_rst_n;
+ wire wbd_clk_int;
+ wire wbd_clk_pinmux_rp;
+ wire wbd_clk_pinmux_skew;
+ wire wbd_clk_qspi_rp;
+ wire wbd_clk_spi;
+ wire wbd_clk_uart_rp;
+ wire wbd_clk_uart_skew;
+ wire wbd_clk_wh;
+ wire wbd_clk_wi_skew;
+ wire wbd_glbl_ack_i;
+ wire \wbd_glbl_adr_o[0] ;
+ wire \wbd_glbl_adr_o[1] ;
+ wire \wbd_glbl_adr_o[2] ;
+ wire \wbd_glbl_adr_o[3] ;
+ wire \wbd_glbl_adr_o[4] ;
+ wire \wbd_glbl_adr_o[5] ;
+ wire \wbd_glbl_adr_o[6] ;
+ wire \wbd_glbl_adr_o[7] ;
+ wire wbd_glbl_cyc_o;
+ wire \wbd_glbl_dat_i[0] ;
+ wire \wbd_glbl_dat_i[10] ;
+ wire \wbd_glbl_dat_i[11] ;
+ wire \wbd_glbl_dat_i[12] ;
+ wire \wbd_glbl_dat_i[13] ;
+ wire \wbd_glbl_dat_i[14] ;
+ wire \wbd_glbl_dat_i[15] ;
+ wire \wbd_glbl_dat_i[16] ;
+ wire \wbd_glbl_dat_i[17] ;
+ wire \wbd_glbl_dat_i[18] ;
+ wire \wbd_glbl_dat_i[19] ;
+ wire \wbd_glbl_dat_i[1] ;
+ wire \wbd_glbl_dat_i[20] ;
+ wire \wbd_glbl_dat_i[21] ;
+ wire \wbd_glbl_dat_i[22] ;
+ wire \wbd_glbl_dat_i[23] ;
+ wire \wbd_glbl_dat_i[24] ;
+ wire \wbd_glbl_dat_i[25] ;
+ wire \wbd_glbl_dat_i[26] ;
+ wire \wbd_glbl_dat_i[27] ;
+ wire \wbd_glbl_dat_i[28] ;
+ wire \wbd_glbl_dat_i[29] ;
+ wire \wbd_glbl_dat_i[2] ;
+ wire \wbd_glbl_dat_i[30] ;
+ wire \wbd_glbl_dat_i[31] ;
+ wire \wbd_glbl_dat_i[3] ;
+ wire \wbd_glbl_dat_i[4] ;
+ wire \wbd_glbl_dat_i[5] ;
+ wire \wbd_glbl_dat_i[6] ;
+ wire \wbd_glbl_dat_i[7] ;
+ wire \wbd_glbl_dat_i[8] ;
+ wire \wbd_glbl_dat_i[9] ;
+ wire \wbd_glbl_dat_o[0] ;
+ wire \wbd_glbl_dat_o[10] ;
+ wire \wbd_glbl_dat_o[11] ;
+ wire \wbd_glbl_dat_o[12] ;
+ wire \wbd_glbl_dat_o[13] ;
+ wire \wbd_glbl_dat_o[14] ;
+ wire \wbd_glbl_dat_o[15] ;
+ wire \wbd_glbl_dat_o[16] ;
+ wire \wbd_glbl_dat_o[17] ;
+ wire \wbd_glbl_dat_o[18] ;
+ wire \wbd_glbl_dat_o[19] ;
+ wire \wbd_glbl_dat_o[1] ;
+ wire \wbd_glbl_dat_o[20] ;
+ wire \wbd_glbl_dat_o[21] ;
+ wire \wbd_glbl_dat_o[22] ;
+ wire \wbd_glbl_dat_o[23] ;
+ wire \wbd_glbl_dat_o[24] ;
+ wire \wbd_glbl_dat_o[25] ;
+ wire \wbd_glbl_dat_o[26] ;
+ wire \wbd_glbl_dat_o[27] ;
+ wire \wbd_glbl_dat_o[28] ;
+ wire \wbd_glbl_dat_o[29] ;
+ wire \wbd_glbl_dat_o[2] ;
+ wire \wbd_glbl_dat_o[30] ;
+ wire \wbd_glbl_dat_o[31] ;
+ wire \wbd_glbl_dat_o[3] ;
+ wire \wbd_glbl_dat_o[4] ;
+ wire \wbd_glbl_dat_o[5] ;
+ wire \wbd_glbl_dat_o[6] ;
+ wire \wbd_glbl_dat_o[7] ;
+ wire \wbd_glbl_dat_o[8] ;
+ wire \wbd_glbl_dat_o[9] ;
+ wire \wbd_glbl_sel_o[0] ;
+ wire \wbd_glbl_sel_o[1] ;
+ wire \wbd_glbl_sel_o[2] ;
+ wire \wbd_glbl_sel_o[3] ;
+ wire wbd_glbl_stb_o;
+ wire wbd_glbl_we_o;
+ wire wbd_int_ack_o;
+ wire \wbd_int_adr_i[0] ;
+ wire \wbd_int_adr_i[10] ;
+ wire \wbd_int_adr_i[11] ;
+ wire \wbd_int_adr_i[12] ;
+ wire \wbd_int_adr_i[13] ;
+ wire \wbd_int_adr_i[14] ;
+ wire \wbd_int_adr_i[15] ;
+ wire \wbd_int_adr_i[16] ;
+ wire \wbd_int_adr_i[17] ;
+ wire \wbd_int_adr_i[18] ;
+ wire \wbd_int_adr_i[19] ;
+ wire \wbd_int_adr_i[1] ;
+ wire \wbd_int_adr_i[20] ;
+ wire \wbd_int_adr_i[21] ;
+ wire \wbd_int_adr_i[22] ;
+ wire \wbd_int_adr_i[23] ;
+ wire \wbd_int_adr_i[24] ;
+ wire \wbd_int_adr_i[25] ;
+ wire \wbd_int_adr_i[26] ;
+ wire \wbd_int_adr_i[27] ;
+ wire \wbd_int_adr_i[28] ;
+ wire \wbd_int_adr_i[29] ;
+ wire \wbd_int_adr_i[2] ;
+ wire \wbd_int_adr_i[30] ;
+ wire \wbd_int_adr_i[31] ;
+ wire \wbd_int_adr_i[3] ;
+ wire \wbd_int_adr_i[4] ;
+ wire \wbd_int_adr_i[5] ;
+ wire \wbd_int_adr_i[6] ;
+ wire \wbd_int_adr_i[7] ;
+ wire \wbd_int_adr_i[8] ;
+ wire \wbd_int_adr_i[9] ;
+ wire wbd_int_cyc_i;
+ wire \wbd_int_dat_i[0] ;
+ wire \wbd_int_dat_i[10] ;
+ wire \wbd_int_dat_i[11] ;
+ wire \wbd_int_dat_i[12] ;
+ wire \wbd_int_dat_i[13] ;
+ wire \wbd_int_dat_i[14] ;
+ wire \wbd_int_dat_i[15] ;
+ wire \wbd_int_dat_i[16] ;
+ wire \wbd_int_dat_i[17] ;
+ wire \wbd_int_dat_i[18] ;
+ wire \wbd_int_dat_i[19] ;
+ wire \wbd_int_dat_i[1] ;
+ wire \wbd_int_dat_i[20] ;
+ wire \wbd_int_dat_i[21] ;
+ wire \wbd_int_dat_i[22] ;
+ wire \wbd_int_dat_i[23] ;
+ wire \wbd_int_dat_i[24] ;
+ wire \wbd_int_dat_i[25] ;
+ wire \wbd_int_dat_i[26] ;
+ wire \wbd_int_dat_i[27] ;
+ wire \wbd_int_dat_i[28] ;
+ wire \wbd_int_dat_i[29] ;
+ wire \wbd_int_dat_i[2] ;
+ wire \wbd_int_dat_i[30] ;
+ wire \wbd_int_dat_i[31] ;
+ wire \wbd_int_dat_i[3] ;
+ wire \wbd_int_dat_i[4] ;
+ wire \wbd_int_dat_i[5] ;
+ wire \wbd_int_dat_i[6] ;
+ wire \wbd_int_dat_i[7] ;
+ wire \wbd_int_dat_i[8] ;
+ wire \wbd_int_dat_i[9] ;
+ wire \wbd_int_dat_o[0] ;
+ wire \wbd_int_dat_o[10] ;
+ wire \wbd_int_dat_o[11] ;
+ wire \wbd_int_dat_o[12] ;
+ wire \wbd_int_dat_o[13] ;
+ wire \wbd_int_dat_o[14] ;
+ wire \wbd_int_dat_o[15] ;
+ wire \wbd_int_dat_o[16] ;
+ wire \wbd_int_dat_o[17] ;
+ wire \wbd_int_dat_o[18] ;
+ wire \wbd_int_dat_o[19] ;
+ wire \wbd_int_dat_o[1] ;
+ wire \wbd_int_dat_o[20] ;
+ wire \wbd_int_dat_o[21] ;
+ wire \wbd_int_dat_o[22] ;
+ wire \wbd_int_dat_o[23] ;
+ wire \wbd_int_dat_o[24] ;
+ wire \wbd_int_dat_o[25] ;
+ wire \wbd_int_dat_o[26] ;
+ wire \wbd_int_dat_o[27] ;
+ wire \wbd_int_dat_o[28] ;
+ wire \wbd_int_dat_o[29] ;
+ wire \wbd_int_dat_o[2] ;
+ wire \wbd_int_dat_o[30] ;
+ wire \wbd_int_dat_o[31] ;
+ wire \wbd_int_dat_o[3] ;
+ wire \wbd_int_dat_o[4] ;
+ wire \wbd_int_dat_o[5] ;
+ wire \wbd_int_dat_o[6] ;
+ wire \wbd_int_dat_o[7] ;
+ wire \wbd_int_dat_o[8] ;
+ wire \wbd_int_dat_o[9] ;
+ wire wbd_int_err_o;
+ wire \wbd_int_sel_i[0] ;
+ wire \wbd_int_sel_i[1] ;
+ wire \wbd_int_sel_i[2] ;
+ wire \wbd_int_sel_i[3] ;
+ wire wbd_int_stb_i;
+ wire wbd_int_we_i;
+ wire wbd_pll_rst_n;
+ wire wbd_spim_ack_i;
+ wire \wbd_spim_adr_o[0] ;
+ wire \wbd_spim_adr_o[10] ;
+ wire \wbd_spim_adr_o[11] ;
+ wire \wbd_spim_adr_o[12] ;
+ wire \wbd_spim_adr_o[13] ;
+ wire \wbd_spim_adr_o[14] ;
+ wire \wbd_spim_adr_o[15] ;
+ wire \wbd_spim_adr_o[16] ;
+ wire \wbd_spim_adr_o[17] ;
+ wire \wbd_spim_adr_o[18] ;
+ wire \wbd_spim_adr_o[19] ;
+ wire \wbd_spim_adr_o[1] ;
+ wire \wbd_spim_adr_o[20] ;
+ wire \wbd_spim_adr_o[21] ;
+ wire \wbd_spim_adr_o[22] ;
+ wire \wbd_spim_adr_o[23] ;
+ wire \wbd_spim_adr_o[24] ;
+ wire \wbd_spim_adr_o[25] ;
+ wire \wbd_spim_adr_o[26] ;
+ wire \wbd_spim_adr_o[27] ;
+ wire \wbd_spim_adr_o[28] ;
+ wire \wbd_spim_adr_o[29] ;
+ wire \wbd_spim_adr_o[2] ;
+ wire \wbd_spim_adr_o[30] ;
+ wire \wbd_spim_adr_o[31] ;
+ wire \wbd_spim_adr_o[3] ;
+ wire \wbd_spim_adr_o[4] ;
+ wire \wbd_spim_adr_o[5] ;
+ wire \wbd_spim_adr_o[6] ;
+ wire \wbd_spim_adr_o[7] ;
+ wire \wbd_spim_adr_o[8] ;
+ wire \wbd_spim_adr_o[9] ;
+ wire \wbd_spim_bl_o[0] ;
+ wire \wbd_spim_bl_o[1] ;
+ wire \wbd_spim_bl_o[2] ;
+ wire \wbd_spim_bl_o[3] ;
+ wire \wbd_spim_bl_o[4] ;
+ wire \wbd_spim_bl_o[5] ;
+ wire \wbd_spim_bl_o[6] ;
+ wire \wbd_spim_bl_o[7] ;
+ wire \wbd_spim_bl_o[8] ;
+ wire \wbd_spim_bl_o[9] ;
+ wire wbd_spim_bry_o;
+ wire wbd_spim_cyc_o;
+ wire \wbd_spim_dat_i[0] ;
+ wire \wbd_spim_dat_i[10] ;
+ wire \wbd_spim_dat_i[11] ;
+ wire \wbd_spim_dat_i[12] ;
+ wire \wbd_spim_dat_i[13] ;
+ wire \wbd_spim_dat_i[14] ;
+ wire \wbd_spim_dat_i[15] ;
+ wire \wbd_spim_dat_i[16] ;
+ wire \wbd_spim_dat_i[17] ;
+ wire \wbd_spim_dat_i[18] ;
+ wire \wbd_spim_dat_i[19] ;
+ wire \wbd_spim_dat_i[1] ;
+ wire \wbd_spim_dat_i[20] ;
+ wire \wbd_spim_dat_i[21] ;
+ wire \wbd_spim_dat_i[22] ;
+ wire \wbd_spim_dat_i[23] ;
+ wire \wbd_spim_dat_i[24] ;
+ wire \wbd_spim_dat_i[25] ;
+ wire \wbd_spim_dat_i[26] ;
+ wire \wbd_spim_dat_i[27] ;
+ wire \wbd_spim_dat_i[28] ;
+ wire \wbd_spim_dat_i[29] ;
+ wire \wbd_spim_dat_i[2] ;
+ wire \wbd_spim_dat_i[30] ;
+ wire \wbd_spim_dat_i[31] ;
+ wire \wbd_spim_dat_i[3] ;
+ wire \wbd_spim_dat_i[4] ;
+ wire \wbd_spim_dat_i[5] ;
+ wire \wbd_spim_dat_i[6] ;
+ wire \wbd_spim_dat_i[7] ;
+ wire \wbd_spim_dat_i[8] ;
+ wire \wbd_spim_dat_i[9] ;
+ wire \wbd_spim_dat_o[0] ;
+ wire \wbd_spim_dat_o[10] ;
+ wire \wbd_spim_dat_o[11] ;
+ wire \wbd_spim_dat_o[12] ;
+ wire \wbd_spim_dat_o[13] ;
+ wire \wbd_spim_dat_o[14] ;
+ wire \wbd_spim_dat_o[15] ;
+ wire \wbd_spim_dat_o[16] ;
+ wire \wbd_spim_dat_o[17] ;
+ wire \wbd_spim_dat_o[18] ;
+ wire \wbd_spim_dat_o[19] ;
+ wire \wbd_spim_dat_o[1] ;
+ wire \wbd_spim_dat_o[20] ;
+ wire \wbd_spim_dat_o[21] ;
+ wire \wbd_spim_dat_o[22] ;
+ wire \wbd_spim_dat_o[23] ;
+ wire \wbd_spim_dat_o[24] ;
+ wire \wbd_spim_dat_o[25] ;
+ wire \wbd_spim_dat_o[26] ;
+ wire \wbd_spim_dat_o[27] ;
+ wire \wbd_spim_dat_o[28] ;
+ wire \wbd_spim_dat_o[29] ;
+ wire \wbd_spim_dat_o[2] ;
+ wire \wbd_spim_dat_o[30] ;
+ wire \wbd_spim_dat_o[31] ;
+ wire \wbd_spim_dat_o[3] ;
+ wire \wbd_spim_dat_o[4] ;
+ wire \wbd_spim_dat_o[5] ;
+ wire \wbd_spim_dat_o[6] ;
+ wire \wbd_spim_dat_o[7] ;
+ wire \wbd_spim_dat_o[8] ;
+ wire \wbd_spim_dat_o[9] ;
+ wire wbd_spim_err_i;
+ wire wbd_spim_lack_i;
+ wire \wbd_spim_sel_o[0] ;
+ wire \wbd_spim_sel_o[1] ;
+ wire \wbd_spim_sel_o[2] ;
+ wire \wbd_spim_sel_o[3] ;
+ wire wbd_spim_stb_o;
+ wire wbd_spim_we_o;
+ wire wbd_uart_ack_i;
+ wire \wbd_uart_adr_o[0] ;
+ wire \wbd_uart_adr_o[1] ;
+ wire \wbd_uart_adr_o[2] ;
+ wire \wbd_uart_adr_o[3] ;
+ wire \wbd_uart_adr_o[4] ;
+ wire \wbd_uart_adr_o[5] ;
+ wire \wbd_uart_adr_o[6] ;
+ wire \wbd_uart_adr_o[7] ;
+ wire \wbd_uart_adr_o[8] ;
+ wire wbd_uart_cyc_o;
+ wire \wbd_uart_dat_i[0] ;
+ wire \wbd_uart_dat_i[10] ;
+ wire \wbd_uart_dat_i[11] ;
+ wire \wbd_uart_dat_i[12] ;
+ wire \wbd_uart_dat_i[13] ;
+ wire \wbd_uart_dat_i[14] ;
+ wire \wbd_uart_dat_i[15] ;
+ wire \wbd_uart_dat_i[16] ;
+ wire \wbd_uart_dat_i[17] ;
+ wire \wbd_uart_dat_i[18] ;
+ wire \wbd_uart_dat_i[19] ;
+ wire \wbd_uart_dat_i[1] ;
+ wire \wbd_uart_dat_i[20] ;
+ wire \wbd_uart_dat_i[21] ;
+ wire \wbd_uart_dat_i[22] ;
+ wire \wbd_uart_dat_i[23] ;
+ wire \wbd_uart_dat_i[24] ;
+ wire \wbd_uart_dat_i[25] ;
+ wire \wbd_uart_dat_i[26] ;
+ wire \wbd_uart_dat_i[27] ;
+ wire \wbd_uart_dat_i[28] ;
+ wire \wbd_uart_dat_i[29] ;
+ wire \wbd_uart_dat_i[2] ;
+ wire \wbd_uart_dat_i[30] ;
+ wire \wbd_uart_dat_i[31] ;
+ wire \wbd_uart_dat_i[3] ;
+ wire \wbd_uart_dat_i[4] ;
+ wire \wbd_uart_dat_i[5] ;
+ wire \wbd_uart_dat_i[6] ;
+ wire \wbd_uart_dat_i[7] ;
+ wire \wbd_uart_dat_i[8] ;
+ wire \wbd_uart_dat_i[9] ;
+ wire \wbd_uart_dat_o[0] ;
+ wire \wbd_uart_dat_o[10] ;
+ wire \wbd_uart_dat_o[11] ;
+ wire \wbd_uart_dat_o[12] ;
+ wire \wbd_uart_dat_o[13] ;
+ wire \wbd_uart_dat_o[14] ;
+ wire \wbd_uart_dat_o[15] ;
+ wire \wbd_uart_dat_o[16] ;
+ wire \wbd_uart_dat_o[17] ;
+ wire \wbd_uart_dat_o[18] ;
+ wire \wbd_uart_dat_o[19] ;
+ wire \wbd_uart_dat_o[1] ;
+ wire \wbd_uart_dat_o[20] ;
+ wire \wbd_uart_dat_o[21] ;
+ wire \wbd_uart_dat_o[22] ;
+ wire \wbd_uart_dat_o[23] ;
+ wire \wbd_uart_dat_o[24] ;
+ wire \wbd_uart_dat_o[25] ;
+ wire \wbd_uart_dat_o[26] ;
+ wire \wbd_uart_dat_o[27] ;
+ wire \wbd_uart_dat_o[28] ;
+ wire \wbd_uart_dat_o[29] ;
+ wire \wbd_uart_dat_o[2] ;
+ wire \wbd_uart_dat_o[30] ;
+ wire \wbd_uart_dat_o[31] ;
+ wire \wbd_uart_dat_o[3] ;
+ wire \wbd_uart_dat_o[4] ;
+ wire \wbd_uart_dat_o[5] ;
+ wire \wbd_uart_dat_o[6] ;
+ wire \wbd_uart_dat_o[7] ;
+ wire \wbd_uart_dat_o[8] ;
+ wire \wbd_uart_dat_o[9] ;
+ wire \wbd_uart_sel_o[0] ;
+ wire \wbd_uart_sel_o[1] ;
+ wire \wbd_uart_sel_o[2] ;
+ wire \wbd_uart_sel_o[3] ;
+ wire wbd_uart_stb_o;
+ wire wbd_uart_we_o;
+
+ sky130_sram_2kbyte_1rw1r_32x512_8 u_dcache_2kb (.csb0(\u_riscv_top.dcache_mem_csb0 ),
+ .csb1(\u_riscv_top.dcache_mem_csb1 ),
+ .web0(\u_riscv_top.dcache_mem_web0 ),
+ .clk0(\u_riscv_top.dcache_mem_clk0 ),
+ .clk1(\u_riscv_top.dcache_mem_clk1 ),
+ .vccd1(vccd1),
+ .vssd1(vssd1),
+ .addr0({\u_riscv_top.dcache_mem_addr0[8] ,
+ \u_riscv_top.dcache_mem_addr0[7] ,
+ \u_riscv_top.dcache_mem_addr0[6] ,
+ \u_riscv_top.dcache_mem_addr0[5] ,
+ \u_riscv_top.dcache_mem_addr0[4] ,
+ \u_riscv_top.dcache_mem_addr0[3] ,
+ \u_riscv_top.dcache_mem_addr0[2] ,
+ \u_riscv_top.dcache_mem_addr0[1] ,
+ \u_riscv_top.dcache_mem_addr0[0] }),
+ .addr1({\u_riscv_top.dcache_mem_addr1[8] ,
+ \u_riscv_top.dcache_mem_addr1[7] ,
+ \u_riscv_top.dcache_mem_addr1[6] ,
+ \u_riscv_top.dcache_mem_addr1[5] ,
+ \u_riscv_top.dcache_mem_addr1[4] ,
+ \u_riscv_top.dcache_mem_addr1[3] ,
+ \u_riscv_top.dcache_mem_addr1[2] ,
+ \u_riscv_top.dcache_mem_addr1[1] ,
+ \u_riscv_top.dcache_mem_addr1[0] }),
+ .din0({\u_riscv_top.dcache_mem_din0[31] ,
+ \u_riscv_top.dcache_mem_din0[30] ,
+ \u_riscv_top.dcache_mem_din0[29] ,
+ \u_riscv_top.dcache_mem_din0[28] ,
+ \u_riscv_top.dcache_mem_din0[27] ,
+ \u_riscv_top.dcache_mem_din0[26] ,
+ \u_riscv_top.dcache_mem_din0[25] ,
+ \u_riscv_top.dcache_mem_din0[24] ,
+ \u_riscv_top.dcache_mem_din0[23] ,
+ \u_riscv_top.dcache_mem_din0[22] ,
+ \u_riscv_top.dcache_mem_din0[21] ,
+ \u_riscv_top.dcache_mem_din0[20] ,
+ \u_riscv_top.dcache_mem_din0[19] ,
+ \u_riscv_top.dcache_mem_din0[18] ,
+ \u_riscv_top.dcache_mem_din0[17] ,
+ \u_riscv_top.dcache_mem_din0[16] ,
+ \u_riscv_top.dcache_mem_din0[15] ,
+ \u_riscv_top.dcache_mem_din0[14] ,
+ \u_riscv_top.dcache_mem_din0[13] ,
+ \u_riscv_top.dcache_mem_din0[12] ,
+ \u_riscv_top.dcache_mem_din0[11] ,
+ \u_riscv_top.dcache_mem_din0[10] ,
+ \u_riscv_top.dcache_mem_din0[9] ,
+ \u_riscv_top.dcache_mem_din0[8] ,
+ \u_riscv_top.dcache_mem_din0[7] ,
+ \u_riscv_top.dcache_mem_din0[6] ,
+ \u_riscv_top.dcache_mem_din0[5] ,
+ \u_riscv_top.dcache_mem_din0[4] ,
+ \u_riscv_top.dcache_mem_din0[3] ,
+ \u_riscv_top.dcache_mem_din0[2] ,
+ \u_riscv_top.dcache_mem_din0[1] ,
+ \u_riscv_top.dcache_mem_din0[0] }),
+ .dout0({\u_riscv_top.dcache_mem_dout0[31] ,
+ \u_riscv_top.dcache_mem_dout0[30] ,
+ \u_riscv_top.dcache_mem_dout0[29] ,
+ \u_riscv_top.dcache_mem_dout0[28] ,
+ \u_riscv_top.dcache_mem_dout0[27] ,
+ \u_riscv_top.dcache_mem_dout0[26] ,
+ \u_riscv_top.dcache_mem_dout0[25] ,
+ \u_riscv_top.dcache_mem_dout0[24] ,
+ \u_riscv_top.dcache_mem_dout0[23] ,
+ \u_riscv_top.dcache_mem_dout0[22] ,
+ \u_riscv_top.dcache_mem_dout0[21] ,
+ \u_riscv_top.dcache_mem_dout0[20] ,
+ \u_riscv_top.dcache_mem_dout0[19] ,
+ \u_riscv_top.dcache_mem_dout0[18] ,
+ \u_riscv_top.dcache_mem_dout0[17] ,
+ \u_riscv_top.dcache_mem_dout0[16] ,
+ \u_riscv_top.dcache_mem_dout0[15] ,
+ \u_riscv_top.dcache_mem_dout0[14] ,
+ \u_riscv_top.dcache_mem_dout0[13] ,
+ \u_riscv_top.dcache_mem_dout0[12] ,
+ \u_riscv_top.dcache_mem_dout0[11] ,
+ \u_riscv_top.dcache_mem_dout0[10] ,
+ \u_riscv_top.dcache_mem_dout0[9] ,
+ \u_riscv_top.dcache_mem_dout0[8] ,
+ \u_riscv_top.dcache_mem_dout0[7] ,
+ \u_riscv_top.dcache_mem_dout0[6] ,
+ \u_riscv_top.dcache_mem_dout0[5] ,
+ \u_riscv_top.dcache_mem_dout0[4] ,
+ \u_riscv_top.dcache_mem_dout0[3] ,
+ \u_riscv_top.dcache_mem_dout0[2] ,
+ \u_riscv_top.dcache_mem_dout0[1] ,
+ \u_riscv_top.dcache_mem_dout0[0] }),
+ .dout1({\u_riscv_top.dcache_mem_dout1[31] ,
+ \u_riscv_top.dcache_mem_dout1[30] ,
+ \u_riscv_top.dcache_mem_dout1[29] ,
+ \u_riscv_top.dcache_mem_dout1[28] ,
+ \u_riscv_top.dcache_mem_dout1[27] ,
+ \u_riscv_top.dcache_mem_dout1[26] ,
+ \u_riscv_top.dcache_mem_dout1[25] ,
+ \u_riscv_top.dcache_mem_dout1[24] ,
+ \u_riscv_top.dcache_mem_dout1[23] ,
+ \u_riscv_top.dcache_mem_dout1[22] ,
+ \u_riscv_top.dcache_mem_dout1[21] ,
+ \u_riscv_top.dcache_mem_dout1[20] ,
+ \u_riscv_top.dcache_mem_dout1[19] ,
+ \u_riscv_top.dcache_mem_dout1[18] ,
+ \u_riscv_top.dcache_mem_dout1[17] ,
+ \u_riscv_top.dcache_mem_dout1[16] ,
+ \u_riscv_top.dcache_mem_dout1[15] ,
+ \u_riscv_top.dcache_mem_dout1[14] ,
+ \u_riscv_top.dcache_mem_dout1[13] ,
+ \u_riscv_top.dcache_mem_dout1[12] ,
+ \u_riscv_top.dcache_mem_dout1[11] ,
+ \u_riscv_top.dcache_mem_dout1[10] ,
+ \u_riscv_top.dcache_mem_dout1[9] ,
+ \u_riscv_top.dcache_mem_dout1[8] ,
+ \u_riscv_top.dcache_mem_dout1[7] ,
+ \u_riscv_top.dcache_mem_dout1[6] ,
+ \u_riscv_top.dcache_mem_dout1[5] ,
+ \u_riscv_top.dcache_mem_dout1[4] ,
+ \u_riscv_top.dcache_mem_dout1[3] ,
+ \u_riscv_top.dcache_mem_dout1[2] ,
+ \u_riscv_top.dcache_mem_dout1[1] ,
+ \u_riscv_top.dcache_mem_dout1[0] }),
+ .wmask0({\u_riscv_top.dcache_mem_wmask0[3] ,
+ \u_riscv_top.dcache_mem_wmask0[2] ,
+ \u_riscv_top.dcache_mem_wmask0[1] ,
+ \u_riscv_top.dcache_mem_wmask0[0] }));
+ sky130_sram_2kbyte_1rw1r_32x512_8 u_icache_2kb (.csb0(\u_riscv_top.icache_mem_csb0 ),
+ .csb1(\u_riscv_top.icache_mem_csb1 ),
+ .web0(\u_riscv_top.icache_mem_web0 ),
+ .clk0(\u_riscv_top.icache_mem_clk0 ),
+ .clk1(\u_riscv_top.icache_mem_clk1 ),
+ .vccd1(vccd1),
+ .vssd1(vssd1),
+ .addr0({\u_riscv_top.icache_mem_addr0[8] ,
+ \u_riscv_top.icache_mem_addr0[7] ,
+ \u_riscv_top.icache_mem_addr0[6] ,
+ \u_riscv_top.icache_mem_addr0[5] ,
+ \u_riscv_top.icache_mem_addr0[4] ,
+ \u_riscv_top.icache_mem_addr0[3] ,
+ \u_riscv_top.icache_mem_addr0[2] ,
+ \u_riscv_top.icache_mem_addr0[1] ,
+ \u_riscv_top.icache_mem_addr0[0] }),
+ .addr1({\u_riscv_top.icache_mem_addr1[8] ,
+ \u_riscv_top.icache_mem_addr1[7] ,
+ \u_riscv_top.icache_mem_addr1[6] ,
+ \u_riscv_top.icache_mem_addr1[5] ,
+ \u_riscv_top.icache_mem_addr1[4] ,
+ \u_riscv_top.icache_mem_addr1[3] ,
+ \u_riscv_top.icache_mem_addr1[2] ,
+ \u_riscv_top.icache_mem_addr1[1] ,
+ \u_riscv_top.icache_mem_addr1[0] }),
+ .din0({\u_riscv_top.icache_mem_din0[31] ,
+ \u_riscv_top.icache_mem_din0[30] ,
+ \u_riscv_top.icache_mem_din0[29] ,
+ \u_riscv_top.icache_mem_din0[28] ,
+ \u_riscv_top.icache_mem_din0[27] ,
+ \u_riscv_top.icache_mem_din0[26] ,
+ \u_riscv_top.icache_mem_din0[25] ,
+ \u_riscv_top.icache_mem_din0[24] ,
+ \u_riscv_top.icache_mem_din0[23] ,
+ \u_riscv_top.icache_mem_din0[22] ,
+ \u_riscv_top.icache_mem_din0[21] ,
+ \u_riscv_top.icache_mem_din0[20] ,
+ \u_riscv_top.icache_mem_din0[19] ,
+ \u_riscv_top.icache_mem_din0[18] ,
+ \u_riscv_top.icache_mem_din0[17] ,
+ \u_riscv_top.icache_mem_din0[16] ,
+ \u_riscv_top.icache_mem_din0[15] ,
+ \u_riscv_top.icache_mem_din0[14] ,
+ \u_riscv_top.icache_mem_din0[13] ,
+ \u_riscv_top.icache_mem_din0[12] ,
+ \u_riscv_top.icache_mem_din0[11] ,
+ \u_riscv_top.icache_mem_din0[10] ,
+ \u_riscv_top.icache_mem_din0[9] ,
+ \u_riscv_top.icache_mem_din0[8] ,
+ \u_riscv_top.icache_mem_din0[7] ,
+ \u_riscv_top.icache_mem_din0[6] ,
+ \u_riscv_top.icache_mem_din0[5] ,
+ \u_riscv_top.icache_mem_din0[4] ,
+ \u_riscv_top.icache_mem_din0[3] ,
+ \u_riscv_top.icache_mem_din0[2] ,
+ \u_riscv_top.icache_mem_din0[1] ,
+ \u_riscv_top.icache_mem_din0[0] }),
+ .dout0({_NC1,
+ _NC2,
+ _NC3,
+ _NC4,
+ _NC5,
+ _NC6,
+ _NC7,
+ _NC8,
+ _NC9,
+ _NC10,
+ _NC11,
+ _NC12,
+ _NC13,
+ _NC14,
+ _NC15,
+ _NC16,
+ _NC17,
+ _NC18,
+ _NC19,
+ _NC20,
+ _NC21,
+ _NC22,
+ _NC23,
+ _NC24,
+ _NC25,
+ _NC26,
+ _NC27,
+ _NC28,
+ _NC29,
+ _NC30,
+ _NC31,
+ _NC32}),
+ .dout1({\u_riscv_top.icache_mem_dout1[31] ,
+ \u_riscv_top.icache_mem_dout1[30] ,
+ \u_riscv_top.icache_mem_dout1[29] ,
+ \u_riscv_top.icache_mem_dout1[28] ,
+ \u_riscv_top.icache_mem_dout1[27] ,
+ \u_riscv_top.icache_mem_dout1[26] ,
+ \u_riscv_top.icache_mem_dout1[25] ,
+ \u_riscv_top.icache_mem_dout1[24] ,
+ \u_riscv_top.icache_mem_dout1[23] ,
+ \u_riscv_top.icache_mem_dout1[22] ,
+ \u_riscv_top.icache_mem_dout1[21] ,
+ \u_riscv_top.icache_mem_dout1[20] ,
+ \u_riscv_top.icache_mem_dout1[19] ,
+ \u_riscv_top.icache_mem_dout1[18] ,
+ \u_riscv_top.icache_mem_dout1[17] ,
+ \u_riscv_top.icache_mem_dout1[16] ,
+ \u_riscv_top.icache_mem_dout1[15] ,
+ \u_riscv_top.icache_mem_dout1[14] ,
+ \u_riscv_top.icache_mem_dout1[13] ,
+ \u_riscv_top.icache_mem_dout1[12] ,
+ \u_riscv_top.icache_mem_dout1[11] ,
+ \u_riscv_top.icache_mem_dout1[10] ,
+ \u_riscv_top.icache_mem_dout1[9] ,
+ \u_riscv_top.icache_mem_dout1[8] ,
+ \u_riscv_top.icache_mem_dout1[7] ,
+ \u_riscv_top.icache_mem_dout1[6] ,
+ \u_riscv_top.icache_mem_dout1[5] ,
+ \u_riscv_top.icache_mem_dout1[4] ,
+ \u_riscv_top.icache_mem_dout1[3] ,
+ \u_riscv_top.icache_mem_dout1[2] ,
+ \u_riscv_top.icache_mem_dout1[1] ,
+ \u_riscv_top.icache_mem_dout1[0] }),
+ .wmask0({\u_riscv_top.icache_mem_wmask0[3] ,
+ \u_riscv_top.icache_mem_wmask0[2] ,
+ \u_riscv_top.icache_mem_wmask0[1] ,
+ \u_riscv_top.icache_mem_wmask0[0] }));
+ wb_interconnect u_intercon (.clk_i(wbd_clk_wi_skew),
+ .m0_wbd_ack_o(wbd_int_ack_o),
+ .m0_wbd_cyc_i(wbd_int_cyc_i),
+ .m0_wbd_err_o(wbd_int_err_o),
+ .m0_wbd_stb_i(wbd_int_stb_i),
+ .m0_wbd_we_i(wbd_int_we_i),
+ .m1_wbd_ack_o(\u_riscv_top.wbd_dmem_ack_i ),
+ .m1_wbd_cyc_i(\u_riscv_top.wbd_dmem_stb_o ),
+ .m1_wbd_err_o(\u_riscv_top.wbd_dmem_err_i ),
+ .m1_wbd_stb_i(\u_riscv_top.wbd_dmem_stb_o ),
+ .m1_wbd_we_i(\u_riscv_top.wbd_dmem_we_o ),
+ .m2_wbd_ack_o(\u_riscv_top.wb_dcache_ack_i ),
+ .m2_wbd_bry_i(\u_riscv_top.wb_dcache_bry_o ),
+ .m2_wbd_cyc_i(\u_riscv_top.wb_dcache_stb_o ),
+ .m2_wbd_err_o(\u_riscv_top.wb_dcache_err_i ),
+ .m2_wbd_lack_o(\u_riscv_top.wb_dcache_lack_i ),
+ .m2_wbd_stb_i(\u_riscv_top.wb_dcache_stb_o ),
+ .m2_wbd_we_i(\u_riscv_top.wb_dcache_we_o ),
+ .m3_wbd_ack_o(\u_riscv_top.wb_icache_ack_i ),
+ .m3_wbd_bry_i(\u_riscv_top.wb_icache_bry_o ),
+ .m3_wbd_cyc_i(\u_riscv_top.wb_icache_stb_o ),
+ .m3_wbd_err_o(\u_riscv_top.wb_icache_err_i ),
+ .m3_wbd_lack_o(\u_riscv_top.wb_icache_lack_i ),
+ .m3_wbd_stb_i(\u_riscv_top.wb_icache_stb_o ),
+ .m3_wbd_we_i(\u_riscv_top.wb_icache_we_o ),
+ .rst_n(\u_riscv_top.pwrup_rst_n ),
+ .s0_wbd_ack_i(wbd_spim_ack_i),
+ .s0_wbd_bry_o(wbd_spim_bry_o),
+ .s0_wbd_cyc_o(wbd_spim_cyc_o),
+ .s0_wbd_lack_i(wbd_spim_lack_i),
+ .s0_wbd_stb_o(wbd_spim_stb_o),
+ .s0_wbd_we_o(wbd_spim_we_o),
+ .s1_wbd_ack_i(wbd_uart_ack_i),
+ .s1_wbd_cyc_o(wbd_uart_cyc_o),
+ .s1_wbd_stb_o(wbd_uart_stb_o),
+ .s1_wbd_we_o(wbd_uart_we_o),
+ .s2_wbd_ack_i(wbd_glbl_ack_i),
+ .s2_wbd_cyc_o(wbd_glbl_cyc_o),
+ .s2_wbd_stb_o(wbd_glbl_stb_o),
+ .s2_wbd_we_o(wbd_glbl_we_o),
+ .vccd1(vccd1),
+ .vssd1(vssd1),
+ .wbd_clk_int(wbd_clk_int),
+ .wbd_clk_wi(wbd_clk_wi_skew),
+ .cfg_cska_wi({\cfg_clk_ctrl1[3] ,
+ \cfg_clk_ctrl1[2] ,
+ \cfg_clk_ctrl1[1] ,
+ \cfg_clk_ctrl1[0] }),
+ .ch_clk_in({wbd_clk_int,
+ wbd_clk_int,
+ wbd_clk_int,
+ wbd_clk_int}),
+ .ch_clk_out({wbd_clk_pinmux_rp,
+ wbd_clk_uart_rp,
+ wbd_clk_qspi_rp,
+ \u_riscv_top.wbd_clk_int }),
+ .ch_data_in({soft_irq,
+ \irq_lines[15] ,
+ \irq_lines[14] ,
+ \irq_lines[13] ,
+ \irq_lines[12] ,
+ \irq_lines[11] ,
+ \irq_lines[10] ,
+ \irq_lines[9] ,
+ \irq_lines[8] ,
+ \irq_lines[7] ,
+ \irq_lines[6] ,
+ \irq_lines[5] ,
+ \irq_lines[4] ,
+ \irq_lines[3] ,
+ \irq_lines[2] ,
+ \irq_lines[1] ,
+ \irq_lines[0] ,
+ \cfg_clk_ctrl1[27] ,
+ \cfg_clk_ctrl1[26] ,
+ \cfg_clk_ctrl1[25] ,
+ \cfg_clk_ctrl1[24] ,
+ \cfg_clk_ctrl1[23] ,
+ \cfg_clk_ctrl1[22] ,
+ \cfg_clk_ctrl1[21] ,
+ \cfg_clk_ctrl1[20] ,
+ \cfg_clk_ctrl1[19] ,
+ \cfg_clk_ctrl1[18] ,
+ \cfg_clk_ctrl1[17] ,
+ \cfg_clk_ctrl1[16] ,
+ \cfg_clk_ctrl1[15] ,
+ \cfg_clk_ctrl1[14] ,
+ \cfg_clk_ctrl1[13] ,
+ \cfg_clk_ctrl1[12] ,
+ \cfg_clk_ctrl1[11] ,
+ \cfg_clk_ctrl1[10] ,
+ \cfg_clk_ctrl1[9] ,
+ \cfg_clk_ctrl1[8] }),
+ .ch_data_out({\u_riscv_top.soft_irq ,
+ \u_riscv_top.irq_lines[15] ,
+ \u_riscv_top.irq_lines[14] ,
+ \u_riscv_top.irq_lines[13] ,
+ \u_riscv_top.irq_lines[12] ,
+ \u_riscv_top.irq_lines[11] ,
+ \u_riscv_top.irq_lines[10] ,
+ \u_riscv_top.irq_lines[9] ,
+ \u_riscv_top.irq_lines[8] ,
+ \u_riscv_top.irq_lines[7] ,
+ \u_riscv_top.irq_lines[6] ,
+ \u_riscv_top.irq_lines[5] ,
+ \u_riscv_top.irq_lines[4] ,
+ \u_riscv_top.irq_lines[3] ,
+ \u_riscv_top.irq_lines[2] ,
+ \u_riscv_top.irq_lines[1] ,
+ \u_riscv_top.irq_lines[0] ,
+ \cfg_cska_qspi_co_rp[3] ,
+ \cfg_cska_qspi_co_rp[2] ,
+ \cfg_cska_qspi_co_rp[1] ,
+ \cfg_cska_qspi_co_rp[0] ,
+ \cfg_cska_pinmux_rp[3] ,
+ \cfg_cska_pinmux_rp[2] ,
+ \cfg_cska_pinmux_rp[1] ,
+ \cfg_cska_pinmux_rp[0] ,
+ \cfg_cska_uart_rp[3] ,
+ \cfg_cska_uart_rp[2] ,
+ \cfg_cska_uart_rp[1] ,
+ \cfg_cska_uart_rp[0] ,
+ \cfg_cska_qspi_rp[3] ,
+ \cfg_cska_qspi_rp[2] ,
+ \cfg_cska_qspi_rp[1] ,
+ \cfg_cska_qspi_rp[0] ,
+ \u_riscv_top.cfg_cska_riscv[3] ,
+ \u_riscv_top.cfg_cska_riscv[2] ,
+ \u_riscv_top.cfg_cska_riscv[1] ,
+ \u_riscv_top.cfg_cska_riscv[0] }),
+ .m0_wbd_adr_i({\wbd_int_adr_i[31] ,
+ \wbd_int_adr_i[30] ,
+ \wbd_int_adr_i[29] ,
+ \wbd_int_adr_i[28] ,
+ \wbd_int_adr_i[27] ,
+ \wbd_int_adr_i[26] ,
+ \wbd_int_adr_i[25] ,
+ \wbd_int_adr_i[24] ,
+ \wbd_int_adr_i[23] ,
+ \wbd_int_adr_i[22] ,
+ \wbd_int_adr_i[21] ,
+ \wbd_int_adr_i[20] ,
+ \wbd_int_adr_i[19] ,
+ \wbd_int_adr_i[18] ,
+ \wbd_int_adr_i[17] ,
+ \wbd_int_adr_i[16] ,
+ \wbd_int_adr_i[15] ,
+ \wbd_int_adr_i[14] ,
+ \wbd_int_adr_i[13] ,
+ \wbd_int_adr_i[12] ,
+ \wbd_int_adr_i[11] ,
+ \wbd_int_adr_i[10] ,
+ \wbd_int_adr_i[9] ,
+ \wbd_int_adr_i[8] ,
+ \wbd_int_adr_i[7] ,
+ \wbd_int_adr_i[6] ,
+ \wbd_int_adr_i[5] ,
+ \wbd_int_adr_i[4] ,
+ \wbd_int_adr_i[3] ,
+ \wbd_int_adr_i[2] ,
+ \wbd_int_adr_i[1] ,
+ \wbd_int_adr_i[0] }),
+ .m0_wbd_dat_i({\wbd_int_dat_i[31] ,
+ \wbd_int_dat_i[30] ,
+ \wbd_int_dat_i[29] ,
+ \wbd_int_dat_i[28] ,
+ \wbd_int_dat_i[27] ,
+ \wbd_int_dat_i[26] ,
+ \wbd_int_dat_i[25] ,
+ \wbd_int_dat_i[24] ,
+ \wbd_int_dat_i[23] ,
+ \wbd_int_dat_i[22] ,
+ \wbd_int_dat_i[21] ,
+ \wbd_int_dat_i[20] ,
+ \wbd_int_dat_i[19] ,
+ \wbd_int_dat_i[18] ,
+ \wbd_int_dat_i[17] ,
+ \wbd_int_dat_i[16] ,
+ \wbd_int_dat_i[15] ,
+ \wbd_int_dat_i[14] ,
+ \wbd_int_dat_i[13] ,
+ \wbd_int_dat_i[12] ,
+ \wbd_int_dat_i[11] ,
+ \wbd_int_dat_i[10] ,
+ \wbd_int_dat_i[9] ,
+ \wbd_int_dat_i[8] ,
+ \wbd_int_dat_i[7] ,
+ \wbd_int_dat_i[6] ,
+ \wbd_int_dat_i[5] ,
+ \wbd_int_dat_i[4] ,
+ \wbd_int_dat_i[3] ,
+ \wbd_int_dat_i[2] ,
+ \wbd_int_dat_i[1] ,
+ \wbd_int_dat_i[0] }),
+ .m0_wbd_dat_o({\wbd_int_dat_o[31] ,
+ \wbd_int_dat_o[30] ,
+ \wbd_int_dat_o[29] ,
+ \wbd_int_dat_o[28] ,
+ \wbd_int_dat_o[27] ,
+ \wbd_int_dat_o[26] ,
+ \wbd_int_dat_o[25] ,
+ \wbd_int_dat_o[24] ,
+ \wbd_int_dat_o[23] ,
+ \wbd_int_dat_o[22] ,
+ \wbd_int_dat_o[21] ,
+ \wbd_int_dat_o[20] ,
+ \wbd_int_dat_o[19] ,
+ \wbd_int_dat_o[18] ,
+ \wbd_int_dat_o[17] ,
+ \wbd_int_dat_o[16] ,
+ \wbd_int_dat_o[15] ,
+ \wbd_int_dat_o[14] ,
+ \wbd_int_dat_o[13] ,
+ \wbd_int_dat_o[12] ,
+ \wbd_int_dat_o[11] ,
+ \wbd_int_dat_o[10] ,
+ \wbd_int_dat_o[9] ,
+ \wbd_int_dat_o[8] ,
+ \wbd_int_dat_o[7] ,
+ \wbd_int_dat_o[6] ,
+ \wbd_int_dat_o[5] ,
+ \wbd_int_dat_o[4] ,
+ \wbd_int_dat_o[3] ,
+ \wbd_int_dat_o[2] ,
+ \wbd_int_dat_o[1] ,
+ \wbd_int_dat_o[0] }),
+ .m0_wbd_sel_i({\wbd_int_sel_i[3] ,
+ \wbd_int_sel_i[2] ,
+ \wbd_int_sel_i[1] ,
+ \wbd_int_sel_i[0] }),
+ .m1_wbd_adr_i({\u_riscv_top.wbd_dmem_adr_o[31] ,
+ \u_riscv_top.wbd_dmem_adr_o[30] ,
+ \u_riscv_top.wbd_dmem_adr_o[29] ,
+ \u_riscv_top.wbd_dmem_adr_o[28] ,
+ \u_riscv_top.wbd_dmem_adr_o[27] ,
+ \u_riscv_top.wbd_dmem_adr_o[26] ,
+ \u_riscv_top.wbd_dmem_adr_o[25] ,
+ \u_riscv_top.wbd_dmem_adr_o[24] ,
+ \u_riscv_top.wbd_dmem_adr_o[23] ,
+ \u_riscv_top.wbd_dmem_adr_o[22] ,
+ \u_riscv_top.wbd_dmem_adr_o[21] ,
+ \u_riscv_top.wbd_dmem_adr_o[20] ,
+ \u_riscv_top.wbd_dmem_adr_o[19] ,
+ \u_riscv_top.wbd_dmem_adr_o[18] ,
+ \u_riscv_top.wbd_dmem_adr_o[17] ,
+ \u_riscv_top.wbd_dmem_adr_o[16] ,
+ \u_riscv_top.wbd_dmem_adr_o[15] ,
+ \u_riscv_top.wbd_dmem_adr_o[14] ,
+ \u_riscv_top.wbd_dmem_adr_o[13] ,
+ \u_riscv_top.wbd_dmem_adr_o[12] ,
+ \u_riscv_top.wbd_dmem_adr_o[11] ,
+ \u_riscv_top.wbd_dmem_adr_o[10] ,
+ \u_riscv_top.wbd_dmem_adr_o[9] ,
+ \u_riscv_top.wbd_dmem_adr_o[8] ,
+ \u_riscv_top.wbd_dmem_adr_o[7] ,
+ \u_riscv_top.wbd_dmem_adr_o[6] ,
+ \u_riscv_top.wbd_dmem_adr_o[5] ,
+ \u_riscv_top.wbd_dmem_adr_o[4] ,
+ \u_riscv_top.wbd_dmem_adr_o[3] ,
+ \u_riscv_top.wbd_dmem_adr_o[2] ,
+ \u_riscv_top.wbd_dmem_adr_o[1] ,
+ \u_riscv_top.wbd_dmem_adr_o[0] }),
+ .m1_wbd_dat_i({\u_riscv_top.wbd_dmem_dat_o[31] ,
+ \u_riscv_top.wbd_dmem_dat_o[30] ,
+ \u_riscv_top.wbd_dmem_dat_o[29] ,
+ \u_riscv_top.wbd_dmem_dat_o[28] ,
+ \u_riscv_top.wbd_dmem_dat_o[27] ,
+ \u_riscv_top.wbd_dmem_dat_o[26] ,
+ \u_riscv_top.wbd_dmem_dat_o[25] ,
+ \u_riscv_top.wbd_dmem_dat_o[24] ,
+ \u_riscv_top.wbd_dmem_dat_o[23] ,
+ \u_riscv_top.wbd_dmem_dat_o[22] ,
+ \u_riscv_top.wbd_dmem_dat_o[21] ,
+ \u_riscv_top.wbd_dmem_dat_o[20] ,
+ \u_riscv_top.wbd_dmem_dat_o[19] ,
+ \u_riscv_top.wbd_dmem_dat_o[18] ,
+ \u_riscv_top.wbd_dmem_dat_o[17] ,
+ \u_riscv_top.wbd_dmem_dat_o[16] ,
+ \u_riscv_top.wbd_dmem_dat_o[15] ,
+ \u_riscv_top.wbd_dmem_dat_o[14] ,
+ \u_riscv_top.wbd_dmem_dat_o[13] ,
+ \u_riscv_top.wbd_dmem_dat_o[12] ,
+ \u_riscv_top.wbd_dmem_dat_o[11] ,
+ \u_riscv_top.wbd_dmem_dat_o[10] ,
+ \u_riscv_top.wbd_dmem_dat_o[9] ,
+ \u_riscv_top.wbd_dmem_dat_o[8] ,
+ \u_riscv_top.wbd_dmem_dat_o[7] ,
+ \u_riscv_top.wbd_dmem_dat_o[6] ,
+ \u_riscv_top.wbd_dmem_dat_o[5] ,
+ \u_riscv_top.wbd_dmem_dat_o[4] ,
+ \u_riscv_top.wbd_dmem_dat_o[3] ,
+ \u_riscv_top.wbd_dmem_dat_o[2] ,
+ \u_riscv_top.wbd_dmem_dat_o[1] ,
+ \u_riscv_top.wbd_dmem_dat_o[0] }),
+ .m1_wbd_dat_o({\u_riscv_top.wbd_dmem_dat_i[31] ,
+ \u_riscv_top.wbd_dmem_dat_i[30] ,
+ \u_riscv_top.wbd_dmem_dat_i[29] ,
+ \u_riscv_top.wbd_dmem_dat_i[28] ,
+ \u_riscv_top.wbd_dmem_dat_i[27] ,
+ \u_riscv_top.wbd_dmem_dat_i[26] ,
+ \u_riscv_top.wbd_dmem_dat_i[25] ,
+ \u_riscv_top.wbd_dmem_dat_i[24] ,
+ \u_riscv_top.wbd_dmem_dat_i[23] ,
+ \u_riscv_top.wbd_dmem_dat_i[22] ,
+ \u_riscv_top.wbd_dmem_dat_i[21] ,
+ \u_riscv_top.wbd_dmem_dat_i[20] ,
+ \u_riscv_top.wbd_dmem_dat_i[19] ,
+ \u_riscv_top.wbd_dmem_dat_i[18] ,
+ \u_riscv_top.wbd_dmem_dat_i[17] ,
+ \u_riscv_top.wbd_dmem_dat_i[16] ,
+ \u_riscv_top.wbd_dmem_dat_i[15] ,
+ \u_riscv_top.wbd_dmem_dat_i[14] ,
+ \u_riscv_top.wbd_dmem_dat_i[13] ,
+ \u_riscv_top.wbd_dmem_dat_i[12] ,
+ \u_riscv_top.wbd_dmem_dat_i[11] ,
+ \u_riscv_top.wbd_dmem_dat_i[10] ,
+ \u_riscv_top.wbd_dmem_dat_i[9] ,
+ \u_riscv_top.wbd_dmem_dat_i[8] ,
+ \u_riscv_top.wbd_dmem_dat_i[7] ,
+ \u_riscv_top.wbd_dmem_dat_i[6] ,
+ \u_riscv_top.wbd_dmem_dat_i[5] ,
+ \u_riscv_top.wbd_dmem_dat_i[4] ,
+ \u_riscv_top.wbd_dmem_dat_i[3] ,
+ \u_riscv_top.wbd_dmem_dat_i[2] ,
+ \u_riscv_top.wbd_dmem_dat_i[1] ,
+ \u_riscv_top.wbd_dmem_dat_i[0] }),
+ .m1_wbd_sel_i({\u_riscv_top.wbd_dmem_sel_o[3] ,
+ \u_riscv_top.wbd_dmem_sel_o[2] ,
+ \u_riscv_top.wbd_dmem_sel_o[1] ,
+ \u_riscv_top.wbd_dmem_sel_o[0] }),
+ .m2_wbd_adr_i({\u_riscv_top.wb_dcache_adr_o[31] ,
+ \u_riscv_top.wb_dcache_adr_o[30] ,
+ \u_riscv_top.wb_dcache_adr_o[29] ,
+ \u_riscv_top.wb_dcache_adr_o[28] ,
+ \u_riscv_top.wb_dcache_adr_o[27] ,
+ \u_riscv_top.wb_dcache_adr_o[26] ,
+ \u_riscv_top.wb_dcache_adr_o[25] ,
+ \u_riscv_top.wb_dcache_adr_o[24] ,
+ \u_riscv_top.wb_dcache_adr_o[23] ,
+ \u_riscv_top.wb_dcache_adr_o[22] ,
+ \u_riscv_top.wb_dcache_adr_o[21] ,
+ \u_riscv_top.wb_dcache_adr_o[20] ,
+ \u_riscv_top.wb_dcache_adr_o[19] ,
+ \u_riscv_top.wb_dcache_adr_o[18] ,
+ \u_riscv_top.wb_dcache_adr_o[17] ,
+ \u_riscv_top.wb_dcache_adr_o[16] ,
+ \u_riscv_top.wb_dcache_adr_o[15] ,
+ \u_riscv_top.wb_dcache_adr_o[14] ,
+ \u_riscv_top.wb_dcache_adr_o[13] ,
+ \u_riscv_top.wb_dcache_adr_o[12] ,
+ \u_riscv_top.wb_dcache_adr_o[11] ,
+ \u_riscv_top.wb_dcache_adr_o[10] ,
+ \u_riscv_top.wb_dcache_adr_o[9] ,
+ \u_riscv_top.wb_dcache_adr_o[8] ,
+ \u_riscv_top.wb_dcache_adr_o[7] ,
+ \u_riscv_top.wb_dcache_adr_o[6] ,
+ \u_riscv_top.wb_dcache_adr_o[5] ,
+ \u_riscv_top.wb_dcache_adr_o[4] ,
+ \u_riscv_top.wb_dcache_adr_o[3] ,
+ \u_riscv_top.wb_dcache_adr_o[2] ,
+ \u_riscv_top.wb_dcache_adr_o[1] ,
+ \u_riscv_top.wb_dcache_adr_o[0] }),
+ .m2_wbd_bl_i({\u_riscv_top.wb_dcache_bl_o[9] ,
+ \u_riscv_top.wb_dcache_bl_o[8] ,
+ \u_riscv_top.wb_dcache_bl_o[7] ,
+ \u_riscv_top.wb_dcache_bl_o[6] ,
+ \u_riscv_top.wb_dcache_bl_o[5] ,
+ \u_riscv_top.wb_dcache_bl_o[4] ,
+ \u_riscv_top.wb_dcache_bl_o[3] ,
+ \u_riscv_top.wb_dcache_bl_o[2] ,
+ \u_riscv_top.wb_dcache_bl_o[1] ,
+ \u_riscv_top.wb_dcache_bl_o[0] }),
+ .m2_wbd_dat_i({\u_riscv_top.wb_dcache_dat_o[31] ,
+ \u_riscv_top.wb_dcache_dat_o[30] ,
+ \u_riscv_top.wb_dcache_dat_o[29] ,
+ \u_riscv_top.wb_dcache_dat_o[28] ,
+ \u_riscv_top.wb_dcache_dat_o[27] ,
+ \u_riscv_top.wb_dcache_dat_o[26] ,
+ \u_riscv_top.wb_dcache_dat_o[25] ,
+ \u_riscv_top.wb_dcache_dat_o[24] ,
+ \u_riscv_top.wb_dcache_dat_o[23] ,
+ \u_riscv_top.wb_dcache_dat_o[22] ,
+ \u_riscv_top.wb_dcache_dat_o[21] ,
+ \u_riscv_top.wb_dcache_dat_o[20] ,
+ \u_riscv_top.wb_dcache_dat_o[19] ,
+ \u_riscv_top.wb_dcache_dat_o[18] ,
+ \u_riscv_top.wb_dcache_dat_o[17] ,
+ \u_riscv_top.wb_dcache_dat_o[16] ,
+ \u_riscv_top.wb_dcache_dat_o[15] ,
+ \u_riscv_top.wb_dcache_dat_o[14] ,
+ \u_riscv_top.wb_dcache_dat_o[13] ,
+ \u_riscv_top.wb_dcache_dat_o[12] ,
+ \u_riscv_top.wb_dcache_dat_o[11] ,
+ \u_riscv_top.wb_dcache_dat_o[10] ,
+ \u_riscv_top.wb_dcache_dat_o[9] ,
+ \u_riscv_top.wb_dcache_dat_o[8] ,
+ \u_riscv_top.wb_dcache_dat_o[7] ,
+ \u_riscv_top.wb_dcache_dat_o[6] ,
+ \u_riscv_top.wb_dcache_dat_o[5] ,
+ \u_riscv_top.wb_dcache_dat_o[4] ,
+ \u_riscv_top.wb_dcache_dat_o[3] ,
+ \u_riscv_top.wb_dcache_dat_o[2] ,
+ \u_riscv_top.wb_dcache_dat_o[1] ,
+ \u_riscv_top.wb_dcache_dat_o[0] }),
+ .m2_wbd_dat_o({\u_riscv_top.wb_dcache_dat_i[31] ,
+ \u_riscv_top.wb_dcache_dat_i[30] ,
+ \u_riscv_top.wb_dcache_dat_i[29] ,
+ \u_riscv_top.wb_dcache_dat_i[28] ,
+ \u_riscv_top.wb_dcache_dat_i[27] ,
+ \u_riscv_top.wb_dcache_dat_i[26] ,
+ \u_riscv_top.wb_dcache_dat_i[25] ,
+ \u_riscv_top.wb_dcache_dat_i[24] ,
+ \u_riscv_top.wb_dcache_dat_i[23] ,
+ \u_riscv_top.wb_dcache_dat_i[22] ,
+ \u_riscv_top.wb_dcache_dat_i[21] ,
+ \u_riscv_top.wb_dcache_dat_i[20] ,
+ \u_riscv_top.wb_dcache_dat_i[19] ,
+ \u_riscv_top.wb_dcache_dat_i[18] ,
+ \u_riscv_top.wb_dcache_dat_i[17] ,
+ \u_riscv_top.wb_dcache_dat_i[16] ,
+ \u_riscv_top.wb_dcache_dat_i[15] ,
+ \u_riscv_top.wb_dcache_dat_i[14] ,
+ \u_riscv_top.wb_dcache_dat_i[13] ,
+ \u_riscv_top.wb_dcache_dat_i[12] ,
+ \u_riscv_top.wb_dcache_dat_i[11] ,
+ \u_riscv_top.wb_dcache_dat_i[10] ,
+ \u_riscv_top.wb_dcache_dat_i[9] ,
+ \u_riscv_top.wb_dcache_dat_i[8] ,
+ \u_riscv_top.wb_dcache_dat_i[7] ,
+ \u_riscv_top.wb_dcache_dat_i[6] ,
+ \u_riscv_top.wb_dcache_dat_i[5] ,
+ \u_riscv_top.wb_dcache_dat_i[4] ,
+ \u_riscv_top.wb_dcache_dat_i[3] ,
+ \u_riscv_top.wb_dcache_dat_i[2] ,
+ \u_riscv_top.wb_dcache_dat_i[1] ,
+ \u_riscv_top.wb_dcache_dat_i[0] }),
+ .m2_wbd_sel_i({\u_riscv_top.wb_dcache_sel_o[3] ,
+ \u_riscv_top.wb_dcache_sel_o[2] ,
+ \u_riscv_top.wb_dcache_sel_o[1] ,
+ \u_riscv_top.wb_dcache_sel_o[0] }),
+ .m3_wbd_adr_i({\u_riscv_top.wb_icache_adr_o[31] ,
+ \u_riscv_top.wb_icache_adr_o[30] ,
+ \u_riscv_top.wb_icache_adr_o[29] ,
+ \u_riscv_top.wb_icache_adr_o[28] ,
+ \u_riscv_top.wb_icache_adr_o[27] ,
+ \u_riscv_top.wb_icache_adr_o[26] ,
+ \u_riscv_top.wb_icache_adr_o[25] ,
+ \u_riscv_top.wb_icache_adr_o[24] ,
+ \u_riscv_top.wb_icache_adr_o[23] ,
+ \u_riscv_top.wb_icache_adr_o[22] ,
+ \u_riscv_top.wb_icache_adr_o[21] ,
+ \u_riscv_top.wb_icache_adr_o[20] ,
+ \u_riscv_top.wb_icache_adr_o[19] ,
+ \u_riscv_top.wb_icache_adr_o[18] ,
+ \u_riscv_top.wb_icache_adr_o[17] ,
+ \u_riscv_top.wb_icache_adr_o[16] ,
+ \u_riscv_top.wb_icache_adr_o[15] ,
+ \u_riscv_top.wb_icache_adr_o[14] ,
+ \u_riscv_top.wb_icache_adr_o[13] ,
+ \u_riscv_top.wb_icache_adr_o[12] ,
+ \u_riscv_top.wb_icache_adr_o[11] ,
+ \u_riscv_top.wb_icache_adr_o[10] ,
+ \u_riscv_top.wb_icache_adr_o[9] ,
+ \u_riscv_top.wb_icache_adr_o[8] ,
+ \u_riscv_top.wb_icache_adr_o[7] ,
+ \u_riscv_top.wb_icache_adr_o[6] ,
+ \u_riscv_top.wb_icache_adr_o[5] ,
+ \u_riscv_top.wb_icache_adr_o[4] ,
+ \u_riscv_top.wb_icache_adr_o[3] ,
+ \u_riscv_top.wb_icache_adr_o[2] ,
+ \u_riscv_top.wb_icache_adr_o[1] ,
+ \u_riscv_top.wb_icache_adr_o[0] }),
+ .m3_wbd_bl_i({\u_riscv_top.wb_icache_bl_o[9] ,
+ \u_riscv_top.wb_icache_bl_o[8] ,
+ \u_riscv_top.wb_icache_bl_o[7] ,
+ \u_riscv_top.wb_icache_bl_o[6] ,
+ \u_riscv_top.wb_icache_bl_o[5] ,
+ \u_riscv_top.wb_icache_bl_o[4] ,
+ \u_riscv_top.wb_icache_bl_o[3] ,
+ \u_riscv_top.wb_icache_bl_o[2] ,
+ \u_riscv_top.wb_icache_bl_o[1] ,
+ \u_riscv_top.wb_icache_bl_o[0] }),
+ .m3_wbd_dat_o({\u_riscv_top.wb_icache_dat_i[31] ,
+ \u_riscv_top.wb_icache_dat_i[30] ,
+ \u_riscv_top.wb_icache_dat_i[29] ,
+ \u_riscv_top.wb_icache_dat_i[28] ,
+ \u_riscv_top.wb_icache_dat_i[27] ,
+ \u_riscv_top.wb_icache_dat_i[26] ,
+ \u_riscv_top.wb_icache_dat_i[25] ,
+ \u_riscv_top.wb_icache_dat_i[24] ,
+ \u_riscv_top.wb_icache_dat_i[23] ,
+ \u_riscv_top.wb_icache_dat_i[22] ,
+ \u_riscv_top.wb_icache_dat_i[21] ,
+ \u_riscv_top.wb_icache_dat_i[20] ,
+ \u_riscv_top.wb_icache_dat_i[19] ,
+ \u_riscv_top.wb_icache_dat_i[18] ,
+ \u_riscv_top.wb_icache_dat_i[17] ,
+ \u_riscv_top.wb_icache_dat_i[16] ,
+ \u_riscv_top.wb_icache_dat_i[15] ,
+ \u_riscv_top.wb_icache_dat_i[14] ,
+ \u_riscv_top.wb_icache_dat_i[13] ,
+ \u_riscv_top.wb_icache_dat_i[12] ,
+ \u_riscv_top.wb_icache_dat_i[11] ,
+ \u_riscv_top.wb_icache_dat_i[10] ,
+ \u_riscv_top.wb_icache_dat_i[9] ,
+ \u_riscv_top.wb_icache_dat_i[8] ,
+ \u_riscv_top.wb_icache_dat_i[7] ,
+ \u_riscv_top.wb_icache_dat_i[6] ,
+ \u_riscv_top.wb_icache_dat_i[5] ,
+ \u_riscv_top.wb_icache_dat_i[4] ,
+ \u_riscv_top.wb_icache_dat_i[3] ,
+ \u_riscv_top.wb_icache_dat_i[2] ,
+ \u_riscv_top.wb_icache_dat_i[1] ,
+ \u_riscv_top.wb_icache_dat_i[0] }),
+ .m3_wbd_sel_i({\u_riscv_top.wb_icache_sel_o[3] ,
+ \u_riscv_top.wb_icache_sel_o[2] ,
+ \u_riscv_top.wb_icache_sel_o[1] ,
+ \u_riscv_top.wb_icache_sel_o[0] }),
+ .s0_wbd_adr_o({\wbd_spim_adr_o[31] ,
+ \wbd_spim_adr_o[30] ,
+ \wbd_spim_adr_o[29] ,
+ \wbd_spim_adr_o[28] ,
+ \wbd_spim_adr_o[27] ,
+ \wbd_spim_adr_o[26] ,
+ \wbd_spim_adr_o[25] ,
+ \wbd_spim_adr_o[24] ,
+ \wbd_spim_adr_o[23] ,
+ \wbd_spim_adr_o[22] ,
+ \wbd_spim_adr_o[21] ,
+ \wbd_spim_adr_o[20] ,
+ \wbd_spim_adr_o[19] ,
+ \wbd_spim_adr_o[18] ,
+ \wbd_spim_adr_o[17] ,
+ \wbd_spim_adr_o[16] ,
+ \wbd_spim_adr_o[15] ,
+ \wbd_spim_adr_o[14] ,
+ \wbd_spim_adr_o[13] ,
+ \wbd_spim_adr_o[12] ,
+ \wbd_spim_adr_o[11] ,
+ \wbd_spim_adr_o[10] ,
+ \wbd_spim_adr_o[9] ,
+ \wbd_spim_adr_o[8] ,
+ \wbd_spim_adr_o[7] ,
+ \wbd_spim_adr_o[6] ,
+ \wbd_spim_adr_o[5] ,
+ \wbd_spim_adr_o[4] ,
+ \wbd_spim_adr_o[3] ,
+ \wbd_spim_adr_o[2] ,
+ \wbd_spim_adr_o[1] ,
+ \wbd_spim_adr_o[0] }),
+ .s0_wbd_bl_o({\wbd_spim_bl_o[9] ,
+ \wbd_spim_bl_o[8] ,
+ \wbd_spim_bl_o[7] ,
+ \wbd_spim_bl_o[6] ,
+ \wbd_spim_bl_o[5] ,
+ \wbd_spim_bl_o[4] ,
+ \wbd_spim_bl_o[3] ,
+ \wbd_spim_bl_o[2] ,
+ \wbd_spim_bl_o[1] ,
+ \wbd_spim_bl_o[0] }),
+ .s0_wbd_dat_i({\wbd_spim_dat_i[31] ,
+ \wbd_spim_dat_i[30] ,
+ \wbd_spim_dat_i[29] ,
+ \wbd_spim_dat_i[28] ,
+ \wbd_spim_dat_i[27] ,
+ \wbd_spim_dat_i[26] ,
+ \wbd_spim_dat_i[25] ,
+ \wbd_spim_dat_i[24] ,
+ \wbd_spim_dat_i[23] ,
+ \wbd_spim_dat_i[22] ,
+ \wbd_spim_dat_i[21] ,
+ \wbd_spim_dat_i[20] ,
+ \wbd_spim_dat_i[19] ,
+ \wbd_spim_dat_i[18] ,
+ \wbd_spim_dat_i[17] ,
+ \wbd_spim_dat_i[16] ,
+ \wbd_spim_dat_i[15] ,
+ \wbd_spim_dat_i[14] ,
+ \wbd_spim_dat_i[13] ,
+ \wbd_spim_dat_i[12] ,
+ \wbd_spim_dat_i[11] ,
+ \wbd_spim_dat_i[10] ,
+ \wbd_spim_dat_i[9] ,
+ \wbd_spim_dat_i[8] ,
+ \wbd_spim_dat_i[7] ,
+ \wbd_spim_dat_i[6] ,
+ \wbd_spim_dat_i[5] ,
+ \wbd_spim_dat_i[4] ,
+ \wbd_spim_dat_i[3] ,
+ \wbd_spim_dat_i[2] ,
+ \wbd_spim_dat_i[1] ,
+ \wbd_spim_dat_i[0] }),
+ .s0_wbd_dat_o({\wbd_spim_dat_o[31] ,
+ \wbd_spim_dat_o[30] ,
+ \wbd_spim_dat_o[29] ,
+ \wbd_spim_dat_o[28] ,
+ \wbd_spim_dat_o[27] ,
+ \wbd_spim_dat_o[26] ,
+ \wbd_spim_dat_o[25] ,
+ \wbd_spim_dat_o[24] ,
+ \wbd_spim_dat_o[23] ,
+ \wbd_spim_dat_o[22] ,
+ \wbd_spim_dat_o[21] ,
+ \wbd_spim_dat_o[20] ,
+ \wbd_spim_dat_o[19] ,
+ \wbd_spim_dat_o[18] ,
+ \wbd_spim_dat_o[17] ,
+ \wbd_spim_dat_o[16] ,
+ \wbd_spim_dat_o[15] ,
+ \wbd_spim_dat_o[14] ,
+ \wbd_spim_dat_o[13] ,
+ \wbd_spim_dat_o[12] ,
+ \wbd_spim_dat_o[11] ,
+ \wbd_spim_dat_o[10] ,
+ \wbd_spim_dat_o[9] ,
+ \wbd_spim_dat_o[8] ,
+ \wbd_spim_dat_o[7] ,
+ \wbd_spim_dat_o[6] ,
+ \wbd_spim_dat_o[5] ,
+ \wbd_spim_dat_o[4] ,
+ \wbd_spim_dat_o[3] ,
+ \wbd_spim_dat_o[2] ,
+ \wbd_spim_dat_o[1] ,
+ \wbd_spim_dat_o[0] }),
+ .s0_wbd_sel_o({\wbd_spim_sel_o[3] ,
+ \wbd_spim_sel_o[2] ,
+ \wbd_spim_sel_o[1] ,
+ \wbd_spim_sel_o[0] }),
+ .s1_wbd_adr_o({\wbd_uart_adr_o[8] ,
+ \wbd_uart_adr_o[7] ,
+ \wbd_uart_adr_o[6] ,
+ \wbd_uart_adr_o[5] ,
+ \wbd_uart_adr_o[4] ,
+ \wbd_uart_adr_o[3] ,
+ \wbd_uart_adr_o[2] ,
+ \wbd_uart_adr_o[1] ,
+ \wbd_uart_adr_o[0] }),
+ .s1_wbd_dat_i({\wbd_uart_dat_i[31] ,
+ \wbd_uart_dat_i[30] ,
+ \wbd_uart_dat_i[29] ,
+ \wbd_uart_dat_i[28] ,
+ \wbd_uart_dat_i[27] ,
+ \wbd_uart_dat_i[26] ,
+ \wbd_uart_dat_i[25] ,
+ \wbd_uart_dat_i[24] ,
+ \wbd_uart_dat_i[23] ,
+ \wbd_uart_dat_i[22] ,
+ \wbd_uart_dat_i[21] ,
+ \wbd_uart_dat_i[20] ,
+ \wbd_uart_dat_i[19] ,
+ \wbd_uart_dat_i[18] ,
+ \wbd_uart_dat_i[17] ,
+ \wbd_uart_dat_i[16] ,
+ \wbd_uart_dat_i[15] ,
+ \wbd_uart_dat_i[14] ,
+ \wbd_uart_dat_i[13] ,
+ \wbd_uart_dat_i[12] ,
+ \wbd_uart_dat_i[11] ,
+ \wbd_uart_dat_i[10] ,
+ \wbd_uart_dat_i[9] ,
+ \wbd_uart_dat_i[8] ,
+ \wbd_uart_dat_i[7] ,
+ \wbd_uart_dat_i[6] ,
+ \wbd_uart_dat_i[5] ,
+ \wbd_uart_dat_i[4] ,
+ \wbd_uart_dat_i[3] ,
+ \wbd_uart_dat_i[2] ,
+ \wbd_uart_dat_i[1] ,
+ \wbd_uart_dat_i[0] }),
+ .s1_wbd_dat_o({\wbd_uart_dat_o[31] ,
+ \wbd_uart_dat_o[30] ,
+ \wbd_uart_dat_o[29] ,
+ \wbd_uart_dat_o[28] ,
+ \wbd_uart_dat_o[27] ,
+ \wbd_uart_dat_o[26] ,
+ \wbd_uart_dat_o[25] ,
+ \wbd_uart_dat_o[24] ,
+ \wbd_uart_dat_o[23] ,
+ \wbd_uart_dat_o[22] ,
+ \wbd_uart_dat_o[21] ,
+ \wbd_uart_dat_o[20] ,
+ \wbd_uart_dat_o[19] ,
+ \wbd_uart_dat_o[18] ,
+ \wbd_uart_dat_o[17] ,
+ \wbd_uart_dat_o[16] ,
+ \wbd_uart_dat_o[15] ,
+ \wbd_uart_dat_o[14] ,
+ \wbd_uart_dat_o[13] ,
+ \wbd_uart_dat_o[12] ,
+ \wbd_uart_dat_o[11] ,
+ \wbd_uart_dat_o[10] ,
+ \wbd_uart_dat_o[9] ,
+ \wbd_uart_dat_o[8] ,
+ \wbd_uart_dat_o[7] ,
+ \wbd_uart_dat_o[6] ,
+ \wbd_uart_dat_o[5] ,
+ \wbd_uart_dat_o[4] ,
+ \wbd_uart_dat_o[3] ,
+ \wbd_uart_dat_o[2] ,
+ \wbd_uart_dat_o[1] ,
+ \wbd_uart_dat_o[0] }),
+ .s1_wbd_sel_o({\wbd_uart_sel_o[3] ,
+ \wbd_uart_sel_o[2] ,
+ \wbd_uart_sel_o[1] ,
+ \wbd_uart_sel_o[0] }),
+ .s2_wbd_adr_o({\wbd_glbl_adr_o[7] ,
+ \wbd_glbl_adr_o[6] ,
+ \wbd_glbl_adr_o[5] ,
+ \wbd_glbl_adr_o[4] ,
+ \wbd_glbl_adr_o[3] ,
+ \wbd_glbl_adr_o[2] ,
+ \wbd_glbl_adr_o[1] ,
+ \wbd_glbl_adr_o[0] }),
+ .s2_wbd_dat_i({\wbd_glbl_dat_i[31] ,
+ \wbd_glbl_dat_i[30] ,
+ \wbd_glbl_dat_i[29] ,
+ \wbd_glbl_dat_i[28] ,
+ \wbd_glbl_dat_i[27] ,
+ \wbd_glbl_dat_i[26] ,
+ \wbd_glbl_dat_i[25] ,
+ \wbd_glbl_dat_i[24] ,
+ \wbd_glbl_dat_i[23] ,
+ \wbd_glbl_dat_i[22] ,
+ \wbd_glbl_dat_i[21] ,
+ \wbd_glbl_dat_i[20] ,
+ \wbd_glbl_dat_i[19] ,
+ \wbd_glbl_dat_i[18] ,
+ \wbd_glbl_dat_i[17] ,
+ \wbd_glbl_dat_i[16] ,
+ \wbd_glbl_dat_i[15] ,
+ \wbd_glbl_dat_i[14] ,
+ \wbd_glbl_dat_i[13] ,
+ \wbd_glbl_dat_i[12] ,
+ \wbd_glbl_dat_i[11] ,
+ \wbd_glbl_dat_i[10] ,
+ \wbd_glbl_dat_i[9] ,
+ \wbd_glbl_dat_i[8] ,
+ \wbd_glbl_dat_i[7] ,
+ \wbd_glbl_dat_i[6] ,
+ \wbd_glbl_dat_i[5] ,
+ \wbd_glbl_dat_i[4] ,
+ \wbd_glbl_dat_i[3] ,
+ \wbd_glbl_dat_i[2] ,
+ \wbd_glbl_dat_i[1] ,
+ \wbd_glbl_dat_i[0] }),
+ .s2_wbd_dat_o({\wbd_glbl_dat_o[31] ,
+ \wbd_glbl_dat_o[30] ,
+ \wbd_glbl_dat_o[29] ,
+ \wbd_glbl_dat_o[28] ,
+ \wbd_glbl_dat_o[27] ,
+ \wbd_glbl_dat_o[26] ,
+ \wbd_glbl_dat_o[25] ,
+ \wbd_glbl_dat_o[24] ,
+ \wbd_glbl_dat_o[23] ,
+ \wbd_glbl_dat_o[22] ,
+ \wbd_glbl_dat_o[21] ,
+ \wbd_glbl_dat_o[20] ,
+ \wbd_glbl_dat_o[19] ,
+ \wbd_glbl_dat_o[18] ,
+ \wbd_glbl_dat_o[17] ,
+ \wbd_glbl_dat_o[16] ,
+ \wbd_glbl_dat_o[15] ,
+ \wbd_glbl_dat_o[14] ,
+ \wbd_glbl_dat_o[13] ,
+ \wbd_glbl_dat_o[12] ,
+ \wbd_glbl_dat_o[11] ,
+ \wbd_glbl_dat_o[10] ,
+ \wbd_glbl_dat_o[9] ,
+ \wbd_glbl_dat_o[8] ,
+ \wbd_glbl_dat_o[7] ,
+ \wbd_glbl_dat_o[6] ,
+ \wbd_glbl_dat_o[5] ,
+ \wbd_glbl_dat_o[4] ,
+ \wbd_glbl_dat_o[3] ,
+ \wbd_glbl_dat_o[2] ,
+ \wbd_glbl_dat_o[1] ,
+ \wbd_glbl_dat_o[0] }),
+ .s2_wbd_sel_o({\wbd_glbl_sel_o[3] ,
+ \wbd_glbl_sel_o[2] ,
+ \wbd_glbl_sel_o[1] ,
+ \wbd_glbl_sel_o[0] }));
+ pinmux u_pinmux (.cpu_intf_rst_n(\u_riscv_top.cpu_intf_rst_n ),
+ .dbg_clk_mon(dbg_clk_mon),
+ .h_reset_n(\u_riscv_top.pwrup_rst_n ),
+ .i2cm_clk_i(i2cm_clk_i),
+ .i2cm_clk_o(i2cm_clk_o),
+ .i2cm_clk_oen(i2cm_clk_oen),
+ .i2cm_data_i(i2cm_data_i),
+ .i2cm_data_o(i2cm_data_o),
+ .i2cm_data_oen(i2cm_data_oen),
+ .i2cm_intr(i2cm_intr_o),
+ .i2cm_rst_n(i2c_rst_n),
+ .mclk(wbd_clk_pinmux_skew),
+ .pulse1m_mclk(pulse1m_mclk),
+ .qspim_rst_n(qspim_rst_n),
+ .reg_ack(wbd_glbl_ack_i),
+ .reg_cs(wbd_glbl_stb_o),
+ .reg_wr(wbd_glbl_we_o),
+ .sflash_sck(sflash_sck),
+ .soft_irq(soft_irq),
+ .spim_miso(sspim_so),
+ .spim_mosi(sspim_si),
+ .spim_sck(sspim_sck),
+ .sspim_rst_n(sspim_rst_n),
+ .uartm_rxd(uartm_rxd),
+ .uartm_txd(uartm_txd),
+ .usb_dn_i(usb_dn_i),
+ .usb_dn_o(usb_dn_o),
+ .usb_dp_i(usb_dp_i),
+ .usb_dp_o(usb_dp_o),
+ .usb_intr(usb_intr_o),
+ .usb_oen(usb_oen),
+ .usb_rst_n(usb_rst_n),
+ .vccd1(vccd1),
+ .vssd1(vssd1),
+ .wbd_clk_int(wbd_clk_pinmux_rp),
+ .wbd_clk_pinmux(wbd_clk_pinmux_skew),
+ .cfg_cska_pinmux({\cfg_cska_pinmux_rp[3] ,
+ \cfg_cska_pinmux_rp[2] ,
+ \cfg_cska_pinmux_rp[1] ,
+ \cfg_cska_pinmux_rp[0] }),
+ .cfg_riscv_ctrl({\cfg_riscv_ctrl[15] ,
+ \cfg_riscv_ctrl[14] ,
+ \cfg_riscv_ctrl[13] ,
+ \cfg_riscv_ctrl[12] ,
+ \cfg_riscv_ctrl[11] ,
+ \cfg_riscv_ctrl[10] ,
+ \cfg_riscv_ctrl[9] ,
+ \cfg_riscv_ctrl[8] ,
+ \cfg_riscv_ctrl[7] ,
+ \cfg_riscv_ctrl[6] ,
+ \cfg_riscv_ctrl[5] ,
+ \cfg_riscv_ctrl[4] ,
+ \cfg_riscv_ctrl[3] ,
+ \cfg_riscv_ctrl[2] ,
+ \cfg_riscv_ctrl[1] ,
+ \cfg_riscv_ctrl[0] }),
+ .cpu_core_rst_n({\u_riscv_top.cpu_core_rst_n[3] ,
+ \u_riscv_top.cpu_core_rst_n[2] ,
+ \u_riscv_top.cpu_core_rst_n[1] ,
+ \u_riscv_top.cpu_core_rst_n[0] }),
+ .digital_io_in({io_in[37],
+ io_in[36],
+ io_in[35],
+ io_in[34],
+ io_in[33],
+ io_in[32],
+ io_in[31],
+ io_in[30],
+ io_in[29],
+ io_in[28],
+ io_in[27],
+ io_in[26],
+ io_in[25],
+ io_in[24],
+ io_in[23],
+ io_in[22],
+ io_in[21],
+ io_in[20],
+ io_in[19],
+ io_in[18],
+ io_in[17],
+ io_in[16],
+ io_in[15],
+ io_in[14],
+ io_in[13],
+ io_in[12],
+ io_in[11],
+ io_in[10],
+ io_in[9],
+ io_in[8],
+ io_in[7],
+ io_in[6],
+ io_in[5],
+ io_in[4],
+ io_in[3],
+ io_in[2],
+ io_in[1],
+ io_in[0]}),
+ .digital_io_oen({io_oeb[37],
+ io_oeb[36],
+ io_oeb[35],
+ io_oeb[34],
+ io_oeb[33],
+ io_oeb[32],
+ io_oeb[31],
+ io_oeb[30],
+ io_oeb[29],
+ io_oeb[28],
+ io_oeb[27],
+ io_oeb[26],
+ io_oeb[25],
+ io_oeb[24],
+ io_oeb[23],
+ io_oeb[22],
+ io_oeb[21],
+ io_oeb[20],
+ io_oeb[19],
+ io_oeb[18],
+ io_oeb[17],
+ io_oeb[16],
+ io_oeb[15],
+ io_oeb[14],
+ io_oeb[13],
+ io_oeb[12],
+ io_oeb[11],
+ io_oeb[10],
+ io_oeb[9],
+ io_oeb[8],
+ io_oeb[7],
+ io_oeb[6],
+ io_oeb[5],
+ io_oeb[4],
+ io_oeb[3],
+ io_oeb[2],
+ io_oeb[1],
+ io_oeb[0]}),
+ .digital_io_out({io_out[37],
+ io_out[36],
+ io_out[35],
+ io_out[34],
+ io_out[33],
+ io_out[32],
+ io_out[31],
+ io_out[30],
+ io_out[29],
+ io_out[28],
+ io_out[27],
+ io_out[26],
+ io_out[25],
+ io_out[24],
+ io_out[23],
+ io_out[22],
+ io_out[21],
+ io_out[20],
+ io_out[19],
+ io_out[18],
+ io_out[17],
+ io_out[16],
+ io_out[15],
+ io_out[14],
+ io_out[13],
+ io_out[12],
+ io_out[11],
+ io_out[10],
+ io_out[9],
+ io_out[8],
+ io_out[7],
+ io_out[6],
+ io_out[5],
+ io_out[4],
+ io_out[3],
+ io_out[2],
+ io_out[1],
+ io_out[0]}),
+ .irq_lines({\irq_lines[15] ,
+ \irq_lines[14] ,
+ \irq_lines[13] ,
+ \irq_lines[12] ,
+ \irq_lines[11] ,
+ \irq_lines[10] ,
+ \irq_lines[9] ,
+ \irq_lines[8] ,
+ \irq_lines[7] ,
+ \irq_lines[6] ,
+ \irq_lines[5] ,
+ \irq_lines[4] ,
+ \irq_lines[3] ,
+ \irq_lines[2] ,
+ \irq_lines[1] ,
+ \irq_lines[0] }),
+ .pinmux_debug({la_data_out[127],
+ la_data_out[126],
+ la_data_out[125],
+ la_data_out[124],
+ la_data_out[123],
+ la_data_out[122],
+ la_data_out[121],
+ la_data_out[120],
+ la_data_out[119],
+ la_data_out[118],
+ la_data_out[117],
+ la_data_out[116],
+ la_data_out[115],
+ la_data_out[114],
+ la_data_out[113],
+ la_data_out[112],
+ la_data_out[111],
+ la_data_out[110],
+ la_data_out[109],
+ la_data_out[108],
+ la_data_out[107],
+ la_data_out[106],
+ la_data_out[105],
+ la_data_out[104],
+ la_data_out[103],
+ la_data_out[102],
+ la_data_out[101],
+ la_data_out[100],
+ la_data_out[99],
+ la_data_out[98],
+ la_data_out[97],
+ la_data_out[96]}),
+ .reg_addr({\wbd_glbl_adr_o[7] ,
+ \wbd_glbl_adr_o[6] ,
+ \wbd_glbl_adr_o[5] ,
+ \wbd_glbl_adr_o[4] ,
+ \wbd_glbl_adr_o[3] ,
+ \wbd_glbl_adr_o[2] ,
+ \wbd_glbl_adr_o[1] ,
+ \wbd_glbl_adr_o[0] }),
+ .reg_be({\wbd_glbl_sel_o[3] ,
+ \wbd_glbl_sel_o[2] ,
+ \wbd_glbl_sel_o[1] ,
+ \wbd_glbl_sel_o[0] }),
+ .reg_rdata({\wbd_glbl_dat_i[31] ,
+ \wbd_glbl_dat_i[30] ,
+ \wbd_glbl_dat_i[29] ,
+ \wbd_glbl_dat_i[28] ,
+ \wbd_glbl_dat_i[27] ,
+ \wbd_glbl_dat_i[26] ,
+ \wbd_glbl_dat_i[25] ,
+ \wbd_glbl_dat_i[24] ,
+ \wbd_glbl_dat_i[23] ,
+ \wbd_glbl_dat_i[22] ,
+ \wbd_glbl_dat_i[21] ,
+ \wbd_glbl_dat_i[20] ,
+ \wbd_glbl_dat_i[19] ,
+ \wbd_glbl_dat_i[18] ,
+ \wbd_glbl_dat_i[17] ,
+ \wbd_glbl_dat_i[16] ,
+ \wbd_glbl_dat_i[15] ,
+ \wbd_glbl_dat_i[14] ,
+ \wbd_glbl_dat_i[13] ,
+ \wbd_glbl_dat_i[12] ,
+ \wbd_glbl_dat_i[11] ,
+ \wbd_glbl_dat_i[10] ,
+ \wbd_glbl_dat_i[9] ,
+ \wbd_glbl_dat_i[8] ,
+ \wbd_glbl_dat_i[7] ,
+ \wbd_glbl_dat_i[6] ,
+ \wbd_glbl_dat_i[5] ,
+ \wbd_glbl_dat_i[4] ,
+ \wbd_glbl_dat_i[3] ,
+ \wbd_glbl_dat_i[2] ,
+ \wbd_glbl_dat_i[1] ,
+ \wbd_glbl_dat_i[0] }),
+ .reg_wdata({\wbd_glbl_dat_o[31] ,
+ \wbd_glbl_dat_o[30] ,
+ \wbd_glbl_dat_o[29] ,
+ \wbd_glbl_dat_o[28] ,
+ \wbd_glbl_dat_o[27] ,
+ \wbd_glbl_dat_o[26] ,
+ \wbd_glbl_dat_o[25] ,
+ \wbd_glbl_dat_o[24] ,
+ \wbd_glbl_dat_o[23] ,
+ \wbd_glbl_dat_o[22] ,
+ \wbd_glbl_dat_o[21] ,
+ \wbd_glbl_dat_o[20] ,
+ \wbd_glbl_dat_o[19] ,
+ \wbd_glbl_dat_o[18] ,
+ \wbd_glbl_dat_o[17] ,
+ \wbd_glbl_dat_o[16] ,
+ \wbd_glbl_dat_o[15] ,
+ \wbd_glbl_dat_o[14] ,
+ \wbd_glbl_dat_o[13] ,
+ \wbd_glbl_dat_o[12] ,
+ \wbd_glbl_dat_o[11] ,
+ \wbd_glbl_dat_o[10] ,
+ \wbd_glbl_dat_o[9] ,
+ \wbd_glbl_dat_o[8] ,
+ \wbd_glbl_dat_o[7] ,
+ \wbd_glbl_dat_o[6] ,
+ \wbd_glbl_dat_o[5] ,
+ \wbd_glbl_dat_o[4] ,
+ \wbd_glbl_dat_o[3] ,
+ \wbd_glbl_dat_o[2] ,
+ \wbd_glbl_dat_o[1] ,
+ \wbd_glbl_dat_o[0] }),
+ .sflash_di({\sflash_di[3] ,
+ \sflash_di[2] ,
+ \sflash_di[1] ,
+ \sflash_di[0] }),
+ .sflash_do({\sflash_do[3] ,
+ \sflash_do[2] ,
+ \sflash_do[1] ,
+ \sflash_do[0] }),
+ .sflash_oen({\sflash_oen[3] ,
+ \sflash_oen[2] ,
+ \sflash_oen[1] ,
+ \sflash_oen[0] }),
+ .sflash_ss({\spi_csn[3] ,
+ \spi_csn[2] ,
+ \spi_csn[1] ,
+ \spi_csn[0] }),
+ .spim_ssn({\sspim_ssn[3] ,
+ \sspim_ssn[2] ,
+ \sspim_ssn[1] ,
+ \sspim_ssn[0] }),
+ .uart_rst_n({\uart_rst_n[1] ,
+ \uart_rst_n[0] }),
+ .uart_rxd({\uart_rxd[1] ,
+ \uart_rxd[0] }),
+ .uart_txd({\uart_txd[1] ,
+ \uart_txd[0] }),
+ .user_irq({user_irq[2],
+ user_irq[1],
+ user_irq[0]}));
+ digital_pll u_pll (.VGND(vssd1),
+ .VPWR(vccd1),
+ .dco(cfg_dco_mode),
+ .enable(cfg_pll_enb),
+ .osc(pll_ref_clk),
+ .resetb(wbd_pll_rst_n),
+ .clockp({\pll_clk_out[1] ,
+ \pll_clk_out[0] }),
+ .div({\cfg_pll_fed_div[4] ,
+ \cfg_pll_fed_div[3] ,
+ \cfg_pll_fed_div[2] ,
+ \cfg_pll_fed_div[1] ,
+ \cfg_pll_fed_div[0] }),
+ .ext_trim({\cfg_dc_trim[25] ,
+ \cfg_dc_trim[24] ,
+ \cfg_dc_trim[23] ,
+ \cfg_dc_trim[22] ,
+ \cfg_dc_trim[21] ,
+ \cfg_dc_trim[20] ,
+ \cfg_dc_trim[19] ,
+ \cfg_dc_trim[18] ,
+ \cfg_dc_trim[17] ,
+ \cfg_dc_trim[16] ,
+ \cfg_dc_trim[15] ,
+ \cfg_dc_trim[14] ,
+ \cfg_dc_trim[13] ,
+ \cfg_dc_trim[12] ,
+ \cfg_dc_trim[11] ,
+ \cfg_dc_trim[10] ,
+ \cfg_dc_trim[9] ,
+ \cfg_dc_trim[8] ,
+ \cfg_dc_trim[7] ,
+ \cfg_dc_trim[6] ,
+ \cfg_dc_trim[5] ,
+ \cfg_dc_trim[4] ,
+ \cfg_dc_trim[3] ,
+ \cfg_dc_trim[2] ,
+ \cfg_dc_trim[1] ,
+ \cfg_dc_trim[0] }));
+ qspim_top u_qspi_master (.mclk(wbd_clk_spi),
+ .rst_n(qspim_rst_n),
+ .spi_clk(sflash_sck),
+ .vccd1(vccd1),
+ .vssd1(vssd1),
+ .wbd_ack_o(wbd_spim_ack_i),
+ .wbd_bry_i(wbd_spim_bry_o),
+ .wbd_clk_int(wbd_clk_qspi_rp),
+ .wbd_clk_spi(wbd_clk_spi),
+ .wbd_err_o(wbd_spim_err_i),
+ .wbd_lack_o(wbd_spim_lack_i),
+ .wbd_stb_i(wbd_spim_stb_o),
+ .wbd_we_i(wbd_spim_we_o),
+ .cfg_cska_sp_co({\cfg_cska_qspi_co_rp[3] ,
+ \cfg_cska_qspi_co_rp[2] ,
+ \cfg_cska_qspi_co_rp[1] ,
+ \cfg_cska_qspi_co_rp[0] }),
+ .cfg_cska_spi({\cfg_cska_qspi_rp[3] ,
+ \cfg_cska_qspi_rp[2] ,
+ \cfg_cska_qspi_rp[1] ,
+ \cfg_cska_qspi_rp[0] }),
+ .spi_csn({\spi_csn[3] ,
+ \spi_csn[2] ,
+ \spi_csn[1] ,
+ \spi_csn[0] }),
+ .spi_debug({la_data_out[95],
+ la_data_out[94],
+ la_data_out[93],
+ la_data_out[92],
+ la_data_out[91],
+ la_data_out[90],
+ la_data_out[89],
+ la_data_out[88],
+ la_data_out[87],
+ la_data_out[86],
+ la_data_out[85],
+ la_data_out[84],
+ la_data_out[83],
+ la_data_out[82],
+ la_data_out[81],
+ la_data_out[80],
+ la_data_out[79],
+ la_data_out[78],
+ la_data_out[77],
+ la_data_out[76],
+ la_data_out[75],
+ la_data_out[74],
+ la_data_out[73],
+ la_data_out[72],
+ la_data_out[71],
+ la_data_out[70],
+ la_data_out[69],
+ la_data_out[68],
+ la_data_out[67],
+ la_data_out[66],
+ la_data_out[65],
+ la_data_out[64]}),
+ .spi_oen({\sflash_oen[3] ,
+ \sflash_oen[2] ,
+ \sflash_oen[1] ,
+ \sflash_oen[0] }),
+ .spi_sdi({\sflash_di[3] ,
+ \sflash_di[2] ,
+ \sflash_di[1] ,
+ \sflash_di[0] }),
+ .spi_sdo({\sflash_do[3] ,
+ \sflash_do[2] ,
+ \sflash_do[1] ,
+ \sflash_do[0] }),
+ .wbd_adr_i({\wbd_spim_adr_o[31] ,
+ \wbd_spim_adr_o[30] ,
+ \wbd_spim_adr_o[29] ,
+ \wbd_spim_adr_o[28] ,
+ \wbd_spim_adr_o[27] ,
+ \wbd_spim_adr_o[26] ,
+ \wbd_spim_adr_o[25] ,
+ \wbd_spim_adr_o[24] ,
+ \wbd_spim_adr_o[23] ,
+ \wbd_spim_adr_o[22] ,
+ \wbd_spim_adr_o[21] ,
+ \wbd_spim_adr_o[20] ,
+ \wbd_spim_adr_o[19] ,
+ \wbd_spim_adr_o[18] ,
+ \wbd_spim_adr_o[17] ,
+ \wbd_spim_adr_o[16] ,
+ \wbd_spim_adr_o[15] ,
+ \wbd_spim_adr_o[14] ,
+ \wbd_spim_adr_o[13] ,
+ \wbd_spim_adr_o[12] ,
+ \wbd_spim_adr_o[11] ,
+ \wbd_spim_adr_o[10] ,
+ \wbd_spim_adr_o[9] ,
+ \wbd_spim_adr_o[8] ,
+ \wbd_spim_adr_o[7] ,
+ \wbd_spim_adr_o[6] ,
+ \wbd_spim_adr_o[5] ,
+ \wbd_spim_adr_o[4] ,
+ \wbd_spim_adr_o[3] ,
+ \wbd_spim_adr_o[2] ,
+ \wbd_spim_adr_o[1] ,
+ \wbd_spim_adr_o[0] }),
+ .wbd_bl_i({\wbd_spim_bl_o[9] ,
+ \wbd_spim_bl_o[8] ,
+ \wbd_spim_bl_o[7] ,
+ \wbd_spim_bl_o[6] ,
+ \wbd_spim_bl_o[5] ,
+ \wbd_spim_bl_o[4] ,
+ \wbd_spim_bl_o[3] ,
+ \wbd_spim_bl_o[2] ,
+ \wbd_spim_bl_o[1] ,
+ \wbd_spim_bl_o[0] }),
+ .wbd_dat_i({\wbd_spim_dat_o[31] ,
+ \wbd_spim_dat_o[30] ,
+ \wbd_spim_dat_o[29] ,
+ \wbd_spim_dat_o[28] ,
+ \wbd_spim_dat_o[27] ,
+ \wbd_spim_dat_o[26] ,
+ \wbd_spim_dat_o[25] ,
+ \wbd_spim_dat_o[24] ,
+ \wbd_spim_dat_o[23] ,
+ \wbd_spim_dat_o[22] ,
+ \wbd_spim_dat_o[21] ,
+ \wbd_spim_dat_o[20] ,
+ \wbd_spim_dat_o[19] ,
+ \wbd_spim_dat_o[18] ,
+ \wbd_spim_dat_o[17] ,
+ \wbd_spim_dat_o[16] ,
+ \wbd_spim_dat_o[15] ,
+ \wbd_spim_dat_o[14] ,
+ \wbd_spim_dat_o[13] ,
+ \wbd_spim_dat_o[12] ,
+ \wbd_spim_dat_o[11] ,
+ \wbd_spim_dat_o[10] ,
+ \wbd_spim_dat_o[9] ,
+ \wbd_spim_dat_o[8] ,
+ \wbd_spim_dat_o[7] ,
+ \wbd_spim_dat_o[6] ,
+ \wbd_spim_dat_o[5] ,
+ \wbd_spim_dat_o[4] ,
+ \wbd_spim_dat_o[3] ,
+ \wbd_spim_dat_o[2] ,
+ \wbd_spim_dat_o[1] ,
+ \wbd_spim_dat_o[0] }),
+ .wbd_dat_o({\wbd_spim_dat_i[31] ,
+ \wbd_spim_dat_i[30] ,
+ \wbd_spim_dat_i[29] ,
+ \wbd_spim_dat_i[28] ,
+ \wbd_spim_dat_i[27] ,
+ \wbd_spim_dat_i[26] ,
+ \wbd_spim_dat_i[25] ,
+ \wbd_spim_dat_i[24] ,
+ \wbd_spim_dat_i[23] ,
+ \wbd_spim_dat_i[22] ,
+ \wbd_spim_dat_i[21] ,
+ \wbd_spim_dat_i[20] ,
+ \wbd_spim_dat_i[19] ,
+ \wbd_spim_dat_i[18] ,
+ \wbd_spim_dat_i[17] ,
+ \wbd_spim_dat_i[16] ,
+ \wbd_spim_dat_i[15] ,
+ \wbd_spim_dat_i[14] ,
+ \wbd_spim_dat_i[13] ,
+ \wbd_spim_dat_i[12] ,
+ \wbd_spim_dat_i[11] ,
+ \wbd_spim_dat_i[10] ,
+ \wbd_spim_dat_i[9] ,
+ \wbd_spim_dat_i[8] ,
+ \wbd_spim_dat_i[7] ,
+ \wbd_spim_dat_i[6] ,
+ \wbd_spim_dat_i[5] ,
+ \wbd_spim_dat_i[4] ,
+ \wbd_spim_dat_i[3] ,
+ \wbd_spim_dat_i[2] ,
+ \wbd_spim_dat_i[1] ,
+ \wbd_spim_dat_i[0] }),
+ .wbd_sel_i({\wbd_spim_sel_o[3] ,
+ \wbd_spim_sel_o[2] ,
+ \wbd_spim_sel_o[1] ,
+ \wbd_spim_sel_o[0] }));
+ ycr_core_top \u_riscv_top.i_core_top_0 (.clk(\u_riscv_top.core_clk ),
+ .clk_o(\u_riscv_top.core_clk_out[0] ),
+ .core2dmem_cmd_o(\u_riscv_top.core0_dmem_cmd ),
+ .core2dmem_req_o(\u_riscv_top.core0_dmem_req ),
+ .core2imem_cmd_o(\u_riscv_top.core0_imem_cmd ),
+ .core2imem_req_o(\u_riscv_top.core0_imem_req ),
+ .core_irq_mtimer_i(\u_riscv_top.core0_timer_irq ),
+ .core_irq_soft_i(\u_riscv_top.core0_soft_irq ),
+ .cpu_rst_n(\u_riscv_top.cpu_core_rst_n[0] ),
+ .dmem2core_req_ack_i(\u_riscv_top.core0_dmem_req_ack ),
+ .imem2core_req_ack_i(\u_riscv_top.core0_imem_req_ack ),
+ .pwrup_rst_n(\u_riscv_top.pwrup_rst_n ),
+ .rst_n(\u_riscv_top.pwrup_rst_n ),
+ .vccd1(vccd1),
+ .vssd1(vssd1),
+ .core2dmem_addr_o({\u_riscv_top.core0_dmem_addr[31] ,
+ \u_riscv_top.core0_dmem_addr[30] ,
+ \u_riscv_top.core0_dmem_addr[29] ,
+ \u_riscv_top.core0_dmem_addr[28] ,
+ \u_riscv_top.core0_dmem_addr[27] ,
+ \u_riscv_top.core0_dmem_addr[26] ,
+ \u_riscv_top.core0_dmem_addr[25] ,
+ \u_riscv_top.core0_dmem_addr[24] ,
+ \u_riscv_top.core0_dmem_addr[23] ,
+ \u_riscv_top.core0_dmem_addr[22] ,
+ \u_riscv_top.core0_dmem_addr[21] ,
+ \u_riscv_top.core0_dmem_addr[20] ,
+ \u_riscv_top.core0_dmem_addr[19] ,
+ \u_riscv_top.core0_dmem_addr[18] ,
+ \u_riscv_top.core0_dmem_addr[17] ,
+ \u_riscv_top.core0_dmem_addr[16] ,
+ \u_riscv_top.core0_dmem_addr[15] ,
+ \u_riscv_top.core0_dmem_addr[14] ,
+ \u_riscv_top.core0_dmem_addr[13] ,
+ \u_riscv_top.core0_dmem_addr[12] ,
+ \u_riscv_top.core0_dmem_addr[11] ,
+ \u_riscv_top.core0_dmem_addr[10] ,
+ \u_riscv_top.core0_dmem_addr[9] ,
+ \u_riscv_top.core0_dmem_addr[8] ,
+ \u_riscv_top.core0_dmem_addr[7] ,
+ \u_riscv_top.core0_dmem_addr[6] ,
+ \u_riscv_top.core0_dmem_addr[5] ,
+ \u_riscv_top.core0_dmem_addr[4] ,
+ \u_riscv_top.core0_dmem_addr[3] ,
+ \u_riscv_top.core0_dmem_addr[2] ,
+ \u_riscv_top.core0_dmem_addr[1] ,
+ \u_riscv_top.core0_dmem_addr[0] }),
+ .core2dmem_wdata_o({\u_riscv_top.core0_dmem_wdata[31] ,
+ \u_riscv_top.core0_dmem_wdata[30] ,
+ \u_riscv_top.core0_dmem_wdata[29] ,
+ \u_riscv_top.core0_dmem_wdata[28] ,
+ \u_riscv_top.core0_dmem_wdata[27] ,
+ \u_riscv_top.core0_dmem_wdata[26] ,
+ \u_riscv_top.core0_dmem_wdata[25] ,
+ \u_riscv_top.core0_dmem_wdata[24] ,
+ \u_riscv_top.core0_dmem_wdata[23] ,
+ \u_riscv_top.core0_dmem_wdata[22] ,
+ \u_riscv_top.core0_dmem_wdata[21] ,
+ \u_riscv_top.core0_dmem_wdata[20] ,
+ \u_riscv_top.core0_dmem_wdata[19] ,
+ \u_riscv_top.core0_dmem_wdata[18] ,
+ \u_riscv_top.core0_dmem_wdata[17] ,
+ \u_riscv_top.core0_dmem_wdata[16] ,
+ \u_riscv_top.core0_dmem_wdata[15] ,
+ \u_riscv_top.core0_dmem_wdata[14] ,
+ \u_riscv_top.core0_dmem_wdata[13] ,
+ \u_riscv_top.core0_dmem_wdata[12] ,
+ \u_riscv_top.core0_dmem_wdata[11] ,
+ \u_riscv_top.core0_dmem_wdata[10] ,
+ \u_riscv_top.core0_dmem_wdata[9] ,
+ \u_riscv_top.core0_dmem_wdata[8] ,
+ \u_riscv_top.core0_dmem_wdata[7] ,
+ \u_riscv_top.core0_dmem_wdata[6] ,
+ \u_riscv_top.core0_dmem_wdata[5] ,
+ \u_riscv_top.core0_dmem_wdata[4] ,
+ \u_riscv_top.core0_dmem_wdata[3] ,
+ \u_riscv_top.core0_dmem_wdata[2] ,
+ \u_riscv_top.core0_dmem_wdata[1] ,
+ \u_riscv_top.core0_dmem_wdata[0] }),
+ .core2dmem_width_o({\u_riscv_top.core0_dmem_width[1] ,
+ \u_riscv_top.core0_dmem_width[0] }),
+ .core2imem_addr_o({\u_riscv_top.core0_imem_addr[31] ,
+ \u_riscv_top.core0_imem_addr[30] ,
+ \u_riscv_top.core0_imem_addr[29] ,
+ \u_riscv_top.core0_imem_addr[28] ,
+ \u_riscv_top.core0_imem_addr[27] ,
+ \u_riscv_top.core0_imem_addr[26] ,
+ \u_riscv_top.core0_imem_addr[25] ,
+ \u_riscv_top.core0_imem_addr[24] ,
+ \u_riscv_top.core0_imem_addr[23] ,
+ \u_riscv_top.core0_imem_addr[22] ,
+ \u_riscv_top.core0_imem_addr[21] ,
+ \u_riscv_top.core0_imem_addr[20] ,
+ \u_riscv_top.core0_imem_addr[19] ,
+ \u_riscv_top.core0_imem_addr[18] ,
+ \u_riscv_top.core0_imem_addr[17] ,
+ \u_riscv_top.core0_imem_addr[16] ,
+ \u_riscv_top.core0_imem_addr[15] ,
+ \u_riscv_top.core0_imem_addr[14] ,
+ \u_riscv_top.core0_imem_addr[13] ,
+ \u_riscv_top.core0_imem_addr[12] ,
+ \u_riscv_top.core0_imem_addr[11] ,
+ \u_riscv_top.core0_imem_addr[10] ,
+ \u_riscv_top.core0_imem_addr[9] ,
+ \u_riscv_top.core0_imem_addr[8] ,
+ \u_riscv_top.core0_imem_addr[7] ,
+ \u_riscv_top.core0_imem_addr[6] ,
+ \u_riscv_top.core0_imem_addr[5] ,
+ \u_riscv_top.core0_imem_addr[4] ,
+ \u_riscv_top.core0_imem_addr[3] ,
+ \u_riscv_top.core0_imem_addr[2] ,
+ \u_riscv_top.core0_imem_addr[1] ,
+ \u_riscv_top.core0_imem_addr[0] }),
+ .core2imem_bl_o({\u_riscv_top.core0_imem_bl[2] ,
+ \u_riscv_top.core0_imem_bl[1] ,
+ \u_riscv_top.core0_imem_bl[0] }),
+ .core_debug({\u_riscv_top.core0_debug[48] ,
+ \u_riscv_top.core0_debug[47] ,
+ \u_riscv_top.core0_debug[46] ,
+ \u_riscv_top.core0_debug[45] ,
+ \u_riscv_top.core0_debug[44] ,
+ \u_riscv_top.core0_debug[43] ,
+ \u_riscv_top.core0_debug[42] ,
+ \u_riscv_top.core0_debug[41] ,
+ \u_riscv_top.core0_debug[40] ,
+ \u_riscv_top.core0_debug[39] ,
+ \u_riscv_top.core0_debug[38] ,
+ \u_riscv_top.core0_debug[37] ,
+ \u_riscv_top.core0_debug[36] ,
+ \u_riscv_top.core0_debug[35] ,
+ \u_riscv_top.core0_debug[34] ,
+ \u_riscv_top.core0_debug[33] ,
+ \u_riscv_top.core0_debug[32] ,
+ \u_riscv_top.core0_debug[31] ,
+ \u_riscv_top.core0_debug[30] ,
+ \u_riscv_top.core0_debug[29] ,
+ \u_riscv_top.core0_debug[28] ,
+ \u_riscv_top.core0_debug[27] ,
+ \u_riscv_top.core0_debug[26] ,
+ \u_riscv_top.core0_debug[25] ,
+ \u_riscv_top.core0_debug[24] ,
+ \u_riscv_top.core0_debug[23] ,
+ \u_riscv_top.core0_debug[22] ,
+ \u_riscv_top.core0_debug[21] ,
+ \u_riscv_top.core0_debug[20] ,
+ \u_riscv_top.core0_debug[19] ,
+ \u_riscv_top.core0_debug[18] ,
+ \u_riscv_top.core0_debug[17] ,
+ \u_riscv_top.core0_debug[16] ,
+ \u_riscv_top.core0_debug[15] ,
+ \u_riscv_top.core0_debug[14] ,
+ \u_riscv_top.core0_debug[13] ,
+ \u_riscv_top.core0_debug[12] ,
+ \u_riscv_top.core0_debug[11] ,
+ \u_riscv_top.core0_debug[10] ,
+ \u_riscv_top.core0_debug[9] ,
+ \u_riscv_top.core0_debug[8] ,
+ \u_riscv_top.core0_debug[7] ,
+ \u_riscv_top.core0_debug[6] ,
+ \u_riscv_top.core0_debug[5] ,
+ \u_riscv_top.core0_debug[4] ,
+ \u_riscv_top.core0_debug[3] ,
+ \u_riscv_top.core0_debug[2] ,
+ \u_riscv_top.core0_debug[1] ,
+ \u_riscv_top.core0_debug[0] }),
+ .core_irq_lines_i({\u_riscv_top.core0_irq_lines[15] ,
+ \u_riscv_top.core0_irq_lines[14] ,
+ \u_riscv_top.core0_irq_lines[13] ,
+ \u_riscv_top.core0_irq_lines[12] ,
+ \u_riscv_top.core0_irq_lines[11] ,
+ \u_riscv_top.core0_irq_lines[10] ,
+ \u_riscv_top.core0_irq_lines[9] ,
+ \u_riscv_top.core0_irq_lines[8] ,
+ \u_riscv_top.core0_irq_lines[7] ,
+ \u_riscv_top.core0_irq_lines[6] ,
+ \u_riscv_top.core0_irq_lines[5] ,
+ \u_riscv_top.core0_irq_lines[4] ,
+ \u_riscv_top.core0_irq_lines[3] ,
+ \u_riscv_top.core0_irq_lines[2] ,
+ \u_riscv_top.core0_irq_lines[1] ,
+ \u_riscv_top.core0_irq_lines[0] }),
+ .core_mtimer_val_i({\u_riscv_top.core0_timer_val[63] ,
+ \u_riscv_top.core0_timer_val[62] ,
+ \u_riscv_top.core0_timer_val[61] ,
+ \u_riscv_top.core0_timer_val[60] ,
+ \u_riscv_top.core0_timer_val[59] ,
+ \u_riscv_top.core0_timer_val[58] ,
+ \u_riscv_top.core0_timer_val[57] ,
+ \u_riscv_top.core0_timer_val[56] ,
+ \u_riscv_top.core0_timer_val[55] ,
+ \u_riscv_top.core0_timer_val[54] ,
+ \u_riscv_top.core0_timer_val[53] ,
+ \u_riscv_top.core0_timer_val[52] ,
+ \u_riscv_top.core0_timer_val[51] ,
+ \u_riscv_top.core0_timer_val[50] ,
+ \u_riscv_top.core0_timer_val[49] ,
+ \u_riscv_top.core0_timer_val[48] ,
+ \u_riscv_top.core0_timer_val[47] ,
+ \u_riscv_top.core0_timer_val[46] ,
+ \u_riscv_top.core0_timer_val[45] ,
+ \u_riscv_top.core0_timer_val[44] ,
+ \u_riscv_top.core0_timer_val[43] ,
+ \u_riscv_top.core0_timer_val[42] ,
+ \u_riscv_top.core0_timer_val[41] ,
+ \u_riscv_top.core0_timer_val[40] ,
+ \u_riscv_top.core0_timer_val[39] ,
+ \u_riscv_top.core0_timer_val[38] ,
+ \u_riscv_top.core0_timer_val[37] ,
+ \u_riscv_top.core0_timer_val[36] ,
+ \u_riscv_top.core0_timer_val[35] ,
+ \u_riscv_top.core0_timer_val[34] ,
+ \u_riscv_top.core0_timer_val[33] ,
+ \u_riscv_top.core0_timer_val[32] ,
+ \u_riscv_top.core0_timer_val[31] ,
+ \u_riscv_top.core0_timer_val[30] ,
+ \u_riscv_top.core0_timer_val[29] ,
+ \u_riscv_top.core0_timer_val[28] ,
+ \u_riscv_top.core0_timer_val[27] ,
+ \u_riscv_top.core0_timer_val[26] ,
+ \u_riscv_top.core0_timer_val[25] ,
+ \u_riscv_top.core0_timer_val[24] ,
+ \u_riscv_top.core0_timer_val[23] ,
+ \u_riscv_top.core0_timer_val[22] ,
+ \u_riscv_top.core0_timer_val[21] ,
+ \u_riscv_top.core0_timer_val[20] ,
+ \u_riscv_top.core0_timer_val[19] ,
+ \u_riscv_top.core0_timer_val[18] ,
+ \u_riscv_top.core0_timer_val[17] ,
+ \u_riscv_top.core0_timer_val[16] ,
+ \u_riscv_top.core0_timer_val[15] ,
+ \u_riscv_top.core0_timer_val[14] ,
+ \u_riscv_top.core0_timer_val[13] ,
+ \u_riscv_top.core0_timer_val[12] ,
+ \u_riscv_top.core0_timer_val[11] ,
+ \u_riscv_top.core0_timer_val[10] ,
+ \u_riscv_top.core0_timer_val[9] ,
+ \u_riscv_top.core0_timer_val[8] ,
+ \u_riscv_top.core0_timer_val[7] ,
+ \u_riscv_top.core0_timer_val[6] ,
+ \u_riscv_top.core0_timer_val[5] ,
+ \u_riscv_top.core0_timer_val[4] ,
+ \u_riscv_top.core0_timer_val[3] ,
+ \u_riscv_top.core0_timer_val[2] ,
+ \u_riscv_top.core0_timer_val[1] ,
+ \u_riscv_top.core0_timer_val[0] }),
+ .core_uid({\u_riscv_top.core0_uid[1] ,
+ \u_riscv_top.core0_uid[0] }),
+ .dmem2core_rdata_i({\u_riscv_top.core0_dmem_rdata[31] ,
+ \u_riscv_top.core0_dmem_rdata[30] ,
+ \u_riscv_top.core0_dmem_rdata[29] ,
+ \u_riscv_top.core0_dmem_rdata[28] ,
+ \u_riscv_top.core0_dmem_rdata[27] ,
+ \u_riscv_top.core0_dmem_rdata[26] ,
+ \u_riscv_top.core0_dmem_rdata[25] ,
+ \u_riscv_top.core0_dmem_rdata[24] ,
+ \u_riscv_top.core0_dmem_rdata[23] ,
+ \u_riscv_top.core0_dmem_rdata[22] ,
+ \u_riscv_top.core0_dmem_rdata[21] ,
+ \u_riscv_top.core0_dmem_rdata[20] ,
+ \u_riscv_top.core0_dmem_rdata[19] ,
+ \u_riscv_top.core0_dmem_rdata[18] ,
+ \u_riscv_top.core0_dmem_rdata[17] ,
+ \u_riscv_top.core0_dmem_rdata[16] ,
+ \u_riscv_top.core0_dmem_rdata[15] ,
+ \u_riscv_top.core0_dmem_rdata[14] ,
+ \u_riscv_top.core0_dmem_rdata[13] ,
+ \u_riscv_top.core0_dmem_rdata[12] ,
+ \u_riscv_top.core0_dmem_rdata[11] ,
+ \u_riscv_top.core0_dmem_rdata[10] ,
+ \u_riscv_top.core0_dmem_rdata[9] ,
+ \u_riscv_top.core0_dmem_rdata[8] ,
+ \u_riscv_top.core0_dmem_rdata[7] ,
+ \u_riscv_top.core0_dmem_rdata[6] ,
+ \u_riscv_top.core0_dmem_rdata[5] ,
+ \u_riscv_top.core0_dmem_rdata[4] ,
+ \u_riscv_top.core0_dmem_rdata[3] ,
+ \u_riscv_top.core0_dmem_rdata[2] ,
+ \u_riscv_top.core0_dmem_rdata[1] ,
+ \u_riscv_top.core0_dmem_rdata[0] }),
+ .dmem2core_resp_i({\u_riscv_top.core0_dmem_resp[1] ,
+ \u_riscv_top.core0_dmem_resp[0] }),
+ .imem2core_rdata_i({\u_riscv_top.core0_imem_rdata[31] ,
+ \u_riscv_top.core0_imem_rdata[30] ,
+ \u_riscv_top.core0_imem_rdata[29] ,
+ \u_riscv_top.core0_imem_rdata[28] ,
+ \u_riscv_top.core0_imem_rdata[27] ,
+ \u_riscv_top.core0_imem_rdata[26] ,
+ \u_riscv_top.core0_imem_rdata[25] ,
+ \u_riscv_top.core0_imem_rdata[24] ,
+ \u_riscv_top.core0_imem_rdata[23] ,
+ \u_riscv_top.core0_imem_rdata[22] ,
+ \u_riscv_top.core0_imem_rdata[21] ,
+ \u_riscv_top.core0_imem_rdata[20] ,
+ \u_riscv_top.core0_imem_rdata[19] ,
+ \u_riscv_top.core0_imem_rdata[18] ,
+ \u_riscv_top.core0_imem_rdata[17] ,
+ \u_riscv_top.core0_imem_rdata[16] ,
+ \u_riscv_top.core0_imem_rdata[15] ,
+ \u_riscv_top.core0_imem_rdata[14] ,
+ \u_riscv_top.core0_imem_rdata[13] ,
+ \u_riscv_top.core0_imem_rdata[12] ,
+ \u_riscv_top.core0_imem_rdata[11] ,
+ \u_riscv_top.core0_imem_rdata[10] ,
+ \u_riscv_top.core0_imem_rdata[9] ,
+ \u_riscv_top.core0_imem_rdata[8] ,
+ \u_riscv_top.core0_imem_rdata[7] ,
+ \u_riscv_top.core0_imem_rdata[6] ,
+ \u_riscv_top.core0_imem_rdata[5] ,
+ \u_riscv_top.core0_imem_rdata[4] ,
+ \u_riscv_top.core0_imem_rdata[3] ,
+ \u_riscv_top.core0_imem_rdata[2] ,
+ \u_riscv_top.core0_imem_rdata[1] ,
+ \u_riscv_top.core0_imem_rdata[0] }),
+ .imem2core_resp_i({\u_riscv_top.core0_imem_resp[1] ,
+ \u_riscv_top.core0_imem_resp[0] }));
+ ycr_core_top \u_riscv_top.i_core_top_1 (.clk(\u_riscv_top.core_clk ),
+ .clk_o(\u_riscv_top.core_clk_out[1] ),
+ .core2dmem_cmd_o(\u_riscv_top.core1_dmem_cmd ),
+ .core2dmem_req_o(\u_riscv_top.core1_dmem_req ),
+ .core2imem_cmd_o(\u_riscv_top.core1_imem_cmd ),
+ .core2imem_req_o(\u_riscv_top.core1_imem_req ),
+ .core_irq_mtimer_i(\u_riscv_top.core1_timer_irq ),
+ .core_irq_soft_i(\u_riscv_top.core1_soft_irq ),
+ .cpu_rst_n(\u_riscv_top.cpu_core_rst_n[1] ),
+ .dmem2core_req_ack_i(\u_riscv_top.core1_dmem_req_ack ),
+ .imem2core_req_ack_i(\u_riscv_top.core1_imem_req_ack ),
+ .pwrup_rst_n(\u_riscv_top.pwrup_rst_n ),
+ .rst_n(\u_riscv_top.pwrup_rst_n ),
+ .vccd1(vccd1),
+ .vssd1(vssd1),
+ .core2dmem_addr_o({\u_riscv_top.core1_dmem_addr[31] ,
+ \u_riscv_top.core1_dmem_addr[30] ,
+ \u_riscv_top.core1_dmem_addr[29] ,
+ \u_riscv_top.core1_dmem_addr[28] ,
+ \u_riscv_top.core1_dmem_addr[27] ,
+ \u_riscv_top.core1_dmem_addr[26] ,
+ \u_riscv_top.core1_dmem_addr[25] ,
+ \u_riscv_top.core1_dmem_addr[24] ,
+ \u_riscv_top.core1_dmem_addr[23] ,
+ \u_riscv_top.core1_dmem_addr[22] ,
+ \u_riscv_top.core1_dmem_addr[21] ,
+ \u_riscv_top.core1_dmem_addr[20] ,
+ \u_riscv_top.core1_dmem_addr[19] ,
+ \u_riscv_top.core1_dmem_addr[18] ,
+ \u_riscv_top.core1_dmem_addr[17] ,
+ \u_riscv_top.core1_dmem_addr[16] ,
+ \u_riscv_top.core1_dmem_addr[15] ,
+ \u_riscv_top.core1_dmem_addr[14] ,
+ \u_riscv_top.core1_dmem_addr[13] ,
+ \u_riscv_top.core1_dmem_addr[12] ,
+ \u_riscv_top.core1_dmem_addr[11] ,
+ \u_riscv_top.core1_dmem_addr[10] ,
+ \u_riscv_top.core1_dmem_addr[9] ,
+ \u_riscv_top.core1_dmem_addr[8] ,
+ \u_riscv_top.core1_dmem_addr[7] ,
+ \u_riscv_top.core1_dmem_addr[6] ,
+ \u_riscv_top.core1_dmem_addr[5] ,
+ \u_riscv_top.core1_dmem_addr[4] ,
+ \u_riscv_top.core1_dmem_addr[3] ,
+ \u_riscv_top.core1_dmem_addr[2] ,
+ \u_riscv_top.core1_dmem_addr[1] ,
+ \u_riscv_top.core1_dmem_addr[0] }),
+ .core2dmem_wdata_o({\u_riscv_top.core1_dmem_wdata[31] ,
+ \u_riscv_top.core1_dmem_wdata[30] ,
+ \u_riscv_top.core1_dmem_wdata[29] ,
+ \u_riscv_top.core1_dmem_wdata[28] ,
+ \u_riscv_top.core1_dmem_wdata[27] ,
+ \u_riscv_top.core1_dmem_wdata[26] ,
+ \u_riscv_top.core1_dmem_wdata[25] ,
+ \u_riscv_top.core1_dmem_wdata[24] ,
+ \u_riscv_top.core1_dmem_wdata[23] ,
+ \u_riscv_top.core1_dmem_wdata[22] ,
+ \u_riscv_top.core1_dmem_wdata[21] ,
+ \u_riscv_top.core1_dmem_wdata[20] ,
+ \u_riscv_top.core1_dmem_wdata[19] ,
+ \u_riscv_top.core1_dmem_wdata[18] ,
+ \u_riscv_top.core1_dmem_wdata[17] ,
+ \u_riscv_top.core1_dmem_wdata[16] ,
+ \u_riscv_top.core1_dmem_wdata[15] ,
+ \u_riscv_top.core1_dmem_wdata[14] ,
+ \u_riscv_top.core1_dmem_wdata[13] ,
+ \u_riscv_top.core1_dmem_wdata[12] ,
+ \u_riscv_top.core1_dmem_wdata[11] ,
+ \u_riscv_top.core1_dmem_wdata[10] ,
+ \u_riscv_top.core1_dmem_wdata[9] ,
+ \u_riscv_top.core1_dmem_wdata[8] ,
+ \u_riscv_top.core1_dmem_wdata[7] ,
+ \u_riscv_top.core1_dmem_wdata[6] ,
+ \u_riscv_top.core1_dmem_wdata[5] ,
+ \u_riscv_top.core1_dmem_wdata[4] ,
+ \u_riscv_top.core1_dmem_wdata[3] ,
+ \u_riscv_top.core1_dmem_wdata[2] ,
+ \u_riscv_top.core1_dmem_wdata[1] ,
+ \u_riscv_top.core1_dmem_wdata[0] }),
+ .core2dmem_width_o({\u_riscv_top.core1_dmem_width[1] ,
+ \u_riscv_top.core1_dmem_width[0] }),
+ .core2imem_addr_o({\u_riscv_top.core1_imem_addr[31] ,
+ \u_riscv_top.core1_imem_addr[30] ,
+ \u_riscv_top.core1_imem_addr[29] ,
+ \u_riscv_top.core1_imem_addr[28] ,
+ \u_riscv_top.core1_imem_addr[27] ,
+ \u_riscv_top.core1_imem_addr[26] ,
+ \u_riscv_top.core1_imem_addr[25] ,
+ \u_riscv_top.core1_imem_addr[24] ,
+ \u_riscv_top.core1_imem_addr[23] ,
+ \u_riscv_top.core1_imem_addr[22] ,
+ \u_riscv_top.core1_imem_addr[21] ,
+ \u_riscv_top.core1_imem_addr[20] ,
+ \u_riscv_top.core1_imem_addr[19] ,
+ \u_riscv_top.core1_imem_addr[18] ,
+ \u_riscv_top.core1_imem_addr[17] ,
+ \u_riscv_top.core1_imem_addr[16] ,
+ \u_riscv_top.core1_imem_addr[15] ,
+ \u_riscv_top.core1_imem_addr[14] ,
+ \u_riscv_top.core1_imem_addr[13] ,
+ \u_riscv_top.core1_imem_addr[12] ,
+ \u_riscv_top.core1_imem_addr[11] ,
+ \u_riscv_top.core1_imem_addr[10] ,
+ \u_riscv_top.core1_imem_addr[9] ,
+ \u_riscv_top.core1_imem_addr[8] ,
+ \u_riscv_top.core1_imem_addr[7] ,
+ \u_riscv_top.core1_imem_addr[6] ,
+ \u_riscv_top.core1_imem_addr[5] ,
+ \u_riscv_top.core1_imem_addr[4] ,
+ \u_riscv_top.core1_imem_addr[3] ,
+ \u_riscv_top.core1_imem_addr[2] ,
+ \u_riscv_top.core1_imem_addr[1] ,
+ \u_riscv_top.core1_imem_addr[0] }),
+ .core2imem_bl_o({\u_riscv_top.core1_imem_bl[2] ,
+ \u_riscv_top.core1_imem_bl[1] ,
+ \u_riscv_top.core1_imem_bl[0] }),
+ .core_debug({\u_riscv_top.core1_debug[48] ,
+ \u_riscv_top.core1_debug[47] ,
+ \u_riscv_top.core1_debug[46] ,
+ \u_riscv_top.core1_debug[45] ,
+ \u_riscv_top.core1_debug[44] ,
+ \u_riscv_top.core1_debug[43] ,
+ \u_riscv_top.core1_debug[42] ,
+ \u_riscv_top.core1_debug[41] ,
+ \u_riscv_top.core1_debug[40] ,
+ \u_riscv_top.core1_debug[39] ,
+ \u_riscv_top.core1_debug[38] ,
+ \u_riscv_top.core1_debug[37] ,
+ \u_riscv_top.core1_debug[36] ,
+ \u_riscv_top.core1_debug[35] ,
+ \u_riscv_top.core1_debug[34] ,
+ \u_riscv_top.core1_debug[33] ,
+ \u_riscv_top.core1_debug[32] ,
+ \u_riscv_top.core1_debug[31] ,
+ \u_riscv_top.core1_debug[30] ,
+ \u_riscv_top.core1_debug[29] ,
+ \u_riscv_top.core1_debug[28] ,
+ \u_riscv_top.core1_debug[27] ,
+ \u_riscv_top.core1_debug[26] ,
+ \u_riscv_top.core1_debug[25] ,
+ \u_riscv_top.core1_debug[24] ,
+ \u_riscv_top.core1_debug[23] ,
+ \u_riscv_top.core1_debug[22] ,
+ \u_riscv_top.core1_debug[21] ,
+ \u_riscv_top.core1_debug[20] ,
+ \u_riscv_top.core1_debug[19] ,
+ \u_riscv_top.core1_debug[18] ,
+ \u_riscv_top.core1_debug[17] ,
+ \u_riscv_top.core1_debug[16] ,
+ \u_riscv_top.core1_debug[15] ,
+ \u_riscv_top.core1_debug[14] ,
+ \u_riscv_top.core1_debug[13] ,
+ \u_riscv_top.core1_debug[12] ,
+ \u_riscv_top.core1_debug[11] ,
+ \u_riscv_top.core1_debug[10] ,
+ \u_riscv_top.core1_debug[9] ,
+ \u_riscv_top.core1_debug[8] ,
+ \u_riscv_top.core1_debug[7] ,
+ \u_riscv_top.core1_debug[6] ,
+ \u_riscv_top.core1_debug[5] ,
+ \u_riscv_top.core1_debug[4] ,
+ \u_riscv_top.core1_debug[3] ,
+ \u_riscv_top.core1_debug[2] ,
+ \u_riscv_top.core1_debug[1] ,
+ \u_riscv_top.core1_debug[0] }),
+ .core_irq_lines_i({\u_riscv_top.core1_irq_lines[15] ,
+ \u_riscv_top.core1_irq_lines[14] ,
+ \u_riscv_top.core1_irq_lines[13] ,
+ \u_riscv_top.core1_irq_lines[12] ,
+ \u_riscv_top.core1_irq_lines[11] ,
+ \u_riscv_top.core1_irq_lines[10] ,
+ \u_riscv_top.core1_irq_lines[9] ,
+ \u_riscv_top.core1_irq_lines[8] ,
+ \u_riscv_top.core1_irq_lines[7] ,
+ \u_riscv_top.core1_irq_lines[6] ,
+ \u_riscv_top.core1_irq_lines[5] ,
+ \u_riscv_top.core1_irq_lines[4] ,
+ \u_riscv_top.core1_irq_lines[3] ,
+ \u_riscv_top.core1_irq_lines[2] ,
+ \u_riscv_top.core1_irq_lines[1] ,
+ \u_riscv_top.core1_irq_lines[0] }),
+ .core_mtimer_val_i({\u_riscv_top.core1_timer_val[63] ,
+ \u_riscv_top.core1_timer_val[62] ,
+ \u_riscv_top.core1_timer_val[61] ,
+ \u_riscv_top.core1_timer_val[60] ,
+ \u_riscv_top.core1_timer_val[59] ,
+ \u_riscv_top.core1_timer_val[58] ,
+ \u_riscv_top.core1_timer_val[57] ,
+ \u_riscv_top.core1_timer_val[56] ,
+ \u_riscv_top.core1_timer_val[55] ,
+ \u_riscv_top.core1_timer_val[54] ,
+ \u_riscv_top.core1_timer_val[53] ,
+ \u_riscv_top.core1_timer_val[52] ,
+ \u_riscv_top.core1_timer_val[51] ,
+ \u_riscv_top.core1_timer_val[50] ,
+ \u_riscv_top.core1_timer_val[49] ,
+ \u_riscv_top.core1_timer_val[48] ,
+ \u_riscv_top.core1_timer_val[47] ,
+ \u_riscv_top.core1_timer_val[46] ,
+ \u_riscv_top.core1_timer_val[45] ,
+ \u_riscv_top.core1_timer_val[44] ,
+ \u_riscv_top.core1_timer_val[43] ,
+ \u_riscv_top.core1_timer_val[42] ,
+ \u_riscv_top.core1_timer_val[41] ,
+ \u_riscv_top.core1_timer_val[40] ,
+ \u_riscv_top.core1_timer_val[39] ,
+ \u_riscv_top.core1_timer_val[38] ,
+ \u_riscv_top.core1_timer_val[37] ,
+ \u_riscv_top.core1_timer_val[36] ,
+ \u_riscv_top.core1_timer_val[35] ,
+ \u_riscv_top.core1_timer_val[34] ,
+ \u_riscv_top.core1_timer_val[33] ,
+ \u_riscv_top.core1_timer_val[32] ,
+ \u_riscv_top.core1_timer_val[31] ,
+ \u_riscv_top.core1_timer_val[30] ,
+ \u_riscv_top.core1_timer_val[29] ,
+ \u_riscv_top.core1_timer_val[28] ,
+ \u_riscv_top.core1_timer_val[27] ,
+ \u_riscv_top.core1_timer_val[26] ,
+ \u_riscv_top.core1_timer_val[25] ,
+ \u_riscv_top.core1_timer_val[24] ,
+ \u_riscv_top.core1_timer_val[23] ,
+ \u_riscv_top.core1_timer_val[22] ,
+ \u_riscv_top.core1_timer_val[21] ,
+ \u_riscv_top.core1_timer_val[20] ,
+ \u_riscv_top.core1_timer_val[19] ,
+ \u_riscv_top.core1_timer_val[18] ,
+ \u_riscv_top.core1_timer_val[17] ,
+ \u_riscv_top.core1_timer_val[16] ,
+ \u_riscv_top.core1_timer_val[15] ,
+ \u_riscv_top.core1_timer_val[14] ,
+ \u_riscv_top.core1_timer_val[13] ,
+ \u_riscv_top.core1_timer_val[12] ,
+ \u_riscv_top.core1_timer_val[11] ,
+ \u_riscv_top.core1_timer_val[10] ,
+ \u_riscv_top.core1_timer_val[9] ,
+ \u_riscv_top.core1_timer_val[8] ,
+ \u_riscv_top.core1_timer_val[7] ,
+ \u_riscv_top.core1_timer_val[6] ,
+ \u_riscv_top.core1_timer_val[5] ,
+ \u_riscv_top.core1_timer_val[4] ,
+ \u_riscv_top.core1_timer_val[3] ,
+ \u_riscv_top.core1_timer_val[2] ,
+ \u_riscv_top.core1_timer_val[1] ,
+ \u_riscv_top.core1_timer_val[0] }),
+ .core_uid({\u_riscv_top.core1_uid[1] ,
+ \u_riscv_top.core1_uid[0] }),
+ .dmem2core_rdata_i({\u_riscv_top.core1_dmem_rdata[31] ,
+ \u_riscv_top.core1_dmem_rdata[30] ,
+ \u_riscv_top.core1_dmem_rdata[29] ,
+ \u_riscv_top.core1_dmem_rdata[28] ,
+ \u_riscv_top.core1_dmem_rdata[27] ,
+ \u_riscv_top.core1_dmem_rdata[26] ,
+ \u_riscv_top.core1_dmem_rdata[25] ,
+ \u_riscv_top.core1_dmem_rdata[24] ,
+ \u_riscv_top.core1_dmem_rdata[23] ,
+ \u_riscv_top.core1_dmem_rdata[22] ,
+ \u_riscv_top.core1_dmem_rdata[21] ,
+ \u_riscv_top.core1_dmem_rdata[20] ,
+ \u_riscv_top.core1_dmem_rdata[19] ,
+ \u_riscv_top.core1_dmem_rdata[18] ,
+ \u_riscv_top.core1_dmem_rdata[17] ,
+ \u_riscv_top.core1_dmem_rdata[16] ,
+ \u_riscv_top.core1_dmem_rdata[15] ,
+ \u_riscv_top.core1_dmem_rdata[14] ,
+ \u_riscv_top.core1_dmem_rdata[13] ,
+ \u_riscv_top.core1_dmem_rdata[12] ,
+ \u_riscv_top.core1_dmem_rdata[11] ,
+ \u_riscv_top.core1_dmem_rdata[10] ,
+ \u_riscv_top.core1_dmem_rdata[9] ,
+ \u_riscv_top.core1_dmem_rdata[8] ,
+ \u_riscv_top.core1_dmem_rdata[7] ,
+ \u_riscv_top.core1_dmem_rdata[6] ,
+ \u_riscv_top.core1_dmem_rdata[5] ,
+ \u_riscv_top.core1_dmem_rdata[4] ,
+ \u_riscv_top.core1_dmem_rdata[3] ,
+ \u_riscv_top.core1_dmem_rdata[2] ,
+ \u_riscv_top.core1_dmem_rdata[1] ,
+ \u_riscv_top.core1_dmem_rdata[0] }),
+ .dmem2core_resp_i({\u_riscv_top.core1_dmem_resp[1] ,
+ \u_riscv_top.core1_dmem_resp[0] }),
+ .imem2core_rdata_i({\u_riscv_top.core1_imem_rdata[31] ,
+ \u_riscv_top.core1_imem_rdata[30] ,
+ \u_riscv_top.core1_imem_rdata[29] ,
+ \u_riscv_top.core1_imem_rdata[28] ,
+ \u_riscv_top.core1_imem_rdata[27] ,
+ \u_riscv_top.core1_imem_rdata[26] ,
+ \u_riscv_top.core1_imem_rdata[25] ,
+ \u_riscv_top.core1_imem_rdata[24] ,
+ \u_riscv_top.core1_imem_rdata[23] ,
+ \u_riscv_top.core1_imem_rdata[22] ,
+ \u_riscv_top.core1_imem_rdata[21] ,
+ \u_riscv_top.core1_imem_rdata[20] ,
+ \u_riscv_top.core1_imem_rdata[19] ,
+ \u_riscv_top.core1_imem_rdata[18] ,
+ \u_riscv_top.core1_imem_rdata[17] ,
+ \u_riscv_top.core1_imem_rdata[16] ,
+ \u_riscv_top.core1_imem_rdata[15] ,
+ \u_riscv_top.core1_imem_rdata[14] ,
+ \u_riscv_top.core1_imem_rdata[13] ,
+ \u_riscv_top.core1_imem_rdata[12] ,
+ \u_riscv_top.core1_imem_rdata[11] ,
+ \u_riscv_top.core1_imem_rdata[10] ,
+ \u_riscv_top.core1_imem_rdata[9] ,
+ \u_riscv_top.core1_imem_rdata[8] ,
+ \u_riscv_top.core1_imem_rdata[7] ,
+ \u_riscv_top.core1_imem_rdata[6] ,
+ \u_riscv_top.core1_imem_rdata[5] ,
+ \u_riscv_top.core1_imem_rdata[4] ,
+ \u_riscv_top.core1_imem_rdata[3] ,
+ \u_riscv_top.core1_imem_rdata[2] ,
+ \u_riscv_top.core1_imem_rdata[1] ,
+ \u_riscv_top.core1_imem_rdata[0] }),
+ .imem2core_resp_i({\u_riscv_top.core1_imem_resp[1] ,
+ \u_riscv_top.core1_imem_resp[0] }));
+ ycr_core_top \u_riscv_top.i_core_top_2 (.clk(\u_riscv_top.core_clk ),
+ .clk_o(\u_riscv_top.core_clk_out[2] ),
+ .core2dmem_cmd_o(\u_riscv_top.core2_dmem_cmd ),
+ .core2dmem_req_o(\u_riscv_top.core2_dmem_req ),
+ .core2imem_cmd_o(\u_riscv_top.core2_imem_cmd ),
+ .core2imem_req_o(\u_riscv_top.core2_imem_req ),
+ .core_irq_mtimer_i(\u_riscv_top.core2_timer_irq ),
+ .core_irq_soft_i(\u_riscv_top.core2_soft_irq ),
+ .cpu_rst_n(\u_riscv_top.cpu_core_rst_n[2] ),
+ .dmem2core_req_ack_i(\u_riscv_top.core2_dmem_req_ack ),
+ .imem2core_req_ack_i(\u_riscv_top.core2_imem_req_ack ),
+ .pwrup_rst_n(\u_riscv_top.pwrup_rst_n ),
+ .rst_n(\u_riscv_top.pwrup_rst_n ),
+ .vccd1(vccd1),
+ .vssd1(vssd1),
+ .core2dmem_addr_o({\u_riscv_top.core2_dmem_addr[31] ,
+ \u_riscv_top.core2_dmem_addr[30] ,
+ \u_riscv_top.core2_dmem_addr[29] ,
+ \u_riscv_top.core2_dmem_addr[28] ,
+ \u_riscv_top.core2_dmem_addr[27] ,
+ \u_riscv_top.core2_dmem_addr[26] ,
+ \u_riscv_top.core2_dmem_addr[25] ,
+ \u_riscv_top.core2_dmem_addr[24] ,
+ \u_riscv_top.core2_dmem_addr[23] ,
+ \u_riscv_top.core2_dmem_addr[22] ,
+ \u_riscv_top.core2_dmem_addr[21] ,
+ \u_riscv_top.core2_dmem_addr[20] ,
+ \u_riscv_top.core2_dmem_addr[19] ,
+ \u_riscv_top.core2_dmem_addr[18] ,
+ \u_riscv_top.core2_dmem_addr[17] ,
+ \u_riscv_top.core2_dmem_addr[16] ,
+ \u_riscv_top.core2_dmem_addr[15] ,
+ \u_riscv_top.core2_dmem_addr[14] ,
+ \u_riscv_top.core2_dmem_addr[13] ,
+ \u_riscv_top.core2_dmem_addr[12] ,
+ \u_riscv_top.core2_dmem_addr[11] ,
+ \u_riscv_top.core2_dmem_addr[10] ,
+ \u_riscv_top.core2_dmem_addr[9] ,
+ \u_riscv_top.core2_dmem_addr[8] ,
+ \u_riscv_top.core2_dmem_addr[7] ,
+ \u_riscv_top.core2_dmem_addr[6] ,
+ \u_riscv_top.core2_dmem_addr[5] ,
+ \u_riscv_top.core2_dmem_addr[4] ,
+ \u_riscv_top.core2_dmem_addr[3] ,
+ \u_riscv_top.core2_dmem_addr[2] ,
+ \u_riscv_top.core2_dmem_addr[1] ,
+ \u_riscv_top.core2_dmem_addr[0] }),
+ .core2dmem_wdata_o({\u_riscv_top.core2_dmem_wdata[31] ,
+ \u_riscv_top.core2_dmem_wdata[30] ,
+ \u_riscv_top.core2_dmem_wdata[29] ,
+ \u_riscv_top.core2_dmem_wdata[28] ,
+ \u_riscv_top.core2_dmem_wdata[27] ,
+ \u_riscv_top.core2_dmem_wdata[26] ,
+ \u_riscv_top.core2_dmem_wdata[25] ,
+ \u_riscv_top.core2_dmem_wdata[24] ,
+ \u_riscv_top.core2_dmem_wdata[23] ,
+ \u_riscv_top.core2_dmem_wdata[22] ,
+ \u_riscv_top.core2_dmem_wdata[21] ,
+ \u_riscv_top.core2_dmem_wdata[20] ,
+ \u_riscv_top.core2_dmem_wdata[19] ,
+ \u_riscv_top.core2_dmem_wdata[18] ,
+ \u_riscv_top.core2_dmem_wdata[17] ,
+ \u_riscv_top.core2_dmem_wdata[16] ,
+ \u_riscv_top.core2_dmem_wdata[15] ,
+ \u_riscv_top.core2_dmem_wdata[14] ,
+ \u_riscv_top.core2_dmem_wdata[13] ,
+ \u_riscv_top.core2_dmem_wdata[12] ,
+ \u_riscv_top.core2_dmem_wdata[11] ,
+ \u_riscv_top.core2_dmem_wdata[10] ,
+ \u_riscv_top.core2_dmem_wdata[9] ,
+ \u_riscv_top.core2_dmem_wdata[8] ,
+ \u_riscv_top.core2_dmem_wdata[7] ,
+ \u_riscv_top.core2_dmem_wdata[6] ,
+ \u_riscv_top.core2_dmem_wdata[5] ,
+ \u_riscv_top.core2_dmem_wdata[4] ,
+ \u_riscv_top.core2_dmem_wdata[3] ,
+ \u_riscv_top.core2_dmem_wdata[2] ,
+ \u_riscv_top.core2_dmem_wdata[1] ,
+ \u_riscv_top.core2_dmem_wdata[0] }),
+ .core2dmem_width_o({\u_riscv_top.core2_dmem_width[1] ,
+ \u_riscv_top.core2_dmem_width[0] }),
+ .core2imem_addr_o({\u_riscv_top.core2_imem_addr[31] ,
+ \u_riscv_top.core2_imem_addr[30] ,
+ \u_riscv_top.core2_imem_addr[29] ,
+ \u_riscv_top.core2_imem_addr[28] ,
+ \u_riscv_top.core2_imem_addr[27] ,
+ \u_riscv_top.core2_imem_addr[26] ,
+ \u_riscv_top.core2_imem_addr[25] ,
+ \u_riscv_top.core2_imem_addr[24] ,
+ \u_riscv_top.core2_imem_addr[23] ,
+ \u_riscv_top.core2_imem_addr[22] ,
+ \u_riscv_top.core2_imem_addr[21] ,
+ \u_riscv_top.core2_imem_addr[20] ,
+ \u_riscv_top.core2_imem_addr[19] ,
+ \u_riscv_top.core2_imem_addr[18] ,
+ \u_riscv_top.core2_imem_addr[17] ,
+ \u_riscv_top.core2_imem_addr[16] ,
+ \u_riscv_top.core2_imem_addr[15] ,
+ \u_riscv_top.core2_imem_addr[14] ,
+ \u_riscv_top.core2_imem_addr[13] ,
+ \u_riscv_top.core2_imem_addr[12] ,
+ \u_riscv_top.core2_imem_addr[11] ,
+ \u_riscv_top.core2_imem_addr[10] ,
+ \u_riscv_top.core2_imem_addr[9] ,
+ \u_riscv_top.core2_imem_addr[8] ,
+ \u_riscv_top.core2_imem_addr[7] ,
+ \u_riscv_top.core2_imem_addr[6] ,
+ \u_riscv_top.core2_imem_addr[5] ,
+ \u_riscv_top.core2_imem_addr[4] ,
+ \u_riscv_top.core2_imem_addr[3] ,
+ \u_riscv_top.core2_imem_addr[2] ,
+ \u_riscv_top.core2_imem_addr[1] ,
+ \u_riscv_top.core2_imem_addr[0] }),
+ .core2imem_bl_o({\u_riscv_top.core2_imem_bl[2] ,
+ \u_riscv_top.core2_imem_bl[1] ,
+ \u_riscv_top.core2_imem_bl[0] }),
+ .core_debug({\u_riscv_top.core2_debug[48] ,
+ \u_riscv_top.core2_debug[47] ,
+ \u_riscv_top.core2_debug[46] ,
+ \u_riscv_top.core2_debug[45] ,
+ \u_riscv_top.core2_debug[44] ,
+ \u_riscv_top.core2_debug[43] ,
+ \u_riscv_top.core2_debug[42] ,
+ \u_riscv_top.core2_debug[41] ,
+ \u_riscv_top.core2_debug[40] ,
+ \u_riscv_top.core2_debug[39] ,
+ \u_riscv_top.core2_debug[38] ,
+ \u_riscv_top.core2_debug[37] ,
+ \u_riscv_top.core2_debug[36] ,
+ \u_riscv_top.core2_debug[35] ,
+ \u_riscv_top.core2_debug[34] ,
+ \u_riscv_top.core2_debug[33] ,
+ \u_riscv_top.core2_debug[32] ,
+ \u_riscv_top.core2_debug[31] ,
+ \u_riscv_top.core2_debug[30] ,
+ \u_riscv_top.core2_debug[29] ,
+ \u_riscv_top.core2_debug[28] ,
+ \u_riscv_top.core2_debug[27] ,
+ \u_riscv_top.core2_debug[26] ,
+ \u_riscv_top.core2_debug[25] ,
+ \u_riscv_top.core2_debug[24] ,
+ \u_riscv_top.core2_debug[23] ,
+ \u_riscv_top.core2_debug[22] ,
+ \u_riscv_top.core2_debug[21] ,
+ \u_riscv_top.core2_debug[20] ,
+ \u_riscv_top.core2_debug[19] ,
+ \u_riscv_top.core2_debug[18] ,
+ \u_riscv_top.core2_debug[17] ,
+ \u_riscv_top.core2_debug[16] ,
+ \u_riscv_top.core2_debug[15] ,
+ \u_riscv_top.core2_debug[14] ,
+ \u_riscv_top.core2_debug[13] ,
+ \u_riscv_top.core2_debug[12] ,
+ \u_riscv_top.core2_debug[11] ,
+ \u_riscv_top.core2_debug[10] ,
+ \u_riscv_top.core2_debug[9] ,
+ \u_riscv_top.core2_debug[8] ,
+ \u_riscv_top.core2_debug[7] ,
+ \u_riscv_top.core2_debug[6] ,
+ \u_riscv_top.core2_debug[5] ,
+ \u_riscv_top.core2_debug[4] ,
+ \u_riscv_top.core2_debug[3] ,
+ \u_riscv_top.core2_debug[2] ,
+ \u_riscv_top.core2_debug[1] ,
+ \u_riscv_top.core2_debug[0] }),
+ .core_irq_lines_i({\u_riscv_top.core2_irq_lines[15] ,
+ \u_riscv_top.core2_irq_lines[14] ,
+ \u_riscv_top.core2_irq_lines[13] ,
+ \u_riscv_top.core2_irq_lines[12] ,
+ \u_riscv_top.core2_irq_lines[11] ,
+ \u_riscv_top.core2_irq_lines[10] ,
+ \u_riscv_top.core2_irq_lines[9] ,
+ \u_riscv_top.core2_irq_lines[8] ,
+ \u_riscv_top.core2_irq_lines[7] ,
+ \u_riscv_top.core2_irq_lines[6] ,
+ \u_riscv_top.core2_irq_lines[5] ,
+ \u_riscv_top.core2_irq_lines[4] ,
+ \u_riscv_top.core2_irq_lines[3] ,
+ \u_riscv_top.core2_irq_lines[2] ,
+ \u_riscv_top.core2_irq_lines[1] ,
+ \u_riscv_top.core2_irq_lines[0] }),
+ .core_mtimer_val_i({\u_riscv_top.core2_timer_val[63] ,
+ \u_riscv_top.core2_timer_val[62] ,
+ \u_riscv_top.core2_timer_val[61] ,
+ \u_riscv_top.core2_timer_val[60] ,
+ \u_riscv_top.core2_timer_val[59] ,
+ \u_riscv_top.core2_timer_val[58] ,
+ \u_riscv_top.core2_timer_val[57] ,
+ \u_riscv_top.core2_timer_val[56] ,
+ \u_riscv_top.core2_timer_val[55] ,
+ \u_riscv_top.core2_timer_val[54] ,
+ \u_riscv_top.core2_timer_val[53] ,
+ \u_riscv_top.core2_timer_val[52] ,
+ \u_riscv_top.core2_timer_val[51] ,
+ \u_riscv_top.core2_timer_val[50] ,
+ \u_riscv_top.core2_timer_val[49] ,
+ \u_riscv_top.core2_timer_val[48] ,
+ \u_riscv_top.core2_timer_val[47] ,
+ \u_riscv_top.core2_timer_val[46] ,
+ \u_riscv_top.core2_timer_val[45] ,
+ \u_riscv_top.core2_timer_val[44] ,
+ \u_riscv_top.core2_timer_val[43] ,
+ \u_riscv_top.core2_timer_val[42] ,
+ \u_riscv_top.core2_timer_val[41] ,
+ \u_riscv_top.core2_timer_val[40] ,
+ \u_riscv_top.core2_timer_val[39] ,
+ \u_riscv_top.core2_timer_val[38] ,
+ \u_riscv_top.core2_timer_val[37] ,
+ \u_riscv_top.core2_timer_val[36] ,
+ \u_riscv_top.core2_timer_val[35] ,
+ \u_riscv_top.core2_timer_val[34] ,
+ \u_riscv_top.core2_timer_val[33] ,
+ \u_riscv_top.core2_timer_val[32] ,
+ \u_riscv_top.core2_timer_val[31] ,
+ \u_riscv_top.core2_timer_val[30] ,
+ \u_riscv_top.core2_timer_val[29] ,
+ \u_riscv_top.core2_timer_val[28] ,
+ \u_riscv_top.core2_timer_val[27] ,
+ \u_riscv_top.core2_timer_val[26] ,
+ \u_riscv_top.core2_timer_val[25] ,
+ \u_riscv_top.core2_timer_val[24] ,
+ \u_riscv_top.core2_timer_val[23] ,
+ \u_riscv_top.core2_timer_val[22] ,
+ \u_riscv_top.core2_timer_val[21] ,
+ \u_riscv_top.core2_timer_val[20] ,
+ \u_riscv_top.core2_timer_val[19] ,
+ \u_riscv_top.core2_timer_val[18] ,
+ \u_riscv_top.core2_timer_val[17] ,
+ \u_riscv_top.core2_timer_val[16] ,
+ \u_riscv_top.core2_timer_val[15] ,
+ \u_riscv_top.core2_timer_val[14] ,
+ \u_riscv_top.core2_timer_val[13] ,
+ \u_riscv_top.core2_timer_val[12] ,
+ \u_riscv_top.core2_timer_val[11] ,
+ \u_riscv_top.core2_timer_val[10] ,
+ \u_riscv_top.core2_timer_val[9] ,
+ \u_riscv_top.core2_timer_val[8] ,
+ \u_riscv_top.core2_timer_val[7] ,
+ \u_riscv_top.core2_timer_val[6] ,
+ \u_riscv_top.core2_timer_val[5] ,
+ \u_riscv_top.core2_timer_val[4] ,
+ \u_riscv_top.core2_timer_val[3] ,
+ \u_riscv_top.core2_timer_val[2] ,
+ \u_riscv_top.core2_timer_val[1] ,
+ \u_riscv_top.core2_timer_val[0] }),
+ .core_uid({\u_riscv_top.core2_uid[1] ,
+ \u_riscv_top.core2_uid[0] }),
+ .dmem2core_rdata_i({\u_riscv_top.core2_dmem_rdata[31] ,
+ \u_riscv_top.core2_dmem_rdata[30] ,
+ \u_riscv_top.core2_dmem_rdata[29] ,
+ \u_riscv_top.core2_dmem_rdata[28] ,
+ \u_riscv_top.core2_dmem_rdata[27] ,
+ \u_riscv_top.core2_dmem_rdata[26] ,
+ \u_riscv_top.core2_dmem_rdata[25] ,
+ \u_riscv_top.core2_dmem_rdata[24] ,
+ \u_riscv_top.core2_dmem_rdata[23] ,
+ \u_riscv_top.core2_dmem_rdata[22] ,
+ \u_riscv_top.core2_dmem_rdata[21] ,
+ \u_riscv_top.core2_dmem_rdata[20] ,
+ \u_riscv_top.core2_dmem_rdata[19] ,
+ \u_riscv_top.core2_dmem_rdata[18] ,
+ \u_riscv_top.core2_dmem_rdata[17] ,
+ \u_riscv_top.core2_dmem_rdata[16] ,
+ \u_riscv_top.core2_dmem_rdata[15] ,
+ \u_riscv_top.core2_dmem_rdata[14] ,
+ \u_riscv_top.core2_dmem_rdata[13] ,
+ \u_riscv_top.core2_dmem_rdata[12] ,
+ \u_riscv_top.core2_dmem_rdata[11] ,
+ \u_riscv_top.core2_dmem_rdata[10] ,
+ \u_riscv_top.core2_dmem_rdata[9] ,
+ \u_riscv_top.core2_dmem_rdata[8] ,
+ \u_riscv_top.core2_dmem_rdata[7] ,
+ \u_riscv_top.core2_dmem_rdata[6] ,
+ \u_riscv_top.core2_dmem_rdata[5] ,
+ \u_riscv_top.core2_dmem_rdata[4] ,
+ \u_riscv_top.core2_dmem_rdata[3] ,
+ \u_riscv_top.core2_dmem_rdata[2] ,
+ \u_riscv_top.core2_dmem_rdata[1] ,
+ \u_riscv_top.core2_dmem_rdata[0] }),
+ .dmem2core_resp_i({\u_riscv_top.core2_dmem_resp[1] ,
+ \u_riscv_top.core2_dmem_resp[0] }),
+ .imem2core_rdata_i({\u_riscv_top.core2_imem_rdata[31] ,
+ \u_riscv_top.core2_imem_rdata[30] ,
+ \u_riscv_top.core2_imem_rdata[29] ,
+ \u_riscv_top.core2_imem_rdata[28] ,
+ \u_riscv_top.core2_imem_rdata[27] ,
+ \u_riscv_top.core2_imem_rdata[26] ,
+ \u_riscv_top.core2_imem_rdata[25] ,
+ \u_riscv_top.core2_imem_rdata[24] ,
+ \u_riscv_top.core2_imem_rdata[23] ,
+ \u_riscv_top.core2_imem_rdata[22] ,
+ \u_riscv_top.core2_imem_rdata[21] ,
+ \u_riscv_top.core2_imem_rdata[20] ,
+ \u_riscv_top.core2_imem_rdata[19] ,
+ \u_riscv_top.core2_imem_rdata[18] ,
+ \u_riscv_top.core2_imem_rdata[17] ,
+ \u_riscv_top.core2_imem_rdata[16] ,
+ \u_riscv_top.core2_imem_rdata[15] ,
+ \u_riscv_top.core2_imem_rdata[14] ,
+ \u_riscv_top.core2_imem_rdata[13] ,
+ \u_riscv_top.core2_imem_rdata[12] ,
+ \u_riscv_top.core2_imem_rdata[11] ,
+ \u_riscv_top.core2_imem_rdata[10] ,
+ \u_riscv_top.core2_imem_rdata[9] ,
+ \u_riscv_top.core2_imem_rdata[8] ,
+ \u_riscv_top.core2_imem_rdata[7] ,
+ \u_riscv_top.core2_imem_rdata[6] ,
+ \u_riscv_top.core2_imem_rdata[5] ,
+ \u_riscv_top.core2_imem_rdata[4] ,
+ \u_riscv_top.core2_imem_rdata[3] ,
+ \u_riscv_top.core2_imem_rdata[2] ,
+ \u_riscv_top.core2_imem_rdata[1] ,
+ \u_riscv_top.core2_imem_rdata[0] }),
+ .imem2core_resp_i({\u_riscv_top.core2_imem_resp[1] ,
+ \u_riscv_top.core2_imem_resp[0] }));
+ ycr_core_top \u_riscv_top.i_core_top_3 (.clk(\u_riscv_top.core_clk ),
+ .clk_o(\u_riscv_top.core_clk_out[3] ),
+ .core2dmem_cmd_o(\u_riscv_top.core3_dmem_cmd ),
+ .core2dmem_req_o(\u_riscv_top.core3_dmem_req ),
+ .core2imem_cmd_o(\u_riscv_top.core3_imem_cmd ),
+ .core2imem_req_o(\u_riscv_top.core3_imem_req ),
+ .core_irq_mtimer_i(\u_riscv_top.core3_timer_irq ),
+ .core_irq_soft_i(\u_riscv_top.core3_soft_irq ),
+ .cpu_rst_n(\u_riscv_top.cpu_core_rst_n[3] ),
+ .dmem2core_req_ack_i(\u_riscv_top.core3_dmem_req_ack ),
+ .imem2core_req_ack_i(\u_riscv_top.core3_imem_req_ack ),
+ .pwrup_rst_n(\u_riscv_top.pwrup_rst_n ),
+ .rst_n(\u_riscv_top.pwrup_rst_n ),
+ .vccd1(vccd1),
+ .vssd1(vssd1),
+ .core2dmem_addr_o({\u_riscv_top.core3_dmem_addr[31] ,
+ \u_riscv_top.core3_dmem_addr[30] ,
+ \u_riscv_top.core3_dmem_addr[29] ,
+ \u_riscv_top.core3_dmem_addr[28] ,
+ \u_riscv_top.core3_dmem_addr[27] ,
+ \u_riscv_top.core3_dmem_addr[26] ,
+ \u_riscv_top.core3_dmem_addr[25] ,
+ \u_riscv_top.core3_dmem_addr[24] ,
+ \u_riscv_top.core3_dmem_addr[23] ,
+ \u_riscv_top.core3_dmem_addr[22] ,
+ \u_riscv_top.core3_dmem_addr[21] ,
+ \u_riscv_top.core3_dmem_addr[20] ,
+ \u_riscv_top.core3_dmem_addr[19] ,
+ \u_riscv_top.core3_dmem_addr[18] ,
+ \u_riscv_top.core3_dmem_addr[17] ,
+ \u_riscv_top.core3_dmem_addr[16] ,
+ \u_riscv_top.core3_dmem_addr[15] ,
+ \u_riscv_top.core3_dmem_addr[14] ,
+ \u_riscv_top.core3_dmem_addr[13] ,
+ \u_riscv_top.core3_dmem_addr[12] ,
+ \u_riscv_top.core3_dmem_addr[11] ,
+ \u_riscv_top.core3_dmem_addr[10] ,
+ \u_riscv_top.core3_dmem_addr[9] ,
+ \u_riscv_top.core3_dmem_addr[8] ,
+ \u_riscv_top.core3_dmem_addr[7] ,
+ \u_riscv_top.core3_dmem_addr[6] ,
+ \u_riscv_top.core3_dmem_addr[5] ,
+ \u_riscv_top.core3_dmem_addr[4] ,
+ \u_riscv_top.core3_dmem_addr[3] ,
+ \u_riscv_top.core3_dmem_addr[2] ,
+ \u_riscv_top.core3_dmem_addr[1] ,
+ \u_riscv_top.core3_dmem_addr[0] }),
+ .core2dmem_wdata_o({\u_riscv_top.core3_dmem_wdata[31] ,
+ \u_riscv_top.core3_dmem_wdata[30] ,
+ \u_riscv_top.core3_dmem_wdata[29] ,
+ \u_riscv_top.core3_dmem_wdata[28] ,
+ \u_riscv_top.core3_dmem_wdata[27] ,
+ \u_riscv_top.core3_dmem_wdata[26] ,
+ \u_riscv_top.core3_dmem_wdata[25] ,
+ \u_riscv_top.core3_dmem_wdata[24] ,
+ \u_riscv_top.core3_dmem_wdata[23] ,
+ \u_riscv_top.core3_dmem_wdata[22] ,
+ \u_riscv_top.core3_dmem_wdata[21] ,
+ \u_riscv_top.core3_dmem_wdata[20] ,
+ \u_riscv_top.core3_dmem_wdata[19] ,
+ \u_riscv_top.core3_dmem_wdata[18] ,
+ \u_riscv_top.core3_dmem_wdata[17] ,
+ \u_riscv_top.core3_dmem_wdata[16] ,
+ \u_riscv_top.core3_dmem_wdata[15] ,
+ \u_riscv_top.core3_dmem_wdata[14] ,
+ \u_riscv_top.core3_dmem_wdata[13] ,
+ \u_riscv_top.core3_dmem_wdata[12] ,
+ \u_riscv_top.core3_dmem_wdata[11] ,
+ \u_riscv_top.core3_dmem_wdata[10] ,
+ \u_riscv_top.core3_dmem_wdata[9] ,
+ \u_riscv_top.core3_dmem_wdata[8] ,
+ \u_riscv_top.core3_dmem_wdata[7] ,
+ \u_riscv_top.core3_dmem_wdata[6] ,
+ \u_riscv_top.core3_dmem_wdata[5] ,
+ \u_riscv_top.core3_dmem_wdata[4] ,
+ \u_riscv_top.core3_dmem_wdata[3] ,
+ \u_riscv_top.core3_dmem_wdata[2] ,
+ \u_riscv_top.core3_dmem_wdata[1] ,
+ \u_riscv_top.core3_dmem_wdata[0] }),
+ .core2dmem_width_o({\u_riscv_top.core3_dmem_width[1] ,
+ \u_riscv_top.core3_dmem_width[0] }),
+ .core2imem_addr_o({\u_riscv_top.core3_imem_addr[31] ,
+ \u_riscv_top.core3_imem_addr[30] ,
+ \u_riscv_top.core3_imem_addr[29] ,
+ \u_riscv_top.core3_imem_addr[28] ,
+ \u_riscv_top.core3_imem_addr[27] ,
+ \u_riscv_top.core3_imem_addr[26] ,
+ \u_riscv_top.core3_imem_addr[25] ,
+ \u_riscv_top.core3_imem_addr[24] ,
+ \u_riscv_top.core3_imem_addr[23] ,
+ \u_riscv_top.core3_imem_addr[22] ,
+ \u_riscv_top.core3_imem_addr[21] ,
+ \u_riscv_top.core3_imem_addr[20] ,
+ \u_riscv_top.core3_imem_addr[19] ,
+ \u_riscv_top.core3_imem_addr[18] ,
+ \u_riscv_top.core3_imem_addr[17] ,
+ \u_riscv_top.core3_imem_addr[16] ,
+ \u_riscv_top.core3_imem_addr[15] ,
+ \u_riscv_top.core3_imem_addr[14] ,
+ \u_riscv_top.core3_imem_addr[13] ,
+ \u_riscv_top.core3_imem_addr[12] ,
+ \u_riscv_top.core3_imem_addr[11] ,
+ \u_riscv_top.core3_imem_addr[10] ,
+ \u_riscv_top.core3_imem_addr[9] ,
+ \u_riscv_top.core3_imem_addr[8] ,
+ \u_riscv_top.core3_imem_addr[7] ,
+ \u_riscv_top.core3_imem_addr[6] ,
+ \u_riscv_top.core3_imem_addr[5] ,
+ \u_riscv_top.core3_imem_addr[4] ,
+ \u_riscv_top.core3_imem_addr[3] ,
+ \u_riscv_top.core3_imem_addr[2] ,
+ \u_riscv_top.core3_imem_addr[1] ,
+ \u_riscv_top.core3_imem_addr[0] }),
+ .core2imem_bl_o({\u_riscv_top.core3_imem_bl[2] ,
+ \u_riscv_top.core3_imem_bl[1] ,
+ \u_riscv_top.core3_imem_bl[0] }),
+ .core_debug({\u_riscv_top.core3_debug[48] ,
+ \u_riscv_top.core3_debug[47] ,
+ \u_riscv_top.core3_debug[46] ,
+ \u_riscv_top.core3_debug[45] ,
+ \u_riscv_top.core3_debug[44] ,
+ \u_riscv_top.core3_debug[43] ,
+ \u_riscv_top.core3_debug[42] ,
+ \u_riscv_top.core3_debug[41] ,
+ \u_riscv_top.core3_debug[40] ,
+ \u_riscv_top.core3_debug[39] ,
+ \u_riscv_top.core3_debug[38] ,
+ \u_riscv_top.core3_debug[37] ,
+ \u_riscv_top.core3_debug[36] ,
+ \u_riscv_top.core3_debug[35] ,
+ \u_riscv_top.core3_debug[34] ,
+ \u_riscv_top.core3_debug[33] ,
+ \u_riscv_top.core3_debug[32] ,
+ \u_riscv_top.core3_debug[31] ,
+ \u_riscv_top.core3_debug[30] ,
+ \u_riscv_top.core3_debug[29] ,
+ \u_riscv_top.core3_debug[28] ,
+ \u_riscv_top.core3_debug[27] ,
+ \u_riscv_top.core3_debug[26] ,
+ \u_riscv_top.core3_debug[25] ,
+ \u_riscv_top.core3_debug[24] ,
+ \u_riscv_top.core3_debug[23] ,
+ \u_riscv_top.core3_debug[22] ,
+ \u_riscv_top.core3_debug[21] ,
+ \u_riscv_top.core3_debug[20] ,
+ \u_riscv_top.core3_debug[19] ,
+ \u_riscv_top.core3_debug[18] ,
+ \u_riscv_top.core3_debug[17] ,
+ \u_riscv_top.core3_debug[16] ,
+ \u_riscv_top.core3_debug[15] ,
+ \u_riscv_top.core3_debug[14] ,
+ \u_riscv_top.core3_debug[13] ,
+ \u_riscv_top.core3_debug[12] ,
+ \u_riscv_top.core3_debug[11] ,
+ \u_riscv_top.core3_debug[10] ,
+ \u_riscv_top.core3_debug[9] ,
+ \u_riscv_top.core3_debug[8] ,
+ \u_riscv_top.core3_debug[7] ,
+ \u_riscv_top.core3_debug[6] ,
+ \u_riscv_top.core3_debug[5] ,
+ \u_riscv_top.core3_debug[4] ,
+ \u_riscv_top.core3_debug[3] ,
+ \u_riscv_top.core3_debug[2] ,
+ \u_riscv_top.core3_debug[1] ,
+ \u_riscv_top.core3_debug[0] }),
+ .core_irq_lines_i({\u_riscv_top.core3_irq_lines[15] ,
+ \u_riscv_top.core3_irq_lines[14] ,
+ \u_riscv_top.core3_irq_lines[13] ,
+ \u_riscv_top.core3_irq_lines[12] ,
+ \u_riscv_top.core3_irq_lines[11] ,
+ \u_riscv_top.core3_irq_lines[10] ,
+ \u_riscv_top.core3_irq_lines[9] ,
+ \u_riscv_top.core3_irq_lines[8] ,
+ \u_riscv_top.core3_irq_lines[7] ,
+ \u_riscv_top.core3_irq_lines[6] ,
+ \u_riscv_top.core3_irq_lines[5] ,
+ \u_riscv_top.core3_irq_lines[4] ,
+ \u_riscv_top.core3_irq_lines[3] ,
+ \u_riscv_top.core3_irq_lines[2] ,
+ \u_riscv_top.core3_irq_lines[1] ,
+ \u_riscv_top.core3_irq_lines[0] }),
+ .core_mtimer_val_i({\u_riscv_top.core3_timer_val[63] ,
+ \u_riscv_top.core3_timer_val[62] ,
+ \u_riscv_top.core3_timer_val[61] ,
+ \u_riscv_top.core3_timer_val[60] ,
+ \u_riscv_top.core3_timer_val[59] ,
+ \u_riscv_top.core3_timer_val[58] ,
+ \u_riscv_top.core3_timer_val[57] ,
+ \u_riscv_top.core3_timer_val[56] ,
+ \u_riscv_top.core3_timer_val[55] ,
+ \u_riscv_top.core3_timer_val[54] ,
+ \u_riscv_top.core3_timer_val[53] ,
+ \u_riscv_top.core3_timer_val[52] ,
+ \u_riscv_top.core3_timer_val[51] ,
+ \u_riscv_top.core3_timer_val[50] ,
+ \u_riscv_top.core3_timer_val[49] ,
+ \u_riscv_top.core3_timer_val[48] ,
+ \u_riscv_top.core3_timer_val[47] ,
+ \u_riscv_top.core3_timer_val[46] ,
+ \u_riscv_top.core3_timer_val[45] ,
+ \u_riscv_top.core3_timer_val[44] ,
+ \u_riscv_top.core3_timer_val[43] ,
+ \u_riscv_top.core3_timer_val[42] ,
+ \u_riscv_top.core3_timer_val[41] ,
+ \u_riscv_top.core3_timer_val[40] ,
+ \u_riscv_top.core3_timer_val[39] ,
+ \u_riscv_top.core3_timer_val[38] ,
+ \u_riscv_top.core3_timer_val[37] ,
+ \u_riscv_top.core3_timer_val[36] ,
+ \u_riscv_top.core3_timer_val[35] ,
+ \u_riscv_top.core3_timer_val[34] ,
+ \u_riscv_top.core3_timer_val[33] ,
+ \u_riscv_top.core3_timer_val[32] ,
+ \u_riscv_top.core3_timer_val[31] ,
+ \u_riscv_top.core3_timer_val[30] ,
+ \u_riscv_top.core3_timer_val[29] ,
+ \u_riscv_top.core3_timer_val[28] ,
+ \u_riscv_top.core3_timer_val[27] ,
+ \u_riscv_top.core3_timer_val[26] ,
+ \u_riscv_top.core3_timer_val[25] ,
+ \u_riscv_top.core3_timer_val[24] ,
+ \u_riscv_top.core3_timer_val[23] ,
+ \u_riscv_top.core3_timer_val[22] ,
+ \u_riscv_top.core3_timer_val[21] ,
+ \u_riscv_top.core3_timer_val[20] ,
+ \u_riscv_top.core3_timer_val[19] ,
+ \u_riscv_top.core3_timer_val[18] ,
+ \u_riscv_top.core3_timer_val[17] ,
+ \u_riscv_top.core3_timer_val[16] ,
+ \u_riscv_top.core3_timer_val[15] ,
+ \u_riscv_top.core3_timer_val[14] ,
+ \u_riscv_top.core3_timer_val[13] ,
+ \u_riscv_top.core3_timer_val[12] ,
+ \u_riscv_top.core3_timer_val[11] ,
+ \u_riscv_top.core3_timer_val[10] ,
+ \u_riscv_top.core3_timer_val[9] ,
+ \u_riscv_top.core3_timer_val[8] ,
+ \u_riscv_top.core3_timer_val[7] ,
+ \u_riscv_top.core3_timer_val[6] ,
+ \u_riscv_top.core3_timer_val[5] ,
+ \u_riscv_top.core3_timer_val[4] ,
+ \u_riscv_top.core3_timer_val[3] ,
+ \u_riscv_top.core3_timer_val[2] ,
+ \u_riscv_top.core3_timer_val[1] ,
+ \u_riscv_top.core3_timer_val[0] }),
+ .core_uid({\u_riscv_top.core3_uid[1] ,
+ \u_riscv_top.core3_uid[0] }),
+ .dmem2core_rdata_i({\u_riscv_top.core3_dmem_rdata[31] ,
+ \u_riscv_top.core3_dmem_rdata[30] ,
+ \u_riscv_top.core3_dmem_rdata[29] ,
+ \u_riscv_top.core3_dmem_rdata[28] ,
+ \u_riscv_top.core3_dmem_rdata[27] ,
+ \u_riscv_top.core3_dmem_rdata[26] ,
+ \u_riscv_top.core3_dmem_rdata[25] ,
+ \u_riscv_top.core3_dmem_rdata[24] ,
+ \u_riscv_top.core3_dmem_rdata[23] ,
+ \u_riscv_top.core3_dmem_rdata[22] ,
+ \u_riscv_top.core3_dmem_rdata[21] ,
+ \u_riscv_top.core3_dmem_rdata[20] ,
+ \u_riscv_top.core3_dmem_rdata[19] ,
+ \u_riscv_top.core3_dmem_rdata[18] ,
+ \u_riscv_top.core3_dmem_rdata[17] ,
+ \u_riscv_top.core3_dmem_rdata[16] ,
+ \u_riscv_top.core3_dmem_rdata[15] ,
+ \u_riscv_top.core3_dmem_rdata[14] ,
+ \u_riscv_top.core3_dmem_rdata[13] ,
+ \u_riscv_top.core3_dmem_rdata[12] ,
+ \u_riscv_top.core3_dmem_rdata[11] ,
+ \u_riscv_top.core3_dmem_rdata[10] ,
+ \u_riscv_top.core3_dmem_rdata[9] ,
+ \u_riscv_top.core3_dmem_rdata[8] ,
+ \u_riscv_top.core3_dmem_rdata[7] ,
+ \u_riscv_top.core3_dmem_rdata[6] ,
+ \u_riscv_top.core3_dmem_rdata[5] ,
+ \u_riscv_top.core3_dmem_rdata[4] ,
+ \u_riscv_top.core3_dmem_rdata[3] ,
+ \u_riscv_top.core3_dmem_rdata[2] ,
+ \u_riscv_top.core3_dmem_rdata[1] ,
+ \u_riscv_top.core3_dmem_rdata[0] }),
+ .dmem2core_resp_i({\u_riscv_top.core3_dmem_resp[1] ,
+ \u_riscv_top.core3_dmem_resp[0] }),
+ .imem2core_rdata_i({\u_riscv_top.core3_imem_rdata[31] ,
+ \u_riscv_top.core3_imem_rdata[30] ,
+ \u_riscv_top.core3_imem_rdata[29] ,
+ \u_riscv_top.core3_imem_rdata[28] ,
+ \u_riscv_top.core3_imem_rdata[27] ,
+ \u_riscv_top.core3_imem_rdata[26] ,
+ \u_riscv_top.core3_imem_rdata[25] ,
+ \u_riscv_top.core3_imem_rdata[24] ,
+ \u_riscv_top.core3_imem_rdata[23] ,
+ \u_riscv_top.core3_imem_rdata[22] ,
+ \u_riscv_top.core3_imem_rdata[21] ,
+ \u_riscv_top.core3_imem_rdata[20] ,
+ \u_riscv_top.core3_imem_rdata[19] ,
+ \u_riscv_top.core3_imem_rdata[18] ,
+ \u_riscv_top.core3_imem_rdata[17] ,
+ \u_riscv_top.core3_imem_rdata[16] ,
+ \u_riscv_top.core3_imem_rdata[15] ,
+ \u_riscv_top.core3_imem_rdata[14] ,
+ \u_riscv_top.core3_imem_rdata[13] ,
+ \u_riscv_top.core3_imem_rdata[12] ,
+ \u_riscv_top.core3_imem_rdata[11] ,
+ \u_riscv_top.core3_imem_rdata[10] ,
+ \u_riscv_top.core3_imem_rdata[9] ,
+ \u_riscv_top.core3_imem_rdata[8] ,
+ \u_riscv_top.core3_imem_rdata[7] ,
+ \u_riscv_top.core3_imem_rdata[6] ,
+ \u_riscv_top.core3_imem_rdata[5] ,
+ \u_riscv_top.core3_imem_rdata[4] ,
+ \u_riscv_top.core3_imem_rdata[3] ,
+ \u_riscv_top.core3_imem_rdata[2] ,
+ \u_riscv_top.core3_imem_rdata[1] ,
+ \u_riscv_top.core3_imem_rdata[0] }),
+ .imem2core_resp_i({\u_riscv_top.core3_imem_resp[1] ,
+ \u_riscv_top.core3_imem_resp[0] }));
+ ycr4_iconnect \u_riscv_top.u_connect (.VGND(vssd1),
+ .VPWR(vccd1),
+ .cfg_dcache_force_flush(\u_riscv_top.cfg_dcache_force_flush ),
+ .core0_dmem_cmd(\u_riscv_top.core0_dmem_cmd ),
+ .core0_dmem_req(\u_riscv_top.core0_dmem_req ),
+ .core0_dmem_req_ack(\u_riscv_top.core0_dmem_req_ack ),
+ .core0_imem_cmd(\u_riscv_top.core0_imem_cmd ),
+ .core0_imem_req(\u_riscv_top.core0_imem_req ),
+ .core0_imem_req_ack(\u_riscv_top.core0_imem_req_ack ),
+ .core0_irq_soft(\u_riscv_top.core0_soft_irq ),
+ .core0_timer_irq(\u_riscv_top.core0_timer_irq ),
+ .core1_dmem_cmd(\u_riscv_top.core1_dmem_cmd ),
+ .core1_dmem_req(\u_riscv_top.core1_dmem_req ),
+ .core1_dmem_req_ack(\u_riscv_top.core1_dmem_req_ack ),
+ .core1_imem_cmd(\u_riscv_top.core1_imem_cmd ),
+ .core1_imem_req(\u_riscv_top.core1_imem_req ),
+ .core1_imem_req_ack(\u_riscv_top.core1_imem_req_ack ),
+ .core1_irq_soft(\u_riscv_top.core1_soft_irq ),
+ .core1_timer_irq(\u_riscv_top.core1_timer_irq ),
+ .core2_dmem_cmd(\u_riscv_top.core2_dmem_cmd ),
+ .core2_dmem_req(\u_riscv_top.core2_dmem_req ),
+ .core2_dmem_req_ack(\u_riscv_top.core2_dmem_req_ack ),
+ .core2_imem_cmd(\u_riscv_top.core2_imem_cmd ),
+ .core2_imem_req(\u_riscv_top.core2_imem_req ),
+ .core2_imem_req_ack(\u_riscv_top.core2_imem_req_ack ),
+ .core2_irq_soft(\u_riscv_top.core2_soft_irq ),
+ .core2_timer_irq(\u_riscv_top.core2_timer_irq ),
+ .core3_dmem_cmd(\u_riscv_top.core3_dmem_cmd ),
+ .core3_dmem_req(\u_riscv_top.core3_dmem_req ),
+ .core3_dmem_req_ack(\u_riscv_top.core3_dmem_req_ack ),
+ .core3_imem_cmd(\u_riscv_top.core3_imem_cmd ),
+ .core3_imem_req(\u_riscv_top.core3_imem_req ),
+ .core3_imem_req_ack(\u_riscv_top.core3_imem_req_ack ),
+ .core3_irq_soft(\u_riscv_top.core3_soft_irq ),
+ .core3_timer_irq(\u_riscv_top.core3_timer_irq ),
+ .core_clk(\u_riscv_top.core_clk ),
+ .core_dcache_cmd(\u_riscv_top.core_dcache_cmd ),
+ .core_dcache_req(\u_riscv_top.core_dcache_req ),
+ .core_dcache_req_ack(\u_riscv_top.core_dcache_req_ack ),
+ .core_dmem_cmd(\u_riscv_top.core_dmem_cmd ),
+ .core_dmem_req(\u_riscv_top.core_dmem_req ),
+ .core_dmem_req_ack(\u_riscv_top.core_dmem_req_ack ),
+ .core_icache_cmd(\u_riscv_top.core_icache_cmd ),
+ .core_icache_req(\u_riscv_top.core_icache_req ),
+ .core_icache_req_ack(\u_riscv_top.core_icache_req_ack ),
+ .core_irq_soft_i(\u_riscv_top.soft_irq ),
+ .cpu_intf_rst_n(\u_riscv_top.cpu_intf_rst_n ),
+ .pwrup_rst_n(\u_riscv_top.pwrup_rst_n ),
+ .rtc_clk(\u_riscv_top.rtc_clk ),
+ .sram0_clk0(\u_riscv_top.sram0_clk0 ),
+ .sram0_clk1(\u_riscv_top.sram0_clk1 ),
+ .sram0_csb0(\u_riscv_top.sram0_csb0 ),
+ .sram0_csb1(\u_riscv_top.sram0_csb1 ),
+ .sram0_web0(\u_riscv_top.sram0_web0 ),
+ .cfg_sram_lphase({\cfg_riscv_ctrl[3] ,
+ \cfg_riscv_ctrl[2] }),
+ .core0_debug({\u_riscv_top.core0_debug[48] ,
+ \u_riscv_top.core0_debug[47] ,
+ \u_riscv_top.core0_debug[46] ,
+ \u_riscv_top.core0_debug[45] ,
+ \u_riscv_top.core0_debug[44] ,
+ \u_riscv_top.core0_debug[43] ,
+ \u_riscv_top.core0_debug[42] ,
+ \u_riscv_top.core0_debug[41] ,
+ \u_riscv_top.core0_debug[40] ,
+ \u_riscv_top.core0_debug[39] ,
+ \u_riscv_top.core0_debug[38] ,
+ \u_riscv_top.core0_debug[37] ,
+ \u_riscv_top.core0_debug[36] ,
+ \u_riscv_top.core0_debug[35] ,
+ \u_riscv_top.core0_debug[34] ,
+ \u_riscv_top.core0_debug[33] ,
+ \u_riscv_top.core0_debug[32] ,
+ \u_riscv_top.core0_debug[31] ,
+ \u_riscv_top.core0_debug[30] ,
+ \u_riscv_top.core0_debug[29] ,
+ \u_riscv_top.core0_debug[28] ,
+ \u_riscv_top.core0_debug[27] ,
+ \u_riscv_top.core0_debug[26] ,
+ \u_riscv_top.core0_debug[25] ,
+ \u_riscv_top.core0_debug[24] ,
+ \u_riscv_top.core0_debug[23] ,
+ \u_riscv_top.core0_debug[22] ,
+ \u_riscv_top.core0_debug[21] ,
+ \u_riscv_top.core0_debug[20] ,
+ \u_riscv_top.core0_debug[19] ,
+ \u_riscv_top.core0_debug[18] ,
+ \u_riscv_top.core0_debug[17] ,
+ \u_riscv_top.core0_debug[16] ,
+ \u_riscv_top.core0_debug[15] ,
+ \u_riscv_top.core0_debug[14] ,
+ \u_riscv_top.core0_debug[13] ,
+ \u_riscv_top.core0_debug[12] ,
+ \u_riscv_top.core0_debug[11] ,
+ \u_riscv_top.core0_debug[10] ,
+ \u_riscv_top.core0_debug[9] ,
+ \u_riscv_top.core0_debug[8] ,
+ \u_riscv_top.core0_debug[7] ,
+ \u_riscv_top.core0_debug[6] ,
+ \u_riscv_top.core0_debug[5] ,
+ \u_riscv_top.core0_debug[4] ,
+ \u_riscv_top.core0_debug[3] ,
+ \u_riscv_top.core0_debug[2] ,
+ \u_riscv_top.core0_debug[1] ,
+ \u_riscv_top.core0_debug[0] }),
+ .core0_dmem_addr({\u_riscv_top.core0_dmem_addr[31] ,
+ \u_riscv_top.core0_dmem_addr[30] ,
+ \u_riscv_top.core0_dmem_addr[29] ,
+ \u_riscv_top.core0_dmem_addr[28] ,
+ \u_riscv_top.core0_dmem_addr[27] ,
+ \u_riscv_top.core0_dmem_addr[26] ,
+ \u_riscv_top.core0_dmem_addr[25] ,
+ \u_riscv_top.core0_dmem_addr[24] ,
+ \u_riscv_top.core0_dmem_addr[23] ,
+ \u_riscv_top.core0_dmem_addr[22] ,
+ \u_riscv_top.core0_dmem_addr[21] ,
+ \u_riscv_top.core0_dmem_addr[20] ,
+ \u_riscv_top.core0_dmem_addr[19] ,
+ \u_riscv_top.core0_dmem_addr[18] ,
+ \u_riscv_top.core0_dmem_addr[17] ,
+ \u_riscv_top.core0_dmem_addr[16] ,
+ \u_riscv_top.core0_dmem_addr[15] ,
+ \u_riscv_top.core0_dmem_addr[14] ,
+ \u_riscv_top.core0_dmem_addr[13] ,
+ \u_riscv_top.core0_dmem_addr[12] ,
+ \u_riscv_top.core0_dmem_addr[11] ,
+ \u_riscv_top.core0_dmem_addr[10] ,
+ \u_riscv_top.core0_dmem_addr[9] ,
+ \u_riscv_top.core0_dmem_addr[8] ,
+ \u_riscv_top.core0_dmem_addr[7] ,
+ \u_riscv_top.core0_dmem_addr[6] ,
+ \u_riscv_top.core0_dmem_addr[5] ,
+ \u_riscv_top.core0_dmem_addr[4] ,
+ \u_riscv_top.core0_dmem_addr[3] ,
+ \u_riscv_top.core0_dmem_addr[2] ,
+ \u_riscv_top.core0_dmem_addr[1] ,
+ \u_riscv_top.core0_dmem_addr[0] }),
+ .core0_dmem_rdata({\u_riscv_top.core0_dmem_rdata[31] ,
+ \u_riscv_top.core0_dmem_rdata[30] ,
+ \u_riscv_top.core0_dmem_rdata[29] ,
+ \u_riscv_top.core0_dmem_rdata[28] ,
+ \u_riscv_top.core0_dmem_rdata[27] ,
+ \u_riscv_top.core0_dmem_rdata[26] ,
+ \u_riscv_top.core0_dmem_rdata[25] ,
+ \u_riscv_top.core0_dmem_rdata[24] ,
+ \u_riscv_top.core0_dmem_rdata[23] ,
+ \u_riscv_top.core0_dmem_rdata[22] ,
+ \u_riscv_top.core0_dmem_rdata[21] ,
+ \u_riscv_top.core0_dmem_rdata[20] ,
+ \u_riscv_top.core0_dmem_rdata[19] ,
+ \u_riscv_top.core0_dmem_rdata[18] ,
+ \u_riscv_top.core0_dmem_rdata[17] ,
+ \u_riscv_top.core0_dmem_rdata[16] ,
+ \u_riscv_top.core0_dmem_rdata[15] ,
+ \u_riscv_top.core0_dmem_rdata[14] ,
+ \u_riscv_top.core0_dmem_rdata[13] ,
+ \u_riscv_top.core0_dmem_rdata[12] ,
+ \u_riscv_top.core0_dmem_rdata[11] ,
+ \u_riscv_top.core0_dmem_rdata[10] ,
+ \u_riscv_top.core0_dmem_rdata[9] ,
+ \u_riscv_top.core0_dmem_rdata[8] ,
+ \u_riscv_top.core0_dmem_rdata[7] ,
+ \u_riscv_top.core0_dmem_rdata[6] ,
+ \u_riscv_top.core0_dmem_rdata[5] ,
+ \u_riscv_top.core0_dmem_rdata[4] ,
+ \u_riscv_top.core0_dmem_rdata[3] ,
+ \u_riscv_top.core0_dmem_rdata[2] ,
+ \u_riscv_top.core0_dmem_rdata[1] ,
+ \u_riscv_top.core0_dmem_rdata[0] }),
+ .core0_dmem_resp({\u_riscv_top.core0_dmem_resp[1] ,
+ \u_riscv_top.core0_dmem_resp[0] }),
+ .core0_dmem_wdata({\u_riscv_top.core0_dmem_wdata[31] ,
+ \u_riscv_top.core0_dmem_wdata[30] ,
+ \u_riscv_top.core0_dmem_wdata[29] ,
+ \u_riscv_top.core0_dmem_wdata[28] ,
+ \u_riscv_top.core0_dmem_wdata[27] ,
+ \u_riscv_top.core0_dmem_wdata[26] ,
+ \u_riscv_top.core0_dmem_wdata[25] ,
+ \u_riscv_top.core0_dmem_wdata[24] ,
+ \u_riscv_top.core0_dmem_wdata[23] ,
+ \u_riscv_top.core0_dmem_wdata[22] ,
+ \u_riscv_top.core0_dmem_wdata[21] ,
+ \u_riscv_top.core0_dmem_wdata[20] ,
+ \u_riscv_top.core0_dmem_wdata[19] ,
+ \u_riscv_top.core0_dmem_wdata[18] ,
+ \u_riscv_top.core0_dmem_wdata[17] ,
+ \u_riscv_top.core0_dmem_wdata[16] ,
+ \u_riscv_top.core0_dmem_wdata[15] ,
+ \u_riscv_top.core0_dmem_wdata[14] ,
+ \u_riscv_top.core0_dmem_wdata[13] ,
+ \u_riscv_top.core0_dmem_wdata[12] ,
+ \u_riscv_top.core0_dmem_wdata[11] ,
+ \u_riscv_top.core0_dmem_wdata[10] ,
+ \u_riscv_top.core0_dmem_wdata[9] ,
+ \u_riscv_top.core0_dmem_wdata[8] ,
+ \u_riscv_top.core0_dmem_wdata[7] ,
+ \u_riscv_top.core0_dmem_wdata[6] ,
+ \u_riscv_top.core0_dmem_wdata[5] ,
+ \u_riscv_top.core0_dmem_wdata[4] ,
+ \u_riscv_top.core0_dmem_wdata[3] ,
+ \u_riscv_top.core0_dmem_wdata[2] ,
+ \u_riscv_top.core0_dmem_wdata[1] ,
+ \u_riscv_top.core0_dmem_wdata[0] }),
+ .core0_dmem_width({\u_riscv_top.core0_dmem_width[1] ,
+ \u_riscv_top.core0_dmem_width[0] }),
+ .core0_imem_addr({\u_riscv_top.core0_imem_addr[31] ,
+ \u_riscv_top.core0_imem_addr[30] ,
+ \u_riscv_top.core0_imem_addr[29] ,
+ \u_riscv_top.core0_imem_addr[28] ,
+ \u_riscv_top.core0_imem_addr[27] ,
+ \u_riscv_top.core0_imem_addr[26] ,
+ \u_riscv_top.core0_imem_addr[25] ,
+ \u_riscv_top.core0_imem_addr[24] ,
+ \u_riscv_top.core0_imem_addr[23] ,
+ \u_riscv_top.core0_imem_addr[22] ,
+ \u_riscv_top.core0_imem_addr[21] ,
+ \u_riscv_top.core0_imem_addr[20] ,
+ \u_riscv_top.core0_imem_addr[19] ,
+ \u_riscv_top.core0_imem_addr[18] ,
+ \u_riscv_top.core0_imem_addr[17] ,
+ \u_riscv_top.core0_imem_addr[16] ,
+ \u_riscv_top.core0_imem_addr[15] ,
+ \u_riscv_top.core0_imem_addr[14] ,
+ \u_riscv_top.core0_imem_addr[13] ,
+ \u_riscv_top.core0_imem_addr[12] ,
+ \u_riscv_top.core0_imem_addr[11] ,
+ \u_riscv_top.core0_imem_addr[10] ,
+ \u_riscv_top.core0_imem_addr[9] ,
+ \u_riscv_top.core0_imem_addr[8] ,
+ \u_riscv_top.core0_imem_addr[7] ,
+ \u_riscv_top.core0_imem_addr[6] ,
+ \u_riscv_top.core0_imem_addr[5] ,
+ \u_riscv_top.core0_imem_addr[4] ,
+ \u_riscv_top.core0_imem_addr[3] ,
+ \u_riscv_top.core0_imem_addr[2] ,
+ \u_riscv_top.core0_imem_addr[1] ,
+ \u_riscv_top.core0_imem_addr[0] }),
+ .core0_imem_bl({\u_riscv_top.core0_imem_bl[2] ,
+ \u_riscv_top.core0_imem_bl[1] ,
+ \u_riscv_top.core0_imem_bl[0] }),
+ .core0_imem_rdata({\u_riscv_top.core0_imem_rdata[31] ,
+ \u_riscv_top.core0_imem_rdata[30] ,
+ \u_riscv_top.core0_imem_rdata[29] ,
+ \u_riscv_top.core0_imem_rdata[28] ,
+ \u_riscv_top.core0_imem_rdata[27] ,
+ \u_riscv_top.core0_imem_rdata[26] ,
+ \u_riscv_top.core0_imem_rdata[25] ,
+ \u_riscv_top.core0_imem_rdata[24] ,
+ \u_riscv_top.core0_imem_rdata[23] ,
+ \u_riscv_top.core0_imem_rdata[22] ,
+ \u_riscv_top.core0_imem_rdata[21] ,
+ \u_riscv_top.core0_imem_rdata[20] ,
+ \u_riscv_top.core0_imem_rdata[19] ,
+ \u_riscv_top.core0_imem_rdata[18] ,
+ \u_riscv_top.core0_imem_rdata[17] ,
+ \u_riscv_top.core0_imem_rdata[16] ,
+ \u_riscv_top.core0_imem_rdata[15] ,
+ \u_riscv_top.core0_imem_rdata[14] ,
+ \u_riscv_top.core0_imem_rdata[13] ,
+ \u_riscv_top.core0_imem_rdata[12] ,
+ \u_riscv_top.core0_imem_rdata[11] ,
+ \u_riscv_top.core0_imem_rdata[10] ,
+ \u_riscv_top.core0_imem_rdata[9] ,
+ \u_riscv_top.core0_imem_rdata[8] ,
+ \u_riscv_top.core0_imem_rdata[7] ,
+ \u_riscv_top.core0_imem_rdata[6] ,
+ \u_riscv_top.core0_imem_rdata[5] ,
+ \u_riscv_top.core0_imem_rdata[4] ,
+ \u_riscv_top.core0_imem_rdata[3] ,
+ \u_riscv_top.core0_imem_rdata[2] ,
+ \u_riscv_top.core0_imem_rdata[1] ,
+ \u_riscv_top.core0_imem_rdata[0] }),
+ .core0_imem_resp({\u_riscv_top.core0_imem_resp[1] ,
+ \u_riscv_top.core0_imem_resp[0] }),
+ .core0_irq_lines({\u_riscv_top.core0_irq_lines[15] ,
+ \u_riscv_top.core0_irq_lines[14] ,
+ \u_riscv_top.core0_irq_lines[13] ,
+ \u_riscv_top.core0_irq_lines[12] ,
+ \u_riscv_top.core0_irq_lines[11] ,
+ \u_riscv_top.core0_irq_lines[10] ,
+ \u_riscv_top.core0_irq_lines[9] ,
+ \u_riscv_top.core0_irq_lines[8] ,
+ \u_riscv_top.core0_irq_lines[7] ,
+ \u_riscv_top.core0_irq_lines[6] ,
+ \u_riscv_top.core0_irq_lines[5] ,
+ \u_riscv_top.core0_irq_lines[4] ,
+ \u_riscv_top.core0_irq_lines[3] ,
+ \u_riscv_top.core0_irq_lines[2] ,
+ \u_riscv_top.core0_irq_lines[1] ,
+ \u_riscv_top.core0_irq_lines[0] }),
+ .core0_timer_val({\u_riscv_top.core0_timer_val[63] ,
+ \u_riscv_top.core0_timer_val[62] ,
+ \u_riscv_top.core0_timer_val[61] ,
+ \u_riscv_top.core0_timer_val[60] ,
+ \u_riscv_top.core0_timer_val[59] ,
+ \u_riscv_top.core0_timer_val[58] ,
+ \u_riscv_top.core0_timer_val[57] ,
+ \u_riscv_top.core0_timer_val[56] ,
+ \u_riscv_top.core0_timer_val[55] ,
+ \u_riscv_top.core0_timer_val[54] ,
+ \u_riscv_top.core0_timer_val[53] ,
+ \u_riscv_top.core0_timer_val[52] ,
+ \u_riscv_top.core0_timer_val[51] ,
+ \u_riscv_top.core0_timer_val[50] ,
+ \u_riscv_top.core0_timer_val[49] ,
+ \u_riscv_top.core0_timer_val[48] ,
+ \u_riscv_top.core0_timer_val[47] ,
+ \u_riscv_top.core0_timer_val[46] ,
+ \u_riscv_top.core0_timer_val[45] ,
+ \u_riscv_top.core0_timer_val[44] ,
+ \u_riscv_top.core0_timer_val[43] ,
+ \u_riscv_top.core0_timer_val[42] ,
+ \u_riscv_top.core0_timer_val[41] ,
+ \u_riscv_top.core0_timer_val[40] ,
+ \u_riscv_top.core0_timer_val[39] ,
+ \u_riscv_top.core0_timer_val[38] ,
+ \u_riscv_top.core0_timer_val[37] ,
+ \u_riscv_top.core0_timer_val[36] ,
+ \u_riscv_top.core0_timer_val[35] ,
+ \u_riscv_top.core0_timer_val[34] ,
+ \u_riscv_top.core0_timer_val[33] ,
+ \u_riscv_top.core0_timer_val[32] ,
+ \u_riscv_top.core0_timer_val[31] ,
+ \u_riscv_top.core0_timer_val[30] ,
+ \u_riscv_top.core0_timer_val[29] ,
+ \u_riscv_top.core0_timer_val[28] ,
+ \u_riscv_top.core0_timer_val[27] ,
+ \u_riscv_top.core0_timer_val[26] ,
+ \u_riscv_top.core0_timer_val[25] ,
+ \u_riscv_top.core0_timer_val[24] ,
+ \u_riscv_top.core0_timer_val[23] ,
+ \u_riscv_top.core0_timer_val[22] ,
+ \u_riscv_top.core0_timer_val[21] ,
+ \u_riscv_top.core0_timer_val[20] ,
+ \u_riscv_top.core0_timer_val[19] ,
+ \u_riscv_top.core0_timer_val[18] ,
+ \u_riscv_top.core0_timer_val[17] ,
+ \u_riscv_top.core0_timer_val[16] ,
+ \u_riscv_top.core0_timer_val[15] ,
+ \u_riscv_top.core0_timer_val[14] ,
+ \u_riscv_top.core0_timer_val[13] ,
+ \u_riscv_top.core0_timer_val[12] ,
+ \u_riscv_top.core0_timer_val[11] ,
+ \u_riscv_top.core0_timer_val[10] ,
+ \u_riscv_top.core0_timer_val[9] ,
+ \u_riscv_top.core0_timer_val[8] ,
+ \u_riscv_top.core0_timer_val[7] ,
+ \u_riscv_top.core0_timer_val[6] ,
+ \u_riscv_top.core0_timer_val[5] ,
+ \u_riscv_top.core0_timer_val[4] ,
+ \u_riscv_top.core0_timer_val[3] ,
+ \u_riscv_top.core0_timer_val[2] ,
+ \u_riscv_top.core0_timer_val[1] ,
+ \u_riscv_top.core0_timer_val[0] }),
+ .core0_uid({\u_riscv_top.core0_uid[1] ,
+ \u_riscv_top.core0_uid[0] }),
+ .core1_debug({\u_riscv_top.core1_debug[48] ,
+ \u_riscv_top.core1_debug[47] ,
+ \u_riscv_top.core1_debug[46] ,
+ \u_riscv_top.core1_debug[45] ,
+ \u_riscv_top.core1_debug[44] ,
+ \u_riscv_top.core1_debug[43] ,
+ \u_riscv_top.core1_debug[42] ,
+ \u_riscv_top.core1_debug[41] ,
+ \u_riscv_top.core1_debug[40] ,
+ \u_riscv_top.core1_debug[39] ,
+ \u_riscv_top.core1_debug[38] ,
+ \u_riscv_top.core1_debug[37] ,
+ \u_riscv_top.core1_debug[36] ,
+ \u_riscv_top.core1_debug[35] ,
+ \u_riscv_top.core1_debug[34] ,
+ \u_riscv_top.core1_debug[33] ,
+ \u_riscv_top.core1_debug[32] ,
+ \u_riscv_top.core1_debug[31] ,
+ \u_riscv_top.core1_debug[30] ,
+ \u_riscv_top.core1_debug[29] ,
+ \u_riscv_top.core1_debug[28] ,
+ \u_riscv_top.core1_debug[27] ,
+ \u_riscv_top.core1_debug[26] ,
+ \u_riscv_top.core1_debug[25] ,
+ \u_riscv_top.core1_debug[24] ,
+ \u_riscv_top.core1_debug[23] ,
+ \u_riscv_top.core1_debug[22] ,
+ \u_riscv_top.core1_debug[21] ,
+ \u_riscv_top.core1_debug[20] ,
+ \u_riscv_top.core1_debug[19] ,
+ \u_riscv_top.core1_debug[18] ,
+ \u_riscv_top.core1_debug[17] ,
+ \u_riscv_top.core1_debug[16] ,
+ \u_riscv_top.core1_debug[15] ,
+ \u_riscv_top.core1_debug[14] ,
+ \u_riscv_top.core1_debug[13] ,
+ \u_riscv_top.core1_debug[12] ,
+ \u_riscv_top.core1_debug[11] ,
+ \u_riscv_top.core1_debug[10] ,
+ \u_riscv_top.core1_debug[9] ,
+ \u_riscv_top.core1_debug[8] ,
+ \u_riscv_top.core1_debug[7] ,
+ \u_riscv_top.core1_debug[6] ,
+ \u_riscv_top.core1_debug[5] ,
+ \u_riscv_top.core1_debug[4] ,
+ \u_riscv_top.core1_debug[3] ,
+ \u_riscv_top.core1_debug[2] ,
+ \u_riscv_top.core1_debug[1] ,
+ \u_riscv_top.core1_debug[0] }),
+ .core1_dmem_addr({\u_riscv_top.core1_dmem_addr[31] ,
+ \u_riscv_top.core1_dmem_addr[30] ,
+ \u_riscv_top.core1_dmem_addr[29] ,
+ \u_riscv_top.core1_dmem_addr[28] ,
+ \u_riscv_top.core1_dmem_addr[27] ,
+ \u_riscv_top.core1_dmem_addr[26] ,
+ \u_riscv_top.core1_dmem_addr[25] ,
+ \u_riscv_top.core1_dmem_addr[24] ,
+ \u_riscv_top.core1_dmem_addr[23] ,
+ \u_riscv_top.core1_dmem_addr[22] ,
+ \u_riscv_top.core1_dmem_addr[21] ,
+ \u_riscv_top.core1_dmem_addr[20] ,
+ \u_riscv_top.core1_dmem_addr[19] ,
+ \u_riscv_top.core1_dmem_addr[18] ,
+ \u_riscv_top.core1_dmem_addr[17] ,
+ \u_riscv_top.core1_dmem_addr[16] ,
+ \u_riscv_top.core1_dmem_addr[15] ,
+ \u_riscv_top.core1_dmem_addr[14] ,
+ \u_riscv_top.core1_dmem_addr[13] ,
+ \u_riscv_top.core1_dmem_addr[12] ,
+ \u_riscv_top.core1_dmem_addr[11] ,
+ \u_riscv_top.core1_dmem_addr[10] ,
+ \u_riscv_top.core1_dmem_addr[9] ,
+ \u_riscv_top.core1_dmem_addr[8] ,
+ \u_riscv_top.core1_dmem_addr[7] ,
+ \u_riscv_top.core1_dmem_addr[6] ,
+ \u_riscv_top.core1_dmem_addr[5] ,
+ \u_riscv_top.core1_dmem_addr[4] ,
+ \u_riscv_top.core1_dmem_addr[3] ,
+ \u_riscv_top.core1_dmem_addr[2] ,
+ \u_riscv_top.core1_dmem_addr[1] ,
+ \u_riscv_top.core1_dmem_addr[0] }),
+ .core1_dmem_rdata({\u_riscv_top.core1_dmem_rdata[31] ,
+ \u_riscv_top.core1_dmem_rdata[30] ,
+ \u_riscv_top.core1_dmem_rdata[29] ,
+ \u_riscv_top.core1_dmem_rdata[28] ,
+ \u_riscv_top.core1_dmem_rdata[27] ,
+ \u_riscv_top.core1_dmem_rdata[26] ,
+ \u_riscv_top.core1_dmem_rdata[25] ,
+ \u_riscv_top.core1_dmem_rdata[24] ,
+ \u_riscv_top.core1_dmem_rdata[23] ,
+ \u_riscv_top.core1_dmem_rdata[22] ,
+ \u_riscv_top.core1_dmem_rdata[21] ,
+ \u_riscv_top.core1_dmem_rdata[20] ,
+ \u_riscv_top.core1_dmem_rdata[19] ,
+ \u_riscv_top.core1_dmem_rdata[18] ,
+ \u_riscv_top.core1_dmem_rdata[17] ,
+ \u_riscv_top.core1_dmem_rdata[16] ,
+ \u_riscv_top.core1_dmem_rdata[15] ,
+ \u_riscv_top.core1_dmem_rdata[14] ,
+ \u_riscv_top.core1_dmem_rdata[13] ,
+ \u_riscv_top.core1_dmem_rdata[12] ,
+ \u_riscv_top.core1_dmem_rdata[11] ,
+ \u_riscv_top.core1_dmem_rdata[10] ,
+ \u_riscv_top.core1_dmem_rdata[9] ,
+ \u_riscv_top.core1_dmem_rdata[8] ,
+ \u_riscv_top.core1_dmem_rdata[7] ,
+ \u_riscv_top.core1_dmem_rdata[6] ,
+ \u_riscv_top.core1_dmem_rdata[5] ,
+ \u_riscv_top.core1_dmem_rdata[4] ,
+ \u_riscv_top.core1_dmem_rdata[3] ,
+ \u_riscv_top.core1_dmem_rdata[2] ,
+ \u_riscv_top.core1_dmem_rdata[1] ,
+ \u_riscv_top.core1_dmem_rdata[0] }),
+ .core1_dmem_resp({\u_riscv_top.core1_dmem_resp[1] ,
+ \u_riscv_top.core1_dmem_resp[0] }),
+ .core1_dmem_wdata({\u_riscv_top.core1_dmem_wdata[31] ,
+ \u_riscv_top.core1_dmem_wdata[30] ,
+ \u_riscv_top.core1_dmem_wdata[29] ,
+ \u_riscv_top.core1_dmem_wdata[28] ,
+ \u_riscv_top.core1_dmem_wdata[27] ,
+ \u_riscv_top.core1_dmem_wdata[26] ,
+ \u_riscv_top.core1_dmem_wdata[25] ,
+ \u_riscv_top.core1_dmem_wdata[24] ,
+ \u_riscv_top.core1_dmem_wdata[23] ,
+ \u_riscv_top.core1_dmem_wdata[22] ,
+ \u_riscv_top.core1_dmem_wdata[21] ,
+ \u_riscv_top.core1_dmem_wdata[20] ,
+ \u_riscv_top.core1_dmem_wdata[19] ,
+ \u_riscv_top.core1_dmem_wdata[18] ,
+ \u_riscv_top.core1_dmem_wdata[17] ,
+ \u_riscv_top.core1_dmem_wdata[16] ,
+ \u_riscv_top.core1_dmem_wdata[15] ,
+ \u_riscv_top.core1_dmem_wdata[14] ,
+ \u_riscv_top.core1_dmem_wdata[13] ,
+ \u_riscv_top.core1_dmem_wdata[12] ,
+ \u_riscv_top.core1_dmem_wdata[11] ,
+ \u_riscv_top.core1_dmem_wdata[10] ,
+ \u_riscv_top.core1_dmem_wdata[9] ,
+ \u_riscv_top.core1_dmem_wdata[8] ,
+ \u_riscv_top.core1_dmem_wdata[7] ,
+ \u_riscv_top.core1_dmem_wdata[6] ,
+ \u_riscv_top.core1_dmem_wdata[5] ,
+ \u_riscv_top.core1_dmem_wdata[4] ,
+ \u_riscv_top.core1_dmem_wdata[3] ,
+ \u_riscv_top.core1_dmem_wdata[2] ,
+ \u_riscv_top.core1_dmem_wdata[1] ,
+ \u_riscv_top.core1_dmem_wdata[0] }),
+ .core1_dmem_width({\u_riscv_top.core1_dmem_width[1] ,
+ \u_riscv_top.core1_dmem_width[0] }),
+ .core1_imem_addr({\u_riscv_top.core1_imem_addr[31] ,
+ \u_riscv_top.core1_imem_addr[30] ,
+ \u_riscv_top.core1_imem_addr[29] ,
+ \u_riscv_top.core1_imem_addr[28] ,
+ \u_riscv_top.core1_imem_addr[27] ,
+ \u_riscv_top.core1_imem_addr[26] ,
+ \u_riscv_top.core1_imem_addr[25] ,
+ \u_riscv_top.core1_imem_addr[24] ,
+ \u_riscv_top.core1_imem_addr[23] ,
+ \u_riscv_top.core1_imem_addr[22] ,
+ \u_riscv_top.core1_imem_addr[21] ,
+ \u_riscv_top.core1_imem_addr[20] ,
+ \u_riscv_top.core1_imem_addr[19] ,
+ \u_riscv_top.core1_imem_addr[18] ,
+ \u_riscv_top.core1_imem_addr[17] ,
+ \u_riscv_top.core1_imem_addr[16] ,
+ \u_riscv_top.core1_imem_addr[15] ,
+ \u_riscv_top.core1_imem_addr[14] ,
+ \u_riscv_top.core1_imem_addr[13] ,
+ \u_riscv_top.core1_imem_addr[12] ,
+ \u_riscv_top.core1_imem_addr[11] ,
+ \u_riscv_top.core1_imem_addr[10] ,
+ \u_riscv_top.core1_imem_addr[9] ,
+ \u_riscv_top.core1_imem_addr[8] ,
+ \u_riscv_top.core1_imem_addr[7] ,
+ \u_riscv_top.core1_imem_addr[6] ,
+ \u_riscv_top.core1_imem_addr[5] ,
+ \u_riscv_top.core1_imem_addr[4] ,
+ \u_riscv_top.core1_imem_addr[3] ,
+ \u_riscv_top.core1_imem_addr[2] ,
+ \u_riscv_top.core1_imem_addr[1] ,
+ \u_riscv_top.core1_imem_addr[0] }),
+ .core1_imem_bl({\u_riscv_top.core1_imem_bl[2] ,
+ \u_riscv_top.core1_imem_bl[1] ,
+ \u_riscv_top.core1_imem_bl[0] }),
+ .core1_imem_rdata({\u_riscv_top.core1_imem_rdata[31] ,
+ \u_riscv_top.core1_imem_rdata[30] ,
+ \u_riscv_top.core1_imem_rdata[29] ,
+ \u_riscv_top.core1_imem_rdata[28] ,
+ \u_riscv_top.core1_imem_rdata[27] ,
+ \u_riscv_top.core1_imem_rdata[26] ,
+ \u_riscv_top.core1_imem_rdata[25] ,
+ \u_riscv_top.core1_imem_rdata[24] ,
+ \u_riscv_top.core1_imem_rdata[23] ,
+ \u_riscv_top.core1_imem_rdata[22] ,
+ \u_riscv_top.core1_imem_rdata[21] ,
+ \u_riscv_top.core1_imem_rdata[20] ,
+ \u_riscv_top.core1_imem_rdata[19] ,
+ \u_riscv_top.core1_imem_rdata[18] ,
+ \u_riscv_top.core1_imem_rdata[17] ,
+ \u_riscv_top.core1_imem_rdata[16] ,
+ \u_riscv_top.core1_imem_rdata[15] ,
+ \u_riscv_top.core1_imem_rdata[14] ,
+ \u_riscv_top.core1_imem_rdata[13] ,
+ \u_riscv_top.core1_imem_rdata[12] ,
+ \u_riscv_top.core1_imem_rdata[11] ,
+ \u_riscv_top.core1_imem_rdata[10] ,
+ \u_riscv_top.core1_imem_rdata[9] ,
+ \u_riscv_top.core1_imem_rdata[8] ,
+ \u_riscv_top.core1_imem_rdata[7] ,
+ \u_riscv_top.core1_imem_rdata[6] ,
+ \u_riscv_top.core1_imem_rdata[5] ,
+ \u_riscv_top.core1_imem_rdata[4] ,
+ \u_riscv_top.core1_imem_rdata[3] ,
+ \u_riscv_top.core1_imem_rdata[2] ,
+ \u_riscv_top.core1_imem_rdata[1] ,
+ \u_riscv_top.core1_imem_rdata[0] }),
+ .core1_imem_resp({\u_riscv_top.core1_imem_resp[1] ,
+ \u_riscv_top.core1_imem_resp[0] }),
+ .core1_irq_lines({\u_riscv_top.core1_irq_lines[15] ,
+ \u_riscv_top.core1_irq_lines[14] ,
+ \u_riscv_top.core1_irq_lines[13] ,
+ \u_riscv_top.core1_irq_lines[12] ,
+ \u_riscv_top.core1_irq_lines[11] ,
+ \u_riscv_top.core1_irq_lines[10] ,
+ \u_riscv_top.core1_irq_lines[9] ,
+ \u_riscv_top.core1_irq_lines[8] ,
+ \u_riscv_top.core1_irq_lines[7] ,
+ \u_riscv_top.core1_irq_lines[6] ,
+ \u_riscv_top.core1_irq_lines[5] ,
+ \u_riscv_top.core1_irq_lines[4] ,
+ \u_riscv_top.core1_irq_lines[3] ,
+ \u_riscv_top.core1_irq_lines[2] ,
+ \u_riscv_top.core1_irq_lines[1] ,
+ \u_riscv_top.core1_irq_lines[0] }),
+ .core1_timer_val({\u_riscv_top.core1_timer_val[63] ,
+ \u_riscv_top.core1_timer_val[62] ,
+ \u_riscv_top.core1_timer_val[61] ,
+ \u_riscv_top.core1_timer_val[60] ,
+ \u_riscv_top.core1_timer_val[59] ,
+ \u_riscv_top.core1_timer_val[58] ,
+ \u_riscv_top.core1_timer_val[57] ,
+ \u_riscv_top.core1_timer_val[56] ,
+ \u_riscv_top.core1_timer_val[55] ,
+ \u_riscv_top.core1_timer_val[54] ,
+ \u_riscv_top.core1_timer_val[53] ,
+ \u_riscv_top.core1_timer_val[52] ,
+ \u_riscv_top.core1_timer_val[51] ,
+ \u_riscv_top.core1_timer_val[50] ,
+ \u_riscv_top.core1_timer_val[49] ,
+ \u_riscv_top.core1_timer_val[48] ,
+ \u_riscv_top.core1_timer_val[47] ,
+ \u_riscv_top.core1_timer_val[46] ,
+ \u_riscv_top.core1_timer_val[45] ,
+ \u_riscv_top.core1_timer_val[44] ,
+ \u_riscv_top.core1_timer_val[43] ,
+ \u_riscv_top.core1_timer_val[42] ,
+ \u_riscv_top.core1_timer_val[41] ,
+ \u_riscv_top.core1_timer_val[40] ,
+ \u_riscv_top.core1_timer_val[39] ,
+ \u_riscv_top.core1_timer_val[38] ,
+ \u_riscv_top.core1_timer_val[37] ,
+ \u_riscv_top.core1_timer_val[36] ,
+ \u_riscv_top.core1_timer_val[35] ,
+ \u_riscv_top.core1_timer_val[34] ,
+ \u_riscv_top.core1_timer_val[33] ,
+ \u_riscv_top.core1_timer_val[32] ,
+ \u_riscv_top.core1_timer_val[31] ,
+ \u_riscv_top.core1_timer_val[30] ,
+ \u_riscv_top.core1_timer_val[29] ,
+ \u_riscv_top.core1_timer_val[28] ,
+ \u_riscv_top.core1_timer_val[27] ,
+ \u_riscv_top.core1_timer_val[26] ,
+ \u_riscv_top.core1_timer_val[25] ,
+ \u_riscv_top.core1_timer_val[24] ,
+ \u_riscv_top.core1_timer_val[23] ,
+ \u_riscv_top.core1_timer_val[22] ,
+ \u_riscv_top.core1_timer_val[21] ,
+ \u_riscv_top.core1_timer_val[20] ,
+ \u_riscv_top.core1_timer_val[19] ,
+ \u_riscv_top.core1_timer_val[18] ,
+ \u_riscv_top.core1_timer_val[17] ,
+ \u_riscv_top.core1_timer_val[16] ,
+ \u_riscv_top.core1_timer_val[15] ,
+ \u_riscv_top.core1_timer_val[14] ,
+ \u_riscv_top.core1_timer_val[13] ,
+ \u_riscv_top.core1_timer_val[12] ,
+ \u_riscv_top.core1_timer_val[11] ,
+ \u_riscv_top.core1_timer_val[10] ,
+ \u_riscv_top.core1_timer_val[9] ,
+ \u_riscv_top.core1_timer_val[8] ,
+ \u_riscv_top.core1_timer_val[7] ,
+ \u_riscv_top.core1_timer_val[6] ,
+ \u_riscv_top.core1_timer_val[5] ,
+ \u_riscv_top.core1_timer_val[4] ,
+ \u_riscv_top.core1_timer_val[3] ,
+ \u_riscv_top.core1_timer_val[2] ,
+ \u_riscv_top.core1_timer_val[1] ,
+ \u_riscv_top.core1_timer_val[0] }),
+ .core1_uid({\u_riscv_top.core1_uid[1] ,
+ \u_riscv_top.core1_uid[0] }),
+ .core2_debug({\u_riscv_top.core2_debug[48] ,
+ \u_riscv_top.core2_debug[47] ,
+ \u_riscv_top.core2_debug[46] ,
+ \u_riscv_top.core2_debug[45] ,
+ \u_riscv_top.core2_debug[44] ,
+ \u_riscv_top.core2_debug[43] ,
+ \u_riscv_top.core2_debug[42] ,
+ \u_riscv_top.core2_debug[41] ,
+ \u_riscv_top.core2_debug[40] ,
+ \u_riscv_top.core2_debug[39] ,
+ \u_riscv_top.core2_debug[38] ,
+ \u_riscv_top.core2_debug[37] ,
+ \u_riscv_top.core2_debug[36] ,
+ \u_riscv_top.core2_debug[35] ,
+ \u_riscv_top.core2_debug[34] ,
+ \u_riscv_top.core2_debug[33] ,
+ \u_riscv_top.core2_debug[32] ,
+ \u_riscv_top.core2_debug[31] ,
+ \u_riscv_top.core2_debug[30] ,
+ \u_riscv_top.core2_debug[29] ,
+ \u_riscv_top.core2_debug[28] ,
+ \u_riscv_top.core2_debug[27] ,
+ \u_riscv_top.core2_debug[26] ,
+ \u_riscv_top.core2_debug[25] ,
+ \u_riscv_top.core2_debug[24] ,
+ \u_riscv_top.core2_debug[23] ,
+ \u_riscv_top.core2_debug[22] ,
+ \u_riscv_top.core2_debug[21] ,
+ \u_riscv_top.core2_debug[20] ,
+ \u_riscv_top.core2_debug[19] ,
+ \u_riscv_top.core2_debug[18] ,
+ \u_riscv_top.core2_debug[17] ,
+ \u_riscv_top.core2_debug[16] ,
+ \u_riscv_top.core2_debug[15] ,
+ \u_riscv_top.core2_debug[14] ,
+ \u_riscv_top.core2_debug[13] ,
+ \u_riscv_top.core2_debug[12] ,
+ \u_riscv_top.core2_debug[11] ,
+ \u_riscv_top.core2_debug[10] ,
+ \u_riscv_top.core2_debug[9] ,
+ \u_riscv_top.core2_debug[8] ,
+ \u_riscv_top.core2_debug[7] ,
+ \u_riscv_top.core2_debug[6] ,
+ \u_riscv_top.core2_debug[5] ,
+ \u_riscv_top.core2_debug[4] ,
+ \u_riscv_top.core2_debug[3] ,
+ \u_riscv_top.core2_debug[2] ,
+ \u_riscv_top.core2_debug[1] ,
+ \u_riscv_top.core2_debug[0] }),
+ .core2_dmem_addr({\u_riscv_top.core2_dmem_addr[31] ,
+ \u_riscv_top.core2_dmem_addr[30] ,
+ \u_riscv_top.core2_dmem_addr[29] ,
+ \u_riscv_top.core2_dmem_addr[28] ,
+ \u_riscv_top.core2_dmem_addr[27] ,
+ \u_riscv_top.core2_dmem_addr[26] ,
+ \u_riscv_top.core2_dmem_addr[25] ,
+ \u_riscv_top.core2_dmem_addr[24] ,
+ \u_riscv_top.core2_dmem_addr[23] ,
+ \u_riscv_top.core2_dmem_addr[22] ,
+ \u_riscv_top.core2_dmem_addr[21] ,
+ \u_riscv_top.core2_dmem_addr[20] ,
+ \u_riscv_top.core2_dmem_addr[19] ,
+ \u_riscv_top.core2_dmem_addr[18] ,
+ \u_riscv_top.core2_dmem_addr[17] ,
+ \u_riscv_top.core2_dmem_addr[16] ,
+ \u_riscv_top.core2_dmem_addr[15] ,
+ \u_riscv_top.core2_dmem_addr[14] ,
+ \u_riscv_top.core2_dmem_addr[13] ,
+ \u_riscv_top.core2_dmem_addr[12] ,
+ \u_riscv_top.core2_dmem_addr[11] ,
+ \u_riscv_top.core2_dmem_addr[10] ,
+ \u_riscv_top.core2_dmem_addr[9] ,
+ \u_riscv_top.core2_dmem_addr[8] ,
+ \u_riscv_top.core2_dmem_addr[7] ,
+ \u_riscv_top.core2_dmem_addr[6] ,
+ \u_riscv_top.core2_dmem_addr[5] ,
+ \u_riscv_top.core2_dmem_addr[4] ,
+ \u_riscv_top.core2_dmem_addr[3] ,
+ \u_riscv_top.core2_dmem_addr[2] ,
+ \u_riscv_top.core2_dmem_addr[1] ,
+ \u_riscv_top.core2_dmem_addr[0] }),
+ .core2_dmem_rdata({\u_riscv_top.core2_dmem_rdata[31] ,
+ \u_riscv_top.core2_dmem_rdata[30] ,
+ \u_riscv_top.core2_dmem_rdata[29] ,
+ \u_riscv_top.core2_dmem_rdata[28] ,
+ \u_riscv_top.core2_dmem_rdata[27] ,
+ \u_riscv_top.core2_dmem_rdata[26] ,
+ \u_riscv_top.core2_dmem_rdata[25] ,
+ \u_riscv_top.core2_dmem_rdata[24] ,
+ \u_riscv_top.core2_dmem_rdata[23] ,
+ \u_riscv_top.core2_dmem_rdata[22] ,
+ \u_riscv_top.core2_dmem_rdata[21] ,
+ \u_riscv_top.core2_dmem_rdata[20] ,
+ \u_riscv_top.core2_dmem_rdata[19] ,
+ \u_riscv_top.core2_dmem_rdata[18] ,
+ \u_riscv_top.core2_dmem_rdata[17] ,
+ \u_riscv_top.core2_dmem_rdata[16] ,
+ \u_riscv_top.core2_dmem_rdata[15] ,
+ \u_riscv_top.core2_dmem_rdata[14] ,
+ \u_riscv_top.core2_dmem_rdata[13] ,
+ \u_riscv_top.core2_dmem_rdata[12] ,
+ \u_riscv_top.core2_dmem_rdata[11] ,
+ \u_riscv_top.core2_dmem_rdata[10] ,
+ \u_riscv_top.core2_dmem_rdata[9] ,
+ \u_riscv_top.core2_dmem_rdata[8] ,
+ \u_riscv_top.core2_dmem_rdata[7] ,
+ \u_riscv_top.core2_dmem_rdata[6] ,
+ \u_riscv_top.core2_dmem_rdata[5] ,
+ \u_riscv_top.core2_dmem_rdata[4] ,
+ \u_riscv_top.core2_dmem_rdata[3] ,
+ \u_riscv_top.core2_dmem_rdata[2] ,
+ \u_riscv_top.core2_dmem_rdata[1] ,
+ \u_riscv_top.core2_dmem_rdata[0] }),
+ .core2_dmem_resp({\u_riscv_top.core2_dmem_resp[1] ,
+ \u_riscv_top.core2_dmem_resp[0] }),
+ .core2_dmem_wdata({\u_riscv_top.core2_dmem_wdata[31] ,
+ \u_riscv_top.core2_dmem_wdata[30] ,
+ \u_riscv_top.core2_dmem_wdata[29] ,
+ \u_riscv_top.core2_dmem_wdata[28] ,
+ \u_riscv_top.core2_dmem_wdata[27] ,
+ \u_riscv_top.core2_dmem_wdata[26] ,
+ \u_riscv_top.core2_dmem_wdata[25] ,
+ \u_riscv_top.core2_dmem_wdata[24] ,
+ \u_riscv_top.core2_dmem_wdata[23] ,
+ \u_riscv_top.core2_dmem_wdata[22] ,
+ \u_riscv_top.core2_dmem_wdata[21] ,
+ \u_riscv_top.core2_dmem_wdata[20] ,
+ \u_riscv_top.core2_dmem_wdata[19] ,
+ \u_riscv_top.core2_dmem_wdata[18] ,
+ \u_riscv_top.core2_dmem_wdata[17] ,
+ \u_riscv_top.core2_dmem_wdata[16] ,
+ \u_riscv_top.core2_dmem_wdata[15] ,
+ \u_riscv_top.core2_dmem_wdata[14] ,
+ \u_riscv_top.core2_dmem_wdata[13] ,
+ \u_riscv_top.core2_dmem_wdata[12] ,
+ \u_riscv_top.core2_dmem_wdata[11] ,
+ \u_riscv_top.core2_dmem_wdata[10] ,
+ \u_riscv_top.core2_dmem_wdata[9] ,
+ \u_riscv_top.core2_dmem_wdata[8] ,
+ \u_riscv_top.core2_dmem_wdata[7] ,
+ \u_riscv_top.core2_dmem_wdata[6] ,
+ \u_riscv_top.core2_dmem_wdata[5] ,
+ \u_riscv_top.core2_dmem_wdata[4] ,
+ \u_riscv_top.core2_dmem_wdata[3] ,
+ \u_riscv_top.core2_dmem_wdata[2] ,
+ \u_riscv_top.core2_dmem_wdata[1] ,
+ \u_riscv_top.core2_dmem_wdata[0] }),
+ .core2_dmem_width({\u_riscv_top.core2_dmem_width[1] ,
+ \u_riscv_top.core2_dmem_width[0] }),
+ .core2_imem_addr({\u_riscv_top.core2_imem_addr[31] ,
+ \u_riscv_top.core2_imem_addr[30] ,
+ \u_riscv_top.core2_imem_addr[29] ,
+ \u_riscv_top.core2_imem_addr[28] ,
+ \u_riscv_top.core2_imem_addr[27] ,
+ \u_riscv_top.core2_imem_addr[26] ,
+ \u_riscv_top.core2_imem_addr[25] ,
+ \u_riscv_top.core2_imem_addr[24] ,
+ \u_riscv_top.core2_imem_addr[23] ,
+ \u_riscv_top.core2_imem_addr[22] ,
+ \u_riscv_top.core2_imem_addr[21] ,
+ \u_riscv_top.core2_imem_addr[20] ,
+ \u_riscv_top.core2_imem_addr[19] ,
+ \u_riscv_top.core2_imem_addr[18] ,
+ \u_riscv_top.core2_imem_addr[17] ,
+ \u_riscv_top.core2_imem_addr[16] ,
+ \u_riscv_top.core2_imem_addr[15] ,
+ \u_riscv_top.core2_imem_addr[14] ,
+ \u_riscv_top.core2_imem_addr[13] ,
+ \u_riscv_top.core2_imem_addr[12] ,
+ \u_riscv_top.core2_imem_addr[11] ,
+ \u_riscv_top.core2_imem_addr[10] ,
+ \u_riscv_top.core2_imem_addr[9] ,
+ \u_riscv_top.core2_imem_addr[8] ,
+ \u_riscv_top.core2_imem_addr[7] ,
+ \u_riscv_top.core2_imem_addr[6] ,
+ \u_riscv_top.core2_imem_addr[5] ,
+ \u_riscv_top.core2_imem_addr[4] ,
+ \u_riscv_top.core2_imem_addr[3] ,
+ \u_riscv_top.core2_imem_addr[2] ,
+ \u_riscv_top.core2_imem_addr[1] ,
+ \u_riscv_top.core2_imem_addr[0] }),
+ .core2_imem_bl({\u_riscv_top.core2_imem_bl[2] ,
+ \u_riscv_top.core2_imem_bl[1] ,
+ \u_riscv_top.core2_imem_bl[0] }),
+ .core2_imem_rdata({\u_riscv_top.core2_imem_rdata[31] ,
+ \u_riscv_top.core2_imem_rdata[30] ,
+ \u_riscv_top.core2_imem_rdata[29] ,
+ \u_riscv_top.core2_imem_rdata[28] ,
+ \u_riscv_top.core2_imem_rdata[27] ,
+ \u_riscv_top.core2_imem_rdata[26] ,
+ \u_riscv_top.core2_imem_rdata[25] ,
+ \u_riscv_top.core2_imem_rdata[24] ,
+ \u_riscv_top.core2_imem_rdata[23] ,
+ \u_riscv_top.core2_imem_rdata[22] ,
+ \u_riscv_top.core2_imem_rdata[21] ,
+ \u_riscv_top.core2_imem_rdata[20] ,
+ \u_riscv_top.core2_imem_rdata[19] ,
+ \u_riscv_top.core2_imem_rdata[18] ,
+ \u_riscv_top.core2_imem_rdata[17] ,
+ \u_riscv_top.core2_imem_rdata[16] ,
+ \u_riscv_top.core2_imem_rdata[15] ,
+ \u_riscv_top.core2_imem_rdata[14] ,
+ \u_riscv_top.core2_imem_rdata[13] ,
+ \u_riscv_top.core2_imem_rdata[12] ,
+ \u_riscv_top.core2_imem_rdata[11] ,
+ \u_riscv_top.core2_imem_rdata[10] ,
+ \u_riscv_top.core2_imem_rdata[9] ,
+ \u_riscv_top.core2_imem_rdata[8] ,
+ \u_riscv_top.core2_imem_rdata[7] ,
+ \u_riscv_top.core2_imem_rdata[6] ,
+ \u_riscv_top.core2_imem_rdata[5] ,
+ \u_riscv_top.core2_imem_rdata[4] ,
+ \u_riscv_top.core2_imem_rdata[3] ,
+ \u_riscv_top.core2_imem_rdata[2] ,
+ \u_riscv_top.core2_imem_rdata[1] ,
+ \u_riscv_top.core2_imem_rdata[0] }),
+ .core2_imem_resp({\u_riscv_top.core2_imem_resp[1] ,
+ \u_riscv_top.core2_imem_resp[0] }),
+ .core2_irq_lines({\u_riscv_top.core2_irq_lines[15] ,
+ \u_riscv_top.core2_irq_lines[14] ,
+ \u_riscv_top.core2_irq_lines[13] ,
+ \u_riscv_top.core2_irq_lines[12] ,
+ \u_riscv_top.core2_irq_lines[11] ,
+ \u_riscv_top.core2_irq_lines[10] ,
+ \u_riscv_top.core2_irq_lines[9] ,
+ \u_riscv_top.core2_irq_lines[8] ,
+ \u_riscv_top.core2_irq_lines[7] ,
+ \u_riscv_top.core2_irq_lines[6] ,
+ \u_riscv_top.core2_irq_lines[5] ,
+ \u_riscv_top.core2_irq_lines[4] ,
+ \u_riscv_top.core2_irq_lines[3] ,
+ \u_riscv_top.core2_irq_lines[2] ,
+ \u_riscv_top.core2_irq_lines[1] ,
+ \u_riscv_top.core2_irq_lines[0] }),
+ .core2_timer_val({\u_riscv_top.core2_timer_val[63] ,
+ \u_riscv_top.core2_timer_val[62] ,
+ \u_riscv_top.core2_timer_val[61] ,
+ \u_riscv_top.core2_timer_val[60] ,
+ \u_riscv_top.core2_timer_val[59] ,
+ \u_riscv_top.core2_timer_val[58] ,
+ \u_riscv_top.core2_timer_val[57] ,
+ \u_riscv_top.core2_timer_val[56] ,
+ \u_riscv_top.core2_timer_val[55] ,
+ \u_riscv_top.core2_timer_val[54] ,
+ \u_riscv_top.core2_timer_val[53] ,
+ \u_riscv_top.core2_timer_val[52] ,
+ \u_riscv_top.core2_timer_val[51] ,
+ \u_riscv_top.core2_timer_val[50] ,
+ \u_riscv_top.core2_timer_val[49] ,
+ \u_riscv_top.core2_timer_val[48] ,
+ \u_riscv_top.core2_timer_val[47] ,
+ \u_riscv_top.core2_timer_val[46] ,
+ \u_riscv_top.core2_timer_val[45] ,
+ \u_riscv_top.core2_timer_val[44] ,
+ \u_riscv_top.core2_timer_val[43] ,
+ \u_riscv_top.core2_timer_val[42] ,
+ \u_riscv_top.core2_timer_val[41] ,
+ \u_riscv_top.core2_timer_val[40] ,
+ \u_riscv_top.core2_timer_val[39] ,
+ \u_riscv_top.core2_timer_val[38] ,
+ \u_riscv_top.core2_timer_val[37] ,
+ \u_riscv_top.core2_timer_val[36] ,
+ \u_riscv_top.core2_timer_val[35] ,
+ \u_riscv_top.core2_timer_val[34] ,
+ \u_riscv_top.core2_timer_val[33] ,
+ \u_riscv_top.core2_timer_val[32] ,
+ \u_riscv_top.core2_timer_val[31] ,
+ \u_riscv_top.core2_timer_val[30] ,
+ \u_riscv_top.core2_timer_val[29] ,
+ \u_riscv_top.core2_timer_val[28] ,
+ \u_riscv_top.core2_timer_val[27] ,
+ \u_riscv_top.core2_timer_val[26] ,
+ \u_riscv_top.core2_timer_val[25] ,
+ \u_riscv_top.core2_timer_val[24] ,
+ \u_riscv_top.core2_timer_val[23] ,
+ \u_riscv_top.core2_timer_val[22] ,
+ \u_riscv_top.core2_timer_val[21] ,
+ \u_riscv_top.core2_timer_val[20] ,
+ \u_riscv_top.core2_timer_val[19] ,
+ \u_riscv_top.core2_timer_val[18] ,
+ \u_riscv_top.core2_timer_val[17] ,
+ \u_riscv_top.core2_timer_val[16] ,
+ \u_riscv_top.core2_timer_val[15] ,
+ \u_riscv_top.core2_timer_val[14] ,
+ \u_riscv_top.core2_timer_val[13] ,
+ \u_riscv_top.core2_timer_val[12] ,
+ \u_riscv_top.core2_timer_val[11] ,
+ \u_riscv_top.core2_timer_val[10] ,
+ \u_riscv_top.core2_timer_val[9] ,
+ \u_riscv_top.core2_timer_val[8] ,
+ \u_riscv_top.core2_timer_val[7] ,
+ \u_riscv_top.core2_timer_val[6] ,
+ \u_riscv_top.core2_timer_val[5] ,
+ \u_riscv_top.core2_timer_val[4] ,
+ \u_riscv_top.core2_timer_val[3] ,
+ \u_riscv_top.core2_timer_val[2] ,
+ \u_riscv_top.core2_timer_val[1] ,
+ \u_riscv_top.core2_timer_val[0] }),
+ .core2_uid({\u_riscv_top.core2_uid[1] ,
+ \u_riscv_top.core2_uid[0] }),
+ .core3_debug({\u_riscv_top.core3_debug[48] ,
+ \u_riscv_top.core3_debug[47] ,
+ \u_riscv_top.core3_debug[46] ,
+ \u_riscv_top.core3_debug[45] ,
+ \u_riscv_top.core3_debug[44] ,
+ \u_riscv_top.core3_debug[43] ,
+ \u_riscv_top.core3_debug[42] ,
+ \u_riscv_top.core3_debug[41] ,
+ \u_riscv_top.core3_debug[40] ,
+ \u_riscv_top.core3_debug[39] ,
+ \u_riscv_top.core3_debug[38] ,
+ \u_riscv_top.core3_debug[37] ,
+ \u_riscv_top.core3_debug[36] ,
+ \u_riscv_top.core3_debug[35] ,
+ \u_riscv_top.core3_debug[34] ,
+ \u_riscv_top.core3_debug[33] ,
+ \u_riscv_top.core3_debug[32] ,
+ \u_riscv_top.core3_debug[31] ,
+ \u_riscv_top.core3_debug[30] ,
+ \u_riscv_top.core3_debug[29] ,
+ \u_riscv_top.core3_debug[28] ,
+ \u_riscv_top.core3_debug[27] ,
+ \u_riscv_top.core3_debug[26] ,
+ \u_riscv_top.core3_debug[25] ,
+ \u_riscv_top.core3_debug[24] ,
+ \u_riscv_top.core3_debug[23] ,
+ \u_riscv_top.core3_debug[22] ,
+ \u_riscv_top.core3_debug[21] ,
+ \u_riscv_top.core3_debug[20] ,
+ \u_riscv_top.core3_debug[19] ,
+ \u_riscv_top.core3_debug[18] ,
+ \u_riscv_top.core3_debug[17] ,
+ \u_riscv_top.core3_debug[16] ,
+ \u_riscv_top.core3_debug[15] ,
+ \u_riscv_top.core3_debug[14] ,
+ \u_riscv_top.core3_debug[13] ,
+ \u_riscv_top.core3_debug[12] ,
+ \u_riscv_top.core3_debug[11] ,
+ \u_riscv_top.core3_debug[10] ,
+ \u_riscv_top.core3_debug[9] ,
+ \u_riscv_top.core3_debug[8] ,
+ \u_riscv_top.core3_debug[7] ,
+ \u_riscv_top.core3_debug[6] ,
+ \u_riscv_top.core3_debug[5] ,
+ \u_riscv_top.core3_debug[4] ,
+ \u_riscv_top.core3_debug[3] ,
+ \u_riscv_top.core3_debug[2] ,
+ \u_riscv_top.core3_debug[1] ,
+ \u_riscv_top.core3_debug[0] }),
+ .core3_dmem_addr({\u_riscv_top.core3_dmem_addr[31] ,
+ \u_riscv_top.core3_dmem_addr[30] ,
+ \u_riscv_top.core3_dmem_addr[29] ,
+ \u_riscv_top.core3_dmem_addr[28] ,
+ \u_riscv_top.core3_dmem_addr[27] ,
+ \u_riscv_top.core3_dmem_addr[26] ,
+ \u_riscv_top.core3_dmem_addr[25] ,
+ \u_riscv_top.core3_dmem_addr[24] ,
+ \u_riscv_top.core3_dmem_addr[23] ,
+ \u_riscv_top.core3_dmem_addr[22] ,
+ \u_riscv_top.core3_dmem_addr[21] ,
+ \u_riscv_top.core3_dmem_addr[20] ,
+ \u_riscv_top.core3_dmem_addr[19] ,
+ \u_riscv_top.core3_dmem_addr[18] ,
+ \u_riscv_top.core3_dmem_addr[17] ,
+ \u_riscv_top.core3_dmem_addr[16] ,
+ \u_riscv_top.core3_dmem_addr[15] ,
+ \u_riscv_top.core3_dmem_addr[14] ,
+ \u_riscv_top.core3_dmem_addr[13] ,
+ \u_riscv_top.core3_dmem_addr[12] ,
+ \u_riscv_top.core3_dmem_addr[11] ,
+ \u_riscv_top.core3_dmem_addr[10] ,
+ \u_riscv_top.core3_dmem_addr[9] ,
+ \u_riscv_top.core3_dmem_addr[8] ,
+ \u_riscv_top.core3_dmem_addr[7] ,
+ \u_riscv_top.core3_dmem_addr[6] ,
+ \u_riscv_top.core3_dmem_addr[5] ,
+ \u_riscv_top.core3_dmem_addr[4] ,
+ \u_riscv_top.core3_dmem_addr[3] ,
+ \u_riscv_top.core3_dmem_addr[2] ,
+ \u_riscv_top.core3_dmem_addr[1] ,
+ \u_riscv_top.core3_dmem_addr[0] }),
+ .core3_dmem_rdata({\u_riscv_top.core3_dmem_rdata[31] ,
+ \u_riscv_top.core3_dmem_rdata[30] ,
+ \u_riscv_top.core3_dmem_rdata[29] ,
+ \u_riscv_top.core3_dmem_rdata[28] ,
+ \u_riscv_top.core3_dmem_rdata[27] ,
+ \u_riscv_top.core3_dmem_rdata[26] ,
+ \u_riscv_top.core3_dmem_rdata[25] ,
+ \u_riscv_top.core3_dmem_rdata[24] ,
+ \u_riscv_top.core3_dmem_rdata[23] ,
+ \u_riscv_top.core3_dmem_rdata[22] ,
+ \u_riscv_top.core3_dmem_rdata[21] ,
+ \u_riscv_top.core3_dmem_rdata[20] ,
+ \u_riscv_top.core3_dmem_rdata[19] ,
+ \u_riscv_top.core3_dmem_rdata[18] ,
+ \u_riscv_top.core3_dmem_rdata[17] ,
+ \u_riscv_top.core3_dmem_rdata[16] ,
+ \u_riscv_top.core3_dmem_rdata[15] ,
+ \u_riscv_top.core3_dmem_rdata[14] ,
+ \u_riscv_top.core3_dmem_rdata[13] ,
+ \u_riscv_top.core3_dmem_rdata[12] ,
+ \u_riscv_top.core3_dmem_rdata[11] ,
+ \u_riscv_top.core3_dmem_rdata[10] ,
+ \u_riscv_top.core3_dmem_rdata[9] ,
+ \u_riscv_top.core3_dmem_rdata[8] ,
+ \u_riscv_top.core3_dmem_rdata[7] ,
+ \u_riscv_top.core3_dmem_rdata[6] ,
+ \u_riscv_top.core3_dmem_rdata[5] ,
+ \u_riscv_top.core3_dmem_rdata[4] ,
+ \u_riscv_top.core3_dmem_rdata[3] ,
+ \u_riscv_top.core3_dmem_rdata[2] ,
+ \u_riscv_top.core3_dmem_rdata[1] ,
+ \u_riscv_top.core3_dmem_rdata[0] }),
+ .core3_dmem_resp({\u_riscv_top.core3_dmem_resp[1] ,
+ \u_riscv_top.core3_dmem_resp[0] }),
+ .core3_dmem_wdata({\u_riscv_top.core3_dmem_wdata[31] ,
+ \u_riscv_top.core3_dmem_wdata[30] ,
+ \u_riscv_top.core3_dmem_wdata[29] ,
+ \u_riscv_top.core3_dmem_wdata[28] ,
+ \u_riscv_top.core3_dmem_wdata[27] ,
+ \u_riscv_top.core3_dmem_wdata[26] ,
+ \u_riscv_top.core3_dmem_wdata[25] ,
+ \u_riscv_top.core3_dmem_wdata[24] ,
+ \u_riscv_top.core3_dmem_wdata[23] ,
+ \u_riscv_top.core3_dmem_wdata[22] ,
+ \u_riscv_top.core3_dmem_wdata[21] ,
+ \u_riscv_top.core3_dmem_wdata[20] ,
+ \u_riscv_top.core3_dmem_wdata[19] ,
+ \u_riscv_top.core3_dmem_wdata[18] ,
+ \u_riscv_top.core3_dmem_wdata[17] ,
+ \u_riscv_top.core3_dmem_wdata[16] ,
+ \u_riscv_top.core3_dmem_wdata[15] ,
+ \u_riscv_top.core3_dmem_wdata[14] ,
+ \u_riscv_top.core3_dmem_wdata[13] ,
+ \u_riscv_top.core3_dmem_wdata[12] ,
+ \u_riscv_top.core3_dmem_wdata[11] ,
+ \u_riscv_top.core3_dmem_wdata[10] ,
+ \u_riscv_top.core3_dmem_wdata[9] ,
+ \u_riscv_top.core3_dmem_wdata[8] ,
+ \u_riscv_top.core3_dmem_wdata[7] ,
+ \u_riscv_top.core3_dmem_wdata[6] ,
+ \u_riscv_top.core3_dmem_wdata[5] ,
+ \u_riscv_top.core3_dmem_wdata[4] ,
+ \u_riscv_top.core3_dmem_wdata[3] ,
+ \u_riscv_top.core3_dmem_wdata[2] ,
+ \u_riscv_top.core3_dmem_wdata[1] ,
+ \u_riscv_top.core3_dmem_wdata[0] }),
+ .core3_dmem_width({\u_riscv_top.core3_dmem_width[1] ,
+ \u_riscv_top.core3_dmem_width[0] }),
+ .core3_imem_addr({\u_riscv_top.core3_imem_addr[31] ,
+ \u_riscv_top.core3_imem_addr[30] ,
+ \u_riscv_top.core3_imem_addr[29] ,
+ \u_riscv_top.core3_imem_addr[28] ,
+ \u_riscv_top.core3_imem_addr[27] ,
+ \u_riscv_top.core3_imem_addr[26] ,
+ \u_riscv_top.core3_imem_addr[25] ,
+ \u_riscv_top.core3_imem_addr[24] ,
+ \u_riscv_top.core3_imem_addr[23] ,
+ \u_riscv_top.core3_imem_addr[22] ,
+ \u_riscv_top.core3_imem_addr[21] ,
+ \u_riscv_top.core3_imem_addr[20] ,
+ \u_riscv_top.core3_imem_addr[19] ,
+ \u_riscv_top.core3_imem_addr[18] ,
+ \u_riscv_top.core3_imem_addr[17] ,
+ \u_riscv_top.core3_imem_addr[16] ,
+ \u_riscv_top.core3_imem_addr[15] ,
+ \u_riscv_top.core3_imem_addr[14] ,
+ \u_riscv_top.core3_imem_addr[13] ,
+ \u_riscv_top.core3_imem_addr[12] ,
+ \u_riscv_top.core3_imem_addr[11] ,
+ \u_riscv_top.core3_imem_addr[10] ,
+ \u_riscv_top.core3_imem_addr[9] ,
+ \u_riscv_top.core3_imem_addr[8] ,
+ \u_riscv_top.core3_imem_addr[7] ,
+ \u_riscv_top.core3_imem_addr[6] ,
+ \u_riscv_top.core3_imem_addr[5] ,
+ \u_riscv_top.core3_imem_addr[4] ,
+ \u_riscv_top.core3_imem_addr[3] ,
+ \u_riscv_top.core3_imem_addr[2] ,
+ \u_riscv_top.core3_imem_addr[1] ,
+ \u_riscv_top.core3_imem_addr[0] }),
+ .core3_imem_bl({\u_riscv_top.core3_imem_bl[2] ,
+ \u_riscv_top.core3_imem_bl[1] ,
+ \u_riscv_top.core3_imem_bl[0] }),
+ .core3_imem_rdata({\u_riscv_top.core3_imem_rdata[31] ,
+ \u_riscv_top.core3_imem_rdata[30] ,
+ \u_riscv_top.core3_imem_rdata[29] ,
+ \u_riscv_top.core3_imem_rdata[28] ,
+ \u_riscv_top.core3_imem_rdata[27] ,
+ \u_riscv_top.core3_imem_rdata[26] ,
+ \u_riscv_top.core3_imem_rdata[25] ,
+ \u_riscv_top.core3_imem_rdata[24] ,
+ \u_riscv_top.core3_imem_rdata[23] ,
+ \u_riscv_top.core3_imem_rdata[22] ,
+ \u_riscv_top.core3_imem_rdata[21] ,
+ \u_riscv_top.core3_imem_rdata[20] ,
+ \u_riscv_top.core3_imem_rdata[19] ,
+ \u_riscv_top.core3_imem_rdata[18] ,
+ \u_riscv_top.core3_imem_rdata[17] ,
+ \u_riscv_top.core3_imem_rdata[16] ,
+ \u_riscv_top.core3_imem_rdata[15] ,
+ \u_riscv_top.core3_imem_rdata[14] ,
+ \u_riscv_top.core3_imem_rdata[13] ,
+ \u_riscv_top.core3_imem_rdata[12] ,
+ \u_riscv_top.core3_imem_rdata[11] ,
+ \u_riscv_top.core3_imem_rdata[10] ,
+ \u_riscv_top.core3_imem_rdata[9] ,
+ \u_riscv_top.core3_imem_rdata[8] ,
+ \u_riscv_top.core3_imem_rdata[7] ,
+ \u_riscv_top.core3_imem_rdata[6] ,
+ \u_riscv_top.core3_imem_rdata[5] ,
+ \u_riscv_top.core3_imem_rdata[4] ,
+ \u_riscv_top.core3_imem_rdata[3] ,
+ \u_riscv_top.core3_imem_rdata[2] ,
+ \u_riscv_top.core3_imem_rdata[1] ,
+ \u_riscv_top.core3_imem_rdata[0] }),
+ .core3_imem_resp({\u_riscv_top.core3_imem_resp[1] ,
+ \u_riscv_top.core3_imem_resp[0] }),
+ .core3_irq_lines({\u_riscv_top.core3_irq_lines[15] ,
+ \u_riscv_top.core3_irq_lines[14] ,
+ \u_riscv_top.core3_irq_lines[13] ,
+ \u_riscv_top.core3_irq_lines[12] ,
+ \u_riscv_top.core3_irq_lines[11] ,
+ \u_riscv_top.core3_irq_lines[10] ,
+ \u_riscv_top.core3_irq_lines[9] ,
+ \u_riscv_top.core3_irq_lines[8] ,
+ \u_riscv_top.core3_irq_lines[7] ,
+ \u_riscv_top.core3_irq_lines[6] ,
+ \u_riscv_top.core3_irq_lines[5] ,
+ \u_riscv_top.core3_irq_lines[4] ,
+ \u_riscv_top.core3_irq_lines[3] ,
+ \u_riscv_top.core3_irq_lines[2] ,
+ \u_riscv_top.core3_irq_lines[1] ,
+ \u_riscv_top.core3_irq_lines[0] }),
+ .core3_timer_val({\u_riscv_top.core3_timer_val[63] ,
+ \u_riscv_top.core3_timer_val[62] ,
+ \u_riscv_top.core3_timer_val[61] ,
+ \u_riscv_top.core3_timer_val[60] ,
+ \u_riscv_top.core3_timer_val[59] ,
+ \u_riscv_top.core3_timer_val[58] ,
+ \u_riscv_top.core3_timer_val[57] ,
+ \u_riscv_top.core3_timer_val[56] ,
+ \u_riscv_top.core3_timer_val[55] ,
+ \u_riscv_top.core3_timer_val[54] ,
+ \u_riscv_top.core3_timer_val[53] ,
+ \u_riscv_top.core3_timer_val[52] ,
+ \u_riscv_top.core3_timer_val[51] ,
+ \u_riscv_top.core3_timer_val[50] ,
+ \u_riscv_top.core3_timer_val[49] ,
+ \u_riscv_top.core3_timer_val[48] ,
+ \u_riscv_top.core3_timer_val[47] ,
+ \u_riscv_top.core3_timer_val[46] ,
+ \u_riscv_top.core3_timer_val[45] ,
+ \u_riscv_top.core3_timer_val[44] ,
+ \u_riscv_top.core3_timer_val[43] ,
+ \u_riscv_top.core3_timer_val[42] ,
+ \u_riscv_top.core3_timer_val[41] ,
+ \u_riscv_top.core3_timer_val[40] ,
+ \u_riscv_top.core3_timer_val[39] ,
+ \u_riscv_top.core3_timer_val[38] ,
+ \u_riscv_top.core3_timer_val[37] ,
+ \u_riscv_top.core3_timer_val[36] ,
+ \u_riscv_top.core3_timer_val[35] ,
+ \u_riscv_top.core3_timer_val[34] ,
+ \u_riscv_top.core3_timer_val[33] ,
+ \u_riscv_top.core3_timer_val[32] ,
+ \u_riscv_top.core3_timer_val[31] ,
+ \u_riscv_top.core3_timer_val[30] ,
+ \u_riscv_top.core3_timer_val[29] ,
+ \u_riscv_top.core3_timer_val[28] ,
+ \u_riscv_top.core3_timer_val[27] ,
+ \u_riscv_top.core3_timer_val[26] ,
+ \u_riscv_top.core3_timer_val[25] ,
+ \u_riscv_top.core3_timer_val[24] ,
+ \u_riscv_top.core3_timer_val[23] ,
+ \u_riscv_top.core3_timer_val[22] ,
+ \u_riscv_top.core3_timer_val[21] ,
+ \u_riscv_top.core3_timer_val[20] ,
+ \u_riscv_top.core3_timer_val[19] ,
+ \u_riscv_top.core3_timer_val[18] ,
+ \u_riscv_top.core3_timer_val[17] ,
+ \u_riscv_top.core3_timer_val[16] ,
+ \u_riscv_top.core3_timer_val[15] ,
+ \u_riscv_top.core3_timer_val[14] ,
+ \u_riscv_top.core3_timer_val[13] ,
+ \u_riscv_top.core3_timer_val[12] ,
+ \u_riscv_top.core3_timer_val[11] ,
+ \u_riscv_top.core3_timer_val[10] ,
+ \u_riscv_top.core3_timer_val[9] ,
+ \u_riscv_top.core3_timer_val[8] ,
+ \u_riscv_top.core3_timer_val[7] ,
+ \u_riscv_top.core3_timer_val[6] ,
+ \u_riscv_top.core3_timer_val[5] ,
+ \u_riscv_top.core3_timer_val[4] ,
+ \u_riscv_top.core3_timer_val[3] ,
+ \u_riscv_top.core3_timer_val[2] ,
+ \u_riscv_top.core3_timer_val[1] ,
+ \u_riscv_top.core3_timer_val[0] }),
+ .core3_uid({\u_riscv_top.core3_uid[1] ,
+ \u_riscv_top.core3_uid[0] }),
+ .core_dcache_addr({\u_riscv_top.core_dcache_addr[31] ,
+ \u_riscv_top.core_dcache_addr[30] ,
+ \u_riscv_top.core_dcache_addr[29] ,
+ \u_riscv_top.core_dcache_addr[28] ,
+ \u_riscv_top.core_dcache_addr[27] ,
+ \u_riscv_top.core_dcache_addr[26] ,
+ \u_riscv_top.core_dcache_addr[25] ,
+ \u_riscv_top.core_dcache_addr[24] ,
+ \u_riscv_top.core_dcache_addr[23] ,
+ \u_riscv_top.core_dcache_addr[22] ,
+ \u_riscv_top.core_dcache_addr[21] ,
+ \u_riscv_top.core_dcache_addr[20] ,
+ \u_riscv_top.core_dcache_addr[19] ,
+ \u_riscv_top.core_dcache_addr[18] ,
+ \u_riscv_top.core_dcache_addr[17] ,
+ \u_riscv_top.core_dcache_addr[16] ,
+ \u_riscv_top.core_dcache_addr[15] ,
+ \u_riscv_top.core_dcache_addr[14] ,
+ \u_riscv_top.core_dcache_addr[13] ,
+ \u_riscv_top.core_dcache_addr[12] ,
+ \u_riscv_top.core_dcache_addr[11] ,
+ \u_riscv_top.core_dcache_addr[10] ,
+ \u_riscv_top.core_dcache_addr[9] ,
+ \u_riscv_top.core_dcache_addr[8] ,
+ \u_riscv_top.core_dcache_addr[7] ,
+ \u_riscv_top.core_dcache_addr[6] ,
+ \u_riscv_top.core_dcache_addr[5] ,
+ \u_riscv_top.core_dcache_addr[4] ,
+ \u_riscv_top.core_dcache_addr[3] ,
+ \u_riscv_top.core_dcache_addr[2] ,
+ \u_riscv_top.core_dcache_addr[1] ,
+ \u_riscv_top.core_dcache_addr[0] }),
+ .core_dcache_rdata({\u_riscv_top.core_dcache_rdata[31] ,
+ \u_riscv_top.core_dcache_rdata[30] ,
+ \u_riscv_top.core_dcache_rdata[29] ,
+ \u_riscv_top.core_dcache_rdata[28] ,
+ \u_riscv_top.core_dcache_rdata[27] ,
+ \u_riscv_top.core_dcache_rdata[26] ,
+ \u_riscv_top.core_dcache_rdata[25] ,
+ \u_riscv_top.core_dcache_rdata[24] ,
+ \u_riscv_top.core_dcache_rdata[23] ,
+ \u_riscv_top.core_dcache_rdata[22] ,
+ \u_riscv_top.core_dcache_rdata[21] ,
+ \u_riscv_top.core_dcache_rdata[20] ,
+ \u_riscv_top.core_dcache_rdata[19] ,
+ \u_riscv_top.core_dcache_rdata[18] ,
+ \u_riscv_top.core_dcache_rdata[17] ,
+ \u_riscv_top.core_dcache_rdata[16] ,
+ \u_riscv_top.core_dcache_rdata[15] ,
+ \u_riscv_top.core_dcache_rdata[14] ,
+ \u_riscv_top.core_dcache_rdata[13] ,
+ \u_riscv_top.core_dcache_rdata[12] ,
+ \u_riscv_top.core_dcache_rdata[11] ,
+ \u_riscv_top.core_dcache_rdata[10] ,
+ \u_riscv_top.core_dcache_rdata[9] ,
+ \u_riscv_top.core_dcache_rdata[8] ,
+ \u_riscv_top.core_dcache_rdata[7] ,
+ \u_riscv_top.core_dcache_rdata[6] ,
+ \u_riscv_top.core_dcache_rdata[5] ,
+ \u_riscv_top.core_dcache_rdata[4] ,
+ \u_riscv_top.core_dcache_rdata[3] ,
+ \u_riscv_top.core_dcache_rdata[2] ,
+ \u_riscv_top.core_dcache_rdata[1] ,
+ \u_riscv_top.core_dcache_rdata[0] }),
+ .core_dcache_resp({\u_riscv_top.core_dcache_resp[1] ,
+ \u_riscv_top.core_dcache_resp[0] }),
+ .core_dcache_wdata({\u_riscv_top.core_dcache_wdata[31] ,
+ \u_riscv_top.core_dcache_wdata[30] ,
+ \u_riscv_top.core_dcache_wdata[29] ,
+ \u_riscv_top.core_dcache_wdata[28] ,
+ \u_riscv_top.core_dcache_wdata[27] ,
+ \u_riscv_top.core_dcache_wdata[26] ,
+ \u_riscv_top.core_dcache_wdata[25] ,
+ \u_riscv_top.core_dcache_wdata[24] ,
+ \u_riscv_top.core_dcache_wdata[23] ,
+ \u_riscv_top.core_dcache_wdata[22] ,
+ \u_riscv_top.core_dcache_wdata[21] ,
+ \u_riscv_top.core_dcache_wdata[20] ,
+ \u_riscv_top.core_dcache_wdata[19] ,
+ \u_riscv_top.core_dcache_wdata[18] ,
+ \u_riscv_top.core_dcache_wdata[17] ,
+ \u_riscv_top.core_dcache_wdata[16] ,
+ \u_riscv_top.core_dcache_wdata[15] ,
+ \u_riscv_top.core_dcache_wdata[14] ,
+ \u_riscv_top.core_dcache_wdata[13] ,
+ \u_riscv_top.core_dcache_wdata[12] ,
+ \u_riscv_top.core_dcache_wdata[11] ,
+ \u_riscv_top.core_dcache_wdata[10] ,
+ \u_riscv_top.core_dcache_wdata[9] ,
+ \u_riscv_top.core_dcache_wdata[8] ,
+ \u_riscv_top.core_dcache_wdata[7] ,
+ \u_riscv_top.core_dcache_wdata[6] ,
+ \u_riscv_top.core_dcache_wdata[5] ,
+ \u_riscv_top.core_dcache_wdata[4] ,
+ \u_riscv_top.core_dcache_wdata[3] ,
+ \u_riscv_top.core_dcache_wdata[2] ,
+ \u_riscv_top.core_dcache_wdata[1] ,
+ \u_riscv_top.core_dcache_wdata[0] }),
+ .core_dcache_width({\u_riscv_top.core_dcache_width[1] ,
+ \u_riscv_top.core_dcache_width[0] }),
+ .core_debug_sel({\cfg_riscv_ctrl[9] ,
+ \cfg_riscv_ctrl[8] }),
+ .core_dmem_addr({\u_riscv_top.core_dmem_addr[31] ,
+ \u_riscv_top.core_dmem_addr[30] ,
+ \u_riscv_top.core_dmem_addr[29] ,
+ \u_riscv_top.core_dmem_addr[28] ,
+ \u_riscv_top.core_dmem_addr[27] ,
+ \u_riscv_top.core_dmem_addr[26] ,
+ \u_riscv_top.core_dmem_addr[25] ,
+ \u_riscv_top.core_dmem_addr[24] ,
+ \u_riscv_top.core_dmem_addr[23] ,
+ \u_riscv_top.core_dmem_addr[22] ,
+ \u_riscv_top.core_dmem_addr[21] ,
+ \u_riscv_top.core_dmem_addr[20] ,
+ \u_riscv_top.core_dmem_addr[19] ,
+ \u_riscv_top.core_dmem_addr[18] ,
+ \u_riscv_top.core_dmem_addr[17] ,
+ \u_riscv_top.core_dmem_addr[16] ,
+ \u_riscv_top.core_dmem_addr[15] ,
+ \u_riscv_top.core_dmem_addr[14] ,
+ \u_riscv_top.core_dmem_addr[13] ,
+ \u_riscv_top.core_dmem_addr[12] ,
+ \u_riscv_top.core_dmem_addr[11] ,
+ \u_riscv_top.core_dmem_addr[10] ,
+ \u_riscv_top.core_dmem_addr[9] ,
+ \u_riscv_top.core_dmem_addr[8] ,
+ \u_riscv_top.core_dmem_addr[7] ,
+ \u_riscv_top.core_dmem_addr[6] ,
+ \u_riscv_top.core_dmem_addr[5] ,
+ \u_riscv_top.core_dmem_addr[4] ,
+ \u_riscv_top.core_dmem_addr[3] ,
+ \u_riscv_top.core_dmem_addr[2] ,
+ \u_riscv_top.core_dmem_addr[1] ,
+ \u_riscv_top.core_dmem_addr[0] }),
+ .core_dmem_rdata({\u_riscv_top.core_dmem_rdata[31] ,
+ \u_riscv_top.core_dmem_rdata[30] ,
+ \u_riscv_top.core_dmem_rdata[29] ,
+ \u_riscv_top.core_dmem_rdata[28] ,
+ \u_riscv_top.core_dmem_rdata[27] ,
+ \u_riscv_top.core_dmem_rdata[26] ,
+ \u_riscv_top.core_dmem_rdata[25] ,
+ \u_riscv_top.core_dmem_rdata[24] ,
+ \u_riscv_top.core_dmem_rdata[23] ,
+ \u_riscv_top.core_dmem_rdata[22] ,
+ \u_riscv_top.core_dmem_rdata[21] ,
+ \u_riscv_top.core_dmem_rdata[20] ,
+ \u_riscv_top.core_dmem_rdata[19] ,
+ \u_riscv_top.core_dmem_rdata[18] ,
+ \u_riscv_top.core_dmem_rdata[17] ,
+ \u_riscv_top.core_dmem_rdata[16] ,
+ \u_riscv_top.core_dmem_rdata[15] ,
+ \u_riscv_top.core_dmem_rdata[14] ,
+ \u_riscv_top.core_dmem_rdata[13] ,
+ \u_riscv_top.core_dmem_rdata[12] ,
+ \u_riscv_top.core_dmem_rdata[11] ,
+ \u_riscv_top.core_dmem_rdata[10] ,
+ \u_riscv_top.core_dmem_rdata[9] ,
+ \u_riscv_top.core_dmem_rdata[8] ,
+ \u_riscv_top.core_dmem_rdata[7] ,
+ \u_riscv_top.core_dmem_rdata[6] ,
+ \u_riscv_top.core_dmem_rdata[5] ,
+ \u_riscv_top.core_dmem_rdata[4] ,
+ \u_riscv_top.core_dmem_rdata[3] ,
+ \u_riscv_top.core_dmem_rdata[2] ,
+ \u_riscv_top.core_dmem_rdata[1] ,
+ \u_riscv_top.core_dmem_rdata[0] }),
+ .core_dmem_resp({\u_riscv_top.core_dmem_resp[1] ,
+ \u_riscv_top.core_dmem_resp[0] }),
+ .core_dmem_wdata({\u_riscv_top.core_dmem_wdata[31] ,
+ \u_riscv_top.core_dmem_wdata[30] ,
+ \u_riscv_top.core_dmem_wdata[29] ,
+ \u_riscv_top.core_dmem_wdata[28] ,
+ \u_riscv_top.core_dmem_wdata[27] ,
+ \u_riscv_top.core_dmem_wdata[26] ,
+ \u_riscv_top.core_dmem_wdata[25] ,
+ \u_riscv_top.core_dmem_wdata[24] ,
+ \u_riscv_top.core_dmem_wdata[23] ,
+ \u_riscv_top.core_dmem_wdata[22] ,
+ \u_riscv_top.core_dmem_wdata[21] ,
+ \u_riscv_top.core_dmem_wdata[20] ,
+ \u_riscv_top.core_dmem_wdata[19] ,
+ \u_riscv_top.core_dmem_wdata[18] ,
+ \u_riscv_top.core_dmem_wdata[17] ,
+ \u_riscv_top.core_dmem_wdata[16] ,
+ \u_riscv_top.core_dmem_wdata[15] ,
+ \u_riscv_top.core_dmem_wdata[14] ,
+ \u_riscv_top.core_dmem_wdata[13] ,
+ \u_riscv_top.core_dmem_wdata[12] ,
+ \u_riscv_top.core_dmem_wdata[11] ,
+ \u_riscv_top.core_dmem_wdata[10] ,
+ \u_riscv_top.core_dmem_wdata[9] ,
+ \u_riscv_top.core_dmem_wdata[8] ,
+ \u_riscv_top.core_dmem_wdata[7] ,
+ \u_riscv_top.core_dmem_wdata[6] ,
+ \u_riscv_top.core_dmem_wdata[5] ,
+ \u_riscv_top.core_dmem_wdata[4] ,
+ \u_riscv_top.core_dmem_wdata[3] ,
+ \u_riscv_top.core_dmem_wdata[2] ,
+ \u_riscv_top.core_dmem_wdata[1] ,
+ \u_riscv_top.core_dmem_wdata[0] }),
+ .core_dmem_width({\u_riscv_top.core_dmem_width[1] ,
+ \u_riscv_top.core_dmem_width[0] }),
+ .core_icache_addr({\u_riscv_top.core_icache_addr[31] ,
+ \u_riscv_top.core_icache_addr[30] ,
+ \u_riscv_top.core_icache_addr[29] ,
+ \u_riscv_top.core_icache_addr[28] ,
+ \u_riscv_top.core_icache_addr[27] ,
+ \u_riscv_top.core_icache_addr[26] ,
+ \u_riscv_top.core_icache_addr[25] ,
+ \u_riscv_top.core_icache_addr[24] ,
+ \u_riscv_top.core_icache_addr[23] ,
+ \u_riscv_top.core_icache_addr[22] ,
+ \u_riscv_top.core_icache_addr[21] ,
+ \u_riscv_top.core_icache_addr[20] ,
+ \u_riscv_top.core_icache_addr[19] ,
+ \u_riscv_top.core_icache_addr[18] ,
+ \u_riscv_top.core_icache_addr[17] ,
+ \u_riscv_top.core_icache_addr[16] ,
+ \u_riscv_top.core_icache_addr[15] ,
+ \u_riscv_top.core_icache_addr[14] ,
+ \u_riscv_top.core_icache_addr[13] ,
+ \u_riscv_top.core_icache_addr[12] ,
+ \u_riscv_top.core_icache_addr[11] ,
+ \u_riscv_top.core_icache_addr[10] ,
+ \u_riscv_top.core_icache_addr[9] ,
+ \u_riscv_top.core_icache_addr[8] ,
+ \u_riscv_top.core_icache_addr[7] ,
+ \u_riscv_top.core_icache_addr[6] ,
+ \u_riscv_top.core_icache_addr[5] ,
+ \u_riscv_top.core_icache_addr[4] ,
+ \u_riscv_top.core_icache_addr[3] ,
+ \u_riscv_top.core_icache_addr[2] ,
+ \u_riscv_top.core_icache_addr[1] ,
+ \u_riscv_top.core_icache_addr[0] }),
+ .core_icache_bl({\u_riscv_top.core_icache_bl[2] ,
+ \u_riscv_top.core_icache_bl[1] ,
+ \u_riscv_top.core_icache_bl[0] }),
+ .core_icache_rdata({\u_riscv_top.core_icache_rdata[31] ,
+ \u_riscv_top.core_icache_rdata[30] ,
+ \u_riscv_top.core_icache_rdata[29] ,
+ \u_riscv_top.core_icache_rdata[28] ,
+ \u_riscv_top.core_icache_rdata[27] ,
+ \u_riscv_top.core_icache_rdata[26] ,
+ \u_riscv_top.core_icache_rdata[25] ,
+ \u_riscv_top.core_icache_rdata[24] ,
+ \u_riscv_top.core_icache_rdata[23] ,
+ \u_riscv_top.core_icache_rdata[22] ,
+ \u_riscv_top.core_icache_rdata[21] ,
+ \u_riscv_top.core_icache_rdata[20] ,
+ \u_riscv_top.core_icache_rdata[19] ,
+ \u_riscv_top.core_icache_rdata[18] ,
+ \u_riscv_top.core_icache_rdata[17] ,
+ \u_riscv_top.core_icache_rdata[16] ,
+ \u_riscv_top.core_icache_rdata[15] ,
+ \u_riscv_top.core_icache_rdata[14] ,
+ \u_riscv_top.core_icache_rdata[13] ,
+ \u_riscv_top.core_icache_rdata[12] ,
+ \u_riscv_top.core_icache_rdata[11] ,
+ \u_riscv_top.core_icache_rdata[10] ,
+ \u_riscv_top.core_icache_rdata[9] ,
+ \u_riscv_top.core_icache_rdata[8] ,
+ \u_riscv_top.core_icache_rdata[7] ,
+ \u_riscv_top.core_icache_rdata[6] ,
+ \u_riscv_top.core_icache_rdata[5] ,
+ \u_riscv_top.core_icache_rdata[4] ,
+ \u_riscv_top.core_icache_rdata[3] ,
+ \u_riscv_top.core_icache_rdata[2] ,
+ \u_riscv_top.core_icache_rdata[1] ,
+ \u_riscv_top.core_icache_rdata[0] }),
+ .core_icache_resp({\u_riscv_top.core_icache_resp[1] ,
+ \u_riscv_top.core_icache_resp[0] }),
+ .core_icache_width({\u_riscv_top.core_icache_width[1] ,
+ \u_riscv_top.core_icache_width[0] }),
+ .core_irq_lines_i({\u_riscv_top.irq_lines[15] ,
+ \u_riscv_top.irq_lines[14] ,
+ \u_riscv_top.irq_lines[13] ,
+ \u_riscv_top.irq_lines[12] ,
+ \u_riscv_top.irq_lines[11] ,
+ \u_riscv_top.irq_lines[10] ,
+ \u_riscv_top.irq_lines[9] ,
+ \u_riscv_top.irq_lines[8] ,
+ \u_riscv_top.irq_lines[7] ,
+ \u_riscv_top.irq_lines[6] ,
+ \u_riscv_top.irq_lines[5] ,
+ \u_riscv_top.irq_lines[4] ,
+ \u_riscv_top.irq_lines[3] ,
+ \u_riscv_top.irq_lines[2] ,
+ \u_riscv_top.irq_lines[1] ,
+ \u_riscv_top.irq_lines[0] }),
+ .riscv_debug({la_data_out[63],
+ la_data_out[62],
+ la_data_out[61],
+ la_data_out[60],
+ la_data_out[59],
+ la_data_out[58],
+ la_data_out[57],
+ la_data_out[56],
+ la_data_out[55],
+ la_data_out[54],
+ la_data_out[53],
+ la_data_out[52],
+ la_data_out[51],
+ la_data_out[50],
+ la_data_out[49],
+ la_data_out[48],
+ la_data_out[47],
+ la_data_out[46],
+ la_data_out[45],
+ la_data_out[44],
+ la_data_out[43],
+ la_data_out[42],
+ la_data_out[41],
+ la_data_out[40],
+ la_data_out[39],
+ la_data_out[38],
+ la_data_out[37],
+ la_data_out[36],
+ la_data_out[35],
+ la_data_out[34],
+ la_data_out[33],
+ la_data_out[32],
+ la_data_out[31],
+ la_data_out[30],
+ la_data_out[29],
+ la_data_out[28],
+ la_data_out[27],
+ la_data_out[26],
+ la_data_out[25],
+ la_data_out[24],
+ la_data_out[23],
+ la_data_out[22],
+ la_data_out[21],
+ la_data_out[20],
+ la_data_out[19],
+ la_data_out[18],
+ la_data_out[17],
+ la_data_out[16],
+ la_data_out[15],
+ la_data_out[14],
+ la_data_out[13],
+ la_data_out[12],
+ la_data_out[11],
+ la_data_out[10],
+ la_data_out[9],
+ la_data_out[8],
+ la_data_out[7],
+ la_data_out[6],
+ la_data_out[5],
+ la_data_out[4],
+ la_data_out[3],
+ la_data_out[2],
+ la_data_out[1],
+ la_data_out[0]}),
+ .sram0_addr0({\u_riscv_top.sram0_addr0[8] ,
+ \u_riscv_top.sram0_addr0[7] ,
+ \u_riscv_top.sram0_addr0[6] ,
+ \u_riscv_top.sram0_addr0[5] ,
+ \u_riscv_top.sram0_addr0[4] ,
+ \u_riscv_top.sram0_addr0[3] ,
+ \u_riscv_top.sram0_addr0[2] ,
+ \u_riscv_top.sram0_addr0[1] ,
+ \u_riscv_top.sram0_addr0[0] }),
+ .sram0_addr1({\u_riscv_top.sram0_addr1[8] ,
+ \u_riscv_top.sram0_addr1[7] ,
+ \u_riscv_top.sram0_addr1[6] ,
+ \u_riscv_top.sram0_addr1[5] ,
+ \u_riscv_top.sram0_addr1[4] ,
+ \u_riscv_top.sram0_addr1[3] ,
+ \u_riscv_top.sram0_addr1[2] ,
+ \u_riscv_top.sram0_addr1[1] ,
+ \u_riscv_top.sram0_addr1[0] }),
+ .sram0_din0({\u_riscv_top.sram0_din0[31] ,
+ \u_riscv_top.sram0_din0[30] ,
+ \u_riscv_top.sram0_din0[29] ,
+ \u_riscv_top.sram0_din0[28] ,
+ \u_riscv_top.sram0_din0[27] ,
+ \u_riscv_top.sram0_din0[26] ,
+ \u_riscv_top.sram0_din0[25] ,
+ \u_riscv_top.sram0_din0[24] ,
+ \u_riscv_top.sram0_din0[23] ,
+ \u_riscv_top.sram0_din0[22] ,
+ \u_riscv_top.sram0_din0[21] ,
+ \u_riscv_top.sram0_din0[20] ,
+ \u_riscv_top.sram0_din0[19] ,
+ \u_riscv_top.sram0_din0[18] ,
+ \u_riscv_top.sram0_din0[17] ,
+ \u_riscv_top.sram0_din0[16] ,
+ \u_riscv_top.sram0_din0[15] ,
+ \u_riscv_top.sram0_din0[14] ,
+ \u_riscv_top.sram0_din0[13] ,
+ \u_riscv_top.sram0_din0[12] ,
+ \u_riscv_top.sram0_din0[11] ,
+ \u_riscv_top.sram0_din0[10] ,
+ \u_riscv_top.sram0_din0[9] ,
+ \u_riscv_top.sram0_din0[8] ,
+ \u_riscv_top.sram0_din0[7] ,
+ \u_riscv_top.sram0_din0[6] ,
+ \u_riscv_top.sram0_din0[5] ,
+ \u_riscv_top.sram0_din0[4] ,
+ \u_riscv_top.sram0_din0[3] ,
+ \u_riscv_top.sram0_din0[2] ,
+ \u_riscv_top.sram0_din0[1] ,
+ \u_riscv_top.sram0_din0[0] }),
+ .sram0_dout0({\u_riscv_top.sram0_dout0[31] ,
+ \u_riscv_top.sram0_dout0[30] ,
+ \u_riscv_top.sram0_dout0[29] ,
+ \u_riscv_top.sram0_dout0[28] ,
+ \u_riscv_top.sram0_dout0[27] ,
+ \u_riscv_top.sram0_dout0[26] ,
+ \u_riscv_top.sram0_dout0[25] ,
+ \u_riscv_top.sram0_dout0[24] ,
+ \u_riscv_top.sram0_dout0[23] ,
+ \u_riscv_top.sram0_dout0[22] ,
+ \u_riscv_top.sram0_dout0[21] ,
+ \u_riscv_top.sram0_dout0[20] ,
+ \u_riscv_top.sram0_dout0[19] ,
+ \u_riscv_top.sram0_dout0[18] ,
+ \u_riscv_top.sram0_dout0[17] ,
+ \u_riscv_top.sram0_dout0[16] ,
+ \u_riscv_top.sram0_dout0[15] ,
+ \u_riscv_top.sram0_dout0[14] ,
+ \u_riscv_top.sram0_dout0[13] ,
+ \u_riscv_top.sram0_dout0[12] ,
+ \u_riscv_top.sram0_dout0[11] ,
+ \u_riscv_top.sram0_dout0[10] ,
+ \u_riscv_top.sram0_dout0[9] ,
+ \u_riscv_top.sram0_dout0[8] ,
+ \u_riscv_top.sram0_dout0[7] ,
+ \u_riscv_top.sram0_dout0[6] ,
+ \u_riscv_top.sram0_dout0[5] ,
+ \u_riscv_top.sram0_dout0[4] ,
+ \u_riscv_top.sram0_dout0[3] ,
+ \u_riscv_top.sram0_dout0[2] ,
+ \u_riscv_top.sram0_dout0[1] ,
+ \u_riscv_top.sram0_dout0[0] }),
+ .sram0_dout1({\u_riscv_top.sram0_dout1[31] ,
+ \u_riscv_top.sram0_dout1[30] ,
+ \u_riscv_top.sram0_dout1[29] ,
+ \u_riscv_top.sram0_dout1[28] ,
+ \u_riscv_top.sram0_dout1[27] ,
+ \u_riscv_top.sram0_dout1[26] ,
+ \u_riscv_top.sram0_dout1[25] ,
+ \u_riscv_top.sram0_dout1[24] ,
+ \u_riscv_top.sram0_dout1[23] ,
+ \u_riscv_top.sram0_dout1[22] ,
+ \u_riscv_top.sram0_dout1[21] ,
+ \u_riscv_top.sram0_dout1[20] ,
+ \u_riscv_top.sram0_dout1[19] ,
+ \u_riscv_top.sram0_dout1[18] ,
+ \u_riscv_top.sram0_dout1[17] ,
+ \u_riscv_top.sram0_dout1[16] ,
+ \u_riscv_top.sram0_dout1[15] ,
+ \u_riscv_top.sram0_dout1[14] ,
+ \u_riscv_top.sram0_dout1[13] ,
+ \u_riscv_top.sram0_dout1[12] ,
+ \u_riscv_top.sram0_dout1[11] ,
+ \u_riscv_top.sram0_dout1[10] ,
+ \u_riscv_top.sram0_dout1[9] ,
+ \u_riscv_top.sram0_dout1[8] ,
+ \u_riscv_top.sram0_dout1[7] ,
+ \u_riscv_top.sram0_dout1[6] ,
+ \u_riscv_top.sram0_dout1[5] ,
+ \u_riscv_top.sram0_dout1[4] ,
+ \u_riscv_top.sram0_dout1[3] ,
+ \u_riscv_top.sram0_dout1[2] ,
+ \u_riscv_top.sram0_dout1[1] ,
+ \u_riscv_top.sram0_dout1[0] }),
+ .sram0_wmask0({\u_riscv_top.sram0_wmask0[3] ,
+ \u_riscv_top.sram0_wmask0[2] ,
+ \u_riscv_top.sram0_wmask0[1] ,
+ \u_riscv_top.sram0_wmask0[0] }));
+ ycr_intf \u_riscv_top.u_intf (.cfg_dcache_force_flush(\u_riscv_top.cfg_dcache_force_flush ),
+ .cfg_dcache_pfet_dis(\cfg_riscv_ctrl[6] ),
+ .cfg_icache_ntag_pfet_dis(\cfg_riscv_ctrl[5] ),
+ .cfg_icache_pfet_dis(\cfg_riscv_ctrl[4] ),
+ .core_clk(\u_riscv_top.core_clk ),
+ .core_dcache_cmd(\u_riscv_top.core_dcache_cmd ),
+ .core_dcache_req(\u_riscv_top.core_dcache_req ),
+ .core_dcache_req_ack(\u_riscv_top.core_dcache_req_ack ),
+ .core_dmem_cmd(\u_riscv_top.core_dmem_cmd ),
+ .core_dmem_req(\u_riscv_top.core_dmem_req ),
+ .core_dmem_req_ack(\u_riscv_top.core_dmem_req_ack ),
+ .core_icache_cmd(\u_riscv_top.core_icache_cmd ),
+ .core_icache_req(\u_riscv_top.core_icache_req ),
+ .core_icache_req_ack(\u_riscv_top.core_icache_req_ack ),
+ .cpu_intf_rst_n(\u_riscv_top.cpu_intf_rst_n ),
+ .dcache_mem_clk0(\u_riscv_top.dcache_mem_clk0 ),
+ .dcache_mem_clk1(\u_riscv_top.dcache_mem_clk1 ),
+ .dcache_mem_csb0(\u_riscv_top.dcache_mem_csb0 ),
+ .dcache_mem_csb1(\u_riscv_top.dcache_mem_csb1 ),
+ .dcache_mem_web0(\u_riscv_top.dcache_mem_web0 ),
+ .icache_mem_clk0(\u_riscv_top.icache_mem_clk0 ),
+ .icache_mem_clk1(\u_riscv_top.icache_mem_clk1 ),
+ .icache_mem_csb0(\u_riscv_top.icache_mem_csb0 ),
+ .icache_mem_csb1(\u_riscv_top.icache_mem_csb1 ),
+ .icache_mem_web0(\u_riscv_top.icache_mem_web0 ),
+ .pwrup_rst_n(\u_riscv_top.pwrup_rst_n ),
+ .vccd1(vccd1),
+ .vssd1(vssd1),
+ .wb_clk(\u_riscv_top.wb_clk ),
+ .wb_dcache_ack_i(\u_riscv_top.wb_dcache_ack_i ),
+ .wb_dcache_bry_o(\u_riscv_top.wb_dcache_bry_o ),
+ .wb_dcache_cyc_o(\u_riscv_top.wb_dcache_cyc_o ),
+ .wb_dcache_err_i(\u_riscv_top.wb_dcache_err_i ),
+ .wb_dcache_lack_i(\u_riscv_top.wb_dcache_lack_i ),
+ .wb_dcache_stb_o(\u_riscv_top.wb_dcache_stb_o ),
+ .wb_dcache_we_o(\u_riscv_top.wb_dcache_we_o ),
+ .wb_icache_ack_i(\u_riscv_top.wb_icache_ack_i ),
+ .wb_icache_bry_o(\u_riscv_top.wb_icache_bry_o ),
+ .wb_icache_cyc_o(\u_riscv_top.wb_icache_cyc_o ),
+ .wb_icache_err_i(\u_riscv_top.wb_icache_err_i ),
+ .wb_icache_lack_i(\u_riscv_top.wb_icache_lack_i ),
+ .wb_icache_stb_o(\u_riscv_top.wb_icache_stb_o ),
+ .wb_icache_we_o(\u_riscv_top.wb_icache_we_o ),
+ .wb_rst_n(\u_riscv_top.pwrup_rst_n ),
+ .wbd_clk_int(\u_riscv_top.wbd_clk_int ),
+ .wbd_clk_riscv(\u_riscv_top.wb_clk ),
+ .wbd_dmem_ack_i(\u_riscv_top.wbd_dmem_ack_i ),
+ .wbd_dmem_err_i(\u_riscv_top.wbd_dmem_err_i ),
+ .wbd_dmem_stb_o(\u_riscv_top.wbd_dmem_stb_o ),
+ .wbd_dmem_we_o(\u_riscv_top.wbd_dmem_we_o ),
+ .cfg_cska_riscv({\u_riscv_top.cfg_cska_riscv[3] ,
+ \u_riscv_top.cfg_cska_riscv[2] ,
+ \u_riscv_top.cfg_cska_riscv[1] ,
+ \u_riscv_top.cfg_cska_riscv[0] }),
+ .cfg_sram_lphase({\cfg_riscv_ctrl[1] ,
+ \cfg_riscv_ctrl[0] }),
+ .core_dcache_addr({\u_riscv_top.core_dcache_addr[31] ,
+ \u_riscv_top.core_dcache_addr[30] ,
+ \u_riscv_top.core_dcache_addr[29] ,
+ \u_riscv_top.core_dcache_addr[28] ,
+ \u_riscv_top.core_dcache_addr[27] ,
+ \u_riscv_top.core_dcache_addr[26] ,
+ \u_riscv_top.core_dcache_addr[25] ,
+ \u_riscv_top.core_dcache_addr[24] ,
+ \u_riscv_top.core_dcache_addr[23] ,
+ \u_riscv_top.core_dcache_addr[22] ,
+ \u_riscv_top.core_dcache_addr[21] ,
+ \u_riscv_top.core_dcache_addr[20] ,
+ \u_riscv_top.core_dcache_addr[19] ,
+ \u_riscv_top.core_dcache_addr[18] ,
+ \u_riscv_top.core_dcache_addr[17] ,
+ \u_riscv_top.core_dcache_addr[16] ,
+ \u_riscv_top.core_dcache_addr[15] ,
+ \u_riscv_top.core_dcache_addr[14] ,
+ \u_riscv_top.core_dcache_addr[13] ,
+ \u_riscv_top.core_dcache_addr[12] ,
+ \u_riscv_top.core_dcache_addr[11] ,
+ \u_riscv_top.core_dcache_addr[10] ,
+ \u_riscv_top.core_dcache_addr[9] ,
+ \u_riscv_top.core_dcache_addr[8] ,
+ \u_riscv_top.core_dcache_addr[7] ,
+ \u_riscv_top.core_dcache_addr[6] ,
+ \u_riscv_top.core_dcache_addr[5] ,
+ \u_riscv_top.core_dcache_addr[4] ,
+ \u_riscv_top.core_dcache_addr[3] ,
+ \u_riscv_top.core_dcache_addr[2] ,
+ \u_riscv_top.core_dcache_addr[1] ,
+ \u_riscv_top.core_dcache_addr[0] }),
+ .core_dcache_rdata({\u_riscv_top.core_dcache_rdata[31] ,
+ \u_riscv_top.core_dcache_rdata[30] ,
+ \u_riscv_top.core_dcache_rdata[29] ,
+ \u_riscv_top.core_dcache_rdata[28] ,
+ \u_riscv_top.core_dcache_rdata[27] ,
+ \u_riscv_top.core_dcache_rdata[26] ,
+ \u_riscv_top.core_dcache_rdata[25] ,
+ \u_riscv_top.core_dcache_rdata[24] ,
+ \u_riscv_top.core_dcache_rdata[23] ,
+ \u_riscv_top.core_dcache_rdata[22] ,
+ \u_riscv_top.core_dcache_rdata[21] ,
+ \u_riscv_top.core_dcache_rdata[20] ,
+ \u_riscv_top.core_dcache_rdata[19] ,
+ \u_riscv_top.core_dcache_rdata[18] ,
+ \u_riscv_top.core_dcache_rdata[17] ,
+ \u_riscv_top.core_dcache_rdata[16] ,
+ \u_riscv_top.core_dcache_rdata[15] ,
+ \u_riscv_top.core_dcache_rdata[14] ,
+ \u_riscv_top.core_dcache_rdata[13] ,
+ \u_riscv_top.core_dcache_rdata[12] ,
+ \u_riscv_top.core_dcache_rdata[11] ,
+ \u_riscv_top.core_dcache_rdata[10] ,
+ \u_riscv_top.core_dcache_rdata[9] ,
+ \u_riscv_top.core_dcache_rdata[8] ,
+ \u_riscv_top.core_dcache_rdata[7] ,
+ \u_riscv_top.core_dcache_rdata[6] ,
+ \u_riscv_top.core_dcache_rdata[5] ,
+ \u_riscv_top.core_dcache_rdata[4] ,
+ \u_riscv_top.core_dcache_rdata[3] ,
+ \u_riscv_top.core_dcache_rdata[2] ,
+ \u_riscv_top.core_dcache_rdata[1] ,
+ \u_riscv_top.core_dcache_rdata[0] }),
+ .core_dcache_resp({\u_riscv_top.core_dcache_resp[1] ,
+ \u_riscv_top.core_dcache_resp[0] }),
+ .core_dcache_wdata({\u_riscv_top.core_dcache_wdata[31] ,
+ \u_riscv_top.core_dcache_wdata[30] ,
+ \u_riscv_top.core_dcache_wdata[29] ,
+ \u_riscv_top.core_dcache_wdata[28] ,
+ \u_riscv_top.core_dcache_wdata[27] ,
+ \u_riscv_top.core_dcache_wdata[26] ,
+ \u_riscv_top.core_dcache_wdata[25] ,
+ \u_riscv_top.core_dcache_wdata[24] ,
+ \u_riscv_top.core_dcache_wdata[23] ,
+ \u_riscv_top.core_dcache_wdata[22] ,
+ \u_riscv_top.core_dcache_wdata[21] ,
+ \u_riscv_top.core_dcache_wdata[20] ,
+ \u_riscv_top.core_dcache_wdata[19] ,
+ \u_riscv_top.core_dcache_wdata[18] ,
+ \u_riscv_top.core_dcache_wdata[17] ,
+ \u_riscv_top.core_dcache_wdata[16] ,
+ \u_riscv_top.core_dcache_wdata[15] ,
+ \u_riscv_top.core_dcache_wdata[14] ,
+ \u_riscv_top.core_dcache_wdata[13] ,
+ \u_riscv_top.core_dcache_wdata[12] ,
+ \u_riscv_top.core_dcache_wdata[11] ,
+ \u_riscv_top.core_dcache_wdata[10] ,
+ \u_riscv_top.core_dcache_wdata[9] ,
+ \u_riscv_top.core_dcache_wdata[8] ,
+ \u_riscv_top.core_dcache_wdata[7] ,
+ \u_riscv_top.core_dcache_wdata[6] ,
+ \u_riscv_top.core_dcache_wdata[5] ,
+ \u_riscv_top.core_dcache_wdata[4] ,
+ \u_riscv_top.core_dcache_wdata[3] ,
+ \u_riscv_top.core_dcache_wdata[2] ,
+ \u_riscv_top.core_dcache_wdata[1] ,
+ \u_riscv_top.core_dcache_wdata[0] }),
+ .core_dcache_width({\u_riscv_top.core_dcache_width[1] ,
+ \u_riscv_top.core_dcache_width[0] }),
+ .core_dmem_addr({\u_riscv_top.core_dmem_addr[31] ,
+ \u_riscv_top.core_dmem_addr[30] ,
+ \u_riscv_top.core_dmem_addr[29] ,
+ \u_riscv_top.core_dmem_addr[28] ,
+ \u_riscv_top.core_dmem_addr[27] ,
+ \u_riscv_top.core_dmem_addr[26] ,
+ \u_riscv_top.core_dmem_addr[25] ,
+ \u_riscv_top.core_dmem_addr[24] ,
+ \u_riscv_top.core_dmem_addr[23] ,
+ \u_riscv_top.core_dmem_addr[22] ,
+ \u_riscv_top.core_dmem_addr[21] ,
+ \u_riscv_top.core_dmem_addr[20] ,
+ \u_riscv_top.core_dmem_addr[19] ,
+ \u_riscv_top.core_dmem_addr[18] ,
+ \u_riscv_top.core_dmem_addr[17] ,
+ \u_riscv_top.core_dmem_addr[16] ,
+ \u_riscv_top.core_dmem_addr[15] ,
+ \u_riscv_top.core_dmem_addr[14] ,
+ \u_riscv_top.core_dmem_addr[13] ,
+ \u_riscv_top.core_dmem_addr[12] ,
+ \u_riscv_top.core_dmem_addr[11] ,
+ \u_riscv_top.core_dmem_addr[10] ,
+ \u_riscv_top.core_dmem_addr[9] ,
+ \u_riscv_top.core_dmem_addr[8] ,
+ \u_riscv_top.core_dmem_addr[7] ,
+ \u_riscv_top.core_dmem_addr[6] ,
+ \u_riscv_top.core_dmem_addr[5] ,
+ \u_riscv_top.core_dmem_addr[4] ,
+ \u_riscv_top.core_dmem_addr[3] ,
+ \u_riscv_top.core_dmem_addr[2] ,
+ \u_riscv_top.core_dmem_addr[1] ,
+ \u_riscv_top.core_dmem_addr[0] }),
+ .core_dmem_rdata({\u_riscv_top.core_dmem_rdata[31] ,
+ \u_riscv_top.core_dmem_rdata[30] ,
+ \u_riscv_top.core_dmem_rdata[29] ,
+ \u_riscv_top.core_dmem_rdata[28] ,
+ \u_riscv_top.core_dmem_rdata[27] ,
+ \u_riscv_top.core_dmem_rdata[26] ,
+ \u_riscv_top.core_dmem_rdata[25] ,
+ \u_riscv_top.core_dmem_rdata[24] ,
+ \u_riscv_top.core_dmem_rdata[23] ,
+ \u_riscv_top.core_dmem_rdata[22] ,
+ \u_riscv_top.core_dmem_rdata[21] ,
+ \u_riscv_top.core_dmem_rdata[20] ,
+ \u_riscv_top.core_dmem_rdata[19] ,
+ \u_riscv_top.core_dmem_rdata[18] ,
+ \u_riscv_top.core_dmem_rdata[17] ,
+ \u_riscv_top.core_dmem_rdata[16] ,
+ \u_riscv_top.core_dmem_rdata[15] ,
+ \u_riscv_top.core_dmem_rdata[14] ,
+ \u_riscv_top.core_dmem_rdata[13] ,
+ \u_riscv_top.core_dmem_rdata[12] ,
+ \u_riscv_top.core_dmem_rdata[11] ,
+ \u_riscv_top.core_dmem_rdata[10] ,
+ \u_riscv_top.core_dmem_rdata[9] ,
+ \u_riscv_top.core_dmem_rdata[8] ,
+ \u_riscv_top.core_dmem_rdata[7] ,
+ \u_riscv_top.core_dmem_rdata[6] ,
+ \u_riscv_top.core_dmem_rdata[5] ,
+ \u_riscv_top.core_dmem_rdata[4] ,
+ \u_riscv_top.core_dmem_rdata[3] ,
+ \u_riscv_top.core_dmem_rdata[2] ,
+ \u_riscv_top.core_dmem_rdata[1] ,
+ \u_riscv_top.core_dmem_rdata[0] }),
+ .core_dmem_resp({\u_riscv_top.core_dmem_resp[1] ,
+ \u_riscv_top.core_dmem_resp[0] }),
+ .core_dmem_wdata({\u_riscv_top.core_dmem_wdata[31] ,
+ \u_riscv_top.core_dmem_wdata[30] ,
+ \u_riscv_top.core_dmem_wdata[29] ,
+ \u_riscv_top.core_dmem_wdata[28] ,
+ \u_riscv_top.core_dmem_wdata[27] ,
+ \u_riscv_top.core_dmem_wdata[26] ,
+ \u_riscv_top.core_dmem_wdata[25] ,
+ \u_riscv_top.core_dmem_wdata[24] ,
+ \u_riscv_top.core_dmem_wdata[23] ,
+ \u_riscv_top.core_dmem_wdata[22] ,
+ \u_riscv_top.core_dmem_wdata[21] ,
+ \u_riscv_top.core_dmem_wdata[20] ,
+ \u_riscv_top.core_dmem_wdata[19] ,
+ \u_riscv_top.core_dmem_wdata[18] ,
+ \u_riscv_top.core_dmem_wdata[17] ,
+ \u_riscv_top.core_dmem_wdata[16] ,
+ \u_riscv_top.core_dmem_wdata[15] ,
+ \u_riscv_top.core_dmem_wdata[14] ,
+ \u_riscv_top.core_dmem_wdata[13] ,
+ \u_riscv_top.core_dmem_wdata[12] ,
+ \u_riscv_top.core_dmem_wdata[11] ,
+ \u_riscv_top.core_dmem_wdata[10] ,
+ \u_riscv_top.core_dmem_wdata[9] ,
+ \u_riscv_top.core_dmem_wdata[8] ,
+ \u_riscv_top.core_dmem_wdata[7] ,
+ \u_riscv_top.core_dmem_wdata[6] ,
+ \u_riscv_top.core_dmem_wdata[5] ,
+ \u_riscv_top.core_dmem_wdata[4] ,
+ \u_riscv_top.core_dmem_wdata[3] ,
+ \u_riscv_top.core_dmem_wdata[2] ,
+ \u_riscv_top.core_dmem_wdata[1] ,
+ \u_riscv_top.core_dmem_wdata[0] }),
+ .core_dmem_width({\u_riscv_top.core_dmem_width[1] ,
+ \u_riscv_top.core_dmem_width[0] }),
+ .core_icache_addr({\u_riscv_top.core_icache_addr[31] ,
+ \u_riscv_top.core_icache_addr[30] ,
+ \u_riscv_top.core_icache_addr[29] ,
+ \u_riscv_top.core_icache_addr[28] ,
+ \u_riscv_top.core_icache_addr[27] ,
+ \u_riscv_top.core_icache_addr[26] ,
+ \u_riscv_top.core_icache_addr[25] ,
+ \u_riscv_top.core_icache_addr[24] ,
+ \u_riscv_top.core_icache_addr[23] ,
+ \u_riscv_top.core_icache_addr[22] ,
+ \u_riscv_top.core_icache_addr[21] ,
+ \u_riscv_top.core_icache_addr[20] ,
+ \u_riscv_top.core_icache_addr[19] ,
+ \u_riscv_top.core_icache_addr[18] ,
+ \u_riscv_top.core_icache_addr[17] ,
+ \u_riscv_top.core_icache_addr[16] ,
+ \u_riscv_top.core_icache_addr[15] ,
+ \u_riscv_top.core_icache_addr[14] ,
+ \u_riscv_top.core_icache_addr[13] ,
+ \u_riscv_top.core_icache_addr[12] ,
+ \u_riscv_top.core_icache_addr[11] ,
+ \u_riscv_top.core_icache_addr[10] ,
+ \u_riscv_top.core_icache_addr[9] ,
+ \u_riscv_top.core_icache_addr[8] ,
+ \u_riscv_top.core_icache_addr[7] ,
+ \u_riscv_top.core_icache_addr[6] ,
+ \u_riscv_top.core_icache_addr[5] ,
+ \u_riscv_top.core_icache_addr[4] ,
+ \u_riscv_top.core_icache_addr[3] ,
+ \u_riscv_top.core_icache_addr[2] ,
+ \u_riscv_top.core_icache_addr[1] ,
+ \u_riscv_top.core_icache_addr[0] }),
+ .core_icache_bl({\u_riscv_top.core_icache_bl[2] ,
+ \u_riscv_top.core_icache_bl[1] ,
+ \u_riscv_top.core_icache_bl[0] }),
+ .core_icache_rdata({\u_riscv_top.core_icache_rdata[31] ,
+ \u_riscv_top.core_icache_rdata[30] ,
+ \u_riscv_top.core_icache_rdata[29] ,
+ \u_riscv_top.core_icache_rdata[28] ,
+ \u_riscv_top.core_icache_rdata[27] ,
+ \u_riscv_top.core_icache_rdata[26] ,
+ \u_riscv_top.core_icache_rdata[25] ,
+ \u_riscv_top.core_icache_rdata[24] ,
+ \u_riscv_top.core_icache_rdata[23] ,
+ \u_riscv_top.core_icache_rdata[22] ,
+ \u_riscv_top.core_icache_rdata[21] ,
+ \u_riscv_top.core_icache_rdata[20] ,
+ \u_riscv_top.core_icache_rdata[19] ,
+ \u_riscv_top.core_icache_rdata[18] ,
+ \u_riscv_top.core_icache_rdata[17] ,
+ \u_riscv_top.core_icache_rdata[16] ,
+ \u_riscv_top.core_icache_rdata[15] ,
+ \u_riscv_top.core_icache_rdata[14] ,
+ \u_riscv_top.core_icache_rdata[13] ,
+ \u_riscv_top.core_icache_rdata[12] ,
+ \u_riscv_top.core_icache_rdata[11] ,
+ \u_riscv_top.core_icache_rdata[10] ,
+ \u_riscv_top.core_icache_rdata[9] ,
+ \u_riscv_top.core_icache_rdata[8] ,
+ \u_riscv_top.core_icache_rdata[7] ,
+ \u_riscv_top.core_icache_rdata[6] ,
+ \u_riscv_top.core_icache_rdata[5] ,
+ \u_riscv_top.core_icache_rdata[4] ,
+ \u_riscv_top.core_icache_rdata[3] ,
+ \u_riscv_top.core_icache_rdata[2] ,
+ \u_riscv_top.core_icache_rdata[1] ,
+ \u_riscv_top.core_icache_rdata[0] }),
+ .core_icache_resp({\u_riscv_top.core_icache_resp[1] ,
+ \u_riscv_top.core_icache_resp[0] }),
+ .core_icache_width({\u_riscv_top.core_icache_width[1] ,
+ \u_riscv_top.core_icache_width[0] }),
+ .dcache_mem_addr0({\u_riscv_top.dcache_mem_addr0[8] ,
+ \u_riscv_top.dcache_mem_addr0[7] ,
+ \u_riscv_top.dcache_mem_addr0[6] ,
+ \u_riscv_top.dcache_mem_addr0[5] ,
+ \u_riscv_top.dcache_mem_addr0[4] ,
+ \u_riscv_top.dcache_mem_addr0[3] ,
+ \u_riscv_top.dcache_mem_addr0[2] ,
+ \u_riscv_top.dcache_mem_addr0[1] ,
+ \u_riscv_top.dcache_mem_addr0[0] }),
+ .dcache_mem_addr1({\u_riscv_top.dcache_mem_addr1[8] ,
+ \u_riscv_top.dcache_mem_addr1[7] ,
+ \u_riscv_top.dcache_mem_addr1[6] ,
+ \u_riscv_top.dcache_mem_addr1[5] ,
+ \u_riscv_top.dcache_mem_addr1[4] ,
+ \u_riscv_top.dcache_mem_addr1[3] ,
+ \u_riscv_top.dcache_mem_addr1[2] ,
+ \u_riscv_top.dcache_mem_addr1[1] ,
+ \u_riscv_top.dcache_mem_addr1[0] }),
+ .dcache_mem_din0({\u_riscv_top.dcache_mem_din0[31] ,
+ \u_riscv_top.dcache_mem_din0[30] ,
+ \u_riscv_top.dcache_mem_din0[29] ,
+ \u_riscv_top.dcache_mem_din0[28] ,
+ \u_riscv_top.dcache_mem_din0[27] ,
+ \u_riscv_top.dcache_mem_din0[26] ,
+ \u_riscv_top.dcache_mem_din0[25] ,
+ \u_riscv_top.dcache_mem_din0[24] ,
+ \u_riscv_top.dcache_mem_din0[23] ,
+ \u_riscv_top.dcache_mem_din0[22] ,
+ \u_riscv_top.dcache_mem_din0[21] ,
+ \u_riscv_top.dcache_mem_din0[20] ,
+ \u_riscv_top.dcache_mem_din0[19] ,
+ \u_riscv_top.dcache_mem_din0[18] ,
+ \u_riscv_top.dcache_mem_din0[17] ,
+ \u_riscv_top.dcache_mem_din0[16] ,
+ \u_riscv_top.dcache_mem_din0[15] ,
+ \u_riscv_top.dcache_mem_din0[14] ,
+ \u_riscv_top.dcache_mem_din0[13] ,
+ \u_riscv_top.dcache_mem_din0[12] ,
+ \u_riscv_top.dcache_mem_din0[11] ,
+ \u_riscv_top.dcache_mem_din0[10] ,
+ \u_riscv_top.dcache_mem_din0[9] ,
+ \u_riscv_top.dcache_mem_din0[8] ,
+ \u_riscv_top.dcache_mem_din0[7] ,
+ \u_riscv_top.dcache_mem_din0[6] ,
+ \u_riscv_top.dcache_mem_din0[5] ,
+ \u_riscv_top.dcache_mem_din0[4] ,
+ \u_riscv_top.dcache_mem_din0[3] ,
+ \u_riscv_top.dcache_mem_din0[2] ,
+ \u_riscv_top.dcache_mem_din0[1] ,
+ \u_riscv_top.dcache_mem_din0[0] }),
+ .dcache_mem_dout0({\u_riscv_top.dcache_mem_dout0[31] ,
+ \u_riscv_top.dcache_mem_dout0[30] ,
+ \u_riscv_top.dcache_mem_dout0[29] ,
+ \u_riscv_top.dcache_mem_dout0[28] ,
+ \u_riscv_top.dcache_mem_dout0[27] ,
+ \u_riscv_top.dcache_mem_dout0[26] ,
+ \u_riscv_top.dcache_mem_dout0[25] ,
+ \u_riscv_top.dcache_mem_dout0[24] ,
+ \u_riscv_top.dcache_mem_dout0[23] ,
+ \u_riscv_top.dcache_mem_dout0[22] ,
+ \u_riscv_top.dcache_mem_dout0[21] ,
+ \u_riscv_top.dcache_mem_dout0[20] ,
+ \u_riscv_top.dcache_mem_dout0[19] ,
+ \u_riscv_top.dcache_mem_dout0[18] ,
+ \u_riscv_top.dcache_mem_dout0[17] ,
+ \u_riscv_top.dcache_mem_dout0[16] ,
+ \u_riscv_top.dcache_mem_dout0[15] ,
+ \u_riscv_top.dcache_mem_dout0[14] ,
+ \u_riscv_top.dcache_mem_dout0[13] ,
+ \u_riscv_top.dcache_mem_dout0[12] ,
+ \u_riscv_top.dcache_mem_dout0[11] ,
+ \u_riscv_top.dcache_mem_dout0[10] ,
+ \u_riscv_top.dcache_mem_dout0[9] ,
+ \u_riscv_top.dcache_mem_dout0[8] ,
+ \u_riscv_top.dcache_mem_dout0[7] ,
+ \u_riscv_top.dcache_mem_dout0[6] ,
+ \u_riscv_top.dcache_mem_dout0[5] ,
+ \u_riscv_top.dcache_mem_dout0[4] ,
+ \u_riscv_top.dcache_mem_dout0[3] ,
+ \u_riscv_top.dcache_mem_dout0[2] ,
+ \u_riscv_top.dcache_mem_dout0[1] ,
+ \u_riscv_top.dcache_mem_dout0[0] }),
+ .dcache_mem_dout1({\u_riscv_top.dcache_mem_dout1[31] ,
+ \u_riscv_top.dcache_mem_dout1[30] ,
+ \u_riscv_top.dcache_mem_dout1[29] ,
+ \u_riscv_top.dcache_mem_dout1[28] ,
+ \u_riscv_top.dcache_mem_dout1[27] ,
+ \u_riscv_top.dcache_mem_dout1[26] ,
+ \u_riscv_top.dcache_mem_dout1[25] ,
+ \u_riscv_top.dcache_mem_dout1[24] ,
+ \u_riscv_top.dcache_mem_dout1[23] ,
+ \u_riscv_top.dcache_mem_dout1[22] ,
+ \u_riscv_top.dcache_mem_dout1[21] ,
+ \u_riscv_top.dcache_mem_dout1[20] ,
+ \u_riscv_top.dcache_mem_dout1[19] ,
+ \u_riscv_top.dcache_mem_dout1[18] ,
+ \u_riscv_top.dcache_mem_dout1[17] ,
+ \u_riscv_top.dcache_mem_dout1[16] ,
+ \u_riscv_top.dcache_mem_dout1[15] ,
+ \u_riscv_top.dcache_mem_dout1[14] ,
+ \u_riscv_top.dcache_mem_dout1[13] ,
+ \u_riscv_top.dcache_mem_dout1[12] ,
+ \u_riscv_top.dcache_mem_dout1[11] ,
+ \u_riscv_top.dcache_mem_dout1[10] ,
+ \u_riscv_top.dcache_mem_dout1[9] ,
+ \u_riscv_top.dcache_mem_dout1[8] ,
+ \u_riscv_top.dcache_mem_dout1[7] ,
+ \u_riscv_top.dcache_mem_dout1[6] ,
+ \u_riscv_top.dcache_mem_dout1[5] ,
+ \u_riscv_top.dcache_mem_dout1[4] ,
+ \u_riscv_top.dcache_mem_dout1[3] ,
+ \u_riscv_top.dcache_mem_dout1[2] ,
+ \u_riscv_top.dcache_mem_dout1[1] ,
+ \u_riscv_top.dcache_mem_dout1[0] }),
+ .dcache_mem_wmask0({\u_riscv_top.dcache_mem_wmask0[3] ,
+ \u_riscv_top.dcache_mem_wmask0[2] ,
+ \u_riscv_top.dcache_mem_wmask0[1] ,
+ \u_riscv_top.dcache_mem_wmask0[0] }),
+ .icache_mem_addr0({\u_riscv_top.icache_mem_addr0[8] ,
+ \u_riscv_top.icache_mem_addr0[7] ,
+ \u_riscv_top.icache_mem_addr0[6] ,
+ \u_riscv_top.icache_mem_addr0[5] ,
+ \u_riscv_top.icache_mem_addr0[4] ,
+ \u_riscv_top.icache_mem_addr0[3] ,
+ \u_riscv_top.icache_mem_addr0[2] ,
+ \u_riscv_top.icache_mem_addr0[1] ,
+ \u_riscv_top.icache_mem_addr0[0] }),
+ .icache_mem_addr1({\u_riscv_top.icache_mem_addr1[8] ,
+ \u_riscv_top.icache_mem_addr1[7] ,
+ \u_riscv_top.icache_mem_addr1[6] ,
+ \u_riscv_top.icache_mem_addr1[5] ,
+ \u_riscv_top.icache_mem_addr1[4] ,
+ \u_riscv_top.icache_mem_addr1[3] ,
+ \u_riscv_top.icache_mem_addr1[2] ,
+ \u_riscv_top.icache_mem_addr1[1] ,
+ \u_riscv_top.icache_mem_addr1[0] }),
+ .icache_mem_din0({\u_riscv_top.icache_mem_din0[31] ,
+ \u_riscv_top.icache_mem_din0[30] ,
+ \u_riscv_top.icache_mem_din0[29] ,
+ \u_riscv_top.icache_mem_din0[28] ,
+ \u_riscv_top.icache_mem_din0[27] ,
+ \u_riscv_top.icache_mem_din0[26] ,
+ \u_riscv_top.icache_mem_din0[25] ,
+ \u_riscv_top.icache_mem_din0[24] ,
+ \u_riscv_top.icache_mem_din0[23] ,
+ \u_riscv_top.icache_mem_din0[22] ,
+ \u_riscv_top.icache_mem_din0[21] ,
+ \u_riscv_top.icache_mem_din0[20] ,
+ \u_riscv_top.icache_mem_din0[19] ,
+ \u_riscv_top.icache_mem_din0[18] ,
+ \u_riscv_top.icache_mem_din0[17] ,
+ \u_riscv_top.icache_mem_din0[16] ,
+ \u_riscv_top.icache_mem_din0[15] ,
+ \u_riscv_top.icache_mem_din0[14] ,
+ \u_riscv_top.icache_mem_din0[13] ,
+ \u_riscv_top.icache_mem_din0[12] ,
+ \u_riscv_top.icache_mem_din0[11] ,
+ \u_riscv_top.icache_mem_din0[10] ,
+ \u_riscv_top.icache_mem_din0[9] ,
+ \u_riscv_top.icache_mem_din0[8] ,
+ \u_riscv_top.icache_mem_din0[7] ,
+ \u_riscv_top.icache_mem_din0[6] ,
+ \u_riscv_top.icache_mem_din0[5] ,
+ \u_riscv_top.icache_mem_din0[4] ,
+ \u_riscv_top.icache_mem_din0[3] ,
+ \u_riscv_top.icache_mem_din0[2] ,
+ \u_riscv_top.icache_mem_din0[1] ,
+ \u_riscv_top.icache_mem_din0[0] }),
+ .icache_mem_dout1({\u_riscv_top.icache_mem_dout1[31] ,
+ \u_riscv_top.icache_mem_dout1[30] ,
+ \u_riscv_top.icache_mem_dout1[29] ,
+ \u_riscv_top.icache_mem_dout1[28] ,
+ \u_riscv_top.icache_mem_dout1[27] ,
+ \u_riscv_top.icache_mem_dout1[26] ,
+ \u_riscv_top.icache_mem_dout1[25] ,
+ \u_riscv_top.icache_mem_dout1[24] ,
+ \u_riscv_top.icache_mem_dout1[23] ,
+ \u_riscv_top.icache_mem_dout1[22] ,
+ \u_riscv_top.icache_mem_dout1[21] ,
+ \u_riscv_top.icache_mem_dout1[20] ,
+ \u_riscv_top.icache_mem_dout1[19] ,
+ \u_riscv_top.icache_mem_dout1[18] ,
+ \u_riscv_top.icache_mem_dout1[17] ,
+ \u_riscv_top.icache_mem_dout1[16] ,
+ \u_riscv_top.icache_mem_dout1[15] ,
+ \u_riscv_top.icache_mem_dout1[14] ,
+ \u_riscv_top.icache_mem_dout1[13] ,
+ \u_riscv_top.icache_mem_dout1[12] ,
+ \u_riscv_top.icache_mem_dout1[11] ,
+ \u_riscv_top.icache_mem_dout1[10] ,
+ \u_riscv_top.icache_mem_dout1[9] ,
+ \u_riscv_top.icache_mem_dout1[8] ,
+ \u_riscv_top.icache_mem_dout1[7] ,
+ \u_riscv_top.icache_mem_dout1[6] ,
+ \u_riscv_top.icache_mem_dout1[5] ,
+ \u_riscv_top.icache_mem_dout1[4] ,
+ \u_riscv_top.icache_mem_dout1[3] ,
+ \u_riscv_top.icache_mem_dout1[2] ,
+ \u_riscv_top.icache_mem_dout1[1] ,
+ \u_riscv_top.icache_mem_dout1[0] }),
+ .icache_mem_wmask0({\u_riscv_top.icache_mem_wmask0[3] ,
+ \u_riscv_top.icache_mem_wmask0[2] ,
+ \u_riscv_top.icache_mem_wmask0[1] ,
+ \u_riscv_top.icache_mem_wmask0[0] }),
+ .wb_dcache_adr_o({\u_riscv_top.wb_dcache_adr_o[31] ,
+ \u_riscv_top.wb_dcache_adr_o[30] ,
+ \u_riscv_top.wb_dcache_adr_o[29] ,
+ \u_riscv_top.wb_dcache_adr_o[28] ,
+ \u_riscv_top.wb_dcache_adr_o[27] ,
+ \u_riscv_top.wb_dcache_adr_o[26] ,
+ \u_riscv_top.wb_dcache_adr_o[25] ,
+ \u_riscv_top.wb_dcache_adr_o[24] ,
+ \u_riscv_top.wb_dcache_adr_o[23] ,
+ \u_riscv_top.wb_dcache_adr_o[22] ,
+ \u_riscv_top.wb_dcache_adr_o[21] ,
+ \u_riscv_top.wb_dcache_adr_o[20] ,
+ \u_riscv_top.wb_dcache_adr_o[19] ,
+ \u_riscv_top.wb_dcache_adr_o[18] ,
+ \u_riscv_top.wb_dcache_adr_o[17] ,
+ \u_riscv_top.wb_dcache_adr_o[16] ,
+ \u_riscv_top.wb_dcache_adr_o[15] ,
+ \u_riscv_top.wb_dcache_adr_o[14] ,
+ \u_riscv_top.wb_dcache_adr_o[13] ,
+ \u_riscv_top.wb_dcache_adr_o[12] ,
+ \u_riscv_top.wb_dcache_adr_o[11] ,
+ \u_riscv_top.wb_dcache_adr_o[10] ,
+ \u_riscv_top.wb_dcache_adr_o[9] ,
+ \u_riscv_top.wb_dcache_adr_o[8] ,
+ \u_riscv_top.wb_dcache_adr_o[7] ,
+ \u_riscv_top.wb_dcache_adr_o[6] ,
+ \u_riscv_top.wb_dcache_adr_o[5] ,
+ \u_riscv_top.wb_dcache_adr_o[4] ,
+ \u_riscv_top.wb_dcache_adr_o[3] ,
+ \u_riscv_top.wb_dcache_adr_o[2] ,
+ \u_riscv_top.wb_dcache_adr_o[1] ,
+ \u_riscv_top.wb_dcache_adr_o[0] }),
+ .wb_dcache_bl_o({\u_riscv_top.wb_dcache_bl_o[9] ,
+ \u_riscv_top.wb_dcache_bl_o[8] ,
+ \u_riscv_top.wb_dcache_bl_o[7] ,
+ \u_riscv_top.wb_dcache_bl_o[6] ,
+ \u_riscv_top.wb_dcache_bl_o[5] ,
+ \u_riscv_top.wb_dcache_bl_o[4] ,
+ \u_riscv_top.wb_dcache_bl_o[3] ,
+ \u_riscv_top.wb_dcache_bl_o[2] ,
+ \u_riscv_top.wb_dcache_bl_o[1] ,
+ \u_riscv_top.wb_dcache_bl_o[0] }),
+ .wb_dcache_dat_i({\u_riscv_top.wb_dcache_dat_i[31] ,
+ \u_riscv_top.wb_dcache_dat_i[30] ,
+ \u_riscv_top.wb_dcache_dat_i[29] ,
+ \u_riscv_top.wb_dcache_dat_i[28] ,
+ \u_riscv_top.wb_dcache_dat_i[27] ,
+ \u_riscv_top.wb_dcache_dat_i[26] ,
+ \u_riscv_top.wb_dcache_dat_i[25] ,
+ \u_riscv_top.wb_dcache_dat_i[24] ,
+ \u_riscv_top.wb_dcache_dat_i[23] ,
+ \u_riscv_top.wb_dcache_dat_i[22] ,
+ \u_riscv_top.wb_dcache_dat_i[21] ,
+ \u_riscv_top.wb_dcache_dat_i[20] ,
+ \u_riscv_top.wb_dcache_dat_i[19] ,
+ \u_riscv_top.wb_dcache_dat_i[18] ,
+ \u_riscv_top.wb_dcache_dat_i[17] ,
+ \u_riscv_top.wb_dcache_dat_i[16] ,
+ \u_riscv_top.wb_dcache_dat_i[15] ,
+ \u_riscv_top.wb_dcache_dat_i[14] ,
+ \u_riscv_top.wb_dcache_dat_i[13] ,
+ \u_riscv_top.wb_dcache_dat_i[12] ,
+ \u_riscv_top.wb_dcache_dat_i[11] ,
+ \u_riscv_top.wb_dcache_dat_i[10] ,
+ \u_riscv_top.wb_dcache_dat_i[9] ,
+ \u_riscv_top.wb_dcache_dat_i[8] ,
+ \u_riscv_top.wb_dcache_dat_i[7] ,
+ \u_riscv_top.wb_dcache_dat_i[6] ,
+ \u_riscv_top.wb_dcache_dat_i[5] ,
+ \u_riscv_top.wb_dcache_dat_i[4] ,
+ \u_riscv_top.wb_dcache_dat_i[3] ,
+ \u_riscv_top.wb_dcache_dat_i[2] ,
+ \u_riscv_top.wb_dcache_dat_i[1] ,
+ \u_riscv_top.wb_dcache_dat_i[0] }),
+ .wb_dcache_dat_o({\u_riscv_top.wb_dcache_dat_o[31] ,
+ \u_riscv_top.wb_dcache_dat_o[30] ,
+ \u_riscv_top.wb_dcache_dat_o[29] ,
+ \u_riscv_top.wb_dcache_dat_o[28] ,
+ \u_riscv_top.wb_dcache_dat_o[27] ,
+ \u_riscv_top.wb_dcache_dat_o[26] ,
+ \u_riscv_top.wb_dcache_dat_o[25] ,
+ \u_riscv_top.wb_dcache_dat_o[24] ,
+ \u_riscv_top.wb_dcache_dat_o[23] ,
+ \u_riscv_top.wb_dcache_dat_o[22] ,
+ \u_riscv_top.wb_dcache_dat_o[21] ,
+ \u_riscv_top.wb_dcache_dat_o[20] ,
+ \u_riscv_top.wb_dcache_dat_o[19] ,
+ \u_riscv_top.wb_dcache_dat_o[18] ,
+ \u_riscv_top.wb_dcache_dat_o[17] ,
+ \u_riscv_top.wb_dcache_dat_o[16] ,
+ \u_riscv_top.wb_dcache_dat_o[15] ,
+ \u_riscv_top.wb_dcache_dat_o[14] ,
+ \u_riscv_top.wb_dcache_dat_o[13] ,
+ \u_riscv_top.wb_dcache_dat_o[12] ,
+ \u_riscv_top.wb_dcache_dat_o[11] ,
+ \u_riscv_top.wb_dcache_dat_o[10] ,
+ \u_riscv_top.wb_dcache_dat_o[9] ,
+ \u_riscv_top.wb_dcache_dat_o[8] ,
+ \u_riscv_top.wb_dcache_dat_o[7] ,
+ \u_riscv_top.wb_dcache_dat_o[6] ,
+ \u_riscv_top.wb_dcache_dat_o[5] ,
+ \u_riscv_top.wb_dcache_dat_o[4] ,
+ \u_riscv_top.wb_dcache_dat_o[3] ,
+ \u_riscv_top.wb_dcache_dat_o[2] ,
+ \u_riscv_top.wb_dcache_dat_o[1] ,
+ \u_riscv_top.wb_dcache_dat_o[0] }),
+ .wb_dcache_sel_o({\u_riscv_top.wb_dcache_sel_o[3] ,
+ \u_riscv_top.wb_dcache_sel_o[2] ,
+ \u_riscv_top.wb_dcache_sel_o[1] ,
+ \u_riscv_top.wb_dcache_sel_o[0] }),
+ .wb_icache_adr_o({\u_riscv_top.wb_icache_adr_o[31] ,
+ \u_riscv_top.wb_icache_adr_o[30] ,
+ \u_riscv_top.wb_icache_adr_o[29] ,
+ \u_riscv_top.wb_icache_adr_o[28] ,
+ \u_riscv_top.wb_icache_adr_o[27] ,
+ \u_riscv_top.wb_icache_adr_o[26] ,
+ \u_riscv_top.wb_icache_adr_o[25] ,
+ \u_riscv_top.wb_icache_adr_o[24] ,
+ \u_riscv_top.wb_icache_adr_o[23] ,
+ \u_riscv_top.wb_icache_adr_o[22] ,
+ \u_riscv_top.wb_icache_adr_o[21] ,
+ \u_riscv_top.wb_icache_adr_o[20] ,
+ \u_riscv_top.wb_icache_adr_o[19] ,
+ \u_riscv_top.wb_icache_adr_o[18] ,
+ \u_riscv_top.wb_icache_adr_o[17] ,
+ \u_riscv_top.wb_icache_adr_o[16] ,
+ \u_riscv_top.wb_icache_adr_o[15] ,
+ \u_riscv_top.wb_icache_adr_o[14] ,
+ \u_riscv_top.wb_icache_adr_o[13] ,
+ \u_riscv_top.wb_icache_adr_o[12] ,
+ \u_riscv_top.wb_icache_adr_o[11] ,
+ \u_riscv_top.wb_icache_adr_o[10] ,
+ \u_riscv_top.wb_icache_adr_o[9] ,
+ \u_riscv_top.wb_icache_adr_o[8] ,
+ \u_riscv_top.wb_icache_adr_o[7] ,
+ \u_riscv_top.wb_icache_adr_o[6] ,
+ \u_riscv_top.wb_icache_adr_o[5] ,
+ \u_riscv_top.wb_icache_adr_o[4] ,
+ \u_riscv_top.wb_icache_adr_o[3] ,
+ \u_riscv_top.wb_icache_adr_o[2] ,
+ \u_riscv_top.wb_icache_adr_o[1] ,
+ \u_riscv_top.wb_icache_adr_o[0] }),
+ .wb_icache_bl_o({\u_riscv_top.wb_icache_bl_o[9] ,
+ \u_riscv_top.wb_icache_bl_o[8] ,
+ \u_riscv_top.wb_icache_bl_o[7] ,
+ \u_riscv_top.wb_icache_bl_o[6] ,
+ \u_riscv_top.wb_icache_bl_o[5] ,
+ \u_riscv_top.wb_icache_bl_o[4] ,
+ \u_riscv_top.wb_icache_bl_o[3] ,
+ \u_riscv_top.wb_icache_bl_o[2] ,
+ \u_riscv_top.wb_icache_bl_o[1] ,
+ \u_riscv_top.wb_icache_bl_o[0] }),
+ .wb_icache_dat_i({\u_riscv_top.wb_icache_dat_i[31] ,
+ \u_riscv_top.wb_icache_dat_i[30] ,
+ \u_riscv_top.wb_icache_dat_i[29] ,
+ \u_riscv_top.wb_icache_dat_i[28] ,
+ \u_riscv_top.wb_icache_dat_i[27] ,
+ \u_riscv_top.wb_icache_dat_i[26] ,
+ \u_riscv_top.wb_icache_dat_i[25] ,
+ \u_riscv_top.wb_icache_dat_i[24] ,
+ \u_riscv_top.wb_icache_dat_i[23] ,
+ \u_riscv_top.wb_icache_dat_i[22] ,
+ \u_riscv_top.wb_icache_dat_i[21] ,
+ \u_riscv_top.wb_icache_dat_i[20] ,
+ \u_riscv_top.wb_icache_dat_i[19] ,
+ \u_riscv_top.wb_icache_dat_i[18] ,
+ \u_riscv_top.wb_icache_dat_i[17] ,
+ \u_riscv_top.wb_icache_dat_i[16] ,
+ \u_riscv_top.wb_icache_dat_i[15] ,
+ \u_riscv_top.wb_icache_dat_i[14] ,
+ \u_riscv_top.wb_icache_dat_i[13] ,
+ \u_riscv_top.wb_icache_dat_i[12] ,
+ \u_riscv_top.wb_icache_dat_i[11] ,
+ \u_riscv_top.wb_icache_dat_i[10] ,
+ \u_riscv_top.wb_icache_dat_i[9] ,
+ \u_riscv_top.wb_icache_dat_i[8] ,
+ \u_riscv_top.wb_icache_dat_i[7] ,
+ \u_riscv_top.wb_icache_dat_i[6] ,
+ \u_riscv_top.wb_icache_dat_i[5] ,
+ \u_riscv_top.wb_icache_dat_i[4] ,
+ \u_riscv_top.wb_icache_dat_i[3] ,
+ \u_riscv_top.wb_icache_dat_i[2] ,
+ \u_riscv_top.wb_icache_dat_i[1] ,
+ \u_riscv_top.wb_icache_dat_i[0] }),
+ .wb_icache_sel_o({\u_riscv_top.wb_icache_sel_o[3] ,
+ \u_riscv_top.wb_icache_sel_o[2] ,
+ \u_riscv_top.wb_icache_sel_o[1] ,
+ \u_riscv_top.wb_icache_sel_o[0] }),
+ .wbd_dmem_adr_o({\u_riscv_top.wbd_dmem_adr_o[31] ,
+ \u_riscv_top.wbd_dmem_adr_o[30] ,
+ \u_riscv_top.wbd_dmem_adr_o[29] ,
+ \u_riscv_top.wbd_dmem_adr_o[28] ,
+ \u_riscv_top.wbd_dmem_adr_o[27] ,
+ \u_riscv_top.wbd_dmem_adr_o[26] ,
+ \u_riscv_top.wbd_dmem_adr_o[25] ,
+ \u_riscv_top.wbd_dmem_adr_o[24] ,
+ \u_riscv_top.wbd_dmem_adr_o[23] ,
+ \u_riscv_top.wbd_dmem_adr_o[22] ,
+ \u_riscv_top.wbd_dmem_adr_o[21] ,
+ \u_riscv_top.wbd_dmem_adr_o[20] ,
+ \u_riscv_top.wbd_dmem_adr_o[19] ,
+ \u_riscv_top.wbd_dmem_adr_o[18] ,
+ \u_riscv_top.wbd_dmem_adr_o[17] ,
+ \u_riscv_top.wbd_dmem_adr_o[16] ,
+ \u_riscv_top.wbd_dmem_adr_o[15] ,
+ \u_riscv_top.wbd_dmem_adr_o[14] ,
+ \u_riscv_top.wbd_dmem_adr_o[13] ,
+ \u_riscv_top.wbd_dmem_adr_o[12] ,
+ \u_riscv_top.wbd_dmem_adr_o[11] ,
+ \u_riscv_top.wbd_dmem_adr_o[10] ,
+ \u_riscv_top.wbd_dmem_adr_o[9] ,
+ \u_riscv_top.wbd_dmem_adr_o[8] ,
+ \u_riscv_top.wbd_dmem_adr_o[7] ,
+ \u_riscv_top.wbd_dmem_adr_o[6] ,
+ \u_riscv_top.wbd_dmem_adr_o[5] ,
+ \u_riscv_top.wbd_dmem_adr_o[4] ,
+ \u_riscv_top.wbd_dmem_adr_o[3] ,
+ \u_riscv_top.wbd_dmem_adr_o[2] ,
+ \u_riscv_top.wbd_dmem_adr_o[1] ,
+ \u_riscv_top.wbd_dmem_adr_o[0] }),
+ .wbd_dmem_dat_i({\u_riscv_top.wbd_dmem_dat_i[31] ,
+ \u_riscv_top.wbd_dmem_dat_i[30] ,
+ \u_riscv_top.wbd_dmem_dat_i[29] ,
+ \u_riscv_top.wbd_dmem_dat_i[28] ,
+ \u_riscv_top.wbd_dmem_dat_i[27] ,
+ \u_riscv_top.wbd_dmem_dat_i[26] ,
+ \u_riscv_top.wbd_dmem_dat_i[25] ,
+ \u_riscv_top.wbd_dmem_dat_i[24] ,
+ \u_riscv_top.wbd_dmem_dat_i[23] ,
+ \u_riscv_top.wbd_dmem_dat_i[22] ,
+ \u_riscv_top.wbd_dmem_dat_i[21] ,
+ \u_riscv_top.wbd_dmem_dat_i[20] ,
+ \u_riscv_top.wbd_dmem_dat_i[19] ,
+ \u_riscv_top.wbd_dmem_dat_i[18] ,
+ \u_riscv_top.wbd_dmem_dat_i[17] ,
+ \u_riscv_top.wbd_dmem_dat_i[16] ,
+ \u_riscv_top.wbd_dmem_dat_i[15] ,
+ \u_riscv_top.wbd_dmem_dat_i[14] ,
+ \u_riscv_top.wbd_dmem_dat_i[13] ,
+ \u_riscv_top.wbd_dmem_dat_i[12] ,
+ \u_riscv_top.wbd_dmem_dat_i[11] ,
+ \u_riscv_top.wbd_dmem_dat_i[10] ,
+ \u_riscv_top.wbd_dmem_dat_i[9] ,
+ \u_riscv_top.wbd_dmem_dat_i[8] ,
+ \u_riscv_top.wbd_dmem_dat_i[7] ,
+ \u_riscv_top.wbd_dmem_dat_i[6] ,
+ \u_riscv_top.wbd_dmem_dat_i[5] ,
+ \u_riscv_top.wbd_dmem_dat_i[4] ,
+ \u_riscv_top.wbd_dmem_dat_i[3] ,
+ \u_riscv_top.wbd_dmem_dat_i[2] ,
+ \u_riscv_top.wbd_dmem_dat_i[1] ,
+ \u_riscv_top.wbd_dmem_dat_i[0] }),
+ .wbd_dmem_dat_o({\u_riscv_top.wbd_dmem_dat_o[31] ,
+ \u_riscv_top.wbd_dmem_dat_o[30] ,
+ \u_riscv_top.wbd_dmem_dat_o[29] ,
+ \u_riscv_top.wbd_dmem_dat_o[28] ,
+ \u_riscv_top.wbd_dmem_dat_o[27] ,
+ \u_riscv_top.wbd_dmem_dat_o[26] ,
+ \u_riscv_top.wbd_dmem_dat_o[25] ,
+ \u_riscv_top.wbd_dmem_dat_o[24] ,
+ \u_riscv_top.wbd_dmem_dat_o[23] ,
+ \u_riscv_top.wbd_dmem_dat_o[22] ,
+ \u_riscv_top.wbd_dmem_dat_o[21] ,
+ \u_riscv_top.wbd_dmem_dat_o[20] ,
+ \u_riscv_top.wbd_dmem_dat_o[19] ,
+ \u_riscv_top.wbd_dmem_dat_o[18] ,
+ \u_riscv_top.wbd_dmem_dat_o[17] ,
+ \u_riscv_top.wbd_dmem_dat_o[16] ,
+ \u_riscv_top.wbd_dmem_dat_o[15] ,
+ \u_riscv_top.wbd_dmem_dat_o[14] ,
+ \u_riscv_top.wbd_dmem_dat_o[13] ,
+ \u_riscv_top.wbd_dmem_dat_o[12] ,
+ \u_riscv_top.wbd_dmem_dat_o[11] ,
+ \u_riscv_top.wbd_dmem_dat_o[10] ,
+ \u_riscv_top.wbd_dmem_dat_o[9] ,
+ \u_riscv_top.wbd_dmem_dat_o[8] ,
+ \u_riscv_top.wbd_dmem_dat_o[7] ,
+ \u_riscv_top.wbd_dmem_dat_o[6] ,
+ \u_riscv_top.wbd_dmem_dat_o[5] ,
+ \u_riscv_top.wbd_dmem_dat_o[4] ,
+ \u_riscv_top.wbd_dmem_dat_o[3] ,
+ \u_riscv_top.wbd_dmem_dat_o[2] ,
+ \u_riscv_top.wbd_dmem_dat_o[1] ,
+ \u_riscv_top.wbd_dmem_dat_o[0] }),
+ .wbd_dmem_sel_o({\u_riscv_top.wbd_dmem_sel_o[3] ,
+ \u_riscv_top.wbd_dmem_sel_o[2] ,
+ \u_riscv_top.wbd_dmem_sel_o[1] ,
+ \u_riscv_top.wbd_dmem_sel_o[0] }));
+ sky130_sram_2kbyte_1rw1r_32x512_8 u_tsram0_2kb (.csb0(\u_riscv_top.sram0_csb0 ),
+ .csb1(\u_riscv_top.sram0_csb1 ),
+ .web0(\u_riscv_top.sram0_web0 ),
+ .clk0(\u_riscv_top.sram0_clk0 ),
+ .clk1(\u_riscv_top.sram0_clk1 ),
+ .vccd1(vccd1),
+ .vssd1(vssd1),
+ .addr0({\u_riscv_top.sram0_addr0[8] ,
+ \u_riscv_top.sram0_addr0[7] ,
+ \u_riscv_top.sram0_addr0[6] ,
+ \u_riscv_top.sram0_addr0[5] ,
+ \u_riscv_top.sram0_addr0[4] ,
+ \u_riscv_top.sram0_addr0[3] ,
+ \u_riscv_top.sram0_addr0[2] ,
+ \u_riscv_top.sram0_addr0[1] ,
+ \u_riscv_top.sram0_addr0[0] }),
+ .addr1({\u_riscv_top.sram0_addr1[8] ,
+ \u_riscv_top.sram0_addr1[7] ,
+ \u_riscv_top.sram0_addr1[6] ,
+ \u_riscv_top.sram0_addr1[5] ,
+ \u_riscv_top.sram0_addr1[4] ,
+ \u_riscv_top.sram0_addr1[3] ,
+ \u_riscv_top.sram0_addr1[2] ,
+ \u_riscv_top.sram0_addr1[1] ,
+ \u_riscv_top.sram0_addr1[0] }),
+ .din0({\u_riscv_top.sram0_din0[31] ,
+ \u_riscv_top.sram0_din0[30] ,
+ \u_riscv_top.sram0_din0[29] ,
+ \u_riscv_top.sram0_din0[28] ,
+ \u_riscv_top.sram0_din0[27] ,
+ \u_riscv_top.sram0_din0[26] ,
+ \u_riscv_top.sram0_din0[25] ,
+ \u_riscv_top.sram0_din0[24] ,
+ \u_riscv_top.sram0_din0[23] ,
+ \u_riscv_top.sram0_din0[22] ,
+ \u_riscv_top.sram0_din0[21] ,
+ \u_riscv_top.sram0_din0[20] ,
+ \u_riscv_top.sram0_din0[19] ,
+ \u_riscv_top.sram0_din0[18] ,
+ \u_riscv_top.sram0_din0[17] ,
+ \u_riscv_top.sram0_din0[16] ,
+ \u_riscv_top.sram0_din0[15] ,
+ \u_riscv_top.sram0_din0[14] ,
+ \u_riscv_top.sram0_din0[13] ,
+ \u_riscv_top.sram0_din0[12] ,
+ \u_riscv_top.sram0_din0[11] ,
+ \u_riscv_top.sram0_din0[10] ,
+ \u_riscv_top.sram0_din0[9] ,
+ \u_riscv_top.sram0_din0[8] ,
+ \u_riscv_top.sram0_din0[7] ,
+ \u_riscv_top.sram0_din0[6] ,
+ \u_riscv_top.sram0_din0[5] ,
+ \u_riscv_top.sram0_din0[4] ,
+ \u_riscv_top.sram0_din0[3] ,
+ \u_riscv_top.sram0_din0[2] ,
+ \u_riscv_top.sram0_din0[1] ,
+ \u_riscv_top.sram0_din0[0] }),
+ .dout0({\u_riscv_top.sram0_dout0[31] ,
+ \u_riscv_top.sram0_dout0[30] ,
+ \u_riscv_top.sram0_dout0[29] ,
+ \u_riscv_top.sram0_dout0[28] ,
+ \u_riscv_top.sram0_dout0[27] ,
+ \u_riscv_top.sram0_dout0[26] ,
+ \u_riscv_top.sram0_dout0[25] ,
+ \u_riscv_top.sram0_dout0[24] ,
+ \u_riscv_top.sram0_dout0[23] ,
+ \u_riscv_top.sram0_dout0[22] ,
+ \u_riscv_top.sram0_dout0[21] ,
+ \u_riscv_top.sram0_dout0[20] ,
+ \u_riscv_top.sram0_dout0[19] ,
+ \u_riscv_top.sram0_dout0[18] ,
+ \u_riscv_top.sram0_dout0[17] ,
+ \u_riscv_top.sram0_dout0[16] ,
+ \u_riscv_top.sram0_dout0[15] ,
+ \u_riscv_top.sram0_dout0[14] ,
+ \u_riscv_top.sram0_dout0[13] ,
+ \u_riscv_top.sram0_dout0[12] ,
+ \u_riscv_top.sram0_dout0[11] ,
+ \u_riscv_top.sram0_dout0[10] ,
+ \u_riscv_top.sram0_dout0[9] ,
+ \u_riscv_top.sram0_dout0[8] ,
+ \u_riscv_top.sram0_dout0[7] ,
+ \u_riscv_top.sram0_dout0[6] ,
+ \u_riscv_top.sram0_dout0[5] ,
+ \u_riscv_top.sram0_dout0[4] ,
+ \u_riscv_top.sram0_dout0[3] ,
+ \u_riscv_top.sram0_dout0[2] ,
+ \u_riscv_top.sram0_dout0[1] ,
+ \u_riscv_top.sram0_dout0[0] }),
+ .dout1({\u_riscv_top.sram0_dout1[31] ,
+ \u_riscv_top.sram0_dout1[30] ,
+ \u_riscv_top.sram0_dout1[29] ,
+ \u_riscv_top.sram0_dout1[28] ,
+ \u_riscv_top.sram0_dout1[27] ,
+ \u_riscv_top.sram0_dout1[26] ,
+ \u_riscv_top.sram0_dout1[25] ,
+ \u_riscv_top.sram0_dout1[24] ,
+ \u_riscv_top.sram0_dout1[23] ,
+ \u_riscv_top.sram0_dout1[22] ,
+ \u_riscv_top.sram0_dout1[21] ,
+ \u_riscv_top.sram0_dout1[20] ,
+ \u_riscv_top.sram0_dout1[19] ,
+ \u_riscv_top.sram0_dout1[18] ,
+ \u_riscv_top.sram0_dout1[17] ,
+ \u_riscv_top.sram0_dout1[16] ,
+ \u_riscv_top.sram0_dout1[15] ,
+ \u_riscv_top.sram0_dout1[14] ,
+ \u_riscv_top.sram0_dout1[13] ,
+ \u_riscv_top.sram0_dout1[12] ,
+ \u_riscv_top.sram0_dout1[11] ,
+ \u_riscv_top.sram0_dout1[10] ,
+ \u_riscv_top.sram0_dout1[9] ,
+ \u_riscv_top.sram0_dout1[8] ,
+ \u_riscv_top.sram0_dout1[7] ,
+ \u_riscv_top.sram0_dout1[6] ,
+ \u_riscv_top.sram0_dout1[5] ,
+ \u_riscv_top.sram0_dout1[4] ,
+ \u_riscv_top.sram0_dout1[3] ,
+ \u_riscv_top.sram0_dout1[2] ,
+ \u_riscv_top.sram0_dout1[1] ,
+ \u_riscv_top.sram0_dout1[0] }),
+ .wmask0({\u_riscv_top.sram0_wmask0[3] ,
+ \u_riscv_top.sram0_wmask0[2] ,
+ \u_riscv_top.sram0_wmask0[1] ,
+ \u_riscv_top.sram0_wmask0[0] }));
+ uart_i2c_usb_spi_top u_uart_i2c_usb_spi (.app_clk(wbd_clk_uart_skew),
+ .i2c_rstn(i2c_rst_n),
+ .i2cm_intr_o(i2cm_intr_o),
+ .reg_ack(wbd_uart_ack_i),
+ .reg_cs(wbd_uart_stb_o),
+ .reg_wr(wbd_uart_we_o),
+ .scl_pad_i(i2cm_clk_i),
+ .scl_pad_o(i2cm_clk_o),
+ .scl_pad_oen_o(i2cm_clk_oen),
+ .sda_pad_i(i2cm_data_i),
+ .sda_pad_o(i2cm_data_o),
+ .sda_padoen_o(i2cm_data_oen),
+ .spi_rstn(sspim_rst_n),
+ .sspim_sck(sspim_sck),
+ .sspim_si(sspim_si),
+ .sspim_so(sspim_so),
+ .usb_clk(usb_clk),
+ .usb_in_dn(usb_dn_i),
+ .usb_in_dp(usb_dp_i),
+ .usb_intr_o(usb_intr_o),
+ .usb_out_dn(usb_dn_o),
+ .usb_out_dp(usb_dp_o),
+ .usb_out_tx_oen(usb_oen),
+ .usb_rstn(usb_rst_n),
+ .vccd1(vccd1),
+ .vssd1(vssd1),
+ .wbd_clk_int(wbd_clk_uart_rp),
+ .wbd_clk_uart(wbd_clk_uart_skew),
+ .cfg_cska_uart({\cfg_cska_uart_rp[3] ,
+ \cfg_cska_uart_rp[2] ,
+ \cfg_cska_uart_rp[1] ,
+ \cfg_cska_uart_rp[0] }),
+ .reg_addr({\wbd_uart_adr_o[8] ,
+ \wbd_uart_adr_o[7] ,
+ \wbd_uart_adr_o[6] ,
+ \wbd_uart_adr_o[5] ,
+ \wbd_uart_adr_o[4] ,
+ \wbd_uart_adr_o[3] ,
+ \wbd_uart_adr_o[2] ,
+ \wbd_uart_adr_o[1] ,
+ \wbd_uart_adr_o[0] }),
+ .reg_be({\wbd_uart_sel_o[3] ,
+ \wbd_uart_sel_o[2] ,
+ \wbd_uart_sel_o[1] ,
+ \wbd_uart_sel_o[0] }),
+ .reg_rdata({\wbd_uart_dat_i[31] ,
+ \wbd_uart_dat_i[30] ,
+ \wbd_uart_dat_i[29] ,
+ \wbd_uart_dat_i[28] ,
+ \wbd_uart_dat_i[27] ,
+ \wbd_uart_dat_i[26] ,
+ \wbd_uart_dat_i[25] ,
+ \wbd_uart_dat_i[24] ,
+ \wbd_uart_dat_i[23] ,
+ \wbd_uart_dat_i[22] ,
+ \wbd_uart_dat_i[21] ,
+ \wbd_uart_dat_i[20] ,
+ \wbd_uart_dat_i[19] ,
+ \wbd_uart_dat_i[18] ,
+ \wbd_uart_dat_i[17] ,
+ \wbd_uart_dat_i[16] ,
+ \wbd_uart_dat_i[15] ,
+ \wbd_uart_dat_i[14] ,
+ \wbd_uart_dat_i[13] ,
+ \wbd_uart_dat_i[12] ,
+ \wbd_uart_dat_i[11] ,
+ \wbd_uart_dat_i[10] ,
+ \wbd_uart_dat_i[9] ,
+ \wbd_uart_dat_i[8] ,
+ \wbd_uart_dat_i[7] ,
+ \wbd_uart_dat_i[6] ,
+ \wbd_uart_dat_i[5] ,
+ \wbd_uart_dat_i[4] ,
+ \wbd_uart_dat_i[3] ,
+ \wbd_uart_dat_i[2] ,
+ \wbd_uart_dat_i[1] ,
+ \wbd_uart_dat_i[0] }),
+ .reg_wdata({\wbd_uart_dat_o[31] ,
+ \wbd_uart_dat_o[30] ,
+ \wbd_uart_dat_o[29] ,
+ \wbd_uart_dat_o[28] ,
+ \wbd_uart_dat_o[27] ,
+ \wbd_uart_dat_o[26] ,
+ \wbd_uart_dat_o[25] ,
+ \wbd_uart_dat_o[24] ,
+ \wbd_uart_dat_o[23] ,
+ \wbd_uart_dat_o[22] ,
+ \wbd_uart_dat_o[21] ,
+ \wbd_uart_dat_o[20] ,
+ \wbd_uart_dat_o[19] ,
+ \wbd_uart_dat_o[18] ,
+ \wbd_uart_dat_o[17] ,
+ \wbd_uart_dat_o[16] ,
+ \wbd_uart_dat_o[15] ,
+ \wbd_uart_dat_o[14] ,
+ \wbd_uart_dat_o[13] ,
+ \wbd_uart_dat_o[12] ,
+ \wbd_uart_dat_o[11] ,
+ \wbd_uart_dat_o[10] ,
+ \wbd_uart_dat_o[9] ,
+ \wbd_uart_dat_o[8] ,
+ \wbd_uart_dat_o[7] ,
+ \wbd_uart_dat_o[6] ,
+ \wbd_uart_dat_o[5] ,
+ \wbd_uart_dat_o[4] ,
+ \wbd_uart_dat_o[3] ,
+ \wbd_uart_dat_o[2] ,
+ \wbd_uart_dat_o[1] ,
+ \wbd_uart_dat_o[0] }),
+ .sspim_ssn({\sspim_ssn[3] ,
+ \sspim_ssn[2] ,
+ \sspim_ssn[1] ,
+ \sspim_ssn[0] }),
+ .uart_rstn({\uart_rst_n[1] ,
+ \uart_rst_n[0] }),
+ .uart_rxd({\uart_rxd[1] ,
+ \uart_rxd[0] }),
+ .uart_txd({\uart_txd[1] ,
+ \uart_txd[0] }));
+ wb_host u_wb_host (.cfg_dco_mode(cfg_dco_mode),
+ .cfg_pll_enb(cfg_pll_enb),
+ .cpu_clk(\u_riscv_top.core_clk ),
+ .dbg_clk_mon(dbg_clk_mon),
+ .pll_ref_clk(pll_ref_clk),
+ .rtc_clk(\u_riscv_top.rtc_clk ),
+ .uartm_rxd(uartm_rxd),
+ .uartm_txd(uartm_txd),
+ .usb_clk(usb_clk),
+ .user_clock1(wb_clk_i),
+ .user_clock2(user_clock2),
+ .vccd1(vccd1),
+ .vssd1(vssd1),
+ .wbd_clk_int(wbd_clk_int),
+ .wbd_clk_wh(wbd_clk_wh),
+ .wbd_int_rst_n(\u_riscv_top.pwrup_rst_n ),
+ .wbd_pll_rst_n(wbd_pll_rst_n),
+ .wbm_ack_o(wbs_ack_o),
+ .wbm_clk_i(wb_clk_i),
+ .wbm_cyc_i(wbs_cyc_i),
+ .wbm_rst_i(wb_rst_i),
+ .wbm_stb_i(wbs_stb_i),
+ .wbm_we_i(wbs_we_i),
+ .wbs_ack_i(wbd_int_ack_o),
+ .wbs_clk_i(wbd_clk_wh),
+ .wbs_clk_out(wbd_clk_int),
+ .wbs_cyc_o(wbd_int_cyc_i),
+ .wbs_err_i(wbd_int_err_o),
+ .wbs_stb_o(wbd_int_stb_i),
+ .wbs_we_o(wbd_int_we_i),
+ .cfg_clk_ctrl1({\cfg_clk_ctrl1[31] ,
+ \cfg_clk_ctrl1[30] ,
+ \cfg_clk_ctrl1[29] ,
+ \cfg_clk_ctrl1[28] ,
+ \cfg_clk_ctrl1[27] ,
+ \cfg_clk_ctrl1[26] ,
+ \cfg_clk_ctrl1[25] ,
+ \cfg_clk_ctrl1[24] ,
+ \cfg_clk_ctrl1[23] ,
+ \cfg_clk_ctrl1[22] ,
+ \cfg_clk_ctrl1[21] ,
+ \cfg_clk_ctrl1[20] ,
+ \cfg_clk_ctrl1[19] ,
+ \cfg_clk_ctrl1[18] ,
+ \cfg_clk_ctrl1[17] ,
+ \cfg_clk_ctrl1[16] ,
+ \cfg_clk_ctrl1[15] ,
+ \cfg_clk_ctrl1[14] ,
+ \cfg_clk_ctrl1[13] ,
+ \cfg_clk_ctrl1[12] ,
+ \cfg_clk_ctrl1[11] ,
+ \cfg_clk_ctrl1[10] ,
+ \cfg_clk_ctrl1[9] ,
+ \cfg_clk_ctrl1[8] ,
+ \cfg_clk_ctrl1[7] ,
+ \cfg_clk_ctrl1[6] ,
+ \cfg_clk_ctrl1[5] ,
+ \cfg_clk_ctrl1[4] ,
+ \cfg_clk_ctrl1[3] ,
+ \cfg_clk_ctrl1[2] ,
+ \cfg_clk_ctrl1[1] ,
+ \cfg_clk_ctrl1[0] }),
+ .cfg_cska_wh({\cfg_clk_ctrl1[7] ,
+ \cfg_clk_ctrl1[6] ,
+ \cfg_clk_ctrl1[5] ,
+ \cfg_clk_ctrl1[4] }),
+ .cfg_dc_trim({\cfg_dc_trim[25] ,
+ \cfg_dc_trim[24] ,
+ \cfg_dc_trim[23] ,
+ \cfg_dc_trim[22] ,
+ \cfg_dc_trim[21] ,
+ \cfg_dc_trim[20] ,
+ \cfg_dc_trim[19] ,
+ \cfg_dc_trim[18] ,
+ \cfg_dc_trim[17] ,
+ \cfg_dc_trim[16] ,
+ \cfg_dc_trim[15] ,
+ \cfg_dc_trim[14] ,
+ \cfg_dc_trim[13] ,
+ \cfg_dc_trim[12] ,
+ \cfg_dc_trim[11] ,
+ \cfg_dc_trim[10] ,
+ \cfg_dc_trim[9] ,
+ \cfg_dc_trim[8] ,
+ \cfg_dc_trim[7] ,
+ \cfg_dc_trim[6] ,
+ \cfg_dc_trim[5] ,
+ \cfg_dc_trim[4] ,
+ \cfg_dc_trim[3] ,
+ \cfg_dc_trim[2] ,
+ \cfg_dc_trim[1] ,
+ \cfg_dc_trim[0] }),
+ .cfg_pll_fed_div({\cfg_pll_fed_div[4] ,
+ \cfg_pll_fed_div[3] ,
+ \cfg_pll_fed_div[2] ,
+ \cfg_pll_fed_div[1] ,
+ \cfg_pll_fed_div[0] }),
+ .la_data_in({la_data_in[17],
+ la_data_in[16],
+ la_data_in[15],
+ la_data_in[14],
+ la_data_in[13],
+ la_data_in[12],
+ la_data_in[11],
+ la_data_in[10],
+ la_data_in[9],
+ la_data_in[8],
+ la_data_in[7],
+ la_data_in[6],
+ la_data_in[5],
+ la_data_in[4],
+ la_data_in[3],
+ la_data_in[2],
+ la_data_in[1],
+ la_data_in[0]}),
+ .pll_clk_out({\pll_clk_out[1] ,
+ \pll_clk_out[0] }),
+ .wbm_adr_i({wbs_adr_i[31],
+ wbs_adr_i[30],
+ wbs_adr_i[29],
+ wbs_adr_i[28],
+ wbs_adr_i[27],
+ wbs_adr_i[26],
+ wbs_adr_i[25],
+ wbs_adr_i[24],
+ wbs_adr_i[23],
+ wbs_adr_i[22],
+ wbs_adr_i[21],
+ wbs_adr_i[20],
+ wbs_adr_i[19],
+ wbs_adr_i[18],
+ wbs_adr_i[17],
+ wbs_adr_i[16],
+ wbs_adr_i[15],
+ wbs_adr_i[14],
+ wbs_adr_i[13],
+ wbs_adr_i[12],
+ wbs_adr_i[11],
+ wbs_adr_i[10],
+ wbs_adr_i[9],
+ wbs_adr_i[8],
+ wbs_adr_i[7],
+ wbs_adr_i[6],
+ wbs_adr_i[5],
+ wbs_adr_i[4],
+ wbs_adr_i[3],
+ wbs_adr_i[2],
+ wbs_adr_i[1],
+ wbs_adr_i[0]}),
+ .wbm_dat_i({wbs_dat_i[31],
+ wbs_dat_i[30],
+ wbs_dat_i[29],
+ wbs_dat_i[28],
+ wbs_dat_i[27],
+ wbs_dat_i[26],
+ wbs_dat_i[25],
+ wbs_dat_i[24],
+ wbs_dat_i[23],
+ wbs_dat_i[22],
+ wbs_dat_i[21],
+ wbs_dat_i[20],
+ wbs_dat_i[19],
+ wbs_dat_i[18],
+ wbs_dat_i[17],
+ wbs_dat_i[16],
+ wbs_dat_i[15],
+ wbs_dat_i[14],
+ wbs_dat_i[13],
+ wbs_dat_i[12],
+ wbs_dat_i[11],
+ wbs_dat_i[10],
+ wbs_dat_i[9],
+ wbs_dat_i[8],
+ wbs_dat_i[7],
+ wbs_dat_i[6],
+ wbs_dat_i[5],
+ wbs_dat_i[4],
+ wbs_dat_i[3],
+ wbs_dat_i[2],
+ wbs_dat_i[1],
+ wbs_dat_i[0]}),
+ .wbm_dat_o({wbs_dat_o[31],
+ wbs_dat_o[30],
+ wbs_dat_o[29],
+ wbs_dat_o[28],
+ wbs_dat_o[27],
+ wbs_dat_o[26],
+ wbs_dat_o[25],
+ wbs_dat_o[24],
+ wbs_dat_o[23],
+ wbs_dat_o[22],
+ wbs_dat_o[21],
+ wbs_dat_o[20],
+ wbs_dat_o[19],
+ wbs_dat_o[18],
+ wbs_dat_o[17],
+ wbs_dat_o[16],
+ wbs_dat_o[15],
+ wbs_dat_o[14],
+ wbs_dat_o[13],
+ wbs_dat_o[12],
+ wbs_dat_o[11],
+ wbs_dat_o[10],
+ wbs_dat_o[9],
+ wbs_dat_o[8],
+ wbs_dat_o[7],
+ wbs_dat_o[6],
+ wbs_dat_o[5],
+ wbs_dat_o[4],
+ wbs_dat_o[3],
+ wbs_dat_o[2],
+ wbs_dat_o[1],
+ wbs_dat_o[0]}),
+ .wbm_sel_i({wbs_sel_i[3],
+ wbs_sel_i[2],
+ wbs_sel_i[1],
+ wbs_sel_i[0]}),
+ .wbs_adr_o({\wbd_int_adr_i[31] ,
+ \wbd_int_adr_i[30] ,
+ \wbd_int_adr_i[29] ,
+ \wbd_int_adr_i[28] ,
+ \wbd_int_adr_i[27] ,
+ \wbd_int_adr_i[26] ,
+ \wbd_int_adr_i[25] ,
+ \wbd_int_adr_i[24] ,
+ \wbd_int_adr_i[23] ,
+ \wbd_int_adr_i[22] ,
+ \wbd_int_adr_i[21] ,
+ \wbd_int_adr_i[20] ,
+ \wbd_int_adr_i[19] ,
+ \wbd_int_adr_i[18] ,
+ \wbd_int_adr_i[17] ,
+ \wbd_int_adr_i[16] ,
+ \wbd_int_adr_i[15] ,
+ \wbd_int_adr_i[14] ,
+ \wbd_int_adr_i[13] ,
+ \wbd_int_adr_i[12] ,
+ \wbd_int_adr_i[11] ,
+ \wbd_int_adr_i[10] ,
+ \wbd_int_adr_i[9] ,
+ \wbd_int_adr_i[8] ,
+ \wbd_int_adr_i[7] ,
+ \wbd_int_adr_i[6] ,
+ \wbd_int_adr_i[5] ,
+ \wbd_int_adr_i[4] ,
+ \wbd_int_adr_i[3] ,
+ \wbd_int_adr_i[2] ,
+ \wbd_int_adr_i[1] ,
+ \wbd_int_adr_i[0] }),
+ .wbs_dat_i({\wbd_int_dat_o[31] ,
+ \wbd_int_dat_o[30] ,
+ \wbd_int_dat_o[29] ,
+ \wbd_int_dat_o[28] ,
+ \wbd_int_dat_o[27] ,
+ \wbd_int_dat_o[26] ,
+ \wbd_int_dat_o[25] ,
+ \wbd_int_dat_o[24] ,
+ \wbd_int_dat_o[23] ,
+ \wbd_int_dat_o[22] ,
+ \wbd_int_dat_o[21] ,
+ \wbd_int_dat_o[20] ,
+ \wbd_int_dat_o[19] ,
+ \wbd_int_dat_o[18] ,
+ \wbd_int_dat_o[17] ,
+ \wbd_int_dat_o[16] ,
+ \wbd_int_dat_o[15] ,
+ \wbd_int_dat_o[14] ,
+ \wbd_int_dat_o[13] ,
+ \wbd_int_dat_o[12] ,
+ \wbd_int_dat_o[11] ,
+ \wbd_int_dat_o[10] ,
+ \wbd_int_dat_o[9] ,
+ \wbd_int_dat_o[8] ,
+ \wbd_int_dat_o[7] ,
+ \wbd_int_dat_o[6] ,
+ \wbd_int_dat_o[5] ,
+ \wbd_int_dat_o[4] ,
+ \wbd_int_dat_o[3] ,
+ \wbd_int_dat_o[2] ,
+ \wbd_int_dat_o[1] ,
+ \wbd_int_dat_o[0] }),
+ .wbs_dat_o({\wbd_int_dat_i[31] ,
+ \wbd_int_dat_i[30] ,
+ \wbd_int_dat_i[29] ,
+ \wbd_int_dat_i[28] ,
+ \wbd_int_dat_i[27] ,
+ \wbd_int_dat_i[26] ,
+ \wbd_int_dat_i[25] ,
+ \wbd_int_dat_i[24] ,
+ \wbd_int_dat_i[23] ,
+ \wbd_int_dat_i[22] ,
+ \wbd_int_dat_i[21] ,
+ \wbd_int_dat_i[20] ,
+ \wbd_int_dat_i[19] ,
+ \wbd_int_dat_i[18] ,
+ \wbd_int_dat_i[17] ,
+ \wbd_int_dat_i[16] ,
+ \wbd_int_dat_i[15] ,
+ \wbd_int_dat_i[14] ,
+ \wbd_int_dat_i[13] ,
+ \wbd_int_dat_i[12] ,
+ \wbd_int_dat_i[11] ,
+ \wbd_int_dat_i[10] ,
+ \wbd_int_dat_i[9] ,
+ \wbd_int_dat_i[8] ,
+ \wbd_int_dat_i[7] ,
+ \wbd_int_dat_i[6] ,
+ \wbd_int_dat_i[5] ,
+ \wbd_int_dat_i[4] ,
+ \wbd_int_dat_i[3] ,
+ \wbd_int_dat_i[2] ,
+ \wbd_int_dat_i[1] ,
+ \wbd_int_dat_i[0] }),
+ .wbs_sel_o({\wbd_int_sel_i[3] ,
+ \wbd_int_sel_i[2] ,
+ \wbd_int_sel_i[1] ,
+ \wbd_int_sel_i[0] }));
+endmodule
diff --git a/mpw_precheck/outputs/user_project_wrapper.magic.drc.mag b/mpw_precheck/outputs/user_project_wrapper.magic.drc.mag
new file mode 100644
index 0000000..36cb481
--- /dev/null
+++ b/mpw_precheck/outputs/user_project_wrapper.magic.drc.mag
@@ -0,0 +1,125150 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1654259434
+<< checkpaint >>
+rect -12658 -11586 596582 715522
+<< metal1 >>
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+timestamp 1646436176
+transform 1 0 30000 0 1 26000
+box 0 0 136620 83308
+use sky130_sram_2kbyte_1rw1r_32x512_8 u_icache_2kb
+timestamp 1646436176
+transform 1 0 190000 0 1 26000
+box 0 0 136620 83308
+use wb_interconnect u_intercon
+timestamp 0
+transform 1 0 370000 0 1 130000
+box 0 0 60000 342768
+use pinmux u_pinmux
+timestamp 0
+transform 1 0 450000 0 1 430000
+box -800 -800 100800 80800
+use digital_pll u_pll
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+transform 1 0 440000 0 1 20000
+box 0 0 15000 15000
+use qspim_top u_qspi_master
+timestamp 0
+transform 1 0 450000 0 1 130000
+box -800 144 90800 110800
+use ycr_core_top u_riscv_top.i_core_top_0
+timestamp 0
+transform 1 0 15000 0 1 280000
+box 13 0 108000 187728
+use ycr_core_top u_riscv_top.i_core_top_1
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+transform -1 0 348000 0 1 280000
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+transform 1 0 15000 0 1 495000
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+use ycr_core_top u_riscv_top.i_core_top_3
+timestamp 0
+transform -1 0 348000 0 1 495000
+box 13 0 108000 187728
+use ycr4_iconnect u_riscv_top.u_connect
+timestamp 0
+transform 1 0 145000 0 1 280000
+box 0 0 76000 377584
+use ycr_intf u_riscv_top.u_intf
+timestamp 0
+transform 1 0 190000 0 1 130000
+box 0 0 162000 128000
+use sky130_sram_2kbyte_1rw1r_32x512_8 u_tsram0_2kb
+timestamp 1646436176
+transform 1 0 30000 0 1 150000
+box 0 0 136620 83308
+use uart_i2c_usb_spi_top u_uart_i2c_usb_spi
+timestamp 0
+transform 1 0 450000 0 1 270000
+box -800 -800 102800 142576
+use wb_host u_wb_host
+timestamp 0
+transform 1 0 350000 0 1 20000
+box -800 -800 70800 85800
+<< labels >>
+rlabel metal3 s 583520 285276 584960 285516 4 analog_io[0]
+port 1 nsew
+rlabel metal2 s 446098 703520 446210 704960 4 analog_io[10]
+port 2 nsew
+rlabel metal2 s 381146 703520 381258 704960 4 analog_io[11]
+port 3 nsew
+rlabel metal2 s 316286 703520 316398 704960 4 analog_io[12]
+port 4 nsew
+rlabel metal2 s 251426 703520 251538 704960 4 analog_io[13]
+port 5 nsew
+rlabel metal2 s 186474 703520 186586 704960 4 analog_io[14]
+port 6 nsew
+rlabel metal2 s 121614 703520 121726 704960 4 analog_io[15]
+port 7 nsew
+rlabel metal2 s 56754 703520 56866 704960 4 analog_io[16]
+port 8 nsew
+rlabel metal3 s -960 697220 480 697460 4 analog_io[17]
+port 9 nsew
+rlabel metal3 s -960 644996 480 645236 4 analog_io[18]
+port 10 nsew
+rlabel metal3 s -960 592908 480 593148 4 analog_io[19]
+port 11 nsew
+rlabel metal3 s 583520 338452 584960 338692 4 analog_io[1]
+port 12 nsew
+rlabel metal3 s -960 540684 480 540924 4 analog_io[20]
+port 13 nsew
+rlabel metal3 s -960 488596 480 488836 4 analog_io[21]
+port 14 nsew
+rlabel metal3 s -960 436508 480 436748 4 analog_io[22]
+port 15 nsew
+rlabel metal3 s -960 384284 480 384524 4 analog_io[23]
+port 16 nsew
+rlabel metal3 s -960 332196 480 332436 4 analog_io[24]
+port 17 nsew
+rlabel metal3 s -960 279972 480 280212 4 analog_io[25]
+port 18 nsew
+rlabel metal3 s -960 227884 480 228124 4 analog_io[26]
+port 19 nsew
+rlabel metal3 s -960 175796 480 176036 4 analog_io[27]
+port 20 nsew
+rlabel metal3 s -960 123572 480 123812 4 analog_io[28]
+port 21 nsew
+rlabel metal3 s 583520 391628 584960 391868 4 analog_io[2]
+port 22 nsew
+rlabel metal3 s 583520 444668 584960 444908 4 analog_io[3]
+port 23 nsew
+rlabel metal3 s 583520 497844 584960 498084 4 analog_io[4]
+port 24 nsew
+rlabel metal3 s 583520 551020 584960 551260 4 analog_io[5]
+port 25 nsew
+rlabel metal3 s 583520 604060 584960 604300 4 analog_io[6]
+port 26 nsew
+rlabel metal3 s 583520 657236 584960 657476 4 analog_io[7]
+port 27 nsew
+rlabel metal2 s 575818 703520 575930 704960 4 analog_io[8]
+port 28 nsew
+rlabel metal2 s 510958 703520 511070 704960 4 analog_io[9]
+port 29 nsew
+rlabel metal3 s 583520 6476 584960 6716 4 io_in[0]
+port 30 nsew
+rlabel metal3 s 583520 457996 584960 458236 4 io_in[10]
+port 31 nsew
+rlabel metal3 s 583520 511172 584960 511412 4 io_in[11]
+port 32 nsew
+rlabel metal3 s 583520 564212 584960 564452 4 io_in[12]
+port 33 nsew
+rlabel metal3 s 583520 617388 584960 617628 4 io_in[13]
+port 34 nsew
+rlabel metal3 s 583520 670564 584960 670804 4 io_in[14]
+port 35 nsew
+rlabel metal2 s 559626 703520 559738 704960 4 io_in[15]
+port 36 nsew
+rlabel metal2 s 494766 703520 494878 704960 4 io_in[16]
+port 37 nsew
+rlabel metal2 s 429814 703520 429926 704960 4 io_in[17]
+port 38 nsew
+rlabel metal2 s 364954 703520 365066 704960 4 io_in[18]
+port 39 nsew
+rlabel metal2 s 300094 703520 300206 704960 4 io_in[19]
+port 40 nsew
+rlabel metal3 s 583520 46188 584960 46428 4 io_in[1]
+port 41 nsew
+rlabel metal2 s 235142 703520 235254 704960 4 io_in[20]
+port 42 nsew
+rlabel metal2 s 170282 703520 170394 704960 4 io_in[21]
+port 43 nsew
+rlabel metal2 s 105422 703520 105534 704960 4 io_in[22]
+port 44 nsew
+rlabel metal2 s 40470 703520 40582 704960 4 io_in[23]
+port 45 nsew
+rlabel metal3 s -960 684164 480 684404 4 io_in[24]
+port 46 nsew
+rlabel metal3 s -960 631940 480 632180 4 io_in[25]
+port 47 nsew
+rlabel metal3 s -960 579852 480 580092 4 io_in[26]
+port 48 nsew
+rlabel metal3 s -960 527764 480 528004 4 io_in[27]
+port 49 nsew
+rlabel metal3 s -960 475540 480 475780 4 io_in[28]
+port 50 nsew
+rlabel metal3 s -960 423452 480 423692 4 io_in[29]
+port 51 nsew
+rlabel metal3 s 583520 86036 584960 86276 4 io_in[2]
+port 52 nsew
+rlabel metal3 s -960 371228 480 371468 4 io_in[30]
+port 53 nsew
+rlabel metal3 s -960 319140 480 319380 4 io_in[31]
+port 54 nsew
+rlabel metal3 s -960 267052 480 267292 4 io_in[32]
+port 55 nsew
+rlabel metal3 s -960 214828 480 215068 4 io_in[33]
+port 56 nsew
+rlabel metal3 s -960 162740 480 162980 4 io_in[34]
+port 57 nsew
+rlabel metal3 s -960 110516 480 110756 4 io_in[35]
+port 58 nsew
+rlabel metal3 s -960 71484 480 71724 4 io_in[36]
+port 59 nsew
+rlabel metal3 s -960 32316 480 32556 4 io_in[37]
+port 60 nsew
+rlabel metal3 s 583520 125884 584960 126124 4 io_in[3]
+port 61 nsew
+rlabel metal3 s 583520 165732 584960 165972 4 io_in[4]
+port 62 nsew
+rlabel metal3 s 583520 205580 584960 205820 4 io_in[5]
+port 63 nsew
+rlabel metal3 s 583520 245428 584960 245668 4 io_in[6]
+port 64 nsew
+rlabel metal3 s 583520 298604 584960 298844 4 io_in[7]
+port 65 nsew
+rlabel metal3 s 583520 351780 584960 352020 4 io_in[8]
+port 66 nsew
+rlabel metal3 s 583520 404820 584960 405060 4 io_in[9]
+port 67 nsew
+rlabel metal3 s 583520 32996 584960 33236 4 io_oeb[0]
+port 68 nsew
+rlabel metal3 s 583520 484516 584960 484756 4 io_oeb[10]
+port 69 nsew
+rlabel metal3 s 583520 537692 584960 537932 4 io_oeb[11]
+port 70 nsew
+rlabel metal3 s 583520 590868 584960 591108 4 io_oeb[12]
+port 71 nsew
+rlabel metal3 s 583520 643908 584960 644148 4 io_oeb[13]
+port 72 nsew
+rlabel metal3 s 583520 697084 584960 697324 4 io_oeb[14]
+port 73 nsew
+rlabel metal2 s 527150 703520 527262 704960 4 io_oeb[15]
+port 74 nsew
+rlabel metal2 s 462290 703520 462402 704960 4 io_oeb[16]
+port 75 nsew
+rlabel metal2 s 397430 703520 397542 704960 4 io_oeb[17]
+port 76 nsew
+rlabel metal2 s 332478 703520 332590 704960 4 io_oeb[18]
+port 77 nsew
+rlabel metal2 s 267618 703520 267730 704960 4 io_oeb[19]
+port 78 nsew
+rlabel metal3 s 583520 72844 584960 73084 4 io_oeb[1]
+port 79 nsew
+rlabel metal2 s 202758 703520 202870 704960 4 io_oeb[20]
+port 80 nsew
+rlabel metal2 s 137806 703520 137918 704960 4 io_oeb[21]
+port 81 nsew
+rlabel metal2 s 72946 703520 73058 704960 4 io_oeb[22]
+port 82 nsew
+rlabel metal2 s 8086 703520 8198 704960 4 io_oeb[23]
+port 83 nsew
+rlabel metal3 s -960 658052 480 658292 4 io_oeb[24]
+port 84 nsew
+rlabel metal3 s -960 605964 480 606204 4 io_oeb[25]
+port 85 nsew
+rlabel metal3 s -960 553740 480 553980 4 io_oeb[26]
+port 86 nsew
+rlabel metal3 s -960 501652 480 501892 4 io_oeb[27]
+port 87 nsew
+rlabel metal3 s -960 449428 480 449668 4 io_oeb[28]
+port 88 nsew
+rlabel metal3 s -960 397340 480 397580 4 io_oeb[29]
+port 89 nsew
+rlabel metal3 s 583520 112692 584960 112932 4 io_oeb[2]
+port 90 nsew
+rlabel metal3 s -960 345252 480 345492 4 io_oeb[30]
+port 91 nsew
+rlabel metal3 s -960 293028 480 293268 4 io_oeb[31]
+port 92 nsew
+rlabel metal3 s -960 240940 480 241180 4 io_oeb[32]
+port 93 nsew
+rlabel metal3 s -960 188716 480 188956 4 io_oeb[33]
+port 94 nsew
+rlabel metal3 s -960 136628 480 136868 4 io_oeb[34]
+port 95 nsew
+rlabel metal3 s -960 84540 480 84780 4 io_oeb[35]
+port 96 nsew
+rlabel metal3 s -960 45372 480 45612 4 io_oeb[36]
+port 97 nsew
+rlabel metal3 s -960 6340 480 6580 4 io_oeb[37]
+port 98 nsew
+rlabel metal3 s 583520 152540 584960 152780 4 io_oeb[3]
+port 99 nsew
+rlabel metal3 s 583520 192388 584960 192628 4 io_oeb[4]
+port 100 nsew
+rlabel metal3 s 583520 232236 584960 232476 4 io_oeb[5]
+port 101 nsew
+rlabel metal3 s 583520 272084 584960 272324 4 io_oeb[6]
+port 102 nsew
+rlabel metal3 s 583520 325124 584960 325364 4 io_oeb[7]
+port 103 nsew
+rlabel metal3 s 583520 378300 584960 378540 4 io_oeb[8]
+port 104 nsew
+rlabel metal3 s 583520 431476 584960 431716 4 io_oeb[9]
+port 105 nsew
+rlabel metal3 s 583520 19668 584960 19908 4 io_out[0]
+port 106 nsew
+rlabel metal3 s 583520 471324 584960 471564 4 io_out[10]
+port 107 nsew
+rlabel metal3 s 583520 524364 584960 524604 4 io_out[11]
+port 108 nsew
+rlabel metal3 s 583520 577540 584960 577780 4 io_out[12]
+port 109 nsew
+rlabel metal3 s 583520 630716 584960 630956 4 io_out[13]
+port 110 nsew
+rlabel metal3 s 583520 683756 584960 683996 4 io_out[14]
+port 111 nsew
+rlabel metal2 s 543434 703520 543546 704960 4 io_out[15]
+port 112 nsew
+rlabel metal2 s 478482 703520 478594 704960 4 io_out[16]
+port 113 nsew
+rlabel metal2 s 413622 703520 413734 704960 4 io_out[17]
+port 114 nsew
+rlabel metal2 s 348762 703520 348874 704960 4 io_out[18]
+port 115 nsew
+rlabel metal2 s 283810 703520 283922 704960 4 io_out[19]
+port 116 nsew
+rlabel metal3 s 583520 59516 584960 59756 4 io_out[1]
+port 117 nsew
+rlabel metal2 s 218950 703520 219062 704960 4 io_out[20]
+port 118 nsew
+rlabel metal2 s 154090 703520 154202 704960 4 io_out[21]
+port 119 nsew
+rlabel metal2 s 89138 703520 89250 704960 4 io_out[22]
+port 120 nsew
+rlabel metal2 s 24278 703520 24390 704960 4 io_out[23]
+port 121 nsew
+rlabel metal3 s -960 671108 480 671348 4 io_out[24]
+port 122 nsew
+rlabel metal3 s -960 619020 480 619260 4 io_out[25]
+port 123 nsew
+rlabel metal3 s -960 566796 480 567036 4 io_out[26]
+port 124 nsew
+rlabel metal3 s -960 514708 480 514948 4 io_out[27]
+port 125 nsew
+rlabel metal3 s -960 462484 480 462724 4 io_out[28]
+port 126 nsew
+rlabel metal3 s -960 410396 480 410636 4 io_out[29]
+port 127 nsew
+rlabel metal3 s 583520 99364 584960 99604 4 io_out[2]
+port 128 nsew
+rlabel metal3 s -960 358308 480 358548 4 io_out[30]
+port 129 nsew
+rlabel metal3 s -960 306084 480 306324 4 io_out[31]
+port 130 nsew
+rlabel metal3 s -960 253996 480 254236 4 io_out[32]
+port 131 nsew
+rlabel metal3 s -960 201772 480 202012 4 io_out[33]
+port 132 nsew
+rlabel metal3 s -960 149684 480 149924 4 io_out[34]
+port 133 nsew
+rlabel metal3 s -960 97460 480 97700 4 io_out[35]
+port 134 nsew
+rlabel metal3 s -960 58428 480 58668 4 io_out[36]
+port 135 nsew
+rlabel metal3 s -960 19260 480 19500 4 io_out[37]
+port 136 nsew
+rlabel metal3 s 583520 139212 584960 139452 4 io_out[3]
+port 137 nsew
+rlabel metal3 s 583520 179060 584960 179300 4 io_out[4]
+port 138 nsew
+rlabel metal3 s 583520 218908 584960 219148 4 io_out[5]
+port 139 nsew
+rlabel metal3 s 583520 258756 584960 258996 4 io_out[6]
+port 140 nsew
+rlabel metal3 s 583520 311932 584960 312172 4 io_out[7]
+port 141 nsew
+rlabel metal3 s 583520 364972 584960 365212 4 io_out[8]
+port 142 nsew
+rlabel metal3 s 583520 418148 584960 418388 4 io_out[9]
+port 143 nsew
+rlabel metal2 s 125846 -960 125958 480 4 la_data_in[0]
+port 144 nsew
+rlabel metal2 s 480506 -960 480618 480 4 la_data_in[100]
+port 145 nsew
+rlabel metal2 s 484002 -960 484114 480 4 la_data_in[101]
+port 146 nsew
+rlabel metal2 s 487590 -960 487702 480 4 la_data_in[102]
+port 147 nsew
+rlabel metal2 s 491086 -960 491198 480 4 la_data_in[103]
+port 148 nsew
+rlabel metal2 s 494674 -960 494786 480 4 la_data_in[104]
+port 149 nsew
+rlabel metal2 s 498170 -960 498282 480 4 la_data_in[105]
+port 150 nsew
+rlabel metal2 s 501758 -960 501870 480 4 la_data_in[106]
+port 151 nsew
+rlabel metal2 s 505346 -960 505458 480 4 la_data_in[107]
+port 152 nsew
+rlabel metal2 s 508842 -960 508954 480 4 la_data_in[108]
+port 153 nsew
+rlabel metal2 s 512430 -960 512542 480 4 la_data_in[109]
+port 154 nsew
+rlabel metal2 s 161266 -960 161378 480 4 la_data_in[10]
+port 155 nsew
+rlabel metal2 s 515926 -960 516038 480 4 la_data_in[110]
+port 156 nsew
+rlabel metal2 s 519514 -960 519626 480 4 la_data_in[111]
+port 157 nsew
+rlabel metal2 s 523010 -960 523122 480 4 la_data_in[112]
+port 158 nsew
+rlabel metal2 s 526598 -960 526710 480 4 la_data_in[113]
+port 159 nsew
+rlabel metal2 s 530094 -960 530206 480 4 la_data_in[114]
+port 160 nsew
+rlabel metal2 s 533682 -960 533794 480 4 la_data_in[115]
+port 161 nsew
+rlabel metal2 s 537178 -960 537290 480 4 la_data_in[116]
+port 162 nsew
+rlabel metal2 s 540766 -960 540878 480 4 la_data_in[117]
+port 163 nsew
+rlabel metal2 s 544354 -960 544466 480 4 la_data_in[118]
+port 164 nsew
+rlabel metal2 s 547850 -960 547962 480 4 la_data_in[119]
+port 165 nsew
+rlabel metal2 s 164854 -960 164966 480 4 la_data_in[11]
+port 166 nsew
+rlabel metal2 s 551438 -960 551550 480 4 la_data_in[120]
+port 167 nsew
+rlabel metal2 s 554934 -960 555046 480 4 la_data_in[121]
+port 168 nsew
+rlabel metal2 s 558522 -960 558634 480 4 la_data_in[122]
+port 169 nsew
+rlabel metal2 s 562018 -960 562130 480 4 la_data_in[123]
+port 170 nsew
+rlabel metal2 s 565606 -960 565718 480 4 la_data_in[124]
+port 171 nsew
+rlabel metal2 s 569102 -960 569214 480 4 la_data_in[125]
+port 172 nsew
+rlabel metal2 s 572690 -960 572802 480 4 la_data_in[126]
+port 173 nsew
+rlabel metal2 s 576278 -960 576390 480 4 la_data_in[127]
+port 174 nsew
+rlabel metal2 s 168350 -960 168462 480 4 la_data_in[12]
+port 175 nsew
+rlabel metal2 s 171938 -960 172050 480 4 la_data_in[13]
+port 176 nsew
+rlabel metal2 s 175434 -960 175546 480 4 la_data_in[14]
+port 177 nsew
+rlabel metal2 s 179022 -960 179134 480 4 la_data_in[15]
+port 178 nsew
+rlabel metal2 s 182518 -960 182630 480 4 la_data_in[16]
+port 179 nsew
+rlabel metal2 s 186106 -960 186218 480 4 la_data_in[17]
+port 180 nsew
+rlabel metal2 s 189694 -960 189806 480 4 la_data_in[18]
+port 181 nsew
+rlabel metal2 s 193190 -960 193302 480 4 la_data_in[19]
+port 182 nsew
+rlabel metal2 s 129342 -960 129454 480 4 la_data_in[1]
+port 183 nsew
+rlabel metal2 s 196778 -960 196890 480 4 la_data_in[20]
+port 184 nsew
+rlabel metal2 s 200274 -960 200386 480 4 la_data_in[21]
+port 185 nsew
+rlabel metal2 s 203862 -960 203974 480 4 la_data_in[22]
+port 186 nsew
+rlabel metal2 s 207358 -960 207470 480 4 la_data_in[23]
+port 187 nsew
+rlabel metal2 s 210946 -960 211058 480 4 la_data_in[24]
+port 188 nsew
+rlabel metal2 s 214442 -960 214554 480 4 la_data_in[25]
+port 189 nsew
+rlabel metal2 s 218030 -960 218142 480 4 la_data_in[26]
+port 190 nsew
+rlabel metal2 s 221526 -960 221638 480 4 la_data_in[27]
+port 191 nsew
+rlabel metal2 s 225114 -960 225226 480 4 la_data_in[28]
+port 192 nsew
+rlabel metal2 s 228702 -960 228814 480 4 la_data_in[29]
+port 193 nsew
+rlabel metal2 s 132930 -960 133042 480 4 la_data_in[2]
+port 194 nsew
+rlabel metal2 s 232198 -960 232310 480 4 la_data_in[30]
+port 195 nsew
+rlabel metal2 s 235786 -960 235898 480 4 la_data_in[31]
+port 196 nsew
+rlabel metal2 s 239282 -960 239394 480 4 la_data_in[32]
+port 197 nsew
+rlabel metal2 s 242870 -960 242982 480 4 la_data_in[33]
+port 198 nsew
+rlabel metal2 s 246366 -960 246478 480 4 la_data_in[34]
+port 199 nsew
+rlabel metal2 s 249954 -960 250066 480 4 la_data_in[35]
+port 200 nsew
+rlabel metal2 s 253450 -960 253562 480 4 la_data_in[36]
+port 201 nsew
+rlabel metal2 s 257038 -960 257150 480 4 la_data_in[37]
+port 202 nsew
+rlabel metal2 s 260626 -960 260738 480 4 la_data_in[38]
+port 203 nsew
+rlabel metal2 s 264122 -960 264234 480 4 la_data_in[39]
+port 204 nsew
+rlabel metal2 s 136426 -960 136538 480 4 la_data_in[3]
+port 205 nsew
+rlabel metal2 s 267710 -960 267822 480 4 la_data_in[40]
+port 206 nsew
+rlabel metal2 s 271206 -960 271318 480 4 la_data_in[41]
+port 207 nsew
+rlabel metal2 s 274794 -960 274906 480 4 la_data_in[42]
+port 208 nsew
+rlabel metal2 s 278290 -960 278402 480 4 la_data_in[43]
+port 209 nsew
+rlabel metal2 s 281878 -960 281990 480 4 la_data_in[44]
+port 210 nsew
+rlabel metal2 s 285374 -960 285486 480 4 la_data_in[45]
+port 211 nsew
+rlabel metal2 s 288962 -960 289074 480 4 la_data_in[46]
+port 212 nsew
+rlabel metal2 s 292550 -960 292662 480 4 la_data_in[47]
+port 213 nsew
+rlabel metal2 s 296046 -960 296158 480 4 la_data_in[48]
+port 214 nsew
+rlabel metal2 s 299634 -960 299746 480 4 la_data_in[49]
+port 215 nsew
+rlabel metal2 s 140014 -960 140126 480 4 la_data_in[4]
+port 216 nsew
+rlabel metal2 s 303130 -960 303242 480 4 la_data_in[50]
+port 217 nsew
+rlabel metal2 s 306718 -960 306830 480 4 la_data_in[51]
+port 218 nsew
+rlabel metal2 s 310214 -960 310326 480 4 la_data_in[52]
+port 219 nsew
+rlabel metal2 s 313802 -960 313914 480 4 la_data_in[53]
+port 220 nsew
+rlabel metal2 s 317298 -960 317410 480 4 la_data_in[54]
+port 221 nsew
+rlabel metal2 s 320886 -960 320998 480 4 la_data_in[55]
+port 222 nsew
+rlabel metal2 s 324382 -960 324494 480 4 la_data_in[56]
+port 223 nsew
+rlabel metal2 s 327970 -960 328082 480 4 la_data_in[57]
+port 224 nsew
+rlabel metal2 s 331558 -960 331670 480 4 la_data_in[58]
+port 225 nsew
+rlabel metal2 s 335054 -960 335166 480 4 la_data_in[59]
+port 226 nsew
+rlabel metal2 s 143510 -960 143622 480 4 la_data_in[5]
+port 227 nsew
+rlabel metal2 s 338642 -960 338754 480 4 la_data_in[60]
+port 228 nsew
+rlabel metal2 s 342138 -960 342250 480 4 la_data_in[61]
+port 229 nsew
+rlabel metal2 s 345726 -960 345838 480 4 la_data_in[62]
+port 230 nsew
+rlabel metal2 s 349222 -960 349334 480 4 la_data_in[63]
+port 231 nsew
+rlabel metal2 s 352810 -960 352922 480 4 la_data_in[64]
+port 232 nsew
+rlabel metal2 s 356306 -960 356418 480 4 la_data_in[65]
+port 233 nsew
+rlabel metal2 s 359894 -960 360006 480 4 la_data_in[66]
+port 234 nsew
+rlabel metal2 s 363482 -960 363594 480 4 la_data_in[67]
+port 235 nsew
+rlabel metal2 s 366978 -960 367090 480 4 la_data_in[68]
+port 236 nsew
+rlabel metal2 s 370566 -960 370678 480 4 la_data_in[69]
+port 237 nsew
+rlabel metal2 s 147098 -960 147210 480 4 la_data_in[6]
+port 238 nsew
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+rlabel metal2 s 106894 -960 107006 480 4 wbs_dat_o[26]
+port 626 nsew
+rlabel metal2 s 110482 -960 110594 480 4 wbs_dat_o[27]
+port 627 nsew
+rlabel metal2 s 113978 -960 114090 480 4 wbs_dat_o[28]
+port 628 nsew
+rlabel metal2 s 117566 -960 117678 480 4 wbs_dat_o[29]
+port 629 nsew
+rlabel metal2 s 19402 -960 19514 480 4 wbs_dat_o[2]
+port 630 nsew
+rlabel metal2 s 121062 -960 121174 480 4 wbs_dat_o[30]
+port 631 nsew
+rlabel metal2 s 124650 -960 124762 480 4 wbs_dat_o[31]
+port 632 nsew
+rlabel metal2 s 24186 -960 24298 480 4 wbs_dat_o[3]
+port 633 nsew
+rlabel metal2 s 28878 -960 28990 480 4 wbs_dat_o[4]
+port 634 nsew
+rlabel metal2 s 32374 -960 32486 480 4 wbs_dat_o[5]
+port 635 nsew
+rlabel metal2 s 35962 -960 36074 480 4 wbs_dat_o[6]
+port 636 nsew
+rlabel metal2 s 39550 -960 39662 480 4 wbs_dat_o[7]
+port 637 nsew
+rlabel metal2 s 43046 -960 43158 480 4 wbs_dat_o[8]
+port 638 nsew
+rlabel metal2 s 46634 -960 46746 480 4 wbs_dat_o[9]
+port 639 nsew
+rlabel metal2 s 11122 -960 11234 480 4 wbs_sel_i[0]
+port 640 nsew
+rlabel metal2 s 15906 -960 16018 480 4 wbs_sel_i[1]
+port 641 nsew
+rlabel metal2 s 20598 -960 20710 480 4 wbs_sel_i[2]
+port 642 nsew
+rlabel metal2 s 25290 -960 25402 480 4 wbs_sel_i[3]
+port 643 nsew
+rlabel metal2 s 5234 -960 5346 480 4 wbs_stb_i
+port 644 nsew
+rlabel metal2 s 6430 -960 6542 480 4 wbs_we_i
+port 645 nsew
+<< properties >>
+string FIXED_BBOX 0 0 584000 704000
+<< end >>
diff --git a/mpw_precheck/outputs/user_project_wrapper.xor.gds b/mpw_precheck/outputs/user_project_wrapper.xor.gds
new file mode 100644
index 0000000..dd60771
--- /dev/null
+++ b/mpw_precheck/outputs/user_project_wrapper.xor.gds
Binary files differ
diff --git a/mpw_precheck/outputs/user_project_wrapper_empty_erased.gds b/mpw_precheck/outputs/user_project_wrapper_empty_erased.gds
new file mode 100644
index 0000000..588e5f8
--- /dev/null
+++ b/mpw_precheck/outputs/user_project_wrapper_empty_erased.gds
Binary files differ
diff --git a/mpw_precheck/outputs/user_project_wrapper_erased.gds b/mpw_precheck/outputs/user_project_wrapper_erased.gds
new file mode 100644
index 0000000..e0495e8
--- /dev/null
+++ b/mpw_precheck/outputs/user_project_wrapper_erased.gds
Binary files differ
diff --git a/mpw_precheck/outputs/user_project_wrapper_no_zero_areas.gds.gz b/mpw_precheck/outputs/user_project_wrapper_no_zero_areas.gds.gz
new file mode 100644
index 0000000..6eb38f3
--- /dev/null
+++ b/mpw_precheck/outputs/user_project_wrapper_no_zero_areas.gds.gz
Binary files differ
diff --git a/signoff/.gitignore b/signoff/.gitignore
new file mode 100644
index 0000000..6407046
--- /dev/null
+++ b/signoff/.gitignore
@@ -0,0 +1 @@
+cdrcpost/*
diff --git a/signoff/assigned_slot b/signoff/assigned_slot
new file mode 100644
index 0000000..ac198be
--- /dev/null
+++ b/signoff/assigned_slot
@@ -0,0 +1 @@
+039
diff --git a/signoff/caravel_layout.png b/signoff/caravel_layout.png
new file mode 100644
index 0000000..012e254
--- /dev/null
+++ b/signoff/caravel_layout.png
Binary files differ
diff --git a/tapeout/logs/compose.log b/tapeout/logs/compose.log
new file mode 100644
index 0000000..f45c7ff
--- /dev/null
+++ b/tapeout/logs/compose.log
@@ -0,0 +1,1773 @@
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/compose.tcl" from command line.
+caravel: 10000 rects
+caravel: 20000 rects
+caravel: 30000 rects
+caravel: 40000 rects
+caravel: 50000 rects
+caravel: 60000 rects
+caravel: 70000 rects
+caravel: 80000 rects
+caravel
+Scaled magic input cell advSeal_6um_gen geometry by factor of 2
+Writing final GDS. . .
+Scaled magic input cell seal_ring_corner_abstract geometry by factor of 2
+Scaled magic input cell caravel_motto geometry by factor of 2
+Scaled magic input cell font_22 geometry by factor of 24
+Scaled magic input cell font_73 geometry by factor of 24
+Scaled magic input cell font_43 geometry by factor of 24
+Scaled magic input cell font_49 geometry by factor of 24
+Scaled magic input cell font_65 geometry by factor of 24
+Scaled magic input cell font_68 geometry by factor of 24
+Scaled magic input cell font_54 geometry by factor of 24
+Scaled magic input cell font_67 geometry by factor of 24
+Scaled magic input cell font_6E geometry by factor of 24
+Scaled magic input cell font_69 geometry by factor of 24
+Scaled magic input cell font_6C geometry by factor of 24
+Scaled magic input cell font_61 geometry by factor of 24
+Scaled magic input cell font_53 geometry by factor of 24
+Scaled magic input cell font_79 geometry by factor of 24
+Scaled magic input cell font_76 geometry by factor of 24
+Scaled magic input cell font_74 geometry by factor of 24
+Scaled magic input cell font_72 geometry by factor of 24
+Scaled magic input cell font_70 geometry by factor of 24
+Scaled magic input cell font_66 geometry by factor of 24
+Scaled magic input cell font_63 geometry by factor of 24
+Scaled magic input cell font_62 geometry by factor of 24
+Scaled magic input cell font_57 geometry by factor of 24
+Scaled magic input cell font_56 geometry by factor of 24
+Scaled magic input cell font_50 geometry by factor of 24
+Scaled magic input cell font_47 geometry by factor of 24
+Scaled magic input cell font_44 geometry by factor of 24
+Scaled magic input cell font_35 geometry by factor of 24
+Scaled magic input cell font_32 geometry by factor of 24
+Scaled magic input cell font_30 geometry by factor of 24
+Scaled magic input cell font_29 geometry by factor of 24
+Scaled magic input cell font_28 geometry by factor of 24
+Scaled magic input cell font_20 geometry by factor of 24
+Scaled magic input cell font_6F geometry by factor of 24
+Scaled magic input cell font_6B geometry by factor of 24
+Scaled magic input cell font_4F geometry by factor of 24
+Scaled magic input cell font_4B geometry by factor of 24
+Scaled magic input cell font_2D geometry by factor of 24
+Scaled magic input cell open_source geometry by factor of 2
+Scaled magic input cell user_id_textblock geometry by factor of 2
+Scaled magic input cell alpha_0 geometry by factor of 2
+Scaled magic input cell user_project_wrapper geometry by factor of 2
+user_project_wrapper: 10000 rects
+user_project_wrapper: 20000 rects
+user_project_wrapper: 30000 rects
+user_project_wrapper: 40000 rects
+user_project_wrapper: 50000 rects
+Processing timestamp mismatches: sky130_ef_sc_hd__decap_12, sky130_fd_sc_hd__buf_8, sky130_fd_sc_hd__tapvpwrvgnd_1, sky130_ef_io__com_bus_slice_10um, sky130_ef_io__com_bus_slice_20um, sky130_ef_io__com_bus_slice_1um, sky130_ef_io__com_bus_slice_5um, sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um, sky130_ef_io__disconnect_vdda_slice_5um, sky130_ef_io__vccd_lvc_clamped_pad, sky130_ef_io__vddio_hvc_clamped_pad, sky130_ef_io__vssd_lvc_clamped_pad, sky130_ef_io__vssio_hvc_clamped_pad, sky130_ef_io__gpiov2_pad_wrapped, sky130_fd_io__top_xres4v2, sky130_ef_io__corner_pad, sky130_ef_io__vccd_lvc_clamped3_pad, sky130_ef_io__vdda_hvc_clamped_pad, sky130_ef_io__vssa_hvc_clamped_pad, sky130_ef_io__vssd_lvc_clamped3_pad, gpio_control_power_routing, gpio_control_power_routing_right, gpio_control_power_routing_top, mgmt_protect, spare_logic_block, user_id_programming, simple_por, digital_pll, housekeeping, gpio_defaults_block, gpio_control_block, buff_flash_clkrst, caravel_clocking, xres_buf, seal_ring_corner_abstract.
+ Generating output for cell advSeal_6um_gen
+Reading "sealring_slots".
+Reading "seal_ring_slots_array".
+Reading "sr_polygon00011".
+Reading "sr_polygon00039".
+Reading "sr_polygon00035".
+Reading "sr_polygon00015".
+Reading "sr_polygon00007".
+Reading "sr_polygon00001".
+Reading "sr_polygon00002".
+Reading "sr_polygon00003".
+Reading "sr_polygon00004".
+Reading "sr_polygon00005".
+Reading "sr_polygon00006".
+Reading "nikon_sealring_shape".
+Reading "sr_polygon00019".
+Reading "sr_polygon00023".
+Reading "sr_polygon00027".
+Reading "sr_polygon00031".
+Reading "sr_polygon00036".
+Reading "sr_polygon00032".
+Reading "sr_polygon00016".
+Reading "sr_polygon00020".
+Reading "sr_polygon00024".
+Reading "sr_polygon00028".
+Reading "seal_ring_corner".
+Reading "advSeal_6um_gen".
+ Generating output for cell caravel_00069f13_fill_pattern
+Reading "caravel_00069f13_fill_pattern_0_0".
+Reading "caravel_00069f13_fill_pattern_1_0".
+Reading "caravel_00069f13_fill_pattern_0_1".
+Reading "caravel_00069f13_fill_pattern_1_1".
+Reading "caravel_00069f13_fill_pattern_2_0".
+Reading "caravel_00069f13_fill_pattern_2_1".
+Reading "caravel_00069f13_fill_pattern_3_0".
+Reading "caravel_00069f13_fill_pattern_3_1".
+Reading "caravel_00069f13_fill_pattern_4_0".
+Reading "caravel_00069f13_fill_pattern_4_1".
+Reading "caravel_00069f13_fill_pattern_5_0".
+Reading "caravel_00069f13_fill_pattern_5_1".
+Reading "caravel_00069f13_fill_pattern_0_2".
+Reading "caravel_00069f13_fill_pattern_1_2".
+Reading "caravel_00069f13_fill_pattern_2_2".
+Reading "caravel_00069f13_fill_pattern_3_2".
+Reading "caravel_00069f13_fill_pattern_4_2".
+Reading "caravel_00069f13_fill_pattern_5_2".
+Reading "caravel_00069f13_fill_pattern_0_3".
+Reading "caravel_00069f13_fill_pattern_1_3".
+Reading "caravel_00069f13_fill_pattern_2_3".
+Reading "caravel_00069f13_fill_pattern_3_3".
+Reading "caravel_00069f13_fill_pattern_4_3".
+Reading "caravel_00069f13_fill_pattern_5_3".
+Reading "caravel_00069f13_fill_pattern_0_4".
+Reading "caravel_00069f13_fill_pattern_1_4".
+Reading "caravel_00069f13_fill_pattern_2_4".
+Reading "caravel_00069f13_fill_pattern_3_4".
+Reading "caravel_00069f13_fill_pattern_4_4".
+Reading "caravel_00069f13_fill_pattern_5_4".
+Reading "caravel_00069f13_fill_pattern_0_5".
+Reading "caravel_00069f13_fill_pattern_1_5".
+Reading "caravel_00069f13_fill_pattern_2_5".
+Reading "caravel_00069f13_fill_pattern_3_5".
+Reading "caravel_00069f13_fill_pattern_4_5".
+Reading "caravel_00069f13_fill_pattern_5_5".
+Reading "caravel_00069f13_fill_pattern_0_6".
+Reading "caravel_00069f13_fill_pattern_1_6".
+Reading "caravel_00069f13_fill_pattern_2_6".
+Reading "caravel_00069f13_fill_pattern_3_6".
+Reading "caravel_00069f13_fill_pattern_4_6".
+Reading "caravel_00069f13_fill_pattern_5_6".
+Reading "caravel_00069f13_fill_pattern_0_7".
+Reading "caravel_00069f13_fill_pattern_1_7".
+Reading "caravel_00069f13_fill_pattern_2_7".
+Reading "caravel_00069f13_fill_pattern_3_7".
+Reading "caravel_00069f13_fill_pattern_4_7".
+Reading "caravel_00069f13_fill_pattern_5_7".
+Reading "caravel_00069f13_fill_pattern".
+ Generating output for cell caravel
+Reading "caravel_logo".
+Reading "font_22".
+Reading "font_73".
+Reading "font_43".
+Reading "font_49".
+Reading "font_65".
+Reading "font_68".
+Reading "font_54".
+Reading "font_67".
+Reading "font_6E".
+Reading "font_69".
+Reading "font_6C".
+Reading "font_61".
+Reading "font_53".
+Reading "caravel_motto".
+Reading "font_79".
+Reading "font_76".
+Reading "font_74".
+Reading "font_72".
+Reading "font_70".
+Reading "font_66".
+Reading "font_63".
+Reading "font_62".
+Reading "font_57".
+Reading "font_56".
+Reading "font_50".
+Reading "font_47".
+Reading "font_44".
+Reading "font_35".
+Reading "font_32".
+Reading "font_30".
+Reading "font_29".
+Reading "font_28".
+Reading "font_20".
+Reading "font_6F".
+Reading "font_6B".
+Reading "font_4F".
+Reading "font_4B".
+Reading "font_2D".
+Reading "copyright_block".
+Reading "open_source".
+Reading "sky130_fd_sc_hvl__decap_8".
+Reading "sky130_fd_sc_hvl__decap_4".
+Reading "sky130_fd_sc_hvl__diode_2".
+Reading "sky130_fd_sc_hvl__fill_1".
+Reading "sky130_fd_sc_hvl__fill_2".
+Reading "sky130_fd_sc_hvl__lsbufhv2lv_1".
+Reading "xres_buf".
+Reading "alpha_6".
+Reading "alpha_9".
+Reading "alpha_F".
+Reading "alpha_1".
+Reading "alpha_3".
+Reading "alpha_0".
+Reading "user_id_textblock".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "gpio_defaults_block_1803".
+Reading "sky130_fd_sc_hd__o21bai_1".
+Reading "sky130_fd_sc_hd__nand3b_1".
+Reading "sky130_fd_sc_hd__nand4bb_1".
+Reading "sky130_fd_sc_hd__o2111ai_2".
+Reading "sky130_fd_sc_hd__o31ai_2".
+Reading "sky130_fd_sc_hd__o2bb2ai_1".
+Reading "sky130_fd_sc_hd__a41oi_1".
+Reading "sky130_fd_sc_hd__o211ai_4".
+Reading "sky130_fd_sc_hd__nor3b_2".
+Reading "sky130_fd_sc_hd__xnor2_1".
+Reading "sky130_fd_sc_hd__o2111ai_1".
+Reading "sky130_fd_sc_hd__nand3_1".
+Reading "sky130_fd_sc_hd__a31o_1".
+Reading "sky130_fd_sc_hd__o21a_1".
+Reading "sky130_fd_sc_hd__nand2b_1".
+Reading "sky130_fd_sc_hd__o22a_1".
+Reading "sky130_fd_sc_hd__o21ai_1".
+Reading "sky130_fd_sc_hd__a2bb2o_1".
+Reading "sky130_fd_sc_hd__nor2_1".
+Reading "sky130_fd_sc_hd__a21oi_1".
+Reading "sky130_fd_sc_hd__nor3_2".
+Reading "sky130_fd_sc_hd__nor3_1".
+Reading "sky130_fd_sc_hd__nor4_1".
+Reading "sky130_fd_sc_hd__o31ai_1".
+Reading "sky130_fd_sc_hd__a21o_1".
+Reading "sky130_fd_sc_hd__o31a_1".
+Reading "sky130_fd_sc_hd__mux2_1".
+Reading "sky130_fd_sc_hd__dfxtp_1".
+Reading "sky130_fd_sc_hd__dfstp_1".
+Reading "sky130_fd_sc_hd__dfrtp_4".
+Reading "sky130_fd_sc_hd__dfrtn_1".
+Reading "sky130_fd_sc_hd__dfstp_2".
+Reading "sky130_fd_sc_hd__dfrtp_1".
+Reading "sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "sky130_fd_sc_hd__buf_12".
+Reading "sky130_fd_sc_hd__o21a_2".
+Reading "sky130_fd_sc_hd__nand2b_2".
+Reading "sky130_fd_sc_hd__o21ai_2".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__dfrtp_2".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__clkbuf_2".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__nor2_2".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__inv_4".
+Reading "sky130_fd_sc_hd__clkinv_4".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__clkinv_2".
+Reading "sky130_fd_sc_hd__and2_1".
+Reading "sky130_fd_sc_hd__clkbuf_4".
+Reading "sky130_fd_sc_hd__nand2_1".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_ef_sc_hd__decap_12".
+Reading "caravel_clocking".
+Reading "sky130_fd_sc_hd__clkbuf_8".
+Reading "buff_flash_clkrst".
+Reading "sky130_fd_sc_hd__nand2_2".
+Reading "sky130_fd_sc_hd__macro_sparecell".
+Reading "sky130_fd_sc_hd__dfbbn_2".
+Reading "sky130_fd_sc_hd__or2_0".
+Reading "sky130_fd_sc_hd__o21ai_4".
+Reading "sky130_fd_sc_hd__and2_0".
+Reading "sky130_fd_sc_hd__mux2_4".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "sky130_fd_sc_hd__and2b_2".
+Reading "sky130_fd_sc_hd__and3b_2".
+Reading "sky130_fd_sc_hd__and2_2".
+Reading "sky130_fd_sc_hd__buf_16".
+Reading "gpio_logic_high".
+Reading "gpio_control_block".
+Reading "sky130_fd_sc_hd__dfstp_4".
+Reading "sky130_fd_sc_hd__a32o_1".
+Reading "sky130_fd_sc_hd__a22o_1".
+Reading "sky130_fd_sc_hd__a221o_1".
+Reading "sky130_fd_sc_hd__a211o_4".
+Reading "sky130_fd_sc_hd__a21bo_1".
+Reading "sky130_fd_sc_hd__o2bb2a_1".
+Reading "sky130_fd_sc_hd__a221o_2".
+Reading "sky130_fd_sc_hd__a211o_1".
+Reading "sky130_fd_sc_hd__o21ba_1".
+Reading "sky130_fd_sc_hd__and4b_1".
+Reading "sky130_fd_sc_hd__and4bb_1".
+Reading "sky130_fd_sc_hd__and4bb_2".
+Reading "sky130_fd_sc_hd__and3_4".
+Reading "sky130_fd_sc_hd__nand3_4".
+Reading "sky130_fd_sc_hd__a311o_1".
+Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__nor2_8".
+Reading "sky130_fd_sc_hd__o221a_1".
+Reading "sky130_fd_sc_hd__a2111o_1".
+Reading "sky130_fd_sc_hd__nor4_2".
+Reading "sky130_fd_sc_hd__a2111o_4".
+Reading "sky130_fd_sc_hd__nor4_4".
+Reading "sky130_fd_sc_hd__a2111o_2".
+Reading "sky130_fd_sc_hd__nand2b_4".
+Reading "sky130_fd_sc_hd__and3_1".
+Reading "sky130_fd_sc_hd__o32a_1".
+Reading "sky130_fd_sc_hd__a21boi_1".
+Reading "sky130_fd_sc_hd__nand4_1".
+Reading "sky130_fd_sc_hd__o311a_1".
+Reading "sky130_fd_sc_hd__o211a_1".
+Reading "sky130_fd_sc_hd__o2111a_1".
+Reading "sky130_fd_sc_hd__nand4b_1".
+Reading "sky130_fd_sc_hd__a31oi_1".
+Reading "sky130_fd_sc_hd__and4_1".
+Reading "sky130_fd_sc_hd__a41o_1".
+Reading "sky130_fd_sc_hd__and2b_1".
+Reading "sky130_fd_sc_hd__a311oi_2".
+Reading "sky130_fd_sc_hd__o41a_1".
+Reading "sky130_fd_sc_hd__nor3b_1".
+Reading "sky130_fd_sc_hd__a2111oi_1".
+Reading "sky130_fd_sc_hd__nand4b_4".
+Reading "sky130_fd_sc_hd__a31oi_4".
+Reading "sky130_fd_sc_hd__and4b_4".
+Reading "sky130_fd_sc_hd__nand3b_4".
+Reading "sky130_fd_sc_hd__o21a_4".
+Reading "sky130_fd_sc_hd__xor2_1".
+Reading "sky130_fd_sc_hd__nor3_4".
+Reading "sky130_fd_sc_hd__o221a_4".
+Reading "sky130_fd_sc_hd__mux2_8".
+Reading "sky130_fd_sc_hd__o31a_4".
+Reading "sky130_fd_sc_hd__and4_2".
+Reading "sky130_fd_sc_hd__a221oi_1".
+Reading "sky130_fd_sc_hd__a221o_4".
+Reading "sky130_fd_sc_hd__a21oi_4".
+Reading "sky130_fd_sc_hd__a21o_4".
+Reading "sky130_fd_sc_hd__inv_6".
+Reading "sky130_fd_sc_hd__a31o_2".
+Reading "sky130_fd_sc_hd__nand4_2".
+Reading "sky130_fd_sc_hd__and4b_2".
+Reading "sky130_fd_sc_hd__xnor2_2".
+Reading "sky130_fd_sc_hd__a21oi_2".
+Reading "sky130_fd_sc_hd__a211o_2".
+Reading "sky130_fd_sc_hd__and3_2".
+Reading "sky130_fd_sc_hd__o211a_2".
+Reading "sky130_fd_sc_hd__o31a_2".
+Reading "sky130_fd_sc_hd__nand3_2".
+Reading "sky130_fd_sc_hd__a21o_2".
+Reading "sky130_fd_sc_hd__a22o_2".
+Reading "sky130_fd_sc_hd__mux2_2".
+Reading "sky130_fd_sc_hd__and2b_4".
+Reading "sky130_fd_sc_hd__and3b_1".
+Reading "sky130_fd_sc_hd__and3b_4".
+Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hd__nand2_4".
+Reading "sky130_fd_sc_hd__nand2_8".
+Reading "sky130_fd_sc_hd__buf_6".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "housekeeping".
+Reading "sky130_fd_sc_hd__einvp_1".
+Reading "sky130_fd_sc_hd__clkinv_1".
+Reading "sky130_fd_sc_hd__einvn_4".
+Reading "sky130_fd_sc_hd__einvn_8".
+Reading "sky130_fd_sc_hd__einvp_2".
+Reading "sky130_fd_sc_hd__or2_2".
+Reading "sky130_fd_sc_hd__a32o_2".
+Reading "sky130_fd_sc_hd__o2111a_2".
+Reading "sky130_fd_sc_hd__o22a_2".
+Reading "sky130_fd_sc_hd__o221a_2".
+Reading "sky130_fd_sc_hd__nand3b_2".
+Reading "sky130_fd_sc_hd__a21boi_2".
+Reading "sky130_fd_sc_hd__xor2_2".
+Reading "sky130_fd_sc_hd__o2bb2a_2".
+Reading "sky130_fd_sc_hd__nand4b_2".
+Reading "sky130_fd_sc_hd__o21ba_2".
+Reading "sky130_fd_sc_hd__o32a_2".
+Reading "sky130_fd_sc_hd__clkinv_8".
+Reading "digital_pll".
+Reading "user_id_programming".
+Reading "D4_sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ".
+Reading "D4_sky130_fd_pr__pfet_g5v0d10v5_3YBPVB".
+Reading "D4_sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC".
+Reading "D4_sky130_fd_pr__nfet_g5v0d10v5_TGFUGS".
+Reading "D4_sky130_fd_pr__pfet_g5v0d10v5_YUHPBG".
+Reading "D4_sky130_fd_pr__pfet_g5v0d10v5_YEUEBV".
+Reading "D4_sky130_fd_pr__nfet_g5v0d10v5_PKVMTM".
+Reading "D4_sky130_fd_pr__pfet_g5v0d10v5_YUHPXE".
+Reading "D4_sky130_fd_sc_hvl__schmittbuf_1".
+Reading "D4_sky130_fd_sc_hvl__buf_8".
+Reading "D4_sky130_fd_sc_hvl__inv_8".
+Reading "D4_sky130_fd_sc_hvl__fill_4".
+Reading "D4_sky130_fd_pr__cap_mim_m3_1_WRT4AW".
+Reading "D4_sky130_fd_pr__cap_mim_m3_2_W5U4AW".
+Reading "D4_sky130_fd_pr__res_xhigh_po_0p69_S5N9F3".
+Reading "simple_por".
+Reading "ZT_sky130_fd_sc_hd__decap_3".
+Reading "ZT_sky130_ef_sc_hd__decap_12".
+Reading "ZT_sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "ZT_sky130_fd_sc_hd__fill_1".
+Reading "ZT_sky130_fd_sc_hd__decap_4".
+Reading "ZT_sky130_fd_sc_hd__decap_6".
+Reading "ZT_sky130_fd_sc_hd__fill_2".
+Reading "ZT_sky130_fd_sc_hd__decap_8".
+Reading "ZT_sky130_fd_sc_hd__diode_2".
+Reading "ZT_sky130_fd_sc_hd__clkbuf_16".
+Reading "ZT_sky130_fd_sc_hd__o211a_1".
+Reading "ZT_sky130_fd_sc_hd__dfxtp_2".
+Reading "ZT_sky130_fd_sc_hd__o21a_1".
+Reading "ZT_sky130_fd_sc_hd__mux2_1".
+Reading "ZT_sky130_fd_sc_hd__or2_1".
+Reading "ZT_sky130_fd_sc_hd__dfxtp_1".
+Reading "ZT_sky130_fd_sc_hd__a22o_1".
+Reading "ZT_sky130_fd_sc_hd__a21o_2".
+Reading "ZT_sky130_fd_sc_hd__a21o_1".
+Reading "ZT_sky130_fd_sc_hd__a22o_4".
+Reading "ZT_sky130_fd_sc_hd__buf_8".
+Reading "ZT_sky130_fd_sc_hd__o21a_2".
+Reading "ZT_sky130_fd_sc_hd__mux2_2".
+Reading "ZT_sky130_fd_sc_hd__buf_4".
+Reading "ZT_sky130_fd_sc_hd__clkbuf_8".
+Reading "ZT_sky130_fd_sc_hd__buf_6".
+Reading "ZT_sky130_fd_sc_hd__dfxtp_4".
+Reading "ZT_sky130_fd_sc_hd__buf_2".
+Reading "ZT_sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "ZT_sky130_fd_sc_hd__o21ai_1".
+Reading "ZT_sky130_fd_sc_hd__mux4_1".
+Reading "ZT_sky130_fd_sc_hd__buf_12".
+Reading "ZT_sky130_fd_sc_hd__mux4_2".
+Reading "ZT_sky130_fd_sc_hd__inv_2".
+Reading "ZT_sky130_fd_sc_hd__and3_2".
+Reading "ZT_sky130_fd_sc_hd__nand2_1".
+Reading "ZT_sky130_fd_sc_hd__a2bb2o_1".
+Reading "ZT_sky130_fd_sc_hd__or3b_1".
+Reading "ZT_sky130_fd_sc_hd__o32a_1".
+Reading "ZT_sky130_fd_sc_hd__a2bb2o_2".
+Reading "ZT_sky130_fd_sc_hd__o311a_1".
+Reading "ZT_sky130_fd_sc_hd__o221a_1".
+Reading "ZT_sky130_fd_sc_hd__o31a_1".
+Reading "ZT_sky130_fd_sc_hd__o211a_2".
+Reading "ZT_sky130_fd_sc_hd__and3_1".
+Reading "ZT_sky130_fd_sc_hd__a211oi_1".
+Reading "ZT_sky130_fd_sc_hd__and4_4".
+Reading "ZT_sky130_fd_sc_hd__and4_1".
+Reading "ZT_sky130_fd_sc_hd__clkbuf_4".
+Reading "ZT_sky130_fd_sc_hd__and3b_1".
+Reading "ZT_sky130_fd_sc_hd__a211o_4".
+Reading "ZT_sky130_fd_sc_hd__a211o_1".
+Reading "ZT_sky130_fd_sc_hd__o21ba_1".
+Reading "ZT_sky130_fd_sc_hd__a21oi_1".
+Reading "ZT_sky130_fd_sc_hd__nor2_1".
+Reading "ZT_sky130_fd_sc_hd__nand2_8".
+Reading "ZT_sky130_fd_sc_hd__a311o_1".
+Reading "ZT_sky130_fd_sc_hd__nor2_2".
+Reading "ZT_sky130_fd_sc_hd__a41o_1".
+Reading "ZT_sky130_fd_sc_hd__nor3_2".
+Reading "ZT_sky130_fd_sc_hd__or4bb_4".
+Reading "ZT_sky130_fd_sc_hd__nor3_1".
+Reading "ZT_sky130_fd_sc_hd__or4b_4".
+Reading "ZT_sky130_fd_sc_hd__or3b_4".
+Reading "ZT_sky130_fd_sc_hd__a31o_1".
+Reading "ZT_sky130_fd_sc_hd__a211o_2".
+Reading "ZT_sky130_fd_sc_hd__or2_2".
+Reading "ZT_sky130_fd_sc_hd__a31o_2".
+Reading "ZT_sky130_fd_sc_hd__a221o_1".
+Reading "ZT_sky130_fd_sc_hd__and4b_4".
+Reading "ZT_sky130_fd_sc_hd__and3_4".
+Reading "ZT_sky130_fd_sc_hd__mux2_8".
+Reading "ZT_sky130_fd_sc_hd__o21ai_2".
+Reading "ZT_sky130_fd_sc_hd__and4b_1".
+Reading "ZT_sky130_fd_sc_hd__or4b_1".
+Reading "ZT_sky130_fd_sc_hd__o211a_4".
+Reading "ZT_sky130_fd_sc_hd__a32o_1".
+Reading "ZT_sky130_fd_sc_hd__a21boi_1".
+Reading "ZT_sky130_fd_sc_hd__o41ai_4".
+Reading "ZT_sky130_fd_sc_hd__o31a_2".
+Reading "ZT_sky130_fd_sc_hd__nand2_4".
+Reading "ZT_sky130_fd_sc_hd__a31oi_4".
+Reading "ZT_sky130_fd_sc_hd__and4_2".
+Reading "ZT_sky130_fd_sc_hd__nand3_4".
+Reading "ZT_sky130_fd_sc_hd__and4b_2".
+Reading "ZT_sky130_fd_sc_hd__o41a_4".
+Reading "ZT_sky130_fd_sc_hd__and4bb_2".
+Reading "ZT_sky130_fd_sc_hd__clkinv_2".
+Reading "ZT_sky130_fd_sc_hd__and2b_2".
+Reading "ZT_sky130_fd_sc_hd__or4bb_1".
+Reading "ZT_sky130_fd_sc_hd__a21oi_2".
+Reading "ZT_sky130_fd_sc_hd__a221oi_1".
+Reading "ZT_sky130_fd_sc_hd__a31oi_1".
+Reading "ZT_sky130_fd_sc_hd__xor2_4".
+Reading "ZT_sky130_fd_sc_hd__clkbuf_1".
+Reading "ZT_sky130_fd_sc_hd__nand3b_4".
+Reading "ZT_sky130_fd_sc_hd__nand2_2".
+Reading "ZT_sky130_fd_sc_hd__xnor2_1".
+Reading "ZT_sky130_fd_sc_hd__and2_1".
+Reading "ZT_sky130_fd_sc_hd__nor2_4".
+Reading "ZT_sky130_fd_sc_hd__nand4_4".
+Reading "ZT_sky130_fd_sc_hd__a32o_2".
+Reading "ZT_sky130_fd_sc_hd__nor4_1".
+Reading "ZT_sky130_fd_sc_hd__nand4_1".
+Reading "ZT_sky130_fd_sc_hd__xor2_1".
+Reading "ZT_sky130_fd_sc_hd__and4bb_4".
+Reading "ZT_sky130_fd_sc_hd__a41o_2".
+Reading "ZT_sky130_fd_sc_hd__o2bb2a_1".
+Reading "ZT_sky130_fd_sc_hd__xnor2_2".
+Reading "ZT_sky130_fd_sc_hd__xor2_2".
+Reading "ZT_sky130_fd_sc_hd__or2_4".
+Reading "ZT_sky130_fd_sc_hd__a2111oi_2".
+Reading "ZT_sky130_fd_sc_hd__nor4_4".
+Reading "ZT_sky130_fd_sc_hd__mux2_4".
+Reading "ZT_sky130_fd_sc_hd__and2b_1".
+Reading "ZT_sky130_fd_sc_hd__and2_2".
+Reading "ZT_sky130_fd_sc_hd__nor4b_1".
+Reading "ZT_sky130_fd_sc_hd__o2111ai_4".
+Reading "ZT_sky130_fd_sc_hd__nor4_2".
+Reading "ZT_sky130_fd_sc_hd__nand3b_2".
+Reading "ZT_sky130_fd_sc_hd__nand3_1".
+Reading "ZT_sky130_fd_sc_hd__nand2b_2".
+Reading "ZT_sky130_fd_sc_hd__o31ai_1".
+Reading "ZT_sky130_fd_sc_hd__o41a_1".
+Reading "ZT_sky130_fd_sc_hd__a21bo_1".
+Reading "ZT_sky130_fd_sc_hd__o41ai_1".
+Reading "ZT_sky130_fd_sc_hd__nand3b_1".
+Reading "ZT_sky130_fd_sc_hd__o2111a_1".
+Reading "ZT_sky130_fd_sc_hd__o21a_4".
+Reading "ZT_sky130_fd_sc_hd__o22a_1".
+Reading "ZT_sky130_fd_sc_hd__or3b_2".
+Reading "ZT_sky130_fd_sc_hd__nand2b_1".
+Reading "ZT_sky130_fd_sc_hd__nor4b_4".
+Reading "ZT_sky130_fd_sc_hd__o21bai_1".
+Reading "ZT_sky130_fd_sc_hd__nor3_4".
+Reading "ZT_sky130_fd_sc_hd__o41a_2".
+Reading "ZT_sky130_fd_sc_hd__or4b_2".
+Reading "ZT_sky130_fd_sc_hd__a221o_4".
+Reading "ZT_sky130_fd_sc_hd__a2111oi_1".
+Reading "ZT_sky130_fd_sc_hd__o31a_4".
+Reading "ZT_sky130_fd_sc_hd__nor2_8".
+Reading "ZT_sky130_fd_sc_hd__clkinv_4".
+Reading "ZT_sky130_fd_sc_hd__a221o_2".
+Reading "ZT_sky130_fd_sc_hd__o21ai_4".
+Reading "ZT_sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "ZT_sky130_fd_sc_hd__clkbuf_2".
+Reading "ZT_sky130_fd_sc_hd__a31o_4".
+Reading "ZT_sky130_fd_sc_hd__ebufn_4".
+Reading "ZT_sky130_fd_sc_hd__dlxtp_1".
+Reading "ZT_sky130_fd_sc_hd__dlclkp_1".
+Reading "ZT_sky130_fd_sc_hd__conb_1".
+Reading "ZT_sky130_fd_sc_hd__inv_1".
+Reading "ZT_sky130_fd_sc_hd__nor4b_2".
+Reading "ZT_sky130_fd_sc_hd__and3b_2".
+Reading "ZT_sky130_fd_sc_hd__nor3b_2".
+Reading "ZT_RAM256".
+Reading "ZT_sky130_fd_sc_hd__a21o_4".
+Reading "ZT_sky130_fd_sc_hd__o2111a_4".
+Reading "ZT_sky130_fd_sc_hd__a22o_2".
+Reading "ZT_sky130_fd_sc_hd__o211ai_4".
+Reading "ZT_sky130_fd_sc_hd__o22ai_4".
+Reading "ZT_sky130_fd_sc_hd__a221oi_4".
+Reading "ZT_sky130_fd_sc_hd__and2b_4".
+Reading "ZT_sky130_fd_sc_hd__and3b_4".
+Reading "ZT_sky130_fd_sc_hd__and4bb_1".
+Reading "ZT_sky130_fd_sc_hd__a21oi_4".
+Reading "ZT_sky130_fd_sc_hd__o22ai_1".
+Reading "ZT_sky130_fd_sc_hd__inv_4".
+Reading "ZT_sky130_fd_sc_hd__a311o_2".
+Reading "ZT_sky130_fd_sc_hd__a2111o_1".
+Reading "ZT_sky130_fd_sc_hd__o311a_4".
+Reading "ZT_sky130_fd_sc_hd__o2111ai_1".
+Reading "ZT_sky130_fd_sc_hd__clkinv_8".
+Reading "ZT_sky130_fd_sc_hd__nand3_2".
+Reading "ZT_sky130_fd_sc_hd__a22oi_1".
+Reading "ZT_sky130_fd_sc_hd__nand4b_4".
+Reading "ZT_sky130_fd_sc_hd__o221ai_4".
+Reading "ZT_sky130_fd_sc_hd__nand4_2".
+Reading "ZT_sky130_fd_sc_hd__inv_6".
+Reading "ZT_sky130_fd_sc_hd__o2bb2ai_1".
+Reading "ZT_sky130_fd_sc_hd__a311oi_4".
+Reading "ZT_sky130_fd_sc_hd__o32ai_4".
+Reading "ZT_sky130_fd_sc_hd__o211ai_1".
+Reading "ZT_sky130_fd_sc_hd__nand4b_1".
+Reading "ZT_sky130_fd_sc_hd__o211ai_2".
+Reading "ZT_sky130_fd_sc_hd__a22oi_4".
+Reading "ZT_sky130_fd_sc_hd__and2_4".
+Reading "ZT_sky130_fd_sc_hd__a211oi_4".
+Reading "ZT_sky130_fd_sc_hd__nor3b_4".
+Reading "ZT_sky130_fd_sc_hd__o22a_2".
+Reading "ZT_sky130_fd_sc_hd__a2111oi_4".
+Reading "ZT_sky130_fd_sc_hd__nand2b_4".
+Reading "ZT_sky130_fd_sc_hd__a2bb2o_4".
+Reading "ZT_sky130_fd_sc_hd__o2bb2a_2".
+Reading "ZT_sky130_fd_sc_hd__o2111ai_2".
+Reading "ZT_sky130_fd_sc_hd__a22oi_2".
+Reading "ZT_sky130_fd_sc_hd__nor3b_1".
+Reading "ZT_sky130_fd_sc_hd__o2bb2a_4".
+Reading "ZT_sky130_fd_sc_hd__o21bai_4".
+Reading "ZT_sky130_fd_sc_hd__o311ai_1".
+Reading "ZT_sky130_fd_sc_hd__a32oi_2".
+Reading "ZT_sky130_fd_sc_hd__o2bb2ai_2".
+Reading "ZT_sky130_fd_sc_hd__o311ai_4".
+Reading "ZT_sky130_fd_sc_hd__o2bb2ai_4".
+Reading "ZT_sky130_fd_sc_hd__o31ai_4".
+Reading "ZT_sky130_fd_sc_hd__o221a_2".
+Reading "ZT_sky130_fd_sc_hd__o2111a_2".
+Reading "ZT_sky130_fd_sc_hd__a31oi_2".
+Reading "ZT_sky130_fd_sc_hd__o311a_2".
+Reading "ZT_sky130_fd_sc_hd__o22a_4".
+Reading "ZT_sky130_fd_sc_hd__a32oi_4".
+Reading "ZT_sky130_fd_sc_hd__a211oi_2".
+Reading "ZT_sky130_fd_sc_hd__o31ai_2".
+Reading "ZT_sky130_fd_sc_hd__o221ai_1".
+Reading "ZT_sky130_fd_sc_hd__clkinv_16".
+Reading "ZT_sky130_fd_sc_hd__or4bb_2".
+Reading "ZT_sky130_fd_sc_hd__a221oi_2".
+Reading "ZT_sky130_fd_sc_hd__inv_8".
+Reading "ZT_sky130_fd_sc_hd__a311oi_2".
+Reading "ZT_sky130_fd_sc_hd__a311oi_1".
+Reading "ZT_sky130_fd_sc_hd__o311ai_2".
+Reading "ZT_sky130_fd_sc_hd__a32oi_1".
+Reading "ZT_sky130_fd_sc_hd__a2bb2oi_2".
+Reading "ZT_sky130_fd_sc_hd__a2bb2oi_1".
+Reading "ZT_sky130_fd_sc_hd__a2bb2oi_4".
+Reading "ZT_sky130_fd_sc_hd__xnor2_4".
+Reading "ZT_sky130_fd_sc_hd__inv_12".
+Reading "ZT_sky130_fd_sc_hd__a2111o_4".
+Reading "ZT_sky130_fd_sc_hd__a32o_4".
+Reading "ZT_sky130_fd_sc_hd__o21ba_2".
+Reading "ZT_sky130_fd_sc_hd__a41oi_2".
+Reading "ZT_sky130_fd_sc_hd__o22ai_2".
+Reading "ZT_sky130_fd_sc_hd__o21bai_2".
+Reading "ZT_sky130_fd_sc_hd__a41oi_4".
+Reading "ZT_sky130_fd_sc_hd__a41o_4".
+Reading "ZT_sky130_fd_sc_hd__a311o_4".
+Reading "ZT_sky130_fd_sc_hd__o32ai_1".
+Reading "ZT_sky130_fd_sc_hd__a21boi_4".
+Reading "ZT_sky130_fd_sc_hd__o32ai_2".
+Reading "ZT_sky130_fd_sc_hd__a21bo_2".
+Reading "ZT_RAM128".
+Reading "mgmt_core_wrapper".
+Reading "gpio_defaults_block_0403".
+Reading "sky130_fd_sc_hd__inv_8".
+Reading "sky130_fd_sc_hd__dfbbp_1".
+Reading "spare_logic_block".
+Reading "sky130_fd_sc_hd__bufbuf_8".
+Reading "sky130_fd_sc_hvl__conb_1".
+Reading "mgmt_protect_hv".
+Reading "mprj_logic_high".
+Reading "mprj2_logic_high".
+Reading "sky130_fd_sc_hd__inv_12".
+Reading "mgmt_protect".
+Reading "gpio_defaults_block_0801".
+Reading "gpio_control_power_routing_top".
+Reading "gpio_control_power_routing_right".
+Reading "gpio_control_power_routing".
+Reading "caravel_power_routing".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_39".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_19".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_14".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_13".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_7".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_38".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_33".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_32".
+Reading "VA_sky130_fd_bd_sram__openram_dff".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_row_addr_dff".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_wmask_dff".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_cr_3".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_col_addr_dff".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_data_dff".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_16".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_29".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_28".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_11".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_360_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_12".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_1".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dli".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sli_dactive".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_1".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w1_680_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w1_680_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_3".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w0_740_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w1_260_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_2".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_0".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m7_w1_680_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m7_w2_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_4".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_1".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_0".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pand2_1".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m24_w2_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m24_w2_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_14".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m8_w2_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m8_w2_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_13".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w2_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w2_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_12".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_11".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_0".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_3".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_17".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_delay_chain".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m18_w2_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m18_w2_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_16".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_5".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dactive".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pnand3".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pand3_0".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m22_w2_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m22_w2_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_15".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_4".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pand3".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m42_w2_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m42_w2_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_10".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m15_w2_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m15_w2_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_9".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w2_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m5_w2_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_8".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w1_260_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w2_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_7".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_2".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_rw".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_cr_5".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array_0".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m41_w2_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m41_w2_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_20".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m14_w2_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m14_w2_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_19".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w1_680_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_18".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_6".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_r".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_cr_4".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_20".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_17".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_0".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pand2_0".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4_0".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_15".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w7_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w7_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec_0".
+Reading "VA_sky130_fd_bd_sram__openram_dp_nand2_dec".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec_0".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver_array".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec".
+Reading "VA_sky130_fd_bd_sram__openram_dp_nand3_dec".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_and3_dec".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode3x8".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_decoder".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_port_address_0".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_port_address".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_27".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_26".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_25".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_24".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w2_880_sli_dli".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_0".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array_0".
+Reading "VA_sky130_fd_bd_sram__openram_sense_amp".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_sense_amp_array".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_23".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_21".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_22".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w0_550_sli_dli".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_precharge_1".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array_0".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_port_data_0".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_column_mux".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pinv".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pnand2".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pand2".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_write_mask_and_array".
+Reading "VA_sky130_fd_bd_sram__openram_write_driver".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_write_driver_array".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_precharge_0".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_port_data".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_9".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_8".
+Reading "VA_sky130_fd_bd_sram__openram_dp_cell_cap_row".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array_0".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array".
+Reading "VA_sky130_fd_bd_sram__openram_dp_cell_cap_col".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array_0".
+Reading "VA_sky130_fd_bd_sram__openram_dp_cell_dummy".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_dummy_array".
+Reading "VA_sky130_fd_bd_sram__openram_dp_cell_replica".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_replica_column_0".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_replica_column".
+Reading "VA_sky130_fd_bd_sram__openram_dp_cell".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_bitcell_array".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_replica_bitcell_array".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_bank".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8".
+Reading "VA_sky130_fd_sc_hd__and2_2".
+Reading "VA_sky130_fd_sc_hd__or4_2".
+Reading "VA_sky130_fd_sc_hd__o41a_2".
+Reading "VA_sky130_fd_sc_hd__o311a_2".
+Reading "VA_sky130_fd_sc_hd__and3_2".
+Reading "VA_sky130_fd_sc_hd__conb_1".
+Reading "VA_sky130_fd_sc_hd__clkbuf_2".
+Reading "VA_sky130_fd_sc_hd__clkbuf_1".
+Reading "VA_sky130_fd_sc_hd__clkinv_2".
+Reading "VA_sky130_fd_sc_hd__mux2_1".
+Reading "VA_sky130_fd_sc_hd__o32a_2".
+Reading "VA_sky130_fd_sc_hd__clkinv_8".
+Reading "VA_sky130_fd_sc_hd__a221o_2".
+Reading "VA_sky130_fd_sc_hd__decap_8".
+Reading "VA_sky130_fd_sc_hd__o31a_2".
+Reading "VA_sky130_fd_sc_hd__a22oi_2".
+Reading "VA_sky130_fd_sc_hd__a21bo_2".
+Reading "VA_sky130_fd_sc_hd__a21o_2".
+Reading "VA_sky130_fd_sc_hd__o22a_2".
+Reading "VA_sky130_fd_sc_hd__o211a_2".
+Reading "VA_sky130_fd_sc_hd__and4_2".
+Reading "VA_sky130_fd_sc_hd__a31o_2".
+Reading "VA_sky130_fd_sc_hd__nand2_2".
+Reading "VA_sky130_fd_sc_hd__o2bb2ai_2".
+Reading "VA_sky130_fd_sc_hd__o21ai_2".
+Reading "VA_sky130_fd_sc_hd__o221a_2".
+Reading "VA_sky130_fd_sc_hd__a2bb2o_2".
+Reading "VA_sky130_fd_sc_hd__or2_2".
+Reading "VA_sky130_fd_sc_hd__inv_2".
+Reading "VA_sky130_fd_sc_hd__fill_2".
+Reading "VA_sky130_fd_sc_hd__or3_2".
+Reading "VA_sky130_fd_sc_hd__a21oi_2".
+Reading "VA_sky130_fd_sc_hd__nor2_2".
+Reading "VA_sky130_fd_sc_hd__a22o_2".
+Reading "VA_sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "VA_sky130_fd_sc_hd__dfrtp_2".
+Reading "VA_sky130_fd_sc_hd__decap_4".
+Reading "VA_sky130_fd_sc_hd__buf_1".
+Reading "VA_sky130_fd_sc_hd__diode_2".
+Reading "VA_sky130_fd_sc_hd__decap_6".
+Reading "VA_sky130_fd_sc_hd__fill_1".
+Reading "VA_sky130_fd_sc_hd__decap_3".
+Reading "VA_sky130_fd_sc_hd__buf_2".
+Reading "VA_sky130_ef_sc_hd__decap_12".
+Reading "VA_sky130_fd_sc_hd__dfrtp_4".
+Reading "VA_sky130_fd_sc_hd__dfrtp_1".
+Reading "VA_sky130_fd_sc_hd__dfstp_2".
+Reading "VA_sky130_fd_sc_hd__clkbuf_16".
+Reading "VA_sky130_fd_sc_hd__xnor2_1".
+Reading "VA_sky130_fd_sc_hd__xor2_1".
+Reading "VA_sky130_fd_sc_hd__o21ai_1".
+Reading "VA_sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "VA_sky130_fd_sc_hd__or2b_1".
+Reading "VA_sky130_fd_sc_hd__o211a_1".
+Reading "VA_sky130_fd_sc_hd__or2_1".
+Reading "VA_sky130_fd_sc_hd__dfstp_1".
+Reading "VA_sky130_fd_sc_hd__a21oi_1".
+Reading "VA_sky130_fd_sc_hd__a221o_1".
+Reading "VA_sky130_fd_sc_hd__a31o_1".
+Reading "VA_sky130_fd_sc_hd__nand2_1".
+Reading "VA_sky130_fd_sc_hd__o21a_1".
+Reading "VA_sky130_fd_sc_hd__o2bb2a_1".
+Reading "VA_sky130_fd_sc_hd__nor2_1".
+Reading "VA_sky130_fd_sc_hd__o21ai_4".
+Reading "VA_sky130_fd_sc_hd__clkbuf_4".
+Reading "VA_sky130_fd_sc_hd__and3_1".
+Reading "VA_sky130_fd_sc_hd__nand3_2".
+Reading "VA_sky130_fd_sc_hd__and2_1".
+Reading "VA_sky130_fd_sc_hd__a21o_1".
+Reading "VA_sky130_fd_sc_hd__a311o_1".
+Reading "VA_sky130_fd_sc_hd__a21bo_1".
+Reading "VA_sky130_fd_sc_hd__a2bb2o_1".
+Reading "VA_sky130_fd_sc_hd__o22a_1".
+Reading "VA_sky130_fd_sc_hd__a211o_1".
+Reading "VA_sky130_fd_sc_hd__a22oi_1".
+Reading "VA_sky130_fd_sc_hd__a22o_1".
+Reading "VA_sky130_fd_sc_hd__and4bb_2".
+Reading "VA_sky130_fd_sc_hd__or2_4".
+Reading "VA_sky130_fd_sc_hd__or4b_1".
+Reading "VA_sky130_fd_sc_hd__buf_8".
+Reading "VA_sky130_fd_sc_hd__mux2_2".
+Reading "VA_sky130_fd_sc_hd__and2_4".
+Reading "VA_sky130_fd_sc_hd__a32o_1".
+Reading "VA_sky130_fd_sc_hd__and2b_1".
+Reading "VA_sky130_fd_sc_hd__a22o_4".
+Reading "VA_sky130_fd_sc_hd__or3_1".
+Reading "VA_sky130_fd_sc_hd__buf_12".
+Reading "VA_sky130_fd_sc_hd__o221a_1".
+Reading "VA_sky130_fd_sc_hd__xor2_2".
+Reading "VA_sky130_fd_sc_hd__nand3_1".
+Reading "VA_sky130_fd_sc_hd__or4b_4".
+Reading "VA_sky130_fd_sc_hd__o211ai_4".
+Reading "VA_sky130_fd_sc_hd__mux4_1".
+Reading "VA_sky130_fd_sc_hd__or3b_1".
+Reading "VA_sky130_fd_sc_hd__mux4_2".
+Reading "VA_sky130_fd_sc_hd__or2b_4".
+Reading "VA_sky130_fd_sc_hd__buf_4".
+Reading "VA_sky130_fd_sc_hd__nor2_4".
+Reading "VA_sky130_fd_sc_hd__nand2_8".
+Reading "VA_sky130_fd_sc_hd__or4_1".
+Reading "VA_sky130_fd_sc_hd__clkbuf_8".
+Reading "VA_sky130_fd_sc_hd__buf_6".
+Reading "VA_sky130_fd_sc_hd__a221o_4".
+Reading "VA_sky130_fd_sc_hd__mux2_8".
+Reading "VA_sky130_fd_sc_hd__a22oi_4".
+Reading "VA_sky130_fd_sc_hd__a221oi_4".
+Reading "VA_sky130_fd_sc_hd__a21o_4".
+Reading "VA_sky130_fd_sc_hd__o221ai_4".
+Reading "VA_sky130_fd_sc_hd__a41o_4".
+Reading "VA_sky130_fd_sc_hd__a211o_4".
+Reading "VA_sky130_fd_sc_hd__o31a_1".
+Reading "VA_sky130_fd_sc_hd__nor4_4".
+Reading "VA_sky130_fd_sc_hd__or4_4".
+Reading "VA_sky130_fd_sc_hd__o211ai_1".
+Reading "VA_sky130_fd_sc_hd__o221a_4".
+Reading "VA_sky130_fd_sc_hd__o31a_4".
+Reading "VA_sky130_fd_sc_hd__o311a_1".
+Reading "VA_sky130_fd_sc_hd__nand4_1".
+Reading "VA_sky130_fd_sc_hd__o211ai_2".
+Reading "VA_sky130_fd_sc_hd__nand4b_1".
+Reading "VA_sky130_fd_sc_hd__and4_1".
+Reading "VA_sky130_fd_sc_hd__or3_4".
+Reading "VA_sky130_fd_sc_hd__and4_4".
+Reading "VA_sky130_fd_sc_hd__o31ai_1".
+Reading "VA_sky130_fd_sc_hd__or4bb_1".
+Reading "VA_sky130_fd_sc_hd__o21ba_1".
+Reading "VA_sky130_fd_sc_hd__and4b_2".
+Reading "VA_sky130_fd_sc_hd__a221oi_1".
+Reading "VA_sky130_fd_sc_hd__nand4_4".
+Reading "VA_sky130_fd_sc_hd__and4b_4".
+Reading "VA_sky130_fd_sc_hd__and4bb_4".
+Reading "VA_sky130_fd_sc_hd__nand2_4".
+Reading "VA_sky130_fd_sc_hd__or4bb_4".
+Reading "VA_sky130_fd_sc_hd__and4b_1".
+Reading "VA_sky130_fd_sc_hd__a32o_4".
+Reading "VA_sky130_fd_sc_hd__dlygate4sd1_1".
+Reading "VA_sky130_fd_sc_hd__o32a_1".
+Reading "VA_sky130_fd_sc_hd__nor4b_4".
+Reading "VA_sky130_fd_sc_hd__nor3_4".
+Reading "VA_sky130_fd_sc_hd__o31ai_4".
+Reading "VA_sky130_fd_sc_hd__and3b_4".
+Reading "VA_sky130_fd_sc_hd__and3_4".
+Reading "VA_sky130_fd_sc_hd__o31ai_2".
+Reading "VA_sky130_fd_sc_hd__a211oi_4".
+Reading "VA_sky130_fd_sc_hd__o22a_4".
+Reading "VA_sky130_fd_sc_hd__nor4_2".
+Reading "VA_sky130_fd_sc_hd__a41o_2".
+Reading "VA_sky130_fd_sc_hd__inv_6".
+Reading "VA_sky130_fd_sc_hd__nand3_4".
+Reading "VA_sky130_fd_sc_hd__o2bb2ai_1".
+Reading "VA_sky130_fd_sc_hd__clkinv_4".
+Reading "VA_sky130_fd_sc_hd__a2111o_4".
+Reading "VA_sky130_fd_sc_hd__and2b_4".
+Reading "VA_sky130_fd_sc_hd__a2bb2o_4".
+Reading "VA_sky130_fd_sc_hd__o21a_4".
+Reading "VA_sky130_fd_sc_hd__o211a_4".
+Reading "VA_sky130_fd_sc_hd__a21oi_4".
+Reading "VA_sky130_fd_sc_hd__o311a_4".
+Reading "VA_sky130_fd_sc_hd__a211o_2".
+Reading "VA_sky130_fd_sc_hd__a32oi_4".
+Reading "VA_sky130_fd_sc_hd__and3b_2".
+Reading "VA_sky130_fd_sc_hd__and3b_1".
+Reading "VA_sky130_fd_sc_hd__nor4_1".
+Reading "VA_sky130_fd_sc_hd__and4bb_1".
+Reading "VA_sky130_fd_sc_hd__a211oi_1".
+Reading "VA_sky130_fd_sc_hd__mux2_4".
+Reading "VA_sky130_fd_sc_hd__nor3_2".
+Reading "VA_sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "VA_sky130_fd_sc_hd__or4b_2".
+Reading "VA_ycr4_iconnect".
+Reading "VA_sky130_fd_sc_hd__o21a_2".
+Reading "VA_sky130_fd_sc_hd__a32o_2".
+Reading "VA_sky130_fd_sc_hd__o22ai_2".
+Reading "VA_sky130_fd_sc_hd__a311o_2".
+Reading "VA_sky130_fd_sc_hd__a41o_1".
+Reading "VA_sky130_fd_sc_hd__o21bai_2".
+Reading "VA_sky130_fd_sc_hd__nor3_1".
+Reading "VA_sky130_fd_sc_hd__a21boi_1".
+Reading "VA_sky130_fd_sc_hd__xnor2_2".
+Reading "VA_sky130_fd_sc_hd__a2111o_2".
+Reading "VA_sky130_fd_sc_hd__o21bai_1".
+Reading "VA_sky130_fd_sc_hd__o2111a_1".
+Reading "VA_sky130_fd_sc_hd__a31oi_4".
+Reading "VA_sky130_fd_sc_hd__a2111oi_4".
+Reading "VA_sky130_fd_sc_hd__nand4_2".
+Reading "VA_sky130_fd_sc_hd__o22ai_1".
+Reading "VA_sky130_fd_sc_hd__a31oi_1".
+Reading "VA_sky130_fd_sc_hd__a311oi_1".
+Reading "VA_sky130_fd_sc_hd__or2b_2".
+Reading "VA_sky130_fd_sc_hd__xnor2_4".
+Reading "VA_sky130_fd_sc_hd__or3b_2".
+Reading "VA_sky130_fd_sc_hd__o41a_1".
+Reading "VA_sky130_fd_sc_hd__nor3b_2".
+Reading "VA_sky130_fd_sc_hd__nand2b_2".
+Reading "VA_sky130_fd_sc_hd__nor4b_2".
+Reading "VA_sky130_fd_sc_hd__nand3b_1".
+Reading "VA_sky130_fd_sc_hd__a211oi_2".
+Reading "VA_sky130_fd_sc_hd__o21ba_2".
+Reading "VA_sky130_fd_sc_hd__nand3b_2".
+Reading "VA_sky130_fd_sc_hd__o22ai_4".
+Reading "VA_sky130_fd_sc_hd__a2111o_1".
+Reading "VA_sky130_fd_sc_hd__a31oi_2".
+Reading "VA_sky130_fd_sc_hd__nor2b_1".
+Reading "VA_sky130_fd_sc_hd__nor3b_1".
+Reading "VA_sky130_fd_sc_hd__a2111oi_1".
+Reading "VA_sky130_fd_sc_hd__and2b_2".
+Reading "VA_sky130_fd_sc_hd__dfxtp_1".
+Reading "VA_sky130_fd_sc_hd__nor4b_1".
+Reading "VA_sky130_fd_sc_hd__a311oi_2".
+Reading "VA_sky130_fd_sc_hd__xor2_4".
+Reading "VA_sky130_fd_sc_hd__dfxtp_2".
+Reading "VA_sky130_fd_sc_hd__a21bo_4".
+Reading "VA_sky130_fd_sc_hd__or3b_4".
+Reading "VA_sky130_fd_sc_hd__or4bb_2".
+Reading "VA_sky130_fd_sc_hd__nor2_8".
+Reading "VA_sky130_fd_sc_hd__inv_4".
+Reading "VA_sky130_fd_sc_hd__o2111ai_4".
+Reading "VA_ycr_core_top".
+Reading "VA_sky130_fd_sc_hd__o221ai_2".
+Reading "VA_sky130_fd_sc_hd__o2111ai_2".
+Reading "VA_sky130_fd_sc_hd__o2bb2a_2".
+Reading "VA_sky130_fd_sc_hd__o2111ai_1".
+Reading "VA_sky130_fd_sc_hd__a2111oi_2".
+Reading "VA_sky130_fd_sc_hd__a221oi_2".
+Reading "VA_sky130_fd_sc_hd__o221ai_1".
+Reading "VA_sky130_fd_sc_hd__o21bai_4".
+Reading "VA_sky130_fd_sc_hd__o32ai_1".
+Reading "VA_sky130_fd_sc_hd__dfstp_4".
+Reading "VA_sky130_fd_sc_hd__o41a_4".
+Reading "VA_sky130_fd_sc_hd__o2bb2a_4".
+Reading "VA_sky130_fd_sc_hd__a21boi_2".
+Reading "VA_sky130_fd_sc_hd__nand2b_1".
+Reading "VA_sky130_fd_sc_hd__o2111a_2".
+Reading "VA_sky130_fd_sc_hd__clkdlybuf4s15_2".
+Reading "VA_ycr_intf".
+Reading "VA_sky130_fd_sc_hd__einvp_2".
+Reading "VA_sky130_fd_sc_hd__decap_12".
+Reading "VA_sky130_fd_sc_hd__clkinv_1".
+Reading "VA_sky130_fd_sc_hd__einvn_8".
+Reading "VA_sky130_fd_sc_hd__einvn_4".
+Reading "VA_sky130_fd_sc_hd__einvp_1".
+Reading "VA_digital_pll".
+Reading "VA_sky130_fd_sc_hd__clkdlybuf4s25_1".
+Reading "VA_sky130_fd_sc_hd__nand4b_2".
+Reading "VA_wb_host".
+Reading "VA_sky130_fd_sc_hd__a31o_4".
+Reading "VA_sky130_fd_sc_hd__nor2b_2".
+Reading "VA_sky130_fd_sc_hd__nor3b_4".
+Reading "VA_uart_i2c_usb_spi_top".
+Reading "VA_sky130_fd_sc_hd__a41oi_1".
+Reading "VA_sky130_fd_sc_hd__a2bb2oi_4".
+Reading "VA_wb_interconnect".
+Reading "VA_pinmux".
+Reading "VA_qspim_top".
+Reading "user_project_wrapper".
+Reading "sky130_ef_io__com_bus_slice_20um".
+Reading "sky130_fd_io__corner_bus_overlay".
+Reading "sky130_ef_io__corner_pad".
+Reading "sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um".
+Reading "sky130_ef_io__com_bus_slice_1um".
+Reading "sky130_ef_io__com_bus_slice_5um".
+Reading "sky130_ef_io__com_bus_slice_10um".
+Reading "sky130_fd_pr__hvdfl1sd__example_5595914180851".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808664".
+Reading "sky130_fd_io__sio_clamp_pcap_4x5".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808680".
+Reading "sky130_fd_io__esd_rcclamp_nfetcap".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808336".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808666".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808665".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808678".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808679".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808677".
+Reading "sky130_fd_pr__via_pol1__example_5595914180839".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808667".
+Reading "sky130_fd_pr__hvdftpl1s__example_55959141808671".
+Reading "sky130_fd_pr__hvdftpl1s2__example_55959141808672".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808673".
+Reading "sky130_fd_pr__dfl1__example_55959141808663".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808660".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808670".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808668".
+Reading "sky130_fd_pr__hvdftpl1s__example_55959141808675".
+Reading "sky130_fd_pr__hvdftpl1s2__example_55959141808676".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808674".
+Reading "sky130_fd_pr__dfl1__example_55959141808662".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808661".
+Reading "sky130_fd_pr__via_l1m1__example_559591418084".
+Reading "sky130_fd_pr__genrivetdlring__example_559591418082".
+Reading "sky130_fd_pr__gendlring__example_559591418081".
+Reading "sky130_fd_pr__padplhp__example_559591418080".
+Reading "sky130_fd_io__pad_esd".
+Reading "sky130_fd_io__com_bus_slice".
+Reading "sky130_fd_io__com_bus_hookup".
+Reading "sky130_fd_io__com_busses_esd".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808669".
+Reading "sky130_fd_io__top_ground_hvc_wpad".
+Reading "sky130_fd_io__overlay_vssa_hvc".
+Reading "sky130_ef_io__hvc_vdda_overlay".
+Reading "sky130_ef_io__vssa_hvc_clamped_pad".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808719".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808767".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808765".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808764".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808720".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808718".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808717".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808716".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808243".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808723".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808722".
+Reading "sky130_fd_pr__hvdfm1sd2__example_5595914180890".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808721".
+Reading "sky130_fd_io__xres_inv_hysv2".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180838".
+Reading "sky130_fd_io__tk_tie_r_out_esd".
+Reading "sky130_fd_io__res250_sub_small".
+Reading "sky130_fd_io__res250only_small".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808264".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180858".
+Reading "sky130_fd_pr__via_pol1__example_5595914180833".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180864".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808715".
+Reading "sky130_fd_pr__res_bent_po__example_5595914180863".
+Reading "sky130_fd_pr__res_bent_po__example_5595914180862".
+Reading "sky130_fd_io__tk_em1s_cdns_55959141808288".
+Reading "sky130_fd_io__tk_em1s_cdns_5595914180859".
+Reading "sky130_fd_io__tk_em1o_cdns_55959141808289".
+Reading "sky130_fd_io__com_res_weak_v2".
+Reading "sky130_fd_pr__via_pol1__example_55959141808274".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808728".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808727".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808726".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808725".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808724".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808554".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808553".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808552".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808551".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808402".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808350".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808261".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808260".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808259".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808400".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808372".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808326".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808290".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808128".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808127".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180897".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180819".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808555".
+Reading "sky130_fd_pr__via_pol1__example_55959141808147".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808157".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808156".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808155".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808154".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808153".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808152".
+Reading "sky130_fd_pr__tpl1__example_55959141808151".
+Reading "sky130_fd_pr__tpl1__example_55959141808150".
+Reading "sky130_fd_pr__tpl1__example_55959141808149".
+Reading "sky130_fd_pr__tpl1__example_55959141808148".
+Reading "sky130_fd_pr__dfl1__example_55959141808158".
+Reading "sky130_fd_io__signal_5_sym_hv_local_5term".
+Reading "sky130_fd_io__gpio_buf_localesdv2".
+Reading "sky130_fd_pr__via_pol1__example_559591418083".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808137".
+Reading "sky130_fd_pr__dfl1sd__example_559591418086".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808371".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808370".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808369".
+Reading "sky130_fd_io__hvsbt_inv_x1".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808316".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808421".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808385".
+Reading "sky130_fd_pr__dfl1sd__example_559591418088".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808422".
+Reading "sky130_fd_io__hvsbt_inv_x2".
+Reading "sky130_fd_pr__via_pol1__example_55959141808612".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808616".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808615".
+Reading "sky130_fd_io__hvsbt_inv_x4".
+Reading "sky130_fd_pr__hvdfm1sd__example_5595914180848".
+Reading "sky130_fd_pr__hvdfm1sd2__example_5595914180849".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808766".
+Reading "sky130_fd_pr__via_m2m3__example_55959141808714".
+Reading "sky130_fd_pr__via_pol1_centered__example_559591418081".
+Reading "sky130_fd_io__tk_em2s_cdns_55959141808652".
+Reading "sky130_fd_io__tk_em2o_cdns_55959141808653".
+Reading "sky130_fd_pr__via_l1m1_centered__example_5595914180812".
+Reading "sky130_fd_pr__via_l1m1_centered__example_5595914180811".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418086".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418084".
+Reading "sky130_fd_pr__hvdftpm1s2__example_55959141808659".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808658".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808657".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808202".
+Reading "sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2".
+Reading "sky130_fd_io__gpio_pudrvr_strong_axres4v2".
+Reading "sky130_fd_pr__via_pol1__example_55959141808273".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808740".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808739".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808738".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808737".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808736".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808735".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808734".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808733".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808732".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808731".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808730".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808752".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808751".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808750".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808749".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808748".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808747".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808746".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808745".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808744".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808743".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808742".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808741".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808324".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808270".
+Reading "sky130_fd_pr__dfl1__example_55959141808187".
+Reading "sky130_fd_pr__res_generic_nd__example_55959141808755".
+Reading "sky130_fd_pr__res_generic_nd__example_55959141808754".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808338".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808337".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808763".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808700".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808559".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808762".
+Reading "sky130_fd_pr__dfl1__example_55959141808729".
+Reading "sky130_fd_io__xres_tk_p_em1o_cdns_55959141808758".
+Reading "sky130_fd_io__xres_tk_p_em1o_cdns_55959141808757".
+Reading "sky130_fd_io__xres_tk_p_em1o_cdns_55959141808756".
+Reading "sky130_fd_io__xres_tk_p_em1c_cdns_55959141808761".
+Reading "sky130_fd_io__xres_tk_p_em1c_cdns_55959141808760".
+Reading "sky130_fd_io__xres_tk_p_em1c_cdns_55959141808759".
+Reading "sky130_fd_io__xres_p_em1c_cdns_55959141808753".
+Reading "sky130_fd_io__xres2v2_rcfilter_lpfv2".
+Reading "sky130_fd_io__tk_em1o_cdns_5595914180860".
+Reading "sky130_fd_pr__res_bent_po__example_5595914180861".
+Reading "sky130_fd_io__com_res_weak_bentbigres".
+Reading "sky130_fd_io__com_res_weak".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180857".
+Reading "sky130_fd_pr__hvdftpm1s2__example_55959141808649".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808651".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808650".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808648".
+Reading "sky130_fd_pr__hvdftpl1s__example_55959141808646".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808647".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808645".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808378".
+Reading "sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2".
+Reading "sky130_fd_io__gpio_pddrvr_strong_xres4v2".
+Reading "sky130_fd_io__top_gpio_pad".
+Reading "sky130_fd_io__com_busses".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808768".
+Reading "sky130_fd_pr__res_bent_nd__example_55959141808769".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808787".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808786".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808782".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808785".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808449".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808784".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808452".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808783".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808781".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808780".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808779".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808233".
+Reading "sky130_fd_pr__hvdfm1sd2__example_5595914180827".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808778".
+Reading "sky130_fd_pr__hvdfm1sd__example_5595914180835".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808777".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808776".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808775".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808242".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808774".
+Reading "sky130_fd_pr__hvdfm1sd2__example_5595914180829".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808773".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808237".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808772".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808771".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808770".
+Reading "sky130_fd_io__tap_1".
+Reading "sky130_fd_io__inv_1".
+Reading "sky130_fd_pr__pfet_01v8__example_559591418085".
+Reading "sky130_fd_pr__nfet_01v8__example_559591418089".
+Reading "sky130_fd_pr__nfet_01v8__example_559591418087".
+Reading "sky130_fd_io__hvsbt_nand2".
+Reading "sky130_fd_io__xres4v2_in_buf".
+Reading "sky130_fd_io__top_xres4v2".
+Reading "sky130_fd_sc_hd__fill_4".
+Reading "sky130_fd_sc_hd__fill_8".
+Reading "constant_block".
+Reading "sky130_fd_io__res75only_small".
+Reading "sky130_fd_io__com_bus_slice_m4".
+Reading "sky130_fd_io__overlay_gpiov2_m4".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808420".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808419".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808418".
+Reading "sky130_fd_io__hvsbt_nor".
+Reading "sky130_fd_io__hvsbt_nand2v2".
+Reading "sky130_fd_io__gpiov2_ictl_logic".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808190".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808611".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180811".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808549".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808548".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808191".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808189".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808517".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808518".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808610".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808609".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180815".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180816".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808608".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808604".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808533".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808529".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180884".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808230".
+Reading "sky130_fd_io__gpiov2_in_buf".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808537".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808106".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808481".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808607".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808504".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808600".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808550".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808528".
+Reading "sky130_fd_io__gpiov2_ipath_hvls".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808595".
+Reading "sky130_fd_pr__nfet_01v8__example_5595914180825".
+Reading "sky130_fd_io__gpiov2_inbuf_lvinv_x1".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180812".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808599".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808598".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808597".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808596".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808547".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808546".
+Reading "sky130_fd_io__gpiov2_ipath_lvls".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808606".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180875".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808605".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808540".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808603".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808602".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808601".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808535".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808527".
+Reading "sky130_fd_io__gpiov2_vcchib_in_buf".
+Reading "sky130_fd_io__gpiov2_ibuf_se".
+Reading "sky130_fd_io__gpiov2_buf_localesd".
+Reading "sky130_fd_io__gpiov2_ipath".
+Reading "sky130_fd_io__tk_em2s_cdns_55959141808438".
+Reading "sky130_fd_io__tk_em2o_cdns_55959141808439".
+Reading "sky130_fd_io__tk_em1s_cdns_5595914180882".
+Reading "sky130_fd_io__tk_em1s_cdns_5595914180881".
+Reading "sky130_fd_io__tk_em1o_cdns_5595914180880".
+Reading "sky130_fd_io__tk_em1o_cdns_5595914180879".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808430".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180823".
+Reading "sky130_fd_pr__pfet_01v8__example_5595914180822".
+Reading "sky130_fd_pr__pfet_01v8__example_5595914180813".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808624".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808510".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808623".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808622".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808621".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808620".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808619".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808618".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808116".
+Reading "sky130_fd_io__com_ctl_lsv2".
+Reading "sky130_fd_pr__via_pol1__example_55959141808394".
+Reading "sky130_fd_pr__via_pol1__example_55959141808298".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808440".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180878".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808434".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808435".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808433".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808432".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808102".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808431".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808115".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808429".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808428".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808100".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808140".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808427".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808426".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808280".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808425".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808424".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808423".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808306".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808383".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808382".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808380".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808379".
+Reading "sky130_fd_io__com_ctl_ls_v2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808617".
+Reading "sky130_fd_io__com_ctl_ls_en_1_v2".
+Reading "sky130_fd_io__com_ctl_ls_1v2".
+Reading "sky130_fd_io__gpiov2_ctl_lsbank".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808614".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808613".
+Reading "sky130_fd_io__hvsbt_inv_x8v2".
+Reading "sky130_fd_io__hvsbt_inv_x8".
+Reading "sky130_fd_io__com_ctl_ls".
+Reading "sky130_fd_io__com_ctl_hldv2".
+Reading "sky130_fd_io__gpiov2_ctl".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808178".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808591".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808594".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808593".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808488".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808592".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808586".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808122".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808123".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808477".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808476".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808475".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808589".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808570".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808569".
+Reading "sky130_fd_io__gpiov2_amux_ctl_lshv2hv".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808588".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808587".
+Reading "sky130_fd_io__gpiov2_amux_ctl_lshv2hv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808590".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808460".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808468".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808467".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808466".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808465".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808464".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808463".
+Reading "sky130_fd_io__gpiov2_amux_ctl_ls".
+Reading "sky130_fd_io__gpiov2_amux_ctl_inv_1".
+Reading "sky130_fd_io__gpiov2_amux_ls".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808573".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808572".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808579".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808578".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808577".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808576".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808566".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180868".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180869".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808565".
+Reading "sky130_fd_io__gpiov2_amx_pucsd_inv".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808441".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808571".
+Reading "sky130_fd_io__gpiov2_amx_inv4".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808567".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808568".
+Reading "sky130_fd_io__gpiov2_amux_drvr_lshv2hv".
+Reading "sky130_fd_io__gpiov2_amux_drvr_lshv2hv2".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808581".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808580".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808278".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808462".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808583".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808582".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808498".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808497".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808496".
+Reading "sky130_fd_io__gpiov2_amux_drvr_ls".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808574".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808575".
+Reading "sky130_fd_io__amx_inv1".
+Reading "sky130_fd_io__gpiov2_amux_drvr".
+Reading "sky130_fd_io__xor2_1".
+Reading "sky130_fd_io__nor2_1".
+Reading "sky130_fd_io__nand2_1".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808200".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808457".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808451".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808450".
+Reading "sky130_fd_pr__hvdfl1sd__example_5595914180894".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808584".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808455".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808447".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808445".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808248".
+Reading "sky130_fd_io__gpiov2_amux_nand5".
+Reading "sky130_fd_pr__dfm1sd__example_55959141808258".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808585".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808446".
+Reading "sky130_fd_io__gpiov2_amux_nand4".
+Reading "sky130_fd_io__gpiov2_amux_decoder".
+Reading "sky130_fd_io__gpiov2_amux_ctl_logic".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808563".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808564".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808562".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808251".
+Reading "sky130_fd_pr__dfm1sd2__example_55959141808561".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808560".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808558".
+Reading "sky130_fd_io__amux_switch_1v2b".
+Reading "sky130_fd_io__gpiov2_amux".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808416".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808417".
+Reading "sky130_fd_io__hvsbt_xorv2".
+Reading "sky130_fd_io__hvsbt_xor".
+Reading "sky130_fd_io__com_ctl_ls_octl".
+Reading "sky130_fd_io__gpiov2_octl".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808267".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808266".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808642".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808184".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808141".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808643".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808183".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808139".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808636".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808635".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808634".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808633".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808632".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808630".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808638".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808637".
+Reading "sky130_fd_io__gpiov2_pdpredrvr_strong_nr3".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808629".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808628".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808627".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808626".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808354".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808631".
+Reading "sky130_fd_io__gpiov2_pdpredrvr_strong_nr2".
+Reading "sky130_fd_pr__nfet_01v8__example_5595914180888".
+Reading "sky130_fd_io__gpiov2_octl_mux".
+Reading "sky130_fd_pr__via_pol1__example_55959141808322".
+Reading "sky130_fd_pr__via_pol1__example_55959141808321".
+Reading "sky130_fd_pr__via_pol1__example_55959141808320".
+Reading "sky130_fd_pr__via_pol1__example_55959141808294".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808325".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808323".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808291".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808641".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808640".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808639".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808348".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808347".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808194".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808346".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808345".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808344".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808343".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808334".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808333".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808332".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808331".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808330".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808329".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808304".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808134".
+Reading "sky130_fd_io__tk_em1o_cdns_55959141808328".
+Reading "sky130_fd_io__tk_em1o_cdns_55959141808327".
+Reading "sky130_fd_io__com_pdpredrvr_pbiasv2".
+Reading "sky130_fd_io__gpiov2_pdpredrvr_strong".
+Reading "sky130_fd_pr__via_pol1__example_55959141808272".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808271".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808143".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808142".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808101".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808144".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_5595914180899".
+Reading "sky130_fd_pr__via_pol1__example_55959141808275".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808276".
+Reading "sky130_fd_pr__res_generic_po__example_55959141808286".
+Reading "sky130_fd_pr__res_generic_po__example_55959141808285".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808284".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808283".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808644".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808287".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808282".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808281".
+Reading "sky130_fd_io__gpiov2_pupredrvr_strong_nd2_a".
+Reading "sky130_fd_io__gpiov2_pupredrvr_strong_nd2".
+Reading "sky130_fd_pr__via_pol1__example_55959141808297".
+Reading "sky130_fd_pr__via_pol1__example_55959141808296".
+Reading "sky130_fd_pr__via_pol1__example_55959141808295".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808293".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808292".
+Reading "sky130_fd_pr__tpl1__example_55959141808300".
+Reading "sky130_fd_pr__tpl1__example_55959141808299".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808319".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808318".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808317".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808315".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808314".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808313".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808312".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808311".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808310".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808309".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808308".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808307".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808305".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808303".
+Reading "sky130_fd_io__tk_em1s_cdns_55959141808301".
+Reading "sky130_fd_io__tk_em1o_cdns_55959141808302".
+Reading "sky130_fd_io__feascom_pupredrvr_nbiasv2".
+Reading "sky130_fd_io__gpio_pupredrvr_strongv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808361".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808360".
+Reading "sky130_fd_io__feas_com_pupredrvr_weak".
+Reading "sky130_fd_pr__via_pol1__example_5595914180854".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808363".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808362".
+Reading "sky130_fd_io__com_pupredrvr_strong_slowv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808366".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808365".
+Reading "sky130_fd_io__com_pdpredrvr_weakv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808364".
+Reading "sky130_fd_io__com_pdpredrvr_strong_slowv2".
+Reading "sky130_fd_io__gpiov2_obpredrvr".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808368".
+Reading "sky130_fd_pr__tpl1__example_55959141808625".
+Reading "sky130_fd_pr__via_pol1__example_55959141808373".
+Reading "sky130_fd_pr__tpl1__example_55959141808374".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808393".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808392".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808391".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808390".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808389".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808388".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808387".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808386".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808384".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808381".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808377".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808376".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808375".
+Reading "sky130_fd_io__gpio_dat_lsv2".
+Reading "sky130_fd_io__gpio_dat_ls_1v2".
+Reading "sky130_fd_pr__via_pol1__example_55959141808398".
+Reading "sky130_fd_pr__via_pol1__example_55959141808397".
+Reading "sky130_fd_pr__via_pol1__example_55959141808396".
+Reading "sky130_fd_pr__via_pol1__example_55959141808395".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808401".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808399".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808269".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808410".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808409".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808408".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808407".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808406".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808405".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808404".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808403".
+Reading "sky130_fd_io__com_cclat".
+Reading "sky130_fd_io__com_opath_datoev2".
+Reading "sky130_fd_io__gpiov2_octl_dat".
+Reading "sky130_fd_pr__via_pol1_centered__example_559591418080".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180832".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180856".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180855".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180853".
+Reading "sky130_fd_io__tk_em1s_cdns_5595914180852".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418083".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418082".
+Reading "sky130_fd_io__nfet_con_diff_wo_abt_270v2".
+Reading "sky130_fd_io__gpiov2_pddrvr_strong".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418085".
+Reading "sky130_fd_io__pfet_con_diff_wo_abt_270v2".
+Reading "sky130_fd_io__gpio_pudrvr_strongv2".
+Reading "sky130_fd_pr__nfet_01v8__example_5595914180850".
+Reading "sky130_fd_io__gpio_pddrvr_weakv2".
+Reading "sky130_fd_io__gpio_pddrvr_strong_slowv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808656".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808655".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808654".
+Reading "sky130_fd_io__com_pudrvr_weakv2".
+Reading "sky130_fd_io__com_pudrvr_strong_slowv2".
+Reading "sky130_fd_io__gpio_odrvr_subv2".
+Reading "sky130_fd_io__gpio_odrvrv2".
+Reading "sky130_fd_io__gpio_opathv2".
+Reading "sky130_fd_io__top_gpiov2".
+Reading "sky130_fd_io__overlay_gpiov2".
+Reading "sky130_ef_io__gpiov2_pad".
+Reading "sky130_ef_io__gpiov2_pad_wrapped".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808691".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808687".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808684".
+Reading "sky130_fd_pr__tpl1__example_55959141808686".
+Reading "sky130_fd_pr__tpl1__example_55959141808685".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808683".
+Reading "sky130_fd_io__gnd2gnd_strap".
+Reading "sky130_fd_io__gnd2gnd_tap".
+Reading "sky130_fd_io__gnd2gnd_diff".
+Reading "sky130_fd_io__gnd2gnd_sub_dnwl".
+Reading "sky130_fd_io__gnd2gnd_120x2_lv_isosub".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808690".
+Reading "sky130_fd_pr__dftpl1s2__example_55959141808702".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808705".
+Reading "sky130_fd_pr__dfl1__example_55959141808682".
+Reading "sky130_fd_pr__dftpl1s2__example_55959141808694".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808693".
+Reading "sky130_fd_pr__dfl1__example_55959141808681".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808688".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808699".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808698".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808697".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808696".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808695".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808704".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808703".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808701".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808689".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808692".
+Reading "sky130_fd_io__top_ground_lvc_wpad".
+Reading "sky130_fd_io__overlay_vssd_lvc".
+Reading "sky130_ef_io__lvc_vccdx_overlay".
+Reading "sky130_ef_io__vssd_lvc_clamped_pad".
+Reading "sky130_fd_io__overlay_vssio_hvc".
+Reading "sky130_ef_io__hvc_vssio_overlay".
+Reading "sky130_ef_io__vssio_hvc_clamped_pad".
+Reading "sky130_fd_io__hvc_clampv2".
+Reading "sky130_fd_io__top_power_hvc_wpadv2".
+Reading "sky130_fd_io__overlay_vdda_hvc".
+Reading "sky130_ef_io__vdda_hvc_clamped_pad".
+Reading "sky130_fd_io__top_power_lvc_wpad".
+Reading "sky130_fd_io__overlay_vccd_lvc".
+Reading "sky130_ef_io__vccd_lvc_clamped_pad".
+Reading "sky130_ef_io__disconnect_vdda_slice_5um".
+Reading "sky130_fd_io__overlay_vddio_hvc".
+Reading "sky130_ef_io__hvc_vddio_overlay".
+Reading "sky130_ef_io__vddio_hvc_clamped_pad".
+Reading "chip_io_gpio_connects".
+Reading "sky130_ef_io__lvc_vccdy_overlay".
+Reading "sky130_ef_io__vssd_lvc_clamped3_pad".
+Reading "sky130_ef_io__vccd_lvc_clamped3_pad".
+Reading "chip_io".
+Reading "gpio_signal_buffering".
+Reading "caravel".
+ Generating output for cell caravel_00069f13
+Ended: 11/15/2022 21:53:14
diff --git a/tapeout/logs/fill_final.log b/tapeout/logs/fill_final.log
new file mode 100644
index 0000000..bf98868
--- /dev/null
+++ b/tapeout/logs/fill_final.log
@@ -0,0 +1,115 @@
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_final.tcl" from command line.
+CIF output style is now "wafflefill(tiled)"
+Scaled magic input cell caravel_00069f13_fill_pattern_3_6 geometry by factor of 2
+Writing final GDS
+ Generating output for cell caravel_00069f13_fill_pattern_0_0
+Reading "caravel_00069f13_fill_pattern_0_0".
+ Generating output for cell caravel_00069f13_fill_pattern_1_0
+Reading "caravel_00069f13_fill_pattern_1_0".
+ Generating output for cell caravel_00069f13_fill_pattern_0_1
+Reading "caravel_00069f13_fill_pattern_0_1".
+ Generating output for cell caravel_00069f13_fill_pattern_1_1
+Reading "caravel_00069f13_fill_pattern_1_1".
+ Generating output for cell caravel_00069f13_fill_pattern_2_0
+Reading "caravel_00069f13_fill_pattern_2_0".
+ Generating output for cell caravel_00069f13_fill_pattern_2_1
+Reading "caravel_00069f13_fill_pattern_2_1".
+ Generating output for cell caravel_00069f13_fill_pattern_3_0
+Reading "caravel_00069f13_fill_pattern_3_0".
+ Generating output for cell caravel_00069f13_fill_pattern_3_1
+Reading "caravel_00069f13_fill_pattern_3_1".
+ Generating output for cell caravel_00069f13_fill_pattern_4_0
+Reading "caravel_00069f13_fill_pattern_4_0".
+ Generating output for cell caravel_00069f13_fill_pattern_4_1
+Reading "caravel_00069f13_fill_pattern_4_1".
+ Generating output for cell caravel_00069f13_fill_pattern_5_0
+Reading "caravel_00069f13_fill_pattern_5_0".
+ Generating output for cell caravel_00069f13_fill_pattern_5_1
+Reading "caravel_00069f13_fill_pattern_5_1".
+ Generating output for cell caravel_00069f13_fill_pattern_0_2
+Reading "caravel_00069f13_fill_pattern_0_2".
+ Generating output for cell caravel_00069f13_fill_pattern_1_2
+Reading "caravel_00069f13_fill_pattern_1_2".
+ Generating output for cell caravel_00069f13_fill_pattern_2_2
+Reading "caravel_00069f13_fill_pattern_2_2".
+ Generating output for cell caravel_00069f13_fill_pattern_3_2
+Reading "caravel_00069f13_fill_pattern_3_2".
+ Generating output for cell caravel_00069f13_fill_pattern_4_2
+Reading "caravel_00069f13_fill_pattern_4_2".
+ Generating output for cell caravel_00069f13_fill_pattern_5_2
+Reading "caravel_00069f13_fill_pattern_5_2".
+ Generating output for cell caravel_00069f13_fill_pattern_0_3
+Reading "caravel_00069f13_fill_pattern_0_3".
+ Generating output for cell caravel_00069f13_fill_pattern_1_3
+Reading "caravel_00069f13_fill_pattern_1_3".
+ Generating output for cell caravel_00069f13_fill_pattern_2_3
+Reading "caravel_00069f13_fill_pattern_2_3".
+ Generating output for cell caravel_00069f13_fill_pattern_3_3
+Reading "caravel_00069f13_fill_pattern_3_3".
+ Generating output for cell caravel_00069f13_fill_pattern_4_3
+Reading "caravel_00069f13_fill_pattern_4_3".
+ Generating output for cell caravel_00069f13_fill_pattern_5_3
+Reading "caravel_00069f13_fill_pattern_5_3".
+ Generating output for cell caravel_00069f13_fill_pattern_0_4
+Reading "caravel_00069f13_fill_pattern_0_4".
+ Generating output for cell caravel_00069f13_fill_pattern_1_4
+Reading "caravel_00069f13_fill_pattern_1_4".
+ Generating output for cell caravel_00069f13_fill_pattern_2_4
+Reading "caravel_00069f13_fill_pattern_2_4".
+ Generating output for cell caravel_00069f13_fill_pattern_3_4
+Reading "caravel_00069f13_fill_pattern_3_4".
+ Generating output for cell caravel_00069f13_fill_pattern_4_4
+Reading "caravel_00069f13_fill_pattern_4_4".
+ Generating output for cell caravel_00069f13_fill_pattern_5_4
+Reading "caravel_00069f13_fill_pattern_5_4".
+ Generating output for cell caravel_00069f13_fill_pattern_0_5
+Reading "caravel_00069f13_fill_pattern_0_5".
+ Generating output for cell caravel_00069f13_fill_pattern_1_5
+Reading "caravel_00069f13_fill_pattern_1_5".
+ Generating output for cell caravel_00069f13_fill_pattern_2_5
+Reading "caravel_00069f13_fill_pattern_2_5".
+ Generating output for cell caravel_00069f13_fill_pattern_3_5
+Reading "caravel_00069f13_fill_pattern_3_5".
+ Generating output for cell caravel_00069f13_fill_pattern_4_5
+Reading "caravel_00069f13_fill_pattern_4_5".
+ Generating output for cell caravel_00069f13_fill_pattern_5_5
+Reading "caravel_00069f13_fill_pattern_5_5".
+ Generating output for cell caravel_00069f13_fill_pattern_0_6
+Reading "caravel_00069f13_fill_pattern_0_6".
+ Generating output for cell caravel_00069f13_fill_pattern_1_6
+Reading "caravel_00069f13_fill_pattern_1_6".
+ Generating output for cell caravel_00069f13_fill_pattern_2_6
+Reading "caravel_00069f13_fill_pattern_2_6".
+ Generating output for cell caravel_00069f13_fill_pattern_3_6
+Reading "caravel_00069f13_fill_pattern_3_6".
+ Generating output for cell caravel_00069f13_fill_pattern_4_6
+Reading "caravel_00069f13_fill_pattern_4_6".
+ Generating output for cell caravel_00069f13_fill_pattern_5_6
+Reading "caravel_00069f13_fill_pattern_5_6".
+ Generating output for cell caravel_00069f13_fill_pattern_0_7
+Reading "caravel_00069f13_fill_pattern_0_7".
+ Generating output for cell caravel_00069f13_fill_pattern_1_7
+Reading "caravel_00069f13_fill_pattern_1_7".
+ Generating output for cell caravel_00069f13_fill_pattern_2_7
+Reading "caravel_00069f13_fill_pattern_2_7".
+ Generating output for cell caravel_00069f13_fill_pattern_3_7
+Reading "caravel_00069f13_fill_pattern_3_7".
+ Generating output for cell caravel_00069f13_fill_pattern_4_7
+Reading "caravel_00069f13_fill_pattern_4_7".
+ Generating output for cell caravel_00069f13_fill_pattern_5_7
+Reading "caravel_00069f13_fill_pattern_5_7".
+ Generating output for cell caravel_00069f13_fill_pattern
+Ended: 11/15/2022 21:52:05
diff --git a/tapeout/logs/fill_initial.log b/tapeout/logs/fill_initial.log
new file mode 100644
index 0000000..d461696
--- /dev/null
+++ b/tapeout/logs/fill_initial.log
@@ -0,0 +1,1852 @@
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill.tcl" from command line.
+Started: 11/15/2022 21:01:30
+Warning: Calma reading is not undoable! I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: caravel
+Reading "caravel_logo".
+Reading "font_22".
+Reading "font_73".
+Reading "font_43".
+Reading "font_49".
+Reading "font_65".
+Reading "font_68".
+Reading "font_54".
+Reading "font_67".
+Reading "font_6E".
+Reading "font_69".
+Reading "font_6C".
+Reading "font_61".
+Reading "font_53".
+Reading "caravel_motto".
+Reading "font_79".
+Reading "font_76".
+Reading "font_74".
+Reading "font_72".
+Reading "font_70".
+Reading "font_66".
+Reading "font_63".
+Reading "font_62".
+Reading "font_57".
+Reading "font_56".
+Reading "font_50".
+Reading "font_47".
+Reading "font_44".
+Reading "font_35".
+Reading "font_32".
+Reading "font_30".
+Reading "font_29".
+Reading "font_28".
+Reading "font_20".
+Reading "font_6F".
+Reading "font_6B".
+Reading "font_4F".
+Reading "font_4B".
+Reading "font_2D".
+Reading "copyright_block".
+Reading "open_source".
+Reading "sky130_fd_sc_hvl__decap_8".
+CIF file read warning: CIF style sky130(vendor): units rescaled by factor of 5 / 1
+Reading "sky130_fd_sc_hvl__decap_4".
+Reading "sky130_fd_sc_hvl__diode_2".
+Reading "sky130_fd_sc_hvl__fill_1".
+Reading "sky130_fd_sc_hvl__fill_2".
+Reading "sky130_fd_sc_hvl__lsbufhv2lv_1".
+Reading "xres_buf".
+Reading "alpha_6".
+Reading "alpha_9".
+Reading "alpha_F".
+Reading "alpha_1".
+Reading "alpha_3".
+Reading "alpha_0".
+Reading "user_id_textblock".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "gpio_defaults_block_1803".
+Reading "sky130_fd_sc_hd__o21bai_1".
+Reading "sky130_fd_sc_hd__nand3b_1".
+Reading "sky130_fd_sc_hd__nand4bb_1".
+Reading "sky130_fd_sc_hd__o2111ai_2".
+Reading "sky130_fd_sc_hd__o31ai_2".
+Reading "sky130_fd_sc_hd__o2bb2ai_1".
+Reading "sky130_fd_sc_hd__a41oi_1".
+Reading "sky130_fd_sc_hd__o211ai_4".
+Reading "sky130_fd_sc_hd__nor3b_2".
+Reading "sky130_fd_sc_hd__xnor2_1".
+Reading "sky130_fd_sc_hd__o2111ai_1".
+Reading "sky130_fd_sc_hd__nand3_1".
+Reading "sky130_fd_sc_hd__a31o_1".
+Reading "sky130_fd_sc_hd__o21a_1".
+Reading "sky130_fd_sc_hd__nand2b_1".
+Reading "sky130_fd_sc_hd__o22a_1".
+Reading "sky130_fd_sc_hd__o21ai_1".
+Reading "sky130_fd_sc_hd__a2bb2o_1".
+Reading "sky130_fd_sc_hd__nor2_1".
+Reading "sky130_fd_sc_hd__a21oi_1".
+Reading "sky130_fd_sc_hd__nor3_2".
+Reading "sky130_fd_sc_hd__nor3_1".
+Reading "sky130_fd_sc_hd__nor4_1".
+Reading "sky130_fd_sc_hd__o31ai_1".
+Reading "sky130_fd_sc_hd__a21o_1".
+Reading "sky130_fd_sc_hd__o31a_1".
+Reading "sky130_fd_sc_hd__mux2_1".
+Reading "sky130_fd_sc_hd__dfxtp_1".
+Reading "sky130_fd_sc_hd__dfstp_1".
+Reading "sky130_fd_sc_hd__dfrtp_4".
+Reading "sky130_fd_sc_hd__dfrtn_1".
+Reading "sky130_fd_sc_hd__dfstp_2".
+Reading "sky130_fd_sc_hd__dfrtp_1".
+Reading "sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "sky130_fd_sc_hd__buf_12".
+Reading "sky130_fd_sc_hd__o21a_2".
+Reading "sky130_fd_sc_hd__nand2b_2".
+Reading "sky130_fd_sc_hd__o21ai_2".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__dfrtp_2".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__clkbuf_2".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__nor2_2".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__inv_4".
+Reading "sky130_fd_sc_hd__clkinv_4".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__clkinv_2".
+Reading "sky130_fd_sc_hd__and2_1".
+Reading "sky130_fd_sc_hd__clkbuf_4".
+Reading "sky130_fd_sc_hd__nand2_1".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_ef_sc_hd__decap_12".
+Reading "caravel_clocking".
+Reading "sky130_fd_sc_hd__clkbuf_8".
+Reading "buff_flash_clkrst".
+Reading "sky130_fd_sc_hd__nand2_2".
+Reading "sky130_fd_sc_hd__macro_sparecell".
+Reading "sky130_fd_sc_hd__dfbbn_2".
+Reading "sky130_fd_sc_hd__or2_0".
+Reading "sky130_fd_sc_hd__o21ai_4".
+Reading "sky130_fd_sc_hd__and2_0".
+Reading "sky130_fd_sc_hd__mux2_4".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "sky130_fd_sc_hd__and2b_2".
+Reading "sky130_fd_sc_hd__and3b_2".
+Reading "sky130_fd_sc_hd__and2_2".
+Reading "sky130_fd_sc_hd__buf_16".
+Reading "gpio_logic_high".
+Reading "gpio_control_block".
+Reading "sky130_fd_sc_hd__dfstp_4".
+Reading "sky130_fd_sc_hd__a32o_1".
+Reading "sky130_fd_sc_hd__a22o_1".
+Reading "sky130_fd_sc_hd__a221o_1".
+Reading "sky130_fd_sc_hd__a211o_4".
+Reading "sky130_fd_sc_hd__a21bo_1".
+Reading "sky130_fd_sc_hd__o2bb2a_1".
+Reading "sky130_fd_sc_hd__a221o_2".
+Reading "sky130_fd_sc_hd__a211o_1".
+Reading "sky130_fd_sc_hd__o21ba_1".
+Reading "sky130_fd_sc_hd__and4b_1".
+Reading "sky130_fd_sc_hd__and4bb_1".
+Reading "sky130_fd_sc_hd__and4bb_2".
+Reading "sky130_fd_sc_hd__and3_4".
+Reading "sky130_fd_sc_hd__nand3_4".
+Reading "sky130_fd_sc_hd__a311o_1".
+Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__nor2_8".
+Reading "sky130_fd_sc_hd__o221a_1".
+Reading "sky130_fd_sc_hd__a2111o_1".
+Reading "sky130_fd_sc_hd__nor4_2".
+Reading "sky130_fd_sc_hd__a2111o_4".
+Reading "sky130_fd_sc_hd__nor4_4".
+Reading "sky130_fd_sc_hd__a2111o_2".
+Reading "sky130_fd_sc_hd__nand2b_4".
+Reading "sky130_fd_sc_hd__and3_1".
+Reading "sky130_fd_sc_hd__o32a_1".
+Reading "sky130_fd_sc_hd__a21boi_1".
+Reading "sky130_fd_sc_hd__nand4_1".
+Reading "sky130_fd_sc_hd__o311a_1".
+Reading "sky130_fd_sc_hd__o211a_1".
+Reading "sky130_fd_sc_hd__o2111a_1".
+Reading "sky130_fd_sc_hd__nand4b_1".
+Reading "sky130_fd_sc_hd__a31oi_1".
+Reading "sky130_fd_sc_hd__and4_1".
+Reading "sky130_fd_sc_hd__a41o_1".
+Reading "sky130_fd_sc_hd__and2b_1".
+Reading "sky130_fd_sc_hd__a311oi_2".
+Reading "sky130_fd_sc_hd__o41a_1".
+Reading "sky130_fd_sc_hd__nor3b_1".
+Reading "sky130_fd_sc_hd__a2111oi_1".
+CIF file read warning: Input off lambda grid by 2/5; snapped to grid.
+Reading "sky130_fd_sc_hd__nand4b_4".
+Reading "sky130_fd_sc_hd__a31oi_4".
+Reading "sky130_fd_sc_hd__and4b_4".
+Reading "sky130_fd_sc_hd__nand3b_4".
+Reading "sky130_fd_sc_hd__o21a_4".
+Reading "sky130_fd_sc_hd__xor2_1".
+Reading "sky130_fd_sc_hd__nor3_4".
+Reading "sky130_fd_sc_hd__o221a_4".
+Reading "sky130_fd_sc_hd__mux2_8".
+Reading "sky130_fd_sc_hd__o31a_4".
+Reading "sky130_fd_sc_hd__and4_2".
+Reading "sky130_fd_sc_hd__a221oi_1".
+Reading "sky130_fd_sc_hd__a221o_4".
+Reading "sky130_fd_sc_hd__a21oi_4".
+Reading "sky130_fd_sc_hd__a21o_4".
+Reading "sky130_fd_sc_hd__inv_6".
+Reading "sky130_fd_sc_hd__a31o_2".
+Reading "sky130_fd_sc_hd__nand4_2".
+Reading "sky130_fd_sc_hd__and4b_2".
+Reading "sky130_fd_sc_hd__xnor2_2".
+Reading "sky130_fd_sc_hd__a21oi_2".
+Reading "sky130_fd_sc_hd__a211o_2".
+Reading "sky130_fd_sc_hd__and3_2".
+Reading "sky130_fd_sc_hd__o211a_2".
+Reading "sky130_fd_sc_hd__o31a_2".
+Reading "sky130_fd_sc_hd__nand3_2".
+Reading "sky130_fd_sc_hd__a21o_2".
+Reading "sky130_fd_sc_hd__a22o_2".
+Reading "sky130_fd_sc_hd__mux2_2".
+Reading "sky130_fd_sc_hd__and2b_4".
+Reading "sky130_fd_sc_hd__and3b_1".
+Reading "sky130_fd_sc_hd__and3b_4".
+Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hd__nand2_4".
+Reading "sky130_fd_sc_hd__nand2_8".
+Reading "sky130_fd_sc_hd__buf_6".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "housekeeping".
+ 5000 uses
+ 10000 uses
+ 15000 uses
+ 20000 uses
+Reading "sky130_fd_sc_hd__einvp_1".
+Reading "sky130_fd_sc_hd__clkinv_1".
+Reading "sky130_fd_sc_hd__einvn_4".
+Reading "sky130_fd_sc_hd__einvn_8".
+Reading "sky130_fd_sc_hd__einvp_2".
+Reading "sky130_fd_sc_hd__or2_2".
+Reading "sky130_fd_sc_hd__a32o_2".
+Reading "sky130_fd_sc_hd__o2111a_2".
+Reading "sky130_fd_sc_hd__o22a_2".
+Reading "sky130_fd_sc_hd__o221a_2".
+Reading "sky130_fd_sc_hd__nand3b_2".
+Reading "sky130_fd_sc_hd__a21boi_2".
+Reading "sky130_fd_sc_hd__xor2_2".
+Reading "sky130_fd_sc_hd__o2bb2a_2".
+Reading "sky130_fd_sc_hd__nand4b_2".
+Reading "sky130_fd_sc_hd__o21ba_2".
+Reading "sky130_fd_sc_hd__o32a_2".
+Reading "sky130_fd_sc_hd__clkinv_8".
+Reading "digital_pll".
+Reading "user_id_programming".
+Reading "D4_sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ".
+Reading "D4_sky130_fd_pr__pfet_g5v0d10v5_3YBPVB".
+Reading "D4_sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC".
+Reading "D4_sky130_fd_pr__nfet_g5v0d10v5_TGFUGS".
+Reading "D4_sky130_fd_pr__pfet_g5v0d10v5_YUHPBG".
+Reading "D4_sky130_fd_pr__pfet_g5v0d10v5_YEUEBV".
+Reading "D4_sky130_fd_pr__nfet_g5v0d10v5_PKVMTM".
+Reading "D4_sky130_fd_pr__pfet_g5v0d10v5_YUHPXE".
+Reading "D4_sky130_fd_sc_hvl__schmittbuf_1".
+Reading "D4_sky130_fd_sc_hvl__buf_8".
+Reading "D4_sky130_fd_sc_hvl__inv_8".
+Reading "D4_sky130_fd_sc_hvl__fill_4".
+Reading "D4_sky130_fd_pr__cap_mim_m3_1_WRT4AW".
+Reading "D4_sky130_fd_pr__cap_mim_m3_2_W5U4AW".
+Reading "D4_sky130_fd_pr__res_xhigh_po_0p69_S5N9F3".
+Reading "simple_por".
+Reading "ZT_sky130_fd_sc_hd__decap_3".
+Reading "ZT_sky130_ef_sc_hd__decap_12".
+Reading "ZT_sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "ZT_sky130_fd_sc_hd__fill_1".
+Reading "ZT_sky130_fd_sc_hd__decap_4".
+Reading "ZT_sky130_fd_sc_hd__decap_6".
+Reading "ZT_sky130_fd_sc_hd__fill_2".
+Reading "ZT_sky130_fd_sc_hd__decap_8".
+Reading "ZT_sky130_fd_sc_hd__diode_2".
+Reading "ZT_sky130_fd_sc_hd__clkbuf_16".
+Reading "ZT_sky130_fd_sc_hd__o211a_1".
+Reading "ZT_sky130_fd_sc_hd__dfxtp_2".
+Reading "ZT_sky130_fd_sc_hd__o21a_1".
+Reading "ZT_sky130_fd_sc_hd__mux2_1".
+Reading "ZT_sky130_fd_sc_hd__or2_1".
+Reading "ZT_sky130_fd_sc_hd__dfxtp_1".
+Reading "ZT_sky130_fd_sc_hd__a22o_1".
+Reading "ZT_sky130_fd_sc_hd__a21o_2".
+Reading "ZT_sky130_fd_sc_hd__a21o_1".
+Reading "ZT_sky130_fd_sc_hd__a22o_4".
+Reading "ZT_sky130_fd_sc_hd__buf_8".
+Reading "ZT_sky130_fd_sc_hd__o21a_2".
+Reading "ZT_sky130_fd_sc_hd__mux2_2".
+Reading "ZT_sky130_fd_sc_hd__buf_4".
+Reading "ZT_sky130_fd_sc_hd__clkbuf_8".
+Reading "ZT_sky130_fd_sc_hd__buf_6".
+Reading "ZT_sky130_fd_sc_hd__dfxtp_4".
+Reading "ZT_sky130_fd_sc_hd__buf_2".
+Reading "ZT_sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "ZT_sky130_fd_sc_hd__o21ai_1".
+Reading "ZT_sky130_fd_sc_hd__mux4_1".
+Reading "ZT_sky130_fd_sc_hd__buf_12".
+Reading "ZT_sky130_fd_sc_hd__mux4_2".
+Reading "ZT_sky130_fd_sc_hd__inv_2".
+Reading "ZT_sky130_fd_sc_hd__and3_2".
+Reading "ZT_sky130_fd_sc_hd__nand2_1".
+Reading "ZT_sky130_fd_sc_hd__a2bb2o_1".
+Reading "ZT_sky130_fd_sc_hd__or3b_1".
+Reading "ZT_sky130_fd_sc_hd__o32a_1".
+Reading "ZT_sky130_fd_sc_hd__a2bb2o_2".
+Reading "ZT_sky130_fd_sc_hd__o311a_1".
+Reading "ZT_sky130_fd_sc_hd__o221a_1".
+Reading "ZT_sky130_fd_sc_hd__o31a_1".
+Reading "ZT_sky130_fd_sc_hd__o211a_2".
+Reading "ZT_sky130_fd_sc_hd__and3_1".
+Reading "ZT_sky130_fd_sc_hd__a211oi_1".
+Reading "ZT_sky130_fd_sc_hd__and4_4".
+Reading "ZT_sky130_fd_sc_hd__and4_1".
+Reading "ZT_sky130_fd_sc_hd__clkbuf_4".
+Reading "ZT_sky130_fd_sc_hd__and3b_1".
+Reading "ZT_sky130_fd_sc_hd__a211o_4".
+Reading "ZT_sky130_fd_sc_hd__a211o_1".
+Reading "ZT_sky130_fd_sc_hd__o21ba_1".
+Reading "ZT_sky130_fd_sc_hd__a21oi_1".
+Reading "ZT_sky130_fd_sc_hd__nor2_1".
+Reading "ZT_sky130_fd_sc_hd__nand2_8".
+Reading "ZT_sky130_fd_sc_hd__a311o_1".
+Reading "ZT_sky130_fd_sc_hd__nor2_2".
+Reading "ZT_sky130_fd_sc_hd__a41o_1".
+Reading "ZT_sky130_fd_sc_hd__nor3_2".
+Reading "ZT_sky130_fd_sc_hd__or4bb_4".
+Reading "ZT_sky130_fd_sc_hd__nor3_1".
+Reading "ZT_sky130_fd_sc_hd__or4b_4".
+Reading "ZT_sky130_fd_sc_hd__or3b_4".
+Reading "ZT_sky130_fd_sc_hd__a31o_1".
+Reading "ZT_sky130_fd_sc_hd__a211o_2".
+Reading "ZT_sky130_fd_sc_hd__or2_2".
+Reading "ZT_sky130_fd_sc_hd__a31o_2".
+Reading "ZT_sky130_fd_sc_hd__a221o_1".
+Reading "ZT_sky130_fd_sc_hd__and4b_4".
+Reading "ZT_sky130_fd_sc_hd__and3_4".
+Reading "ZT_sky130_fd_sc_hd__mux2_8".
+Reading "ZT_sky130_fd_sc_hd__o21ai_2".
+Reading "ZT_sky130_fd_sc_hd__and4b_1".
+Reading "ZT_sky130_fd_sc_hd__or4b_1".
+Reading "ZT_sky130_fd_sc_hd__o211a_4".
+Reading "ZT_sky130_fd_sc_hd__a32o_1".
+Reading "ZT_sky130_fd_sc_hd__a21boi_1".
+Reading "ZT_sky130_fd_sc_hd__o41ai_4".
+Reading "ZT_sky130_fd_sc_hd__o31a_2".
+Reading "ZT_sky130_fd_sc_hd__nand2_4".
+Reading "ZT_sky130_fd_sc_hd__a31oi_4".
+Reading "ZT_sky130_fd_sc_hd__and4_2".
+Reading "ZT_sky130_fd_sc_hd__nand3_4".
+Reading "ZT_sky130_fd_sc_hd__and4b_2".
+Reading "ZT_sky130_fd_sc_hd__o41a_4".
+Reading "ZT_sky130_fd_sc_hd__and4bb_2".
+Reading "ZT_sky130_fd_sc_hd__clkinv_2".
+Reading "ZT_sky130_fd_sc_hd__and2b_2".
+Reading "ZT_sky130_fd_sc_hd__or4bb_1".
+Reading "ZT_sky130_fd_sc_hd__a21oi_2".
+Reading "ZT_sky130_fd_sc_hd__a221oi_1".
+Reading "ZT_sky130_fd_sc_hd__a31oi_1".
+Reading "ZT_sky130_fd_sc_hd__xor2_4".
+Reading "ZT_sky130_fd_sc_hd__clkbuf_1".
+Reading "ZT_sky130_fd_sc_hd__nand3b_4".
+Reading "ZT_sky130_fd_sc_hd__nand2_2".
+Reading "ZT_sky130_fd_sc_hd__xnor2_1".
+Reading "ZT_sky130_fd_sc_hd__and2_1".
+Reading "ZT_sky130_fd_sc_hd__nor2_4".
+Reading "ZT_sky130_fd_sc_hd__nand4_4".
+Reading "ZT_sky130_fd_sc_hd__a32o_2".
+Reading "ZT_sky130_fd_sc_hd__nor4_1".
+Reading "ZT_sky130_fd_sc_hd__nand4_1".
+Reading "ZT_sky130_fd_sc_hd__xor2_1".
+Reading "ZT_sky130_fd_sc_hd__and4bb_4".
+Reading "ZT_sky130_fd_sc_hd__a41o_2".
+Reading "ZT_sky130_fd_sc_hd__o2bb2a_1".
+Reading "ZT_sky130_fd_sc_hd__xnor2_2".
+Reading "ZT_sky130_fd_sc_hd__xor2_2".
+Reading "ZT_sky130_fd_sc_hd__or2_4".
+Reading "ZT_sky130_fd_sc_hd__a2111oi_2".
+Reading "ZT_sky130_fd_sc_hd__nor4_4".
+Reading "ZT_sky130_fd_sc_hd__mux2_4".
+Reading "ZT_sky130_fd_sc_hd__and2b_1".
+Reading "ZT_sky130_fd_sc_hd__and2_2".
+Reading "ZT_sky130_fd_sc_hd__nor4b_1".
+Reading "ZT_sky130_fd_sc_hd__o2111ai_4".
+Reading "ZT_sky130_fd_sc_hd__nor4_2".
+Reading "ZT_sky130_fd_sc_hd__nand3b_2".
+Reading "ZT_sky130_fd_sc_hd__nand3_1".
+Reading "ZT_sky130_fd_sc_hd__nand2b_2".
+Reading "ZT_sky130_fd_sc_hd__o31ai_1".
+Reading "ZT_sky130_fd_sc_hd__o41a_1".
+Reading "ZT_sky130_fd_sc_hd__a21bo_1".
+Reading "ZT_sky130_fd_sc_hd__o41ai_1".
+Reading "ZT_sky130_fd_sc_hd__nand3b_1".
+Reading "ZT_sky130_fd_sc_hd__o2111a_1".
+Reading "ZT_sky130_fd_sc_hd__o21a_4".
+Reading "ZT_sky130_fd_sc_hd__o22a_1".
+Reading "ZT_sky130_fd_sc_hd__or3b_2".
+Reading "ZT_sky130_fd_sc_hd__nand2b_1".
+Reading "ZT_sky130_fd_sc_hd__nor4b_4".
+Reading "ZT_sky130_fd_sc_hd__o21bai_1".
+Reading "ZT_sky130_fd_sc_hd__nor3_4".
+Reading "ZT_sky130_fd_sc_hd__o41a_2".
+Reading "ZT_sky130_fd_sc_hd__or4b_2".
+Reading "ZT_sky130_fd_sc_hd__a221o_4".
+Reading "ZT_sky130_fd_sc_hd__a2111oi_1".
+Reading "ZT_sky130_fd_sc_hd__o31a_4".
+Reading "ZT_sky130_fd_sc_hd__nor2_8".
+Reading "ZT_sky130_fd_sc_hd__clkinv_4".
+Reading "ZT_sky130_fd_sc_hd__a221o_2".
+Reading "ZT_sky130_fd_sc_hd__o21ai_4".
+Reading "ZT_sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "ZT_sky130_fd_sc_hd__clkbuf_2".
+Reading "ZT_sky130_fd_sc_hd__a31o_4".
+Reading "ZT_sky130_fd_sc_hd__ebufn_4".
+Reading "ZT_sky130_fd_sc_hd__dlxtp_1".
+Reading "ZT_sky130_fd_sc_hd__dlclkp_1".
+Reading "ZT_sky130_fd_sc_hd__conb_1".
+Reading "ZT_sky130_fd_sc_hd__inv_1".
+Reading "ZT_sky130_fd_sc_hd__nor4b_2".
+Reading "ZT_sky130_fd_sc_hd__and3b_2".
+Reading "ZT_sky130_fd_sc_hd__nor3b_2".
+Reading "ZT_RAM256".
+ 5000 uses
+ 10000 uses
+ 15000 uses
+ 20000 uses
+ 25000 uses
+ 30000 uses
+ 35000 uses
+ 40000 uses
+ 45000 uses
+ 50000 uses
+ 55000 uses
+Reading "ZT_sky130_fd_sc_hd__a21o_4".
+Reading "ZT_sky130_fd_sc_hd__o2111a_4".
+Reading "ZT_sky130_fd_sc_hd__a22o_2".
+Reading "ZT_sky130_fd_sc_hd__o211ai_4".
+Reading "ZT_sky130_fd_sc_hd__o22ai_4".
+Reading "ZT_sky130_fd_sc_hd__a221oi_4".
+Reading "ZT_sky130_fd_sc_hd__and2b_4".
+Reading "ZT_sky130_fd_sc_hd__and3b_4".
+Reading "ZT_sky130_fd_sc_hd__and4bb_1".
+Reading "ZT_sky130_fd_sc_hd__a21oi_4".
+Reading "ZT_sky130_fd_sc_hd__o22ai_1".
+Reading "ZT_sky130_fd_sc_hd__inv_4".
+Reading "ZT_sky130_fd_sc_hd__a311o_2".
+Reading "ZT_sky130_fd_sc_hd__a2111o_1".
+Reading "ZT_sky130_fd_sc_hd__o311a_4".
+Reading "ZT_sky130_fd_sc_hd__o2111ai_1".
+Reading "ZT_sky130_fd_sc_hd__clkinv_8".
+Reading "ZT_sky130_fd_sc_hd__nand3_2".
+Reading "ZT_sky130_fd_sc_hd__a22oi_1".
+Reading "ZT_sky130_fd_sc_hd__nand4b_4".
+Reading "ZT_sky130_fd_sc_hd__o221ai_4".
+Reading "ZT_sky130_fd_sc_hd__nand4_2".
+Reading "ZT_sky130_fd_sc_hd__inv_6".
+Reading "ZT_sky130_fd_sc_hd__o2bb2ai_1".
+Reading "ZT_sky130_fd_sc_hd__a311oi_4".
+Reading "ZT_sky130_fd_sc_hd__o32ai_4".
+Reading "ZT_sky130_fd_sc_hd__o211ai_1".
+Reading "ZT_sky130_fd_sc_hd__nand4b_1".
+Reading "ZT_sky130_fd_sc_hd__o211ai_2".
+Reading "ZT_sky130_fd_sc_hd__a22oi_4".
+Reading "ZT_sky130_fd_sc_hd__and2_4".
+Reading "ZT_sky130_fd_sc_hd__a211oi_4".
+Reading "ZT_sky130_fd_sc_hd__nor3b_4".
+Reading "ZT_sky130_fd_sc_hd__o22a_2".
+Reading "ZT_sky130_fd_sc_hd__a2111oi_4".
+Reading "ZT_sky130_fd_sc_hd__nand2b_4".
+Reading "ZT_sky130_fd_sc_hd__a2bb2o_4".
+Reading "ZT_sky130_fd_sc_hd__o2bb2a_2".
+Reading "ZT_sky130_fd_sc_hd__o2111ai_2".
+Reading "ZT_sky130_fd_sc_hd__a22oi_2".
+Reading "ZT_sky130_fd_sc_hd__nor3b_1".
+Reading "ZT_sky130_fd_sc_hd__o2bb2a_4".
+Reading "ZT_sky130_fd_sc_hd__o21bai_4".
+Reading "ZT_sky130_fd_sc_hd__o311ai_1".
+Reading "ZT_sky130_fd_sc_hd__a32oi_2".
+Reading "ZT_sky130_fd_sc_hd__o2bb2ai_2".
+Reading "ZT_sky130_fd_sc_hd__o311ai_4".
+Reading "ZT_sky130_fd_sc_hd__o2bb2ai_4".
+Reading "ZT_sky130_fd_sc_hd__o31ai_4".
+Reading "ZT_sky130_fd_sc_hd__o221a_2".
+Reading "ZT_sky130_fd_sc_hd__o2111a_2".
+Reading "ZT_sky130_fd_sc_hd__a31oi_2".
+Reading "ZT_sky130_fd_sc_hd__o311a_2".
+Reading "ZT_sky130_fd_sc_hd__o22a_4".
+Reading "ZT_sky130_fd_sc_hd__a32oi_4".
+Reading "ZT_sky130_fd_sc_hd__a211oi_2".
+Reading "ZT_sky130_fd_sc_hd__o31ai_2".
+Reading "ZT_sky130_fd_sc_hd__o221ai_1".
+Reading "ZT_sky130_fd_sc_hd__clkinv_16".
+Reading "ZT_sky130_fd_sc_hd__or4bb_2".
+Reading "ZT_sky130_fd_sc_hd__a221oi_2".
+Reading "ZT_sky130_fd_sc_hd__inv_8".
+Reading "ZT_sky130_fd_sc_hd__a311oi_2".
+Reading "ZT_sky130_fd_sc_hd__a311oi_1".
+Reading "ZT_sky130_fd_sc_hd__o311ai_2".
+Reading "ZT_sky130_fd_sc_hd__a32oi_1".
+Reading "ZT_sky130_fd_sc_hd__a2bb2oi_2".
+Reading "ZT_sky130_fd_sc_hd__a2bb2oi_1".
+Reading "ZT_sky130_fd_sc_hd__a2bb2oi_4".
+Reading "ZT_sky130_fd_sc_hd__xnor2_4".
+Reading "ZT_sky130_fd_sc_hd__inv_12".
+Reading "ZT_sky130_fd_sc_hd__a2111o_4".
+Reading "ZT_sky130_fd_sc_hd__a32o_4".
+Reading "ZT_sky130_fd_sc_hd__o21ba_2".
+Reading "ZT_sky130_fd_sc_hd__a41oi_2".
+Reading "ZT_sky130_fd_sc_hd__o22ai_2".
+Reading "ZT_sky130_fd_sc_hd__o21bai_2".
+Reading "ZT_sky130_fd_sc_hd__a41oi_4".
+Reading "ZT_sky130_fd_sc_hd__a41o_4".
+Reading "ZT_sky130_fd_sc_hd__a311o_4".
+Reading "ZT_sky130_fd_sc_hd__o32ai_1".
+Reading "ZT_sky130_fd_sc_hd__a21boi_4".
+Reading "ZT_sky130_fd_sc_hd__o32ai_2".
+Reading "ZT_sky130_fd_sc_hd__a21bo_2".
+Reading "ZT_RAM128".
+ 5000 uses
+ 10000 uses
+ 15000 uses
+ 20000 uses
+ 25000 uses
+Reading "mgmt_core_wrapper".
+ 5000 uses
+ 10000 uses
+ 15000 uses
+ 20000 uses
+ 25000 uses
+ 30000 uses
+ 35000 uses
+ 40000 uses
+ 45000 uses
+ 50000 uses
+ 55000 uses
+ 60000 uses
+ 65000 uses
+ 70000 uses
+ 75000 uses
+ 80000 uses
+ 85000 uses
+ 90000 uses
+ 95000 uses
+ 100000 uses
+ 105000 uses
+ 110000 uses
+ 115000 uses
+ 120000 uses
+ 125000 uses
+ 130000 uses
+ 135000 uses
+ 140000 uses
+ 145000 uses
+ 150000 uses
+ 155000 uses
+ 160000 uses
+ 165000 uses
+ 170000 uses
+ 175000 uses
+ 180000 uses
+ 185000 uses
+ 190000 uses
+ 195000 uses
+ 200000 uses
+ 205000 uses
+ 210000 uses
+ 215000 uses
+ 220000 uses
+Reading "gpio_defaults_block_0403".
+Reading "sky130_fd_sc_hd__inv_8".
+Reading "sky130_fd_sc_hd__dfbbp_1".
+Reading "spare_logic_block".
+Reading "sky130_fd_sc_hd__bufbuf_8".
+Reading "sky130_fd_sc_hvl__conb_1".
+Reading "mgmt_protect_hv".
+Reading "mprj_logic_high".
+Reading "mprj2_logic_high".
+Reading "sky130_fd_sc_hd__inv_12".
+Reading "mgmt_protect".
+ 5000 uses
+ 10000 uses
+ 15000 uses
+ 20000 uses
+ 25000 uses
+ 30000 uses
+ 35000 uses
+Reading "gpio_defaults_block_0801".
+Reading "gpio_control_power_routing_top".
+Reading "gpio_control_power_routing_right".
+Reading "gpio_control_power_routing".
+Reading "caravel_power_routing".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_39".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_19".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_14".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_13".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_7".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_38".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_33".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_32".
+Reading "VA_sky130_fd_bd_sram__openram_dff".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_row_addr_dff".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_wmask_dff".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_cr_3".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_col_addr_dff".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_data_dff".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_16".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_29".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_28".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_11".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_360_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_12".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_1".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dli".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sli_dactive".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_1".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w1_680_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w1_680_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_3".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w0_740_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w1_260_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_2".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_0".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m7_w1_680_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m7_w2_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_4".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_1".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_0".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pand2_1".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m24_w2_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m24_w2_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_14".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m8_w2_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m8_w2_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_13".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w2_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w2_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_12".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_11".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_0".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_3".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_17".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_delay_chain".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m18_w2_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m18_w2_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_16".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_5".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dactive".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pnand3".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pand3_0".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m22_w2_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m22_w2_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_15".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_4".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pand3".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m42_w2_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m42_w2_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_10".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m15_w2_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m15_w2_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_9".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w2_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m5_w2_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_8".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w1_260_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w2_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_7".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_2".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_rw".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_cr_5".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array_0".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m41_w2_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m41_w2_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_20".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m14_w2_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m14_w2_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_19".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w1_680_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_18".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_6".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_r".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_cr_4".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_20".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_17".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_0".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pand2_0".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4_0".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_15".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w7_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w7_000_sli_dli_da_p".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec_0".
+Reading "VA_sky130_fd_bd_sram__openram_dp_nand2_dec".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec_0".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver_array".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec".
+Reading "VA_sky130_fd_bd_sram__openram_dp_nand3_dec".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_and3_dec".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode3x8".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_decoder".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_port_address_0".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_port_address".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_27".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_26".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_25".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_24".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w2_880_sli_dli".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_0".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array_0".
+Reading "VA_sky130_fd_bd_sram__openram_sense_amp".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_sense_amp_array".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_23".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_21".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_22".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w0_550_sli_dli".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_precharge_1".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array_0".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_port_data_0".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_column_mux".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pinv".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pdriver".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pnand2".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_pand2".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_write_mask_and_array".
+Reading "VA_sky130_fd_bd_sram__openram_write_driver".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_write_driver_array".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_precharge_0".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_port_data".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_9".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_contact_8".
+Reading "VA_sky130_fd_bd_sram__openram_dp_cell_cap_row".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array_0".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array".
+Reading "VA_sky130_fd_bd_sram__openram_dp_cell_cap_col".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array_0".
+Reading "VA_sky130_fd_bd_sram__openram_dp_cell_dummy".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_dummy_array".
+Reading "VA_sky130_fd_bd_sram__openram_dp_cell_replica".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_replica_column_0".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_replica_column".
+Reading "VA_sky130_fd_bd_sram__openram_dp_cell".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_bitcell_array".
+ 5000 uses
+ 10000 uses
+ 15000 uses
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_replica_bitcell_array".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8_bank".
+Reading "VA_sky130_sram_2kbyte_1rw1r_32x512_8".
+ 5000 uses
+Reading "VA_sky130_fd_sc_hd__and2_2".
+Reading "VA_sky130_fd_sc_hd__or4_2".
+Reading "VA_sky130_fd_sc_hd__o41a_2".
+Reading "VA_sky130_fd_sc_hd__o311a_2".
+Reading "VA_sky130_fd_sc_hd__and3_2".
+Reading "VA_sky130_fd_sc_hd__conb_1".
+Reading "VA_sky130_fd_sc_hd__clkbuf_2".
+Reading "VA_sky130_fd_sc_hd__clkbuf_1".
+Reading "VA_sky130_fd_sc_hd__clkinv_2".
+Reading "VA_sky130_fd_sc_hd__mux2_1".
+Reading "VA_sky130_fd_sc_hd__o32a_2".
+Reading "VA_sky130_fd_sc_hd__clkinv_8".
+Reading "VA_sky130_fd_sc_hd__a221o_2".
+Reading "VA_sky130_fd_sc_hd__decap_8".
+Reading "VA_sky130_fd_sc_hd__o31a_2".
+Reading "VA_sky130_fd_sc_hd__a22oi_2".
+Reading "VA_sky130_fd_sc_hd__a21bo_2".
+Reading "VA_sky130_fd_sc_hd__a21o_2".
+Reading "VA_sky130_fd_sc_hd__o22a_2".
+Reading "VA_sky130_fd_sc_hd__o211a_2".
+Reading "VA_sky130_fd_sc_hd__and4_2".
+Reading "VA_sky130_fd_sc_hd__a31o_2".
+Reading "VA_sky130_fd_sc_hd__nand2_2".
+Reading "VA_sky130_fd_sc_hd__o2bb2ai_2".
+Reading "VA_sky130_fd_sc_hd__o21ai_2".
+Reading "VA_sky130_fd_sc_hd__o221a_2".
+Reading "VA_sky130_fd_sc_hd__a2bb2o_2".
+Reading "VA_sky130_fd_sc_hd__or2_2".
+Reading "VA_sky130_fd_sc_hd__inv_2".
+Reading "VA_sky130_fd_sc_hd__fill_2".
+Reading "VA_sky130_fd_sc_hd__or3_2".
+Reading "VA_sky130_fd_sc_hd__a21oi_2".
+Reading "VA_sky130_fd_sc_hd__nor2_2".
+Reading "VA_sky130_fd_sc_hd__a22o_2".
+Reading "VA_sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "VA_sky130_fd_sc_hd__dfrtp_2".
+Reading "VA_sky130_fd_sc_hd__decap_4".
+Reading "VA_sky130_fd_sc_hd__buf_1".
+Reading "VA_sky130_fd_sc_hd__diode_2".
+Reading "VA_sky130_fd_sc_hd__decap_6".
+Reading "VA_sky130_fd_sc_hd__fill_1".
+Reading "VA_sky130_fd_sc_hd__decap_3".
+Reading "VA_sky130_fd_sc_hd__buf_2".
+Reading "VA_sky130_ef_sc_hd__decap_12".
+Reading "VA_sky130_fd_sc_hd__dfrtp_4".
+Reading "VA_sky130_fd_sc_hd__dfrtp_1".
+Reading "VA_sky130_fd_sc_hd__dfstp_2".
+Reading "VA_sky130_fd_sc_hd__clkbuf_16".
+Reading "VA_sky130_fd_sc_hd__xnor2_1".
+Reading "VA_sky130_fd_sc_hd__xor2_1".
+Reading "VA_sky130_fd_sc_hd__o21ai_1".
+Reading "VA_sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "VA_sky130_fd_sc_hd__or2b_1".
+Reading "VA_sky130_fd_sc_hd__o211a_1".
+Reading "VA_sky130_fd_sc_hd__or2_1".
+Reading "VA_sky130_fd_sc_hd__dfstp_1".
+Reading "VA_sky130_fd_sc_hd__a21oi_1".
+Reading "VA_sky130_fd_sc_hd__a221o_1".
+Reading "VA_sky130_fd_sc_hd__a31o_1".
+Reading "VA_sky130_fd_sc_hd__nand2_1".
+Reading "VA_sky130_fd_sc_hd__o21a_1".
+Reading "VA_sky130_fd_sc_hd__o2bb2a_1".
+Reading "VA_sky130_fd_sc_hd__nor2_1".
+Reading "VA_sky130_fd_sc_hd__o21ai_4".
+Reading "VA_sky130_fd_sc_hd__clkbuf_4".
+Reading "VA_sky130_fd_sc_hd__and3_1".
+Reading "VA_sky130_fd_sc_hd__nand3_2".
+Reading "VA_sky130_fd_sc_hd__and2_1".
+Reading "VA_sky130_fd_sc_hd__a21o_1".
+Reading "VA_sky130_fd_sc_hd__a311o_1".
+Reading "VA_sky130_fd_sc_hd__a21bo_1".
+Reading "VA_sky130_fd_sc_hd__a2bb2o_1".
+Reading "VA_sky130_fd_sc_hd__o22a_1".
+Reading "VA_sky130_fd_sc_hd__a211o_1".
+Reading "VA_sky130_fd_sc_hd__a22oi_1".
+Reading "VA_sky130_fd_sc_hd__a22o_1".
+Reading "VA_sky130_fd_sc_hd__and4bb_2".
+Reading "VA_sky130_fd_sc_hd__or2_4".
+Reading "VA_sky130_fd_sc_hd__or4b_1".
+Reading "VA_sky130_fd_sc_hd__buf_8".
+Reading "VA_sky130_fd_sc_hd__mux2_2".
+Reading "VA_sky130_fd_sc_hd__and2_4".
+Reading "VA_sky130_fd_sc_hd__a32o_1".
+Reading "VA_sky130_fd_sc_hd__and2b_1".
+Reading "VA_sky130_fd_sc_hd__a22o_4".
+Reading "VA_sky130_fd_sc_hd__or3_1".
+Reading "VA_sky130_fd_sc_hd__buf_12".
+Reading "VA_sky130_fd_sc_hd__o221a_1".
+Reading "VA_sky130_fd_sc_hd__xor2_2".
+Reading "VA_sky130_fd_sc_hd__nand3_1".
+Reading "VA_sky130_fd_sc_hd__or4b_4".
+Reading "VA_sky130_fd_sc_hd__o211ai_4".
+Reading "VA_sky130_fd_sc_hd__mux4_1".
+Reading "VA_sky130_fd_sc_hd__or3b_1".
+Reading "VA_sky130_fd_sc_hd__mux4_2".
+Reading "VA_sky130_fd_sc_hd__or2b_4".
+Reading "VA_sky130_fd_sc_hd__buf_4".
+Reading "VA_sky130_fd_sc_hd__nor2_4".
+Reading "VA_sky130_fd_sc_hd__nand2_8".
+Reading "VA_sky130_fd_sc_hd__or4_1".
+Reading "VA_sky130_fd_sc_hd__clkbuf_8".
+Reading "VA_sky130_fd_sc_hd__buf_6".
+Reading "VA_sky130_fd_sc_hd__a221o_4".
+Reading "VA_sky130_fd_sc_hd__mux2_8".
+Reading "VA_sky130_fd_sc_hd__a22oi_4".
+Reading "VA_sky130_fd_sc_hd__a221oi_4".
+Reading "VA_sky130_fd_sc_hd__a21o_4".
+Reading "VA_sky130_fd_sc_hd__o221ai_4".
+Reading "VA_sky130_fd_sc_hd__a41o_4".
+Reading "VA_sky130_fd_sc_hd__a211o_4".
+Reading "VA_sky130_fd_sc_hd__o31a_1".
+Reading "VA_sky130_fd_sc_hd__nor4_4".
+Reading "VA_sky130_fd_sc_hd__or4_4".
+Reading "VA_sky130_fd_sc_hd__o211ai_1".
+Reading "VA_sky130_fd_sc_hd__o221a_4".
+Reading "VA_sky130_fd_sc_hd__o31a_4".
+Reading "VA_sky130_fd_sc_hd__o311a_1".
+Reading "VA_sky130_fd_sc_hd__nand4_1".
+Reading "VA_sky130_fd_sc_hd__o211ai_2".
+Reading "VA_sky130_fd_sc_hd__nand4b_1".
+Reading "VA_sky130_fd_sc_hd__and4_1".
+Reading "VA_sky130_fd_sc_hd__or3_4".
+Reading "VA_sky130_fd_sc_hd__and4_4".
+Reading "VA_sky130_fd_sc_hd__o31ai_1".
+Reading "VA_sky130_fd_sc_hd__or4bb_1".
+Reading "VA_sky130_fd_sc_hd__o21ba_1".
+Reading "VA_sky130_fd_sc_hd__and4b_2".
+Reading "VA_sky130_fd_sc_hd__a221oi_1".
+Reading "VA_sky130_fd_sc_hd__nand4_4".
+Reading "VA_sky130_fd_sc_hd__and4b_4".
+Reading "VA_sky130_fd_sc_hd__and4bb_4".
+Reading "VA_sky130_fd_sc_hd__nand2_4".
+Reading "VA_sky130_fd_sc_hd__or4bb_4".
+Reading "VA_sky130_fd_sc_hd__and4b_1".
+Reading "VA_sky130_fd_sc_hd__a32o_4".
+Reading "VA_sky130_fd_sc_hd__dlygate4sd1_1".
+Reading "VA_sky130_fd_sc_hd__o32a_1".
+Reading "VA_sky130_fd_sc_hd__nor4b_4".
+Reading "VA_sky130_fd_sc_hd__nor3_4".
+Reading "VA_sky130_fd_sc_hd__o31ai_4".
+Reading "VA_sky130_fd_sc_hd__and3b_4".
+Reading "VA_sky130_fd_sc_hd__and3_4".
+Reading "VA_sky130_fd_sc_hd__o31ai_2".
+Reading "VA_sky130_fd_sc_hd__a211oi_4".
+Reading "VA_sky130_fd_sc_hd__o22a_4".
+Reading "VA_sky130_fd_sc_hd__nor4_2".
+Reading "VA_sky130_fd_sc_hd__a41o_2".
+Reading "VA_sky130_fd_sc_hd__inv_6".
+Reading "VA_sky130_fd_sc_hd__nand3_4".
+Reading "VA_sky130_fd_sc_hd__o2bb2ai_1".
+Reading "VA_sky130_fd_sc_hd__clkinv_4".
+Reading "VA_sky130_fd_sc_hd__a2111o_4".
+Reading "VA_sky130_fd_sc_hd__and2b_4".
+Reading "VA_sky130_fd_sc_hd__a2bb2o_4".
+Reading "VA_sky130_fd_sc_hd__o21a_4".
+Reading "VA_sky130_fd_sc_hd__o211a_4".
+Reading "VA_sky130_fd_sc_hd__a21oi_4".
+Reading "VA_sky130_fd_sc_hd__o311a_4".
+Reading "VA_sky130_fd_sc_hd__a211o_2".
+Reading "VA_sky130_fd_sc_hd__a32oi_4".
+Reading "VA_sky130_fd_sc_hd__and3b_2".
+Reading "VA_sky130_fd_sc_hd__and3b_1".
+Reading "VA_sky130_fd_sc_hd__nor4_1".
+Reading "VA_sky130_fd_sc_hd__and4bb_1".
+Reading "VA_sky130_fd_sc_hd__a211oi_1".
+Reading "VA_sky130_fd_sc_hd__mux2_4".
+Reading "VA_sky130_fd_sc_hd__nor3_2".
+Reading "VA_sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "VA_sky130_fd_sc_hd__or4b_2".
+Reading "VA_ycr4_iconnect".
+ 5000 uses
+ 10000 uses
+ 15000 uses
+ 20000 uses
+ 25000 uses
+ 30000 uses
+ 35000 uses
+ 40000 uses
+ 45000 uses
+ 50000 uses
+ 55000 uses
+ 60000 uses
+ 65000 uses
+ 70000 uses
+ 75000 uses
+Reading "VA_sky130_fd_sc_hd__o21a_2".
+Reading "VA_sky130_fd_sc_hd__a32o_2".
+Reading "VA_sky130_fd_sc_hd__o22ai_2".
+Reading "VA_sky130_fd_sc_hd__a311o_2".
+Reading "VA_sky130_fd_sc_hd__a41o_1".
+Reading "VA_sky130_fd_sc_hd__o21bai_2".
+Reading "VA_sky130_fd_sc_hd__nor3_1".
+Reading "VA_sky130_fd_sc_hd__a21boi_1".
+Reading "VA_sky130_fd_sc_hd__xnor2_2".
+Reading "VA_sky130_fd_sc_hd__a2111o_2".
+Reading "VA_sky130_fd_sc_hd__o21bai_1".
+Reading "VA_sky130_fd_sc_hd__o2111a_1".
+Reading "VA_sky130_fd_sc_hd__a31oi_4".
+Reading "VA_sky130_fd_sc_hd__a2111oi_4".
+Reading "VA_sky130_fd_sc_hd__nand4_2".
+Reading "VA_sky130_fd_sc_hd__o22ai_1".
+Reading "VA_sky130_fd_sc_hd__a31oi_1".
+Reading "VA_sky130_fd_sc_hd__a311oi_1".
+Reading "VA_sky130_fd_sc_hd__or2b_2".
+Reading "VA_sky130_fd_sc_hd__xnor2_4".
+Reading "VA_sky130_fd_sc_hd__or3b_2".
+Reading "VA_sky130_fd_sc_hd__o41a_1".
+Reading "VA_sky130_fd_sc_hd__nor3b_2".
+Reading "VA_sky130_fd_sc_hd__nand2b_2".
+Reading "VA_sky130_fd_sc_hd__nor4b_2".
+Reading "VA_sky130_fd_sc_hd__nand3b_1".
+Reading "VA_sky130_fd_sc_hd__a211oi_2".
+Reading "VA_sky130_fd_sc_hd__o21ba_2".
+Reading "VA_sky130_fd_sc_hd__nand3b_2".
+Reading "VA_sky130_fd_sc_hd__o22ai_4".
+Reading "VA_sky130_fd_sc_hd__a2111o_1".
+Reading "VA_sky130_fd_sc_hd__a31oi_2".
+Reading "VA_sky130_fd_sc_hd__nor2b_1".
+Reading "VA_sky130_fd_sc_hd__nor3b_1".
+Reading "VA_sky130_fd_sc_hd__a2111oi_1".
+Reading "VA_sky130_fd_sc_hd__and2b_2".
+Reading "VA_sky130_fd_sc_hd__dfxtp_1".
+Reading "VA_sky130_fd_sc_hd__nor4b_1".
+Reading "VA_sky130_fd_sc_hd__a311oi_2".
+Reading "VA_sky130_fd_sc_hd__xor2_4".
+Reading "VA_sky130_fd_sc_hd__dfxtp_2".
+Reading "VA_sky130_fd_sc_hd__a21bo_4".
+Reading "VA_sky130_fd_sc_hd__or3b_4".
+Reading "VA_sky130_fd_sc_hd__or4bb_2".
+Reading "VA_sky130_fd_sc_hd__nor2_8".
+Reading "VA_sky130_fd_sc_hd__inv_4".
+Reading "VA_sky130_fd_sc_hd__o2111ai_4".
+Reading "VA_ycr_core_top".
+ 5000 uses
+ 10000 uses
+ 15000 uses
+ 20000 uses
+ 25000 uses
+ 30000 uses
+ 35000 uses
+ 40000 uses
+ 45000 uses
+ 50000 uses
+ 55000 uses
+ 60000 uses
+ 65000 uses
+ 70000 uses
+Reading "VA_sky130_fd_sc_hd__o221ai_2".
+Reading "VA_sky130_fd_sc_hd__o2111ai_2".
+Reading "VA_sky130_fd_sc_hd__o2bb2a_2".
+Reading "VA_sky130_fd_sc_hd__o2111ai_1".
+Reading "VA_sky130_fd_sc_hd__a2111oi_2".
+Reading "VA_sky130_fd_sc_hd__a221oi_2".
+Reading "VA_sky130_fd_sc_hd__o221ai_1".
+Reading "VA_sky130_fd_sc_hd__o21bai_4".
+Reading "VA_sky130_fd_sc_hd__o32ai_1".
+Reading "VA_sky130_fd_sc_hd__dfstp_4".
+Reading "VA_sky130_fd_sc_hd__o41a_4".
+Reading "VA_sky130_fd_sc_hd__o2bb2a_4".
+Reading "VA_sky130_fd_sc_hd__a21boi_2".
+Reading "VA_sky130_fd_sc_hd__nand2b_1".
+Reading "VA_sky130_fd_sc_hd__o2111a_2".
+Reading "VA_sky130_fd_sc_hd__clkdlybuf4s15_2".
+Reading "VA_ycr_intf".
+ 5000 uses
+ 10000 uses
+ 15000 uses
+ 20000 uses
+ 25000 uses
+ 30000 uses
+ 35000 uses
+ 40000 uses
+ 45000 uses
+ 50000 uses
+ 55000 uses
+ 60000 uses
+Reading "VA_sky130_fd_sc_hd__einvp_2".
+Reading "VA_sky130_fd_sc_hd__decap_12".
+Reading "VA_sky130_fd_sc_hd__clkinv_1".
+Reading "VA_sky130_fd_sc_hd__einvn_8".
+Reading "VA_sky130_fd_sc_hd__einvn_4".
+Reading "VA_sky130_fd_sc_hd__einvp_1".
+Reading "VA_digital_pll".
+Reading "VA_sky130_fd_sc_hd__clkdlybuf4s25_1".
+Reading "VA_sky130_fd_sc_hd__nand4b_2".
+Reading "VA_wb_host".
+ 5000 uses
+ 10000 uses
+ 15000 uses
+ 20000 uses
+Reading "VA_sky130_fd_sc_hd__a31o_4".
+Reading "VA_sky130_fd_sc_hd__nor2b_2".
+Reading "VA_sky130_fd_sc_hd__nor3b_4".
+Reading "VA_uart_i2c_usb_spi_top".
+ 5000 uses
+ 10000 uses
+ 15000 uses
+ 20000 uses
+ 25000 uses
+ 30000 uses
+ 35000 uses
+ 40000 uses
+ 45000 uses
+ 50000 uses
+ 55000 uses
+Reading "VA_sky130_fd_sc_hd__a41oi_1".
+Reading "VA_sky130_fd_sc_hd__a2bb2oi_4".
+Reading "VA_wb_interconnect".
+ 5000 uses
+ 10000 uses
+ 15000 uses
+ 20000 uses
+ 25000 uses
+ 30000 uses
+ 35000 uses
+ 40000 uses
+ 45000 uses
+ 50000 uses
+ 55000 uses
+ 60000 uses
+Reading "VA_pinmux".
+ 5000 uses
+ 10000 uses
+ 15000 uses
+ 20000 uses
+ 25000 uses
+ 30000 uses
+Reading "VA_qspim_top".
+ 5000 uses
+ 10000 uses
+ 15000 uses
+ 20000 uses
+ 25000 uses
+ 30000 uses
+ 35000 uses
+Reading "user_project_wrapper".
+Reading "sky130_ef_io__com_bus_slice_20um".
+Reading "sky130_fd_io__corner_bus_overlay".
+Reading "sky130_ef_io__corner_pad".
+Reading "sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um".
+Reading "sky130_ef_io__com_bus_slice_1um".
+Reading "sky130_ef_io__com_bus_slice_5um".
+Reading "sky130_ef_io__com_bus_slice_10um".
+Reading "sky130_fd_pr__hvdfl1sd__example_5595914180851".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808664".
+Reading "sky130_fd_io__sio_clamp_pcap_4x5".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808680".
+Reading "sky130_fd_io__esd_rcclamp_nfetcap".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808336".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808666".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808665".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808678".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808679".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808677".
+Reading "sky130_fd_pr__via_pol1__example_5595914180839".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808667".
+Reading "sky130_fd_pr__hvdftpl1s__example_55959141808671".
+Reading "sky130_fd_pr__hvdftpl1s2__example_55959141808672".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808673".
+Reading "sky130_fd_pr__dfl1__example_55959141808663".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808660".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808670".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808668".
+Reading "sky130_fd_pr__hvdftpl1s__example_55959141808675".
+Reading "sky130_fd_pr__hvdftpl1s2__example_55959141808676".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808674".
+Reading "sky130_fd_pr__dfl1__example_55959141808662".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808661".
+Reading "sky130_fd_pr__via_l1m1__example_559591418084".
+Reading "sky130_fd_pr__genrivetdlring__example_559591418082".
+Reading "sky130_fd_pr__gendlring__example_559591418081".
+Reading "sky130_fd_pr__padplhp__example_559591418080".
+Reading "sky130_fd_io__pad_esd".
+Reading "sky130_fd_io__com_bus_slice".
+Reading "sky130_fd_io__com_bus_hookup".
+Reading "sky130_fd_io__com_busses_esd".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808669".
+Reading "sky130_fd_io__top_ground_hvc_wpad".
+Reading "sky130_fd_io__overlay_vssa_hvc".
+Reading "sky130_ef_io__hvc_vdda_overlay".
+Reading "sky130_ef_io__vssa_hvc_clamped_pad".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808719".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808767".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808765".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808764".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808720".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808718".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808717".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808716".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808243".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808723".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808722".
+Reading "sky130_fd_pr__hvdfm1sd2__example_5595914180890".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808721".
+Reading "sky130_fd_io__xres_inv_hysv2".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180838".
+Reading "sky130_fd_io__tk_tie_r_out_esd".
+Reading "sky130_fd_io__res250_sub_small".
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 633309758): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 633309790): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 633312382): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 633312414): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 633312446): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 633312478): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 633312510): NODE elements not supported: skipping.
+Error while reading cell "sky130_fd_io__res250_sub_small" (byte position 633312606): NODE elements not supported: skipping.
+Reading "sky130_fd_io__res250only_small".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808264".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180858".
+Reading "sky130_fd_pr__via_pol1__example_5595914180833".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180864".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808715".
+Reading "sky130_fd_pr__res_bent_po__example_5595914180863".
+Reading "sky130_fd_pr__res_bent_po__example_5595914180862".
+Reading "sky130_fd_io__tk_em1s_cdns_55959141808288".
+Reading "sky130_fd_io__tk_em1s_cdns_5595914180859".
+Reading "sky130_fd_io__tk_em1o_cdns_55959141808289".
+Reading "sky130_fd_io__com_res_weak_v2".
+Reading "sky130_fd_pr__via_pol1__example_55959141808274".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808728".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808727".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808726".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808725".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808724".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808554".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808553".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808552".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808551".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808402".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808350".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808261".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808260".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808259".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808400".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808372".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808326".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808290".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808128".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808127".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180897".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180819".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808555".
+Reading "sky130_fd_pr__via_pol1__example_55959141808147".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808157".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808156".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808155".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808154".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808153".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808152".
+Reading "sky130_fd_pr__tpl1__example_55959141808151".
+Reading "sky130_fd_pr__tpl1__example_55959141808150".
+Reading "sky130_fd_pr__tpl1__example_55959141808149".
+Reading "sky130_fd_pr__tpl1__example_55959141808148".
+Reading "sky130_fd_pr__dfl1__example_55959141808158".
+Reading "sky130_fd_io__signal_5_sym_hv_local_5term".
+Reading "sky130_fd_io__gpio_buf_localesdv2".
+Reading "sky130_fd_pr__via_pol1__example_559591418083".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808137".
+Reading "sky130_fd_pr__dfl1sd__example_559591418086".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808371".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808370".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808369".
+Reading "sky130_fd_io__hvsbt_inv_x1".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808316".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808421".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808385".
+Reading "sky130_fd_pr__dfl1sd__example_559591418088".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808422".
+Reading "sky130_fd_io__hvsbt_inv_x2".
+Reading "sky130_fd_pr__via_pol1__example_55959141808612".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808616".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808615".
+Reading "sky130_fd_io__hvsbt_inv_x4".
+Reading "sky130_fd_pr__hvdfm1sd__example_5595914180848".
+Reading "sky130_fd_pr__hvdfm1sd2__example_5595914180849".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808766".
+Reading "sky130_fd_pr__via_m2m3__example_55959141808714".
+Reading "sky130_fd_pr__via_pol1_centered__example_559591418081".
+Reading "sky130_fd_io__tk_em2s_cdns_55959141808652".
+Reading "sky130_fd_io__tk_em2o_cdns_55959141808653".
+Reading "sky130_fd_pr__via_l1m1_centered__example_5595914180812".
+Reading "sky130_fd_pr__via_l1m1_centered__example_5595914180811".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418086".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418084".
+Reading "sky130_fd_pr__hvdftpm1s2__example_55959141808659".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808658".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808657".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808202".
+Reading "sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2".
+Reading "sky130_fd_io__gpio_pudrvr_strong_axres4v2".
+Reading "sky130_fd_pr__via_pol1__example_55959141808273".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808740".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808739".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808738".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808737".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808736".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808735".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808734".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808733".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808732".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808731".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808730".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808752".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808751".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808750".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808749".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808748".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808747".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808746".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808745".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808744".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808743".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808742".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808741".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808324".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808270".
+Reading "sky130_fd_pr__dfl1__example_55959141808187".
+Reading "sky130_fd_pr__res_generic_nd__example_55959141808755".
+Reading "sky130_fd_pr__res_generic_nd__example_55959141808754".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808338".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808337".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808763".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808700".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808559".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808762".
+Reading "sky130_fd_pr__dfl1__example_55959141808729".
+Reading "sky130_fd_io__xres_tk_p_em1o_cdns_55959141808758".
+Reading "sky130_fd_io__xres_tk_p_em1o_cdns_55959141808757".
+Reading "sky130_fd_io__xres_tk_p_em1o_cdns_55959141808756".
+Reading "sky130_fd_io__xres_tk_p_em1c_cdns_55959141808761".
+Reading "sky130_fd_io__xres_tk_p_em1c_cdns_55959141808760".
+Reading "sky130_fd_io__xres_tk_p_em1c_cdns_55959141808759".
+Reading "sky130_fd_io__xres_p_em1c_cdns_55959141808753".
+Reading "sky130_fd_io__xres2v2_rcfilter_lpfv2".
+Reading "sky130_fd_io__tk_em1o_cdns_5595914180860".
+Reading "sky130_fd_pr__res_bent_po__example_5595914180861".
+Reading "sky130_fd_io__com_res_weak_bentbigres".
+Reading "sky130_fd_io__com_res_weak".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180857".
+Reading "sky130_fd_pr__hvdftpm1s2__example_55959141808649".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808651".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808650".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808648".
+Reading "sky130_fd_pr__hvdftpl1s__example_55959141808646".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808647".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808645".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808378".
+Reading "sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2".
+Reading "sky130_fd_io__gpio_pddrvr_strong_xres4v2".
+Reading "sky130_fd_io__top_gpio_pad".
+Reading "sky130_fd_io__com_busses".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808768".
+Reading "sky130_fd_pr__res_bent_nd__example_55959141808769".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808787".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808786".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808782".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808785".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808449".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808784".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808452".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808783".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808781".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808780".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808779".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808233".
+Reading "sky130_fd_pr__hvdfm1sd2__example_5595914180827".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808778".
+Reading "sky130_fd_pr__hvdfm1sd__example_5595914180835".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808777".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808776".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808775".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808242".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808774".
+Reading "sky130_fd_pr__hvdfm1sd2__example_5595914180829".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808773".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808237".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808772".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808771".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808770".
+Reading "sky130_fd_io__tap_1".
+Reading "sky130_fd_io__inv_1".
+Reading "sky130_fd_pr__pfet_01v8__example_559591418085".
+Reading "sky130_fd_pr__nfet_01v8__example_559591418089".
+Reading "sky130_fd_pr__nfet_01v8__example_559591418087".
+Reading "sky130_fd_io__hvsbt_nand2".
+Reading "sky130_fd_io__xres4v2_in_buf".
+Reading "sky130_fd_io__top_xres4v2".
+Reading "sky130_fd_sc_hd__fill_4".
+Reading "sky130_fd_sc_hd__fill_8".
+Reading "constant_block".
+Reading "sky130_fd_io__res75only_small".
+Reading "sky130_fd_io__com_bus_slice_m4".
+Reading "sky130_fd_io__overlay_gpiov2_m4".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808420".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808419".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808418".
+Reading "sky130_fd_io__hvsbt_nor".
+Reading "sky130_fd_io__hvsbt_nand2v2".
+Reading "sky130_fd_io__gpiov2_ictl_logic".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808190".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808611".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180811".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808549".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808548".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808191".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808189".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808517".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808518".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808610".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808609".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180815".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180816".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808608".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808604".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808533".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808529".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180884".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808230".
+Reading "sky130_fd_io__gpiov2_in_buf".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808537".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808106".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808481".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808607".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808504".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808600".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808550".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808528".
+Reading "sky130_fd_io__gpiov2_ipath_hvls".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808595".
+Reading "sky130_fd_pr__nfet_01v8__example_5595914180825".
+Reading "sky130_fd_io__gpiov2_inbuf_lvinv_x1".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180812".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808599".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808598".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808597".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808596".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808547".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808546".
+Reading "sky130_fd_io__gpiov2_ipath_lvls".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808606".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180875".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808605".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808540".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808603".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808602".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808601".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808535".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808527".
+Reading "sky130_fd_io__gpiov2_vcchib_in_buf".
+Reading "sky130_fd_io__gpiov2_ibuf_se".
+Reading "sky130_fd_io__gpiov2_buf_localesd".
+Reading "sky130_fd_io__gpiov2_ipath".
+Reading "sky130_fd_io__tk_em2s_cdns_55959141808438".
+Reading "sky130_fd_io__tk_em2o_cdns_55959141808439".
+Reading "sky130_fd_io__tk_em1s_cdns_5595914180882".
+Reading "sky130_fd_io__tk_em1s_cdns_5595914180881".
+Reading "sky130_fd_io__tk_em1o_cdns_5595914180880".
+Reading "sky130_fd_io__tk_em1o_cdns_5595914180879".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808430".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180823".
+Reading "sky130_fd_pr__pfet_01v8__example_5595914180822".
+Reading "sky130_fd_pr__pfet_01v8__example_5595914180813".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808624".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808510".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808623".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808622".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808621".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808620".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808619".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808618".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808116".
+Reading "sky130_fd_io__com_ctl_lsv2".
+Reading "sky130_fd_pr__via_pol1__example_55959141808394".
+Reading "sky130_fd_pr__via_pol1__example_55959141808298".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808440".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180878".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808434".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808435".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808433".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808432".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808102".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808431".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808115".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808429".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808428".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808100".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808140".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808427".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808426".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808280".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808425".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808424".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808423".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808306".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808383".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808382".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808380".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808379".
+Reading "sky130_fd_io__com_ctl_ls_v2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808617".
+Reading "sky130_fd_io__com_ctl_ls_en_1_v2".
+Reading "sky130_fd_io__com_ctl_ls_1v2".
+Reading "sky130_fd_io__gpiov2_ctl_lsbank".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808614".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808613".
+Reading "sky130_fd_io__hvsbt_inv_x8v2".
+Reading "sky130_fd_io__hvsbt_inv_x8".
+Reading "sky130_fd_io__com_ctl_ls".
+Reading "sky130_fd_io__com_ctl_hldv2".
+Reading "sky130_fd_io__gpiov2_ctl".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808178".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808591".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808594".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808593".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808488".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808592".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808586".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808122".
+Reading "sky130_fd_pr__dfl1sd__example_55959141808123".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808477".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808476".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808475".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808589".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808570".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808569".
+Reading "sky130_fd_io__gpiov2_amux_ctl_lshv2hv".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808588".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808587".
+Reading "sky130_fd_io__gpiov2_amux_ctl_lshv2hv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808590".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808460".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808468".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808467".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808466".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808465".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808464".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808463".
+Reading "sky130_fd_io__gpiov2_amux_ctl_ls".
+Reading "sky130_fd_io__gpiov2_amux_ctl_inv_1".
+Reading "sky130_fd_io__gpiov2_amux_ls".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808573".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808572".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808579".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808578".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808577".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808576".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808566".
+Reading "sky130_fd_pr__dfl1sd__example_5595914180868".
+Reading "sky130_fd_pr__dfl1sd2__example_5595914180869".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808565".
+Reading "sky130_fd_io__gpiov2_amx_pucsd_inv".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808441".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808571".
+Reading "sky130_fd_io__gpiov2_amx_inv4".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808567".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808568".
+Reading "sky130_fd_io__gpiov2_amux_drvr_lshv2hv".
+Reading "sky130_fd_io__gpiov2_amux_drvr_lshv2hv2".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808581".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808580".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808278".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808462".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808583".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808582".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808498".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808497".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808496".
+Reading "sky130_fd_io__gpiov2_amux_drvr_ls".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808574".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808575".
+Reading "sky130_fd_io__amx_inv1".
+Reading "sky130_fd_io__gpiov2_amux_drvr".
+Reading "sky130_fd_io__xor2_1".
+Reading "sky130_fd_io__nor2_1".
+Reading "sky130_fd_io__nand2_1".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808200".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808457".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808451".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808450".
+Reading "sky130_fd_pr__hvdfl1sd__example_5595914180894".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808584".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808455".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808447".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808445".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808248".
+Reading "sky130_fd_io__gpiov2_amux_nand5".
+Reading "sky130_fd_pr__dfm1sd__example_55959141808258".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808585".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808446".
+Reading "sky130_fd_io__gpiov2_amux_nand4".
+Reading "sky130_fd_io__gpiov2_amux_decoder".
+Reading "sky130_fd_io__gpiov2_amux_ctl_logic".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808563".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808564".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808562".
+Reading "sky130_fd_pr__hvdfm1sd2__example_55959141808251".
+Reading "sky130_fd_pr__dfm1sd2__example_55959141808561".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808560".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808558".
+Reading "sky130_fd_io__amux_switch_1v2b".
+Reading "sky130_fd_io__gpiov2_amux".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808416".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808417".
+Reading "sky130_fd_io__hvsbt_xorv2".
+Reading "sky130_fd_io__hvsbt_xor".
+Reading "sky130_fd_io__com_ctl_ls_octl".
+Reading "sky130_fd_io__gpiov2_octl".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808267".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808266".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808642".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808184".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808141".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808643".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808183".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808139".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808636".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808635".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808634".
+Reading "sky130_fd_pr__dfl1sd2__example_55959141808633".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808632".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808630".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808638".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808637".
+Reading "sky130_fd_io__gpiov2_pdpredrvr_strong_nr3".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808629".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808628".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808627".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808626".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808354".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808631".
+Reading "sky130_fd_io__gpiov2_pdpredrvr_strong_nr2".
+Reading "sky130_fd_pr__nfet_01v8__example_5595914180888".
+Reading "sky130_fd_io__gpiov2_octl_mux".
+Reading "sky130_fd_pr__via_pol1__example_55959141808322".
+Reading "sky130_fd_pr__via_pol1__example_55959141808321".
+Reading "sky130_fd_pr__via_pol1__example_55959141808320".
+Reading "sky130_fd_pr__via_pol1__example_55959141808294".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808325".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808323".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808291".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808641".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808640".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808639".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808348".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808347".
+Reading "sky130_fd_pr__hvdfl1sd__example_55959141808194".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808346".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808345".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808344".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808343".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808334".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808333".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808332".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808331".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808330".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808329".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808304".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808134".
+Reading "sky130_fd_io__tk_em1o_cdns_55959141808328".
+Reading "sky130_fd_io__tk_em1o_cdns_55959141808327".
+Reading "sky130_fd_io__com_pdpredrvr_pbiasv2".
+Reading "sky130_fd_io__gpiov2_pdpredrvr_strong".
+Reading "sky130_fd_pr__via_pol1__example_55959141808272".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808271".
+Reading "sky130_fd_pr__hvdfl1sd2__example_55959141808143".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808142".
+Reading "sky130_fd_pr__model__pfet_highvoltage__example_55959141808101".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_55959141808144".
+Reading "sky130_fd_pr__model__nfet_highvoltage__example_5595914180899".
+Reading "sky130_fd_pr__via_pol1__example_55959141808275".
+Reading "sky130_fd_pr__via_m1m2__example_55959141808276".
+Reading "sky130_fd_pr__res_generic_po__example_55959141808286".
+Reading "sky130_fd_pr__res_generic_po__example_55959141808285".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808284".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808283".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808644".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808287".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808282".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808281".
+Reading "sky130_fd_io__gpiov2_pupredrvr_strong_nd2_a".
+Reading "sky130_fd_io__gpiov2_pupredrvr_strong_nd2".
+Reading "sky130_fd_pr__via_pol1__example_55959141808297".
+Reading "sky130_fd_pr__via_pol1__example_55959141808296".
+Reading "sky130_fd_pr__via_pol1__example_55959141808295".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808293".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808292".
+Reading "sky130_fd_pr__tpl1__example_55959141808300".
+Reading "sky130_fd_pr__tpl1__example_55959141808299".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808319".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808318".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808317".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808315".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808314".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808313".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808312".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808311".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808310".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808309".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808308".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808307".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808305".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808303".
+Reading "sky130_fd_io__tk_em1s_cdns_55959141808301".
+Reading "sky130_fd_io__tk_em1o_cdns_55959141808302".
+Reading "sky130_fd_io__feascom_pupredrvr_nbiasv2".
+Reading "sky130_fd_io__gpio_pupredrvr_strongv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808361".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808360".
+Reading "sky130_fd_io__feas_com_pupredrvr_weak".
+Reading "sky130_fd_pr__via_pol1__example_5595914180854".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808363".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808362".
+Reading "sky130_fd_io__com_pupredrvr_strong_slowv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808366".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808365".
+Reading "sky130_fd_io__com_pdpredrvr_weakv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808364".
+Reading "sky130_fd_io__com_pdpredrvr_strong_slowv2".
+Reading "sky130_fd_io__gpiov2_obpredrvr".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808368".
+Reading "sky130_fd_pr__tpl1__example_55959141808625".
+Reading "sky130_fd_pr__via_pol1__example_55959141808373".
+Reading "sky130_fd_pr__tpl1__example_55959141808374".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808393".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808392".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808391".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808390".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808389".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808388".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808387".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808386".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808384".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808381".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808377".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808376".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808375".
+Reading "sky130_fd_io__gpio_dat_lsv2".
+Reading "sky130_fd_io__gpio_dat_ls_1v2".
+Reading "sky130_fd_pr__via_pol1__example_55959141808398".
+Reading "sky130_fd_pr__via_pol1__example_55959141808397".
+Reading "sky130_fd_pr__via_pol1__example_55959141808396".
+Reading "sky130_fd_pr__via_pol1__example_55959141808395".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808401".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808399".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808269".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808410".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808409".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808408".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808407".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808406".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808405".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808404".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808403".
+Reading "sky130_fd_io__com_cclat".
+Reading "sky130_fd_io__com_opath_datoev2".
+Reading "sky130_fd_io__gpiov2_octl_dat".
+Reading "sky130_fd_pr__via_pol1_centered__example_559591418080".
+Reading "sky130_fd_pr__via_l1m1__example_5595914180832".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180856".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180855".
+Reading "sky130_fd_pr__res_generic_po__example_5595914180853".
+Reading "sky130_fd_io__tk_em1s_cdns_5595914180852".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418083".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418082".
+Reading "sky130_fd_io__nfet_con_diff_wo_abt_270v2".
+Reading "sky130_fd_io__gpiov2_pddrvr_strong".
+Reading "sky130_fd_pr__via_l1m1_centered__example_559591418085".
+Reading "sky130_fd_io__pfet_con_diff_wo_abt_270v2".
+Reading "sky130_fd_io__gpio_pudrvr_strongv2".
+Reading "sky130_fd_pr__nfet_01v8__example_5595914180850".
+Reading "sky130_fd_io__gpio_pddrvr_weakv2".
+Reading "sky130_fd_io__gpio_pddrvr_strong_slowv2".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808656".
+Reading "sky130_fd_pr__hvdfm1sd__example_55959141808655".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808654".
+Reading "sky130_fd_io__com_pudrvr_weakv2".
+Reading "sky130_fd_io__com_pudrvr_strong_slowv2".
+Reading "sky130_fd_io__gpio_odrvr_subv2".
+Reading "sky130_fd_io__gpio_odrvrv2".
+Reading "sky130_fd_io__gpio_opathv2".
+Reading "sky130_fd_io__top_gpiov2".
+Reading "sky130_fd_io__overlay_gpiov2".
+Reading "sky130_ef_io__gpiov2_pad".
+Reading "sky130_ef_io__gpiov2_pad_wrapped".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808691".
+Reading "sky130_fd_pr__pfet_01v8__example_55959141808687".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808684".
+Reading "sky130_fd_pr__tpl1__example_55959141808686".
+Reading "sky130_fd_pr__tpl1__example_55959141808685".
+Reading "sky130_fd_pr__via_l1m1__example_55959141808683".
+Reading "sky130_fd_io__gnd2gnd_strap".
+Reading "sky130_fd_io__gnd2gnd_tap".
+Reading "sky130_fd_io__gnd2gnd_diff".
+Reading "sky130_fd_io__gnd2gnd_sub_dnwl".
+Reading "sky130_fd_io__gnd2gnd_120x2_lv_isosub".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808690".
+Reading "sky130_fd_pr__dftpl1s2__example_55959141808702".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808705".
+Reading "sky130_fd_pr__dfl1__example_55959141808682".
+Reading "sky130_fd_pr__dftpl1s2__example_55959141808694".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808693".
+Reading "sky130_fd_pr__dfl1__example_55959141808681".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808688".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808699".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808698".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808697".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808696".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808695".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808704".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808703".
+Reading "sky130_fd_pr__nfet_01v8__example_55959141808701".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808689".
+Reading "sky130_fd_pr__res_bent_po__example_55959141808692".
+Reading "sky130_fd_io__top_ground_lvc_wpad".
+Reading "sky130_fd_io__overlay_vssd_lvc".
+Reading "sky130_ef_io__lvc_vccdx_overlay".
+Reading "sky130_ef_io__vssd_lvc_clamped_pad".
+Reading "sky130_fd_io__overlay_vssio_hvc".
+Reading "sky130_ef_io__hvc_vssio_overlay".
+Reading "sky130_ef_io__vssio_hvc_clamped_pad".
+Reading "sky130_fd_io__hvc_clampv2".
+Reading "sky130_fd_io__top_power_hvc_wpadv2".
+Reading "sky130_fd_io__overlay_vdda_hvc".
+Reading "sky130_ef_io__vdda_hvc_clamped_pad".
+Reading "sky130_fd_io__top_power_lvc_wpad".
+Reading "sky130_fd_io__overlay_vccd_lvc".
+Reading "sky130_ef_io__vccd_lvc_clamped_pad".
+Reading "sky130_ef_io__disconnect_vdda_slice_5um".
+Reading "sky130_fd_io__overlay_vddio_hvc".
+Reading "sky130_ef_io__hvc_vddio_overlay".
+Reading "sky130_ef_io__vddio_hvc_clamped_pad".
+Reading "chip_io_gpio_connects".
+Reading "sky130_ef_io__lvc_vccdy_overlay".
+Reading "sky130_ef_io__vssd_lvc_clamped3_pad".
+Reading "sky130_ef_io__vccd_lvc_clamped3_pad".
+Reading "chip_io".
+Reading "gpio_signal_buffering".
+Reading "caravel".
+Flattening layout of tile x=0 y=0. . .
+Flattening layout of tile x=1 y=0. . .
+Flattening layout of tile x=2 y=0. . .
+Flattening layout of tile x=3 y=0. . .
+Flattening layout of tile x=4 y=0. . .
+Flattening layout of tile x=5 y=0. . .
+Flattening layout of tile x=0 y=1. . .
+Flattening layout of tile x=1 y=1. . .
+Flattening layout of tile x=2 y=1. . .
+Flattening layout of tile x=3 y=1. . .
+Flattening layout of tile x=4 y=1. . .
+Flattening layout of tile x=5 y=1. . .
+Flattening layout of tile x=0 y=2. . .
+Flattening layout of tile x=1 y=2. . .
+Flattening layout of tile x=2 y=2. . .
+Flattening layout of tile x=3 y=2. . .
+Flattening layout of tile x=4 y=2. . .
+Flattening layout of tile x=5 y=2. . .
+Flattening layout of tile x=0 y=3. . .
+Flattening layout of tile x=1 y=3. . .
+Flattening layout of tile x=2 y=3. . .
+Flattening layout of tile x=3 y=3. . .
+Flattening layout of tile x=4 y=3. . .
+Flattening layout of tile x=5 y=3. . .
+Flattening layout of tile x=0 y=4. . .
+Flattening layout of tile x=1 y=4. . .
+Flattening layout of tile x=2 y=4. . .
+Flattening layout of tile x=3 y=4. . .
+Flattening layout of tile x=4 y=4. . .
+Flattening layout of tile x=5 y=4. . .
+Flattening layout of tile x=0 y=5. . .
+Flattening layout of tile x=1 y=5. . .
+Flattening layout of tile x=2 y=5. . .
+Flattening layout of tile x=3 y=5. . .
+Flattening layout of tile x=4 y=5. . .
+Flattening layout of tile x=5 y=5. . .
+Flattening layout of tile x=0 y=6. . .
+Flattening layout of tile x=1 y=6. . .
+Flattening layout of tile x=2 y=6. . .
+Flattening layout of tile x=3 y=6. . .
+Flattening layout of tile x=4 y=6. . .
+Flattening layout of tile x=5 y=6. . .
+Flattening layout of tile x=0 y=7. . .
+Flattening layout of tile x=1 y=7. . .
+Flattening layout of tile x=2 y=7. . .
+Flattening layout of tile x=3 y=7. . .
+Flattening layout of tile x=4 y=7. . .
+Flattening layout of tile x=5 y=7. . .
+Ended: 11/15/2022 21:23:25
diff --git a/tapeout/logs/fill_intermediate.log b/tapeout/logs/fill_intermediate.log
new file mode 100644
index 0000000..9f50182
--- /dev/null
+++ b/tapeout/logs/fill_intermediate.log
@@ -0,0 +1,18701 @@
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Starting magic under Tcl interpreter
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Using the terminal as the console.
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Starting magic under Tcl interpreter
+Using NULL graphics device.
+Using the terminal as the console.
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Starting magic under Tcl interpreter
+Starting magic under Tcl interpreter
+Using NULL graphics device.
+Using the terminal as the console.
+Using the terminal as the console.
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Using NULL graphics device.
+Using NULL graphics device.
+Using NULL graphics device.
+Using NULL graphics device.
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Starting magic under Tcl interpreter
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using the terminal as the console.
+Using NULL graphics device.
+Using NULL graphics device.
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Starting magic under Tcl interpreter
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Using the terminal as the console.
+Starting magic under Tcl interpreter
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Using the terminal as the console.
+Starting magic under Tcl interpreter
+Starting magic under Tcl interpreter
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Using the terminal as the console.
+Using the terminal as the console.
+Starting magic under Tcl interpreter
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Using the terminal as the console.
+Starting magic under Tcl interpreter
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Using the terminal as the console.
+Starting magic under Tcl interpreter
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Using the terminal as the console.
+Starting magic under Tcl interpreter
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Using the terminal as the console.
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Starting magic under Tcl interpreter
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Starting magic under Tcl interpreter
+Using NULL graphics device.
+Using the terminal as the console.
+Starting magic under Tcl interpreter
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Using the terminal as the console.
+Using the terminal as the console.
+Using NULL graphics device.
+Starting magic under Tcl interpreter
+Using NULL graphics device.
+Using NULL graphics device.
+Using the terminal as the console.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Using NULL graphics device.
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Using NULL graphics device.
+Using NULL graphics device.
+Starting magic under Tcl interpreter
+Starting magic under Tcl interpreter
+Using NULL graphics device.
+Using the terminal as the console.
+Using the terminal as the console.
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Using NULL graphics device.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Using NULL graphics device.
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Using NULL graphics device.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Using NULL graphics device.
+Using NULL graphics device.
+Using NULL graphics device.
+Using NULL graphics device.
+Starting magic under Tcl interpreter
+Using NULL graphics device.
+Using the terminal as the console.
+Using NULL graphics device.
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+Sourcing design .magicrc for technology sky130A ...
+Sourcing design .magicrc for technology sky130A ...
+Sourcing design .magicrc for technology sky130A ...
+Sourcing design .magicrc for technology sky130A ...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+2 Magic internal units = 1 Lambda
+2 Magic internal units = 1 Lambda
+2 Magic internal units = 1 Lambda
+2 Magic internal units = 1 Lambda
+2 Magic internal units = 1 Lambda
+Sourcing design .magicrc for technology sky130A ...
+Processing system .magicrc file
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+Sourcing design .magicrc for technology sky130A ...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+2 Magic internal units = 1 Lambda
+2 Magic internal units = 1 Lambda
+Sourcing design .magicrc for technology sky130A ...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Sourcing design .magicrc for technology sky130A ...
+Processing system .magicrc file
+2 Magic internal units = 1 Lambda
+2 Magic internal units = 1 Lambda
+2 Magic internal units = 1 Lambda
+Sourcing design .magicrc for technology sky130A ...
+Sourcing design .magicrc for technology sky130A ...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Sourcing design .magicrc for technology sky130A ...
+Sourcing design .magicrc for technology sky130A ...
+Sourcing design .magicrc for technology sky130A ...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+2 Magic internal units = 1 Lambda
+2 Magic internal units = 1 Lambda
+2 Magic internal units = 1 Lambda
+2 Magic internal units = 1 Lambda
+Sourcing design .magicrc for technology sky130A ...
+Sourcing design .magicrc for technology sky130A ...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Sourcing design .magicrc for technology sky130A ...
+Sourcing design .magicrc for technology sky130A ...
+Sourcing design .magicrc for technology sky130A ...
+Sourcing design .magicrc for technology sky130A ...
+Sourcing design .magicrc for technology sky130A ...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+2 Magic internal units = 1 Lambda
+2 Magic internal units = 1 Lambda
+2 Magic internal units = 1 Lambda
+2 Magic internal units = 1 Lambda
+2 Magic internal units = 1 Lambda
+2 Magic internal units = 1 Lambda
+2 Magic internal units = 1 Lambda
+2 Magic internal units = 1 Lambda
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Sourcing design .magicrc for technology sky130A ...
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+2 Magic internal units = 1 Lambda
+Sourcing design .magicrc for technology sky130A ...
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Processing system .magicrc file
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+Scaled tech values by 2 / 1 to match internal grid scaling
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+Loading sky130A Device Generator Menu ...
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+Scaled tech values by 2 / 1 to match internal grid scaling
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Scaled tech values by 2 / 1 to match internal grid scaling
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+Loading sky130A Device Generator Menu ...
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+Scaled tech values by 2 / 1 to match internal grid scaling
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+Loading sky130A Device Generator Menu ...
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Loading sky130A Device Generator Menu ...
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+Loading sky130A Device Generator Menu ...
+The following types are not handled by extraction and will be treated as non-electrical types:
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+ ubm
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Scaled tech values by 2 / 1 to match internal grid scaling
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Loading sky130A Device Generator Menu ...
+Scaled tech values by 2 / 1 to match internal grid scaling
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading sky130A Device Generator Menu ...
+Loading sky130A Device Generator Menu ...
+Scaled tech values by 2 / 1 to match internal grid scaling
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Loading sky130A Device Generator Menu ...
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Scaled tech values by 2 / 1 to match internal grid scaling
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Loading sky130A Device Generator Menu ...
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Scaled tech values by 2 / 1 to match internal grid scaling
+Scaled tech values by 2 / 1 to match internal grid scaling
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading sky130A Device Generator Menu ...
+Loading sky130A Device Generator Menu ...
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Loading sky130A Device Generator Menu ...
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Scaled tech values by 2 / 1 to match internal grid scaling
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading sky130A Device Generator Menu ...
+caravel_00069f13_fill_pattern_4_3: 10000 rects
+Loading sky130A Device Generator Menu ...
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Scaled tech values by 2 / 1 to match internal grid scaling
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Scaled tech values by 2 / 1 to match internal grid scaling
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Loading sky130A Device Generator Menu ...
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_00069f13_fill_pattern_4_3: 20000 rects
+caravel_00069f13_fill_pattern_0_6: 10000 rects
+caravel_00069f13_fill_pattern_4_3: 30000 rects
+caravel_00069f13_fill_pattern_1_5: 10000 rects
+caravel_00069f13_fill_pattern_3_7: 10000 rects
+caravel_00069f13_fill_pattern_0_2: 10000 rects
+caravel_00069f13_fill_pattern_0_6: 20000 rects
+caravel_00069f13_fill_pattern_4_3: 40000 rects
+caravel_00069f13_fill_pattern_4_2: 10000 rects
+caravel_00069f13_fill_pattern_1_5: 20000 rects
+caravel_00069f13_fill_pattern_3_7: 20000 rects
+caravel_00069f13_fill_pattern_0_0: 10000 rects
+caravel_00069f13_fill_pattern_0_2: 20000 rects
+caravel_00069f13_fill_pattern_4_7: 10000 rects
+caravel_00069f13_fill_pattern_2_4: 10000 rects
+caravel_00069f13_fill_pattern_4_3: 50000 rects
+caravel_00069f13_fill_pattern_0_6: 30000 rects
+caravel_00069f13_fill_pattern_0_7: 10000 rects
+caravel_00069f13_fill_pattern_4_2: 20000 rects
+caravel_00069f13_fill_pattern_1_5: 30000 rects
+caravel_00069f13_fill_pattern_0_0: 20000 rects
+caravel_00069f13_fill_pattern_0_2: 30000 rects
+caravel_00069f13_fill_pattern_5_2: 10000 rects
+caravel_00069f13_fill_pattern_3_7: 30000 rects
+caravel_00069f13_fill_pattern_4_7: 20000 rects
+caravel_00069f13_fill_pattern_5_3: 10000 rects
+caravel_00069f13_fill_pattern_4_3: 60000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+caravel_00069f13_fill_pattern_4_6: 10000 rects
+caravel_00069f13_fill_pattern_4_2: 30000 rects
+caravel_00069f13_fill_pattern_1_5: 40000 rects
+caravel_00069f13_fill_pattern_0_2: 40000 rects
+caravel_00069f13_fill_pattern_2_4: 20000 rects
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+caravel_00069f13_fill_pattern_0_7: 20000 rects
+caravel_00069f13_fill_pattern_0_6: 40000 rects
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_00069f13_fill_pattern_4_3: 70000 rects
+caravel_00069f13_fill_pattern_1_1: 10000 rects
+caravel_00069f13_fill_pattern_3_7: 40000 rects
+caravel_00069f13_fill_pattern_4_7: 30000 rects
+caravel_00069f13_fill_pattern_4_6: 20000 rects
+caravel_00069f13_fill_pattern_5_3: 20000 rects
+caravel_00069f13_fill_pattern_4_2: 40000 rects
+caravel_00069f13_fill_pattern_5_2: 20000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+caravel_00069f13_fill_pattern_1_5: 50000 rects
+caravel_00069f13_fill_pattern_0_2: 50000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+caravel_00069f13_fill_pattern_1_7: 10000 rects
+caravel_00069f13_fill_pattern_4_7: 40000 rects
+caravel_00069f13_fill_pattern_0_0: 30000 rects
+caravel_00069f13_fill_pattern_4_2: 50000 rects
+caravel_00069f13_fill_pattern_0_2: 60000 rects
+Scaled tech values by 2 / 1 to match internal grid scaling
+caravel_00069f13_fill_pattern_3_7: 50000 rects
+caravel_00069f13_fill_pattern_2_4: 30000 rects
+Loading sky130A Device Generator Menu ...
+caravel_00069f13_fill_pattern_0_6: 50000 rects
+caravel_00069f13_fill_pattern_4_4: 10000 rects
+caravel_00069f13_fill_pattern_1_5: 60000 rects
+Scaled tech values by 2 / 1 to match internal grid scaling
+caravel_00069f13_fill_pattern_0_7: 30000 rects
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+Loading sky130A Device Generator Menu ...
+caravel_00069f13_fill_pattern_0_4: 10000 rects
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_00069f13_fill_pattern_4_3: 80000 rects
+caravel_00069f13_fill_pattern_5_3: 30000 rects
+caravel_00069f13_fill_pattern_1_1: 20000 rects
+caravel_00069f13_fill_pattern_4_7: 50000 rects
+caravel_00069f13_fill_pattern_5_2: 30000 rects
+caravel_00069f13_fill_pattern_4_2: 60000 rects
+caravel_00069f13_fill_pattern_3_7: 60000 rects
+caravel_00069f13_fill_pattern_0_2: 70000 rects
+caravel_00069f13_fill_pattern_1_5: 70000 rects
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+caravel_00069f13_fill_pattern_5_3: 40000 rects
+caravel_00069f13_fill_pattern_0_4: 20000 rects
+caravel_00069f13_fill_pattern_4_7: 60000 rects
+caravel_00069f13_fill_pattern_4_6: 30000 rects
+caravel_00069f13_fill_pattern_1_7: 20000 rects
+caravel_00069f13_fill_pattern_4_2: 70000 rects
+caravel_00069f13_fill_pattern_4_4: 20000 rects
+caravel_00069f13_fill_pattern_0_6: 60000 rects
+caravel_00069f13_fill_pattern_0_7: 40000 rects
+caravel_00069f13_fill_pattern_2_4: 40000 rects
+caravel_00069f13_fill_pattern_3_7: 70000 rects
+caravel_00069f13_fill_pattern_4_3: 90000 rects
+caravel_00069f13_fill_pattern_5_2: 40000 rects
+caravel_00069f13_fill_pattern_5_3: 50000 rects
+caravel_00069f13_fill_pattern_0_2: 80000 rects
+caravel_00069f13_fill_pattern_1_5: 80000 rects
+caravel_00069f13_fill_pattern_4_7: 70000 rects
+caravel_00069f13_fill_pattern_1_1: 30000 rects
+caravel_00069f13_fill_pattern_4_2: 80000 rects
+caravel_00069f13_fill_pattern_0_0: 50000 rects
+caravel_00069f13_fill_pattern_4_6: 40000 rects
+caravel_00069f13_fill_pattern_4_3: 100000 rects
+caravel_00069f13_fill_pattern_5_3: 60000 rects
+caravel_00069f13_fill_pattern_3_4: 10000 rects
+caravel_00069f13_fill_pattern_0_7: 50000 rects
+caravel_00069f13_fill_pattern_4_7: 80000 rects
+caravel_00069f13_fill_pattern_1_5: 90000 rects
+caravel_00069f13_fill_pattern_1_7: 30000 rects
+caravel_00069f13_fill_pattern_3_7: 80000 rects
+caravel_00069f13_fill_pattern_2_6: 10000 rects
+caravel_00069f13_fill_pattern_0_6: 70000 rects
+caravel_00069f13_fill_pattern_2_4: 50000 rects
+caravel_00069f13_fill_pattern_4_2: 90000 rects
+caravel_00069f13_fill_pattern_5_2: 50000 rects
+caravel_00069f13_fill_pattern_0_2: 90000 rects
+caravel_00069f13_fill_pattern_1_3: 10000 rects
+caravel_00069f13_fill_pattern_5_3: 70000 rects
+caravel_00069f13_fill_pattern_3_4: 20000 rects
+caravel_00069f13_fill_pattern_1_1: 40000 rects
+caravel_00069f13_fill_pattern_1_5: 100000 rects
+caravel_00069f13_fill_pattern_4_3: 110000 rects
+caravel_00069f13_fill_pattern_4_7: 90000 rects
+caravel_00069f13_fill_pattern_0_4: 30000 rects
+caravel_00069f13_fill_pattern_2_6: 20000 rects
+caravel_00069f13_fill_pattern_4_2: 100000 rects
+caravel_00069f13_fill_pattern_4_6: 50000 rects
+caravel_00069f13_fill_pattern_0_7: 60000 rects
+caravel_00069f13_fill_pattern_3_7: 90000 rects
+caravel_00069f13_fill_pattern_0_0: 60000 rects
+caravel_00069f13_fill_pattern_0_2: 100000 rects
+caravel_00069f13_fill_pattern_0_6: 80000 rects
+caravel_00069f13_fill_pattern_1_7: 40000 rects
+caravel_00069f13_fill_pattern_5_3: 80000 rects
+caravel_00069f13_fill_pattern_5_2: 60000 rects
+caravel_00069f13_fill_pattern_4_4: 30000 rects
+caravel_00069f13_fill_pattern_1_5: 110000 rects
+caravel_00069f13_fill_pattern_2_4: 60000 rects
+caravel_00069f13_fill_pattern_4_7: 100000 rects
+caravel_00069f13_fill_pattern_4_2: 110000 rects
+caravel_00069f13_fill_pattern_3_0: 10000 rects
+caravel_00069f13_fill_pattern_1_1: 50000 rects
+caravel_00069f13_fill_pattern_0_2: 110000 rects
+caravel_00069f13_fill_pattern_4_3: 120000 rects
+caravel_00069f13_fill_pattern_0_4: 40000 rects
+caravel_00069f13_fill_pattern_4_6: 60000 rects
+caravel_00069f13_fill_pattern_1_5: 120000 rects
+caravel_00069f13_fill_pattern_5_3: 90000 rects
+caravel_00069f13_fill_pattern_1_3: 20000 rects
+caravel_00069f13_fill_pattern_0_7: 70000 rects
+caravel_00069f13_fill_pattern_4_2: 120000 rects
+caravel_00069f13_fill_pattern_3_7: 100000 rects
+caravel_00069f13_fill_pattern_4_7: 110000 rects
+caravel_00069f13_fill_pattern_5_2: 70000 rects
+caravel_00069f13_fill_pattern_0_6: 90000 rects
+caravel_00069f13_fill_pattern_4_4: 40000 rects
+caravel_00069f13_fill_pattern_0_0: 70000 rects
+caravel_00069f13_fill_pattern_0_2: 120000 rects
+caravel_00069f13_fill_pattern_1_7: 50000 rects
+caravel_00069f13_fill_pattern_2_4: 70000 rects
+caravel_00069f13_fill_pattern_1_5: 130000 rects
+caravel_00069f13_fill_pattern_4_2: 130000 rects
+caravel_00069f13_fill_pattern_3_0: 20000 rects
+caravel_00069f13_fill_pattern_5_3: 100000 rects
+caravel_00069f13_fill_pattern_0_4: 50000 rects
+caravel_00069f13_fill_pattern_1_1: 60000 rects
+caravel_00069f13_fill_pattern_2_6: 30000 rects
+caravel_00069f13_fill_pattern_0_2: 130000 rects
+caravel_00069f13_fill_pattern_3_4: 30000 rects
+caravel_00069f13_fill_pattern_4_7: 120000 rects
+caravel_00069f13_fill_pattern_4_6: 70000 rects
+caravel_00069f13_fill_pattern_4_3: 130000 rects
+caravel_00069f13_fill_pattern_0_7: 80000 rects
+caravel_00069f13_fill_pattern_5_2: 80000 rects
+caravel_00069f13_fill_pattern_1_5: 140000 rects
+caravel_00069f13_fill_pattern_3_7: 110000 rects
+caravel_00069f13_fill_pattern_4_4: 50000 rects
+caravel_00069f13_fill_pattern_0_6: 100000 rects
+caravel_00069f13_fill_pattern_1_7: 60000 rects
+caravel_00069f13_fill_pattern_0_4: 60000 rects
+caravel_00069f13_fill_pattern_2_6: 40000 rects
+caravel_00069f13_fill_pattern_0_0: 80000 rects
+caravel_00069f13_fill_pattern_2_4: 80000 rects
+caravel_00069f13_fill_pattern_0_2: 140000 rects
+caravel_00069f13_fill_pattern_4_2: 140000 rects
+caravel_00069f13_fill_pattern_3_4: 40000 rects
+caravel_00069f13_fill_pattern_1_3: 30000 rects
+caravel_00069f13_fill_pattern_0_7: 90000 rects
+caravel_00069f13_fill_pattern_5_3: 110000 rects
+caravel_00069f13_fill_pattern_1_1: 70000 rects
+caravel_00069f13_fill_pattern_1_5: 150000 rects
+caravel_00069f13_fill_pattern_4_3: 140000 rects
+caravel_00069f13_fill_pattern_0_4: 70000 rects
+caravel_00069f13_fill_pattern_4_6: 80000 rects
+caravel_00069f13_fill_pattern_5_2: 90000 rects
+caravel_00069f13_fill_pattern_0_2: 150000 rects
+caravel_00069f13_fill_pattern_2_6: 50000 rects
+caravel_00069f13_fill_pattern_0_7: 100000 rects
+caravel_00069f13_fill_pattern_3_7: 120000 rects
+caravel_00069f13_fill_pattern_1_2: 10000 rects
+caravel_00069f13_fill_pattern_4_4: 60000 rects
+caravel_00069f13_fill_pattern_4_7: 130000 rects
+caravel_00069f13_fill_pattern_3_4: 50000 rects
+caravel_00069f13_fill_pattern_0_6: 110000 rects
+caravel_00069f13_fill_pattern_1_7: 70000 rects
+caravel_00069f13_fill_pattern_2_4: 90000 rects
+caravel_00069f13_fill_pattern_0_4: 80000 rects
+caravel_00069f13_fill_pattern_5_3: 120000 rects
+caravel_00069f13_fill_pattern_4_2: 150000 rects
+caravel_00069f13_fill_pattern_0_2: 160000 rects
+caravel_00069f13_fill_pattern_0_0: 90000 rects
+caravel_00069f13_fill_pattern_1_1: 80000 rects
+caravel_00069f13_fill_pattern_3_4: 60000 rects
+caravel_00069f13_fill_pattern_2_6: 60000 rects
+caravel_00069f13_fill_pattern_1_5: 160000 rects
+caravel_00069f13_fill_pattern_0_7: 110000 rects
+caravel_00069f13_fill_pattern_4_3: 150000 rects
+caravel_00069f13_fill_pattern_1_3: 40000 rects
+caravel_00069f13_fill_pattern_5_2: 100000 rects
+caravel_00069f13_fill_pattern_3_7: 130000 rects
+caravel_00069f13_fill_pattern_4_4: 70000 rects
+caravel_00069f13_fill_pattern_4_6: 90000 rects
+caravel_00069f13_fill_pattern_1_7: 80000 rects
+caravel_00069f13_fill_pattern_0_2: 170000 rects
+caravel_00069f13_fill_pattern_3_4: 70000 rects
+caravel_00069f13_fill_pattern_0_6: 120000 rects
+caravel_00069f13_fill_pattern_0_7: 120000 rects
+caravel_00069f13_fill_pattern_0_4: 90000 rects
+caravel_00069f13_fill_pattern_4_7: 140000 rects
+caravel_00069f13_fill_pattern_2_4: 100000 rects
+caravel_00069f13_fill_pattern_5_3: 130000 rects
+caravel_00069f13_fill_pattern_5_5: 10000 rects
+caravel_00069f13_fill_pattern_3_0: 30000 rects
+caravel_00069f13_fill_pattern_4_2: 160000 rects
+caravel_00069f13_fill_pattern_2_6: 70000 rects
+caravel_00069f13_fill_pattern_1_1: 90000 rects
+caravel_00069f13_fill_pattern_1_2: 20000 rects
+caravel_00069f13_fill_pattern_1_5: 170000 rects
+caravel_00069f13_fill_pattern_4_3: 160000 rects
+caravel_00069f13_fill_pattern_0_0: 100000 rects
+caravel_00069f13_fill_pattern_3_4: 80000 rects
+caravel_00069f13_fill_pattern_0_2: 180000 rects
+caravel_00069f13_fill_pattern_3_7: 140000 rects
+caravel_00069f13_fill_pattern_1_3: 50000 rects
+caravel_00069f13_fill_pattern_5_2: 110000 rects
+caravel_00069f13_fill_pattern_1_7: 90000 rects
+caravel_00069f13_fill_pattern_4_4: 80000 rects
+caravel_00069f13_fill_pattern_0_7: 130000 rects
+caravel_00069f13_fill_pattern_4_7: 150000 rects
+caravel_00069f13_fill_pattern_0_6: 130000 rects
+caravel_00069f13_fill_pattern_5_5: 20000 rects
+caravel_00069f13_fill_pattern_4_6: 100000 rects
+caravel_00069f13_fill_pattern_0_4: 100000 rects
+caravel_00069f13_fill_pattern_3_4: 90000 rects
+caravel_00069f13_fill_pattern_3_0: 40000 rects
+caravel_00069f13_fill_pattern_0_2: 190000 rects
+caravel_00069f13_fill_pattern_2_4: 110000 rects
+caravel_00069f13_fill_pattern_2_6: 80000 rects
+caravel_00069f13_fill_pattern_5_3: 140000 rects
+caravel_00069f13_fill_pattern_1_5: 180000 rects
+caravel_00069f13_fill_pattern_1_1: 100000 rects
+caravel_00069f13_fill_pattern_4_3: 170000 rects
+caravel_00069f13_fill_pattern_3_7: 150000 rects
+caravel_00069f13_fill_pattern_1_3: 60000 rects
+caravel_00069f13_fill_pattern_1_7: 100000 rects
+caravel_00069f13_fill_pattern_5_2: 120000 rects
+caravel_00069f13_fill_pattern_0_7: 140000 rects
+caravel_00069f13_fill_pattern_0_0: 110000 rects
+caravel_00069f13_fill_pattern_3_4: 100000 rects
+caravel_00069f13_fill_pattern_4_2: 170000 rects
+caravel_00069f13_fill_pattern_4_4: 90000 rects
+caravel_00069f13_fill_pattern_0_2: 200000 rects
+caravel_00069f13_fill_pattern_2_6: 90000 rects
+caravel_00069f13_fill_pattern_1_5: 190000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00069f13_fill_pattern_0_6: 140000 rects
+caravel_00069f13_fill_pattern_5_3: 150000 rects
+caravel_00069f13_fill_pattern_3_0: 50000 rects
+caravel_00069f13_fill_pattern_0_4: 110000 rects
+caravel_00069f13_fill_pattern_4_7: 160000 rects
+caravel_00069f13_fill_pattern_3_4: 110000 rects
+caravel_00069f13_fill_pattern_4_6: 110000 rects
+caravel_00069f13_fill_pattern_1_2: 30000 rects
+caravel_00069f13_fill_pattern_2_4: 120000 rects
+caravel_00069f13_fill_pattern_4_3: 180000 rects
+caravel_00069f13_fill_pattern_1_1: 110000 rects
+caravel_00069f13_fill_pattern_1_3: 70000 rects
+caravel_00069f13_fill_pattern_0_2: 210000 rects
+caravel_00069f13_fill_pattern_1_5: 200000 rects
+caravel_00069f13_fill_pattern_1_7: 110000 rects
+caravel_00069f13_fill_pattern_0_7: 150000 rects
+caravel_00069f13_fill_pattern_2_6: 100000 rects
+caravel_00069f13_fill_pattern_3_7: 160000 rects
+caravel_00069f13_fill_pattern_3_4: 120000 rects
+caravel_00069f13_fill_pattern_4_4: 100000 rects
+caravel_00069f13_fill_pattern_5_3: 160000 rects
+caravel_00069f13_fill_pattern_0_0: 120000 rects
+caravel_00069f13_fill_pattern_5_2: 130000 rects
+caravel_00069f13_fill_pattern_4_2: 180000 rects
+caravel_00069f13_fill_pattern_0_6: 150000 rects
+caravel_00069f13_fill_pattern_3_0: 60000 rects
+caravel_00069f13_fill_pattern_0_4: 120000 rects
+caravel_00069f13_fill_pattern_1_5: 210000 rects
+caravel_00069f13_fill_pattern_3_4: 130000 rects
+caravel_00069f13_fill_pattern_4_3: 190000 rects
+caravel_00069f13_fill_pattern_1_3: 80000 rects
+caravel_00069f13_fill_pattern_2_1: 10000 rects
+caravel_00069f13_fill_pattern_0_2: 220000 rects
+caravel_00069f13_fill_pattern_2_4: 130000 rects
+caravel_00069f13_fill_pattern_0_7: 160000 rects
+caravel_00069f13_fill_pattern_2_6: 110000 rects
+caravel_00069f13_fill_pattern_4_6: 120000 rects
+caravel_00069f13_fill_pattern_5_3: 170000 rects
+caravel_00069f13_fill_pattern_1_2: 40000 rects
+caravel_00069f13_fill_pattern_3_7: 170000 rects
+caravel_00069f13_fill_pattern_1_7: 120000 rects
+caravel_00069f13_fill_pattern_4_4: 110000 rects
+caravel_00069f13_fill_pattern_5_5: 30000 rects
+caravel_00069f13_fill_pattern_3_4: 140000 rects
+caravel_00069f13_fill_pattern_3_0: 70000 rects
+caravel_00069f13_fill_pattern_0_0: 130000 rects
+caravel_00069f13_fill_pattern_1_1: 120000 rects
+caravel_00069f13_fill_pattern_1_5: 220000 rects
+caravel_00069f13_fill_pattern_0_6: 160000 rects
+caravel_00069f13_fill_pattern_4_2: 190000 rects
+caravel_00069f13_fill_pattern_0_4: 130000 rects
+caravel_00069f13_fill_pattern_5_2: 140000 rects
+caravel_00069f13_fill_pattern_2_1: 20000 rects
+caravel_00069f13_fill_pattern_4_3: 200000 rects
+caravel_00069f13_fill_pattern_3_4: 150000 rects
+caravel_00069f13_fill_pattern_0_2: 230000 rects
+caravel_00069f13_fill_pattern_4_7: 170000 rects
+caravel_00069f13_fill_pattern_1_3: 90000 rects
+caravel_00069f13_fill_pattern_5_3: 180000 rects
+caravel_00069f13_fill_pattern_0_7: 170000 rects
+caravel_00069f13_fill_pattern_2_4: 140000 rects
+caravel_00069f13_fill_pattern_1_2: 50000 rects
+caravel_00069f13_fill_pattern_5_5: 40000 rects
+caravel_00069f13_fill_pattern_1_5: 230000 rects
+caravel_00069f13_fill_pattern_1_7: 130000 rects
+caravel_00069f13_fill_pattern_2_6: 120000 rects
+caravel_00069f13_fill_pattern_4_4: 120000 rects
+caravel_00069f13_fill_pattern_3_7: 180000 rects
+caravel_00069f13_fill_pattern_3_0: 80000 rects
+caravel_00069f13_fill_pattern_3_4: 160000 rects
+caravel_00069f13_fill_pattern_0_2: 240000 rects
+caravel_00069f13_fill_pattern_1_1: 130000 rects
+caravel_00069f13_fill_pattern_0_4: 140000 rects
+caravel_00069f13_fill_pattern_4_6: 130000 rects
+caravel_00069f13_fill_pattern_0_6: 170000 rects
+caravel_00069f13_fill_pattern_0_0: 140000 rects
+caravel_00069f13_fill_pattern_4_2: 200000 rects
+caravel_00069f13_fill_pattern_1_5: 240000 rects
+caravel_00069f13_fill_pattern_4_3: 210000 rects
+caravel_00069f13_fill_pattern_5_5: 50000 rects
+caravel_00069f13_fill_pattern_5_2: 150000 rects
+caravel_00069f13_fill_pattern_0_2: 250000 rects
+caravel_00069f13_fill_pattern_5_3: 190000 rects
+caravel_00069f13_fill_pattern_3_4: 170000 rects
+caravel_00069f13_fill_pattern_1_7: 140000 rects
+ Generating output for cell caravel_00069f13_fill_pattern_5_7
+caravel_00069f13_fill_pattern_4_4: 130000 rects
+caravel_00069f13_fill_pattern_0_7: 180000 rects
+caravel_00069f13_fill_pattern_1_3: 100000 rects
+caravel_00069f13_fill_pattern_2_4: 150000 rects
+caravel_00069f13_fill_pattern_1_2: 60000 rects
+caravel_00069f13_fill_pattern_2_6: 130000 rects
+caravel_00069f13_fill_pattern_1_5: 250000 rects
+caravel_00069f13_fill_pattern_0_4: 150000 rects
+caravel_00069f13_fill_pattern_3_7: 190000 rects
+caravel_00069f13_fill_pattern_0_6: 180000 rects
+caravel_00069f13_fill_pattern_3_1: 10000 rects
+caravel_00069f13_fill_pattern_1_1: 140000 rects
+caravel_00069f13_fill_pattern_3_0: 90000 rects
+caravel_00069f13_fill_pattern_0_0: 150000 rects
+caravel_00069f13_fill_pattern_0_2: 260000 rects
+caravel_00069f13_fill_pattern_4_7: 180000 rects
+caravel_00069f13_fill_pattern_5_5: 60000 rects
+caravel_00069f13_fill_pattern_4_3: 220000 rects
+caravel_00069f13_fill_pattern_4_6: 140000 rects
+caravel_00069f13_fill_pattern_0_7: 190000 rects
+caravel_00069f13_fill_pattern_1_7: 150000 rects
+caravel_00069f13_fill_pattern_1_5: 260000 rects
+caravel_00069f13_fill_pattern_3_4: 180000 rects
+caravel_00069f13_fill_pattern_4_2: 210000 rects
+caravel_00069f13_fill_pattern_5_2: 160000 rects
+caravel_00069f13_fill_pattern_4_4: 140000 rects
+caravel_00069f13_fill_pattern_2_4: 160000 rects
+caravel_00069f13_fill_pattern_2_6: 140000 rects
+caravel_00069f13_fill_pattern_1_2: 70000 rects
+caravel_00069f13_fill_pattern_2_1: 30000 rects
+caravel_00069f13_fill_pattern_1_3: 110000 rects
+caravel_00069f13_fill_pattern_5_3: 200000 rects
+caravel_00069f13_fill_pattern_3_1: 20000 rects
+caravel_00069f13_fill_pattern_0_6: 190000 rects
+caravel_00069f13_fill_pattern_0_4: 160000 rects
+caravel_00069f13_fill_pattern_1_5: 270000 rects
+caravel_00069f13_fill_pattern_1_1: 150000 rects
+caravel_00069f13_fill_pattern_0_2: 270000 rects
+caravel_00069f13_fill_pattern_3_7: 200000 rects
+caravel_00069f13_fill_pattern_3_0: 100000 rects
+caravel_00069f13_fill_pattern_1_7: 160000 rects
+caravel_00069f13_fill_pattern_0_0: 160000 rects
+caravel_00069f13_fill_pattern_5_5: 70000 rects
+caravel_00069f13_fill_pattern_4_3: 230000 rects
+caravel_00069f13_fill_pattern_3_4: 190000 rects
+caravel_00069f13_fill_pattern_0_7: 200000 rects
+caravel_00069f13_fill_pattern_4_7: 190000 rects
+caravel_00069f13_fill_pattern_4_6: 150000 rects
+caravel_00069f13_fill_pattern_4_4: 150000 rects
+caravel_00069f13_fill_pattern_5_2: 170000 rects
+caravel_00069f13_fill_pattern_0_4: 170000 rects
+caravel_00069f13_fill_pattern_1_5: 280000 rects
+caravel_00069f13_fill_pattern_2_1: 40000 rects
+caravel_00069f13_fill_pattern_2_4: 170000 rects
+caravel_00069f13_fill_pattern_2_6: 150000 rects
+caravel_00069f13_fill_pattern_3_4: 200000 rects
+caravel_00069f13_fill_pattern_4_2: 220000 rects
+caravel_00069f13_fill_pattern_0_6: 200000 rects
+caravel_00069f13_fill_pattern_1_2: 80000 rects
+caravel_00069f13_fill_pattern_0_2: 280000 rects
+caravel_00069f13_fill_pattern_1_3: 120000 rects
+caravel_00069f13_fill_pattern_3_0: 110000 rects
+caravel_00069f13_fill_pattern_1_1: 160000 rects
+caravel_00069f13_fill_pattern_4_3: 240000 rects
+caravel_00069f13_fill_pattern_5_3: 210000 rects
+caravel_00069f13_fill_pattern_1_7: 170000 rects
+caravel_00069f13_fill_pattern_5_5: 80000 rects
+caravel_00069f13_fill_pattern_0_4: 180000 rects
+caravel_00069f13_fill_pattern_0_0: 170000 rects
+caravel_00069f13_fill_pattern_1_5: 290000 rects
+caravel_00069f13_fill_pattern_0_7: 210000 rects
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+Ended: 11/15/2022 21:23:28
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+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
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+caravel_00069f13_fill_pattern_4_7: 450000 rects
+caravel_00069f13_fill_pattern_0_2: 680000 rects
+Processing system .magicrc file
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+caravel_00069f13_fill_pattern_3_1: 390000 rects
+caravel_00069f13_fill_pattern_5_3: 500000 rects
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+caravel_00069f13_fill_pattern_3_5: 430000 rects
+caravel_00069f13_fill_pattern_4_4: 590000 rects
+Sourcing design .magicrc for technology sky130A ...
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+caravel_00069f13_fill_pattern_1_5: 740000 rects
+2 Magic internal units = 1 Lambda
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+caravel_00069f13_fill_pattern_2_5: 370000 rects
+caravel_00069f13_fill_pattern_1_2: 440000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
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+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
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+caravel_00069f13_fill_pattern_0_7: 560000 rects
+caravel_00069f13_fill_pattern_3_0: 570000 rects
+caravel_00069f13_fill_pattern_3_5: 550000 rects
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+caravel_00069f13_fill_pattern_2_2: 310000 rects
+caravel_00069f13_fill_pattern_1_6: 280000 rects
+Scaled tech values by 2 / 1 to match internal grid scaling
+caravel_00069f13_fill_pattern_4_0: 440000 rects
+Loading sky130A Device Generator Menu ...
+caravel_00069f13_fill_pattern_4_2: 510000 rects
+caravel_00069f13_fill_pattern_3_1: 490000 rects
+caravel_00069f13_fill_pattern_4_7: 520000 rects
+caravel_00069f13_fill_pattern_3_3: 260000 rects
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
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+caravel_00069f13_fill_pattern_3_4: 800000 rects
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+caravel_00069f13_fill_pattern_2_7: 80000 rects
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+caravel_00069f13_fill_pattern_4_7: 610000 rects
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+caravel_00069f13_fill_pattern_5_5: 510000 rects
+caravel_00069f13_fill_pattern_1_5: 1000000 rects
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+caravel_00069f13_fill_pattern_0_0: 750000 rects
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+caravel_00069f13_fill_pattern_3_5: 700000 rects
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+caravel_00069f13_fill_pattern_1_6: 420000 rects
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+caravel_00069f13_fill_pattern_2_7: 90000 rects
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+caravel_00069f13_fill_pattern_1_5: 1010000 rects
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+caravel_00069f13_fill_pattern_2_5: 560000 rects
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+caravel_00069f13_fill_pattern_4_2: 610000 rects
+caravel_00069f13_fill_pattern_5_5: 520000 rects
+caravel_00069f13_fill_pattern_4_6: 540000 rects
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+caravel_00069f13_fill_pattern_4_7: 620000 rects
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+caravel_00069f13_fill_pattern_1_6: 430000 rects
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+caravel_00069f13_fill_pattern_0_4: 990000 rects
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+caravel_00069f13_fill_pattern_0_0: 770000 rects
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+caravel_00069f13_fill_pattern_0_3: 440000 rects
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+caravel_00069f13_fill_pattern_3_4: 970000 rects
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+caravel_00069f13_fill_pattern_5_5: 530000 rects
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+caravel_00069f13_fill_pattern_2_7: 100000 rects
+caravel_00069f13_fill_pattern_1_6: 440000 rects
+caravel_00069f13_fill_pattern_4_0: 600000 rects
+caravel_00069f13_fill_pattern_0_4: 1000000 rects
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+caravel_00069f13_fill_pattern_2_0: 500000 rects
+caravel_00069f13_fill_pattern_2_1: 630000 rects
+caravel_00069f13_fill_pattern_0_0: 780000 rects
+caravel_00069f13_fill_pattern_3_1: 620000 rects
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+caravel_00069f13_fill_pattern_4_3: 900000 rects
+caravel_00069f13_fill_pattern_3_0: 700000 rects
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+caravel_00069f13_fill_pattern_2_5: 580000 rects
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+caravel_00069f13_fill_pattern_2_6: 650000 rects
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+caravel_00069f13_fill_pattern_1_6: 450000 rects
+caravel_00069f13_fill_pattern_3_3: 420000 rects
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+caravel_00069f13_fill_pattern_3_5: 730000 rects
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+caravel_00069f13_fill_pattern_5_5: 550000 rects
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+caravel_00069f13_fill_pattern_0_4: 1020000 rects
+caravel_00069f13_fill_pattern_0_3: 460000 rects
+caravel_00069f13_fill_pattern_0_6: 890000 rects
+caravel_00069f13_fill_pattern_2_2: 400000 rects
+caravel_00069f13_fill_pattern_4_3: 910000 rects
+caravel_00069f13_fill_pattern_3_3: 430000 rects
+caravel_00069f13_fill_pattern_1_7: 590000 rects
+caravel_00069f13_fill_pattern_4_0: 620000 rects
+caravel_00069f13_fill_pattern_4_2: 640000 rects
+caravel_00069f13_fill_pattern_1_5: 1050000 rects
+caravel_00069f13_fill_pattern_3_5: 740000 rects
+caravel_00069f13_fill_pattern_3_4: 1000000 rects
+caravel_00069f13_fill_pattern_2_4: 770000 rects
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+caravel_00069f13_fill_pattern_5_6: 340000 rects
+caravel_00069f13_fill_pattern_1_3: 710000 rects
+caravel_00069f13_fill_pattern_0_7: 670000 rects
+caravel_00069f13_fill_pattern_0_2: 880000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00069f13_fill_pattern_0_0: 800000 rects
+caravel_00069f13_fill_pattern_4_4: 910000 rects
+caravel_00069f13_fill_pattern_1_2: 660000 rects
+caravel_00069f13_fill_pattern_2_1: 650000 rects
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+caravel_00069f13_fill_pattern_5_5: 560000 rects
+caravel_00069f13_fill_pattern_0_4: 1030000 rects
+caravel_00069f13_fill_pattern_1_6: 470000 rects
+caravel_00069f13_fill_pattern_3_0: 720000 rects
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+caravel_00069f13_fill_pattern_2_6: 670000 rects
+caravel_00069f13_fill_pattern_0_6: 900000 rects
+ Generating output for cell caravel_00069f13_fill_pattern_5_3
+caravel_00069f13_fill_pattern_5_2: 620000 rects
+caravel_00069f13_fill_pattern_3_3: 440000 rects
+caravel_00069f13_fill_pattern_4_3: 920000 rects
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+caravel_00069f13_fill_pattern_0_0: 1110000 rects
+caravel_00069f13_fill_pattern_0_4: 1370000 rects
+caravel_00069f13_fill_pattern_5_6: 550000 rects
+caravel_00069f13_fill_pattern_4_3: 1190000 rects
+caravel_00069f13_fill_pattern_3_5: 1010000 rects
+caravel_00069f13_fill_pattern_2_5: 850000 rects
+caravel_00069f13_fill_pattern_5_2: 830000 rects
+caravel_00069f13_fill_pattern_2_4: 1000000 rects
+caravel_00069f13_fill_pattern_1_6: 810000 rects
+caravel_00069f13_fill_pattern_2_0: 830000 rects
+caravel_00069f13_fill_pattern_2_6: 950000 rects
+caravel_00069f13_fill_pattern_1_2: 970000 rects
+caravel_00069f13_fill_pattern_0_6: 1220000 rects
+caravel_00069f13_fill_pattern_1_5: 1360000 rects
+caravel_00069f13_fill_pattern_1_1: 970000 rects
+caravel_00069f13_fill_pattern_3_4: 1410000 rects
+caravel_00069f13_fill_pattern_4_4: 1230000 rects
+caravel_00069f13_fill_pattern_1_3: 1010000 rects
+caravel_00069f13_fill_pattern_2_7: 400000 rects
+caravel_00069f13_fill_pattern_0_3: 750000 rects
+caravel_00069f13_fill_pattern_3_3: 750000 rects
+caravel_00069f13_fill_pattern_4_6: 650000 rects
+caravel_00069f13_fill_pattern_4_2: 690000 rects
+caravel_00069f13_fill_pattern_3_0: 1030000 rects
+caravel_00069f13_fill_pattern_5_1: 560000 rects
+caravel_00069f13_fill_pattern_3_1: 940000 rects
+caravel_00069f13_fill_pattern_4_0: 870000 rects
+caravel_00069f13_fill_pattern_0_0: 1120000 rects
+caravel_00069f13_fill_pattern_2_1: 920000 rects
+caravel_00069f13_fill_pattern_1_6: 820000 rects
+caravel_00069f13_fill_pattern_0_4: 1380000 rects
+caravel_00069f13_fill_pattern_2_5: 860000 rects
+caravel_00069f13_fill_pattern_0_2: 1160000 rects
+caravel_00069f13_fill_pattern_4_3: 1200000 rects
+caravel_00069f13_fill_pattern_3_4: 1420000 rects
+caravel_00069f13_fill_pattern_2_0: 840000 rects
+caravel_00069f13_fill_pattern_2_6: 960000 rects
+caravel_00069f13_fill_pattern_1_7: 790000 rects
+caravel_00069f13_fill_pattern_2_2: 640000 rects
+caravel_00069f13_fill_pattern_3_7: 830000 rects
+caravel_00069f13_fill_pattern_5_2: 840000 rects
+caravel_00069f13_fill_pattern_1_3: 1020000 rects
+caravel_00069f13_fill_pattern_0_6: 1230000 rects
+caravel_00069f13_fill_pattern_3_3: 760000 rects
+caravel_00069f13_fill_pattern_1_1: 980000 rects
+caravel_00069f13_fill_pattern_1_5: 1370000 rects
+caravel_00069f13_fill_pattern_4_4: 1240000 rects
+caravel_00069f13_fill_pattern_1_2: 980000 rects
+caravel_00069f13_fill_pattern_3_5: 1020000 rects
+caravel_00069f13_fill_pattern_2_7: 410000 rects
+caravel_00069f13_fill_pattern_3_0: 1040000 rects
+caravel_00069f13_fill_pattern_5_1: 570000 rects
+caravel_00069f13_fill_pattern_3_1: 950000 rects
+caravel_00069f13_fill_pattern_2_4: 1010000 rects
+caravel_00069f13_fill_pattern_1_6: 830000 rects
+caravel_00069f13_fill_pattern_2_1: 930000 rects
+caravel_00069f13_fill_pattern_5_6: 560000 rects
+caravel_00069f13_fill_pattern_0_3: 760000 rects
+caravel_00069f13_fill_pattern_3_4: 1430000 rects
+caravel_00069f13_fill_pattern_0_4: 1390000 rects
+caravel_00069f13_fill_pattern_2_5: 870000 rects
+caravel_00069f13_fill_pattern_5_2: 850000 rects
+caravel_00069f13_fill_pattern_1_3: 1030000 rects
+caravel_00069f13_fill_pattern_3_3: 770000 rects
+caravel_00069f13_fill_pattern_2_0: 850000 rects
+caravel_00069f13_fill_pattern_4_0: 880000 rects
+caravel_00069f13_fill_pattern_0_0: 1130000 rects
+caravel_00069f13_fill_pattern_2_6: 970000 rects
+caravel_00069f13_fill_pattern_1_7: 800000 rects
+caravel_00069f13_fill_pattern_4_6: 660000 rects
+caravel_00069f13_fill_pattern_4_3: 1210000 rects
+caravel_00069f13_fill_pattern_1_5: 1380000 rects
+caravel_00069f13_fill_pattern_1_1: 990000 rects
+caravel_00069f13_fill_pattern_4_4: 1250000 rects
+caravel_00069f13_fill_pattern_0_6: 1240000 rects
+caravel_00069f13_fill_pattern_2_2: 650000 rects
+caravel_00069f13_fill_pattern_0_7: 900000 rects
+caravel_00069f13_fill_pattern_1_6: 840000 rects
+caravel_00069f13_fill_pattern_1_2: 990000 rects
+caravel_00069f13_fill_pattern_5_1: 580000 rects
+caravel_00069f13_fill_pattern_3_1: 960000 rects
+caravel_00069f13_fill_pattern_3_0: 1050000 rects
+caravel_00069f13_fill_pattern_0_3: 770000 rects
+caravel_00069f13_fill_pattern_2_1: 940000 rects
+caravel_00069f13_fill_pattern_1_3: 1040000 rects
+caravel_00069f13_fill_pattern_5_2: 860000 rects
+caravel_00069f13_fill_pattern_3_4: 1440000 rects
+caravel_00069f13_fill_pattern_3_3: 780000 rects
+caravel_00069f13_fill_pattern_0_2: 1170000 rects
+caravel_00069f13_fill_pattern_3_5: 1030000 rects
+caravel_00069f13_fill_pattern_2_5: 880000 rects
+caravel_00069f13_fill_pattern_3_7: 840000 rects
+caravel_00069f13_fill_pattern_0_4: 1400000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00069f13_fill_pattern_2_0: 860000 rects
+caravel_00069f13_fill_pattern_4_6: 670000 rects
+caravel_00069f13_fill_pattern_2_6: 980000 rects
+caravel_00069f13_fill_pattern_4_2: 700000 rects
+caravel_00069f13_fill_pattern_2_7: 420000 rects
+caravel_00069f13_fill_pattern_1_7: 810000 rects
+caravel_00069f13_fill_pattern_1_1: 1000000 rects
+caravel_00069f13_fill_pattern_1_5: 1390000 rects
+caravel_00069f13_fill_pattern_1_6: 850000 rects
+caravel_00069f13_fill_pattern_4_3: 1220000 rects
+caravel_00069f13_fill_pattern_0_0: 1140000 rects
+caravel_00069f13_fill_pattern_5_6: 570000 rects
+caravel_00069f13_fill_pattern_4_0: 890000 rects
+ Generating output for cell caravel_00069f13_fill_pattern_4_7
+caravel_00069f13_fill_pattern_1_3: 1050000 rects
+caravel_00069f13_fill_pattern_3_1: 970000 rects
+caravel_00069f13_fill_pattern_5_2: 870000 rects
+caravel_00069f13_fill_pattern_0_3: 780000 rects
+caravel_00069f13_fill_pattern_5_1: 590000 rects
+caravel_00069f13_fill_pattern_4_4: 1260000 rects
+caravel_00069f13_fill_pattern_2_2: 660000 rects
+caravel_00069f13_fill_pattern_3_0: 1060000 rects
+caravel_00069f13_fill_pattern_3_4: 1450000 rects
+caravel_00069f13_fill_pattern_2_5: 890000 rects
+caravel_00069f13_fill_pattern_2_1: 950000 rects
+caravel_00069f13_fill_pattern_1_2: 1000000 rects
+caravel_00069f13_fill_pattern_0_7: 910000 rects
+caravel_00069f13_fill_pattern_0_4: 1410000 rects
+caravel_00069f13_fill_pattern_2_0: 870000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00069f13_fill_pattern_3_3: 790000 rects
+caravel_00069f13_fill_pattern_2_6: 990000 rects
+caravel_00069f13_fill_pattern_3_5: 1040000 rects
+caravel_00069f13_fill_pattern_0_6: 1250000 rects
+caravel_00069f13_fill_pattern_1_6: 860000 rects
+caravel_00069f13_fill_pattern_5_6: 580000 rects
+caravel_00069f13_fill_pattern_2_4: 1020000 rects
+caravel_00069f13_fill_pattern_1_3: 1060000 rects
+caravel_00069f13_fill_pattern_1_7: 820000 rects
+caravel_00069f13_fill_pattern_1_1: 1010000 rects
+caravel_00069f13_fill_pattern_4_3: 1230000 rects
+caravel_00069f13_fill_pattern_1_5: 1400000 rects
+caravel_00069f13_fill_pattern_0_3: 790000 rects
+caravel_00069f13_fill_pattern_3_1: 980000 rects
+ Generating output for cell caravel_00069f13_fill_pattern_5_5
+caravel_00069f13_fill_pattern_0_2: 1180000 rects
+caravel_00069f13_fill_pattern_4_2: 710000 rects
+caravel_00069f13_fill_pattern_3_7: 850000 rects
+caravel_00069f13_fill_pattern_3_4: 1460000 rects
+caravel_00069f13_fill_pattern_2_5: 900000 rects
+caravel_00069f13_fill_pattern_5_1: 600000 rects
+caravel_00069f13_fill_pattern_2_1: 960000 rects
+caravel_00069f13_fill_pattern_3_0: 1070000 rects
+caravel_00069f13_fill_pattern_5_2: 880000 rects
+caravel_00069f13_fill_pattern_4_0: 900000 rects
+caravel_00069f13_fill_pattern_2_0: 880000 rects
+caravel_00069f13_fill_pattern_0_0: 1150000 rects
+caravel_00069f13_fill_pattern_2_2: 670000 rects
+caravel_00069f13_fill_pattern_0_4: 1420000 rects
+caravel_00069f13_fill_pattern_1_6: 870000 rects
+caravel_00069f13_fill_pattern_1_2: 1010000 rects
+caravel_00069f13_fill_pattern_2_6: 1000000 rects
+caravel_00069f13_fill_pattern_1_3: 1070000 rects
+caravel_00069f13_fill_pattern_4_4: 1270000 rects
+caravel_00069f13_fill_pattern_0_7: 920000 rects
+caravel_00069f13_fill_pattern_4_3: 1240000 rects
+caravel_00069f13_fill_pattern_1_7: 830000 rects
+caravel_00069f13_fill_pattern_0_3: 800000 rects
+caravel_00069f13_fill_pattern_2_7: 430000 rects
+caravel_00069f13_fill_pattern_1_5: 1410000 rects
+caravel_00069f13_fill_pattern_3_1: 990000 rects
+caravel_00069f13_fill_pattern_2_4: 1030000 rects
+caravel_00069f13_fill_pattern_5_6: 590000 rects
+caravel_00069f13_fill_pattern_3_5: 1050000 rects
+caravel_00069f13_fill_pattern_3_4: 1470000 rects
+caravel_00069f13_fill_pattern_2_5: 910000 rects
+caravel_00069f13_fill_pattern_0_6: 1260000 rects
+caravel_00069f13_fill_pattern_2_1: 970000 rects
+caravel_00069f13_fill_pattern_3_3: 800000 rects
+caravel_00069f13_fill_pattern_1_6: 880000 rects
+caravel_00069f13_fill_pattern_3_0: 1080000 rects
+caravel_00069f13_fill_pattern_2_0: 890000 rects
+caravel_00069f13_fill_pattern_1_1: 1020000 rects
+caravel_00069f13_fill_pattern_1_3: 1080000 rects
+caravel_00069f13_fill_pattern_0_4: 1430000 rects
+caravel_00069f13_fill_pattern_5_1: 610000 rects
+caravel_00069f13_fill_pattern_2_6: 1010000 rects
+caravel_00069f13_fill_pattern_2_2: 680000 rects
+caravel_00069f13_fill_pattern_0_7: 930000 rects
+caravel_00069f13_fill_pattern_1_2: 1020000 rects
+caravel_00069f13_fill_pattern_5_2: 890000 rects
+caravel_00069f13_fill_pattern_4_0: 910000 rects
+caravel_00069f13_fill_pattern_4_3: 1250000 rects
+caravel_00069f13_fill_pattern_0_0: 1160000 rects
+caravel_00069f13_fill_pattern_1_7: 840000 rects
+caravel_00069f13_fill_pattern_4_2: 720000 rects
+caravel_00069f13_fill_pattern_3_1: 1000000 rects
+caravel_00069f13_fill_pattern_3_4: 1480000 rects
+caravel_00069f13_fill_pattern_4_6: 680000 rects
+caravel_00069f13_fill_pattern_1_6: 890000 rects
+caravel_00069f13_fill_pattern_2_5: 920000 rects
+caravel_00069f13_fill_pattern_2_4: 1040000 rects
+caravel_00069f13_fill_pattern_2_1: 980000 rects
+caravel_00069f13_fill_pattern_1_3: 1090000 rects
+caravel_00069f13_fill_pattern_1_5: 1420000 rects
+caravel_00069f13_fill_pattern_3_7: 860000 rects
+caravel_00069f13_fill_pattern_0_2: 1190000 rects
+caravel_00069f13_fill_pattern_2_0: 900000 rects
+caravel_00069f13_fill_pattern_4_4: 1280000 rects
+caravel_00069f13_fill_pattern_0_3: 810000 rects
+caravel_00069f13_fill_pattern_3_0: 1090000 rects
+caravel_00069f13_fill_pattern_3_5: 1060000 rects
+caravel_00069f13_fill_pattern_0_4: 1440000 rects
+caravel_00069f13_fill_pattern_0_7: 940000 rects
+caravel_00069f13_fill_pattern_3_3: 810000 rects
+caravel_00069f13_fill_pattern_1_1: 1030000 rects
+caravel_00069f13_fill_pattern_5_6: 600000 rects
+caravel_00069f13_fill_pattern_2_6: 1020000 rects
+caravel_00069f13_fill_pattern_4_3: 1260000 rects
+caravel_00069f13_fill_pattern_2_2: 690000 rects
+caravel_00069f13_fill_pattern_1_2: 1030000 rects
+caravel_00069f13_fill_pattern_1_6: 900000 rects
+caravel_00069f13_fill_pattern_1_3: 1100000 rects
+caravel_00069f13_fill_pattern_3_4: 1490000 rects
+caravel_00069f13_fill_pattern_0_6: 1270000 rects
+caravel_00069f13_fill_pattern_2_5: 930000 rects
+caravel_00069f13_fill_pattern_3_1: 1010000 rects
+caravel_00069f13_fill_pattern_1_7: 850000 rects
+caravel_00069f13_fill_pattern_2_7: 440000 rects
+caravel_00069f13_fill_pattern_5_1: 620000 rects
+caravel_00069f13_fill_pattern_2_1: 990000 rects
+caravel_00069f13_fill_pattern_2_0: 910000 rects
+caravel_00069f13_fill_pattern_5_2: 900000 rects
+caravel_00069f13_fill_pattern_4_0: 920000 rects
+caravel_00069f13_fill_pattern_1_5: 1430000 rects
+caravel_00069f13_fill_pattern_0_3: 820000 rects
+caravel_00069f13_fill_pattern_3_3: 820000 rects
+caravel_00069f13_fill_pattern_4_4: 1290000 rects
+caravel_00069f13_fill_pattern_3_0: 1100000 rects
+caravel_00069f13_fill_pattern_0_4: 1450000 rects
+caravel_00069f13_fill_pattern_2_6: 1030000 rects
+caravel_00069f13_fill_pattern_1_1: 1040000 rects
+caravel_00069f13_fill_pattern_1_3: 1110000 rects
+caravel_00069f13_fill_pattern_1_6: 910000 rects
+caravel_00069f13_fill_pattern_3_7: 870000 rects
+caravel_00069f13_fill_pattern_3_5: 1070000 rects
+caravel_00069f13_fill_pattern_4_3: 1270000 rects
+caravel_00069f13_fill_pattern_3_4: 1500000 rects
+caravel_00069f13_fill_pattern_2_5: 940000 rects
+caravel_00069f13_fill_pattern_3_1: 1020000 rects
+caravel_00069f13_fill_pattern_4_2: 730000 rects
+caravel_00069f13_fill_pattern_5_6: 610000 rects
+caravel_00069f13_fill_pattern_0_0: 1170000 rects
+caravel_00069f13_fill_pattern_2_1: 1000000 rects
+caravel_00069f13_fill_pattern_2_0: 920000 rects
+caravel_00069f13_fill_pattern_1_2: 1040000 rects
+caravel_00069f13_fill_pattern_2_2: 700000 rects
+caravel_00069f13_fill_pattern_0_2: 1200000 rects
+caravel_00069f13_fill_pattern_0_3: 830000 rects
+caravel_00069f13_fill_pattern_1_7: 860000 rects
+caravel_00069f13_fill_pattern_0_6: 1280000 rects
+caravel_00069f13_fill_pattern_3_0: 1110000 rects
+caravel_00069f13_fill_pattern_4_4: 1300000 rects
+caravel_00069f13_fill_pattern_2_6: 1040000 rects
+caravel_00069f13_fill_pattern_0_4: 1460000 rects
+caravel_00069f13_fill_pattern_3_3: 830000 rects
+caravel_00069f13_fill_pattern_1_3: 1120000 rects
+caravel_00069f13_fill_pattern_2_4: 1050000 rects
+caravel_00069f13_fill_pattern_1_6: 920000 rects
+caravel_00069f13_fill_pattern_5_1: 630000 rects
+caravel_00069f13_fill_pattern_1_1: 1050000 rects
+caravel_00069f13_fill_pattern_1_5: 1440000 rects
+caravel_00069f13_fill_pattern_4_0: 930000 rects
+caravel_00069f13_fill_pattern_5_2: 910000 rects
+caravel_00069f13_fill_pattern_0_7: 950000 rects
+caravel_00069f13_fill_pattern_3_4: 1510000 rects
+caravel_00069f13_fill_pattern_3_1: 1030000 rects
+caravel_00069f13_fill_pattern_2_5: 950000 rects
+caravel_00069f13_fill_pattern_4_3: 1280000 rects
+caravel_00069f13_fill_pattern_2_1: 1010000 rects
+caravel_00069f13_fill_pattern_2_0: 930000 rects
+caravel_00069f13_fill_pattern_2_7: 450000 rects
+caravel_00069f13_fill_pattern_0_3: 840000 rects
+caravel_00069f13_fill_pattern_5_6: 620000 rects
+caravel_00069f13_fill_pattern_3_5: 1080000 rects
+caravel_00069f13_fill_pattern_1_3: 1130000 rects
+caravel_00069f13_fill_pattern_3_7: 880000 rects
+caravel_00069f13_fill_pattern_1_2: 1050000 rects
+caravel_00069f13_fill_pattern_2_2: 710000 rects
+caravel_00069f13_fill_pattern_1_6: 930000 rects
+caravel_00069f13_fill_pattern_2_6: 1050000 rects
+caravel_00069f13_fill_pattern_3_0: 1120000 rects
+caravel_00069f13_fill_pattern_4_4: 1310000 rects
+caravel_00069f13_fill_pattern_0_4: 1470000 rects
+caravel_00069f13_fill_pattern_1_7: 870000 rects
+caravel_00069f13_fill_pattern_0_6: 1290000 rects
+caravel_00069f13_fill_pattern_3_4: 1520000 rects
+caravel_00069f13_fill_pattern_3_1: 1040000 rects
+caravel_00069f13_fill_pattern_2_1: 1020000 rects
+caravel_00069f13_fill_pattern_2_5: 960000 rects
+caravel_00069f13_fill_pattern_2_0: 940000 rects
+caravel_00069f13_fill_pattern_4_2: 740000 rects
+caravel_00069f13_fill_pattern_5_1: 640000 rects
+caravel_00069f13_fill_pattern_1_1: 1060000 rects
+caravel_00069f13_fill_pattern_1_3: 1140000 rects
+caravel_00069f13_fill_pattern_5_2: 920000 rects
+caravel_00069f13_fill_pattern_4_0: 940000 rects
+caravel_00069f13_fill_pattern_0_2: 1210000 rects
+caravel_00069f13_fill_pattern_1_6: 940000 rects
+caravel_00069f13_fill_pattern_5_6: 630000 rects
+caravel_00069f13_fill_pattern_0_3: 850000 rects
+caravel_00069f13_fill_pattern_3_3: 840000 rects
+caravel_00069f13_fill_pattern_0_0: 1180000 rects
+caravel_00069f13_fill_pattern_1_5: 1450000 rects
+caravel_00069f13_fill_pattern_2_6: 1060000 rects
+caravel_00069f13_fill_pattern_2_4: 1060000 rects
+caravel_00069f13_fill_pattern_3_0: 1130000 rects
+caravel_00069f13_fill_pattern_4_3: 1290000 rects
+caravel_00069f13_fill_pattern_1_2: 1060000 rects
+caravel_00069f13_fill_pattern_0_4: 1480000 rects
+caravel_00069f13_fill_pattern_2_2: 720000 rects
+caravel_00069f13_fill_pattern_3_5: 1090000 rects
+caravel_00069f13_fill_pattern_3_4: 1530000 rects
+caravel_00069f13_fill_pattern_3_7: 890000 rects
+caravel_00069f13_fill_pattern_2_1: 1030000 rects
+caravel_00069f13_fill_pattern_2_0: 950000 rects
+caravel_00069f13_fill_pattern_4_4: 1320000 rects
+caravel_00069f13_fill_pattern_1_3: 1150000 rects
+caravel_00069f13_fill_pattern_3_1: 1050000 rects
+caravel_00069f13_fill_pattern_2_5: 970000 rects
+caravel_00069f13_fill_pattern_0_6: 1300000 rects
+caravel_00069f13_fill_pattern_5_2: 930000 rects
+caravel_00069f13_fill_pattern_1_6: 950000 rects
+caravel_00069f13_fill_pattern_2_7: 460000 rects
+caravel_00069f13_fill_pattern_1_7: 880000 rects
+caravel_00069f13_fill_pattern_0_3: 860000 rects
+caravel_00069f13_fill_pattern_2_6: 1070000 rects
+caravel_00069f13_fill_pattern_5_1: 650000 rects
+caravel_00069f13_fill_pattern_3_0: 1140000 rects
+caravel_00069f13_fill_pattern_0_7: 960000 rects
+caravel_00069f13_fill_pattern_0_4: 1490000 rects
+caravel_00069f13_fill_pattern_4_0: 950000 rects
+caravel_00069f13_fill_pattern_4_2: 750000 rects
+caravel_00069f13_fill_pattern_1_1: 1070000 rects
+caravel_00069f13_fill_pattern_1_3: 1160000 rects
+caravel_00069f13_fill_pattern_0_0: 1190000 rects
+caravel_00069f13_fill_pattern_3_4: 1540000 rects
+caravel_00069f13_fill_pattern_1_2: 1070000 rects
+caravel_00069f13_fill_pattern_2_1: 1040000 rects
+caravel_00069f13_fill_pattern_3_1: 1060000 rects
+caravel_00069f13_fill_pattern_2_0: 960000 rects
+caravel_00069f13_fill_pattern_2_5: 980000 rects
+caravel_00069f13_fill_pattern_5_2: 940000 rects
+caravel_00069f13_fill_pattern_5_6: 640000 rects
+caravel_00069f13_fill_pattern_2_2: 730000 rects
+caravel_00069f13_fill_pattern_1_6: 960000 rects
+caravel_00069f13_fill_pattern_1_5: 1460000 rects
+caravel_00069f13_fill_pattern_2_4: 1070000 rects
+caravel_00069f13_fill_pattern_3_3: 850000 rects
+caravel_00069f13_fill_pattern_3_5: 1100000 rects
+caravel_00069f13_fill_pattern_3_7: 900000 rects
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+caravel_00069f13_fill_pattern_4_4: 1330000 rects
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+caravel_00069f13_fill_pattern_1_3: 1170000 rects
+caravel_00069f13_fill_pattern_0_4: 1500000 rects
+caravel_00069f13_fill_pattern_3_0: 1150000 rects
+caravel_00069f13_fill_pattern_0_6: 1310000 rects
+caravel_00069f13_fill_pattern_3_4: 1550000 rects
+caravel_00069f13_fill_pattern_1_6: 970000 rects
+caravel_00069f13_fill_pattern_2_0: 970000 rects
+caravel_00069f13_fill_pattern_0_0: 1200000 rects
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+caravel_00069f13_fill_pattern_3_1: 1070000 rects
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+caravel_00069f13_fill_pattern_1_7: 890000 rects
+caravel_00069f13_fill_pattern_1_2: 1080000 rects
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+caravel_00069f13_fill_pattern_4_2: 760000 rects
+caravel_00069f13_fill_pattern_4_0: 960000 rects
+caravel_00069f13_fill_pattern_2_4: 1080000 rects
+caravel_00069f13_fill_pattern_2_6: 1090000 rects
+caravel_00069f13_fill_pattern_1_3: 1180000 rects
+caravel_00069f13_fill_pattern_5_2: 950000 rects
+caravel_00069f13_fill_pattern_3_3: 860000 rects
+caravel_00069f13_fill_pattern_2_7: 470000 rects
+caravel_00069f13_fill_pattern_5_6: 650000 rects
+caravel_00069f13_fill_pattern_3_5: 1110000 rects
+caravel_00069f13_fill_pattern_1_6: 980000 rects
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+caravel_00069f13_fill_pattern_4_3: 1300000 rects
+caravel_00069f13_fill_pattern_3_4: 1560000 rects
+caravel_00069f13_fill_pattern_0_3: 880000 rects
+caravel_00069f13_fill_pattern_2_5: 1000000 rects
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+caravel_00069f13_fill_pattern_2_6: 1110000 rects
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+caravel_00069f13_fill_pattern_1_6: 1000000 rects
+caravel_00069f13_fill_pattern_1_7: 900000 rects
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+caravel_00069f13_fill_pattern_3_4: 1580000 rects
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+caravel_00069f13_fill_pattern_2_0: 1000000 rects
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+caravel_00069f13_fill_pattern_5_2: 970000 rects
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+caravel_00069f13_fill_pattern_2_5: 1030000 rects
+caravel_00069f13_fill_pattern_0_7: 1000000 rects
+caravel_00069f13_fill_pattern_2_4: 1100000 rects
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+caravel_00069f13_fill_pattern_2_2: 770000 rects
+caravel_00069f13_fill_pattern_2_6: 1130000 rects
+CIF output style is now "wafflefill(tiled)"
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+caravel_00069f13_fill_pattern_1_7: 910000 rects
+caravel_00069f13_fill_pattern_1_1: 1110000 rects
+caravel_00069f13_fill_pattern_4_2: 780000 rects
+caravel_00069f13_fill_pattern_5_2: 980000 rects
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+caravel_00069f13_fill_pattern_3_7: 930000 rects
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+caravel_00069f13_fill_pattern_0_6: 1340000 rects
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+caravel_00069f13_fill_pattern_3_5: 1140000 rects
+caravel_00069f13_fill_pattern_2_7: 490000 rects
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+caravel_00069f13_fill_pattern_1_6: 1030000 rects
+caravel_00069f13_fill_pattern_1_5: 1500000 rects
+ Generating output for cell caravel_00069f13_fill_pattern_4_6
+caravel_00069f13_fill_pattern_4_4: 1370000 rects
+caravel_00069f13_fill_pattern_2_6: 1140000 rects
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+caravel_00069f13_fill_pattern_4_0: 1000000 rects
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+caravel_00069f13_fill_pattern_0_3: 950000 rects
+caravel_00069f13_fill_pattern_3_1: 1210000 rects
+caravel_00069f13_fill_pattern_3_3: 980000 rects
+caravel_00069f13_fill_pattern_2_1: 1200000 rects
+caravel_00069f13_fill_pattern_3_4: 1700000 rects
+caravel_00069f13_fill_pattern_4_4: 1440000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00069f13_fill_pattern_2_5: 1140000 rects
+caravel_00069f13_fill_pattern_5_1: 780000 rects
+caravel_00069f13_fill_pattern_2_0: 1120000 rects
+caravel_00069f13_fill_pattern_2_2: 850000 rects
+caravel_00069f13_fill_pattern_1_3: 1310000 rects
+caravel_00069f13_fill_pattern_2_7: 530000 rects
+caravel_00069f13_fill_pattern_1_2: 1170000 rects
+caravel_00069f13_fill_pattern_2_6: 1240000 rects
+caravel_00069f13_fill_pattern_3_0: 1290000 rects
+caravel_00069f13_fill_pattern_1_6: 1130000 rects
+caravel_00069f13_fill_pattern_1_5: 1580000 rects
+caravel_00069f13_fill_pattern_3_5: 1210000 rects
+caravel_00069f13_fill_pattern_4_0: 1090000 rects
+caravel_00069f13_fill_pattern_0_0: 1310000 rects
+caravel_00069f13_fill_pattern_2_4: 1190000 rects
+caravel_00069f13_fill_pattern_3_3: 990000 rects
+ Generating output for cell caravel_00069f13_fill_pattern_5_6
+caravel_00069f13_fill_pattern_1_1: 1210000 rects
+caravel_00069f13_fill_pattern_1_7: 970000 rects
+caravel_00069f13_fill_pattern_2_0: 1130000 rects
+caravel_00069f13_fill_pattern_0_4: 1610000 rects
+caravel_00069f13_fill_pattern_3_4: 1710000 rects
+caravel_00069f13_fill_pattern_2_1: 1210000 rects
+caravel_00069f13_fill_pattern_2_5: 1150000 rects
+caravel_00069f13_fill_pattern_3_1: 1220000 rects
+caravel_00069f13_fill_pattern_4_3: 1350000 rects
+caravel_00069f13_fill_pattern_4_4: 1450000 rects
+caravel_00069f13_fill_pattern_0_6: 1400000 rects
+caravel_00069f13_fill_pattern_1_3: 1320000 rects
+caravel_00069f13_fill_pattern_2_6: 1250000 rects
+caravel_00069f13_fill_pattern_2_2: 860000 rects
+caravel_00069f13_fill_pattern_3_0: 1300000 rects
+caravel_00069f13_fill_pattern_2_0: 1140000 rects
+caravel_00069f13_fill_pattern_1_6: 1140000 rects
+caravel_00069f13_fill_pattern_3_3: 1000000 rects
+caravel_00069f13_fill_pattern_0_2: 1300000 rects
+caravel_00069f13_fill_pattern_3_7: 1030000 rects
+caravel_00069f13_fill_pattern_0_0: 1320000 rects
+caravel_00069f13_fill_pattern_1_2: 1180000 rects
+caravel_00069f13_fill_pattern_5_1: 790000 rects
+caravel_00069f13_fill_pattern_1_5: 1590000 rects
+caravel_00069f13_fill_pattern_1_1: 1220000 rects
+caravel_00069f13_fill_pattern_2_4: 1200000 rects
+caravel_00069f13_fill_pattern_3_4: 1720000 rects
+caravel_00069f13_fill_pattern_0_3: 960000 rects
+caravel_00069f13_fill_pattern_2_5: 1160000 rects
+caravel_00069f13_fill_pattern_2_1: 1220000 rects
+caravel_00069f13_fill_pattern_3_5: 1220000 rects
+caravel_00069f13_fill_pattern_3_1: 1230000 rects
+caravel_00069f13_fill_pattern_0_4: 1620000 rects
+caravel_00069f13_fill_pattern_2_0: 1150000 rects
+caravel_00069f13_fill_pattern_1_7: 980000 rects
+caravel_00069f13_fill_pattern_2_6: 1260000 rects
+caravel_00069f13_fill_pattern_3_0: 1310000 rects
+caravel_00069f13_fill_pattern_3_3: 1010000 rects
+caravel_00069f13_fill_pattern_4_4: 1460000 rects
+caravel_00069f13_fill_pattern_2_7: 540000 rects
+caravel_00069f13_fill_pattern_1_3: 1330000 rects
+caravel_00069f13_fill_pattern_1_6: 1150000 rects
+caravel_00069f13_fill_pattern_2_2: 870000 rects
+caravel_00069f13_fill_pattern_1_1: 1230000 rects
+caravel_00069f13_fill_pattern_0_0: 1330000 rects
+caravel_00069f13_fill_pattern_2_4: 1210000 rects
+caravel_00069f13_fill_pattern_3_4: 1730000 rects
+caravel_00069f13_fill_pattern_2_1: 1230000 rects
+caravel_00069f13_fill_pattern_2_5: 1170000 rects
+caravel_00069f13_fill_pattern_0_6: 1410000 rects
+caravel_00069f13_fill_pattern_1_5: 1600000 rects
+caravel_00069f13_fill_pattern_1_2: 1190000 rects
+caravel_00069f13_fill_pattern_3_1: 1240000 rects
+caravel_00069f13_fill_pattern_2_0: 1160000 rects
+caravel_00069f13_fill_pattern_3_7: 1040000 rects
+caravel_00069f13_fill_pattern_2_6: 1270000 rects
+caravel_00069f13_fill_pattern_3_3: 1020000 rects
+caravel_00069f13_fill_pattern_3_5: 1230000 rects
+caravel_00069f13_fill_pattern_3_0: 1320000 rects
+caravel_00069f13_fill_pattern_5_1: 800000 rects
+caravel_00069f13_fill_pattern_0_2: 1310000 rects
+caravel_00069f13_fill_pattern_4_0: 1100000 rects
+caravel_00069f13_fill_pattern_4_4: 1470000 rects
+caravel_00069f13_fill_pattern_1_6: 1160000 rects
+caravel_00069f13_fill_pattern_1_1: 1240000 rects
+caravel_00069f13_fill_pattern_2_1: 1240000 rects
+caravel_00069f13_fill_pattern_2_4: 1220000 rects
+caravel_00069f13_fill_pattern_2_5: 1180000 rects
+caravel_00069f13_fill_pattern_0_0: 1340000 rects
+caravel_00069f13_fill_pattern_2_0: 1170000 rects
+caravel_00069f13_fill_pattern_1_3: 1340000 rects
+caravel_00069f13_fill_pattern_1_7: 990000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00069f13_fill_pattern_2_2: 880000 rects
+caravel_00069f13_fill_pattern_2_6: 1280000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00069f13_fill_pattern_3_3: 1030000 rects
+caravel_00069f13_fill_pattern_0_6: 1420000 rects
+caravel_00069f13_fill_pattern_1_5: 1610000 rects
+caravel_00069f13_fill_pattern_0_4: 1630000 rects
+caravel_00069f13_fill_pattern_3_0: 1330000 rects
+ Generating output for cell caravel_00069f13_fill_pattern_0_7
+caravel_00069f13_fill_pattern_2_7: 550000 rects
+caravel_00069f13_fill_pattern_3_1: 1250000 rects
+caravel_00069f13_fill_pattern_3_5: 1240000 rects
+caravel_00069f13_fill_pattern_3_4: 1740000 rects
+caravel_00069f13_fill_pattern_1_2: 1200000 rects
+caravel_00069f13_fill_pattern_4_3: 1360000 rects
+caravel_00069f13_fill_pattern_1_1: 1250000 rects
+caravel_00069f13_fill_pattern_2_1: 1250000 rects
+caravel_00069f13_fill_pattern_2_5: 1190000 rects
+caravel_00069f13_fill_pattern_1_6: 1170000 rects
+caravel_00069f13_fill_pattern_2_4: 1230000 rects
+caravel_00069f13_fill_pattern_0_3: 970000 rects
+caravel_00069f13_fill_pattern_0_0: 1350000 rects
+caravel_00069f13_fill_pattern_5_1: 810000 rects
+caravel_00069f13_fill_pattern_4_4: 1480000 rects
+caravel_00069f13_fill_pattern_2_6: 1290000 rects
+caravel_00069f13_fill_pattern_3_3: 1040000 rects
+caravel_00069f13_fill_pattern_1_3: 1350000 rects
+ Generating output for cell caravel_00069f13_fill_pattern_5_2
+caravel_00069f13_fill_pattern_2_0: 1180000 rects
+caravel_00069f13_fill_pattern_3_7: 1050000 rects
+caravel_00069f13_fill_pattern_2_2: 890000 rects
+caravel_00069f13_fill_pattern_3_0: 1340000 rects
+caravel_00069f13_fill_pattern_1_5: 1620000 rects
+caravel_00069f13_fill_pattern_0_6: 1430000 rects
+caravel_00069f13_fill_pattern_1_7: 1000000 rects
+caravel_00069f13_fill_pattern_3_5: 1250000 rects
+caravel_00069f13_fill_pattern_1_1: 1260000 rects
+caravel_00069f13_fill_pattern_2_5: 1200000 rects
+caravel_00069f13_fill_pattern_1_6: 1180000 rects
+caravel_00069f13_fill_pattern_0_2: 1320000 rects
+caravel_00069f13_fill_pattern_3_1: 1260000 rects
+caravel_00069f13_fill_pattern_2_4: 1240000 rects
+caravel_00069f13_fill_pattern_0_4: 1640000 rects
+caravel_00069f13_fill_pattern_2_1: 1260000 rects
+caravel_00069f13_fill_pattern_3_3: 1050000 rects
+caravel_00069f13_fill_pattern_2_6: 1300000 rects
+caravel_00069f13_fill_pattern_0_0: 1360000 rects
+caravel_00069f13_fill_pattern_5_1: 820000 rects
+caravel_00069f13_fill_pattern_4_4: 1490000 rects
+caravel_00069f13_fill_pattern_1_3: 1360000 rects
+caravel_00069f13_fill_pattern_3_4: 1750000 rects
+caravel_00069f13_fill_pattern_3_0: 1350000 rects
+caravel_00069f13_fill_pattern_1_2: 1210000 rects
+caravel_00069f13_fill_pattern_2_2: 900000 rects
+caravel_00069f13_fill_pattern_2_7: 560000 rects
+caravel_00069f13_fill_pattern_2_0: 1190000 rects
+caravel_00069f13_fill_pattern_2_5: 1210000 rects
+caravel_00069f13_fill_pattern_1_5: 1630000 rects
+caravel_00069f13_fill_pattern_0_6: 1440000 rects
+caravel_00069f13_fill_pattern_3_5: 1260000 rects
+caravel_00069f13_fill_pattern_1_1: 1270000 rects
+caravel_00069f13_fill_pattern_1_6: 1190000 rects
+caravel_00069f13_fill_pattern_3_3: 1060000 rects
+caravel_00069f13_fill_pattern_5_1: 830000 rects
+caravel_00069f13_fill_pattern_2_6: 1310000 rects
+caravel_00069f13_fill_pattern_0_3: 980000 rects
+caravel_00069f13_fill_pattern_0_0: 1370000 rects
+caravel_00069f13_fill_pattern_1_7: 1010000 rects
+caravel_00069f13_fill_pattern_2_1: 1270000 rects
+caravel_00069f13_fill_pattern_2_4: 1250000 rects
+caravel_00069f13_fill_pattern_3_0: 1360000 rects
+caravel_00069f13_fill_pattern_4_4: 1500000 rects
+caravel_00069f13_fill_pattern_0_4: 1650000 rects
+caravel_00069f13_fill_pattern_2_5: 1220000 rects
+caravel_00069f13_fill_pattern_3_1: 1270000 rects
+caravel_00069f13_fill_pattern_4_0: 1110000 rects
+caravel_00069f13_fill_pattern_1_3: 1370000 rects
+caravel_00069f13_fill_pattern_3_3: 1070000 rects
+caravel_00069f13_fill_pattern_3_5: 1270000 rects
+caravel_00069f13_fill_pattern_1_1: 1280000 rects
+caravel_00069f13_fill_pattern_5_1: 840000 rects
+caravel_00069f13_fill_pattern_2_2: 910000 rects
+caravel_00069f13_fill_pattern_0_2: 1330000 rects
+caravel_00069f13_fill_pattern_1_5: 1640000 rects
+caravel_00069f13_fill_pattern_1_6: 1200000 rects
+caravel_00069f13_fill_pattern_2_0: 1200000 rects
+caravel_00069f13_fill_pattern_2_6: 1320000 rects
+caravel_00069f13_fill_pattern_4_3: 1370000 rects
+caravel_00069f13_fill_pattern_0_6: 1450000 rects
+caravel_00069f13_fill_pattern_3_7: 1060000 rects
+caravel_00069f13_fill_pattern_1_2: 1220000 rects
+caravel_00069f13_fill_pattern_0_0: 1380000 rects
+caravel_00069f13_fill_pattern_2_4: 1260000 rects
+caravel_00069f13_fill_pattern_2_5: 1230000 rects
+caravel_00069f13_fill_pattern_3_0: 1370000 rects
+caravel_00069f13_fill_pattern_3_4: 1760000 rects
+caravel_00069f13_fill_pattern_2_1: 1280000 rects
+caravel_00069f13_fill_pattern_3_3: 1080000 rects
+caravel_00069f13_fill_pattern_2_7: 570000 rects
+caravel_00069f13_fill_pattern_5_1: 850000 rects
+caravel_00069f13_fill_pattern_4_4: 1510000 rects
+caravel_00069f13_fill_pattern_3_5: 1280000 rects
+caravel_00069f13_fill_pattern_1_1: 1290000 rects
+caravel_00069f13_fill_pattern_1_3: 1380000 rects
+caravel_00069f13_fill_pattern_3_1: 1280000 rects
+caravel_00069f13_fill_pattern_2_6: 1330000 rects
+caravel_00069f13_fill_pattern_1_7: 1020000 rects
+caravel_00069f13_fill_pattern_1_6: 1210000 rects
+caravel_00069f13_fill_pattern_0_3: 990000 rects
+caravel_00069f13_fill_pattern_1_5: 1650000 rects
+caravel_00069f13_fill_pattern_2_2: 920000 rects
+caravel_00069f13_fill_pattern_2_0: 1210000 rects
+caravel_00069f13_fill_pattern_0_6: 1460000 rects
+caravel_00069f13_fill_pattern_2_4: 1270000 rects
+caravel_00069f13_fill_pattern_3_3: 1090000 rects
+caravel_00069f13_fill_pattern_3_0: 1380000 rects
+caravel_00069f13_fill_pattern_2_5: 1240000 rects
+caravel_00069f13_fill_pattern_0_4: 1660000 rects
+caravel_00069f13_fill_pattern_3_5: 1290000 rects
+caravel_00069f13_fill_pattern_1_3: 1390000 rects
+caravel_00069f13_fill_pattern_1_1: 1300000 rects
+caravel_00069f13_fill_pattern_2_6: 1340000 rects
+caravel_00069f13_fill_pattern_5_1: 860000 rects
+caravel_00069f13_fill_pattern_0_2: 1340000 rects
+caravel_00069f13_fill_pattern_1_2: 1230000 rects
+caravel_00069f13_fill_pattern_3_1: 1290000 rects
+caravel_00069f13_fill_pattern_1_6: 1220000 rects
+caravel_00069f13_fill_pattern_0_0: 1390000 rects
+caravel_00069f13_fill_pattern_1_5: 1660000 rects
+caravel_00069f13_fill_pattern_4_4: 1520000 rects
+caravel_00069f13_fill_pattern_3_3: 1100000 rects
+caravel_00069f13_fill_pattern_2_0: 1220000 rects
+caravel_00069f13_fill_pattern_2_2: 930000 rects
+caravel_00069f13_fill_pattern_2_5: 1250000 rects
+caravel_00069f13_fill_pattern_3_4: 1770000 rects
+caravel_00069f13_fill_pattern_4_0: 1120000 rects
+caravel_00069f13_fill_pattern_3_0: 1390000 rects
+caravel_00069f13_fill_pattern_2_1: 1290000 rects
+caravel_00069f13_fill_pattern_3_7: 1070000 rects
+caravel_00069f13_fill_pattern_2_7: 580000 rects
+caravel_00069f13_fill_pattern_1_7: 1030000 rects
+caravel_00069f13_fill_pattern_3_5: 1300000 rects
+caravel_00069f13_fill_pattern_0_6: 1470000 rects
+caravel_00069f13_fill_pattern_1_1: 1310000 rects
+caravel_00069f13_fill_pattern_1_3: 1400000 rects
+caravel_00069f13_fill_pattern_2_6: 1350000 rects
+caravel_00069f13_fill_pattern_2_4: 1280000 rects
+caravel_00069f13_fill_pattern_0_4: 1670000 rects
+caravel_00069f13_fill_pattern_4_3: 1380000 rects
+caravel_00069f13_fill_pattern_1_6: 1230000 rects
+caravel_00069f13_fill_pattern_0_3: 1000000 rects
+caravel_00069f13_fill_pattern_3_3: 1110000 rects
+caravel_00069f13_fill_pattern_3_1: 1300000 rects
+caravel_00069f13_fill_pattern_3_4: 1780000 rects
+caravel_00069f13_fill_pattern_1_5: 1670000 rects
+caravel_00069f13_fill_pattern_3_0: 1400000 rects
+caravel_00069f13_fill_pattern_5_1: 870000 rects
+caravel_00069f13_fill_pattern_2_5: 1260000 rects
+caravel_00069f13_fill_pattern_4_4: 1530000 rects
+caravel_00069f13_fill_pattern_2_0: 1230000 rects
+caravel_00069f13_fill_pattern_1_2: 1240000 rects
+caravel_00069f13_fill_pattern_2_2: 940000 rects
+caravel_00069f13_fill_pattern_3_5: 1310000 rects
+caravel_00069f13_fill_pattern_1_1: 1320000 rects
+caravel_00069f13_fill_pattern_2_1: 1300000 rects
+caravel_00069f13_fill_pattern_0_0: 1400000 rects
+caravel_00069f13_fill_pattern_2_6: 1360000 rects
+caravel_00069f13_fill_pattern_2_4: 1290000 rects
+caravel_00069f13_fill_pattern_3_3: 1120000 rects
+caravel_00069f13_fill_pattern_0_6: 1480000 rects
+caravel_00069f13_fill_pattern_3_7: 1080000 rects
+caravel_00069f13_fill_pattern_1_6: 1240000 rects
+caravel_00069f13_fill_pattern_0_2: 1350000 rects
+caravel_00069f13_fill_pattern_3_4: 1790000 rects
+caravel_00069f13_fill_pattern_1_7: 1040000 rects
+caravel_00069f13_fill_pattern_3_0: 1410000 rects
+caravel_00069f13_fill_pattern_0_4: 1680000 rects
+caravel_00069f13_fill_pattern_1_3: 1410000 rects
+caravel_00069f13_fill_pattern_2_5: 1270000 rects
+caravel_00069f13_fill_pattern_2_7: 590000 rects
+caravel_00069f13_fill_pattern_3_1: 1310000 rects
+caravel_00069f13_fill_pattern_0_0: 1410000 rects
+caravel_00069f13_fill_pattern_1_5: 1680000 rects
+caravel_00069f13_fill_pattern_3_5: 1320000 rects
+caravel_00069f13_fill_pattern_1_1: 1330000 rects
+caravel_00069f13_fill_pattern_2_6: 1370000 rects
+caravel_00069f13_fill_pattern_5_1: 880000 rects
+caravel_00069f13_fill_pattern_2_0: 1240000 rects
+caravel_00069f13_fill_pattern_3_3: 1130000 rects
+caravel_00069f13_fill_pattern_4_4: 1540000 rects
+caravel_00069f13_fill_pattern_1_2: 1250000 rects
+caravel_00069f13_fill_pattern_2_1: 1310000 rects
+caravel_00069f13_fill_pattern_2_2: 950000 rects
+caravel_00069f13_fill_pattern_0_3: 1010000 rects
+caravel_00069f13_fill_pattern_0_6: 1490000 rects
+caravel_00069f13_fill_pattern_4_3: 1390000 rects
+caravel_00069f13_fill_pattern_2_4: 1300000 rects
+caravel_00069f13_fill_pattern_1_6: 1250000 rects
+caravel_00069f13_fill_pattern_4_0: 1130000 rects
+caravel_00069f13_fill_pattern_3_0: 1420000 rects
+caravel_00069f13_fill_pattern_3_4: 1800000 rects
+caravel_00069f13_fill_pattern_2_5: 1280000 rects
+caravel_00069f13_fill_pattern_2_6: 1380000 rects
+caravel_00069f13_fill_pattern_3_5: 1330000 rects
+caravel_00069f13_fill_pattern_3_3: 1140000 rects
+caravel_00069f13_fill_pattern_1_1: 1340000 rects
+caravel_00069f13_fill_pattern_1_7: 1050000 rects
+caravel_00069f13_fill_pattern_1_5: 1690000 rects
+caravel_00069f13_fill_pattern_3_1: 1320000 rects
+caravel_00069f13_fill_pattern_0_4: 1690000 rects
+caravel_00069f13_fill_pattern_0_0: 1420000 rects
+caravel_00069f13_fill_pattern_2_0: 1250000 rects
+caravel_00069f13_fill_pattern_4_4: 1550000 rects
+caravel_00069f13_fill_pattern_2_1: 1320000 rects
+caravel_00069f13_fill_pattern_1_3: 1420000 rects
+caravel_00069f13_fill_pattern_2_2: 960000 rects
+caravel_00069f13_fill_pattern_5_1: 890000 rects
+caravel_00069f13_fill_pattern_3_7: 1090000 rects
+caravel_00069f13_fill_pattern_2_4: 1310000 rects
+caravel_00069f13_fill_pattern_1_6: 1260000 rects
+caravel_00069f13_fill_pattern_3_0: 1430000 rects
+caravel_00069f13_fill_pattern_1_2: 1260000 rects
+caravel_00069f13_fill_pattern_3_3: 1150000 rects
+caravel_00069f13_fill_pattern_2_5: 1290000 rects
+caravel_00069f13_fill_pattern_0_6: 1500000 rects
+caravel_00069f13_fill_pattern_0_2: 1360000 rects
+caravel_00069f13_fill_pattern_2_6: 1390000 rects
+caravel_00069f13_fill_pattern_1_7: 1060000 rects
+caravel_00069f13_fill_pattern_2_7: 600000 rects
+caravel_00069f13_fill_pattern_1_1: 1350000 rects
+caravel_00069f13_fill_pattern_3_5: 1340000 rects
+caravel_00069f13_fill_pattern_3_4: 1810000 rects
+caravel_00069f13_fill_pattern_1_5: 1700000 rects
+caravel_00069f13_fill_pattern_0_4: 1700000 rects
+caravel_00069f13_fill_pattern_4_3: 1400000 rects
+caravel_00069f13_fill_pattern_3_1: 1330000 rects
+caravel_00069f13_fill_pattern_2_0: 1260000 rects
+caravel_00069f13_fill_pattern_3_3: 1160000 rects
+caravel_00069f13_fill_pattern_3_0: 1440000 rects
+caravel_00069f13_fill_pattern_2_1: 1330000 rects
+caravel_00069f13_fill_pattern_1_7: 1070000 rects
+caravel_00069f13_fill_pattern_0_3: 1020000 rects
+caravel_00069f13_fill_pattern_1_6: 1270000 rects
+caravel_00069f13_fill_pattern_2_6: 1400000 rects
+caravel_00069f13_fill_pattern_5_1: 900000 rects
+caravel_00069f13_fill_pattern_2_5: 1300000 rects
+caravel_00069f13_fill_pattern_4_4: 1560000 rects
+caravel_00069f13_fill_pattern_2_2: 970000 rects
+caravel_00069f13_fill_pattern_0_6: 1510000 rects
+caravel_00069f13_fill_pattern_1_1: 1360000 rects
+caravel_00069f13_fill_pattern_2_4: 1320000 rects
+caravel_00069f13_fill_pattern_3_5: 1350000 rects
+caravel_00069f13_fill_pattern_1_3: 1430000 rects
+caravel_00069f13_fill_pattern_3_7: 1100000 rects
+caravel_00069f13_fill_pattern_3_4: 1820000 rects
+caravel_00069f13_fill_pattern_2_0: 1270000 rects
+caravel_00069f13_fill_pattern_1_5: 1710000 rects
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+CIF output style is now "wafflefill(tiled)"
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+caravel_00069f13_fill_pattern_1_2: 1440000 rects
+caravel_00069f13_fill_pattern_2_2: 1160000 rects
+ Generating output for cell caravel_00069f13_fill_pattern_5_1
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+caravel_00069f13_fill_pattern_2_6: 1900000 rects
+caravel_00069f13_fill_pattern_1_6: 1720000 rects
+caravel_00069f13_fill_pattern_0_2: 1740000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00069f13_fill_pattern_2_0: 1680000 rects
+caravel_00069f13_fill_pattern_2_4: 1800000 rects
+caravel_00069f13_fill_pattern_0_4: 2130000 rects
+caravel_00069f13_fill_pattern_1_5: 2180000 rects
+caravel_00069f13_fill_pattern_2_7: 980000 rects
+caravel_00069f13_fill_pattern_0_6: 1970000 rects
+caravel_00069f13_fill_pattern_1_2: 1740000 rects
+caravel_00069f13_fill_pattern_0_3: 1440000 rects
+ Generating output for cell caravel_00069f13_fill_pattern_4_2
+caravel_00069f13_fill_pattern_2_2: 1470000 rects
+caravel_00069f13_fill_pattern_1_3: 1850000 rects
+caravel_00069f13_fill_pattern_4_4: 2010000 rects
+caravel_00069f13_fill_pattern_0_2: 1750000 rects
+caravel_00069f13_fill_pattern_2_5: 1790000 rects
+caravel_00069f13_fill_pattern_2_6: 1910000 rects
+caravel_00069f13_fill_pattern_1_6: 1730000 rects
+caravel_00069f13_fill_pattern_1_5: 2190000 rects
+caravel_00069f13_fill_pattern_0_0: 1760000 rects
+caravel_00069f13_fill_pattern_3_3: 1690000 rects
+caravel_00069f13_fill_pattern_2_4: 1810000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00069f13_fill_pattern_1_1: 1750000 rects
+caravel_00069f13_fill_pattern_0_6: 1980000 rects
+caravel_00069f13_fill_pattern_3_1: 1690000 rects
+caravel_00069f13_fill_pattern_0_4: 2140000 rects
+caravel_00069f13_fill_pattern_2_1: 1710000 rects
+caravel_00069f13_fill_pattern_3_0: 1850000 rects
+caravel_00069f13_fill_pattern_3_4: 2200000 rects
+caravel_00069f13_fill_pattern_4_3: 1610000 rects
+caravel_00069f13_fill_pattern_1_2: 1750000 rects
+caravel_00069f13_fill_pattern_0_3: 1450000 rects
+caravel_00069f13_fill_pattern_4_4: 2020000 rects
+caravel_00069f13_fill_pattern_3_5: 1550000 rects
+ Generating output for cell caravel_00069f13_fill_pattern_3_7
+caravel_00069f13_fill_pattern_1_3: 1860000 rects
+caravel_00069f13_fill_pattern_2_7: 990000 rects
+caravel_00069f13_fill_pattern_2_0: 1690000 rects
+caravel_00069f13_fill_pattern_0_2: 1760000 rects
+caravel_00069f13_fill_pattern_1_5: 2200000 rects
+caravel_00069f13_fill_pattern_2_5: 1800000 rects
+caravel_00069f13_fill_pattern_2_6: 1920000 rects
+caravel_00069f13_fill_pattern_4_0: 1330000 rects
+caravel_00069f13_fill_pattern_2_4: 1820000 rects
+caravel_00069f13_fill_pattern_2_2: 1480000 rects
+caravel_00069f13_fill_pattern_0_3: 1460000 rects
+caravel_00069f13_fill_pattern_0_0: 1770000 rects
+caravel_00069f13_fill_pattern_1_2: 1760000 rects
+caravel_00069f13_fill_pattern_1_5: 2210000 rects
+caravel_00069f13_fill_pattern_0_4: 2150000 rects
+caravel_00069f13_fill_pattern_3_0: 1860000 rects
+caravel_00069f13_fill_pattern_3_3: 1700000 rects
+caravel_00069f13_fill_pattern_1_3: 1870000 rects
+caravel_00069f13_fill_pattern_4_4: 2030000 rects
+caravel_00069f13_fill_pattern_3_4: 2210000 rects
+caravel_00069f13_fill_pattern_3_1: 1700000 rects
+caravel_00069f13_fill_pattern_0_6: 1990000 rects
+caravel_00069f13_fill_pattern_0_2: 1770000 rects
+caravel_00069f13_fill_pattern_2_4: 1830000 rects
+caravel_00069f13_fill_pattern_2_5: 1810000 rects
+caravel_00069f13_fill_pattern_2_6: 1930000 rects
+caravel_00069f13_fill_pattern_1_1: 1760000 rects
+caravel_00069f13_fill_pattern_2_7: 1000000 rects
+caravel_00069f13_fill_pattern_1_5: 2220000 rects
+caravel_00069f13_fill_pattern_2_0: 1700000 rects
+caravel_00069f13_fill_pattern_0_3: 1470000 rects
+caravel_00069f13_fill_pattern_1_2: 1770000 rects
+caravel_00069f13_fill_pattern_1_6: 1740000 rects
+caravel_00069f13_fill_pattern_4_4: 2040000 rects
+caravel_00069f13_fill_pattern_1_3: 1880000 rects
+caravel_00069f13_fill_pattern_0_2: 1780000 rects
+caravel_00069f13_fill_pattern_0_4: 2160000 rects
+caravel_00069f13_fill_pattern_3_0: 1870000 rects
+caravel_00069f13_fill_pattern_3_3: 1710000 rects
+caravel_00069f13_fill_pattern_2_4: 1840000 rects
+caravel_00069f13_fill_pattern_0_0: 1780000 rects
+caravel_00069f13_fill_pattern_4_3: 1620000 rects
+caravel_00069f13_fill_pattern_2_5: 1820000 rects
+caravel_00069f13_fill_pattern_3_1: 1710000 rects
+caravel_00069f13_fill_pattern_2_6: 1940000 rects
+caravel_00069f13_fill_pattern_1_5: 2230000 rects
+caravel_00069f13_fill_pattern_3_5: 1560000 rects
+caravel_00069f13_fill_pattern_3_4: 2220000 rects
+caravel_00069f13_fill_pattern_2_2: 1490000 rects
+caravel_00069f13_fill_pattern_0_3: 1480000 rects
+caravel_00069f13_fill_pattern_2_1: 1720000 rects
+caravel_00069f13_fill_pattern_2_7: 1010000 rects
+caravel_00069f13_fill_pattern_0_2: 1790000 rects
+caravel_00069f13_fill_pattern_1_3: 1890000 rects
+caravel_00069f13_fill_pattern_1_2: 1780000 rects
+caravel_00069f13_fill_pattern_4_4: 2050000 rects
+caravel_00069f13_fill_pattern_0_6: 2000000 rects
+caravel_00069f13_fill_pattern_3_0: 1880000 rects
+caravel_00069f13_fill_pattern_2_0: 1710000 rects
+caravel_00069f13_fill_pattern_0_4: 2170000 rects
+caravel_00069f13_fill_pattern_1_1: 1770000 rects
+caravel_00069f13_fill_pattern_4_0: 1340000 rects
+caravel_00069f13_fill_pattern_1_6: 1750000 rects
+caravel_00069f13_fill_pattern_2_5: 1830000 rects
+caravel_00069f13_fill_pattern_2_6: 1950000 rects
+caravel_00069f13_fill_pattern_2_4: 1850000 rects
+caravel_00069f13_fill_pattern_3_3: 1720000 rects
+caravel_00069f13_fill_pattern_0_0: 1790000 rects
+caravel_00069f13_fill_pattern_0_3: 1490000 rects
+caravel_00069f13_fill_pattern_0_2: 1800000 rects
+caravel_00069f13_fill_pattern_1_2: 1790000 rects
+caravel_00069f13_fill_pattern_3_4: 2230000 rects
+caravel_00069f13_fill_pattern_4_4: 2060000 rects
+caravel_00069f13_fill_pattern_1_3: 1900000 rects
+caravel_00069f13_fill_pattern_0_4: 2180000 rects
+caravel_00069f13_fill_pattern_3_0: 1890000 rects
+caravel_00069f13_fill_pattern_1_6: 1760000 rects
+caravel_00069f13_fill_pattern_2_5: 1840000 rects
+caravel_00069f13_fill_pattern_1_5: 2240000 rects
+caravel_00069f13_fill_pattern_2_6: 1960000 rects
+caravel_00069f13_fill_pattern_2_7: 1020000 rects
+caravel_00069f13_fill_pattern_2_0: 1720000 rects
+caravel_00069f13_fill_pattern_0_3: 1500000 rects
+caravel_00069f13_fill_pattern_4_3: 1630000 rects
+caravel_00069f13_fill_pattern_2_2: 1500000 rects
+caravel_00069f13_fill_pattern_0_6: 2010000 rects
+caravel_00069f13_fill_pattern_0_2: 1810000 rects
+caravel_00069f13_fill_pattern_3_1: 1720000 rects
+caravel_00069f13_fill_pattern_1_2: 1800000 rects
+caravel_00069f13_fill_pattern_1_1: 1780000 rects
+caravel_00069f13_fill_pattern_1_3: 1910000 rects
+caravel_00069f13_fill_pattern_3_3: 1730000 rects
+caravel_00069f13_fill_pattern_0_0: 1800000 rects
+caravel_00069f13_fill_pattern_0_4: 2190000 rects
+caravel_00069f13_fill_pattern_4_4: 2070000 rects
+caravel_00069f13_fill_pattern_2_5: 1850000 rects
+caravel_00069f13_fill_pattern_3_5: 1570000 rects
+caravel_00069f13_fill_pattern_1_6: 1770000 rects
+caravel_00069f13_fill_pattern_2_4: 1860000 rects
+caravel_00069f13_fill_pattern_3_0: 1900000 rects
+caravel_00069f13_fill_pattern_2_6: 1970000 rects
+caravel_00069f13_fill_pattern_3_4: 2240000 rects
+caravel_00069f13_fill_pattern_0_3: 1510000 rects
+caravel_00069f13_fill_pattern_0_2: 1820000 rects
+caravel_00069f13_fill_pattern_2_7: 1030000 rects
+caravel_00069f13_fill_pattern_1_3: 1920000 rects
+caravel_00069f13_fill_pattern_1_2: 1810000 rects
+caravel_00069f13_fill_pattern_4_0: 1350000 rects
+caravel_00069f13_fill_pattern_2_0: 1730000 rects
+caravel_00069f13_fill_pattern_2_1: 1730000 rects
+caravel_00069f13_fill_pattern_2_4: 1870000 rects
+caravel_00069f13_fill_pattern_3_3: 1740000 rects
+caravel_00069f13_fill_pattern_2_5: 1860000 rects
+caravel_00069f13_fill_pattern_1_6: 1780000 rects
+caravel_00069f13_fill_pattern_0_4: 2200000 rects
+caravel_00069f13_fill_pattern_2_6: 1980000 rects
+caravel_00069f13_fill_pattern_0_3: 1520000 rects
+caravel_00069f13_fill_pattern_3_0: 1910000 rects
+caravel_00069f13_fill_pattern_0_6: 2020000 rects
+caravel_00069f13_fill_pattern_2_2: 1510000 rects
+caravel_00069f13_fill_pattern_2_7: 1040000 rects
+caravel_00069f13_fill_pattern_0_0: 1810000 rects
+caravel_00069f13_fill_pattern_0_2: 1830000 rects
+caravel_00069f13_fill_pattern_1_5: 2250000 rects
+caravel_00069f13_fill_pattern_3_4: 2250000 rects
+caravel_00069f13_fill_pattern_1_3: 1930000 rects
+caravel_00069f13_fill_pattern_4_4: 2080000 rects
+caravel_00069f13_fill_pattern_1_2: 1820000 rects
+caravel_00069f13_fill_pattern_3_1: 1730000 rects
+caravel_00069f13_fill_pattern_2_4: 1880000 rects
+caravel_00069f13_fill_pattern_4_3: 1640000 rects
+caravel_00069f13_fill_pattern_1_1: 1790000 rects
+caravel_00069f13_fill_pattern_1_6: 1790000 rects
+caravel_00069f13_fill_pattern_2_7: 1050000 rects
+caravel_00069f13_fill_pattern_0_3: 1530000 rects
+caravel_00069f13_fill_pattern_2_6: 1990000 rects
+caravel_00069f13_fill_pattern_0_4: 2210000 rects
+caravel_00069f13_fill_pattern_3_0: 1920000 rects
+caravel_00069f13_fill_pattern_0_2: 1840000 rects
+caravel_00069f13_fill_pattern_2_0: 1740000 rects
+caravel_00069f13_fill_pattern_3_5: 1580000 rects
+caravel_00069f13_fill_pattern_1_3: 1940000 rects
+caravel_00069f13_fill_pattern_1_2: 1830000 rects
+caravel_00069f13_fill_pattern_2_7: 1060000 rects
+caravel_00069f13_fill_pattern_0_0: 1820000 rects
+caravel_00069f13_fill_pattern_3_3: 1750000 rects
+caravel_00069f13_fill_pattern_3_4: 2260000 rects
+caravel_00069f13_fill_pattern_0_6: 2030000 rects
+caravel_00069f13_fill_pattern_1_6: 1800000 rects
+caravel_00069f13_fill_pattern_1_1: 1800000 rects
+caravel_00069f13_fill_pattern_0_3: 1540000 rects
+caravel_00069f13_fill_pattern_2_5: 1870000 rects
+caravel_00069f13_fill_pattern_2_4: 1890000 rects
+caravel_00069f13_fill_pattern_2_6: 2000000 rects
+caravel_00069f13_fill_pattern_2_1: 1740000 rects
+caravel_00069f13_fill_pattern_0_4: 2220000 rects
+caravel_00069f13_fill_pattern_0_2: 1850000 rects
+caravel_00069f13_fill_pattern_2_2: 1520000 rects
+caravel_00069f13_fill_pattern_4_0: 1360000 rects
+caravel_00069f13_fill_pattern_3_0: 1930000 rects
+caravel_00069f13_fill_pattern_2_7: 1070000 rects
+caravel_00069f13_fill_pattern_4_4: 2090000 rects
+caravel_00069f13_fill_pattern_1_3: 1950000 rects
+caravel_00069f13_fill_pattern_3_3: 1760000 rects
+caravel_00069f13_fill_pattern_1_2: 1840000 rects
+caravel_00069f13_fill_pattern_2_0: 1750000 rects
+caravel_00069f13_fill_pattern_1_5: 2260000 rects
+caravel_00069f13_fill_pattern_0_3: 1550000 rects
+caravel_00069f13_fill_pattern_1_1: 1810000 rects
+caravel_00069f13_fill_pattern_1_6: 1810000 rects
+caravel_00069f13_fill_pattern_3_4: 2270000 rects
+caravel_00069f13_fill_pattern_3_1: 1740000 rects
+caravel_00069f13_fill_pattern_0_2: 1860000 rects
+caravel_00069f13_fill_pattern_2_6: 2010000 rects
+caravel_00069f13_fill_pattern_4_3: 1650000 rects
+caravel_00069f13_fill_pattern_0_0: 1830000 rects
+caravel_00069f13_fill_pattern_0_4: 2230000 rects
+caravel_00069f13_fill_pattern_2_7: 1080000 rects
+caravel_00069f13_fill_pattern_0_6: 2040000 rects
+caravel_00069f13_fill_pattern_3_0: 1940000 rects
+caravel_00069f13_fill_pattern_1_3: 1960000 rects
+caravel_00069f13_fill_pattern_2_4: 1900000 rects
+caravel_00069f13_fill_pattern_3_3: 1770000 rects
+caravel_00069f13_fill_pattern_1_2: 1850000 rects
+caravel_00069f13_fill_pattern_0_3: 1560000 rects
+caravel_00069f13_fill_pattern_2_5: 1880000 rects
+caravel_00069f13_fill_pattern_2_1: 1750000 rects
+caravel_00069f13_fill_pattern_1_6: 1820000 rects
+caravel_00069f13_fill_pattern_0_2: 1870000 rects
+caravel_00069f13_fill_pattern_2_2: 1530000 rects
+caravel_00069f13_fill_pattern_2_0: 1760000 rects
+caravel_00069f13_fill_pattern_2_6: 2020000 rects
+caravel_00069f13_fill_pattern_2_7: 1090000 rects
+caravel_00069f13_fill_pattern_3_5: 1590000 rects
+caravel_00069f13_fill_pattern_1_1: 1820000 rects
+caravel_00069f13_fill_pattern_0_4: 2240000 rects
+caravel_00069f13_fill_pattern_1_3: 1970000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00069f13_fill_pattern_3_3: 1780000 rects
+caravel_00069f13_fill_pattern_0_0: 1840000 rects
+caravel_00069f13_fill_pattern_3_0: 1950000 rects
+caravel_00069f13_fill_pattern_0_3: 1570000 rects
+caravel_00069f13_fill_pattern_1_2: 1860000 rects
+caravel_00069f13_fill_pattern_4_0: 1370000 rects
+caravel_00069f13_fill_pattern_2_7: 1100000 rects
+caravel_00069f13_fill_pattern_3_4: 2280000 rects
+caravel_00069f13_fill_pattern_0_2: 1880000 rects
+caravel_00069f13_fill_pattern_1_6: 1830000 rects
+caravel_00069f13_fill_pattern_4_4: 2100000 rects
+caravel_00069f13_fill_pattern_2_6: 2030000 rects
+caravel_00069f13_fill_pattern_3_1: 1750000 rects
+caravel_00069f13_fill_pattern_1_5: 2270000 rects
+ Generating output for cell caravel_00069f13_fill_pattern_1_7
+caravel_00069f13_fill_pattern_1_3: 1980000 rects
+caravel_00069f13_fill_pattern_0_6: 2050000 rects
+caravel_00069f13_fill_pattern_2_2: 1540000 rects
+caravel_00069f13_fill_pattern_3_3: 1790000 rects
+caravel_00069f13_fill_pattern_1_1: 1830000 rects
+caravel_00069f13_fill_pattern_0_4: 2250000 rects
+caravel_00069f13_fill_pattern_0_3: 1580000 rects
+caravel_00069f13_fill_pattern_4_3: 1660000 rects
+caravel_00069f13_fill_pattern_2_0: 1770000 rects
+caravel_00069f13_fill_pattern_2_1: 1760000 rects
+caravel_00069f13_fill_pattern_2_7: 1110000 rects
+caravel_00069f13_fill_pattern_2_4: 1910000 rects
+caravel_00069f13_fill_pattern_1_2: 1870000 rects
+caravel_00069f13_fill_pattern_3_0: 1960000 rects
+caravel_00069f13_fill_pattern_2_5: 1890000 rects
+caravel_00069f13_fill_pattern_0_2: 1890000 rects
+caravel_00069f13_fill_pattern_0_0: 1850000 rects
+caravel_00069f13_fill_pattern_1_6: 1840000 rects
+caravel_00069f13_fill_pattern_1_3: 1990000 rects
+caravel_00069f13_fill_pattern_2_6: 2040000 rects
+caravel_00069f13_fill_pattern_2_7: 1120000 rects
+caravel_00069f13_fill_pattern_3_3: 1800000 rects
+caravel_00069f13_fill_pattern_0_3: 1590000 rects
+caravel_00069f13_fill_pattern_2_4: 1920000 rects
+caravel_00069f13_fill_pattern_0_4: 2260000 rects
+caravel_00069f13_fill_pattern_3_4: 2290000 rects
+caravel_00069f13_fill_pattern_1_1: 1840000 rects
+caravel_00069f13_fill_pattern_3_5: 1600000 rects
+caravel_00069f13_fill_pattern_1_2: 1880000 rects
+caravel_00069f13_fill_pattern_2_2: 1550000 rects
+caravel_00069f13_fill_pattern_3_0: 1970000 rects
+caravel_00069f13_fill_pattern_0_2: 1900000 rects
+caravel_00069f13_fill_pattern_2_1: 1770000 rects
+caravel_00069f13_fill_pattern_2_0: 1780000 rects
+caravel_00069f13_fill_pattern_3_1: 1760000 rects
+caravel_00069f13_fill_pattern_1_3: 2000000 rects
+caravel_00069f13_fill_pattern_1_6: 1850000 rects
+caravel_00069f13_fill_pattern_0_6: 2060000 rects
+caravel_00069f13_fill_pattern_3_3: 1810000 rects
+caravel_00069f13_fill_pattern_2_4: 1930000 rects
+caravel_00069f13_fill_pattern_4_0: 1380000 rects
+caravel_00069f13_fill_pattern_0_3: 1600000 rects
+caravel_00069f13_fill_pattern_1_5: 2280000 rects
+caravel_00069f13_fill_pattern_0_0: 1860000 rects
+caravel_00069f13_fill_pattern_2_5: 1900000 rects
+caravel_00069f13_fill_pattern_0_4: 2270000 rects
+caravel_00069f13_fill_pattern_1_2: 1890000 rects
+caravel_00069f13_fill_pattern_0_2: 1910000 rects
+caravel_00069f13_fill_pattern_4_4: 2110000 rects
+caravel_00069f13_fill_pattern_3_0: 1980000 rects
+caravel_00069f13_fill_pattern_1_1: 1850000 rects
+caravel_00069f13_fill_pattern_4_3: 1670000 rects
+caravel_00069f13_fill_pattern_2_2: 1560000 rects
+caravel_00069f13_fill_pattern_1_3: 2010000 rects
+caravel_00069f13_fill_pattern_2_4: 1940000 rects
+caravel_00069f13_fill_pattern_3_3: 1820000 rects
+caravel_00069f13_fill_pattern_1_6: 1860000 rects
+caravel_00069f13_fill_pattern_3_4: 2300000 rects
+caravel_00069f13_fill_pattern_2_7: 1130000 rects
+caravel_00069f13_fill_pattern_2_6: 2050000 rects
+caravel_00069f13_fill_pattern_2_1: 1780000 rects
+caravel_00069f13_fill_pattern_2_0: 1790000 rects
+caravel_00069f13_fill_pattern_0_3: 1610000 rects
+caravel_00069f13_fill_pattern_0_2: 1920000 rects
+caravel_00069f13_fill_pattern_0_4: 2280000 rects
+caravel_00069f13_fill_pattern_1_2: 1900000 rects
+caravel_00069f13_fill_pattern_3_0: 1990000 rects
+caravel_00069f13_fill_pattern_0_0: 1870000 rects
+caravel_00069f13_fill_pattern_2_5: 1910000 rects
+caravel_00069f13_fill_pattern_1_3: 2020000 rects
+caravel_00069f13_fill_pattern_3_3: 1830000 rects
+caravel_00069f13_fill_pattern_1_1: 1860000 rects
+caravel_00069f13_fill_pattern_3_5: 1610000 rects
+caravel_00069f13_fill_pattern_1_6: 1870000 rects
+caravel_00069f13_fill_pattern_3_1: 1770000 rects
+caravel_00069f13_fill_pattern_2_2: 1570000 rects
+caravel_00069f13_fill_pattern_2_1: 1790000 rects
+caravel_00069f13_fill_pattern_0_2: 1930000 rects
+caravel_00069f13_fill_pattern_0_6: 2070000 rects
+caravel_00069f13_fill_pattern_2_0: 1800000 rects
+caravel_00069f13_fill_pattern_1_5: 2290000 rects
+caravel_00069f13_fill_pattern_2_4: 1950000 rects
+caravel_00069f13_fill_pattern_2_7: 1140000 rects
+caravel_00069f13_fill_pattern_0_4: 2290000 rects
+caravel_00069f13_fill_pattern_3_0: 2000000 rects
+caravel_00069f13_fill_pattern_1_2: 1910000 rects
+caravel_00069f13_fill_pattern_4_0: 1390000 rects
+caravel_00069f13_fill_pattern_3_4: 2310000 rects
+caravel_00069f13_fill_pattern_1_3: 2030000 rects
+caravel_00069f13_fill_pattern_3_3: 1840000 rects
+caravel_00069f13_fill_pattern_0_3: 1620000 rects
+caravel_00069f13_fill_pattern_2_5: 1920000 rects
+caravel_00069f13_fill_pattern_2_6: 2060000 rects
+caravel_00069f13_fill_pattern_1_1: 1870000 rects
+caravel_00069f13_fill_pattern_4_3: 1680000 rects
+caravel_00069f13_fill_pattern_0_0: 1880000 rects
+caravel_00069f13_fill_pattern_1_6: 1880000 rects
+caravel_00069f13_fill_pattern_4_4: 2120000 rects
+caravel_00069f13_fill_pattern_0_2: 1940000 rects
+caravel_00069f13_fill_pattern_1_2: 1920000 rects
+caravel_00069f13_fill_pattern_2_2: 1580000 rects
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+caravel_00069f13_fill_pattern_1_3: 2530000 rects
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+caravel_00069f13_fill_pattern_4_0: 1560000 rects
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+caravel_00069f13_fill_pattern_4_4: 2300000 rects
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+caravel_00069f13_fill_pattern_3_5: 1800000 rects
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+caravel_00069f13_fill_pattern_0_0: 2240000 rects
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+caravel_00069f13_fill_pattern_1_1: 2180000 rects
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+caravel_00069f13_fill_pattern_1_3: 2560000 rects
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+caravel_00069f13_fill_pattern_2_0: 2200000 rects
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+caravel_00069f13_fill_pattern_1_2: 2290000 rects
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+caravel_00069f13_fill_pattern_3_1: 2090000 rects
+caravel_00069f13_fill_pattern_2_2: 1950000 rects
+caravel_00069f13_fill_pattern_2_6: 2420000 rects
+caravel_00069f13_fill_pattern_2_4: 2410000 rects
+caravel_00069f13_fill_pattern_0_4: 2610000 rects
+caravel_00069f13_fill_pattern_2_0: 2210000 rects
+caravel_00069f13_fill_pattern_1_3: 2570000 rects
+caravel_00069f13_fill_pattern_3_5: 1810000 rects
+caravel_00069f13_fill_pattern_3_4: 2710000 rects
+caravel_00069f13_fill_pattern_1_2: 2300000 rects
+caravel_00069f13_fill_pattern_4_4: 2320000 rects
+caravel_00069f13_fill_pattern_4_3: 1900000 rects
+caravel_00069f13_fill_pattern_2_2: 1960000 rects
+caravel_00069f13_fill_pattern_2_5: 2280000 rects
+caravel_00069f13_fill_pattern_2_1: 2200000 rects
+caravel_00069f13_fill_pattern_2_0: 2220000 rects
+caravel_00069f13_fill_pattern_2_6: 2430000 rects
+caravel_00069f13_fill_pattern_3_0: 2350000 rects
+caravel_00069f13_fill_pattern_1_1: 2200000 rects
+Ended: 11/15/2022 21:23:36
+caravel_00069f13_fill_pattern_4_0: 1590000 rects
+caravel_00069f13_fill_pattern_3_4: 2720000 rects
+caravel_00069f13_fill_pattern_1_3: 2580000 rects
+caravel_00069f13_fill_pattern_3_3: 2260000 rects
+caravel_00069f13_fill_pattern_0_0: 2250000 rects
+caravel_00069f13_fill_pattern_0_6: 2280000 rects
+caravel_00069f13_fill_pattern_3_1: 2100000 rects
+caravel_00069f13_fill_pattern_1_2: 2310000 rects
+caravel_00069f13_fill_pattern_1_5: 2500000 rects
+caravel_00069f13_fill_pattern_2_0: 2230000 rects
+caravel_00069f13_fill_pattern_2_4: 2420000 rects
+caravel_00069f13_fill_pattern_2_2: 1970000 rects
+caravel_00069f13_fill_pattern_1_6: 2180000 rects
+caravel_00069f13_fill_pattern_2_1: 2210000 rects
+caravel_00069f13_fill_pattern_2_5: 2290000 rects
+caravel_00069f13_fill_pattern_3_4: 2730000 rects
+caravel_00069f13_fill_pattern_2_6: 2440000 rects
+caravel_00069f13_fill_pattern_2_0: 2240000 rects
+caravel_00069f13_fill_pattern_1_3: 2590000 rects
+caravel_00069f13_fill_pattern_0_4: 2620000 rects
+caravel_00069f13_fill_pattern_3_3: 2270000 rects
+caravel_00069f13_fill_pattern_1_1: 2210000 rects
+caravel_00069f13_fill_pattern_2_1: 2220000 rects
+caravel_00069f13_fill_pattern_1_2: 2320000 rects
+caravel_00069f13_fill_pattern_3_5: 1820000 rects
+caravel_00069f13_fill_pattern_0_3: 1780000 rects
+caravel_00069f13_fill_pattern_4_3: 1910000 rects
+caravel_00069f13_fill_pattern_2_2: 1980000 rects
+caravel_00069f13_fill_pattern_3_0: 2360000 rects
+caravel_00069f13_fill_pattern_4_0: 1600000 rects
+caravel_00069f13_fill_pattern_2_0: 2250000 rects
+caravel_00069f13_fill_pattern_4_4: 2330000 rects
+caravel_00069f13_fill_pattern_2_5: 2300000 rects
+caravel_00069f13_fill_pattern_3_4: 2740000 rects
+caravel_00069f13_fill_pattern_3_1: 2110000 rects
+caravel_00069f13_fill_pattern_2_4: 2430000 rects
+caravel_00069f13_fill_pattern_2_1: 2230000 rects
+caravel_00069f13_fill_pattern_1_3: 2600000 rects
+caravel_00069f13_fill_pattern_2_6: 2450000 rects
+caravel_00069f13_fill_pattern_2_0: 2260000 rects
+caravel_00069f13_fill_pattern_3_3: 2280000 rects
+caravel_00069f13_fill_pattern_1_2: 2330000 rects
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_00069f13_fill_pattern_2_2: 1990000 rects
+caravel_00069f13_fill_pattern_1_1: 2220000 rects
+caravel_00069f13_fill_pattern_1_6: 2190000 rects
+caravel_00069f13_fill_pattern_0_6: 2290000 rects
+caravel_00069f13_fill_pattern_3_4: 2750000 rects
+caravel_00069f13_fill_pattern_2_1: 2240000 rects
+caravel_00069f13_fill_pattern_2_5: 2310000 rects
+caravel_00069f13_fill_pattern_1_5: 2510000 rects
+caravel_00069f13_fill_pattern_2_0: 2270000 rects
+caravel_00069f13_fill_pattern_3_0: 2370000 rects
+caravel_00069f13_fill_pattern_1_2: 2340000 rects
+caravel_00069f13_fill_pattern_1_3: 2610000 rects
+caravel_00069f13_fill_pattern_0_0: 2260000 rects
+caravel_00069f13_fill_pattern_4_0: 1610000 rects
+caravel_00069f13_fill_pattern_3_3: 2290000 rects
+caravel_00069f13_fill_pattern_2_6: 2460000 rects
+caravel_00069f13_fill_pattern_0_4: 2630000 rects
+caravel_00069f13_fill_pattern_4_3: 1920000 rects
+caravel_00069f13_fill_pattern_2_1: 2250000 rects
+caravel_00069f13_fill_pattern_2_0: 2280000 rects
+caravel_00069f13_fill_pattern_3_4: 2760000 rects
+caravel_00069f13_fill_pattern_3_1: 2120000 rects
+caravel_00069f13_fill_pattern_2_4: 2440000 rects
+caravel_00069f13_fill_pattern_1_1: 2230000 rects
+caravel_00069f13_fill_pattern_4_4: 2340000 rects
+caravel_00069f13_fill_pattern_3_5: 1830000 rects
+caravel_00069f13_fill_pattern_2_5: 2320000 rects
+caravel_00069f13_fill_pattern_2_2: 2000000 rects
+caravel_00069f13_fill_pattern_1_2: 2350000 rects
+caravel_00069f13_fill_pattern_2_1: 2260000 rects
+caravel_00069f13_fill_pattern_2_0: 2290000 rects
+caravel_00069f13_fill_pattern_1_3: 2620000 rects
+caravel_00069f13_fill_pattern_3_3: 2300000 rects
+Processing system .magicrc file
+caravel_00069f13_fill_pattern_2_6: 2470000 rects
+caravel_00069f13_fill_pattern_3_4: 2770000 rects
+caravel_00069f13_fill_pattern_0_3: 1790000 rects
+caravel_00069f13_fill_pattern_3_0: 2380000 rects
+caravel_00069f13_fill_pattern_0_6: 2300000 rects
+caravel_00069f13_fill_pattern_1_6: 2200000 rects
+caravel_00069f13_fill_pattern_2_1: 2270000 rects
+caravel_00069f13_fill_pattern_2_0: 2300000 rects
+caravel_00069f13_fill_pattern_4_0: 1620000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00069f13_fill_pattern_1_3: 2630000 rects
+caravel_00069f13_fill_pattern_1_1: 2240000 rects
+caravel_00069f13_fill_pattern_1_2: 2360000 rects
+Sourcing design .magicrc for technology sky130A ...
+caravel_00069f13_fill_pattern_2_5: 2330000 rects
+2 Magic internal units = 1 Lambda
+caravel_00069f13_fill_pattern_1_5: 2520000 rects
+caravel_00069f13_fill_pattern_2_4: 2450000 rects
+caravel_00069f13_fill_pattern_3_1: 2130000 rects
+ Generating output for cell caravel_00069f13_fill_pattern_2_7
+caravel_00069f13_fill_pattern_3_3: 2310000 rects
+caravel_00069f13_fill_pattern_2_2: 2010000 rects
+caravel_00069f13_fill_pattern_2_1: 2280000 rects
+caravel_00069f13_fill_pattern_4_3: 1930000 rects
+caravel_00069f13_fill_pattern_3_4: 2780000 rects
+caravel_00069f13_fill_pattern_0_4: 2640000 rects
+caravel_00069f13_fill_pattern_2_6: 2480000 rects
+caravel_00069f13_fill_pattern_2_0: 2310000 rects
+caravel_00069f13_fill_pattern_1_2: 2370000 rects
+caravel_00069f13_fill_pattern_0_0: 2270000 rects
+caravel_00069f13_fill_pattern_0_2: 2310000 rects
+caravel_00069f13_fill_pattern_2_1: 2290000 rects
+caravel_00069f13_fill_pattern_3_0: 2390000 rects
+caravel_00069f13_fill_pattern_1_1: 2250000 rects
+caravel_00069f13_fill_pattern_2_5: 2340000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_00069f13_fill_pattern_4_4: 2350000 rects
+caravel_00069f13_fill_pattern_1_3: 2640000 rects
+caravel_00069f13_fill_pattern_2_4: 2460000 rects
+caravel_00069f13_fill_pattern_2_2: 2020000 rects
+caravel_00069f13_fill_pattern_2_0: 2320000 rects
+caravel_00069f13_fill_pattern_3_3: 2320000 rects
+caravel_00069f13_fill_pattern_3_5: 1840000 rects
+caravel_00069f13_fill_pattern_3_1: 2140000 rects
+caravel_00069f13_fill_pattern_4_0: 1630000 rects
+caravel_00069f13_fill_pattern_2_6: 2490000 rects
+caravel_00069f13_fill_pattern_3_4: 2790000 rects
+caravel_00069f13_fill_pattern_2_1: 2300000 rects
+caravel_00069f13_fill_pattern_0_6: 2310000 rects
+caravel_00069f13_fill_pattern_1_2: 2380000 rects
+caravel_00069f13_fill_pattern_1_6: 2210000 rects
+caravel_00069f13_fill_pattern_2_5: 2350000 rects
+caravel_00069f13_fill_pattern_2_0: 2330000 rects
+caravel_00069f13_fill_pattern_2_2: 2030000 rects
+caravel_00069f13_fill_pattern_1_5: 2530000 rects
+caravel_00069f13_fill_pattern_1_1: 2260000 rects
+caravel_00069f13_fill_pattern_2_4: 2470000 rects
+caravel_00069f13_fill_pattern_4_3: 1940000 rects
+caravel_00069f13_fill_pattern_0_3: 1800000 rects
+caravel_00069f13_fill_pattern_3_0: 2400000 rects
+caravel_00069f13_fill_pattern_2_1: 2310000 rects
+caravel_00069f13_fill_pattern_0_4: 2650000 rects
+caravel_00069f13_fill_pattern_1_2: 2390000 rects
+caravel_00069f13_fill_pattern_3_3: 2330000 rects
+caravel_00069f13_fill_pattern_2_6: 2500000 rects
+caravel_00069f13_fill_pattern_2_0: 2340000 rects
+caravel_00069f13_fill_pattern_1_3: 2650000 rects
+caravel_00069f13_fill_pattern_2_2: 2040000 rects
+caravel_00069f13_fill_pattern_3_1: 2150000 rects
+caravel_00069f13_fill_pattern_4_0: 1640000 rects
+caravel_00069f13_fill_pattern_4_4: 2360000 rects
+caravel_00069f13_fill_pattern_2_1: 2320000 rects
+caravel_00069f13_fill_pattern_2_4: 2480000 rects
+caravel_00069f13_fill_pattern_2_0: 2350000 rects
+caravel_00069f13_fill_pattern_1_2: 2400000 rects
+caravel_00069f13_fill_pattern_1_1: 2270000 rects
+caravel_00069f13_fill_pattern_2_5: 2360000 rects
+caravel_00069f13_fill_pattern_1_6: 2220000 rects
+caravel_00069f13_fill_pattern_3_3: 2340000 rects
+caravel_00069f13_fill_pattern_3_4: 2800000 rects
+caravel_00069f13_fill_pattern_0_6: 2320000 rects
+caravel_00069f13_fill_pattern_3_0: 2410000 rects
+caravel_00069f13_fill_pattern_2_6: 2510000 rects
+caravel_00069f13_fill_pattern_2_2: 2050000 rects
+caravel_00069f13_fill_pattern_2_1: 2330000 rects
+caravel_00069f13_fill_pattern_3_5: 1850000 rects
+caravel_00069f13_fill_pattern_2_0: 2360000 rects
+caravel_00069f13_fill_pattern_1_5: 2540000 rects
+caravel_00069f13_fill_pattern_4_3: 1950000 rects
+caravel_00069f13_fill_pattern_1_2: 2410000 rects
+caravel_00069f13_fill_pattern_1_3: 2660000 rects
+caravel_00069f13_fill_pattern_2_5: 2370000 rects
+caravel_00069f13_fill_pattern_2_4: 2490000 rects
+caravel_00069f13_fill_pattern_3_1: 2160000 rects
+caravel_00069f13_fill_pattern_0_4: 2660000 rects
+caravel_00069f13_fill_pattern_2_1: 2340000 rects
+caravel_00069f13_fill_pattern_2_2: 2060000 rects
+caravel_00069f13_fill_pattern_2_0: 2370000 rects
+caravel_00069f13_fill_pattern_4_0: 1650000 rects
+caravel_00069f13_fill_pattern_3_3: 2350000 rects
+caravel_00069f13_fill_pattern_2_6: 2520000 rects
+caravel_00069f13_fill_pattern_1_1: 2280000 rects
+caravel_00069f13_fill_pattern_0_3: 1810000 rects
+caravel_00069f13_fill_pattern_3_0: 2420000 rects
+caravel_00069f13_fill_pattern_4_4: 2370000 rects
+caravel_00069f13_fill_pattern_1_2: 2420000 rects
+caravel_00069f13_fill_pattern_2_1: 2350000 rects
+caravel_00069f13_fill_pattern_2_0: 2380000 rects
+caravel_00069f13_fill_pattern_1_6: 2230000 rects
+caravel_00069f13_fill_pattern_2_5: 2380000 rects
+caravel_00069f13_fill_pattern_2_4: 2500000 rects
+caravel_00069f13_fill_pattern_2_2: 2070000 rects
+caravel_00069f13_fill_pattern_0_6: 2330000 rects
+caravel_00069f13_fill_pattern_3_4: 2810000 rects
+caravel_00069f13_fill_pattern_2_6: 2530000 rects
+caravel_00069f13_fill_pattern_3_5: 1860000 rects
+caravel_00069f13_fill_pattern_1_3: 2670000 rects
+caravel_00069f13_fill_pattern_1_2: 2430000 rects
+caravel_00069f13_fill_pattern_3_1: 2170000 rects
+caravel_00069f13_fill_pattern_4_3: 1960000 rects
+caravel_00069f13_fill_pattern_2_0: 2390000 rects
+caravel_00069f13_fill_pattern_2_1: 2360000 rects
+caravel_00069f13_fill_pattern_0_2: 2320000 rects
+caravel_00069f13_fill_pattern_0_0: 2280000 rects
+caravel_00069f13_fill_pattern_1_5: 2550000 rects
+caravel_00069f13_fill_pattern_4_0: 1660000 rects
+caravel_00069f13_fill_pattern_2_2: 2080000 rects
+caravel_00069f13_fill_pattern_3_3: 2360000 rects
+caravel_00069f13_fill_pattern_2_5: 2390000 rects
+caravel_00069f13_fill_pattern_3_0: 2430000 rects
+caravel_00069f13_fill_pattern_1_1: 2290000 rects
+caravel_00069f13_fill_pattern_2_4: 2510000 rects
+caravel_00069f13_fill_pattern_0_4: 2670000 rects
+caravel_00069f13_fill_pattern_2_1: 2370000 rects
+caravel_00069f13_fill_pattern_2_0: 2400000 rects
+caravel_00069f13_fill_pattern_1_2: 2440000 rects
+caravel_00069f13_fill_pattern_2_6: 2540000 rects
+caravel_00069f13_fill_pattern_3_1: 2180000 rects
+caravel_00069f13_fill_pattern_2_5: 2400000 rects
+caravel_00069f13_fill_pattern_1_6: 2240000 rects
+caravel_00069f13_fill_pattern_4_4: 2380000 rects
+caravel_00069f13_fill_pattern_2_2: 2090000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+caravel_00069f13_fill_pattern_2_0: 2410000 rects
+caravel_00069f13_fill_pattern_1_3: 2680000 rects
+caravel_00069f13_fill_pattern_2_1: 2380000 rects
+caravel_00069f13_fill_pattern_0_6: 2340000 rects
+caravel_00069f13_fill_pattern_3_4: 2820000 rects
+caravel_00069f13_fill_pattern_1_2: 2450000 rects
+caravel_00069f13_fill_pattern_2_4: 2520000 rects
+caravel_00069f13_fill_pattern_3_1: 2190000 rects
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+caravel_00069f13_fill_pattern_1_1: 2300000 rects
+caravel_00069f13_fill_pattern_0_3: 1820000 rects
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_00069f13_fill_pattern_3_3: 2370000 rects
+caravel_00069f13_fill_pattern_3_0: 2440000 rects
+caravel_00069f13_fill_pattern_4_3: 1970000 rects
+caravel_00069f13_fill_pattern_4_0: 1670000 rects
+caravel_00069f13_fill_pattern_2_6: 2550000 rects
+caravel_00069f13_fill_pattern_2_2: 2100000 rects
+caravel_00069f13_fill_pattern_2_5: 2410000 rects
+caravel_00069f13_fill_pattern_2_0: 2420000 rects
+caravel_00069f13_fill_pattern_1_5: 2560000 rects
+caravel_00069f13_fill_pattern_2_1: 2390000 rects
+caravel_00069f13_fill_pattern_3_1: 2200000 rects
+caravel_00069f13_fill_pattern_1_2: 2460000 rects
+caravel_00069f13_fill_pattern_0_4: 2680000 rects
+caravel_00069f13_fill_pattern_2_4: 2530000 rects
+caravel_00069f13_fill_pattern_3_1: 2210000 rects
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+caravel_00069f13_fill_pattern_0_0: 2430000 rects
+caravel_00069f13_fill_pattern_4_0: 2040000 rects
+caravel_00069f13_fill_pattern_2_6: 2910000 rects
+caravel_00069f13_fill_pattern_4_3: 2280000 rects
+caravel_00069f13_fill_pattern_0_2: 2580000 rects
+caravel_00069f13_fill_pattern_3_5: 2060000 rects
+caravel_00069f13_fill_pattern_3_0: 2690000 rects
+caravel_00069f13_fill_pattern_4_4: 2580000 rects
+caravel_00069f13_fill_pattern_1_2: 2920000 rects
+caravel_00069f13_fill_pattern_1_5: 2750000 rects
+caravel_00069f13_fill_pattern_2_5: 2820000 rects
+caravel_00069f13_fill_pattern_2_2: 2560000 rects
+caravel_00069f13_fill_pattern_4_5: 640000 rects
+caravel_00069f13_fill_pattern_2_4: 2890000 rects
+caravel_00069f13_fill_pattern_1_1: 2710000 rects
+caravel_00069f13_fill_pattern_1_6: 2440000 rects
+caravel_00069f13_fill_pattern_0_2: 2590000 rects
+caravel_00069f13_fill_pattern_3_3: 2750000 rects
+caravel_00069f13_fill_pattern_3_1: 2490000 rects
+caravel_00069f13_fill_pattern_2_1: 2550000 rects
+caravel_00069f13_fill_pattern_2_5: 2830000 rects
+caravel_00069f13_fill_pattern_0_6: 2530000 rects
+caravel_00069f13_fill_pattern_4_3: 2290000 rects
+caravel_00069f13_fill_pattern_2_6: 2920000 rects
+caravel_00069f13_fill_pattern_0_2: 2600000 rects
+caravel_00069f13_fill_pattern_1_2: 2930000 rects
+caravel_00069f13_fill_pattern_4_5: 650000 rects
+caravel_00069f13_fill_pattern_4_0: 2050000 rects
+caravel_00069f13_fill_pattern_1_1: 2720000 rects
+caravel_00069f13_fill_pattern_2_2: 2570000 rects
+caravel_00069f13_fill_pattern_2_0: 2540000 rects
+caravel_00069f13_fill_pattern_1_3: 2930000 rects
+caravel_00069f13_fill_pattern_0_4: 2890000 rects
+caravel_00069f13_fill_pattern_2_5: 2840000 rects
+caravel_00069f13_fill_pattern_3_4: 3010000 rects
+caravel_00069f13_fill_pattern_0_2: 2610000 rects
+caravel_00069f13_fill_pattern_3_0: 2700000 rects
+caravel_00069f13_fill_pattern_2_4: 2900000 rects
+caravel_00069f13_fill_pattern_1_2: 2940000 rects
+caravel_00069f13_fill_pattern_4_5: 660000 rects
+caravel_00069f13_fill_pattern_1_1: 2730000 rects
+caravel_00069f13_fill_pattern_2_6: 2930000 rects
+caravel_00069f13_fill_pattern_3_5: 2070000 rects
+caravel_00069f13_fill_pattern_0_2: 2620000 rects
+caravel_00069f13_fill_pattern_2_2: 2580000 rects
+caravel_00069f13_fill_pattern_2_5: 2850000 rects
+caravel_00069f13_fill_pattern_4_3: 2300000 rects
+caravel_00069f13_fill_pattern_1_5: 2760000 rects
+caravel_00069f13_fill_pattern_4_4: 2590000 rects
+caravel_00069f13_fill_pattern_0_0: 2440000 rects
+caravel_00069f13_fill_pattern_1_6: 2450000 rects
+caravel_00069f13_fill_pattern_0_2: 2630000 rects
+caravel_00069f13_fill_pattern_4_5: 670000 rects
+caravel_00069f13_fill_pattern_1_2: 2950000 rects
+caravel_00069f13_fill_pattern_2_4: 2910000 rects
+caravel_00069f13_fill_pattern_3_3: 2760000 rects
+caravel_00069f13_fill_pattern_1_1: 2740000 rects
+caravel_00069f13_fill_pattern_2_2: 2590000 rects
+caravel_00069f13_fill_pattern_2_5: 2860000 rects
+caravel_00069f13_fill_pattern_3_0: 2710000 rects
+caravel_00069f13_fill_pattern_1_3: 2940000 rects
+caravel_00069f13_fill_pattern_4_3: 2310000 rects
+caravel_00069f13_fill_pattern_2_6: 2940000 rects
+caravel_00069f13_fill_pattern_0_2: 2640000 rects
+caravel_00069f13_fill_pattern_3_1: 2500000 rects
+caravel_00069f13_fill_pattern_0_6: 2540000 rects
+caravel_00069f13_fill_pattern_4_5: 680000 rects
+caravel_00069f13_fill_pattern_3_4: 3020000 rects
+caravel_00069f13_fill_pattern_1_2: 2960000 rects
+caravel_00069f13_fill_pattern_2_1: 2560000 rects
+caravel_00069f13_fill_pattern_0_4: 2900000 rects
+caravel_00069f13_fill_pattern_4_0: 2060000 rects
+caravel_00069f13_fill_pattern_2_2: 2600000 rects
+caravel_00069f13_fill_pattern_0_2: 2650000 rects
+caravel_00069f13_fill_pattern_4_3: 2320000 rects
+caravel_00069f13_fill_pattern_2_4: 2920000 rects
+caravel_00069f13_fill_pattern_3_5: 2080000 rects
+caravel_00069f13_fill_pattern_4_5: 690000 rects
+caravel_00069f13_fill_pattern_1_5: 2770000 rects
+caravel_00069f13_fill_pattern_2_6: 2950000 rects
+caravel_00069f13_fill_pattern_1_2: 2970000 rects
+caravel_00069f13_fill_pattern_4_4: 2600000 rects
+caravel_00069f13_fill_pattern_3_0: 2720000 rects
+caravel_00069f13_fill_pattern_1_6: 2460000 rects
+caravel_00069f13_fill_pattern_2_2: 2610000 rects
+caravel_00069f13_fill_pattern_1_3: 2950000 rects
+caravel_00069f13_fill_pattern_3_3: 2770000 rects
+caravel_00069f13_fill_pattern_4_5: 700000 rects
+caravel_00069f13_fill_pattern_0_2: 2660000 rects
+Ended: 11/15/2022 21:23:39
+caravel_00069f13_fill_pattern_0_0: 2450000 rects
+caravel_00069f13_fill_pattern_2_4: 2930000 rects
+caravel_00069f13_fill_pattern_1_2: 2980000 rects
+caravel_00069f13_fill_pattern_2_0: 2550000 rects
+caravel_00069f13_fill_pattern_0_6: 2550000 rects
+caravel_00069f13_fill_pattern_2_6: 2960000 rects
+caravel_00069f13_fill_pattern_3_4: 3030000 rects
+caravel_00069f13_fill_pattern_2_2: 2620000 rects
+caravel_00069f13_fill_pattern_4_3: 2330000 rects
+caravel_00069f13_fill_pattern_4_0: 2070000 rects
+caravel_00069f13_fill_pattern_4_5: 710000 rects
+caravel_00069f13_fill_pattern_3_1: 2510000 rects
+caravel_00069f13_fill_pattern_3_5: 2090000 rects
+caravel_00069f13_fill_pattern_0_4: 2910000 rects
+caravel_00069f13_fill_pattern_2_5: 2870000 rects
+caravel_00069f13_fill_pattern_1_1: 2750000 rects
+caravel_00069f13_fill_pattern_3_0: 2730000 rects
+caravel_00069f13_fill_pattern_1_2: 2990000 rects
+caravel_00069f13_fill_pattern_4_4: 2610000 rects
+caravel_00069f13_fill_pattern_1_5: 2780000 rects
+caravel_00069f13_fill_pattern_0_2: 2670000 rects
+caravel_00069f13_fill_pattern_2_4: 2940000 rects
+caravel_00069f13_fill_pattern_1_6: 2470000 rects
+caravel_00069f13_fill_pattern_2_6: 2970000 rects
+caravel_00069f13_fill_pattern_4_5: 720000 rects
+caravel_00069f13_fill_pattern_1_3: 2960000 rects
+caravel_00069f13_fill_pattern_2_2: 2630000 rects
+caravel_00069f13_fill_pattern_3_3: 2780000 rects
+caravel_00069f13_fill_pattern_1_2: 3000000 rects
+caravel_00069f13_fill_pattern_4_0: 2080000 rects
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_00069f13_fill_pattern_4_3: 2340000 rects
+caravel_00069f13_fill_pattern_2_1: 2570000 rects
+caravel_00069f13_fill_pattern_0_0: 2460000 rects
+caravel_00069f13_fill_pattern_2_4: 2950000 rects
+caravel_00069f13_fill_pattern_0_2: 2680000 rects
+caravel_00069f13_fill_pattern_3_4: 3040000 rects
+caravel_00069f13_fill_pattern_2_2: 2640000 rects
+caravel_00069f13_fill_pattern_2_6: 2980000 rects
+caravel_00069f13_fill_pattern_3_0: 2740000 rects
+caravel_00069f13_fill_pattern_4_4: 2620000 rects
+caravel_00069f13_fill_pattern_1_2: 3010000 rects
+caravel_00069f13_fill_pattern_0_6: 2560000 rects
+caravel_00069f13_fill_pattern_4_5: 730000 rects
+caravel_00069f13_fill_pattern_3_5: 2100000 rects
+caravel_00069f13_fill_pattern_1_3: 2970000 rects
+caravel_00069f13_fill_pattern_0_4: 2920000 rects
+caravel_00069f13_fill_pattern_1_5: 2790000 rects
+caravel_00069f13_fill_pattern_4_0: 2090000 rects
+caravel_00069f13_fill_pattern_1_6: 2480000 rects
+caravel_00069f13_fill_pattern_3_1: 2520000 rects
+caravel_00069f13_fill_pattern_2_2: 2650000 rects
+caravel_00069f13_fill_pattern_2_6: 2990000 rects
+Processing system .magicrc file
+caravel_00069f13_fill_pattern_4_3: 2350000 rects
+caravel_00069f13_fill_pattern_2_4: 2960000 rects
+caravel_00069f13_fill_pattern_1_2: 3020000 rects
+caravel_00069f13_fill_pattern_2_5: 2880000 rects
+caravel_00069f13_fill_pattern_3_3: 2790000 rects
+caravel_00069f13_fill_pattern_0_2: 2690000 rects
+caravel_00069f13_fill_pattern_0_0: 2470000 rects
+caravel_00069f13_fill_pattern_4_5: 740000 rects
+caravel_00069f13_fill_pattern_3_0: 2750000 rects
+Sourcing design .magicrc for technology sky130A ...
+caravel_00069f13_fill_pattern_2_0: 2560000 rects
+2 Magic internal units = 1 Lambda
+caravel_00069f13_fill_pattern_2_6: 3000000 rects
+caravel_00069f13_fill_pattern_2_2: 2660000 rects
+caravel_00069f13_fill_pattern_1_2: 3030000 rects
+caravel_00069f13_fill_pattern_3_4: 3050000 rects
+caravel_00069f13_fill_pattern_1_3: 2980000 rects
+caravel_00069f13_fill_pattern_2_6: 3010000 rects
+caravel_00069f13_fill_pattern_4_5: 750000 rects
+caravel_00069f13_fill_pattern_4_0: 2100000 rects
+Ended: 11/15/2022 21:23:40
+caravel_00069f13_fill_pattern_0_6: 2570000 rects
+caravel_00069f13_fill_pattern_4_3: 2360000 rects
+caravel_00069f13_fill_pattern_2_4: 2970000 rects
+caravel_00069f13_fill_pattern_1_1: 2760000 rects
+caravel_00069f13_fill_pattern_0_2: 2700000 rects
+caravel_00069f13_fill_pattern_3_5: 2110000 rects
+caravel_00069f13_fill_pattern_2_2: 2670000 rects
+caravel_00069f13_fill_pattern_4_4: 2630000 rects
+caravel_00069f13_fill_pattern_1_2: 3040000 rects
+caravel_00069f13_fill_pattern_0_0: 2480000 rects
+caravel_00069f13_fill_pattern_1_6: 2490000 rects
+caravel_00069f13_fill_pattern_0_4: 2930000 rects
+caravel_00069f13_fill_pattern_1_5: 2800000 rects
+caravel_00069f13_fill_pattern_2_6: 3020000 rects
+caravel_00069f13_fill_pattern_3_0: 2760000 rects
+caravel_00069f13_fill_pattern_3_3: 2800000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_00069f13_fill_pattern_2_1: 2580000 rects
+caravel_00069f13_fill_pattern_3_1: 2530000 rects
+caravel_00069f13_fill_pattern_4_5: 760000 rects
+caravel_00069f13_fill_pattern_2_6: 3030000 rects
+caravel_00069f13_fill_pattern_2_2: 2680000 rects
+caravel_00069f13_fill_pattern_2_4: 2980000 rects
+caravel_00069f13_fill_pattern_1_2: 3050000 rects
+caravel_00069f13_fill_pattern_4_0: 2110000 rects
+caravel_00069f13_fill_pattern_4_3: 2370000 rects
+caravel_00069f13_fill_pattern_1_3: 2990000 rects
+caravel_00069f13_fill_pattern_2_5: 2890000 rects
+caravel_00069f13_fill_pattern_0_2: 2710000 rects
+caravel_00069f13_fill_pattern_4_5: 770000 rects
+caravel_00069f13_fill_pattern_2_6: 3040000 rects
+caravel_00069f13_fill_pattern_2_2: 2690000 rects
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_00069f13_fill_pattern_0_0: 2490000 rects
+caravel_00069f13_fill_pattern_3_0: 2770000 rects
+caravel_00069f13_fill_pattern_0_3: 2160000 rects
+caravel_00069f13_fill_pattern_1_2: 3060000 rects
+caravel_00069f13_fill_pattern_1_6: 2500000 rects
+caravel_00069f13_fill_pattern_3_4: 3060000 rects
+caravel_00069f13_fill_pattern_0_6: 2580000 rects
+caravel_00069f13_fill_pattern_2_4: 2990000 rects
+caravel_00069f13_fill_pattern_1_5: 2810000 rects
+caravel_00069f13_fill_pattern_3_5: 2120000 rects
+caravel_00069f13_fill_pattern_2_6: 3050000 rects
+caravel_00069f13_fill_pattern_4_4: 2640000 rects
+caravel_00069f13_fill_pattern_0_4: 2940000 rects
+caravel_00069f13_fill_pattern_4_3: 2380000 rects
+caravel_00069f13_fill_pattern_3_3: 2810000 rects
+Processing system .magicrc file
+caravel_00069f13_fill_pattern_2_0: 2570000 rects
+caravel_00069f13_fill_pattern_4_0: 2120000 rects
+caravel_00069f13_fill_pattern_2_2: 2700000 rects
+caravel_00069f13_fill_pattern_1_3: 3000000 rects
+caravel_00069f13_fill_pattern_1_2: 3070000 rects
+caravel_00069f13_fill_pattern_2_6: 3060000 rects
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_00069f13_fill_pattern_4_5: 780000 rects
+caravel_00069f13_fill_pattern_2_4: 3000000 rects
+caravel_00069f13_fill_pattern_3_0: 2780000 rects
+caravel_00069f13_fill_pattern_3_1: 2540000 rects
+caravel_00069f13_fill_pattern_0_2: 2720000 rects
+caravel_00069f13_fill_pattern_2_6: 3070000 rects
+caravel_00069f13_fill_pattern_1_2: 3080000 rects
+caravel_00069f13_fill_pattern_4_3: 2390000 rects
+caravel_00069f13_fill_pattern_2_2: 2710000 rects
+caravel_00069f13_fill_pattern_1_6: 2510000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_00069f13_fill_pattern_0_3: 2170000 rects
+caravel_00069f13_fill_pattern_2_5: 2900000 rects
+caravel_00069f13_fill_pattern_1_5: 2820000 rects
+caravel_00069f13_fill_pattern_2_6: 3080000 rects
+caravel_00069f13_fill_pattern_2_4: 3010000 rects
+caravel_00069f13_fill_pattern_0_4: 2950000 rects
+caravel_00069f13_fill_pattern_0_0: 2500000 rects
+caravel_00069f13_fill_pattern_3_5: 2130000 rects
+caravel_00069f13_fill_pattern_4_0: 2130000 rects
+caravel_00069f13_fill_pattern_4_4: 2650000 rects
+caravel_00069f13_fill_pattern_1_3: 3010000 rects
+caravel_00069f13_fill_pattern_1_2: 3090000 rects
+caravel_00069f13_fill_pattern_4_5: 790000 rects
+caravel_00069f13_fill_pattern_3_3: 2820000 rects
+caravel_00069f13_fill_pattern_0_6: 2590000 rects
+caravel_00069f13_fill_pattern_1_1: 2770000 rects
+caravel_00069f13_fill_pattern_3_0: 2790000 rects
+caravel_00069f13_fill_pattern_3_4: 3070000 rects
+caravel_00069f13_fill_pattern_2_6: 3090000 rects
+caravel_00069f13_fill_pattern_2_2: 2720000 rects
+caravel_00069f13_fill_pattern_4_3: 2400000 rects
+caravel_00069f13_fill_pattern_2_1: 2590000 rects
+caravel_00069f13_fill_pattern_0_2: 2730000 rects
+caravel_00069f13_fill_pattern_2_4: 3020000 rects
+caravel_00069f13_fill_pattern_1_2: 3100000 rects
+caravel_00069f13_fill_pattern_2_6: 3100000 rects
+caravel_00069f13_fill_pattern_1_6: 2520000 rects
+caravel_00069f13_fill_pattern_2_2: 2730000 rects
+caravel_00069f13_fill_pattern_4_0: 2140000 rects
+caravel_00069f13_fill_pattern_1_5: 2830000 rects
+caravel_00069f13_fill_pattern_2_6: 3110000 rects
+caravel_00069f13_fill_pattern_1_3: 3020000 rects
+caravel_00069f13_fill_pattern_1_2: 3110000 rects
+caravel_00069f13_fill_pattern_4_3: 2410000 rects
+caravel_00069f13_fill_pattern_2_4: 3030000 rects
+caravel_00069f13_fill_pattern_3_0: 2800000 rects
+caravel_00069f13_fill_pattern_4_4: 2660000 rects
+caravel_00069f13_fill_pattern_3_1: 2550000 rects
+caravel_00069f13_fill_pattern_0_2: 2740000 rects
+caravel_00069f13_fill_pattern_0_4: 2960000 rects
+caravel_00069f13_fill_pattern_3_5: 2140000 rects
+caravel_00069f13_fill_pattern_3_3: 2830000 rects
+caravel_00069f13_fill_pattern_0_3: 2180000 rects
+caravel_00069f13_fill_pattern_3_4: 3080000 rects
+caravel_00069f13_fill_pattern_0_6: 2600000 rects
+caravel_00069f13_fill_pattern_4_5: 800000 rects
+caravel_00069f13_fill_pattern_2_6: 3120000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+caravel_00069f13_fill_pattern_0_0: 2510000 rects
+caravel_00069f13_fill_pattern_2_2: 2740000 rects
+caravel_00069f13_fill_pattern_2_5: 2910000 rects
+caravel_00069f13_fill_pattern_1_2: 3120000 rects
+caravel_00069f13_fill_pattern_2_0: 2580000 rects
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+caravel_00069f13_fill_pattern_2_4: 3040000 rects
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_00069f13_fill_pattern_4_3: 2420000 rects
+caravel_00069f13_fill_pattern_1_1: 2780000 rects
+caravel_00069f13_fill_pattern_1_6: 2530000 rects
+caravel_00069f13_fill_pattern_3_0: 2810000 rects
+caravel_00069f13_fill_pattern_0_2: 2750000 rects
+Scaled magic input cell caravel_00069f13_fill_pattern_3_6 geometry by factor of 2
+caravel_00069f13_fill_pattern_1_2: 3130000 rects
+caravel_00069f13_fill_pattern_1_5: 2840000 rects
+caravel_00069f13_fill_pattern_4_0: 2150000 rects
+caravel_00069f13_fill_pattern_2_2: 2750000 rects
+caravel_00069f13_fill_pattern_0_4: 2970000 rects
+caravel_00069f13_fill_pattern_1_3: 3030000 rects
+caravel_00069f13_fill_pattern_2_4: 3050000 rects
+caravel_00069f13_fill_pattern_4_5: 810000 rects
+caravel_00069f13_fill_pattern_3_5: 2150000 rects
+caravel_00069f13_fill_pattern_3_3: 2840000 rects
+caravel_00069f13_fill_pattern_4_3: 2430000 rects
+caravel_00069f13_fill_pattern_3_4: 3090000 rects
+caravel_00069f13_fill_pattern_0_6: 2610000 rects
+caravel_00069f13_fill_pattern_1_2: 3140000 rects
+caravel_00069f13_fill_pattern_3_0: 2820000 rects
+caravel_00069f13_fill_pattern_4_5: 820000 rects
+caravel_00069f13_fill_pattern_4_4: 2670000 rects
+caravel_00069f13_fill_pattern_0_2: 2760000 rects
+caravel_00069f13_fill_pattern_4_0: 2160000 rects
+caravel_00069f13_fill_pattern_2_2: 2760000 rects
+caravel_00069f13_fill_pattern_2_4: 3060000 rects
+caravel_00069f13_fill_pattern_1_6: 2540000 rects
+caravel_00069f13_fill_pattern_2_1: 2600000 rects
+caravel_00069f13_fill_pattern_3_1: 2560000 rects
+caravel_00069f13_fill_pattern_0_0: 2520000 rects
+caravel_00069f13_fill_pattern_2_6: 3130000 rects
+caravel_00069f13_fill_pattern_0_3: 2190000 rects
+caravel_00069f13_fill_pattern_4_3: 2440000 rects
+caravel_00069f13_fill_pattern_1_3: 3040000 rects
+caravel_00069f13_fill_pattern_1_5: 2850000 rects
+caravel_00069f13_fill_pattern_1_2: 3150000 rects
+caravel_00069f13_fill_pattern_0_4: 2980000 rects
+caravel_00069f13_fill_pattern_4_5: 830000 rects
+caravel_00069f13_fill_pattern_1_1: 2790000 rects
+caravel_00069f13_fill_pattern_4_0: 2170000 rects
+caravel_00069f13_fill_pattern_2_5: 2920000 rects
+caravel_00069f13_fill_pattern_2_2: 2770000 rects
+caravel_00069f13_fill_pattern_2_4: 3070000 rects
+caravel_00069f13_fill_pattern_3_5: 2160000 rects
+caravel_00069f13_fill_pattern_2_0: 2590000 rects
+caravel_00069f13_fill_pattern_3_4: 3100000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+caravel_00069f13_fill_pattern_3_3: 2850000 rects
+caravel_00069f13_fill_pattern_3_0: 2830000 rects
+caravel_00069f13_fill_pattern_1_2: 3160000 rects
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+caravel_00069f13_fill_pattern_4_3: 2450000 rects
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_00069f13_fill_pattern_1_6: 2550000 rects
+caravel_00069f13_fill_pattern_4_0: 2180000 rects
+caravel_00069f13_fill_pattern_2_4: 3080000 rects
+caravel_00069f13_fill_pattern_2_2: 2780000 rects
+caravel_00069f13_fill_pattern_4_5: 840000 rects
+caravel_00069f13_fill_pattern_1_3: 3050000 rects
+caravel_00069f13_fill_pattern_1_5: 2860000 rects
+caravel_00069f13_fill_pattern_1_2: 3170000 rects
+caravel_00069f13_fill_pattern_3_0: 2840000 rects
+caravel_00069f13_fill_pattern_0_6: 2620000 rects
+caravel_00069f13_fill_pattern_2_1: 2610000 rects
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+CIF output style is now "wafflefill(tiled)"
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+ Generating output for cell caravel_00069f13_fill_pattern_3_6
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+caravel_00069f13_fill_pattern_4_0: 2390000 rects
+caravel_00069f13_fill_pattern_3_5: 2360000 rects
+caravel_00069f13_fill_pattern_0_3: 2360000 rects
+caravel_00069f13_fill_pattern_5_4: 280000 rects
+caravel_00069f13_fill_pattern_4_5: 1100000 rects
+caravel_00069f13_fill_pattern_1_6: 2670000 rects
+caravel_00069f13_fill_pattern_3_0: 3000000 rects
+caravel_00069f13_fill_pattern_2_2: 2870000 rects
+caravel_00069f13_fill_pattern_1_3: 3320000 rects
+caravel_00069f13_fill_pattern_1_2: 3410000 rects
+caravel_00069f13_fill_pattern_4_0: 2400000 rects
+caravel_00069f13_fill_pattern_3_1: 2640000 rects
+caravel_00069f13_fill_pattern_2_4: 3310000 rects
+caravel_00069f13_fill_pattern_3_4: 3230000 rects
+caravel_00069f13_fill_pattern_5_4: 290000 rects
+caravel_00069f13_fill_pattern_2_0: 2660000 rects
+caravel_00069f13_fill_pattern_0_2: 2830000 rects
+caravel_00069f13_fill_pattern_2_1: 2700000 rects
+caravel_00069f13_fill_pattern_3_5: 2370000 rects
+caravel_00069f13_fill_pattern_4_5: 1110000 rects
+caravel_00069f13_fill_pattern_4_3: 2610000 rects
+caravel_00069f13_fill_pattern_4_0: 2410000 rects
+caravel_00069f13_fill_pattern_4_4: 2810000 rects
+caravel_00069f13_fill_pattern_1_3: 3330000 rects
+caravel_00069f13_fill_pattern_2_5: 3010000 rects
+caravel_00069f13_fill_pattern_0_2: 2840000 rects
+caravel_00069f13_fill_pattern_3_0: 3010000 rects
+caravel_00069f13_fill_pattern_0_6: 2720000 rects
+caravel_00069f13_fill_pattern_2_4: 3320000 rects
+caravel_00069f13_fill_pattern_5_4: 300000 rects
+caravel_00069f13_fill_pattern_2_6: 3220000 rects
+caravel_00069f13_fill_pattern_4_0: 2420000 rects
+caravel_00069f13_fill_pattern_0_3: 2370000 rects
+caravel_00069f13_fill_pattern_1_5: 2990000 rects
+caravel_00069f13_fill_pattern_4_5: 1120000 rects
+caravel_00069f13_fill_pattern_3_3: 2980000 rects
+caravel_00069f13_fill_pattern_0_2: 2850000 rects
+caravel_00069f13_fill_pattern_0_0: 2620000 rects
+caravel_00069f13_fill_pattern_3_5: 2380000 rects
+caravel_00069f13_fill_pattern_3_0: 3020000 rects
+caravel_00069f13_fill_pattern_1_3: 3340000 rects
+caravel_00069f13_fill_pattern_4_3: 2620000 rects
+caravel_00069f13_fill_pattern_1_1: 2880000 rects
+caravel_00069f13_fill_pattern_1_6: 2680000 rects
+caravel_00069f13_fill_pattern_0_2: 2860000 rects
+caravel_00069f13_fill_pattern_4_5: 1130000 rects
+caravel_00069f13_fill_pattern_2_4: 3330000 rects
+caravel_00069f13_fill_pattern_5_4: 310000 rects
+caravel_00069f13_fill_pattern_4_4: 2820000 rects
+caravel_00069f13_fill_pattern_1_3: 3350000 rects
+caravel_00069f13_fill_pattern_0_2: 2870000 rects
+caravel_00069f13_fill_pattern_4_3: 2630000 rects
+caravel_00069f13_fill_pattern_3_5: 2390000 rects
+caravel_00069f13_fill_pattern_3_1: 2650000 rects
+caravel_00069f13_fill_pattern_3_4: 3240000 rects
+caravel_00069f13_fill_pattern_4_5: 1140000 rects
+caravel_00069f13_fill_pattern_0_2: 2880000 rects
+caravel_00069f13_fill_pattern_3_0: 3030000 rects
+caravel_00069f13_fill_pattern_0_6: 2730000 rects
+caravel_00069f13_fill_pattern_2_4: 3340000 rects
+caravel_00069f13_fill_pattern_3_3: 2990000 rects
+caravel_00069f13_fill_pattern_1_3: 3360000 rects
+caravel_00069f13_fill_pattern_2_0: 2670000 rects
+caravel_00069f13_fill_pattern_1_5: 3000000 rects
+caravel_00069f13_fill_pattern_0_2: 2890000 rects
+Ended: 11/15/2022 21:23:42
+caravel_00069f13_fill_pattern_5_4: 320000 rects
+caravel_00069f13_fill_pattern_0_4: 3080000 rects
+caravel_00069f13_fill_pattern_2_5: 3020000 rects
+caravel_00069f13_fill_pattern_4_5: 1150000 rects
+caravel_00069f13_fill_pattern_3_0: 3040000 rects
+caravel_00069f13_fill_pattern_1_6: 2690000 rects
+caravel_00069f13_fill_pattern_2_2: 2880000 rects
+caravel_00069f13_fill_pattern_4_3: 2640000 rects
+caravel_00069f13_fill_pattern_3_5: 2400000 rects
+caravel_00069f13_fill_pattern_0_3: 2380000 rects
+caravel_00069f13_fill_pattern_0_0: 2630000 rects
+caravel_00069f13_fill_pattern_1_3: 3370000 rects
+caravel_00069f13_fill_pattern_2_4: 3350000 rects
+caravel_00069f13_fill_pattern_2_6: 3230000 rects
+caravel_00069f13_fill_pattern_4_4: 2830000 rects
+caravel_00069f13_fill_pattern_0_2: 2900000 rects
+caravel_00069f13_fill_pattern_3_0: 3050000 rects
+caravel_00069f13_fill_pattern_4_5: 1160000 rects
+caravel_00069f13_fill_pattern_3_4: 3250000 rects
+caravel_00069f13_fill_pattern_4_3: 2650000 rects
+caravel_00069f13_fill_pattern_1_3: 3380000 rects
+caravel_00069f13_fill_pattern_1_1: 2890000 rects
+caravel_00069f13_fill_pattern_5_4: 330000 rects
+caravel_00069f13_fill_pattern_3_5: 2410000 rects
+caravel_00069f13_fill_pattern_0_6: 2740000 rects
+caravel_00069f13_fill_pattern_2_4: 3360000 rects
+caravel_00069f13_fill_pattern_3_3: 3000000 rects
+caravel_00069f13_fill_pattern_1_5: 3010000 rects
+caravel_00069f13_fill_pattern_2_1: 2710000 rects
+caravel_00069f13_fill_pattern_3_0: 3060000 rects
+caravel_00069f13_fill_pattern_4_5: 1170000 rects
+caravel_00069f13_fill_pattern_1_3: 3390000 rects
+caravel_00069f13_fill_pattern_0_2: 2910000 rects
+caravel_00069f13_fill_pattern_4_3: 2660000 rects
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_00069f13_fill_pattern_3_1: 2660000 rects
+caravel_00069f13_fill_pattern_1_6: 2700000 rects
+caravel_00069f13_fill_pattern_0_4: 3090000 rects
+caravel_00069f13_fill_pattern_0_3: 2390000 rects
+caravel_00069f13_fill_pattern_3_5: 2420000 rects
+caravel_00069f13_fill_pattern_2_4: 3370000 rects
+caravel_00069f13_fill_pattern_3_0: 3070000 rects
+caravel_00069f13_fill_pattern_4_5: 1180000 rects
+caravel_00069f13_fill_pattern_5_4: 340000 rects
+caravel_00069f13_fill_pattern_2_0: 2680000 rects
+caravel_00069f13_fill_pattern_0_0: 2640000 rects
+caravel_00069f13_fill_pattern_4_4: 2840000 rects
+caravel_00069f13_fill_pattern_1_3: 3400000 rects
+caravel_00069f13_fill_pattern_0_3: 2400000 rects
+caravel_00069f13_fill_pattern_4_3: 2670000 rects
+caravel_00069f13_fill_pattern_2_5: 3030000 rects
+caravel_00069f13_fill_pattern_3_4: 3260000 rects
+caravel_00069f13_fill_pattern_4_5: 1190000 rects
+caravel_00069f13_fill_pattern_3_0: 3080000 rects
+caravel_00069f13_fill_pattern_2_2: 2890000 rects
+caravel_00069f13_fill_pattern_1_5: 3020000 rects
+caravel_00069f13_fill_pattern_0_3: 2410000 rects
+caravel_00069f13_fill_pattern_0_6: 2750000 rects
+caravel_00069f13_fill_pattern_2_4: 3380000 rects
+caravel_00069f13_fill_pattern_0_2: 2920000 rects
+caravel_00069f13_fill_pattern_3_5: 2430000 rects
+caravel_00069f13_fill_pattern_1_3: 3410000 rects
+Processing system .magicrc file
+caravel_00069f13_fill_pattern_1_1: 2900000 rects
+caravel_00069f13_fill_pattern_4_5: 1200000 rects
+caravel_00069f13_fill_pattern_3_0: 3090000 rects
+caravel_00069f13_fill_pattern_4_3: 2680000 rects
+caravel_00069f13_fill_pattern_5_4: 350000 rects
+caravel_00069f13_fill_pattern_2_6: 3240000 rects
+caravel_00069f13_fill_pattern_1_2: 3420000 rects
+caravel_00069f13_fill_pattern_1_6: 2710000 rects
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_00069f13_fill_pattern_0_4: 3100000 rects
+caravel_00069f13_fill_pattern_1_3: 3420000 rects
+caravel_00069f13_fill_pattern_2_4: 3390000 rects
+caravel_00069f13_fill_pattern_0_2: 2930000 rects
+caravel_00069f13_fill_pattern_3_0: 3100000 rects
+caravel_00069f13_fill_pattern_4_5: 1210000 rects
+caravel_00069f13_fill_pattern_2_1: 2720000 rects
+caravel_00069f13_fill_pattern_3_5: 2440000 rects
+caravel_00069f13_fill_pattern_0_3: 2420000 rects
+caravel_00069f13_fill_pattern_3_1: 2670000 rects
+caravel_00069f13_fill_pattern_3_4: 3270000 rects
+caravel_00069f13_fill_pattern_4_3: 2690000 rects
+caravel_00069f13_fill_pattern_4_4: 2850000 rects
+caravel_00069f13_fill_pattern_1_3: 3430000 rects
+caravel_00069f13_fill_pattern_3_3: 3010000 rects
+caravel_00069f13_fill_pattern_5_4: 360000 rects
+caravel_00069f13_fill_pattern_0_0: 2650000 rects
+caravel_00069f13_fill_pattern_1_5: 3030000 rects
+caravel_00069f13_fill_pattern_3_0: 3110000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_00069f13_fill_pattern_2_4: 3400000 rects
+caravel_00069f13_fill_pattern_4_3: 2700000 rects
+caravel_00069f13_fill_pattern_2_0: 2690000 rects
+caravel_00069f13_fill_pattern_0_6: 2760000 rects
+caravel_00069f13_fill_pattern_4_5: 1220000 rects
+caravel_00069f13_fill_pattern_4_0: 2430000 rects
+caravel_00069f13_fill_pattern_3_5: 2450000 rects
+caravel_00069f13_fill_pattern_1_3: 3440000 rects
+caravel_00069f13_fill_pattern_1_6: 2720000 rects
+caravel_00069f13_fill_pattern_4_3: 2710000 rects
+caravel_00069f13_fill_pattern_2_5: 3040000 rects
+caravel_00069f13_fill_pattern_0_2: 2940000 rects
+caravel_00069f13_fill_pattern_3_0: 3120000 rects
+caravel_00069f13_fill_pattern_0_4: 3110000 rects
+caravel_00069f13_fill_pattern_2_4: 3410000 rects
+caravel_00069f13_fill_pattern_4_5: 1230000 rects
+caravel_00069f13_fill_pattern_4_3: 2720000 rects
+caravel_00069f13_fill_pattern_5_4: 370000 rects
+caravel_00069f13_fill_pattern_2_2: 2900000 rects
+caravel_00069f13_fill_pattern_1_3: 3450000 rects
+caravel_00069f13_fill_pattern_3_4: 3280000 rects
+caravel_00069f13_fill_pattern_1_1: 2910000 rects
+caravel_00069f13_fill_pattern_3_0: 3130000 rects
+caravel_00069f13_fill_pattern_3_5: 2460000 rects
+caravel_00069f13_fill_pattern_4_3: 2730000 rects
+caravel_00069f13_fill_pattern_4_4: 2860000 rects
+caravel_00069f13_fill_pattern_1_5: 3040000 rects
+caravel_00069f13_fill_pattern_4_5: 1240000 rects
+caravel_00069f13_fill_pattern_0_2: 2950000 rects
+caravel_00069f13_fill_pattern_2_4: 3420000 rects
+caravel_00069f13_fill_pattern_2_6: 3250000 rects
+caravel_00069f13_fill_pattern_3_0: 3140000 rects
+caravel_00069f13_fill_pattern_1_3: 3460000 rects
+caravel_00069f13_fill_pattern_4_3: 2740000 rects
+caravel_00069f13_fill_pattern_0_6: 2770000 rects
+caravel_00069f13_fill_pattern_3_1: 2680000 rects
+caravel_00069f13_fill_pattern_5_4: 380000 rects
+caravel_00069f13_fill_pattern_0_3: 2430000 rects
+caravel_00069f13_fill_pattern_1_6: 2730000 rects
+caravel_00069f13_fill_pattern_4_5: 1250000 rects
+caravel_00069f13_fill_pattern_3_5: 2470000 rects
+caravel_00069f13_fill_pattern_4_3: 2750000 rects
+caravel_00069f13_fill_pattern_2_1: 2730000 rects
+caravel_00069f13_fill_pattern_2_4: 3430000 rects
+caravel_00069f13_fill_pattern_1_3: 3470000 rects
+caravel_00069f13_fill_pattern_3_0: 3150000 rects
+caravel_00069f13_fill_pattern_0_0: 2660000 rects
+caravel_00069f13_fill_pattern_0_4: 3120000 rects
+caravel_00069f13_fill_pattern_0_2: 2960000 rects
+caravel_00069f13_fill_pattern_3_4: 3290000 rects
+caravel_00069f13_fill_pattern_4_3: 2760000 rects
+caravel_00069f13_fill_pattern_2_5: 3050000 rects
+caravel_00069f13_fill_pattern_1_5: 3050000 rects
+caravel_00069f13_fill_pattern_3_3: 3020000 rects
+caravel_00069f13_fill_pattern_2_0: 2700000 rects
+caravel_00069f13_fill_pattern_4_5: 1260000 rects
+caravel_00069f13_fill_pattern_5_4: 390000 rects
+caravel_00069f13_fill_pattern_1_3: 3480000 rects
+caravel_00069f13_fill_pattern_3_0: 3160000 rects
+caravel_00069f13_fill_pattern_3_5: 2480000 rects
+caravel_00069f13_fill_pattern_4_3: 2770000 rects
+caravel_00069f13_fill_pattern_2_4: 3440000 rects
+caravel_00069f13_fill_pattern_1_1: 2920000 rects
+caravel_00069f13_fill_pattern_4_4: 2870000 rects
+caravel_00069f13_fill_pattern_1_3: 3490000 rects
+caravel_00069f13_fill_pattern_4_3: 2780000 rects
+caravel_00069f13_fill_pattern_0_6: 2780000 rects
+caravel_00069f13_fill_pattern_0_2: 2970000 rects
+caravel_00069f13_fill_pattern_1_6: 2740000 rects
+caravel_00069f13_fill_pattern_3_0: 3170000 rects
+caravel_00069f13_fill_pattern_2_2: 2910000 rects
+caravel_00069f13_fill_pattern_2_6: 3260000 rects
+caravel_00069f13_fill_pattern_5_4: 400000 rects
+caravel_00069f13_fill_pattern_4_3: 2790000 rects
+caravel_00069f13_fill_pattern_3_4: 3300000 rects
+caravel_00069f13_fill_pattern_2_4: 3450000 rects
+caravel_00069f13_fill_pattern_3_5: 2490000 rects
+caravel_00069f13_fill_pattern_1_3: 3500000 rects
+caravel_00069f13_fill_pattern_0_4: 3130000 rects
+caravel_00069f13_fill_pattern_0_0: 2670000 rects
+caravel_00069f13_fill_pattern_3_0: 3180000 rects
+caravel_00069f13_fill_pattern_1_5: 3060000 rects
+caravel_00069f13_fill_pattern_4_3: 2800000 rects
+caravel_00069f13_fill_pattern_0_2: 2980000 rects
+caravel_00069f13_fill_pattern_4_0: 2440000 rects
+caravel_00069f13_fill_pattern_3_3: 3030000 rects
+caravel_00069f13_fill_pattern_1_2: 3430000 rects
+caravel_00069f13_fill_pattern_2_4: 3460000 rects
+caravel_00069f13_fill_pattern_1_3: 3510000 rects
+caravel_00069f13_fill_pattern_3_0: 3190000 rects
+caravel_00069f13_fill_pattern_5_4: 410000 rects
+caravel_00069f13_fill_pattern_4_4: 2880000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+caravel_00069f13_fill_pattern_2_5: 3060000 rects
+caravel_00069f13_fill_pattern_2_1: 2740000 rects
+caravel_00069f13_fill_pattern_1_6: 2750000 rects
+caravel_00069f13_fill_pattern_0_2: 2990000 rects
+caravel_00069f13_fill_pattern_3_1: 2690000 rects
+caravel_00069f13_fill_pattern_4_5: 1270000 rects
+Scaled tech values by 2 / 1 to match internal grid scaling
+caravel_00069f13_fill_pattern_4_3: 2810000 rects
+Loading sky130A Device Generator Menu ...
+caravel_00069f13_fill_pattern_3_5: 2500000 rects
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_00069f13_fill_pattern_0_6: 2790000 rects
+caravel_00069f13_fill_pattern_3_4: 3310000 rects
+caravel_00069f13_fill_pattern_1_1: 2930000 rects
+caravel_00069f13_fill_pattern_2_0: 2710000 rects
+caravel_00069f13_fill_pattern_1_3: 3520000 rects
+caravel_00069f13_fill_pattern_3_0: 3200000 rects
+caravel_00069f13_fill_pattern_0_2: 3000000 rects
+caravel_00069f13_fill_pattern_2_4: 3470000 rects
+caravel_00069f13_fill_pattern_0_4: 3140000 rects
+caravel_00069f13_fill_pattern_1_5: 3070000 rects
+caravel_00069f13_fill_pattern_0_2: 3010000 rects
+caravel_00069f13_fill_pattern_5_4: 420000 rects
+caravel_00069f13_fill_pattern_1_3: 3530000 rects
+caravel_00069f13_fill_pattern_2_6: 3270000 rects
+caravel_00069f13_fill_pattern_3_0: 3210000 rects
+caravel_00069f13_fill_pattern_0_0: 2680000 rects
+caravel_00069f13_fill_pattern_3_5: 2510000 rects
+caravel_00069f13_fill_pattern_4_5: 1280000 rects
+caravel_00069f13_fill_pattern_0_2: 3020000 rects
+caravel_00069f13_fill_pattern_2_4: 3480000 rects
+caravel_00069f13_fill_pattern_4_4: 2890000 rects
+caravel_00069f13_fill_pattern_0_1: 10000 rects
+caravel_00069f13_fill_pattern_1_6: 2760000 rects
+caravel_00069f13_fill_pattern_1_3: 3540000 rects
+caravel_00069f13_fill_pattern_3_0: 3220000 rects
+caravel_00069f13_fill_pattern_3_4: 3320000 rects
+caravel_00069f13_fill_pattern_3_3: 3040000 rects
+caravel_00069f13_fill_pattern_0_6: 2800000 rects
+caravel_00069f13_fill_pattern_4_3: 2820000 rects
+caravel_00069f13_fill_pattern_2_2: 2920000 rects
+caravel_00069f13_fill_pattern_5_4: 430000 rects
+caravel_00069f13_fill_pattern_1_5: 3080000 rects
+caravel_00069f13_fill_pattern_2_4: 3490000 rects
+caravel_00069f13_fill_pattern_1_3: 3550000 rects
+caravel_00069f13_fill_pattern_2_5: 3070000 rects
+caravel_00069f13_fill_pattern_0_2: 3030000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00069f13_fill_pattern_3_5: 2520000 rects
+caravel_00069f13_fill_pattern_0_4: 3150000 rects
+caravel_00069f13_fill_pattern_3_0: 3230000 rects
+caravel_00069f13_fill_pattern_0_1: 20000 rects
+caravel_00069f13_fill_pattern_1_1: 2940000 rects
+caravel_00069f13_fill_pattern_2_1: 2750000 rects
+caravel_00069f13_fill_pattern_4_5: 1290000 rects
+ Generating output for cell caravel_00069f13_fill_pattern_0_3
+caravel_00069f13_fill_pattern_1_3: 3560000 rects
+caravel_00069f13_fill_pattern_0_1: 30000 rects
+caravel_00069f13_fill_pattern_2_4: 3500000 rects
+caravel_00069f13_fill_pattern_0_0: 2690000 rects
+caravel_00069f13_fill_pattern_5_4: 440000 rects
+caravel_00069f13_fill_pattern_3_0: 3240000 rects
+caravel_00069f13_fill_pattern_1_6: 2770000 rects
+caravel_00069f13_fill_pattern_4_4: 2900000 rects
+caravel_00069f13_fill_pattern_0_6: 2810000 rects
+caravel_00069f13_fill_pattern_2_0: 2720000 rects
+caravel_00069f13_fill_pattern_2_6: 3280000 rects
+caravel_00069f13_fill_pattern_3_5: 2530000 rects
+caravel_00069f13_fill_pattern_1_3: 3570000 rects
+caravel_00069f13_fill_pattern_0_1: 40000 rects
+caravel_00069f13_fill_pattern_1_5: 3090000 rects
+caravel_00069f13_fill_pattern_0_2: 3040000 rects
+caravel_00069f13_fill_pattern_3_3: 3050000 rects
+caravel_00069f13_fill_pattern_3_1: 2700000 rects
+caravel_00069f13_fill_pattern_2_4: 3510000 rects
+caravel_00069f13_fill_pattern_5_4: 450000 rects
+caravel_00069f13_fill_pattern_0_1: 50000 rects
+caravel_00069f13_fill_pattern_3_4: 3330000 rects
+caravel_00069f13_fill_pattern_0_4: 3160000 rects
+caravel_00069f13_fill_pattern_1_3: 3580000 rects
+caravel_00069f13_fill_pattern_4_0: 2450000 rects
+caravel_00069f13_fill_pattern_0_6: 2820000 rects
+caravel_00069f13_fill_pattern_4_5: 1300000 rects
+caravel_00069f13_fill_pattern_4_3: 2830000 rects
+caravel_00069f13_fill_pattern_0_1: 60000 rects
+caravel_00069f13_fill_pattern_3_5: 2540000 rects
+caravel_00069f13_fill_pattern_1_6: 2780000 rects
+caravel_00069f13_fill_pattern_2_5: 3080000 rects
+caravel_00069f13_fill_pattern_2_4: 3520000 rects
+caravel_00069f13_fill_pattern_1_3: 3590000 rects
+caravel_00069f13_fill_pattern_4_4: 2910000 rects
+caravel_00069f13_fill_pattern_0_1: 70000 rects
+caravel_00069f13_fill_pattern_2_2: 2930000 rects
+caravel_00069f13_fill_pattern_0_0: 2700000 rects
+caravel_00069f13_fill_pattern_5_4: 460000 rects
+caravel_00069f13_fill_pattern_1_5: 3100000 rects
+caravel_00069f13_fill_pattern_1_1: 2950000 rects
+caravel_00069f13_fill_pattern_0_2: 3050000 rects
+caravel_00069f13_fill_pattern_2_4: 3530000 rects
+caravel_00069f13_fill_pattern_2_1: 2760000 rects
+caravel_00069f13_fill_pattern_0_6: 2830000 rects
+caravel_00069f13_fill_pattern_1_3: 3600000 rects
+caravel_00069f13_fill_pattern_0_1: 80000 rects
+caravel_00069f13_fill_pattern_3_0: 3250000 rects
+caravel_00069f13_fill_pattern_0_4: 3170000 rects
+caravel_00069f13_fill_pattern_2_6: 3290000 rects
+caravel_00069f13_fill_pattern_2_4: 3540000 rects
+caravel_00069f13_fill_pattern_4_5: 1310000 rects
+caravel_00069f13_fill_pattern_1_2: 3440000 rects
+caravel_00069f13_fill_pattern_3_5: 2550000 rects
+caravel_00069f13_fill_pattern_3_3: 3060000 rects
+caravel_00069f13_fill_pattern_2_0: 2730000 rects
+caravel_00069f13_fill_pattern_0_1: 90000 rects
+caravel_00069f13_fill_pattern_1_3: 3610000 rects
+caravel_00069f13_fill_pattern_5_4: 470000 rects
+caravel_00069f13_fill_pattern_2_4: 3550000 rects
+caravel_00069f13_fill_pattern_1_6: 2790000 rects
+caravel_00069f13_fill_pattern_3_4: 3340000 rects
+caravel_00069f13_fill_pattern_4_4: 2920000 rects
+caravel_00069f13_fill_pattern_0_1: 100000 rects
+caravel_00069f13_fill_pattern_2_4: 3560000 rects
+caravel_00069f13_fill_pattern_1_5: 3110000 rects
+caravel_00069f13_fill_pattern_1_3: 3620000 rects
+caravel_00069f13_fill_pattern_0_6: 2840000 rects
+caravel_00069f13_fill_pattern_3_5: 2560000 rects
+caravel_00069f13_fill_pattern_0_0: 2710000 rects
+caravel_00069f13_fill_pattern_2_5: 3090000 rects
+caravel_00069f13_fill_pattern_4_5: 1320000 rects
+caravel_00069f13_fill_pattern_2_4: 3570000 rects
+caravel_00069f13_fill_pattern_5_4: 480000 rects
+caravel_00069f13_fill_pattern_4_3: 2840000 rects
+caravel_00069f13_fill_pattern_0_1: 110000 rects
+caravel_00069f13_fill_pattern_0_2: 3060000 rects
+caravel_00069f13_fill_pattern_0_4: 3180000 rects
+caravel_00069f13_fill_pattern_1_3: 3630000 rects
+caravel_00069f13_fill_pattern_0_1: 120000 rects
+caravel_00069f13_fill_pattern_2_4: 3580000 rects
+caravel_00069f13_fill_pattern_2_2: 2940000 rects
+caravel_00069f13_fill_pattern_1_6: 2800000 rects
+caravel_00069f13_fill_pattern_3_3: 3070000 rects
+caravel_00069f13_fill_pattern_3_0: 3260000 rects
+caravel_00069f13_fill_pattern_1_3: 3640000 rects
+caravel_00069f13_fill_pattern_3_5: 2570000 rects
+caravel_00069f13_fill_pattern_2_4: 3590000 rects
+caravel_00069f13_fill_pattern_0_1: 130000 rects
+caravel_00069f13_fill_pattern_4_4: 2930000 rects
+caravel_00069f13_fill_pattern_1_5: 3120000 rects
+caravel_00069f13_fill_pattern_3_1: 2710000 rects
+caravel_00069f13_fill_pattern_2_1: 2770000 rects
+caravel_00069f13_fill_pattern_1_1: 2960000 rects
+Ended: 11/15/2022 21:23:43
+caravel_00069f13_fill_pattern_5_4: 490000 rects
+caravel_00069f13_fill_pattern_2_6: 3300000 rects
+caravel_00069f13_fill_pattern_2_4: 3600000 rects
+caravel_00069f13_fill_pattern_3_4: 3350000 rects
+caravel_00069f13_fill_pattern_0_6: 2850000 rects
+caravel_00069f13_fill_pattern_1_3: 3650000 rects
+caravel_00069f13_fill_pattern_0_1: 140000 rects
+caravel_00069f13_fill_pattern_4_5: 1330000 rects
+caravel_00069f13_fill_pattern_2_0: 2740000 rects
+caravel_00069f13_fill_pattern_4_0: 2460000 rects
+caravel_00069f13_fill_pattern_0_0: 2720000 rects
+caravel_00069f13_fill_pattern_0_2: 3070000 rects
+caravel_00069f13_fill_pattern_0_4: 3190000 rects
+caravel_00069f13_fill_pattern_2_4: 3610000 rects
+caravel_00069f13_fill_pattern_1_6: 2810000 rects
+caravel_00069f13_fill_pattern_3_5: 2580000 rects
+caravel_00069f13_fill_pattern_0_1: 150000 rects
+caravel_00069f13_fill_pattern_1_3: 3660000 rects
+caravel_00069f13_fill_pattern_4_4: 2940000 rects
+caravel_00069f13_fill_pattern_0_2: 3080000 rects
+caravel_00069f13_fill_pattern_1_5: 3130000 rects
+caravel_00069f13_fill_pattern_5_4: 500000 rects
+caravel_00069f13_fill_pattern_2_4: 3620000 rects
+caravel_00069f13_fill_pattern_0_1: 160000 rects
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_00069f13_fill_pattern_0_2: 3090000 rects
+caravel_00069f13_fill_pattern_2_5: 3100000 rects
+caravel_00069f13_fill_pattern_1_3: 3670000 rects
+caravel_00069f13_fill_pattern_3_4: 3360000 rects
+caravel_00069f13_fill_pattern_4_3: 2850000 rects
+caravel_00069f13_fill_pattern_0_1: 170000 rects
+caravel_00069f13_fill_pattern_4_5: 1340000 rects
+caravel_00069f13_fill_pattern_3_3: 3080000 rects
+caravel_00069f13_fill_pattern_3_0: 3270000 rects
+caravel_00069f13_fill_pattern_0_2: 3100000 rects
+caravel_00069f13_fill_pattern_0_6: 2860000 rects
+caravel_00069f13_fill_pattern_3_5: 2590000 rects
+Processing system .magicrc file
+caravel_00069f13_fill_pattern_0_1: 180000 rects
+caravel_00069f13_fill_pattern_2_4: 3630000 rects
+caravel_00069f13_fill_pattern_1_6: 2820000 rects
+caravel_00069f13_fill_pattern_1_1: 2970000 rects
+caravel_00069f13_fill_pattern_0_4: 3200000 rects
+caravel_00069f13_fill_pattern_1_3: 3680000 rects
+caravel_00069f13_fill_pattern_5_4: 510000 rects
+caravel_00069f13_fill_pattern_2_6: 3310000 rects
+Sourcing design .magicrc for technology sky130A ...
+caravel_00069f13_fill_pattern_0_2: 3110000 rects
+2 Magic internal units = 1 Lambda
+caravel_00069f13_fill_pattern_1_5: 3140000 rects
+caravel_00069f13_fill_pattern_0_1: 190000 rects
+caravel_00069f13_fill_pattern_2_2: 2950000 rects
+caravel_00069f13_fill_pattern_4_4: 2950000 rects
+caravel_00069f13_fill_pattern_2_4: 3640000 rects
+caravel_00069f13_fill_pattern_0_2: 3120000 rects
+caravel_00069f13_fill_pattern_1_3: 3690000 rects
+caravel_00069f13_fill_pattern_2_0: 2750000 rects
+caravel_00069f13_fill_pattern_0_1: 200000 rects
+caravel_00069f13_fill_pattern_5_4: 520000 rects
+caravel_00069f13_fill_pattern_2_4: 3650000 rects
+caravel_00069f13_fill_pattern_3_5: 2600000 rects
+caravel_00069f13_fill_pattern_3_4: 3370000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_00069f13_fill_pattern_4_5: 1350000 rects
+caravel_00069f13_fill_pattern_1_3: 3700000 rects
+caravel_00069f13_fill_pattern_3_0: 3280000 rects
+caravel_00069f13_fill_pattern_2_4: 3660000 rects
+caravel_00069f13_fill_pattern_5_4: 530000 rects
+caravel_00069f13_fill_pattern_0_1: 210000 rects
+caravel_00069f13_fill_pattern_1_6: 2830000 rects
+caravel_00069f13_fill_pattern_4_0: 2470000 rects
+caravel_00069f13_fill_pattern_0_6: 2870000 rects
+caravel_00069f13_fill_pattern_0_4: 3210000 rects
+caravel_00069f13_fill_pattern_3_3: 3090000 rects
+caravel_00069f13_fill_pattern_0_0: 2730000 rects
+caravel_00069f13_fill_pattern_1_5: 3150000 rects
+caravel_00069f13_fill_pattern_2_1: 2780000 rects
+caravel_00069f13_fill_pattern_2_5: 3110000 rects
+caravel_00069f13_fill_pattern_1_1: 2980000 rects
+caravel_00069f13_fill_pattern_2_4: 3670000 rects
+caravel_00069f13_fill_pattern_3_1: 2720000 rects
+caravel_00069f13_fill_pattern_1_3: 3710000 rects
+caravel_00069f13_fill_pattern_0_1: 220000 rects
+caravel_00069f13_fill_pattern_5_4: 540000 rects
+caravel_00069f13_fill_pattern_4_4: 2960000 rects
+caravel_00069f13_fill_pattern_3_5: 2610000 rects
+caravel_00069f13_fill_pattern_4_3: 2860000 rects
+caravel_00069f13_fill_pattern_2_6: 3320000 rects
+caravel_00069f13_fill_pattern_3_4: 3380000 rects
+caravel_00069f13_fill_pattern_2_4: 3680000 rects
+caravel_00069f13_fill_pattern_5_4: 550000 rects
+caravel_00069f13_fill_pattern_1_3: 3720000 rects
+caravel_00069f13_fill_pattern_4_5: 1360000 rects
+caravel_00069f13_fill_pattern_4_0: 2480000 rects
+caravel_00069f13_fill_pattern_0_1: 230000 rects
+caravel_00069f13_fill_pattern_1_2: 3450000 rects
+caravel_00069f13_fill_pattern_1_6: 2840000 rects
+caravel_00069f13_fill_pattern_0_2: 3130000 rects
+caravel_00069f13_fill_pattern_1_5: 3160000 rects
+caravel_00069f13_fill_pattern_2_0: 2760000 rects
+caravel_00069f13_fill_pattern_3_5: 2620000 rects
+caravel_00069f13_fill_pattern_0_6: 2880000 rects
+caravel_00069f13_fill_pattern_5_4: 560000 rects
+caravel_00069f13_fill_pattern_1_3: 3730000 rects
+caravel_00069f13_fill_pattern_0_1: 240000 rects
+caravel_00069f13_fill_pattern_0_4: 3220000 rects
+caravel_00069f13_fill_pattern_1_1: 2990000 rects
+caravel_00069f13_fill_pattern_3_0: 3290000 rects
+caravel_00069f13_fill_pattern_3_3: 3100000 rects
+caravel_00069f13_fill_pattern_4_4: 2970000 rects
+caravel_00069f13_fill_pattern_2_2: 2960000 rects
+caravel_00069f13_fill_pattern_0_1: 250000 rects
+caravel_00069f13_fill_pattern_5_4: 570000 rects
+caravel_00069f13_fill_pattern_4_0: 2490000 rects
+caravel_00069f13_fill_pattern_1_3: 3740000 rects
+caravel_00069f13_fill_pattern_3_4: 3390000 rects
+caravel_00069f13_fill_pattern_2_5: 3120000 rects
+caravel_00069f13_fill_pattern_4_5: 1370000 rects
+caravel_00069f13_fill_pattern_5_4: 580000 rects
+caravel_00069f13_fill_pattern_3_5: 2630000 rects
+caravel_00069f13_fill_pattern_4_3: 2870000 rects
+caravel_00069f13_fill_pattern_0_1: 260000 rects
+caravel_00069f13_fill_pattern_2_6: 3330000 rects
+caravel_00069f13_fill_pattern_1_5: 3170000 rects
+caravel_00069f13_fill_pattern_1_6: 2850000 rects
+caravel_00069f13_fill_pattern_1_3: 3750000 rects
+caravel_00069f13_fill_pattern_4_0: 2500000 rects
+caravel_00069f13_fill_pattern_2_4: 3690000 rects
+caravel_00069f13_fill_pattern_0_6: 2890000 rects
+caravel_00069f13_fill_pattern_0_4: 3230000 rects
+caravel_00069f13_fill_pattern_0_0: 2740000 rects
+caravel_00069f13_fill_pattern_0_1: 270000 rects
+caravel_00069f13_fill_pattern_1_3: 3760000 rects
+caravel_00069f13_fill_pattern_4_4: 2980000 rects
+caravel_00069f13_fill_pattern_5_4: 590000 rects
+caravel_00069f13_fill_pattern_3_5: 2640000 rects
+caravel_00069f13_fill_pattern_4_0: 2510000 rects
+caravel_00069f13_fill_pattern_3_4: 3400000 rects
+caravel_00069f13_fill_pattern_0_1: 280000 rects
+caravel_00069f13_fill_pattern_1_1: 3000000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+caravel_00069f13_fill_pattern_4_5: 1380000 rects
+caravel_00069f13_fill_pattern_1_3: 3770000 rects
+caravel_00069f13_fill_pattern_3_3: 3110000 rects
+caravel_00069f13_fill_pattern_1_5: 3180000 rects
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+caravel_00069f13_fill_pattern_3_0: 3300000 rects
+caravel_00069f13_fill_pattern_2_0: 2770000 rects
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_00069f13_fill_pattern_1_6: 2860000 rects
+caravel_00069f13_fill_pattern_2_2: 2970000 rects
+caravel_00069f13_fill_pattern_0_1: 290000 rects
+caravel_00069f13_fill_pattern_5_4: 600000 rects
+caravel_00069f13_fill_pattern_2_1: 2790000 rects
+caravel_00069f13_fill_pattern_2_5: 3130000 rects
+caravel_00069f13_fill_pattern_4_0: 2520000 rects
+caravel_00069f13_fill_pattern_1_3: 3780000 rects
+caravel_00069f13_fill_pattern_0_1: 300000 rects
+caravel_00069f13_fill_pattern_3_5: 2650000 rects
+caravel_00069f13_fill_pattern_0_4: 3240000 rects
+caravel_00069f13_fill_pattern_0_6: 2900000 rects
+caravel_00069f13_fill_pattern_2_6: 3340000 rects
+caravel_00069f13_fill_pattern_4_4: 2990000 rects
+caravel_00069f13_fill_pattern_3_4: 3410000 rects
+caravel_00069f13_fill_pattern_0_1: 310000 rects
+caravel_00069f13_fill_pattern_5_4: 610000 rects
+caravel_00069f13_fill_pattern_2_4: 3700000 rects
+caravel_00069f13_fill_pattern_1_3: 3790000 rects
+caravel_00069f13_fill_pattern_3_1: 2730000 rects
+caravel_00069f13_fill_pattern_2_2: 2980000 rects
+caravel_00069f13_fill_pattern_4_5: 1390000 rects
+caravel_00069f13_fill_pattern_1_1: 3010000 rects
+caravel_00069f13_fill_pattern_1_6: 2870000 rects
+caravel_00069f13_fill_pattern_4_0: 2530000 rects
+caravel_00069f13_fill_pattern_0_1: 320000 rects
+caravel_00069f13_fill_pattern_0_0: 2750000 rects
+caravel_00069f13_fill_pattern_5_4: 620000 rects
+caravel_00069f13_fill_pattern_1_0: 10000 rects
+caravel_00069f13_fill_pattern_1_5: 3190000 rects
+caravel_00069f13_fill_pattern_3_5: 2660000 rects
+caravel_00069f13_fill_pattern_1_3: 3800000 rects
+caravel_00069f13_fill_pattern_3_3: 3120000 rects
+caravel_00069f13_fill_pattern_0_1: 330000 rects
+caravel_00069f13_fill_pattern_5_4: 630000 rects
+caravel_00069f13_fill_pattern_1_0: 20000 rects
+caravel_00069f13_fill_pattern_3_0: 3310000 rects
+caravel_00069f13_fill_pattern_0_4: 3250000 rects
+caravel_00069f13_fill_pattern_0_6: 2910000 rects
+caravel_00069f13_fill_pattern_2_0: 2780000 rects
+caravel_00069f13_fill_pattern_3_4: 3420000 rects
+caravel_00069f13_fill_pattern_4_0: 2540000 rects
+caravel_00069f13_fill_pattern_1_3: 3810000 rects
+caravel_00069f13_fill_pattern_4_5: 1400000 rects
+caravel_00069f13_fill_pattern_2_2: 2990000 rects
+caravel_00069f13_fill_pattern_4_4: 3000000 rects
+caravel_00069f13_fill_pattern_1_0: 30000 rects
+caravel_00069f13_fill_pattern_2_5: 3140000 rects
+caravel_00069f13_fill_pattern_1_6: 2880000 rects
+caravel_00069f13_fill_pattern_3_5: 2670000 rects
+caravel_00069f13_fill_pattern_1_1: 3020000 rects
+caravel_00069f13_fill_pattern_0_1: 340000 rects
+caravel_00069f13_fill_pattern_1_0: 40000 rects
+caravel_00069f13_fill_pattern_1_3: 3820000 rects
+caravel_00069f13_fill_pattern_2_4: 3710000 rects
+caravel_00069f13_fill_pattern_5_4: 640000 rects
+caravel_00069f13_fill_pattern_4_0: 2550000 rects
+caravel_00069f13_fill_pattern_1_0: 50000 rects
+caravel_00069f13_fill_pattern_0_0: 2760000 rects
+caravel_00069f13_fill_pattern_0_1: 350000 rects
+caravel_00069f13_fill_pattern_1_3: 3830000 rects
+caravel_00069f13_fill_pattern_2_2: 3000000 rects
+caravel_00069f13_fill_pattern_3_4: 3430000 rects
+caravel_00069f13_fill_pattern_4_0: 2560000 rects
+caravel_00069f13_fill_pattern_0_4: 3260000 rects
+caravel_00069f13_fill_pattern_3_3: 3130000 rects
+caravel_00069f13_fill_pattern_3_5: 2680000 rects
+caravel_00069f13_fill_pattern_2_1: 2800000 rects
+caravel_00069f13_fill_pattern_0_6: 2920000 rects
+caravel_00069f13_fill_pattern_4_5: 1410000 rects
+caravel_00069f13_fill_pattern_1_6: 2890000 rects
+caravel_00069f13_fill_pattern_1_0: 60000 rects
+caravel_00069f13_fill_pattern_0_1: 360000 rects
+caravel_00069f13_fill_pattern_4_4: 3010000 rects
+caravel_00069f13_fill_pattern_1_5: 3200000 rects
+caravel_00069f13_fill_pattern_4_0: 2570000 rects
+caravel_00069f13_fill_pattern_1_3: 3840000 rects
+caravel_00069f13_fill_pattern_1_2: 3460000 rects
+caravel_00069f13_fill_pattern_2_6: 3350000 rects
+caravel_00069f13_fill_pattern_3_0: 3320000 rects
+caravel_00069f13_fill_pattern_2_0: 2790000 rects
+caravel_00069f13_fill_pattern_0_1: 370000 rects
+caravel_00069f13_fill_pattern_4_0: 2580000 rects
+caravel_00069f13_fill_pattern_5_4: 650000 rects
+caravel_00069f13_fill_pattern_1_1: 3030000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00069f13_fill_pattern_1_3: 3850000 rects
+caravel_00069f13_fill_pattern_2_2: 3010000 rects
+caravel_00069f13_fill_pattern_1_0: 70000 rects
+caravel_00069f13_fill_pattern_3_1: 2740000 rects
+caravel_00069f13_fill_pattern_3_5: 2690000 rects
+ Generating output for cell caravel_00069f13_fill_pattern_0_2
+caravel_00069f13_fill_pattern_2_5: 3150000 rects
+caravel_00069f13_fill_pattern_4_0: 2590000 rects
+caravel_00069f13_fill_pattern_0_1: 380000 rects
+caravel_00069f13_fill_pattern_3_4: 3440000 rects
+caravel_00069f13_fill_pattern_1_0: 80000 rects
+caravel_00069f13_fill_pattern_4_4: 3020000 rects
+caravel_00069f13_fill_pattern_0_0: 2770000 rects
+caravel_00069f13_fill_pattern_1_3: 3860000 rects
+caravel_00069f13_fill_pattern_4_5: 1420000 rects
+caravel_00069f13_fill_pattern_4_0: 2600000 rects
+caravel_00069f13_fill_pattern_1_6: 2900000 rects
+caravel_00069f13_fill_pattern_2_4: 3720000 rects
+caravel_00069f13_fill_pattern_0_4: 3270000 rects
+caravel_00069f13_fill_pattern_3_3: 3140000 rects
+caravel_00069f13_fill_pattern_0_6: 2930000 rects
+caravel_00069f13_fill_pattern_1_0: 90000 rects
+caravel_00069f13_fill_pattern_4_0: 2610000 rects
+caravel_00069f13_fill_pattern_3_5: 2700000 rects
+caravel_00069f13_fill_pattern_2_2: 3020000 rects
+caravel_00069f13_fill_pattern_1_3: 3870000 rects
+caravel_00069f13_fill_pattern_5_4: 660000 rects
+caravel_00069f13_fill_pattern_0_1: 390000 rects
+caravel_00069f13_fill_pattern_1_0: 100000 rects
+caravel_00069f13_fill_pattern_1_5: 3210000 rects
+caravel_00069f13_fill_pattern_3_0: 3330000 rects
+caravel_00069f13_fill_pattern_4_4: 3030000 rects
+caravel_00069f13_fill_pattern_1_3: 3880000 rects
+caravel_00069f13_fill_pattern_4_5: 1430000 rects
+caravel_00069f13_fill_pattern_1_0: 110000 rects
+caravel_00069f13_fill_pattern_2_0: 2800000 rects
+caravel_00069f13_fill_pattern_3_4: 3450000 rects
+caravel_00069f13_fill_pattern_1_6: 2910000 rects
+caravel_00069f13_fill_pattern_2_6: 3360000 rects
+caravel_00069f13_fill_pattern_0_1: 400000 rects
+caravel_00069f13_fill_pattern_1_1: 3040000 rects
+caravel_00069f13_fill_pattern_4_0: 2620000 rects
+caravel_00069f13_fill_pattern_3_5: 2710000 rects
+caravel_00069f13_fill_pattern_0_0: 2780000 rects
+caravel_00069f13_fill_pattern_2_5: 3160000 rects
+caravel_00069f13_fill_pattern_2_2: 3030000 rects
+caravel_00069f13_fill_pattern_0_4: 3280000 rects
+caravel_00069f13_fill_pattern_1_0: 120000 rects
+caravel_00069f13_fill_pattern_1_3: 3890000 rects
+caravel_00069f13_fill_pattern_0_6: 2940000 rects
+caravel_00069f13_fill_pattern_3_3: 3150000 rects
+caravel_00069f13_fill_pattern_0_1: 410000 rects
+caravel_00069f13_fill_pattern_5_4: 670000 rects
+caravel_00069f13_fill_pattern_1_0: 130000 rects
+caravel_00069f13_fill_pattern_3_5: 2720000 rects
+caravel_00069f13_fill_pattern_2_4: 3730000 rects
+caravel_00069f13_fill_pattern_1_3: 3900000 rects
+caravel_00069f13_fill_pattern_0_1: 420000 rects
+caravel_00069f13_fill_pattern_4_5: 1440000 rects
+caravel_00069f13_fill_pattern_3_5: 2730000 rects
+caravel_00069f13_fill_pattern_3_4: 3460000 rects
+caravel_00069f13_fill_pattern_1_0: 140000 rects
+caravel_00069f13_fill_pattern_4_4: 3040000 rects
+caravel_00069f13_fill_pattern_1_5: 3220000 rects
+caravel_00069f13_fill_pattern_3_0: 3340000 rects
+caravel_00069f13_fill_pattern_1_6: 2920000 rects
+caravel_00069f13_fill_pattern_2_2: 3040000 rects
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+caravel_00069f13_fill_pattern_2_5: 3250000 rects
+caravel_00069f13_fill_pattern_2_6: 3450000 rects
+caravel_00069f13_fill_pattern_5_4: 940000 rects
+caravel_00069f13_fill_pattern_1_2: 3500000 rects
+caravel_00069f13_fill_pattern_1_0: 470000 rects
+caravel_00069f13_fill_pattern_1_3: 4200000 rects
+caravel_00069f13_fill_pattern_4_5: 1560000 rects
+caravel_00069f13_fill_pattern_1_6: 3050000 rects
+caravel_00069f13_fill_pattern_2_2: 3320000 rects
+caravel_00069f13_fill_pattern_0_1: 820000 rects
+caravel_00069f13_fill_pattern_1_5: 3310000 rects
+caravel_00069f13_fill_pattern_0_4: 3430000 rects
+caravel_00069f13_fill_pattern_2_0: 2890000 rects
+caravel_00069f13_fill_pattern_1_0: 480000 rects
+caravel_00069f13_fill_pattern_3_1: 2820000 rects
+caravel_00069f13_fill_pattern_5_4: 950000 rects
+caravel_00069f13_fill_pattern_1_3: 4210000 rects
+caravel_00069f13_fill_pattern_0_1: 830000 rects
+caravel_00069f13_fill_pattern_2_2: 3330000 rects
+caravel_00069f13_fill_pattern_1_0: 490000 rects
+caravel_00069f13_fill_pattern_3_4: 3600000 rects
+caravel_00069f13_fill_pattern_3_0: 3430000 rects
+caravel_00069f13_fill_pattern_2_4: 3820000 rects
+caravel_00069f13_fill_pattern_4_4: 3150000 rects
+caravel_00069f13_fill_pattern_5_4: 960000 rects
+caravel_00069f13_fill_pattern_0_6: 3070000 rects
+caravel_00069f13_fill_pattern_1_3: 4220000 rects
+caravel_00069f13_fill_pattern_0_0: 2890000 rects
+caravel_00069f13_fill_pattern_2_2: 3340000 rects
+caravel_00069f13_fill_pattern_1_6: 3060000 rects
+caravel_00069f13_fill_pattern_1_0: 500000 rects
+caravel_00069f13_fill_pattern_4_5: 1570000 rects
+caravel_00069f13_fill_pattern_2_6: 3460000 rects
+caravel_00069f13_fill_pattern_3_3: 3260000 rects
+caravel_00069f13_fill_pattern_5_4: 970000 rects
+caravel_00069f13_fill_pattern_0_4: 3440000 rects
+caravel_00069f13_fill_pattern_0_1: 840000 rects
+caravel_00069f13_fill_pattern_2_5: 3260000 rects
+caravel_00069f13_fill_pattern_1_3: 4230000 rects
+caravel_00069f13_fill_pattern_2_2: 3350000 rects
+caravel_00069f13_fill_pattern_1_0: 510000 rects
+caravel_00069f13_fill_pattern_2_1: 2860000 rects
+caravel_00069f13_fill_pattern_4_3: 3060000 rects
+caravel_00069f13_fill_pattern_5_4: 980000 rects
+caravel_00069f13_fill_pattern_0_1: 850000 rects
+caravel_00069f13_fill_pattern_3_1: 2830000 rects
+caravel_00069f13_fill_pattern_1_0: 520000 rects
+caravel_00069f13_fill_pattern_3_4: 3610000 rects
+caravel_00069f13_fill_pattern_2_0: 2900000 rects
+caravel_00069f13_fill_pattern_2_2: 3360000 rects
+caravel_00069f13_fill_pattern_1_5: 3320000 rects
+caravel_00069f13_fill_pattern_1_3: 4240000 rects
+caravel_00069f13_fill_pattern_5_4: 990000 rects
+caravel_00069f13_fill_pattern_4_4: 3160000 rects
+caravel_00069f13_fill_pattern_1_6: 3070000 rects
+caravel_00069f13_fill_pattern_0_6: 3080000 rects
+caravel_00069f13_fill_pattern_4_5: 1580000 rects
+caravel_00069f13_fill_pattern_0_1: 860000 rects
+caravel_00069f13_fill_pattern_1_0: 530000 rects
+caravel_00069f13_fill_pattern_0_0: 2900000 rects
+caravel_00069f13_fill_pattern_0_4: 3450000 rects
+caravel_00069f13_fill_pattern_2_2: 3370000 rects
+caravel_00069f13_fill_pattern_4_3: 3070000 rects
+caravel_00069f13_fill_pattern_1_3: 4250000 rects
+caravel_00069f13_fill_pattern_2_4: 3830000 rects
+caravel_00069f13_fill_pattern_3_3: 3270000 rects
+caravel_00069f13_fill_pattern_1_1: 3110000 rects
+caravel_00069f13_fill_pattern_1_0: 540000 rects
+caravel_00069f13_fill_pattern_2_6: 3470000 rects
+caravel_00069f13_fill_pattern_4_3: 3080000 rects
+caravel_00069f13_fill_pattern_0_1: 870000 rects
+caravel_00069f13_fill_pattern_5_4: 1000000 rects
+caravel_00069f13_fill_pattern_3_0: 3440000 rects
+caravel_00069f13_fill_pattern_2_2: 3380000 rects
+caravel_00069f13_fill_pattern_3_4: 3620000 rects
+caravel_00069f13_fill_pattern_1_3: 4260000 rects
+caravel_00069f13_fill_pattern_2_5: 3270000 rects
+caravel_00069f13_fill_pattern_1_0: 550000 rects
+caravel_00069f13_fill_pattern_1_6: 3080000 rects
+caravel_00069f13_fill_pattern_4_4: 3170000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00069f13_fill_pattern_0_6: 3090000 rects
+caravel_00069f13_fill_pattern_5_4: 1010000 rects
+caravel_00069f13_fill_pattern_3_1: 2840000 rects
+caravel_00069f13_fill_pattern_2_2: 3390000 rects
+caravel_00069f13_fill_pattern_1_5: 3330000 rects
+caravel_00069f13_fill_pattern_4_5: 1590000 rects
+caravel_00069f13_fill_pattern_0_1: 880000 rects
+caravel_00069f13_fill_pattern_1_3: 4270000 rects
+caravel_00069f13_fill_pattern_0_4: 3460000 rects
+caravel_00069f13_fill_pattern_1_0: 560000 rects
+caravel_00069f13_fill_pattern_3_5: 2810000 rects
+ Generating output for cell caravel_00069f13_fill_pattern_4_0
+caravel_00069f13_fill_pattern_5_4: 1020000 rects
+caravel_00069f13_fill_pattern_0_0: 2910000 rects
+caravel_00069f13_fill_pattern_1_2: 3510000 rects
+caravel_00069f13_fill_pattern_0_1: 890000 rects
+caravel_00069f13_fill_pattern_2_1: 2870000 rects
+caravel_00069f13_fill_pattern_2_2: 3400000 rects
+caravel_00069f13_fill_pattern_2_0: 2910000 rects
+caravel_00069f13_fill_pattern_3_0: 3450000 rects
+caravel_00069f13_fill_pattern_1_0: 570000 rects
+caravel_00069f13_fill_pattern_5_4: 1030000 rects
+caravel_00069f13_fill_pattern_3_4: 3630000 rects
+caravel_00069f13_fill_pattern_1_3: 4280000 rects
+caravel_00069f13_fill_pattern_3_3: 3280000 rects
+caravel_00069f13_fill_pattern_2_4: 3840000 rects
+caravel_00069f13_fill_pattern_0_1: 900000 rects
+caravel_00069f13_fill_pattern_4_3: 3090000 rects
+caravel_00069f13_fill_pattern_4_4: 3180000 rects
+caravel_00069f13_fill_pattern_1_6: 3090000 rects
+caravel_00069f13_fill_pattern_1_0: 580000 rects
+caravel_00069f13_fill_pattern_2_2: 3410000 rects
+caravel_00069f13_fill_pattern_2_6: 3480000 rects
+caravel_00069f13_fill_pattern_0_6: 3100000 rects
+caravel_00069f13_fill_pattern_4_5: 1600000 rects
+caravel_00069f13_fill_pattern_1_3: 4290000 rects
+caravel_00069f13_fill_pattern_0_4: 3470000 rects
+caravel_00069f13_fill_pattern_2_5: 3280000 rects
+caravel_00069f13_fill_pattern_0_1: 910000 rects
+caravel_00069f13_fill_pattern_1_0: 590000 rects
+caravel_00069f13_fill_pattern_2_2: 3420000 rects
+caravel_00069f13_fill_pattern_3_1: 2850000 rects
+caravel_00069f13_fill_pattern_1_5: 3340000 rects
+caravel_00069f13_fill_pattern_0_0: 2920000 rects
+caravel_00069f13_fill_pattern_0_1: 920000 rects
+caravel_00069f13_fill_pattern_1_3: 4300000 rects
+caravel_00069f13_fill_pattern_3_4: 3640000 rects
+caravel_00069f13_fill_pattern_1_0: 600000 rects
+caravel_00069f13_fill_pattern_2_1: 2880000 rects
+caravel_00069f13_fill_pattern_2_2: 3430000 rects
+caravel_00069f13_fill_pattern_1_6: 3100000 rects
+caravel_00069f13_fill_pattern_4_4: 3190000 rects
+caravel_00069f13_fill_pattern_0_1: 930000 rects
+caravel_00069f13_fill_pattern_0_4: 3480000 rects
+caravel_00069f13_fill_pattern_3_3: 3290000 rects
+caravel_00069f13_fill_pattern_3_0: 3460000 rects
+caravel_00069f13_fill_pattern_1_0: 610000 rects
+caravel_00069f13_fill_pattern_1_3: 4310000 rects
+caravel_00069f13_fill_pattern_3_5: 2820000 rects
+caravel_00069f13_fill_pattern_4_5: 1610000 rects
+caravel_00069f13_fill_pattern_0_6: 3110000 rects
+caravel_00069f13_fill_pattern_2_4: 3850000 rects
+caravel_00069f13_fill_pattern_2_2: 3440000 rects
+caravel_00069f13_fill_pattern_1_1: 3120000 rects
+caravel_00069f13_fill_pattern_2_0: 2920000 rects
+caravel_00069f13_fill_pattern_0_1: 940000 rects
+caravel_00069f13_fill_pattern_1_0: 620000 rects
+caravel_00069f13_fill_pattern_1_3: 4320000 rects
+caravel_00069f13_fill_pattern_3_4: 3650000 rects
+caravel_00069f13_fill_pattern_2_6: 3490000 rects
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+caravel_00069f13_fill_pattern_1_0: 630000 rects
+caravel_00069f13_fill_pattern_0_1: 950000 rects
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+caravel_00069f13_fill_pattern_1_5: 3350000 rects
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+caravel_00069f13_fill_pattern_0_4: 3490000 rects
+caravel_00069f13_fill_pattern_3_1: 2860000 rects
+caravel_00069f13_fill_pattern_1_0: 640000 rects
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+caravel_00069f13_fill_pattern_4_5: 1620000 rects
+caravel_00069f13_fill_pattern_0_1: 960000 rects
+caravel_00069f13_fill_pattern_1_3: 4340000 rects
+caravel_00069f13_fill_pattern_0_6: 3120000 rects
+caravel_00069f13_fill_pattern_3_3: 3300000 rects
+caravel_00069f13_fill_pattern_2_1: 2890000 rects
+caravel_00069f13_fill_pattern_2_2: 3470000 rects
+caravel_00069f13_fill_pattern_3_0: 3470000 rects
+caravel_00069f13_fill_pattern_3_4: 3660000 rects
+caravel_00069f13_fill_pattern_2_4: 3860000 rects
+caravel_00069f13_fill_pattern_1_0: 650000 rects
+caravel_00069f13_fill_pattern_0_1: 970000 rects
+caravel_00069f13_fill_pattern_1_3: 4350000 rects
+caravel_00069f13_fill_pattern_4_4: 3210000 rects
+caravel_00069f13_fill_pattern_3_5: 2830000 rects
+caravel_00069f13_fill_pattern_1_6: 3120000 rects
+caravel_00069f13_fill_pattern_1_2: 3520000 rects
+caravel_00069f13_fill_pattern_0_4: 3500000 rects
+caravel_00069f13_fill_pattern_0_0: 2940000 rects
+caravel_00069f13_fill_pattern_1_0: 660000 rects
+caravel_00069f13_fill_pattern_2_2: 3480000 rects
+caravel_00069f13_fill_pattern_0_1: 980000 rects
+caravel_00069f13_fill_pattern_2_0: 2930000 rects
+caravel_00069f13_fill_pattern_2_6: 3500000 rects
+caravel_00069f13_fill_pattern_4_5: 1630000 rects
+caravel_00069f13_fill_pattern_1_3: 4360000 rects
+caravel_00069f13_fill_pattern_1_0: 670000 rects
+caravel_00069f13_fill_pattern_2_5: 3300000 rects
+caravel_00069f13_fill_pattern_0_6: 3130000 rects
+caravel_00069f13_fill_pattern_2_2: 3490000 rects
+caravel_00069f13_fill_pattern_3_1: 2870000 rects
+caravel_00069f13_fill_pattern_3_4: 3670000 rects
+caravel_00069f13_fill_pattern_1_5: 3360000 rects
+caravel_00069f13_fill_pattern_3_3: 3310000 rects
+caravel_00069f13_fill_pattern_1_0: 680000 rects
+caravel_00069f13_fill_pattern_0_1: 990000 rects
+caravel_00069f13_fill_pattern_1_3: 4370000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00069f13_fill_pattern_4_4: 3220000 rects
+caravel_00069f13_fill_pattern_2_2: 3500000 rects
+caravel_00069f13_fill_pattern_1_6: 3130000 rects
+caravel_00069f13_fill_pattern_2_4: 3870000 rects
+caravel_00069f13_fill_pattern_3_0: 3480000 rects
+caravel_00069f13_fill_pattern_0_4: 3510000 rects
+caravel_00069f13_fill_pattern_1_0: 690000 rects
+ Generating output for cell caravel_00069f13_fill_pattern_4_3
+CIF output style is now "wafflefill(tiled)"
+caravel_00069f13_fill_pattern_4_5: 1640000 rects
+caravel_00069f13_fill_pattern_1_3: 4380000 rects
+caravel_00069f13_fill_pattern_2_2: 3510000 rects
+caravel_00069f13_fill_pattern_3_5: 2840000 rects
+caravel_00069f13_fill_pattern_3_4: 3680000 rects
+caravel_00069f13_fill_pattern_2_1: 2900000 rects
+ Generating output for cell caravel_00069f13_fill_pattern_5_4
+caravel_00069f13_fill_pattern_1_0: 700000 rects
+caravel_00069f13_fill_pattern_0_6: 3140000 rects
+caravel_00069f13_fill_pattern_0_0: 2950000 rects
+caravel_00069f13_fill_pattern_0_1: 1000000 rects
+caravel_00069f13_fill_pattern_2_6: 3510000 rects
+caravel_00069f13_fill_pattern_2_0: 2940000 rects
+caravel_00069f13_fill_pattern_1_1: 3130000 rects
+caravel_00069f13_fill_pattern_2_2: 3520000 rects
+caravel_00069f13_fill_pattern_1_0: 710000 rects
+caravel_00069f13_fill_pattern_1_5: 3370000 rects
+caravel_00069f13_fill_pattern_3_3: 3320000 rects
+caravel_00069f13_fill_pattern_4_4: 3230000 rects
+caravel_00069f13_fill_pattern_2_5: 3310000 rects
+caravel_00069f13_fill_pattern_1_6: 3140000 rects
+caravel_00069f13_fill_pattern_3_1: 2880000 rects
+caravel_00069f13_fill_pattern_0_4: 3520000 rects
+caravel_00069f13_fill_pattern_1_3: 4390000 rects
+caravel_00069f13_fill_pattern_1_0: 720000 rects
+caravel_00069f13_fill_pattern_2_2: 3530000 rects
+caravel_00069f13_fill_pattern_0_1: 1010000 rects
+caravel_00069f13_fill_pattern_3_4: 3690000 rects
+caravel_00069f13_fill_pattern_2_4: 3880000 rects
+caravel_00069f13_fill_pattern_1_0: 730000 rects
+caravel_00069f13_fill_pattern_4_5: 1650000 rects
+caravel_00069f13_fill_pattern_3_0: 3490000 rects
+caravel_00069f13_fill_pattern_0_1: 1020000 rects
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+caravel_00069f13_fill_pattern_2_2: 3540000 rects
+caravel_00069f13_fill_pattern_0_0: 2960000 rects
+caravel_00069f13_fill_pattern_1_0: 740000 rects
+caravel_00069f13_fill_pattern_0_1: 1030000 rects
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+caravel_00069f13_fill_pattern_2_1: 2910000 rects
+caravel_00069f13_fill_pattern_2_0: 2950000 rects
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+caravel_00069f13_fill_pattern_1_0: 750000 rects
+caravel_00069f13_fill_pattern_3_1: 2890000 rects
+caravel_00069f13_fill_pattern_2_5: 3320000 rects
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+caravel_00069f13_fill_pattern_3_5: 2850000 rects
+caravel_00069f13_fill_pattern_0_1: 1040000 rects
+caravel_00069f13_fill_pattern_2_2: 3560000 rects
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+caravel_00069f13_fill_pattern_3_3: 3330000 rects
+caravel_00069f13_fill_pattern_0_6: 3160000 rects
+caravel_00069f13_fill_pattern_1_0: 770000 rects
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+caravel_00069f13_fill_pattern_2_2: 3570000 rects
+caravel_00069f13_fill_pattern_0_1: 1050000 rects
+caravel_00069f13_fill_pattern_2_4: 3890000 rects
+caravel_00069f13_fill_pattern_4_5: 1660000 rects
+caravel_00069f13_fill_pattern_4_4: 3250000 rects
+caravel_00069f13_fill_pattern_0_0: 2970000 rects
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+caravel_00069f13_fill_pattern_1_0: 780000 rects
+caravel_00069f13_fill_pattern_3_4: 3710000 rects
+caravel_00069f13_fill_pattern_0_1: 1060000 rects
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+caravel_00069f13_fill_pattern_3_1: 2900000 rects
+caravel_00069f13_fill_pattern_1_0: 790000 rects
+caravel_00069f13_fill_pattern_1_5: 3390000 rects
+caravel_00069f13_fill_pattern_0_1: 1070000 rects
+caravel_00069f13_fill_pattern_2_5: 3330000 rects
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+caravel_00069f13_fill_pattern_2_2: 3590000 rects
+caravel_00069f13_fill_pattern_3_5: 2860000 rects
+caravel_00069f13_fill_pattern_2_6: 3530000 rects
+caravel_00069f13_fill_pattern_2_1: 2920000 rects
+caravel_00069f13_fill_pattern_3_3: 3340000 rects
+caravel_00069f13_fill_pattern_1_6: 3170000 rects
+caravel_00069f13_fill_pattern_4_4: 3260000 rects
+caravel_00069f13_fill_pattern_3_0: 3510000 rects
+caravel_00069f13_fill_pattern_0_4: 3550000 rects
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+caravel_00069f13_fill_pattern_1_0: 800000 rects
+caravel_00069f13_fill_pattern_0_0: 2980000 rects
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+caravel_00069f13_fill_pattern_0_1: 1090000 rects
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+caravel_00069f13_fill_pattern_3_5: 2880000 rects
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+caravel_00069f13_fill_pattern_1_0: 810000 rects
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+caravel_00069f13_fill_pattern_4_4: 3270000 rects
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+caravel_00069f13_fill_pattern_0_1: 1100000 rects
+caravel_00069f13_fill_pattern_1_0: 820000 rects
+caravel_00069f13_fill_pattern_3_1: 2910000 rects
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+caravel_00069f13_fill_pattern_3_3: 3350000 rects
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+caravel_00069f13_fill_pattern_2_0: 2970000 rects
+caravel_00069f13_fill_pattern_1_0: 830000 rects
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+caravel_00069f13_fill_pattern_2_6: 3540000 rects
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+caravel_00069f13_fill_pattern_2_1: 2930000 rects
+caravel_00069f13_fill_pattern_1_0: 840000 rects
+caravel_00069f13_fill_pattern_3_0: 3520000 rects
+caravel_00069f13_fill_pattern_0_1: 1110000 rects
+caravel_00069f13_fill_pattern_4_5: 1680000 rects
+caravel_00069f13_fill_pattern_0_4: 3560000 rects
+caravel_00069f13_fill_pattern_0_0: 2990000 rects
+caravel_00069f13_fill_pattern_1_2: 3540000 rects
+caravel_00069f13_fill_pattern_1_0: 850000 rects
+caravel_00069f13_fill_pattern_4_4: 3280000 rects
+caravel_00069f13_fill_pattern_1_6: 3190000 rects
+caravel_00069f13_fill_pattern_0_6: 3190000 rects
+caravel_00069f13_fill_pattern_3_5: 2900000 rects
+caravel_00069f13_fill_pattern_2_2: 3640000 rects
+caravel_00069f13_fill_pattern_3_4: 3740000 rects
+caravel_00069f13_fill_pattern_1_1: 3150000 rects
+caravel_00069f13_fill_pattern_0_1: 1120000 rects
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+caravel_00069f13_fill_pattern_2_4: 3910000 rects
+caravel_00069f13_fill_pattern_3_1: 2920000 rects
+caravel_00069f13_fill_pattern_1_0: 870000 rects
+caravel_00069f13_fill_pattern_3_3: 3360000 rects
+caravel_00069f13_fill_pattern_0_1: 1130000 rects
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+CIF output style is now "wafflefill(tiled)"
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+ Generating output for cell caravel_00069f13_fill_pattern_3_5
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+caravel_00069f13_fill_pattern_0_4: 4930000 rects
+caravel_00069f13_fill_pattern_1_3: 4690000 rects
+caravel_00069f13_fill_pattern_1_0: 3080000 rects
+caravel_00069f13_fill_pattern_0_1: 2540000 rects
+caravel_00069f13_fill_pattern_4_5: 2890000 rects
+caravel_00069f13_fill_pattern_3_1: 3550000 rects
+caravel_00069f13_fill_pattern_2_1: 3610000 rects
+caravel_00069f13_fill_pattern_1_6: 4370000 rects
+caravel_00069f13_fill_pattern_1_1: 3810000 rects
+caravel_00069f13_fill_pattern_2_0: 3610000 rects
+caravel_00069f13_fill_pattern_3_4: 4900000 rects
+caravel_00069f13_fill_pattern_1_2: 3910000 rects
+caravel_00069f13_fill_pattern_0_4: 4940000 rects
+caravel_00069f13_fill_pattern_0_0: 4090000 rects
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_00069f13_fill_pattern_1_5: 4540000 rects
+caravel_00069f13_fill_pattern_3_0: 4240000 rects
+caravel_00069f13_fill_pattern_3_4: 4910000 rects
+caravel_00069f13_fill_pattern_3_3: 4110000 rects
+caravel_00069f13_fill_pattern_4_5: 2900000 rects
+caravel_00069f13_fill_pattern_1_0: 3090000 rects
+caravel_00069f13_fill_pattern_0_4: 4950000 rects
+caravel_00069f13_fill_pattern_2_4: 4560000 rects
+caravel_00069f13_fill_pattern_0_0: 4100000 rects
+caravel_00069f13_fill_pattern_0_1: 2550000 rects
+caravel_00069f13_fill_pattern_2_5: 4030000 rects
+caravel_00069f13_fill_pattern_2_6: 4230000 rects
+caravel_00069f13_fill_pattern_3_4: 4920000 rects
+caravel_00069f13_fill_pattern_2_1: 3620000 rects
+caravel_00069f13_fill_pattern_1_5: 4550000 rects
+Processing system .magicrc file
+caravel_00069f13_fill_pattern_1_2: 3920000 rects
+caravel_00069f13_fill_pattern_1_1: 3820000 rects
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_00069f13_fill_pattern_0_6: 4560000 rects
+caravel_00069f13_fill_pattern_0_4: 4960000 rects
+caravel_00069f13_fill_pattern_0_0: 4110000 rects
+caravel_00069f13_fill_pattern_2_0: 3620000 rects
+caravel_00069f13_fill_pattern_1_2: 3930000 rects
+caravel_00069f13_fill_pattern_0_6: 4570000 rects
+caravel_00069f13_fill_pattern_4_5: 2910000 rects
+caravel_00069f13_fill_pattern_3_4: 4930000 rects
+caravel_00069f13_fill_pattern_1_2: 3940000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_00069f13_fill_pattern_0_6: 4580000 rects
+caravel_00069f13_fill_pattern_3_0: 4250000 rects
+caravel_00069f13_fill_pattern_3_3: 4120000 rects
+caravel_00069f13_fill_pattern_0_4: 4970000 rects
+caravel_00069f13_fill_pattern_1_0: 3100000 rects
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+caravel_00069f13_fill_pattern_1_2: 3960000 rects
+caravel_00069f13_fill_pattern_2_4: 4570000 rects
+caravel_00069f13_fill_pattern_2_6: 4240000 rects
+caravel_00069f13_fill_pattern_2_5: 4040000 rects
+caravel_00069f13_fill_pattern_0_6: 4600000 rects
+caravel_00069f13_fill_pattern_0_1: 2560000 rects
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+caravel_00069f13_fill_pattern_1_2: 3980000 rects
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+caravel_00069f13_fill_pattern_3_0: 4260000 rects
+caravel_00069f13_fill_pattern_1_5: 4570000 rects
+caravel_00069f13_fill_pattern_1_0: 3110000 rects
+caravel_00069f13_fill_pattern_1_2: 3990000 rects
+caravel_00069f13_fill_pattern_0_6: 4620000 rects
+caravel_00069f13_fill_pattern_2_0: 3630000 rects
+caravel_00069f13_fill_pattern_3_4: 4950000 rects
+caravel_00069f13_fill_pattern_0_4: 4990000 rects
+caravel_00069f13_fill_pattern_3_3: 4130000 rects
+caravel_00069f13_fill_pattern_1_2: 4000000 rects
+caravel_00069f13_fill_pattern_0_1: 2570000 rects
+caravel_00069f13_fill_pattern_0_0: 4140000 rects
+caravel_00069f13_fill_pattern_1_2: 4010000 rects
+caravel_00069f13_fill_pattern_0_6: 4630000 rects
+caravel_00069f13_fill_pattern_2_6: 4250000 rects
+caravel_00069f13_fill_pattern_0_4: 5000000 rects
+caravel_00069f13_fill_pattern_1_2: 4020000 rects
+caravel_00069f13_fill_pattern_4_5: 2930000 rects
+caravel_00069f13_fill_pattern_1_5: 4580000 rects
+caravel_00069f13_fill_pattern_2_5: 4050000 rects
+caravel_00069f13_fill_pattern_1_1: 3840000 rects
+caravel_00069f13_fill_pattern_2_4: 4580000 rects
+caravel_00069f13_fill_pattern_1_2: 4030000 rects
+caravel_00069f13_fill_pattern_0_0: 4150000 rects
+caravel_00069f13_fill_pattern_2_1: 3640000 rects
+caravel_00069f13_fill_pattern_3_0: 4270000 rects
+caravel_00069f13_fill_pattern_4_5: 2940000 rects
+caravel_00069f13_fill_pattern_1_0: 3120000 rects
+caravel_00069f13_fill_pattern_3_4: 4960000 rects
+caravel_00069f13_fill_pattern_1_2: 4040000 rects
+caravel_00069f13_fill_pattern_0_4: 5010000 rects
+caravel_00069f13_fill_pattern_0_6: 4640000 rects
+caravel_00069f13_fill_pattern_4_5: 2950000 rects
+caravel_00069f13_fill_pattern_1_2: 4050000 rects
+caravel_00069f13_fill_pattern_3_3: 4140000 rects
+caravel_00069f13_fill_pattern_2_0: 3640000 rects
+caravel_00069f13_fill_pattern_1_5: 4590000 rects
+caravel_00069f13_fill_pattern_1_3: 4710000 rects
+caravel_00069f13_fill_pattern_1_1: 3850000 rects
+caravel_00069f13_fill_pattern_0_0: 4160000 rects
+caravel_00069f13_fill_pattern_4_5: 2960000 rects
+caravel_00069f13_fill_pattern_1_2: 4060000 rects
+caravel_00069f13_fill_pattern_0_4: 5020000 rects
+caravel_00069f13_fill_pattern_3_4: 4970000 rects
+caravel_00069f13_fill_pattern_2_6: 4260000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+caravel_00069f13_fill_pattern_0_1: 2580000 rects
+caravel_00069f13_fill_pattern_2_5: 4060000 rects
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+caravel_00069f13_fill_pattern_1_2: 4070000 rects
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_00069f13_fill_pattern_3_1: 3570000 rects
+caravel_00069f13_fill_pattern_0_6: 4650000 rects
+caravel_00069f13_fill_pattern_2_4: 4590000 rects
+caravel_00069f13_fill_pattern_0_0: 4170000 rects
+caravel_00069f13_fill_pattern_0_4: 5030000 rects
+caravel_00069f13_fill_pattern_1_5: 4600000 rects
+caravel_00069f13_fill_pattern_1_0: 3130000 rects
+caravel_00069f13_fill_pattern_1_2: 4080000 rects
+caravel_00069f13_fill_pattern_3_0: 4280000 rects
+caravel_00069f13_fill_pattern_2_1: 3650000 rects
+caravel_00069f13_fill_pattern_3_4: 4980000 rects
+caravel_00069f13_fill_pattern_4_5: 2970000 rects
+caravel_00069f13_fill_pattern_1_2: 4090000 rects
+caravel_00069f13_fill_pattern_3_3: 4150000 rects
+caravel_00069f13_fill_pattern_2_2: 4770000 rects
+caravel_00069f13_fill_pattern_0_4: 5040000 rects
+caravel_00069f13_fill_pattern_1_6: 4380000 rects
+caravel_00069f13_fill_pattern_1_1: 3860000 rects
+caravel_00069f13_fill_pattern_0_0: 4180000 rects
+caravel_00069f13_fill_pattern_2_0: 3650000 rects
+caravel_00069f13_fill_pattern_2_3: 10000 rects
+caravel_00069f13_fill_pattern_0_6: 4660000 rects
+caravel_00069f13_fill_pattern_1_2: 4100000 rects
+caravel_00069f13_fill_pattern_3_4: 4990000 rects
+caravel_00069f13_fill_pattern_1_5: 4610000 rects
+caravel_00069f13_fill_pattern_2_6: 4270000 rects
+caravel_00069f13_fill_pattern_2_5: 4070000 rects
+caravel_00069f13_fill_pattern_1_2: 4110000 rects
+caravel_00069f13_fill_pattern_0_4: 5050000 rects
+caravel_00069f13_fill_pattern_0_0: 4190000 rects
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+caravel_00069f13_fill_pattern_1_0: 3140000 rects
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+caravel_00069f13_fill_pattern_1_2: 4120000 rects
+caravel_00069f13_fill_pattern_3_1: 3580000 rects
+caravel_00069f13_fill_pattern_0_6: 4670000 rects
+caravel_00069f13_fill_pattern_3_0: 4290000 rects
+caravel_00069f13_fill_pattern_2_3: 30000 rects
+caravel_00069f13_fill_pattern_3_3: 4160000 rects
+caravel_00069f13_fill_pattern_1_5: 4620000 rects
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+caravel_00069f13_fill_pattern_2_3: 40000 rects
+caravel_00069f13_fill_pattern_1_2: 4130000 rects
+caravel_00069f13_fill_pattern_0_0: 4200000 rects
+caravel_00069f13_fill_pattern_0_1: 2590000 rects
+caravel_00069f13_fill_pattern_2_3: 50000 rects
+caravel_00069f13_fill_pattern_3_4: 5010000 rects
+caravel_00069f13_fill_pattern_2_0: 3660000 rects
+caravel_00069f13_fill_pattern_1_2: 4140000 rects
+caravel_00069f13_fill_pattern_0_4: 5070000 rects
+caravel_00069f13_fill_pattern_2_6: 4280000 rects
+caravel_00069f13_fill_pattern_2_5: 4080000 rects
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+caravel_00069f13_fill_pattern_1_5: 4630000 rects
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+caravel_00069f13_fill_pattern_2_3: 100000 rects
+caravel_00069f13_fill_pattern_2_5: 4090000 rects
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+caravel_00069f13_fill_pattern_0_4: 5190000 rects
+caravel_00069f13_fill_pattern_2_3: 310000 rects
+caravel_00069f13_fill_pattern_3_0: 4360000 rects
+caravel_00069f13_fill_pattern_0_0: 4330000 rects
+caravel_00069f13_fill_pattern_3_4: 5140000 rects
+caravel_00069f13_fill_pattern_1_0: 3220000 rects
+caravel_00069f13_fill_pattern_2_6: 4340000 rects
+caravel_00069f13_fill_pattern_1_6: 4430000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00069f13_fill_pattern_2_3: 320000 rects
+caravel_00069f13_fill_pattern_2_0: 3720000 rects
+caravel_00069f13_fill_pattern_2_5: 4140000 rects
+caravel_00069f13_fill_pattern_0_4: 5200000 rects
+ Generating output for cell caravel_00069f13_fill_pattern_4_5
+caravel_00069f13_fill_pattern_0_1: 2650000 rects
+caravel_00069f13_fill_pattern_1_1: 3950000 rects
+caravel_00069f13_fill_pattern_2_4: 4670000 rects
+caravel_00069f13_fill_pattern_1_5: 4780000 rects
+caravel_00069f13_fill_pattern_3_4: 5150000 rects
+caravel_00069f13_fill_pattern_0_0: 4340000 rects
+caravel_00069f13_fill_pattern_2_3: 330000 rects
+caravel_00069f13_fill_pattern_2_1: 3720000 rects
+caravel_00069f13_fill_pattern_3_1: 3640000 rects
+caravel_00069f13_fill_pattern_0_4: 5210000 rects
+caravel_00069f13_fill_pattern_2_3: 340000 rects
+caravel_00069f13_fill_pattern_0_0: 4350000 rects
+caravel_00069f13_fill_pattern_3_4: 5160000 rects
+caravel_00069f13_fill_pattern_1_6: 4440000 rects
+caravel_00069f13_fill_pattern_3_3: 4220000 rects
+caravel_00069f13_fill_pattern_3_0: 4370000 rects
+caravel_00069f13_fill_pattern_2_3: 350000 rects
+caravel_00069f13_fill_pattern_1_2: 4270000 rects
+caravel_00069f13_fill_pattern_1_0: 3230000 rects
+caravel_00069f13_fill_pattern_0_4: 5220000 rects
+caravel_00069f13_fill_pattern_0_1: 2660000 rects
+caravel_00069f13_fill_pattern_2_5: 4150000 rects
+caravel_00069f13_fill_pattern_1_1: 3960000 rects
+caravel_00069f13_fill_pattern_2_6: 4350000 rects
+caravel_00069f13_fill_pattern_0_6: 4780000 rects
+caravel_00069f13_fill_pattern_2_3: 360000 rects
+caravel_00069f13_fill_pattern_0_0: 4360000 rects
+caravel_00069f13_fill_pattern_2_0: 3730000 rects
+caravel_00069f13_fill_pattern_3_4: 5170000 rects
+caravel_00069f13_fill_pattern_2_4: 4680000 rects
+caravel_00069f13_fill_pattern_0_6: 4790000 rects
+caravel_00069f13_fill_pattern_1_3: 4760000 rects
+caravel_00069f13_fill_pattern_0_4: 5230000 rects
+caravel_00069f13_fill_pattern_2_3: 370000 rects
+caravel_00069f13_fill_pattern_0_6: 4800000 rects
+caravel_00069f13_fill_pattern_3_1: 3650000 rects
+caravel_00069f13_fill_pattern_1_6: 4450000 rects
+caravel_00069f13_fill_pattern_2_1: 3730000 rects
+caravel_00069f13_fill_pattern_0_6: 4810000 rects
+caravel_00069f13_fill_pattern_2_3: 380000 rects
+caravel_00069f13_fill_pattern_3_4: 5180000 rects
+caravel_00069f13_fill_pattern_2_2: 4800000 rects
+caravel_00069f13_fill_pattern_0_0: 4370000 rects
+caravel_00069f13_fill_pattern_3_3: 4230000 rects
+caravel_00069f13_fill_pattern_3_0: 4380000 rects
+caravel_00069f13_fill_pattern_0_4: 5240000 rects
+caravel_00069f13_fill_pattern_0_1: 2670000 rects
+caravel_00069f13_fill_pattern_1_5: 4790000 rects
+caravel_00069f13_fill_pattern_1_0: 3240000 rects
+caravel_00069f13_fill_pattern_2_3: 390000 rects
+caravel_00069f13_fill_pattern_1_1: 3970000 rects
+caravel_00069f13_fill_pattern_2_5: 4160000 rects
+caravel_00069f13_fill_pattern_2_0: 3740000 rects
+caravel_00069f13_fill_pattern_2_6: 4360000 rects
+caravel_00069f13_fill_pattern_3_4: 5190000 rects
+caravel_00069f13_fill_pattern_2_3: 400000 rects
+caravel_00069f13_fill_pattern_0_0: 4380000 rects
+caravel_00069f13_fill_pattern_1_2: 4280000 rects
+caravel_00069f13_fill_pattern_2_4: 4690000 rects
+caravel_00069f13_fill_pattern_0_4: 5250000 rects
+caravel_00069f13_fill_pattern_1_6: 4460000 rects
+caravel_00069f13_fill_pattern_0_6: 4820000 rects
+caravel_00069f13_fill_pattern_2_3: 410000 rects
+caravel_00069f13_fill_pattern_2_1: 3740000 rects
+caravel_00069f13_fill_pattern_3_1: 3660000 rects
+caravel_00069f13_fill_pattern_3_4: 5200000 rects
+caravel_00069f13_fill_pattern_3_3: 4240000 rects
+caravel_00069f13_fill_pattern_0_0: 4390000 rects
+caravel_00069f13_fill_pattern_0_4: 5260000 rects
+caravel_00069f13_fill_pattern_2_3: 420000 rects
+caravel_00069f13_fill_pattern_1_1: 3980000 rects
+caravel_00069f13_fill_pattern_1_0: 3250000 rects
+caravel_00069f13_fill_pattern_3_0: 4390000 rects
+caravel_00069f13_fill_pattern_0_1: 2680000 rects
+caravel_00069f13_fill_pattern_1_3: 4770000 rects
+caravel_00069f13_fill_pattern_2_3: 430000 rects
+caravel_00069f13_fill_pattern_2_0: 3750000 rects
+caravel_00069f13_fill_pattern_3_4: 5210000 rects
+caravel_00069f13_fill_pattern_1_6: 4470000 rects
+caravel_00069f13_fill_pattern_0_0: 4400000 rects
+caravel_00069f13_fill_pattern_0_4: 5270000 rects
+caravel_00069f13_fill_pattern_2_6: 4370000 rects
+caravel_00069f13_fill_pattern_2_5: 4170000 rects
+caravel_00069f13_fill_pattern_2_3: 440000 rects
+caravel_00069f13_fill_pattern_1_1: 3990000 rects
+caravel_00069f13_fill_pattern_2_4: 4700000 rects
+caravel_00069f13_fill_pattern_1_6: 4480000 rects
+caravel_00069f13_fill_pattern_2_3: 450000 rects
+caravel_00069f13_fill_pattern_3_3: 4250000 rects
+caravel_00069f13_fill_pattern_0_4: 5280000 rects
+caravel_00069f13_fill_pattern_0_0: 4410000 rects
+caravel_00069f13_fill_pattern_1_6: 4490000 rects
+caravel_00069f13_fill_pattern_3_4: 5220000 rects
+caravel_00069f13_fill_pattern_2_1: 3750000 rects
+caravel_00069f13_fill_pattern_3_1: 3670000 rects
+caravel_00069f13_fill_pattern_1_0: 3260000 rects
+caravel_00069f13_fill_pattern_2_3: 460000 rects
+caravel_00069f13_fill_pattern_1_2: 4290000 rects
+caravel_00069f13_fill_pattern_1_5: 4800000 rects
+caravel_00069f13_fill_pattern_3_0: 4400000 rects
+caravel_00069f13_fill_pattern_0_1: 2690000 rects
+caravel_00069f13_fill_pattern_2_0: 3760000 rects
+caravel_00069f13_fill_pattern_0_4: 5290000 rects
+caravel_00069f13_fill_pattern_0_0: 4420000 rects
+caravel_00069f13_fill_pattern_2_3: 470000 rects
+caravel_00069f13_fill_pattern_3_4: 5230000 rects
+caravel_00069f13_fill_pattern_2_6: 4380000 rects
+caravel_00069f13_fill_pattern_2_3: 480000 rects
+caravel_00069f13_fill_pattern_2_4: 4710000 rects
+caravel_00069f13_fill_pattern_0_4: 5300000 rects
+caravel_00069f13_fill_pattern_2_0: 3770000 rects
+caravel_00069f13_fill_pattern_2_2: 4810000 rects
+caravel_00069f13_fill_pattern_0_0: 4430000 rects
+caravel_00069f13_fill_pattern_0_4: 5310000 rects
+caravel_00069f13_fill_pattern_2_3: 490000 rects
+caravel_00069f13_fill_pattern_2_1: 3760000 rects
+caravel_00069f13_fill_pattern_3_4: 5240000 rects
+caravel_00069f13_fill_pattern_1_0: 3270000 rects
+caravel_00069f13_fill_pattern_1_1: 4000000 rects
+caravel_00069f13_fill_pattern_1_3: 4780000 rects
+caravel_00069f13_fill_pattern_3_1: 3680000 rects
+caravel_00069f13_fill_pattern_0_4: 5320000 rects
+caravel_00069f13_fill_pattern_0_1: 2700000 rects
+caravel_00069f13_fill_pattern_3_0: 4410000 rects
+caravel_00069f13_fill_pattern_3_3: 4260000 rects
+caravel_00069f13_fill_pattern_2_3: 500000 rects
+caravel_00069f13_fill_pattern_0_4: 5330000 rects
+caravel_00069f13_fill_pattern_2_0: 3780000 rects
+caravel_00069f13_fill_pattern_2_5: 4180000 rects
+caravel_00069f13_fill_pattern_2_6: 4390000 rects
+caravel_00069f13_fill_pattern_0_0: 4440000 rects
+caravel_00069f13_fill_pattern_3_4: 5250000 rects
+caravel_00069f13_fill_pattern_2_3: 510000 rects
+caravel_00069f13_fill_pattern_0_4: 5340000 rects
+caravel_00069f13_fill_pattern_1_0: 3280000 rects
+caravel_00069f13_fill_pattern_0_4: 5350000 rects
+caravel_00069f13_fill_pattern_1_5: 4810000 rects
+caravel_00069f13_fill_pattern_2_4: 4720000 rects
+caravel_00069f13_fill_pattern_2_3: 520000 rects
+caravel_00069f13_fill_pattern_1_2: 4300000 rects
+caravel_00069f13_fill_pattern_2_0: 3790000 rects
+caravel_00069f13_fill_pattern_1_6: 4500000 rects
+caravel_00069f13_fill_pattern_0_4: 5360000 rects
+caravel_00069f13_fill_pattern_3_0: 4420000 rects
+caravel_00069f13_fill_pattern_3_4: 5260000 rects
+caravel_00069f13_fill_pattern_0_0: 4450000 rects
+caravel_00069f13_fill_pattern_2_1: 3770000 rects
+caravel_00069f13_fill_pattern_0_1: 2710000 rects
+caravel_00069f13_fill_pattern_4_4: 4610000 rects
+caravel_00069f13_fill_pattern_2_3: 530000 rects
+caravel_00069f13_fill_pattern_0_4: 5370000 rects
+caravel_00069f13_fill_pattern_3_3: 4270000 rects
+caravel_00069f13_fill_pattern_1_1: 4010000 rects
+caravel_00069f13_fill_pattern_3_1: 3690000 rects
+caravel_00069f13_fill_pattern_0_4: 5380000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00069f13_fill_pattern_2_0: 3800000 rects
+caravel_00069f13_fill_pattern_2_3: 540000 rects
+caravel_00069f13_fill_pattern_0_0: 4460000 rects
+caravel_00069f13_fill_pattern_2_6: 4400000 rects
+ Generating output for cell caravel_00069f13_fill_pattern_0_6
+caravel_00069f13_fill_pattern_0_4: 5390000 rects
+caravel_00069f13_fill_pattern_3_4: 5270000 rects
+caravel_00069f13_fill_pattern_4_4: 4620000 rects
+caravel_00069f13_fill_pattern_1_3: 4790000 rects
+caravel_00069f13_fill_pattern_2_3: 550000 rects
+caravel_00069f13_fill_pattern_1_0: 3290000 rects
+caravel_00069f13_fill_pattern_0_4: 5400000 rects
+caravel_00069f13_fill_pattern_0_0: 4470000 rects
+caravel_00069f13_fill_pattern_2_4: 4730000 rects
+caravel_00069f13_fill_pattern_2_0: 3810000 rects
+caravel_00069f13_fill_pattern_0_4: 5410000 rects
+caravel_00069f13_fill_pattern_2_3: 560000 rects
+caravel_00069f13_fill_pattern_0_1: 2720000 rects
+caravel_00069f13_fill_pattern_2_5: 4190000 rects
+caravel_00069f13_fill_pattern_4_4: 4630000 rects
+caravel_00069f13_fill_pattern_3_0: 4430000 rects
+caravel_00069f13_fill_pattern_3_4: 5280000 rects
+caravel_00069f13_fill_pattern_0_4: 5420000 rects
+caravel_00069f13_fill_pattern_1_1: 4020000 rects
+caravel_00069f13_fill_pattern_0_0: 4480000 rects
+caravel_00069f13_fill_pattern_3_3: 4280000 rects
+caravel_00069f13_fill_pattern_2_3: 570000 rects
+caravel_00069f13_fill_pattern_2_0: 3820000 rects
+caravel_00069f13_fill_pattern_0_4: 5430000 rects
+caravel_00069f13_fill_pattern_2_1: 3780000 rects
+caravel_00069f13_fill_pattern_3_1: 3700000 rects
+caravel_00069f13_fill_pattern_4_4: 4640000 rects
+caravel_00069f13_fill_pattern_2_3: 580000 rects
+caravel_00069f13_fill_pattern_0_4: 5440000 rects
+caravel_00069f13_fill_pattern_2_6: 4410000 rects
+caravel_00069f13_fill_pattern_1_2: 4310000 rects
+caravel_00069f13_fill_pattern_0_0: 4490000 rects
+caravel_00069f13_fill_pattern_3_4: 5290000 rects
+caravel_00069f13_fill_pattern_1_0: 3300000 rects
+caravel_00069f13_fill_pattern_0_4: 5450000 rects
+caravel_00069f13_fill_pattern_2_0: 3830000 rects
+caravel_00069f13_fill_pattern_2_2: 4820000 rects
+caravel_00069f13_fill_pattern_2_3: 590000 rects
+caravel_00069f13_fill_pattern_2_4: 4740000 rects
+caravel_00069f13_fill_pattern_1_5: 4820000 rects
+caravel_00069f13_fill_pattern_0_0: 4500000 rects
+caravel_00069f13_fill_pattern_0_4: 5460000 rects
+caravel_00069f13_fill_pattern_4_4: 4650000 rects
+caravel_00069f13_fill_pattern_1_1: 4030000 rects
+caravel_00069f13_fill_pattern_2_3: 600000 rects
+caravel_00069f13_fill_pattern_0_1: 2730000 rects
+caravel_00069f13_fill_pattern_3_4: 5300000 rects
+caravel_00069f13_fill_pattern_0_4: 5470000 rects
+caravel_00069f13_fill_pattern_3_0: 4440000 rects
+caravel_00069f13_fill_pattern_3_1: 3710000 rects
+caravel_00069f13_fill_pattern_2_0: 3840000 rects
+caravel_00069f13_fill_pattern_0_0: 4510000 rects
+caravel_00069f13_fill_pattern_2_5: 4200000 rects
+caravel_00069f13_fill_pattern_1_3: 4800000 rects
+caravel_00069f13_fill_pattern_0_4: 5480000 rects
+caravel_00069f13_fill_pattern_4_4: 4660000 rects
+caravel_00069f13_fill_pattern_2_3: 610000 rects
+caravel_00069f13_fill_pattern_2_1: 3790000 rects
+caravel_00069f13_fill_pattern_0_0: 4520000 rects
+caravel_00069f13_fill_pattern_0_4: 5490000 rects
+caravel_00069f13_fill_pattern_2_6: 4420000 rects
+caravel_00069f13_fill_pattern_3_4: 5310000 rects
+caravel_00069f13_fill_pattern_2_3: 620000 rects
+caravel_00069f13_fill_pattern_2_0: 3850000 rects
+caravel_00069f13_fill_pattern_4_4: 4670000 rects
+caravel_00069f13_fill_pattern_0_0: 4530000 rects
+caravel_00069f13_fill_pattern_3_1: 3720000 rects
+caravel_00069f13_fill_pattern_4_4: 4680000 rects
+caravel_00069f13_fill_pattern_3_3: 4290000 rects
+caravel_00069f13_fill_pattern_1_0: 3310000 rects
+caravel_00069f13_fill_pattern_0_0: 4540000 rects
+caravel_00069f13_fill_pattern_2_3: 630000 rects
+caravel_00069f13_fill_pattern_0_4: 5500000 rects
+caravel_00069f13_fill_pattern_2_4: 4750000 rects
+caravel_00069f13_fill_pattern_1_1: 4040000 rects
+caravel_00069f13_fill_pattern_0_1: 2740000 rects
+caravel_00069f13_fill_pattern_4_4: 4690000 rects
+caravel_00069f13_fill_pattern_0_0: 4550000 rects
+caravel_00069f13_fill_pattern_3_4: 5320000 rects
+caravel_00069f13_fill_pattern_2_0: 3860000 rects
+caravel_00069f13_fill_pattern_3_0: 4450000 rects
+caravel_00069f13_fill_pattern_2_3: 640000 rects
+caravel_00069f13_fill_pattern_4_4: 4700000 rects
+caravel_00069f13_fill_pattern_0_0: 4560000 rects
+caravel_00069f13_fill_pattern_2_5: 4210000 rects
+caravel_00069f13_fill_pattern_1_2: 4320000 rects
+caravel_00069f13_fill_pattern_4_4: 4710000 rects
+caravel_00069f13_fill_pattern_2_3: 650000 rects
+caravel_00069f13_fill_pattern_2_1: 3800000 rects
+caravel_00069f13_fill_pattern_0_0: 4570000 rects
+caravel_00069f13_fill_pattern_2_6: 4430000 rects
+caravel_00069f13_fill_pattern_2_0: 3870000 rects
+caravel_00069f13_fill_pattern_3_4: 5330000 rects
+caravel_00069f13_fill_pattern_4_4: 4720000 rects
+caravel_00069f13_fill_pattern_1_1: 4050000 rects
+caravel_00069f13_fill_pattern_3_3: 4300000 rects
+caravel_00069f13_fill_pattern_0_0: 4580000 rects
+caravel_00069f13_fill_pattern_1_0: 3320000 rects
+caravel_00069f13_fill_pattern_2_3: 660000 rects
+caravel_00069f13_fill_pattern_0_4: 5510000 rects
+caravel_00069f13_fill_pattern_1_3: 4810000 rects
+caravel_00069f13_fill_pattern_0_0: 4590000 rects
+caravel_00069f13_fill_pattern_0_1: 2750000 rects
+caravel_00069f13_fill_pattern_2_0: 3880000 rects
+caravel_00069f13_fill_pattern_2_3: 670000 rects
+caravel_00069f13_fill_pattern_2_4: 4760000 rects
+caravel_00069f13_fill_pattern_3_4: 5340000 rects
+caravel_00069f13_fill_pattern_0_0: 4600000 rects
+caravel_00069f13_fill_pattern_3_0: 4460000 rects
+caravel_00069f13_fill_pattern_0_4: 5520000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00069f13_fill_pattern_4_4: 4730000 rects
+caravel_00069f13_fill_pattern_2_3: 680000 rects
+caravel_00069f13_fill_pattern_0_0: 4610000 rects
+caravel_00069f13_fill_pattern_2_1: 3810000 rects
+ Generating output for cell caravel_00069f13_fill_pattern_1_6
+caravel_00069f13_fill_pattern_1_1: 4060000 rects
+caravel_00069f13_fill_pattern_2_0: 3890000 rects
+caravel_00069f13_fill_pattern_0_0: 4620000 rects
+caravel_00069f13_fill_pattern_3_4: 5350000 rects
+caravel_00069f13_fill_pattern_2_3: 690000 rects
+caravel_00069f13_fill_pattern_3_1: 3730000 rects
+caravel_00069f13_fill_pattern_3_3: 4310000 rects
+caravel_00069f13_fill_pattern_2_5: 4220000 rects
+caravel_00069f13_fill_pattern_2_6: 4440000 rects
+caravel_00069f13_fill_pattern_0_4: 5530000 rects
+caravel_00069f13_fill_pattern_1_0: 3330000 rects
+caravel_00069f13_fill_pattern_2_2: 4830000 rects
+caravel_00069f13_fill_pattern_0_0: 4630000 rects
+caravel_00069f13_fill_pattern_0_1: 2760000 rects
+caravel_00069f13_fill_pattern_2_3: 700000 rects
+caravel_00069f13_fill_pattern_0_0: 4640000 rects
+caravel_00069f13_fill_pattern_4_4: 4740000 rects
+caravel_00069f13_fill_pattern_2_0: 3900000 rects
+caravel_00069f13_fill_pattern_3_4: 5360000 rects
+caravel_00069f13_fill_pattern_2_4: 4770000 rects
+caravel_00069f13_fill_pattern_2_3: 710000 rects
+caravel_00069f13_fill_pattern_0_0: 4650000 rects
+caravel_00069f13_fill_pattern_1_2: 4330000 rects
+caravel_00069f13_fill_pattern_0_4: 5540000 rects
+caravel_00069f13_fill_pattern_3_0: 4470000 rects
+caravel_00069f13_fill_pattern_1_0: 3340000 rects
+caravel_00069f13_fill_pattern_0_0: 4660000 rects
+caravel_00069f13_fill_pattern_2_3: 720000 rects
+caravel_00069f13_fill_pattern_1_1: 4070000 rects
+caravel_00069f13_fill_pattern_2_1: 3820000 rects
+caravel_00069f13_fill_pattern_1_3: 4820000 rects
+caravel_00069f13_fill_pattern_3_3: 4320000 rects
+caravel_00069f13_fill_pattern_2_0: 3910000 rects
+caravel_00069f13_fill_pattern_3_4: 5370000 rects
+caravel_00069f13_fill_pattern_0_0: 4670000 rects
+caravel_00069f13_fill_pattern_0_4: 5550000 rects
+caravel_00069f13_fill_pattern_2_6: 4450000 rects
+caravel_00069f13_fill_pattern_2_5: 4230000 rects
+caravel_00069f13_fill_pattern_2_3: 730000 rects
+caravel_00069f13_fill_pattern_0_1: 2770000 rects
+caravel_00069f13_fill_pattern_0_0: 4680000 rects
+caravel_00069f13_fill_pattern_4_4: 4750000 rects
+caravel_00069f13_fill_pattern_1_5: 4830000 rects
+caravel_00069f13_fill_pattern_2_0: 3920000 rects
+caravel_00069f13_fill_pattern_2_3: 740000 rects
+caravel_00069f13_fill_pattern_3_1: 3740000 rects
+caravel_00069f13_fill_pattern_3_0: 4480000 rects
+caravel_00069f13_fill_pattern_3_4: 5380000 rects
+caravel_00069f13_fill_pattern_2_4: 4780000 rects
+caravel_00069f13_fill_pattern_0_4: 5560000 rects
+caravel_00069f13_fill_pattern_0_0: 4690000 rects
+caravel_00069f13_fill_pattern_3_3: 4330000 rects
+caravel_00069f13_fill_pattern_2_3: 750000 rects
+caravel_00069f13_fill_pattern_1_0: 3350000 rects
+caravel_00069f13_fill_pattern_2_0: 3930000 rects
+caravel_00069f13_fill_pattern_0_0: 4700000 rects
+caravel_00069f13_fill_pattern_2_1: 3830000 rects
+caravel_00069f13_fill_pattern_3_4: 5390000 rects
+caravel_00069f13_fill_pattern_2_3: 760000 rects
+caravel_00069f13_fill_pattern_3_3: 4340000 rects
+caravel_00069f13_fill_pattern_4_4: 4760000 rects
+caravel_00069f13_fill_pattern_2_6: 4460000 rects
+caravel_00069f13_fill_pattern_1_1: 4080000 rects
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+CIF output style is now "wafflefill(tiled)"
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+ Generating output for cell caravel_00069f13_fill_pattern_4_4
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+ Generating output for cell caravel_00069f13_fill_pattern_0_0
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+CIF output style is now "wafflefill(tiled)"
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+caravel_00069f13_fill_pattern_3_0: 5000000 rects
+caravel_00069f13_fill_pattern_1_1: 4770000 rects
+ Generating output for cell caravel_00069f13_fill_pattern_0_4
+caravel_00069f13_fill_pattern_3_3: 5410000 rects
+caravel_00069f13_fill_pattern_2_5: 4790000 rects
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+CIF output style is now "wafflefill(tiled)"
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+caravel_00069f13_fill_pattern_1_0: 4000000 rects
+caravel_00069f13_fill_pattern_2_0: 5040000 rects
+ Generating output for cell caravel_00069f13_fill_pattern_1_5
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+caravel_00069f13_fill_pattern_0_1: 3740000 rects
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+CIF output style is now "wafflefill(tiled)"
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+ Generating output for cell caravel_00069f13_fill_pattern_1_2
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+caravel_00069f13_fill_pattern_2_5: 5500000 rects
+caravel_00069f13_fill_pattern_2_1: 5090000 rects
+Ended: 11/15/2022 21:24:14
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+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
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+caravel_00069f13_fill_pattern_2_4: 5630000 rects
+caravel_00069f13_fill_pattern_2_1: 5120000 rects
+Processing system .magicrc file
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+caravel_00069f13_fill_pattern_2_1: 5130000 rects
+caravel_00069f13_fill_pattern_2_2: 5240000 rects
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
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+caravel_00069f13_fill_pattern_1_0: 4350000 rects
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+caravel_00069f13_fill_pattern_2_1: 5150000 rects
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+Input style sky130(vendor): scaleFactor=2, multiplier=2
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+caravel_00069f13_fill_pattern_3_1: 5180000 rects
+caravel_00069f13_fill_pattern_2_1: 5260000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+caravel_00069f13_fill_pattern_1_0: 4380000 rects
+Scaled tech values by 2 / 1 to match internal grid scaling
+caravel_00069f13_fill_pattern_2_0: 5640000 rects
+Loading sky130A Device Generator Menu ...
+caravel_00069f13_fill_pattern_3_0: 5950000 rects
+caravel_00069f13_fill_pattern_1_1: 5420000 rects
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
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+caravel_00069f13_fill_pattern_2_5: 5660000 rects
+caravel_00069f13_fill_pattern_4_1: 190000 rects
+Ended: 11/15/2022 21:24:15
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+caravel_00069f13_fill_pattern_2_2: 5430000 rects
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+caravel_00069f13_fill_pattern_3_0: 6060000 rects
+caravel_00069f13_fill_pattern_2_2: 5460000 rects
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
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+caravel_00069f13_fill_pattern_4_1: 230000 rects
+caravel_00069f13_fill_pattern_0_1: 4520000 rects
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+caravel_00069f13_fill_pattern_4_1: 240000 rects
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+caravel_00069f13_fill_pattern_2_1: 5310000 rects
+caravel_00069f13_fill_pattern_4_1: 250000 rects
+caravel_00069f13_fill_pattern_1_1: 5530000 rects
+Processing system .magicrc file
+caravel_00069f13_fill_pattern_2_4: 5720000 rects
+caravel_00069f13_fill_pattern_3_1: 5220000 rects
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_00069f13_fill_pattern_1_0: 4450000 rects
+caravel_00069f13_fill_pattern_2_2: 5490000 rects
+caravel_00069f13_fill_pattern_4_1: 260000 rects
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+caravel_00069f13_fill_pattern_4_1: 270000 rects
+caravel_00069f13_fill_pattern_2_2: 5500000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
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+caravel_00069f13_fill_pattern_0_1: 4580000 rects
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+caravel_00069f13_fill_pattern_1_1: 5560000 rects
+caravel_00069f13_fill_pattern_2_5: 5720000 rects
+caravel_00069f13_fill_pattern_4_1: 340000 rects
+caravel_00069f13_fill_pattern_0_1: 4590000 rects
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+caravel_00069f13_fill_pattern_2_2: 5550000 rects
+caravel_00069f13_fill_pattern_1_0: 4470000 rects
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+caravel_00069f13_fill_pattern_4_1: 380000 rects
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+caravel_00069f13_fill_pattern_2_0: 5690000 rects
+caravel_00069f13_fill_pattern_1_0: 4480000 rects
+caravel_00069f13_fill_pattern_4_1: 390000 rects
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+caravel_00069f13_fill_pattern_3_0: 6130000 rects
+caravel_00069f13_fill_pattern_1_1: 5580000 rects
+caravel_00069f13_fill_pattern_2_5: 5740000 rects
+caravel_00069f13_fill_pattern_4_1: 400000 rects
+caravel_00069f13_fill_pattern_0_1: 4610000 rects
+caravel_00069f13_fill_pattern_3_4: 5920000 rects
+caravel_00069f13_fill_pattern_2_4: 5750000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
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+caravel_00069f13_fill_pattern_4_1: 410000 rects
+caravel_00069f13_fill_pattern_2_6: 5890000 rects
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+caravel_00069f13_fill_pattern_2_1: 5330000 rects
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
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+caravel_00069f13_fill_pattern_4_1: 420000 rects
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+caravel_00069f13_fill_pattern_0_1: 4620000 rects
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+caravel_00069f13_fill_pattern_0_5: 10000 rects
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+caravel_00069f13_fill_pattern_4_1: 690000 rects
+caravel_00069f13_fill_pattern_2_1: 5360000 rects
+caravel_00069f13_fill_pattern_3_0: 6250000 rects
+caravel_00069f13_fill_pattern_0_5: 220000 rects
+caravel_00069f13_fill_pattern_2_2: 5720000 rects
+caravel_00069f13_fill_pattern_3_3: 5580000 rects
+caravel_00069f13_fill_pattern_2_6: 6000000 rects
+caravel_00069f13_fill_pattern_4_1: 700000 rects
+caravel_00069f13_fill_pattern_2_4: 5790000 rects
+caravel_00069f13_fill_pattern_2_3: 3640000 rects
+caravel_00069f13_fill_pattern_3_4: 6030000 rects
+caravel_00069f13_fill_pattern_4_1: 710000 rects
+caravel_00069f13_fill_pattern_0_5: 230000 rects
+caravel_00069f13_fill_pattern_2_0: 5730000 rects
+caravel_00069f13_fill_pattern_3_4: 6040000 rects
+caravel_00069f13_fill_pattern_3_1: 5270000 rects
+caravel_00069f13_fill_pattern_4_1: 720000 rects
+caravel_00069f13_fill_pattern_3_0: 6260000 rects
+caravel_00069f13_fill_pattern_3_4: 6050000 rects
+caravel_00069f13_fill_pattern_0_5: 240000 rects
+caravel_00069f13_fill_pattern_2_6: 6010000 rects
+caravel_00069f13_fill_pattern_3_4: 6060000 rects
+caravel_00069f13_fill_pattern_4_1: 730000 rects
+caravel_00069f13_fill_pattern_0_5: 250000 rects
+caravel_00069f13_fill_pattern_1_0: 4560000 rects
+caravel_00069f13_fill_pattern_3_4: 6070000 rects
+caravel_00069f13_fill_pattern_4_1: 740000 rects
+caravel_00069f13_fill_pattern_0_5: 260000 rects
+caravel_00069f13_fill_pattern_1_1: 5770000 rects
+caravel_00069f13_fill_pattern_3_0: 6270000 rects
+caravel_00069f13_fill_pattern_4_1: 750000 rects
+caravel_00069f13_fill_pattern_0_5: 270000 rects
+caravel_00069f13_fill_pattern_2_6: 6020000 rects
+caravel_00069f13_fill_pattern_2_4: 5800000 rects
+caravel_00069f13_fill_pattern_4_1: 760000 rects
+caravel_00069f13_fill_pattern_3_3: 5590000 rects
+caravel_00069f13_fill_pattern_2_2: 5730000 rects
+caravel_00069f13_fill_pattern_0_5: 280000 rects
+caravel_00069f13_fill_pattern_2_1: 5370000 rects
+caravel_00069f13_fill_pattern_2_3: 3650000 rects
+caravel_00069f13_fill_pattern_1_0: 4570000 rects
+caravel_00069f13_fill_pattern_0_5: 290000 rects
+caravel_00069f13_fill_pattern_3_0: 6280000 rects
+caravel_00069f13_fill_pattern_4_1: 770000 rects
+caravel_00069f13_fill_pattern_2_6: 6030000 rects
+caravel_00069f13_fill_pattern_0_5: 300000 rects
+caravel_00069f13_fill_pattern_2_0: 5740000 rects
+caravel_00069f13_fill_pattern_4_1: 780000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00069f13_fill_pattern_0_5: 310000 rects
+ Generating output for cell caravel_00069f13_fill_pattern_0_1
+caravel_00069f13_fill_pattern_3_0: 6290000 rects
+caravel_00069f13_fill_pattern_4_1: 790000 rects
+caravel_00069f13_fill_pattern_3_1: 5280000 rects
+caravel_00069f13_fill_pattern_0_5: 320000 rects
+caravel_00069f13_fill_pattern_1_1: 5780000 rects
+caravel_00069f13_fill_pattern_2_6: 6040000 rects
+caravel_00069f13_fill_pattern_2_4: 5810000 rects
+caravel_00069f13_fill_pattern_3_3: 5600000 rects
+caravel_00069f13_fill_pattern_4_1: 800000 rects
+caravel_00069f13_fill_pattern_0_5: 330000 rects
+caravel_00069f13_fill_pattern_1_0: 4580000 rects
+caravel_00069f13_fill_pattern_0_5: 340000 rects
+caravel_00069f13_fill_pattern_4_1: 810000 rects
+caravel_00069f13_fill_pattern_2_3: 3660000 rects
+caravel_00069f13_fill_pattern_0_5: 350000 rects
+caravel_00069f13_fill_pattern_2_6: 6050000 rects
+caravel_00069f13_fill_pattern_4_1: 820000 rects
+caravel_00069f13_fill_pattern_3_0: 6300000 rects
+caravel_00069f13_fill_pattern_2_2: 5740000 rects
+caravel_00069f13_fill_pattern_0_5: 360000 rects
+caravel_00069f13_fill_pattern_4_1: 830000 rects
+caravel_00069f13_fill_pattern_0_5: 370000 rects
+caravel_00069f13_fill_pattern_2_6: 6060000 rects
+caravel_00069f13_fill_pattern_4_1: 840000 rects
+caravel_00069f13_fill_pattern_0_5: 380000 rects
+caravel_00069f13_fill_pattern_1_0: 4590000 rects
+caravel_00069f13_fill_pattern_2_4: 5820000 rects
+caravel_00069f13_fill_pattern_3_3: 5610000 rects
+caravel_00069f13_fill_pattern_2_1: 5380000 rects
+Ended: 11/15/2022 21:24:17
+caravel_00069f13_fill_pattern_2_0: 5750000 rects
+caravel_00069f13_fill_pattern_0_5: 390000 rects
+caravel_00069f13_fill_pattern_4_1: 850000 rects
+caravel_00069f13_fill_pattern_1_1: 5790000 rects
+caravel_00069f13_fill_pattern_3_0: 6310000 rects
+caravel_00069f13_fill_pattern_0_5: 400000 rects
+caravel_00069f13_fill_pattern_3_1: 5290000 rects
+caravel_00069f13_fill_pattern_2_3: 3670000 rects
+caravel_00069f13_fill_pattern_2_6: 6070000 rects
+caravel_00069f13_fill_pattern_4_1: 860000 rects
+caravel_00069f13_fill_pattern_1_3: 5590000 rects
+caravel_00069f13_fill_pattern_0_5: 410000 rects
+caravel_00069f13_fill_pattern_0_5: 420000 rects
+caravel_00069f13_fill_pattern_4_1: 870000 rects
+caravel_00069f13_fill_pattern_3_0: 6320000 rects
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_00069f13_fill_pattern_2_0: 5760000 rects
+caravel_00069f13_fill_pattern_1_0: 4600000 rects
+caravel_00069f13_fill_pattern_2_2: 5750000 rects
+caravel_00069f13_fill_pattern_2_6: 6080000 rects
+caravel_00069f13_fill_pattern_0_5: 430000 rects
+caravel_00069f13_fill_pattern_4_1: 880000 rects
+caravel_00069f13_fill_pattern_3_3: 5620000 rects
+caravel_00069f13_fill_pattern_2_4: 5830000 rects
+caravel_00069f13_fill_pattern_1_1: 5800000 rects
+caravel_00069f13_fill_pattern_0_5: 440000 rects
+caravel_00069f13_fill_pattern_4_1: 890000 rects
+caravel_00069f13_fill_pattern_3_0: 6330000 rects
+caravel_00069f13_fill_pattern_2_0: 5770000 rects
+caravel_00069f13_fill_pattern_0_5: 450000 rects
+Processing system .magicrc file
+caravel_00069f13_fill_pattern_3_3: 5630000 rects
+caravel_00069f13_fill_pattern_2_6: 6090000 rects
+caravel_00069f13_fill_pattern_2_1: 5390000 rects
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_00069f13_fill_pattern_4_1: 900000 rects
+caravel_00069f13_fill_pattern_0_5: 460000 rects
+caravel_00069f13_fill_pattern_2_3: 3680000 rects
+caravel_00069f13_fill_pattern_3_3: 5640000 rects
+caravel_00069f13_fill_pattern_3_1: 5300000 rects
+caravel_00069f13_fill_pattern_3_0: 6340000 rects
+caravel_00069f13_fill_pattern_0_5: 470000 rects
+caravel_00069f13_fill_pattern_4_1: 910000 rects
+caravel_00069f13_fill_pattern_1_0: 4610000 rects
+caravel_00069f13_fill_pattern_3_3: 5650000 rects
+caravel_00069f13_fill_pattern_2_0: 5780000 rects
+caravel_00069f13_fill_pattern_0_5: 480000 rects
+caravel_00069f13_fill_pattern_2_6: 6100000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_00069f13_fill_pattern_3_3: 5660000 rects
+caravel_00069f13_fill_pattern_4_1: 920000 rects
+caravel_00069f13_fill_pattern_2_4: 5840000 rects
+caravel_00069f13_fill_pattern_1_3: 5600000 rects
+caravel_00069f13_fill_pattern_3_0: 6350000 rects
+caravel_00069f13_fill_pattern_0_5: 490000 rects
+caravel_00069f13_fill_pattern_4_1: 930000 rects
+caravel_00069f13_fill_pattern_3_3: 5670000 rects
+caravel_00069f13_fill_pattern_2_6: 6110000 rects
+caravel_00069f13_fill_pattern_0_5: 500000 rects
+caravel_00069f13_fill_pattern_4_1: 940000 rects
+caravel_00069f13_fill_pattern_2_0: 5790000 rects
+caravel_00069f13_fill_pattern_1_0: 4620000 rects
+caravel_00069f13_fill_pattern_3_0: 6360000 rects
+caravel_00069f13_fill_pattern_2_3: 3690000 rects
+caravel_00069f13_fill_pattern_0_5: 510000 rects
+caravel_00069f13_fill_pattern_2_2: 5760000 rects
+caravel_00069f13_fill_pattern_1_1: 5810000 rects
+caravel_00069f13_fill_pattern_2_6: 6120000 rects
+caravel_00069f13_fill_pattern_2_5: 5900000 rects
+caravel_00069f13_fill_pattern_3_1: 5310000 rects
+caravel_00069f13_fill_pattern_3_3: 5680000 rects
+caravel_00069f13_fill_pattern_0_5: 520000 rects
+caravel_00069f13_fill_pattern_2_0: 5800000 rects
+caravel_00069f13_fill_pattern_4_1: 950000 rects
+caravel_00069f13_fill_pattern_2_4: 5850000 rects
+caravel_00069f13_fill_pattern_3_0: 6370000 rects
+caravel_00069f13_fill_pattern_2_1: 5400000 rects
+caravel_00069f13_fill_pattern_0_5: 530000 rects
+caravel_00069f13_fill_pattern_4_1: 960000 rects
+caravel_00069f13_fill_pattern_2_6: 6130000 rects
+caravel_00069f13_fill_pattern_2_0: 5810000 rects
+caravel_00069f13_fill_pattern_0_5: 540000 rects
+caravel_00069f13_fill_pattern_1_0: 4630000 rects
+caravel_00069f13_fill_pattern_4_1: 970000 rects
+caravel_00069f13_fill_pattern_3_0: 6380000 rects
+caravel_00069f13_fill_pattern_0_5: 550000 rects
+caravel_00069f13_fill_pattern_3_3: 5690000 rects
+caravel_00069f13_fill_pattern_2_3: 3700000 rects
+caravel_00069f13_fill_pattern_4_1: 980000 rects
+caravel_00069f13_fill_pattern_0_5: 560000 rects
+caravel_00069f13_fill_pattern_2_6: 6140000 rects
+caravel_00069f13_fill_pattern_0_5: 570000 rects
+caravel_00069f13_fill_pattern_3_1: 5320000 rects
+caravel_00069f13_fill_pattern_3_0: 6390000 rects
+caravel_00069f13_fill_pattern_4_1: 990000 rects
+caravel_00069f13_fill_pattern_2_4: 5860000 rects
+caravel_00069f13_fill_pattern_1_0: 4640000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+caravel_00069f13_fill_pattern_0_5: 580000 rects
+caravel_00069f13_fill_pattern_2_2: 5770000 rects
+caravel_00069f13_fill_pattern_1_1: 5820000 rects
+caravel_00069f13_fill_pattern_2_0: 5820000 rects
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_00069f13_fill_pattern_0_5: 590000 rects
+caravel_00069f13_fill_pattern_2_6: 6150000 rects
+caravel_00069f13_fill_pattern_4_1: 1000000 rects
+caravel_00069f13_fill_pattern_1_3: 5610000 rects
+caravel_00069f13_fill_pattern_3_0: 6400000 rects
+caravel_00069f13_fill_pattern_0_5: 600000 rects
+caravel_00069f13_fill_pattern_3_3: 5700000 rects
+caravel_00069f13_fill_pattern_2_0: 5830000 rects
+caravel_00069f13_fill_pattern_0_5: 610000 rects
+caravel_00069f13_fill_pattern_2_1: 5410000 rects
+caravel_00069f13_fill_pattern_3_2: 10000 rects
+caravel_00069f13_fill_pattern_2_3: 3710000 rects
+caravel_00069f13_fill_pattern_4_1: 1010000 rects
+caravel_00069f13_fill_pattern_2_6: 6160000 rects
+caravel_00069f13_fill_pattern_3_0: 6410000 rects
+caravel_00069f13_fill_pattern_0_5: 620000 rects
+caravel_00069f13_fill_pattern_2_0: 5840000 rects
+caravel_00069f13_fill_pattern_1_0: 4650000 rects
+caravel_00069f13_fill_pattern_2_4: 5870000 rects
+caravel_00069f13_fill_pattern_3_2: 20000 rects
+caravel_00069f13_fill_pattern_4_1: 1020000 rects
+caravel_00069f13_fill_pattern_3_4: 6080000 rects
+caravel_00069f13_fill_pattern_0_5: 630000 rects
+caravel_00069f13_fill_pattern_3_1: 5330000 rects
+caravel_00069f13_fill_pattern_0_5: 640000 rects
+caravel_00069f13_fill_pattern_4_1: 1030000 rects
+caravel_00069f13_fill_pattern_2_6: 6170000 rects
+caravel_00069f13_fill_pattern_2_0: 5850000 rects
+caravel_00069f13_fill_pattern_3_2: 30000 rects
+caravel_00069f13_fill_pattern_0_5: 650000 rects
+caravel_00069f13_fill_pattern_3_3: 5710000 rects
+caravel_00069f13_fill_pattern_1_1: 5830000 rects
+caravel_00069f13_fill_pattern_2_0: 5860000 rects
+caravel_00069f13_fill_pattern_3_0: 6420000 rects
+caravel_00069f13_fill_pattern_0_5: 660000 rects
+caravel_00069f13_fill_pattern_3_2: 40000 rects
+caravel_00069f13_fill_pattern_4_1: 1040000 rects
+caravel_00069f13_fill_pattern_1_3: 5620000 rects
+caravel_00069f13_fill_pattern_2_0: 5870000 rects
+caravel_00069f13_fill_pattern_2_6: 6180000 rects
+caravel_00069f13_fill_pattern_0_5: 670000 rects
+caravel_00069f13_fill_pattern_3_2: 50000 rects
+caravel_00069f13_fill_pattern_2_3: 3720000 rects
+caravel_00069f13_fill_pattern_1_0: 4660000 rects
+caravel_00069f13_fill_pattern_2_2: 5780000 rects
+caravel_00069f13_fill_pattern_2_4: 5880000 rects
+caravel_00069f13_fill_pattern_4_1: 1050000 rects
+caravel_00069f13_fill_pattern_0_5: 680000 rects
+caravel_00069f13_fill_pattern_2_0: 5880000 rects
+caravel_00069f13_fill_pattern_3_2: 60000 rects
+caravel_00069f13_fill_pattern_1_3: 5630000 rects
+caravel_00069f13_fill_pattern_4_1: 1060000 rects
+caravel_00069f13_fill_pattern_3_2: 70000 rects
+caravel_00069f13_fill_pattern_0_5: 690000 rects
+caravel_00069f13_fill_pattern_3_3: 5720000 rects
+caravel_00069f13_fill_pattern_2_0: 5890000 rects
+caravel_00069f13_fill_pattern_2_6: 6190000 rects
+caravel_00069f13_fill_pattern_2_5: 5910000 rects
+caravel_00069f13_fill_pattern_1_3: 5640000 rects
+caravel_00069f13_fill_pattern_2_1: 5420000 rects
+caravel_00069f13_fill_pattern_3_2: 80000 rects
+caravel_00069f13_fill_pattern_3_0: 6430000 rects
+caravel_00069f13_fill_pattern_0_5: 700000 rects
+caravel_00069f13_fill_pattern_3_3: 5730000 rects
+caravel_00069f13_fill_pattern_3_2: 90000 rects
+caravel_00069f13_fill_pattern_3_1: 5340000 rects
+caravel_00069f13_fill_pattern_2_0: 5900000 rects
+caravel_00069f13_fill_pattern_4_1: 1070000 rects
+caravel_00069f13_fill_pattern_0_5: 710000 rects
+caravel_00069f13_fill_pattern_3_3: 5740000 rects
+caravel_00069f13_fill_pattern_1_0: 4670000 rects
+caravel_00069f13_fill_pattern_2_6: 6200000 rects
+caravel_00069f13_fill_pattern_1_3: 5650000 rects
+caravel_00069f13_fill_pattern_3_0: 6440000 rects
+caravel_00069f13_fill_pattern_2_0: 5910000 rects
+caravel_00069f13_fill_pattern_3_3: 5750000 rects
+caravel_00069f13_fill_pattern_3_2: 100000 rects
+caravel_00069f13_fill_pattern_0_5: 720000 rects
+caravel_00069f13_fill_pattern_2_4: 5890000 rects
+caravel_00069f13_fill_pattern_4_1: 1080000 rects
+caravel_00069f13_fill_pattern_3_3: 5760000 rects
+caravel_00069f13_fill_pattern_2_0: 5920000 rects
+caravel_00069f13_fill_pattern_3_2: 110000 rects
+caravel_00069f13_fill_pattern_2_3: 3730000 rects
+caravel_00069f13_fill_pattern_0_5: 730000 rects
+caravel_00069f13_fill_pattern_3_0: 6450000 rects
+caravel_00069f13_fill_pattern_2_0: 5930000 rects
+caravel_00069f13_fill_pattern_0_5: 740000 rects
+caravel_00069f13_fill_pattern_2_6: 6210000 rects
+caravel_00069f13_fill_pattern_4_1: 1090000 rects
+caravel_00069f13_fill_pattern_3_2: 120000 rects
+caravel_00069f13_fill_pattern_1_3: 5660000 rects
+caravel_00069f13_fill_pattern_2_0: 5940000 rects
+caravel_00069f13_fill_pattern_1_1: 5840000 rects
+caravel_00069f13_fill_pattern_0_5: 750000 rects
+caravel_00069f13_fill_pattern_3_2: 130000 rects
+caravel_00069f13_fill_pattern_3_0: 6460000 rects
+caravel_00069f13_fill_pattern_2_0: 5950000 rects
+caravel_00069f13_fill_pattern_0_5: 760000 rects
+caravel_00069f13_fill_pattern_2_2: 5790000 rects
+caravel_00069f13_fill_pattern_4_1: 1100000 rects
+caravel_00069f13_fill_pattern_1_0: 4680000 rects
+caravel_00069f13_fill_pattern_2_6: 6220000 rects
+caravel_00069f13_fill_pattern_3_2: 140000 rects
+caravel_00069f13_fill_pattern_2_1: 5430000 rects
+caravel_00069f13_fill_pattern_0_5: 770000 rects
+caravel_00069f13_fill_pattern_1_3: 5670000 rects
+caravel_00069f13_fill_pattern_3_1: 5350000 rects
+caravel_00069f13_fill_pattern_3_0: 6470000 rects
+caravel_00069f13_fill_pattern_4_1: 1110000 rects
+caravel_00069f13_fill_pattern_0_5: 780000 rects
+caravel_00069f13_fill_pattern_2_4: 5900000 rects
+caravel_00069f13_fill_pattern_1_3: 5680000 rects
+caravel_00069f13_fill_pattern_3_2: 150000 rects
+caravel_00069f13_fill_pattern_2_0: 5960000 rects
+caravel_00069f13_fill_pattern_0_5: 790000 rects
+caravel_00069f13_fill_pattern_2_3: 3740000 rects
+caravel_00069f13_fill_pattern_2_6: 6230000 rects
+caravel_00069f13_fill_pattern_3_0: 6480000 rects
+caravel_00069f13_fill_pattern_4_1: 1120000 rects
+caravel_00069f13_fill_pattern_0_5: 800000 rects
+caravel_00069f13_fill_pattern_3_2: 160000 rects
+caravel_00069f13_fill_pattern_1_0: 4690000 rects
+caravel_00069f13_fill_pattern_0_5: 810000 rects
+caravel_00069f13_fill_pattern_3_2: 170000 rects
+caravel_00069f13_fill_pattern_1_3: 5690000 rects
+caravel_00069f13_fill_pattern_3_0: 6490000 rects
+caravel_00069f13_fill_pattern_4_1: 1130000 rects
+caravel_00069f13_fill_pattern_2_5: 5920000 rects
+caravel_00069f13_fill_pattern_0_5: 820000 rects
+caravel_00069f13_fill_pattern_1_1: 5850000 rects
+caravel_00069f13_fill_pattern_3_2: 180000 rects
+caravel_00069f13_fill_pattern_0_5: 830000 rects
+caravel_00069f13_fill_pattern_3_0: 6500000 rects
+caravel_00069f13_fill_pattern_2_6: 6240000 rects
+caravel_00069f13_fill_pattern_4_1: 1140000 rects
+caravel_00069f13_fill_pattern_2_0: 5970000 rects
+caravel_00069f13_fill_pattern_3_2: 190000 rects
+caravel_00069f13_fill_pattern_0_5: 840000 rects
+caravel_00069f13_fill_pattern_1_0: 4700000 rects
+Ended: 11/15/2022 21:24:19
+caravel_00069f13_fill_pattern_2_1: 5440000 rects
+caravel_00069f13_fill_pattern_2_4: 5910000 rects
+caravel_00069f13_fill_pattern_3_2: 200000 rects
+caravel_00069f13_fill_pattern_3_0: 6510000 rects
+caravel_00069f13_fill_pattern_0_5: 850000 rects
+caravel_00069f13_fill_pattern_2_3: 3750000 rects
+caravel_00069f13_fill_pattern_3_1: 5360000 rects
+caravel_00069f13_fill_pattern_4_1: 1150000 rects
+caravel_00069f13_fill_pattern_2_6: 6250000 rects
+caravel_00069f13_fill_pattern_0_5: 860000 rects
+caravel_00069f13_fill_pattern_3_2: 210000 rects
+caravel_00069f13_fill_pattern_2_2: 5800000 rects
+caravel_00069f13_fill_pattern_3_0: 6520000 rects
+caravel_00069f13_fill_pattern_4_1: 1160000 rects
+caravel_00069f13_fill_pattern_0_5: 870000 rects
+caravel_00069f13_fill_pattern_1_0: 4710000 rects
+caravel_00069f13_fill_pattern_3_2: 220000 rects
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_00069f13_fill_pattern_2_0: 5980000 rects
+caravel_00069f13_fill_pattern_0_5: 880000 rects
+caravel_00069f13_fill_pattern_2_6: 6260000 rects
+caravel_00069f13_fill_pattern_3_0: 6530000 rects
+caravel_00069f13_fill_pattern_3_2: 230000 rects
+caravel_00069f13_fill_pattern_4_1: 1170000 rects
+caravel_00069f13_fill_pattern_0_5: 890000 rects
+caravel_00069f13_fill_pattern_3_2: 240000 rects
+caravel_00069f13_fill_pattern_1_1: 5860000 rects
+caravel_00069f13_fill_pattern_0_5: 900000 rects
+caravel_00069f13_fill_pattern_4_1: 1180000 rects
+caravel_00069f13_fill_pattern_3_0: 6540000 rects
+Processing system .magicrc file
+caravel_00069f13_fill_pattern_3_2: 250000 rects
+caravel_00069f13_fill_pattern_1_0: 4720000 rects
+Sourcing design .magicrc for technology sky130A ...
+caravel_00069f13_fill_pattern_2_6: 6270000 rects
+2 Magic internal units = 1 Lambda
+caravel_00069f13_fill_pattern_3_1: 5370000 rects
+caravel_00069f13_fill_pattern_2_3: 3760000 rects
+caravel_00069f13_fill_pattern_2_1: 5450000 rects
+caravel_00069f13_fill_pattern_0_5: 910000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00069f13_fill_pattern_3_2: 260000 rects
+caravel_00069f13_fill_pattern_4_1: 1190000 rects
+caravel_00069f13_fill_pattern_2_4: 5920000 rects
+caravel_00069f13_fill_pattern_3_0: 6550000 rects
+ Generating output for cell caravel_00069f13_fill_pattern_3_4
+caravel_00069f13_fill_pattern_2_5: 5930000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_00069f13_fill_pattern_3_2: 270000 rects
+caravel_00069f13_fill_pattern_0_5: 920000 rects
+caravel_00069f13_fill_pattern_2_0: 5990000 rects
+caravel_00069f13_fill_pattern_2_6: 6280000 rects
+caravel_00069f13_fill_pattern_4_1: 1200000 rects
+caravel_00069f13_fill_pattern_3_1: 5380000 rects
+caravel_00069f13_fill_pattern_3_2: 280000 rects
+caravel_00069f13_fill_pattern_3_0: 6560000 rects
+caravel_00069f13_fill_pattern_3_1: 5390000 rects
+caravel_00069f13_fill_pattern_0_5: 930000 rects
+caravel_00069f13_fill_pattern_3_2: 290000 rects
+caravel_00069f13_fill_pattern_4_1: 1210000 rects
+caravel_00069f13_fill_pattern_3_0: 6570000 rects
+caravel_00069f13_fill_pattern_0_5: 940000 rects
+caravel_00069f13_fill_pattern_3_2: 300000 rects
+caravel_00069f13_fill_pattern_3_1: 5400000 rects
+caravel_00069f13_fill_pattern_2_6: 6290000 rects
+caravel_00069f13_fill_pattern_1_0: 4730000 rects
+caravel_00069f13_fill_pattern_2_3: 3770000 rects
+caravel_00069f13_fill_pattern_2_2: 5810000 rects
+caravel_00069f13_fill_pattern_0_5: 950000 rects
+caravel_00069f13_fill_pattern_4_1: 1220000 rects
+caravel_00069f13_fill_pattern_3_0: 6580000 rects
+caravel_00069f13_fill_pattern_3_2: 310000 rects
+caravel_00069f13_fill_pattern_1_1: 5870000 rects
+caravel_00069f13_fill_pattern_3_1: 5410000 rects
+caravel_00069f13_fill_pattern_2_4: 5930000 rects
+caravel_00069f13_fill_pattern_0_5: 960000 rects
+caravel_00069f13_fill_pattern_3_0: 6590000 rects
+caravel_00069f13_fill_pattern_3_2: 320000 rects
+caravel_00069f13_fill_pattern_2_0: 6000000 rects
+caravel_00069f13_fill_pattern_4_1: 1230000 rects
+caravel_00069f13_fill_pattern_2_6: 6300000 rects
+caravel_00069f13_fill_pattern_0_5: 970000 rects
+caravel_00069f13_fill_pattern_3_0: 6600000 rects
+caravel_00069f13_fill_pattern_3_2: 330000 rects
+caravel_00069f13_fill_pattern_3_1: 5420000 rects
+caravel_00069f13_fill_pattern_2_1: 5460000 rects
+caravel_00069f13_fill_pattern_0_5: 980000 rects
+caravel_00069f13_fill_pattern_3_0: 6610000 rects
+caravel_00069f13_fill_pattern_3_2: 340000 rects
+caravel_00069f13_fill_pattern_4_1: 1240000 rects
+caravel_00069f13_fill_pattern_3_1: 5430000 rects
+caravel_00069f13_fill_pattern_3_0: 6620000 rects
+caravel_00069f13_fill_pattern_0_5: 990000 rects
+caravel_00069f13_fill_pattern_3_2: 350000 rects
+caravel_00069f13_fill_pattern_2_6: 6310000 rects
+caravel_00069f13_fill_pattern_2_3: 3780000 rects
+caravel_00069f13_fill_pattern_3_0: 6630000 rects
+caravel_00069f13_fill_pattern_1_0: 4740000 rects
+caravel_00069f13_fill_pattern_4_1: 1250000 rects
+caravel_00069f13_fill_pattern_3_2: 360000 rects
+caravel_00069f13_fill_pattern_0_5: 1000000 rects
+caravel_00069f13_fill_pattern_3_0: 6640000 rects
+caravel_00069f13_fill_pattern_2_6: 6320000 rects
+caravel_00069f13_fill_pattern_1_1: 5880000 rects
+caravel_00069f13_fill_pattern_2_0: 6010000 rects
+caravel_00069f13_fill_pattern_3_2: 370000 rects
+caravel_00069f13_fill_pattern_3_1: 5440000 rects
+caravel_00069f13_fill_pattern_2_4: 5940000 rects
+caravel_00069f13_fill_pattern_4_1: 1260000 rects
+caravel_00069f13_fill_pattern_3_0: 6650000 rects
+caravel_00069f13_fill_pattern_0_5: 1010000 rects
+caravel_00069f13_fill_pattern_2_6: 6330000 rects
+caravel_00069f13_fill_pattern_3_2: 380000 rects
+caravel_00069f13_fill_pattern_3_0: 6660000 rects
+caravel_00069f13_fill_pattern_2_6: 6340000 rects
+caravel_00069f13_fill_pattern_0_5: 1020000 rects
+caravel_00069f13_fill_pattern_2_5: 5940000 rects
+caravel_00069f13_fill_pattern_4_1: 1270000 rects
+caravel_00069f13_fill_pattern_3_2: 390000 rects
+caravel_00069f13_fill_pattern_3_0: 6670000 rects
+caravel_00069f13_fill_pattern_2_6: 6350000 rects
+caravel_00069f13_fill_pattern_0_5: 1030000 rects
+caravel_00069f13_fill_pattern_1_0: 4750000 rects
+caravel_00069f13_fill_pattern_3_0: 6680000 rects
+caravel_00069f13_fill_pattern_3_2: 400000 rects
+caravel_00069f13_fill_pattern_2_6: 6360000 rects
+caravel_00069f13_fill_pattern_4_1: 1280000 rects
+caravel_00069f13_fill_pattern_2_1: 5470000 rects
+caravel_00069f13_fill_pattern_2_3: 3790000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+caravel_00069f13_fill_pattern_0_5: 1040000 rects
+caravel_00069f13_fill_pattern_3_1: 5450000 rects
+caravel_00069f13_fill_pattern_3_0: 6690000 rects
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+caravel_00069f13_fill_pattern_2_2: 5820000 rects
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_00069f13_fill_pattern_2_6: 6370000 rects
+caravel_00069f13_fill_pattern_3_2: 410000 rects
+caravel_00069f13_fill_pattern_2_4: 5950000 rects
+caravel_00069f13_fill_pattern_2_0: 6020000 rects
+caravel_00069f13_fill_pattern_0_5: 1050000 rects
+caravel_00069f13_fill_pattern_4_1: 1290000 rects
+caravel_00069f13_fill_pattern_3_0: 6700000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00069f13_fill_pattern_2_6: 6380000 rects
+caravel_00069f13_fill_pattern_3_2: 420000 rects
+caravel_00069f13_fill_pattern_0_5: 1060000 rects
+caravel_00069f13_fill_pattern_3_0: 6710000 rects
+ Generating output for cell caravel_00069f13_fill_pattern_1_3
+caravel_00069f13_fill_pattern_2_6: 6390000 rects
+caravel_00069f13_fill_pattern_3_2: 430000 rects
+caravel_00069f13_fill_pattern_4_1: 1300000 rects
+caravel_00069f13_fill_pattern_1_1: 5890000 rects
+caravel_00069f13_fill_pattern_5_0: 10000 rects
+caravel_00069f13_fill_pattern_3_0: 6720000 rects
+caravel_00069f13_fill_pattern_0_5: 1070000 rects
+caravel_00069f13_fill_pattern_2_6: 6400000 rects
+caravel_00069f13_fill_pattern_3_2: 440000 rects
+caravel_00069f13_fill_pattern_3_0: 6730000 rects
+caravel_00069f13_fill_pattern_4_1: 1310000 rects
+caravel_00069f13_fill_pattern_3_1: 5460000 rects
+caravel_00069f13_fill_pattern_2_6: 6410000 rects
+caravel_00069f13_fill_pattern_0_5: 1080000 rects
+caravel_00069f13_fill_pattern_1_0: 4760000 rects
+caravel_00069f13_fill_pattern_3_2: 450000 rects
+caravel_00069f13_fill_pattern_2_0: 6030000 rects
+caravel_00069f13_fill_pattern_3_0: 6740000 rects
+caravel_00069f13_fill_pattern_2_3: 3800000 rects
+caravel_00069f13_fill_pattern_2_6: 6420000 rects
+caravel_00069f13_fill_pattern_0_5: 1090000 rects
+caravel_00069f13_fill_pattern_3_2: 460000 rects
+caravel_00069f13_fill_pattern_3_0: 6750000 rects
+caravel_00069f13_fill_pattern_4_1: 1320000 rects
+caravel_00069f13_fill_pattern_2_6: 6430000 rects
+caravel_00069f13_fill_pattern_5_0: 20000 rects
+caravel_00069f13_fill_pattern_2_1: 5480000 rects
+caravel_00069f13_fill_pattern_2_4: 5960000 rects
+caravel_00069f13_fill_pattern_3_0: 6760000 rects
+caravel_00069f13_fill_pattern_3_2: 470000 rects
+caravel_00069f13_fill_pattern_0_5: 1100000 rects
+caravel_00069f13_fill_pattern_2_0: 6040000 rects
+caravel_00069f13_fill_pattern_2_6: 6440000 rects
+caravel_00069f13_fill_pattern_3_0: 6770000 rects
+caravel_00069f13_fill_pattern_2_5: 5950000 rects
+caravel_00069f13_fill_pattern_4_1: 1330000 rects
+caravel_00069f13_fill_pattern_3_2: 480000 rects
+caravel_00069f13_fill_pattern_0_5: 1110000 rects
+caravel_00069f13_fill_pattern_2_6: 6450000 rects
+caravel_00069f13_fill_pattern_5_0: 30000 rects
+caravel_00069f13_fill_pattern_3_2: 490000 rects
+caravel_00069f13_fill_pattern_1_0: 4770000 rects
+caravel_00069f13_fill_pattern_0_5: 1120000 rects
+caravel_00069f13_fill_pattern_3_1: 5470000 rects
+caravel_00069f13_fill_pattern_4_1: 1340000 rects
+caravel_00069f13_fill_pattern_3_2: 500000 rects
+caravel_00069f13_fill_pattern_1_1: 5900000 rects
+caravel_00069f13_fill_pattern_2_0: 6050000 rects
+caravel_00069f13_fill_pattern_0_5: 1130000 rects
+caravel_00069f13_fill_pattern_3_2: 510000 rects
+caravel_00069f13_fill_pattern_5_0: 40000 rects
+caravel_00069f13_fill_pattern_4_1: 1350000 rects
+caravel_00069f13_fill_pattern_2_3: 3810000 rects
+caravel_00069f13_fill_pattern_3_2: 520000 rects
+caravel_00069f13_fill_pattern_0_5: 1140000 rects
+caravel_00069f13_fill_pattern_5_0: 50000 rects
+caravel_00069f13_fill_pattern_3_2: 530000 rects
+caravel_00069f13_fill_pattern_1_0: 4780000 rects
+caravel_00069f13_fill_pattern_4_1: 1360000 rects
+caravel_00069f13_fill_pattern_2_2: 5830000 rects
+caravel_00069f13_fill_pattern_2_0: 6060000 rects
+caravel_00069f13_fill_pattern_0_5: 1150000 rects
+caravel_00069f13_fill_pattern_3_2: 540000 rects
+caravel_00069f13_fill_pattern_5_0: 60000 rects
+caravel_00069f13_fill_pattern_2_1: 5490000 rects
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+caravel_00069f13_fill_pattern_3_2: 550000 rects
+caravel_00069f13_fill_pattern_2_4: 5970000 rects
+caravel_00069f13_fill_pattern_4_1: 1370000 rects
+caravel_00069f13_fill_pattern_3_1: 5480000 rects
+caravel_00069f13_fill_pattern_0_5: 1170000 rects
+caravel_00069f13_fill_pattern_3_2: 560000 rects
+caravel_00069f13_fill_pattern_3_0: 6780000 rects
+caravel_00069f13_fill_pattern_5_0: 70000 rects
+caravel_00069f13_fill_pattern_2_0: 6070000 rects
+caravel_00069f13_fill_pattern_3_2: 570000 rects
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+caravel_00069f13_fill_pattern_1_1: 5910000 rects
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+caravel_00069f13_fill_pattern_5_0: 80000 rects
+caravel_00069f13_fill_pattern_1_0: 4790000 rects
+caravel_00069f13_fill_pattern_3_3: 5770000 rects
+caravel_00069f13_fill_pattern_3_2: 580000 rects
+caravel_00069f13_fill_pattern_2_3: 3820000 rects
+caravel_00069f13_fill_pattern_0_5: 1190000 rects
+caravel_00069f13_fill_pattern_4_1: 1390000 rects
+caravel_00069f13_fill_pattern_5_0: 90000 rects
+caravel_00069f13_fill_pattern_3_2: 590000 rects
+caravel_00069f13_fill_pattern_2_0: 6080000 rects
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+caravel_00069f13_fill_pattern_4_1: 1400000 rects
+caravel_00069f13_fill_pattern_3_1: 5490000 rects
+caravel_00069f13_fill_pattern_1_0: 4800000 rects
+caravel_00069f13_fill_pattern_3_2: 610000 rects
+caravel_00069f13_fill_pattern_0_5: 1210000 rects
+caravel_00069f13_fill_pattern_2_0: 6090000 rects
+caravel_00069f13_fill_pattern_5_0: 100000 rects
+caravel_00069f13_fill_pattern_2_1: 5500000 rects
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+caravel_00069f13_fill_pattern_2_4: 5980000 rects
+caravel_00069f13_fill_pattern_0_5: 1220000 rects
+caravel_00069f13_fill_pattern_4_1: 1410000 rects
+caravel_00069f13_fill_pattern_3_2: 630000 rects
+caravel_00069f13_fill_pattern_2_0: 6110000 rects
+caravel_00069f13_fill_pattern_1_0: 4810000 rects
+caravel_00069f13_fill_pattern_0_5: 1230000 rects
+caravel_00069f13_fill_pattern_3_2: 640000 rects
+caravel_00069f13_fill_pattern_5_0: 110000 rects
+caravel_00069f13_fill_pattern_4_1: 1420000 rects
+caravel_00069f13_fill_pattern_2_0: 6120000 rects
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+caravel_00069f13_fill_pattern_2_3: 3830000 rects
+caravel_00069f13_fill_pattern_3_2: 650000 rects
+caravel_00069f13_fill_pattern_2_0: 6130000 rects
+caravel_00069f13_fill_pattern_0_5: 1240000 rects
+caravel_00069f13_fill_pattern_4_1: 1430000 rects
+caravel_00069f13_fill_pattern_3_2: 660000 rects
+caravel_00069f13_fill_pattern_3_1: 5500000 rects
+caravel_00069f13_fill_pattern_1_0: 4820000 rects
+caravel_00069f13_fill_pattern_2_0: 6140000 rects
+caravel_00069f13_fill_pattern_5_0: 120000 rects
+caravel_00069f13_fill_pattern_3_2: 670000 rects
+caravel_00069f13_fill_pattern_2_0: 6150000 rects
+caravel_00069f13_fill_pattern_4_1: 1440000 rects
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+caravel_00069f13_fill_pattern_1_0: 4830000 rects
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+caravel_00069f13_fill_pattern_3_1: 5510000 rects
+caravel_00069f13_fill_pattern_2_3: 3840000 rects
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+caravel_00069f13_fill_pattern_1_0: 4840000 rects
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+caravel_00069f13_fill_pattern_0_5: 1300000 rects
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+caravel_00069f13_fill_pattern_1_0: 4860000 rects
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+caravel_00069f13_fill_pattern_4_1: 1560000 rects
+caravel_00069f13_fill_pattern_5_0: 250000 rects
+caravel_00069f13_fill_pattern_3_3: 5780000 rects
+caravel_00069f13_fill_pattern_0_5: 1370000 rects
+caravel_00069f13_fill_pattern_1_0: 4910000 rects
+caravel_00069f13_fill_pattern_1_1: 5940000 rects
+caravel_00069f13_fill_pattern_3_2: 880000 rects
+caravel_00069f13_fill_pattern_2_0: 6210000 rects
+caravel_00069f13_fill_pattern_2_4: 6070000 rects
+caravel_00069f13_fill_pattern_5_0: 260000 rects
+caravel_00069f13_fill_pattern_2_1: 5550000 rects
+caravel_00069f13_fill_pattern_2_6: 6470000 rects
+caravel_00069f13_fill_pattern_3_2: 890000 rects
+caravel_00069f13_fill_pattern_4_1: 1570000 rects
+caravel_00069f13_fill_pattern_1_0: 4920000 rects
+caravel_00069f13_fill_pattern_0_5: 1380000 rects
+caravel_00069f13_fill_pattern_5_0: 270000 rects
+caravel_00069f13_fill_pattern_3_2: 900000 rects
+caravel_00069f13_fill_pattern_2_0: 6220000 rects
+caravel_00069f13_fill_pattern_2_4: 6080000 rects
+caravel_00069f13_fill_pattern_5_0: 280000 rects
+caravel_00069f13_fill_pattern_3_2: 910000 rects
+caravel_00069f13_fill_pattern_0_5: 1390000 rects
+caravel_00069f13_fill_pattern_2_1: 5560000 rects
+caravel_00069f13_fill_pattern_2_0: 6230000 rects
+caravel_00069f13_fill_pattern_1_0: 4930000 rects
+caravel_00069f13_fill_pattern_2_3: 3880000 rects
+caravel_00069f13_fill_pattern_2_2: 5860000 rects
+caravel_00069f13_fill_pattern_4_1: 1580000 rects
+caravel_00069f13_fill_pattern_3_2: 920000 rects
+caravel_00069f13_fill_pattern_5_0: 290000 rects
+caravel_00069f13_fill_pattern_0_5: 1400000 rects
+caravel_00069f13_fill_pattern_2_0: 6240000 rects
+caravel_00069f13_fill_pattern_2_4: 6090000 rects
+caravel_00069f13_fill_pattern_3_2: 930000 rects
+caravel_00069f13_fill_pattern_2_1: 5570000 rects
+caravel_00069f13_fill_pattern_2_0: 6250000 rects
+caravel_00069f13_fill_pattern_1_0: 4940000 rects
+caravel_00069f13_fill_pattern_5_0: 300000 rects
+caravel_00069f13_fill_pattern_0_5: 1410000 rects
+caravel_00069f13_fill_pattern_2_0: 6260000 rects
+caravel_00069f13_fill_pattern_2_5: 5990000 rects
+caravel_00069f13_fill_pattern_2_4: 6100000 rects
+caravel_00069f13_fill_pattern_5_0: 310000 rects
+caravel_00069f13_fill_pattern_2_1: 5580000 rects
+caravel_00069f13_fill_pattern_3_2: 940000 rects
+caravel_00069f13_fill_pattern_2_0: 6270000 rects
+caravel_00069f13_fill_pattern_1_1: 5950000 rects
+caravel_00069f13_fill_pattern_0_5: 1420000 rects
+caravel_00069f13_fill_pattern_4_1: 1590000 rects
+caravel_00069f13_fill_pattern_1_0: 4950000 rects
+caravel_00069f13_fill_pattern_5_0: 320000 rects
+caravel_00069f13_fill_pattern_2_3: 3890000 rects
+caravel_00069f13_fill_pattern_2_1: 5590000 rects
+caravel_00069f13_fill_pattern_0_5: 1430000 rects
+caravel_00069f13_fill_pattern_3_2: 950000 rects
+caravel_00069f13_fill_pattern_2_4: 6110000 rects
+caravel_00069f13_fill_pattern_1_0: 4960000 rects
+caravel_00069f13_fill_pattern_2_6: 6480000 rects
+caravel_00069f13_fill_pattern_0_5: 1440000 rects
+caravel_00069f13_fill_pattern_3_2: 960000 rects
+caravel_00069f13_fill_pattern_1_0: 4970000 rects
+caravel_00069f13_fill_pattern_2_1: 5600000 rects
+caravel_00069f13_fill_pattern_4_1: 1600000 rects
+caravel_00069f13_fill_pattern_3_2: 970000 rects
+caravel_00069f13_fill_pattern_0_5: 1450000 rects
+caravel_00069f13_fill_pattern_2_4: 6120000 rects
+caravel_00069f13_fill_pattern_2_3: 3900000 rects
+caravel_00069f13_fill_pattern_1_0: 4980000 rects
+caravel_00069f13_fill_pattern_3_2: 980000 rects
+caravel_00069f13_fill_pattern_0_5: 1460000 rects
+caravel_00069f13_fill_pattern_2_0: 6280000 rects
+caravel_00069f13_fill_pattern_2_1: 5610000 rects
+caravel_00069f13_fill_pattern_1_1: 5960000 rects
+caravel_00069f13_fill_pattern_3_2: 990000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00069f13_fill_pattern_2_4: 6130000 rects
+caravel_00069f13_fill_pattern_2_5: 6000000 rects
+caravel_00069f13_fill_pattern_1_0: 4990000 rects
+caravel_00069f13_fill_pattern_0_5: 1470000 rects
+ Generating output for cell caravel_00069f13_fill_pattern_3_1
+caravel_00069f13_fill_pattern_4_1: 1610000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00069f13_fill_pattern_3_2: 1000000 rects
+ Generating output for cell caravel_00069f13_fill_pattern_3_3
+caravel_00069f13_fill_pattern_2_2: 5870000 rects
+caravel_00069f13_fill_pattern_0_5: 1480000 rects
+caravel_00069f13_fill_pattern_3_2: 1010000 rects
+caravel_00069f13_fill_pattern_1_0: 5000000 rects
+caravel_00069f13_fill_pattern_2_4: 6140000 rects
+caravel_00069f13_fill_pattern_0_5: 1490000 rects
+caravel_00069f13_fill_pattern_2_1: 5620000 rects
+caravel_00069f13_fill_pattern_2_3: 3910000 rects
+caravel_00069f13_fill_pattern_4_1: 1620000 rects
+caravel_00069f13_fill_pattern_0_5: 1500000 rects
+caravel_00069f13_fill_pattern_3_2: 1020000 rects
+caravel_00069f13_fill_pattern_2_4: 6150000 rects
+caravel_00069f13_fill_pattern_2_6: 6490000 rects
+caravel_00069f13_fill_pattern_1_0: 5010000 rects
+caravel_00069f13_fill_pattern_0_5: 1510000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00069f13_fill_pattern_3_0: 6810000 rects
+ Generating output for cell caravel_00069f13_fill_pattern_5_0
+caravel_00069f13_fill_pattern_1_1: 5970000 rects
+caravel_00069f13_fill_pattern_3_2: 1030000 rects
+caravel_00069f13_fill_pattern_2_1: 5630000 rects
+caravel_00069f13_fill_pattern_0_5: 1520000 rects
+caravel_00069f13_fill_pattern_4_1: 1630000 rects
+caravel_00069f13_fill_pattern_2_4: 6160000 rects
+caravel_00069f13_fill_pattern_3_2: 1040000 rects
+caravel_00069f13_fill_pattern_2_3: 3920000 rects
+caravel_00069f13_fill_pattern_1_0: 5020000 rects
+caravel_00069f13_fill_pattern_0_5: 1530000 rects
+caravel_00069f13_fill_pattern_3_2: 1050000 rects
+caravel_00069f13_fill_pattern_2_4: 6170000 rects
+caravel_00069f13_fill_pattern_1_0: 5030000 rects
+caravel_00069f13_fill_pattern_2_1: 5640000 rects
+caravel_00069f13_fill_pattern_4_1: 1640000 rects
+caravel_00069f13_fill_pattern_3_2: 1060000 rects
+caravel_00069f13_fill_pattern_0_5: 1540000 rects
+caravel_00069f13_fill_pattern_2_4: 6180000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00069f13_fill_pattern_3_2: 1070000 rects
+caravel_00069f13_fill_pattern_1_1: 5980000 rects
+caravel_00069f13_fill_pattern_1_0: 5040000 rects
+ Generating output for cell caravel_00069f13_fill_pattern_2_0
+caravel_00069f13_fill_pattern_2_5: 6010000 rects
+caravel_00069f13_fill_pattern_2_3: 3930000 rects
+caravel_00069f13_fill_pattern_0_5: 1550000 rects
+caravel_00069f13_fill_pattern_3_2: 1080000 rects
+caravel_00069f13_fill_pattern_2_2: 5880000 rects
+caravel_00069f13_fill_pattern_4_1: 1650000 rects
+caravel_00069f13_fill_pattern_1_0: 5050000 rects
+caravel_00069f13_fill_pattern_3_0: 6820000 rects
+caravel_00069f13_fill_pattern_2_4: 6190000 rects
+caravel_00069f13_fill_pattern_2_1: 5650000 rects
+caravel_00069f13_fill_pattern_3_2: 1090000 rects
+caravel_00069f13_fill_pattern_0_5: 1560000 rects
+caravel_00069f13_fill_pattern_1_0: 5060000 rects
+caravel_00069f13_fill_pattern_2_4: 6200000 rects
+caravel_00069f13_fill_pattern_0_5: 1570000 rects
+caravel_00069f13_fill_pattern_1_0: 5070000 rects
+caravel_00069f13_fill_pattern_3_2: 1100000 rects
+caravel_00069f13_fill_pattern_4_1: 1660000 rects
+caravel_00069f13_fill_pattern_1_1: 5990000 rects
+caravel_00069f13_fill_pattern_2_3: 3940000 rects
+caravel_00069f13_fill_pattern_0_5: 1580000 rects
+caravel_00069f13_fill_pattern_2_6: 6500000 rects
+caravel_00069f13_fill_pattern_2_4: 6210000 rects
+caravel_00069f13_fill_pattern_2_1: 5660000 rects
+caravel_00069f13_fill_pattern_1_0: 5080000 rects
+caravel_00069f13_fill_pattern_0_5: 1590000 rects
+caravel_00069f13_fill_pattern_3_2: 1110000 rects
+caravel_00069f13_fill_pattern_3_0: 6830000 rects
+caravel_00069f13_fill_pattern_2_4: 6220000 rects
+caravel_00069f13_fill_pattern_4_1: 1670000 rects
+caravel_00069f13_fill_pattern_0_5: 1600000 rects
+caravel_00069f13_fill_pattern_1_0: 5090000 rects
+caravel_00069f13_fill_pattern_2_5: 6020000 rects
+caravel_00069f13_fill_pattern_3_2: 1120000 rects
+caravel_00069f13_fill_pattern_0_5: 1610000 rects
+caravel_00069f13_fill_pattern_2_4: 6230000 rects
+caravel_00069f13_fill_pattern_1_1: 6000000 rects
+caravel_00069f13_fill_pattern_1_0: 5100000 rects
+caravel_00069f13_fill_pattern_2_3: 3950000 rects
+caravel_00069f13_fill_pattern_3_2: 1130000 rects
+caravel_00069f13_fill_pattern_4_1: 1680000 rects
+caravel_00069f13_fill_pattern_0_5: 1620000 rects
+caravel_00069f13_fill_pattern_1_1: 6010000 rects
+caravel_00069f13_fill_pattern_1_0: 5110000 rects
+caravel_00069f13_fill_pattern_2_1: 5670000 rects
+caravel_00069f13_fill_pattern_3_2: 1140000 rects
+caravel_00069f13_fill_pattern_2_4: 6240000 rects
+caravel_00069f13_fill_pattern_1_1: 6020000 rects
+caravel_00069f13_fill_pattern_0_5: 1630000 rects
+caravel_00069f13_fill_pattern_1_1: 6030000 rects
+caravel_00069f13_fill_pattern_3_2: 1150000 rects
+caravel_00069f13_fill_pattern_1_0: 5120000 rects
+caravel_00069f13_fill_pattern_0_5: 1640000 rects
+caravel_00069f13_fill_pattern_4_1: 1690000 rects
+caravel_00069f13_fill_pattern_2_2: 5890000 rects
+caravel_00069f13_fill_pattern_2_4: 6250000 rects
+caravel_00069f13_fill_pattern_1_1: 6040000 rects
+caravel_00069f13_fill_pattern_3_2: 1160000 rects
+caravel_00069f13_fill_pattern_0_5: 1650000 rects
+caravel_00069f13_fill_pattern_3_0: 6840000 rects
+caravel_00069f13_fill_pattern_1_0: 5130000 rects
+caravel_00069f13_fill_pattern_2_3: 3960000 rects
+caravel_00069f13_fill_pattern_1_1: 6050000 rects
+caravel_00069f13_fill_pattern_3_2: 1170000 rects
+caravel_00069f13_fill_pattern_0_5: 1660000 rects
+caravel_00069f13_fill_pattern_2_4: 6260000 rects
+caravel_00069f13_fill_pattern_1_0: 5140000 rects
+caravel_00069f13_fill_pattern_2_1: 5680000 rects
+caravel_00069f13_fill_pattern_3_2: 1180000 rects
+caravel_00069f13_fill_pattern_4_1: 1700000 rects
+caravel_00069f13_fill_pattern_2_6: 6510000 rects
+caravel_00069f13_fill_pattern_1_1: 6060000 rects
+caravel_00069f13_fill_pattern_0_5: 1670000 rects
+caravel_00069f13_fill_pattern_3_2: 1190000 rects
+caravel_00069f13_fill_pattern_2_4: 6270000 rects
+caravel_00069f13_fill_pattern_1_0: 5150000 rects
+caravel_00069f13_fill_pattern_0_5: 1680000 rects
+caravel_00069f13_fill_pattern_3_2: 1200000 rects
+caravel_00069f13_fill_pattern_1_1: 6070000 rects
+caravel_00069f13_fill_pattern_2_5: 6030000 rects
+caravel_00069f13_fill_pattern_1_0: 5160000 rects
+caravel_00069f13_fill_pattern_0_5: 1690000 rects
+caravel_00069f13_fill_pattern_2_4: 6280000 rects
+caravel_00069f13_fill_pattern_3_2: 1210000 rects
+caravel_00069f13_fill_pattern_4_1: 1710000 rects
+caravel_00069f13_fill_pattern_2_1: 5690000 rects
+caravel_00069f13_fill_pattern_0_5: 1700000 rects
+caravel_00069f13_fill_pattern_1_0: 5170000 rects
+caravel_00069f13_fill_pattern_3_2: 1220000 rects
+caravel_00069f13_fill_pattern_2_3: 3970000 rects
+caravel_00069f13_fill_pattern_2_4: 6290000 rects
+caravel_00069f13_fill_pattern_0_5: 1710000 rects
+caravel_00069f13_fill_pattern_1_1: 6080000 rects
+caravel_00069f13_fill_pattern_1_0: 5180000 rects
+caravel_00069f13_fill_pattern_3_2: 1230000 rects
+caravel_00069f13_fill_pattern_3_0: 6850000 rects
+caravel_00069f13_fill_pattern_4_1: 1720000 rects
+caravel_00069f13_fill_pattern_0_5: 1720000 rects
+caravel_00069f13_fill_pattern_2_4: 6300000 rects
+caravel_00069f13_fill_pattern_3_2: 1240000 rects
+caravel_00069f13_fill_pattern_1_0: 5190000 rects
+caravel_00069f13_fill_pattern_0_5: 1730000 rects
+caravel_00069f13_fill_pattern_2_1: 5700000 rects
+caravel_00069f13_fill_pattern_3_2: 1250000 rects
+caravel_00069f13_fill_pattern_1_1: 6090000 rects
+caravel_00069f13_fill_pattern_2_4: 6310000 rects
+caravel_00069f13_fill_pattern_2_2: 5900000 rects
+caravel_00069f13_fill_pattern_0_5: 1740000 rects
+caravel_00069f13_fill_pattern_1_0: 5200000 rects
+caravel_00069f13_fill_pattern_2_3: 3980000 rects
+caravel_00069f13_fill_pattern_4_1: 1730000 rects
+caravel_00069f13_fill_pattern_3_2: 1260000 rects
+caravel_00069f13_fill_pattern_0_5: 1750000 rects
+caravel_00069f13_fill_pattern_2_6: 6520000 rects
+caravel_00069f13_fill_pattern_2_4: 6320000 rects
+caravel_00069f13_fill_pattern_1_0: 5210000 rects
+caravel_00069f13_fill_pattern_3_2: 1270000 rects
+caravel_00069f13_fill_pattern_0_5: 1760000 rects
+caravel_00069f13_fill_pattern_1_1: 6100000 rects
+caravel_00069f13_fill_pattern_3_0: 6860000 rects
+caravel_00069f13_fill_pattern_0_5: 1770000 rects
+caravel_00069f13_fill_pattern_3_2: 1280000 rects
+caravel_00069f13_fill_pattern_4_1: 1740000 rects
+caravel_00069f13_fill_pattern_2_1: 5710000 rects
+caravel_00069f13_fill_pattern_2_4: 6330000 rects
+caravel_00069f13_fill_pattern_2_5: 6040000 rects
+caravel_00069f13_fill_pattern_0_5: 1780000 rects
+caravel_00069f13_fill_pattern_3_2: 1290000 rects
+caravel_00069f13_fill_pattern_1_0: 5220000 rects
+caravel_00069f13_fill_pattern_2_3: 3990000 rects
+caravel_00069f13_fill_pattern_2_4: 6340000 rects
+caravel_00069f13_fill_pattern_3_2: 1300000 rects
+caravel_00069f13_fill_pattern_0_5: 1790000 rects
+caravel_00069f13_fill_pattern_1_1: 6110000 rects
+caravel_00069f13_fill_pattern_2_1: 5720000 rects
+caravel_00069f13_fill_pattern_3_2: 1310000 rects
+caravel_00069f13_fill_pattern_0_5: 1800000 rects
+caravel_00069f13_fill_pattern_4_1: 1750000 rects
+caravel_00069f13_fill_pattern_2_1: 5730000 rects
+caravel_00069f13_fill_pattern_2_4: 6350000 rects
+caravel_00069f13_fill_pattern_1_0: 5230000 rects
+caravel_00069f13_fill_pattern_2_1: 5740000 rects
+caravel_00069f13_fill_pattern_3_2: 1320000 rects
+caravel_00069f13_fill_pattern_0_5: 1810000 rects
+caravel_00069f13_fill_pattern_2_1: 5750000 rects
+caravel_00069f13_fill_pattern_2_1: 5760000 rects
+caravel_00069f13_fill_pattern_2_4: 6360000 rects
+caravel_00069f13_fill_pattern_3_2: 1330000 rects
+caravel_00069f13_fill_pattern_0_5: 1820000 rects
+caravel_00069f13_fill_pattern_1_0: 5240000 rects
+caravel_00069f13_fill_pattern_1_1: 6120000 rects
+caravel_00069f13_fill_pattern_2_3: 4000000 rects
+caravel_00069f13_fill_pattern_2_6: 6530000 rects
+caravel_00069f13_fill_pattern_3_0: 6870000 rects
+caravel_00069f13_fill_pattern_4_1: 1760000 rects
+caravel_00069f13_fill_pattern_3_2: 1340000 rects
+caravel_00069f13_fill_pattern_0_5: 1830000 rects
+caravel_00069f13_fill_pattern_2_4: 6370000 rects
+caravel_00069f13_fill_pattern_3_2: 1350000 rects
+caravel_00069f13_fill_pattern_0_5: 1840000 rects
+caravel_00069f13_fill_pattern_3_2: 1360000 rects
+caravel_00069f13_fill_pattern_1_0: 5250000 rects
+caravel_00069f13_fill_pattern_4_1: 1770000 rects
+caravel_00069f13_fill_pattern_1_1: 6130000 rects
+caravel_00069f13_fill_pattern_0_5: 1850000 rects
+caravel_00069f13_fill_pattern_2_4: 6380000 rects
+caravel_00069f13_fill_pattern_2_2: 5910000 rects
+caravel_00069f13_fill_pattern_3_2: 1370000 rects
+caravel_00069f13_fill_pattern_2_3: 4010000 rects
+caravel_00069f13_fill_pattern_0_5: 1860000 rects
+caravel_00069f13_fill_pattern_2_5: 6050000 rects
+caravel_00069f13_fill_pattern_2_1: 5770000 rects
+caravel_00069f13_fill_pattern_3_2: 1380000 rects
+caravel_00069f13_fill_pattern_0_5: 1870000 rects
+caravel_00069f13_fill_pattern_1_0: 5260000 rects
+caravel_00069f13_fill_pattern_1_1: 6140000 rects
+caravel_00069f13_fill_pattern_4_1: 1780000 rects
+caravel_00069f13_fill_pattern_3_2: 1390000 rects
+caravel_00069f13_fill_pattern_3_0: 6880000 rects
+caravel_00069f13_fill_pattern_2_4: 6390000 rects
+caravel_00069f13_fill_pattern_0_5: 1880000 rects
+caravel_00069f13_fill_pattern_1_0: 5270000 rects
+caravel_00069f13_fill_pattern_3_2: 1400000 rects
+caravel_00069f13_fill_pattern_0_5: 1890000 rects
+caravel_00069f13_fill_pattern_2_3: 4020000 rects
+caravel_00069f13_fill_pattern_1_0: 5280000 rects
+caravel_00069f13_fill_pattern_3_2: 1410000 rects
+caravel_00069f13_fill_pattern_2_4: 6400000 rects
+caravel_00069f13_fill_pattern_4_1: 1790000 rects
+caravel_00069f13_fill_pattern_0_5: 1900000 rects
+caravel_00069f13_fill_pattern_1_1: 6150000 rects
+caravel_00069f13_fill_pattern_3_2: 1420000 rects
+caravel_00069f13_fill_pattern_1_0: 5290000 rects
+caravel_00069f13_fill_pattern_0_5: 1910000 rects
+caravel_00069f13_fill_pattern_2_4: 6410000 rects
+caravel_00069f13_fill_pattern_3_2: 1430000 rects
+caravel_00069f13_fill_pattern_4_1: 1800000 rects
+caravel_00069f13_fill_pattern_2_1: 5780000 rects
+caravel_00069f13_fill_pattern_2_5: 6060000 rects
+caravel_00069f13_fill_pattern_0_5: 1920000 rects
+caravel_00069f13_fill_pattern_3_2: 1440000 rects
+caravel_00069f13_fill_pattern_2_3: 4030000 rects
+caravel_00069f13_fill_pattern_2_4: 6420000 rects
+caravel_00069f13_fill_pattern_0_5: 1930000 rects
+caravel_00069f13_fill_pattern_2_6: 6540000 rects
+caravel_00069f13_fill_pattern_1_0: 5300000 rects
+caravel_00069f13_fill_pattern_3_2: 1450000 rects
+caravel_00069f13_fill_pattern_1_1: 6160000 rects
+caravel_00069f13_fill_pattern_4_1: 1810000 rects
+caravel_00069f13_fill_pattern_3_0: 6890000 rects
+caravel_00069f13_fill_pattern_0_5: 1940000 rects
+caravel_00069f13_fill_pattern_2_4: 6430000 rects
+caravel_00069f13_fill_pattern_3_2: 1460000 rects
+caravel_00069f13_fill_pattern_1_1: 6170000 rects
+caravel_00069f13_fill_pattern_0_5: 1950000 rects
+caravel_00069f13_fill_pattern_1_0: 5310000 rects
+caravel_00069f13_fill_pattern_1_1: 6180000 rects
+caravel_00069f13_fill_pattern_2_2: 5920000 rects
+caravel_00069f13_fill_pattern_3_2: 1470000 rects
+caravel_00069f13_fill_pattern_2_4: 6440000 rects
+caravel_00069f13_fill_pattern_0_5: 1960000 rects
+caravel_00069f13_fill_pattern_1_1: 6190000 rects
+caravel_00069f13_fill_pattern_1_1: 6200000 rects
+caravel_00069f13_fill_pattern_4_1: 1820000 rects
+caravel_00069f13_fill_pattern_0_5: 1970000 rects
+caravel_00069f13_fill_pattern_2_1: 5790000 rects
+caravel_00069f13_fill_pattern_3_2: 1480000 rects
+caravel_00069f13_fill_pattern_1_0: 5320000 rects
+caravel_00069f13_fill_pattern_2_4: 6450000 rects
+caravel_00069f13_fill_pattern_2_5: 6070000 rects
+caravel_00069f13_fill_pattern_2_3: 4040000 rects
+caravel_00069f13_fill_pattern_0_5: 1980000 rects
+caravel_00069f13_fill_pattern_3_2: 1490000 rects
+caravel_00069f13_fill_pattern_3_0: 6900000 rects
+caravel_00069f13_fill_pattern_0_5: 1990000 rects
+caravel_00069f13_fill_pattern_1_0: 5330000 rects
+caravel_00069f13_fill_pattern_3_2: 1500000 rects
+caravel_00069f13_fill_pattern_2_4: 6460000 rects
+caravel_00069f13_fill_pattern_0_5: 2000000 rects
+caravel_00069f13_fill_pattern_1_0: 5340000 rects
+caravel_00069f13_fill_pattern_4_1: 1830000 rects
+caravel_00069f13_fill_pattern_3_2: 1510000 rects
+caravel_00069f13_fill_pattern_1_1: 6210000 rects
+caravel_00069f13_fill_pattern_0_5: 2010000 rects
+caravel_00069f13_fill_pattern_1_0: 5350000 rects
+caravel_00069f13_fill_pattern_3_2: 1520000 rects
+caravel_00069f13_fill_pattern_0_5: 2020000 rects
+caravel_00069f13_fill_pattern_2_6: 6550000 rects
+caravel_00069f13_fill_pattern_1_0: 5360000 rects
+caravel_00069f13_fill_pattern_2_4: 6470000 rects
+caravel_00069f13_fill_pattern_3_2: 1530000 rects
+caravel_00069f13_fill_pattern_4_1: 1840000 rects
+caravel_00069f13_fill_pattern_2_3: 4050000 rects
+caravel_00069f13_fill_pattern_0_5: 2030000 rects
+caravel_00069f13_fill_pattern_3_2: 1540000 rects
+caravel_00069f13_fill_pattern_1_0: 5370000 rects
+caravel_00069f13_fill_pattern_3_0: 6910000 rects
+caravel_00069f13_fill_pattern_0_5: 2040000 rects
+caravel_00069f13_fill_pattern_3_2: 1550000 rects
+caravel_00069f13_fill_pattern_1_0: 5380000 rects
+caravel_00069f13_fill_pattern_2_4: 6480000 rects
+caravel_00069f13_fill_pattern_4_1: 1850000 rects
+caravel_00069f13_fill_pattern_3_2: 1560000 rects
+caravel_00069f13_fill_pattern_0_5: 2050000 rects
+caravel_00069f13_fill_pattern_1_0: 5390000 rects
+caravel_00069f13_fill_pattern_2_5: 6080000 rects
+caravel_00069f13_fill_pattern_3_2: 1570000 rects
+caravel_00069f13_fill_pattern_1_0: 5400000 rects
+caravel_00069f13_fill_pattern_0_5: 2060000 rects
+caravel_00069f13_fill_pattern_2_4: 6490000 rects
+caravel_00069f13_fill_pattern_3_2: 1580000 rects
+caravel_00069f13_fill_pattern_1_0: 5410000 rects
+caravel_00069f13_fill_pattern_2_3: 4060000 rects
+caravel_00069f13_fill_pattern_4_1: 1860000 rects
+caravel_00069f13_fill_pattern_3_2: 1590000 rects
+caravel_00069f13_fill_pattern_1_0: 5420000 rects
+caravel_00069f13_fill_pattern_1_1: 6220000 rects
+caravel_00069f13_fill_pattern_3_0: 6920000 rects
+caravel_00069f13_fill_pattern_2_4: 6500000 rects
+caravel_00069f13_fill_pattern_2_2: 5930000 rects
+caravel_00069f13_fill_pattern_2_5: 6090000 rects
+caravel_00069f13_fill_pattern_0_5: 2070000 rects
+caravel_00069f13_fill_pattern_1_0: 5430000 rects
+caravel_00069f13_fill_pattern_3_2: 1600000 rects
+caravel_00069f13_fill_pattern_2_5: 6100000 rects
+caravel_00069f13_fill_pattern_1_0: 5440000 rects
+caravel_00069f13_fill_pattern_2_5: 6110000 rects
+caravel_00069f13_fill_pattern_4_1: 1870000 rects
+caravel_00069f13_fill_pattern_2_4: 6510000 rects
+caravel_00069f13_fill_pattern_1_0: 5450000 rects
+caravel_00069f13_fill_pattern_1_0: 5460000 rects
+caravel_00069f13_fill_pattern_2_6: 6560000 rects
+caravel_00069f13_fill_pattern_2_3: 4070000 rects
+caravel_00069f13_fill_pattern_0_5: 2080000 rects
+caravel_00069f13_fill_pattern_3_2: 1610000 rects
+caravel_00069f13_fill_pattern_1_0: 5470000 rects
+caravel_00069f13_fill_pattern_2_5: 6120000 rects
+caravel_00069f13_fill_pattern_2_4: 6520000 rects
+caravel_00069f13_fill_pattern_3_0: 6930000 rects
+CIF output style is now "wafflefill(tiled)"
+ Generating output for cell caravel_00069f13_fill_pattern_2_1
+caravel_00069f13_fill_pattern_4_1: 1880000 rects
+caravel_00069f13_fill_pattern_2_4: 6530000 rects
+caravel_00069f13_fill_pattern_1_0: 5480000 rects
+caravel_00069f13_fill_pattern_0_5: 2090000 rects
+caravel_00069f13_fill_pattern_2_5: 6130000 rects
+caravel_00069f13_fill_pattern_3_2: 1620000 rects
+caravel_00069f13_fill_pattern_4_1: 1890000 rects
+caravel_00069f13_fill_pattern_2_4: 6540000 rects
+caravel_00069f13_fill_pattern_2_3: 4080000 rects
+caravel_00069f13_fill_pattern_3_0: 6940000 rects
+caravel_00069f13_fill_pattern_1_0: 5490000 rects
+caravel_00069f13_fill_pattern_2_5: 6140000 rects
+caravel_00069f13_fill_pattern_0_5: 2100000 rects
+caravel_00069f13_fill_pattern_2_4: 6550000 rects
+caravel_00069f13_fill_pattern_3_2: 1630000 rects
+caravel_00069f13_fill_pattern_1_0: 5500000 rects
+caravel_00069f13_fill_pattern_3_0: 6950000 rects
+caravel_00069f13_fill_pattern_4_1: 1900000 rects
+caravel_00069f13_fill_pattern_2_2: 5940000 rects
+caravel_00069f13_fill_pattern_2_5: 6150000 rects
+caravel_00069f13_fill_pattern_0_5: 2110000 rects
+caravel_00069f13_fill_pattern_2_4: 6560000 rects
+caravel_00069f13_fill_pattern_2_3: 4090000 rects
+caravel_00069f13_fill_pattern_1_0: 5510000 rects
+caravel_00069f13_fill_pattern_3_0: 6960000 rects
+caravel_00069f13_fill_pattern_4_1: 1910000 rects
+caravel_00069f13_fill_pattern_2_6: 6570000 rects
+caravel_00069f13_fill_pattern_2_4: 6570000 rects
+caravel_00069f13_fill_pattern_2_5: 6160000 rects
+caravel_00069f13_fill_pattern_0_5: 2120000 rects
+caravel_00069f13_fill_pattern_1_0: 5520000 rects
+caravel_00069f13_fill_pattern_3_0: 6970000 rects
+caravel_00069f13_fill_pattern_2_4: 6580000 rects
+caravel_00069f13_fill_pattern_4_1: 1920000 rects
+caravel_00069f13_fill_pattern_2_5: 6170000 rects
+caravel_00069f13_fill_pattern_3_0: 6980000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00069f13_fill_pattern_0_5: 2130000 rects
+caravel_00069f13_fill_pattern_3_2: 1640000 rects
+ Generating output for cell caravel_00069f13_fill_pattern_1_1
+caravel_00069f13_fill_pattern_1_0: 5530000 rects
+caravel_00069f13_fill_pattern_2_5: 6180000 rects
+caravel_00069f13_fill_pattern_2_3: 4100000 rects
+caravel_00069f13_fill_pattern_2_5: 6190000 rects
+caravel_00069f13_fill_pattern_2_4: 6590000 rects
+caravel_00069f13_fill_pattern_3_0: 6990000 rects
+caravel_00069f13_fill_pattern_4_1: 1930000 rects
+caravel_00069f13_fill_pattern_1_0: 5540000 rects
+caravel_00069f13_fill_pattern_0_5: 2140000 rects
+caravel_00069f13_fill_pattern_2_4: 6600000 rects
+caravel_00069f13_fill_pattern_3_0: 7000000 rects
+caravel_00069f13_fill_pattern_1_0: 5550000 rects
+caravel_00069f13_fill_pattern_4_1: 1940000 rects
+caravel_00069f13_fill_pattern_2_3: 4110000 rects
+caravel_00069f13_fill_pattern_3_2: 1650000 rects
+caravel_00069f13_fill_pattern_3_0: 7010000 rects
+caravel_00069f13_fill_pattern_2_4: 6610000 rects
+caravel_00069f13_fill_pattern_2_6: 6580000 rects
+caravel_00069f13_fill_pattern_0_5: 2150000 rects
+caravel_00069f13_fill_pattern_3_0: 7020000 rects
+caravel_00069f13_fill_pattern_1_0: 5560000 rects
+caravel_00069f13_fill_pattern_3_0: 7030000 rects
+caravel_00069f13_fill_pattern_2_4: 6620000 rects
+caravel_00069f13_fill_pattern_4_1: 1950000 rects
+caravel_00069f13_fill_pattern_3_0: 7040000 rects
+caravel_00069f13_fill_pattern_3_0: 7050000 rects
+caravel_00069f13_fill_pattern_3_2: 1660000 rects
+caravel_00069f13_fill_pattern_1_0: 5570000 rects
+caravel_00069f13_fill_pattern_2_2: 5950000 rects
+caravel_00069f13_fill_pattern_3_0: 7060000 rects
+caravel_00069f13_fill_pattern_2_4: 6630000 rects
+caravel_00069f13_fill_pattern_2_3: 4120000 rects
+caravel_00069f13_fill_pattern_3_0: 7070000 rects
+caravel_00069f13_fill_pattern_4_1: 1960000 rects
+caravel_00069f13_fill_pattern_2_5: 6200000 rects
+caravel_00069f13_fill_pattern_3_0: 7080000 rects
+caravel_00069f13_fill_pattern_1_0: 5580000 rects
+caravel_00069f13_fill_pattern_0_5: 2160000 rects
+caravel_00069f13_fill_pattern_2_4: 6640000 rects
+caravel_00069f13_fill_pattern_3_2: 1670000 rects
+caravel_00069f13_fill_pattern_4_1: 1970000 rects
+caravel_00069f13_fill_pattern_1_0: 5590000 rects
+caravel_00069f13_fill_pattern_2_6: 6590000 rects
+caravel_00069f13_fill_pattern_2_4: 6650000 rects
+caravel_00069f13_fill_pattern_0_5: 2170000 rects
+caravel_00069f13_fill_pattern_2_3: 4130000 rects
+caravel_00069f13_fill_pattern_3_0: 7090000 rects
+caravel_00069f13_fill_pattern_1_0: 5600000 rects
+caravel_00069f13_fill_pattern_2_4: 6660000 rects
+caravel_00069f13_fill_pattern_4_1: 1980000 rects
+caravel_00069f13_fill_pattern_3_2: 1680000 rects
+caravel_00069f13_fill_pattern_1_0: 5610000 rects
+caravel_00069f13_fill_pattern_0_5: 2180000 rects
+caravel_00069f13_fill_pattern_2_4: 6670000 rects
+caravel_00069f13_fill_pattern_3_0: 7100000 rects
+caravel_00069f13_fill_pattern_4_1: 1990000 rects
+caravel_00069f13_fill_pattern_2_3: 4140000 rects
+caravel_00069f13_fill_pattern_3_2: 1690000 rects
+caravel_00069f13_fill_pattern_1_0: 5620000 rects
+caravel_00069f13_fill_pattern_2_4: 6680000 rects
+caravel_00069f13_fill_pattern_2_6: 6600000 rects
+caravel_00069f13_fill_pattern_2_5: 6210000 rects
+caravel_00069f13_fill_pattern_4_1: 2000000 rects
+caravel_00069f13_fill_pattern_2_2: 5960000 rects
+caravel_00069f13_fill_pattern_1_0: 5630000 rects
+caravel_00069f13_fill_pattern_2_4: 6690000 rects
+caravel_00069f13_fill_pattern_3_0: 7110000 rects
+caravel_00069f13_fill_pattern_3_2: 1700000 rects
+caravel_00069f13_fill_pattern_0_5: 2190000 rects
+caravel_00069f13_fill_pattern_2_3: 4150000 rects
+caravel_00069f13_fill_pattern_1_0: 5640000 rects
+caravel_00069f13_fill_pattern_2_4: 6700000 rects
+caravel_00069f13_fill_pattern_4_1: 2010000 rects
+caravel_00069f13_fill_pattern_3_0: 7120000 rects
+caravel_00069f13_fill_pattern_0_5: 2200000 rects
+caravel_00069f13_fill_pattern_3_2: 1710000 rects
+caravel_00069f13_fill_pattern_1_0: 5650000 rects
+caravel_00069f13_fill_pattern_2_4: 6710000 rects
+caravel_00069f13_fill_pattern_2_3: 4160000 rects
+caravel_00069f13_fill_pattern_3_0: 7130000 rects
+caravel_00069f13_fill_pattern_4_1: 2020000 rects
+caravel_00069f13_fill_pattern_1_0: 5660000 rects
+caravel_00069f13_fill_pattern_2_4: 6720000 rects
+caravel_00069f13_fill_pattern_3_0: 7140000 rects
+caravel_00069f13_fill_pattern_2_6: 6610000 rects
+caravel_00069f13_fill_pattern_3_2: 1720000 rects
+caravel_00069f13_fill_pattern_1_0: 5670000 rects
+caravel_00069f13_fill_pattern_2_4: 6730000 rects
+caravel_00069f13_fill_pattern_4_1: 2030000 rects
+caravel_00069f13_fill_pattern_3_0: 7150000 rects
+caravel_00069f13_fill_pattern_0_5: 2210000 rects
+caravel_00069f13_fill_pattern_2_3: 4170000 rects
+caravel_00069f13_fill_pattern_3_0: 7160000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00069f13_fill_pattern_1_0: 5680000 rects
+caravel_00069f13_fill_pattern_2_4: 6740000 rects
+ Generating output for cell caravel_00069f13_fill_pattern_2_5
+caravel_00069f13_fill_pattern_3_0: 7170000 rects
+caravel_00069f13_fill_pattern_3_2: 1730000 rects
+caravel_00069f13_fill_pattern_3_0: 7180000 rects
+caravel_00069f13_fill_pattern_0_5: 2220000 rects
+caravel_00069f13_fill_pattern_4_1: 2040000 rects
+caravel_00069f13_fill_pattern_3_0: 7190000 rects
+caravel_00069f13_fill_pattern_2_4: 6750000 rects
+caravel_00069f13_fill_pattern_1_0: 5690000 rects
+caravel_00069f13_fill_pattern_3_0: 7200000 rects
+caravel_00069f13_fill_pattern_3_0: 7210000 rects
+caravel_00069f13_fill_pattern_2_2: 5970000 rects
+caravel_00069f13_fill_pattern_2_6: 6620000 rects
+caravel_00069f13_fill_pattern_2_3: 4180000 rects
+caravel_00069f13_fill_pattern_0_5: 2230000 rects
+caravel_00069f13_fill_pattern_3_2: 1740000 rects
+caravel_00069f13_fill_pattern_4_1: 2050000 rects
+caravel_00069f13_fill_pattern_2_4: 6760000 rects
+caravel_00069f13_fill_pattern_1_0: 5700000 rects
+caravel_00069f13_fill_pattern_2_4: 6770000 rects
+caravel_00069f13_fill_pattern_1_0: 5710000 rects
+caravel_00069f13_fill_pattern_0_5: 2240000 rects
+caravel_00069f13_fill_pattern_3_2: 1750000 rects
+caravel_00069f13_fill_pattern_4_1: 2060000 rects
+caravel_00069f13_fill_pattern_2_3: 4190000 rects
+caravel_00069f13_fill_pattern_2_4: 6780000 rects
+caravel_00069f13_fill_pattern_1_0: 5720000 rects
+caravel_00069f13_fill_pattern_0_5: 2250000 rects
+caravel_00069f13_fill_pattern_3_0: 7220000 rects
+caravel_00069f13_fill_pattern_4_1: 2070000 rects
+caravel_00069f13_fill_pattern_3_2: 1760000 rects
+caravel_00069f13_fill_pattern_2_4: 6790000 rects
+caravel_00069f13_fill_pattern_1_0: 5730000 rects
+caravel_00069f13_fill_pattern_2_3: 4200000 rects
+caravel_00069f13_fill_pattern_2_6: 6630000 rects
+caravel_00069f13_fill_pattern_0_5: 2260000 rects
+caravel_00069f13_fill_pattern_2_4: 6800000 rects
+caravel_00069f13_fill_pattern_3_0: 7230000 rects
+caravel_00069f13_fill_pattern_1_0: 5740000 rects
+caravel_00069f13_fill_pattern_4_1: 2080000 rects
+caravel_00069f13_fill_pattern_3_2: 1770000 rects
+caravel_00069f13_fill_pattern_3_0: 7240000 rects
+caravel_00069f13_fill_pattern_2_4: 6810000 rects
+caravel_00069f13_fill_pattern_0_5: 2270000 rects
+caravel_00069f13_fill_pattern_1_0: 5750000 rects
+caravel_00069f13_fill_pattern_3_0: 7250000 rects
+caravel_00069f13_fill_pattern_4_1: 2090000 rects
+caravel_00069f13_fill_pattern_2_2: 5980000 rects
+caravel_00069f13_fill_pattern_3_2: 1780000 rects
+caravel_00069f13_fill_pattern_3_0: 7260000 rects
+caravel_00069f13_fill_pattern_2_3: 4210000 rects
+caravel_00069f13_fill_pattern_2_4: 6820000 rects
+caravel_00069f13_fill_pattern_3_0: 7270000 rects
+caravel_00069f13_fill_pattern_1_0: 5760000 rects
+caravel_00069f13_fill_pattern_0_5: 2280000 rects
+caravel_00069f13_fill_pattern_2_6: 6640000 rects
+caravel_00069f13_fill_pattern_4_1: 2100000 rects
+caravel_00069f13_fill_pattern_2_4: 6830000 rects
+caravel_00069f13_fill_pattern_3_2: 1790000 rects
+caravel_00069f13_fill_pattern_1_0: 5770000 rects
+caravel_00069f13_fill_pattern_3_0: 7280000 rects
+caravel_00069f13_fill_pattern_0_5: 2290000 rects
+caravel_00069f13_fill_pattern_2_4: 6840000 rects
+caravel_00069f13_fill_pattern_2_3: 4220000 rects
+caravel_00069f13_fill_pattern_4_1: 2110000 rects
+caravel_00069f13_fill_pattern_1_0: 5780000 rects
+caravel_00069f13_fill_pattern_3_2: 1800000 rects
+caravel_00069f13_fill_pattern_2_4: 6850000 rects
+caravel_00069f13_fill_pattern_0_5: 2300000 rects
+caravel_00069f13_fill_pattern_1_0: 5790000 rects
+caravel_00069f13_fill_pattern_4_1: 2120000 rects
+caravel_00069f13_fill_pattern_2_6: 6650000 rects
+caravel_00069f13_fill_pattern_2_4: 6860000 rects
+caravel_00069f13_fill_pattern_1_0: 5800000 rects
+caravel_00069f13_fill_pattern_2_3: 4230000 rects
+caravel_00069f13_fill_pattern_3_2: 1810000 rects
+caravel_00069f13_fill_pattern_2_4: 6870000 rects
+caravel_00069f13_fill_pattern_0_5: 2310000 rects
+caravel_00069f13_fill_pattern_4_1: 2130000 rects
+Ended: 11/15/2022 21:24:27
+caravel_00069f13_fill_pattern_1_0: 5810000 rects
+caravel_00069f13_fill_pattern_3_2: 1820000 rects
+caravel_00069f13_fill_pattern_2_4: 6880000 rects
+caravel_00069f13_fill_pattern_1_0: 5820000 rects
+caravel_00069f13_fill_pattern_0_5: 2320000 rects
+caravel_00069f13_fill_pattern_2_3: 4240000 rects
+caravel_00069f13_fill_pattern_2_6: 6660000 rects
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+caravel_00069f13_fill_pattern_4_1: 2140000 rects
+caravel_00069f13_fill_pattern_2_4: 6890000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00069f13_fill_pattern_3_2: 1830000 rects
+ Generating output for cell caravel_00069f13_fill_pattern_3_0
+caravel_00069f13_fill_pattern_1_0: 5830000 rects
+Processing system .magicrc file
+caravel_00069f13_fill_pattern_0_5: 2330000 rects
+caravel_00069f13_fill_pattern_2_4: 6900000 rects
+caravel_00069f13_fill_pattern_4_1: 2150000 rects
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+caravel_00069f13_fill_pattern_2_2: 5990000 rects
+caravel_00069f13_fill_pattern_1_0: 5840000 rects
+caravel_00069f13_fill_pattern_3_2: 1840000 rects
+caravel_00069f13_fill_pattern_2_3: 4250000 rects
+caravel_00069f13_fill_pattern_2_4: 6910000 rects
+caravel_00069f13_fill_pattern_0_5: 2340000 rects
+caravel_00069f13_fill_pattern_4_1: 2160000 rects
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+caravel_00069f13_fill_pattern_2_6: 6670000 rects
+caravel_00069f13_fill_pattern_1_0: 5850000 rects
+caravel_00069f13_fill_pattern_2_6: 6680000 rects
+caravel_00069f13_fill_pattern_2_4: 6920000 rects
+caravel_00069f13_fill_pattern_3_2: 1850000 rects
+caravel_00069f13_fill_pattern_0_5: 2350000 rects
+caravel_00069f13_fill_pattern_2_6: 6690000 rects
+caravel_00069f13_fill_pattern_1_0: 5860000 rects
+caravel_00069f13_fill_pattern_4_1: 2170000 rects
+caravel_00069f13_fill_pattern_2_4: 6930000 rects
+caravel_00069f13_fill_pattern_2_6: 6700000 rects
+caravel_00069f13_fill_pattern_2_3: 4260000 rects
+caravel_00069f13_fill_pattern_3_2: 1860000 rects
+caravel_00069f13_fill_pattern_0_5: 2360000 rects
+caravel_00069f13_fill_pattern_1_0: 5870000 rects
+caravel_00069f13_fill_pattern_2_4: 6940000 rects
+caravel_00069f13_fill_pattern_4_1: 2180000 rects
+caravel_00069f13_fill_pattern_2_6: 6710000 rects
+caravel_00069f13_fill_pattern_1_0: 5880000 rects
+caravel_00069f13_fill_pattern_2_4: 6950000 rects
+caravel_00069f13_fill_pattern_0_5: 2370000 rects
+caravel_00069f13_fill_pattern_3_2: 1870000 rects
+caravel_00069f13_fill_pattern_2_3: 4270000 rects
+caravel_00069f13_fill_pattern_4_1: 2190000 rects
+caravel_00069f13_fill_pattern_1_0: 5890000 rects
+caravel_00069f13_fill_pattern_2_4: 6960000 rects
+caravel_00069f13_fill_pattern_2_6: 6720000 rects
+caravel_00069f13_fill_pattern_0_5: 2380000 rects
+caravel_00069f13_fill_pattern_3_2: 1880000 rects
+caravel_00069f13_fill_pattern_4_1: 2200000 rects
+caravel_00069f13_fill_pattern_1_0: 5900000 rects
+caravel_00069f13_fill_pattern_2_2: 6000000 rects
+caravel_00069f13_fill_pattern_2_4: 6970000 rects
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/generate_fill_distributed.tcl" from command line.
+caravel_00069f13_fill_pattern_0_5: 2390000 rects
+caravel_00069f13_fill_pattern_2_3: 4280000 rects
+caravel_00069f13_fill_pattern_2_6: 6730000 rects
+caravel_00069f13_fill_pattern_1_0: 5910000 rects
+caravel_00069f13_fill_pattern_3_2: 1890000 rects
+caravel_00069f13_fill_pattern_2_4: 6980000 rects
+caravel_00069f13_fill_pattern_4_1: 2210000 rects
+caravel_00069f13_fill_pattern_0_5: 2400000 rects
+caravel_00069f13_fill_pattern_1_0: 5920000 rects
+caravel_00069f13_fill_pattern_1_4: 10000 rects
+caravel_00069f13_fill_pattern_2_4: 6990000 rects
+caravel_00069f13_fill_pattern_4_1: 2220000 rects
+caravel_00069f13_fill_pattern_3_2: 1900000 rects
+caravel_00069f13_fill_pattern_1_4: 20000 rects
+caravel_00069f13_fill_pattern_1_4: 30000 rects
+caravel_00069f13_fill_pattern_2_4: 7000000 rects
+caravel_00069f13_fill_pattern_0_5: 2410000 rects
+caravel_00069f13_fill_pattern_2_3: 4290000 rects
+caravel_00069f13_fill_pattern_1_4: 40000 rects
+caravel_00069f13_fill_pattern_2_6: 6740000 rects
+caravel_00069f13_fill_pattern_4_1: 2230000 rects
+caravel_00069f13_fill_pattern_1_4: 50000 rects
+caravel_00069f13_fill_pattern_1_0: 5930000 rects
+caravel_00069f13_fill_pattern_3_2: 1910000 rects
+caravel_00069f13_fill_pattern_1_4: 60000 rects
+caravel_00069f13_fill_pattern_2_4: 7010000 rects
+caravel_00069f13_fill_pattern_1_4: 70000 rects
+caravel_00069f13_fill_pattern_0_5: 2420000 rects
+caravel_00069f13_fill_pattern_1_4: 80000 rects
+caravel_00069f13_fill_pattern_4_1: 2240000 rects
+caravel_00069f13_fill_pattern_2_4: 7020000 rects
+caravel_00069f13_fill_pattern_1_4: 90000 rects
+caravel_00069f13_fill_pattern_1_0: 5940000 rects
+caravel_00069f13_fill_pattern_3_2: 1920000 rects
+caravel_00069f13_fill_pattern_1_4: 100000 rects
+caravel_00069f13_fill_pattern_0_5: 2430000 rects
+caravel_00069f13_fill_pattern_2_6: 6750000 rects
+caravel_00069f13_fill_pattern_1_4: 110000 rects
+caravel_00069f13_fill_pattern_4_1: 2250000 rects
+caravel_00069f13_fill_pattern_2_4: 7030000 rects
+caravel_00069f13_fill_pattern_1_4: 120000 rects
+caravel_00069f13_fill_pattern_1_4: 130000 rects
+caravel_00069f13_fill_pattern_3_2: 1930000 rects
+caravel_00069f13_fill_pattern_1_4: 140000 rects
+caravel_00069f13_fill_pattern_1_0: 5950000 rects
+caravel_00069f13_fill_pattern_4_1: 2260000 rects
+caravel_00069f13_fill_pattern_0_5: 2440000 rects
+caravel_00069f13_fill_pattern_2_4: 7040000 rects
+caravel_00069f13_fill_pattern_1_4: 150000 rects
+caravel_00069f13_fill_pattern_2_3: 4300000 rects
+caravel_00069f13_fill_pattern_2_6: 6760000 rects
+caravel_00069f13_fill_pattern_1_4: 160000 rects
+caravel_00069f13_fill_pattern_2_2: 6010000 rects
+caravel_00069f13_fill_pattern_1_0: 5960000 rects
+caravel_00069f13_fill_pattern_2_4: 7050000 rects
+caravel_00069f13_fill_pattern_1_4: 170000 rects
+caravel_00069f13_fill_pattern_4_1: 2270000 rects
+caravel_00069f13_fill_pattern_3_2: 1940000 rects
+caravel_00069f13_fill_pattern_0_5: 2450000 rects
+caravel_00069f13_fill_pattern_1_4: 180000 rects
+caravel_00069f13_fill_pattern_2_4: 7060000 rects
+caravel_00069f13_fill_pattern_2_6: 6770000 rects
+caravel_00069f13_fill_pattern_1_0: 5970000 rects
+caravel_00069f13_fill_pattern_4_1: 2280000 rects
+caravel_00069f13_fill_pattern_1_4: 190000 rects
+caravel_00069f13_fill_pattern_2_6: 6780000 rects
+caravel_00069f13_fill_pattern_3_2: 1950000 rects
+caravel_00069f13_fill_pattern_0_5: 2460000 rects
+caravel_00069f13_fill_pattern_2_6: 6790000 rects
+caravel_00069f13_fill_pattern_2_3: 4310000 rects
+caravel_00069f13_fill_pattern_1_4: 200000 rects
+caravel_00069f13_fill_pattern_2_4: 7070000 rects
+caravel_00069f13_fill_pattern_1_0: 5980000 rects
+caravel_00069f13_fill_pattern_4_1: 2290000 rects
+caravel_00069f13_fill_pattern_1_4: 210000 rects
+caravel_00069f13_fill_pattern_0_5: 2470000 rects
+caravel_00069f13_fill_pattern_2_4: 7080000 rects
+caravel_00069f13_fill_pattern_3_2: 1960000 rects
+caravel_00069f13_fill_pattern_1_0: 5990000 rects
+caravel_00069f13_fill_pattern_1_4: 220000 rects
+caravel_00069f13_fill_pattern_2_2: 6020000 rects
+caravel_00069f13_fill_pattern_0_5: 2480000 rects
+caravel_00069f13_fill_pattern_4_1: 2300000 rects
+caravel_00069f13_fill_pattern_2_4: 7090000 rects
+caravel_00069f13_fill_pattern_1_4: 230000 rects
+caravel_00069f13_fill_pattern_2_3: 4320000 rects
+caravel_00069f13_fill_pattern_1_0: 6000000 rects
+caravel_00069f13_fill_pattern_0_5: 2490000 rects
+caravel_00069f13_fill_pattern_3_2: 1970000 rects
+caravel_00069f13_fill_pattern_2_4: 7100000 rects
+caravel_00069f13_fill_pattern_4_1: 2310000 rects
+caravel_00069f13_fill_pattern_0_5: 2500000 rects
+caravel_00069f13_fill_pattern_1_4: 240000 rects
+caravel_00069f13_fill_pattern_1_0: 6010000 rects
+caravel_00069f13_fill_pattern_1_4: 250000 rects
+caravel_00069f13_fill_pattern_2_4: 7110000 rects
+caravel_00069f13_fill_pattern_0_5: 2510000 rects
+caravel_00069f13_fill_pattern_3_2: 1980000 rects
+caravel_00069f13_fill_pattern_2_6: 6800000 rects
+caravel_00069f13_fill_pattern_1_4: 260000 rects
+caravel_00069f13_fill_pattern_4_1: 2320000 rects
+caravel_00069f13_fill_pattern_2_2: 6030000 rects
+caravel_00069f13_fill_pattern_1_0: 6020000 rects
+caravel_00069f13_fill_pattern_2_3: 4330000 rects
+caravel_00069f13_fill_pattern_1_4: 270000 rects
+caravel_00069f13_fill_pattern_2_2: 6040000 rects
+caravel_00069f13_fill_pattern_2_4: 7120000 rects
+caravel_00069f13_fill_pattern_1_4: 280000 rects
+caravel_00069f13_fill_pattern_0_5: 2520000 rects
+caravel_00069f13_fill_pattern_2_2: 6050000 rects
+caravel_00069f13_fill_pattern_3_2: 1990000 rects
+caravel_00069f13_fill_pattern_1_0: 6030000 rects
+caravel_00069f13_fill_pattern_4_1: 2330000 rects
+caravel_00069f13_fill_pattern_1_4: 290000 rects
+caravel_00069f13_fill_pattern_2_4: 7130000 rects
+caravel_00069f13_fill_pattern_1_4: 300000 rects
+caravel_00069f13_fill_pattern_2_2: 6060000 rects
+caravel_00069f13_fill_pattern_0_5: 2530000 rects
+caravel_00069f13_fill_pattern_1_4: 310000 rects
+caravel_00069f13_fill_pattern_1_0: 6040000 rects
+caravel_00069f13_fill_pattern_3_2: 2000000 rects
+caravel_00069f13_fill_pattern_4_1: 2340000 rects
+caravel_00069f13_fill_pattern_2_4: 7140000 rects
+caravel_00069f13_fill_pattern_1_4: 320000 rects
+caravel_00069f13_fill_pattern_2_3: 4340000 rects
+caravel_00069f13_fill_pattern_2_2: 6070000 rects
+caravel_00069f13_fill_pattern_1_4: 330000 rects
+caravel_00069f13_fill_pattern_1_0: 6050000 rects
+caravel_00069f13_fill_pattern_0_5: 2540000 rects
+caravel_00069f13_fill_pattern_4_1: 2350000 rects
+caravel_00069f13_fill_pattern_1_4: 340000 rects
+caravel_00069f13_fill_pattern_2_2: 6080000 rects
+caravel_00069f13_fill_pattern_2_4: 7150000 rects
+caravel_00069f13_fill_pattern_3_2: 2010000 rects
+caravel_00069f13_fill_pattern_1_4: 350000 rects
+caravel_00069f13_fill_pattern_2_2: 6090000 rects
+caravel_00069f13_fill_pattern_1_0: 6060000 rects
+caravel_00069f13_fill_pattern_1_4: 360000 rects
+caravel_00069f13_fill_pattern_0_5: 2550000 rects
+caravel_00069f13_fill_pattern_2_4: 7160000 rects
+caravel_00069f13_fill_pattern_2_6: 6810000 rects
+caravel_00069f13_fill_pattern_4_1: 2360000 rects
+caravel_00069f13_fill_pattern_1_4: 370000 rects
+caravel_00069f13_fill_pattern_2_2: 6100000 rects
+caravel_00069f13_fill_pattern_2_3: 4350000 rects
+caravel_00069f13_fill_pattern_1_4: 380000 rects
+caravel_00069f13_fill_pattern_3_2: 2020000 rects
+caravel_00069f13_fill_pattern_1_0: 6070000 rects
+caravel_00069f13_fill_pattern_2_4: 7170000 rects
+caravel_00069f13_fill_pattern_0_5: 2560000 rects
+caravel_00069f13_fill_pattern_1_4: 390000 rects
+caravel_00069f13_fill_pattern_4_1: 2370000 rects
+caravel_00069f13_fill_pattern_1_4: 400000 rects
+caravel_00069f13_fill_pattern_2_4: 7180000 rects
+caravel_00069f13_fill_pattern_1_0: 6080000 rects
+caravel_00069f13_fill_pattern_1_4: 410000 rects
+caravel_00069f13_fill_pattern_3_2: 2030000 rects
+caravel_00069f13_fill_pattern_0_5: 2570000 rects
+caravel_00069f13_fill_pattern_4_1: 2380000 rects
+caravel_00069f13_fill_pattern_1_4: 420000 rects
+caravel_00069f13_fill_pattern_2_3: 4360000 rects
+caravel_00069f13_fill_pattern_1_4: 430000 rects
+caravel_00069f13_fill_pattern_2_4: 7190000 rects
+caravel_00069f13_fill_pattern_1_0: 6090000 rects
+caravel_00069f13_fill_pattern_1_4: 440000 rects
+caravel_00069f13_fill_pattern_4_1: 2390000 rects
+caravel_00069f13_fill_pattern_0_5: 2580000 rects
+caravel_00069f13_fill_pattern_3_2: 2040000 rects
+caravel_00069f13_fill_pattern_1_4: 450000 rects
+caravel_00069f13_fill_pattern_2_4: 7200000 rects
+caravel_00069f13_fill_pattern_1_0: 6100000 rects
+caravel_00069f13_fill_pattern_1_4: 460000 rects
+caravel_00069f13_fill_pattern_4_1: 2400000 rects
+caravel_00069f13_fill_pattern_1_4: 470000 rects
+caravel_00069f13_fill_pattern_2_4: 7210000 rects
+caravel_00069f13_fill_pattern_2_3: 4370000 rects
+caravel_00069f13_fill_pattern_0_5: 2590000 rects
+caravel_00069f13_fill_pattern_1_0: 6110000 rects
+caravel_00069f13_fill_pattern_1_4: 480000 rects
+caravel_00069f13_fill_pattern_3_2: 2050000 rects
+CIF output style is now "wafflefill(tiled)"
+ Generating output for cell caravel_00069f13_fill_pattern_2_2
+caravel_00069f13_fill_pattern_1_4: 490000 rects
+caravel_00069f13_fill_pattern_2_4: 7220000 rects
+caravel_00069f13_fill_pattern_4_1: 2410000 rects
+caravel_00069f13_fill_pattern_1_4: 500000 rects
+caravel_00069f13_fill_pattern_1_0: 6120000 rects
+caravel_00069f13_fill_pattern_0_5: 2600000 rects
+caravel_00069f13_fill_pattern_1_4: 510000 rects
+caravel_00069f13_fill_pattern_3_2: 2060000 rects
+caravel_00069f13_fill_pattern_2_4: 7230000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00069f13_fill_pattern_1_4: 520000 rects
+caravel_00069f13_fill_pattern_4_1: 2420000 rects
+ Generating output for cell caravel_00069f13_fill_pattern_2_6
+caravel_00069f13_fill_pattern_1_0: 6130000 rects
+caravel_00069f13_fill_pattern_2_3: 4380000 rects
+caravel_00069f13_fill_pattern_0_5: 2610000 rects
+caravel_00069f13_fill_pattern_1_4: 530000 rects
+caravel_00069f13_fill_pattern_2_4: 7240000 rects
+caravel_00069f13_fill_pattern_1_4: 540000 rects
+caravel_00069f13_fill_pattern_3_2: 2070000 rects
+caravel_00069f13_fill_pattern_4_1: 2430000 rects
+caravel_00069f13_fill_pattern_1_0: 6140000 rects
+caravel_00069f13_fill_pattern_1_4: 550000 rects
+caravel_00069f13_fill_pattern_0_5: 2620000 rects
+caravel_00069f13_fill_pattern_2_4: 7250000 rects
+Ended: 11/15/2022 21:24:30
+caravel_00069f13_fill_pattern_1_4: 560000 rects
+caravel_00069f13_fill_pattern_3_2: 2080000 rects
+caravel_00069f13_fill_pattern_4_1: 2440000 rects
+caravel_00069f13_fill_pattern_1_4: 570000 rects
+caravel_00069f13_fill_pattern_1_0: 6150000 rects
+caravel_00069f13_fill_pattern_2_4: 7260000 rects
+caravel_00069f13_fill_pattern_2_3: 4390000 rects
+caravel_00069f13_fill_pattern_1_4: 580000 rects
+caravel_00069f13_fill_pattern_0_5: 2630000 rects
+caravel_00069f13_fill_pattern_1_4: 590000 rects
+caravel_00069f13_fill_pattern_3_2: 2090000 rects
+caravel_00069f13_fill_pattern_4_1: 2450000 rects
+caravel_00069f13_fill_pattern_1_0: 6160000 rects
+caravel_00069f13_fill_pattern_1_4: 600000 rects
+caravel_00069f13_fill_pattern_2_4: 7270000 rects
+caravel_00069f13_fill_pattern_0_5: 2640000 rects
+caravel_00069f13_fill_pattern_1_4: 610000 rects
+caravel_00069f13_fill_pattern_4_1: 2460000 rects
+caravel_00069f13_fill_pattern_1_4: 620000 rects
+caravel_00069f13_fill_pattern_2_4: 7280000 rects
+caravel_00069f13_fill_pattern_4_1: 2470000 rects
+caravel_00069f13_fill_pattern_1_0: 6170000 rects
+caravel_00069f13_fill_pattern_3_2: 2100000 rects
+caravel_00069f13_fill_pattern_2_3: 4400000 rects
+caravel_00069f13_fill_pattern_1_4: 630000 rects
+caravel_00069f13_fill_pattern_0_5: 2650000 rects
+caravel_00069f13_fill_pattern_4_1: 2480000 rects
+caravel_00069f13_fill_pattern_1_4: 640000 rects
+caravel_00069f13_fill_pattern_2_4: 7290000 rects
+caravel_00069f13_fill_pattern_4_1: 2490000 rects
+caravel_00069f13_fill_pattern_1_4: 650000 rects
+caravel_00069f13_fill_pattern_1_0: 6180000 rects
+caravel_00069f13_fill_pattern_1_4: 660000 rects
+caravel_00069f13_fill_pattern_3_2: 2110000 rects
+caravel_00069f13_fill_pattern_0_5: 2660000 rects
+caravel_00069f13_fill_pattern_4_1: 2500000 rects
+caravel_00069f13_fill_pattern_1_0: 6190000 rects
+caravel_00069f13_fill_pattern_2_4: 7300000 rects
+caravel_00069f13_fill_pattern_1_4: 670000 rects
+caravel_00069f13_fill_pattern_4_1: 2510000 rects
+caravel_00069f13_fill_pattern_1_4: 680000 rects
+caravel_00069f13_fill_pattern_2_3: 4410000 rects
+caravel_00069f13_fill_pattern_1_0: 6200000 rects
+caravel_00069f13_fill_pattern_1_4: 690000 rects
+caravel_00069f13_fill_pattern_0_5: 2670000 rects
+caravel_00069f13_fill_pattern_2_4: 7310000 rects
+caravel_00069f13_fill_pattern_4_1: 2520000 rects
+caravel_00069f13_fill_pattern_3_2: 2120000 rects
+caravel_00069f13_fill_pattern_1_0: 6210000 rects
+caravel_00069f13_fill_pattern_1_4: 700000 rects
+caravel_00069f13_fill_pattern_4_1: 2530000 rects
+caravel_00069f13_fill_pattern_1_4: 710000 rects
+caravel_00069f13_fill_pattern_1_0: 6220000 rects
+caravel_00069f13_fill_pattern_2_4: 7320000 rects
+caravel_00069f13_fill_pattern_1_4: 720000 rects
+caravel_00069f13_fill_pattern_0_5: 2680000 rects
+caravel_00069f13_fill_pattern_4_1: 2540000 rects
+caravel_00069f13_fill_pattern_1_0: 6230000 rects
+caravel_00069f13_fill_pattern_1_4: 730000 rects
+caravel_00069f13_fill_pattern_2_3: 4420000 rects
+caravel_00069f13_fill_pattern_3_2: 2130000 rects
+caravel_00069f13_fill_pattern_4_1: 2550000 rects
+caravel_00069f13_fill_pattern_2_4: 7330000 rects
+caravel_00069f13_fill_pattern_1_4: 740000 rects
+caravel_00069f13_fill_pattern_1_0: 6240000 rects
+caravel_00069f13_fill_pattern_4_1: 2560000 rects
+caravel_00069f13_fill_pattern_1_4: 750000 rects
+caravel_00069f13_fill_pattern_0_5: 2690000 rects
+caravel_00069f13_fill_pattern_1_0: 6250000 rects
+caravel_00069f13_fill_pattern_1_4: 760000 rects
+caravel_00069f13_fill_pattern_2_4: 7340000 rects
+caravel_00069f13_fill_pattern_4_1: 2570000 rects
+caravel_00069f13_fill_pattern_3_2: 2140000 rects
+caravel_00069f13_fill_pattern_1_4: 770000 rects
+caravel_00069f13_fill_pattern_1_0: 6260000 rects
+caravel_00069f13_fill_pattern_2_3: 4430000 rects
+caravel_00069f13_fill_pattern_4_1: 2580000 rects
+caravel_00069f13_fill_pattern_0_5: 2700000 rects
+caravel_00069f13_fill_pattern_1_4: 780000 rects
+caravel_00069f13_fill_pattern_2_4: 7350000 rects
+caravel_00069f13_fill_pattern_1_0: 6270000 rects
+caravel_00069f13_fill_pattern_1_4: 790000 rects
+caravel_00069f13_fill_pattern_4_1: 2590000 rects
+caravel_00069f13_fill_pattern_3_2: 2150000 rects
+caravel_00069f13_fill_pattern_1_4: 800000 rects
+caravel_00069f13_fill_pattern_1_0: 6280000 rects
+caravel_00069f13_fill_pattern_2_4: 7360000 rects
+caravel_00069f13_fill_pattern_1_4: 810000 rects
+caravel_00069f13_fill_pattern_0_5: 2710000 rects
+caravel_00069f13_fill_pattern_4_1: 2600000 rects
+caravel_00069f13_fill_pattern_1_0: 6290000 rects
+caravel_00069f13_fill_pattern_2_3: 4440000 rects
+caravel_00069f13_fill_pattern_1_4: 820000 rects
+caravel_00069f13_fill_pattern_4_1: 2610000 rects
+caravel_00069f13_fill_pattern_1_4: 830000 rects
+caravel_00069f13_fill_pattern_1_0: 6300000 rects
+caravel_00069f13_fill_pattern_2_4: 7370000 rects
+caravel_00069f13_fill_pattern_3_2: 2160000 rects
+caravel_00069f13_fill_pattern_1_4: 840000 rects
+caravel_00069f13_fill_pattern_0_5: 2720000 rects
+caravel_00069f13_fill_pattern_1_0: 6310000 rects
+caravel_00069f13_fill_pattern_4_1: 2620000 rects
+caravel_00069f13_fill_pattern_1_4: 850000 rects
+caravel_00069f13_fill_pattern_1_0: 6320000 rects
+caravel_00069f13_fill_pattern_2_4: 7380000 rects
+caravel_00069f13_fill_pattern_1_4: 860000 rects
+caravel_00069f13_fill_pattern_4_1: 2630000 rects
+caravel_00069f13_fill_pattern_1_0: 6330000 rects
+caravel_00069f13_fill_pattern_1_4: 870000 rects
+caravel_00069f13_fill_pattern_3_2: 2170000 rects
+caravel_00069f13_fill_pattern_1_0: 6340000 rects
+caravel_00069f13_fill_pattern_2_3: 4450000 rects
+caravel_00069f13_fill_pattern_1_4: 880000 rects
+caravel_00069f13_fill_pattern_0_5: 2730000 rects
+caravel_00069f13_fill_pattern_4_1: 2640000 rects
+caravel_00069f13_fill_pattern_1_0: 6350000 rects
+caravel_00069f13_fill_pattern_2_4: 7390000 rects
+caravel_00069f13_fill_pattern_1_4: 890000 rects
+caravel_00069f13_fill_pattern_1_0: 6360000 rects
+caravel_00069f13_fill_pattern_2_4: 7400000 rects
+caravel_00069f13_fill_pattern_4_1: 2650000 rects
+caravel_00069f13_fill_pattern_1_4: 900000 rects
+caravel_00069f13_fill_pattern_1_0: 6370000 rects
+caravel_00069f13_fill_pattern_2_4: 7410000 rects
+caravel_00069f13_fill_pattern_1_4: 910000 rects
+caravel_00069f13_fill_pattern_3_2: 2180000 rects
+caravel_00069f13_fill_pattern_1_0: 6380000 rects
+caravel_00069f13_fill_pattern_2_4: 7420000 rects
+caravel_00069f13_fill_pattern_4_1: 2660000 rects
+caravel_00069f13_fill_pattern_0_5: 2740000 rects
+caravel_00069f13_fill_pattern_1_0: 6390000 rects
+caravel_00069f13_fill_pattern_1_4: 920000 rects
+caravel_00069f13_fill_pattern_2_4: 7430000 rects
+caravel_00069f13_fill_pattern_4_1: 2670000 rects
+caravel_00069f13_fill_pattern_1_0: 6400000 rects
+caravel_00069f13_fill_pattern_2_4: 7440000 rects
+caravel_00069f13_fill_pattern_1_4: 930000 rects
+caravel_00069f13_fill_pattern_2_3: 4460000 rects
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+CIF output style is now "wafflefill(tiled)"
+ Generating output for cell caravel_00069f13_fill_pattern_1_0
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+caravel_00069f13_fill_pattern_3_2: 3300000 rects
+caravel_00069f13_fill_pattern_0_5: 4110000 rects
+caravel_00069f13_fill_pattern_2_4: 7870000 rects
+caravel_00069f13_fill_pattern_4_1: 3600000 rects
+caravel_00069f13_fill_pattern_2_3: 5030000 rects
+caravel_00069f13_fill_pattern_1_4: 2960000 rects
+caravel_00069f13_fill_pattern_0_5: 4120000 rects
+caravel_00069f13_fill_pattern_0_5: 4130000 rects
+caravel_00069f13_fill_pattern_2_4: 7880000 rects
+caravel_00069f13_fill_pattern_2_3: 5040000 rects
+caravel_00069f13_fill_pattern_1_4: 2970000 rects
+caravel_00069f13_fill_pattern_3_2: 3310000 rects
+caravel_00069f13_fill_pattern_0_5: 4140000 rects
+caravel_00069f13_fill_pattern_0_5: 4150000 rects
+caravel_00069f13_fill_pattern_3_2: 3320000 rects
+caravel_00069f13_fill_pattern_3_2: 3330000 rects
+caravel_00069f13_fill_pattern_2_4: 7890000 rects
+caravel_00069f13_fill_pattern_3_2: 3340000 rects
+caravel_00069f13_fill_pattern_0_5: 4160000 rects
+caravel_00069f13_fill_pattern_1_4: 2980000 rects
+caravel_00069f13_fill_pattern_3_2: 3350000 rects
+caravel_00069f13_fill_pattern_2_3: 5050000 rects
+caravel_00069f13_fill_pattern_0_5: 4170000 rects
+caravel_00069f13_fill_pattern_2_4: 7900000 rects
+caravel_00069f13_fill_pattern_0_5: 4180000 rects
+caravel_00069f13_fill_pattern_3_2: 3360000 rects
+caravel_00069f13_fill_pattern_1_4: 2990000 rects
+caravel_00069f13_fill_pattern_3_2: 3370000 rects
+caravel_00069f13_fill_pattern_0_5: 4190000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00069f13_fill_pattern_3_2: 3380000 rects
+ Generating output for cell caravel_00069f13_fill_pattern_4_1
+caravel_00069f13_fill_pattern_2_3: 5060000 rects
+caravel_00069f13_fill_pattern_3_2: 3390000 rects
+caravel_00069f13_fill_pattern_2_4: 7910000 rects
+caravel_00069f13_fill_pattern_0_5: 4200000 rects
+caravel_00069f13_fill_pattern_3_2: 3400000 rects
+caravel_00069f13_fill_pattern_0_5: 4210000 rects
+caravel_00069f13_fill_pattern_2_4: 7920000 rects
+caravel_00069f13_fill_pattern_2_4: 7930000 rects
+caravel_00069f13_fill_pattern_1_4: 3000000 rects
+caravel_00069f13_fill_pattern_0_5: 4220000 rects
+caravel_00069f13_fill_pattern_2_3: 5070000 rects
+caravel_00069f13_fill_pattern_2_4: 7940000 rects
+caravel_00069f13_fill_pattern_0_5: 4230000 rects
+caravel_00069f13_fill_pattern_0_5: 4240000 rects
+caravel_00069f13_fill_pattern_1_4: 3010000 rects
+caravel_00069f13_fill_pattern_2_3: 5080000 rects
+caravel_00069f13_fill_pattern_0_5: 4250000 rects
+caravel_00069f13_fill_pattern_0_5: 4260000 rects
+caravel_00069f13_fill_pattern_0_5: 4270000 rects
+caravel_00069f13_fill_pattern_1_4: 3020000 rects
+caravel_00069f13_fill_pattern_2_3: 5090000 rects
+caravel_00069f13_fill_pattern_0_5: 4280000 rects
+caravel_00069f13_fill_pattern_0_5: 4290000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00069f13_fill_pattern_1_4: 3030000 rects
+ Generating output for cell caravel_00069f13_fill_pattern_3_2
+caravel_00069f13_fill_pattern_0_5: 4300000 rects
+caravel_00069f13_fill_pattern_2_3: 5100000 rects
+caravel_00069f13_fill_pattern_2_4: 7950000 rects
+caravel_00069f13_fill_pattern_0_5: 4310000 rects
+caravel_00069f13_fill_pattern_0_5: 4320000 rects
+caravel_00069f13_fill_pattern_1_4: 3040000 rects
+caravel_00069f13_fill_pattern_2_3: 5110000 rects
+caravel_00069f13_fill_pattern_0_5: 4330000 rects
+caravel_00069f13_fill_pattern_0_5: 4340000 rects
+caravel_00069f13_fill_pattern_0_5: 4350000 rects
+caravel_00069f13_fill_pattern_1_4: 3050000 rects
+caravel_00069f13_fill_pattern_2_3: 5120000 rects
+caravel_00069f13_fill_pattern_0_5: 4360000 rects
+caravel_00069f13_fill_pattern_0_5: 4370000 rects
+caravel_00069f13_fill_pattern_1_4: 3060000 rects
+caravel_00069f13_fill_pattern_0_5: 4380000 rects
+caravel_00069f13_fill_pattern_2_4: 7960000 rects
+caravel_00069f13_fill_pattern_2_3: 5130000 rects
+caravel_00069f13_fill_pattern_0_5: 4390000 rects
+caravel_00069f13_fill_pattern_0_5: 4400000 rects
+caravel_00069f13_fill_pattern_1_4: 3070000 rects
+caravel_00069f13_fill_pattern_0_5: 4410000 rects
+caravel_00069f13_fill_pattern_2_3: 5140000 rects
+caravel_00069f13_fill_pattern_0_5: 4420000 rects
+caravel_00069f13_fill_pattern_0_5: 4430000 rects
+caravel_00069f13_fill_pattern_1_4: 3080000 rects
+caravel_00069f13_fill_pattern_0_5: 4440000 rects
+caravel_00069f13_fill_pattern_2_3: 5150000 rects
+caravel_00069f13_fill_pattern_0_5: 4450000 rects
+caravel_00069f13_fill_pattern_0_5: 4460000 rects
+caravel_00069f13_fill_pattern_0_5: 4470000 rects
+caravel_00069f13_fill_pattern_1_4: 3090000 rects
+caravel_00069f13_fill_pattern_0_5: 4480000 rects
+caravel_00069f13_fill_pattern_0_5: 4490000 rects
+caravel_00069f13_fill_pattern_0_5: 4500000 rects
+caravel_00069f13_fill_pattern_2_3: 5160000 rects
+caravel_00069f13_fill_pattern_0_5: 4510000 rects
+caravel_00069f13_fill_pattern_1_4: 3100000 rects
+caravel_00069f13_fill_pattern_0_5: 4520000 rects
+caravel_00069f13_fill_pattern_0_5: 4530000 rects
+CIF output style is now "wafflefill(tiled)"
+caravel_00069f13_fill_pattern_0_5: 4540000 rects
+ Generating output for cell caravel_00069f13_fill_pattern_2_4
+caravel_00069f13_fill_pattern_0_5: 4550000 rects
+caravel_00069f13_fill_pattern_0_5: 4560000 rects
+caravel_00069f13_fill_pattern_0_5: 4570000 rects
+caravel_00069f13_fill_pattern_2_3: 5170000 rects
+caravel_00069f13_fill_pattern_0_5: 4580000 rects
+caravel_00069f13_fill_pattern_1_4: 3110000 rects
+caravel_00069f13_fill_pattern_0_5: 4590000 rects
+caravel_00069f13_fill_pattern_0_5: 4600000 rects
+caravel_00069f13_fill_pattern_0_5: 4610000 rects
+caravel_00069f13_fill_pattern_0_5: 4620000 rects
+caravel_00069f13_fill_pattern_1_4: 3120000 rects
+caravel_00069f13_fill_pattern_2_3: 5180000 rects
+caravel_00069f13_fill_pattern_0_5: 4630000 rects
+caravel_00069f13_fill_pattern_0_5: 4640000 rects
+caravel_00069f13_fill_pattern_0_5: 4650000 rects
+caravel_00069f13_fill_pattern_1_4: 3130000 rects
+caravel_00069f13_fill_pattern_2_3: 5190000 rects
+caravel_00069f13_fill_pattern_0_5: 4660000 rects
+caravel_00069f13_fill_pattern_0_5: 4670000 rects
+caravel_00069f13_fill_pattern_1_4: 3140000 rects
+caravel_00069f13_fill_pattern_0_5: 4680000 rects
+caravel_00069f13_fill_pattern_2_3: 5200000 rects
+caravel_00069f13_fill_pattern_0_5: 4690000 rects
+caravel_00069f13_fill_pattern_1_4: 3150000 rects
+caravel_00069f13_fill_pattern_0_5: 4700000 rects
+caravel_00069f13_fill_pattern_2_3: 5210000 rects
+caravel_00069f13_fill_pattern_0_5: 4710000 rects
+caravel_00069f13_fill_pattern_0_5: 4720000 rects
+caravel_00069f13_fill_pattern_1_4: 3160000 rects
+caravel_00069f13_fill_pattern_0_5: 4730000 rects
+caravel_00069f13_fill_pattern_2_3: 5220000 rects
+caravel_00069f13_fill_pattern_1_4: 3170000 rects
+caravel_00069f13_fill_pattern_2_3: 5230000 rects
+caravel_00069f13_fill_pattern_1_4: 3180000 rects
+caravel_00069f13_fill_pattern_2_3: 5240000 rects
+caravel_00069f13_fill_pattern_0_5: 4740000 rects
+caravel_00069f13_fill_pattern_1_4: 3190000 rects
+caravel_00069f13_fill_pattern_2_3: 5250000 rects
+caravel_00069f13_fill_pattern_1_4: 3200000 rects
+caravel_00069f13_fill_pattern_2_3: 5260000 rects
+caravel_00069f13_fill_pattern_0_5: 4750000 rects
+caravel_00069f13_fill_pattern_1_4: 3210000 rects
+caravel_00069f13_fill_pattern_2_3: 5270000 rects
+caravel_00069f13_fill_pattern_1_4: 3220000 rects
+caravel_00069f13_fill_pattern_0_5: 4760000 rects
+caravel_00069f13_fill_pattern_2_3: 5280000 rects
+caravel_00069f13_fill_pattern_1_4: 3230000 rects
+caravel_00069f13_fill_pattern_2_3: 5290000 rects
+caravel_00069f13_fill_pattern_1_4: 3240000 rects
+caravel_00069f13_fill_pattern_0_5: 4770000 rects
+caravel_00069f13_fill_pattern_2_3: 5300000 rects
+caravel_00069f13_fill_pattern_1_4: 3250000 rects
+caravel_00069f13_fill_pattern_0_5: 4780000 rects
+caravel_00069f13_fill_pattern_2_3: 5310000 rects
+caravel_00069f13_fill_pattern_1_4: 3260000 rects
+caravel_00069f13_fill_pattern_2_3: 5320000 rects
+caravel_00069f13_fill_pattern_1_4: 3270000 rects
+caravel_00069f13_fill_pattern_0_5: 4790000 rects
+caravel_00069f13_fill_pattern_1_4: 3280000 rects
+caravel_00069f13_fill_pattern_2_3: 5330000 rects
+caravel_00069f13_fill_pattern_0_5: 4800000 rects
+caravel_00069f13_fill_pattern_1_4: 3290000 rects
+caravel_00069f13_fill_pattern_2_3: 5340000 rects
+caravel_00069f13_fill_pattern_0_5: 4810000 rects
+caravel_00069f13_fill_pattern_1_4: 3300000 rects
+caravel_00069f13_fill_pattern_2_3: 5350000 rects
+caravel_00069f13_fill_pattern_1_4: 3310000 rects
+caravel_00069f13_fill_pattern_2_3: 5360000 rects
+caravel_00069f13_fill_pattern_0_5: 4820000 rects
+caravel_00069f13_fill_pattern_1_4: 3320000 rects
+caravel_00069f13_fill_pattern_2_3: 5370000 rects
+caravel_00069f13_fill_pattern_0_5: 4830000 rects
+caravel_00069f13_fill_pattern_1_4: 3330000 rects
+caravel_00069f13_fill_pattern_2_3: 5380000 rects
+caravel_00069f13_fill_pattern_1_4: 3340000 rects
+caravel_00069f13_fill_pattern_0_5: 4840000 rects
+caravel_00069f13_fill_pattern_2_3: 5390000 rects
+caravel_00069f13_fill_pattern_0_5: 4850000 rects
+caravel_00069f13_fill_pattern_0_5: 4860000 rects
+caravel_00069f13_fill_pattern_0_5: 4870000 rects
+caravel_00069f13_fill_pattern_0_5: 4880000 rects
+caravel_00069f13_fill_pattern_1_4: 3350000 rects
+caravel_00069f13_fill_pattern_0_5: 4890000 rects
+caravel_00069f13_fill_pattern_2_3: 5400000 rects
+caravel_00069f13_fill_pattern_0_5: 4900000 rects
+caravel_00069f13_fill_pattern_0_5: 4910000 rects
+caravel_00069f13_fill_pattern_0_5: 4920000 rects
+caravel_00069f13_fill_pattern_1_4: 3360000 rects
+caravel_00069f13_fill_pattern_0_5: 4930000 rects
+caravel_00069f13_fill_pattern_2_3: 5410000 rects
+caravel_00069f13_fill_pattern_0_5: 4940000 rects
+caravel_00069f13_fill_pattern_1_4: 3370000 rects
+caravel_00069f13_fill_pattern_0_5: 4950000 rects
+caravel_00069f13_fill_pattern_2_3: 5420000 rects
+caravel_00069f13_fill_pattern_0_5: 4960000 rects
+caravel_00069f13_fill_pattern_1_4: 3380000 rects
+caravel_00069f13_fill_pattern_0_5: 4970000 rects
+caravel_00069f13_fill_pattern_2_3: 5430000 rects
+caravel_00069f13_fill_pattern_0_5: 4980000 rects
+caravel_00069f13_fill_pattern_1_4: 3390000 rects
+caravel_00069f13_fill_pattern_0_5: 4990000 rects
+caravel_00069f13_fill_pattern_2_3: 5440000 rects
+caravel_00069f13_fill_pattern_0_5: 5000000 rects
+caravel_00069f13_fill_pattern_1_4: 3400000 rects
+caravel_00069f13_fill_pattern_0_5: 5010000 rects
+caravel_00069f13_fill_pattern_2_3: 5450000 rects
+caravel_00069f13_fill_pattern_0_5: 5020000 rects
+caravel_00069f13_fill_pattern_1_4: 3410000 rects
+caravel_00069f13_fill_pattern_0_5: 5030000 rects
+caravel_00069f13_fill_pattern_2_3: 5460000 rects
+caravel_00069f13_fill_pattern_0_5: 5040000 rects
+caravel_00069f13_fill_pattern_0_5: 5050000 rects
+caravel_00069f13_fill_pattern_1_4: 3420000 rects
+caravel_00069f13_fill_pattern_0_5: 5060000 rects
+caravel_00069f13_fill_pattern_0_5: 5070000 rects
+caravel_00069f13_fill_pattern_0_5: 5080000 rects
+caravel_00069f13_fill_pattern_2_3: 5470000 rects
+caravel_00069f13_fill_pattern_0_5: 5090000 rects
+caravel_00069f13_fill_pattern_1_4: 3430000 rects
+caravel_00069f13_fill_pattern_0_5: 5100000 rects
+caravel_00069f13_fill_pattern_2_3: 5480000 rects
+caravel_00069f13_fill_pattern_1_4: 3440000 rects
+caravel_00069f13_fill_pattern_0_5: 5110000 rects
+caravel_00069f13_fill_pattern_1_4: 3450000 rects
+caravel_00069f13_fill_pattern_2_3: 5490000 rects
+caravel_00069f13_fill_pattern_0_5: 5120000 rects
+caravel_00069f13_fill_pattern_1_4: 3460000 rects
+caravel_00069f13_fill_pattern_2_3: 5500000 rects
+caravel_00069f13_fill_pattern_0_5: 5130000 rects
+caravel_00069f13_fill_pattern_1_4: 3470000 rects
+caravel_00069f13_fill_pattern_2_3: 5510000 rects
+caravel_00069f13_fill_pattern_1_4: 3480000 rects
+caravel_00069f13_fill_pattern_0_5: 5140000 rects
+caravel_00069f13_fill_pattern_2_3: 5520000 rects
+caravel_00069f13_fill_pattern_0_5: 5150000 rects
+caravel_00069f13_fill_pattern_0_5: 5160000 rects
+caravel_00069f13_fill_pattern_0_5: 5170000 rects
+caravel_00069f13_fill_pattern_0_5: 5180000 rects
+caravel_00069f13_fill_pattern_1_4: 3490000 rects
+caravel_00069f13_fill_pattern_0_5: 5190000 rects
+caravel_00069f13_fill_pattern_2_3: 5530000 rects
+caravel_00069f13_fill_pattern_1_4: 3500000 rects
+caravel_00069f13_fill_pattern_2_3: 5540000 rects
+caravel_00069f13_fill_pattern_0_5: 5200000 rects
+caravel_00069f13_fill_pattern_1_4: 3510000 rects
+caravel_00069f13_fill_pattern_1_4: 3520000 rects
+caravel_00069f13_fill_pattern_2_3: 5550000 rects
+caravel_00069f13_fill_pattern_1_4: 3530000 rects
+caravel_00069f13_fill_pattern_2_3: 5560000 rects
+caravel_00069f13_fill_pattern_1_4: 3540000 rects
+caravel_00069f13_fill_pattern_2_3: 5570000 rects
+CIF output style is now "wafflefill(tiled)"
+ Generating output for cell caravel_00069f13_fill_pattern_0_5
+caravel_00069f13_fill_pattern_1_4: 3550000 rects
+caravel_00069f13_fill_pattern_2_3: 5580000 rects
+caravel_00069f13_fill_pattern_1_4: 3560000 rects
+caravel_00069f13_fill_pattern_2_3: 5590000 rects
+caravel_00069f13_fill_pattern_1_4: 3570000 rects
+caravel_00069f13_fill_pattern_2_3: 5600000 rects
+caravel_00069f13_fill_pattern_1_4: 3580000 rects
+caravel_00069f13_fill_pattern_2_3: 5610000 rects
+caravel_00069f13_fill_pattern_1_4: 3590000 rects
+caravel_00069f13_fill_pattern_2_3: 5620000 rects
+caravel_00069f13_fill_pattern_1_4: 3600000 rects
+caravel_00069f13_fill_pattern_2_3: 5630000 rects
+caravel_00069f13_fill_pattern_2_3: 5640000 rects
+caravel_00069f13_fill_pattern_1_4: 3610000 rects
+caravel_00069f13_fill_pattern_2_3: 5650000 rects
+caravel_00069f13_fill_pattern_2_3: 5660000 rects
+caravel_00069f13_fill_pattern_1_4: 3620000 rects
+caravel_00069f13_fill_pattern_2_3: 5670000 rects
+caravel_00069f13_fill_pattern_2_3: 5680000 rects
+caravel_00069f13_fill_pattern_1_4: 3630000 rects
+caravel_00069f13_fill_pattern_2_3: 5690000 rects
+caravel_00069f13_fill_pattern_2_3: 5700000 rects
+caravel_00069f13_fill_pattern_1_4: 3640000 rects
+caravel_00069f13_fill_pattern_2_3: 5710000 rects
+caravel_00069f13_fill_pattern_2_3: 5720000 rects
+caravel_00069f13_fill_pattern_1_4: 3650000 rects
+caravel_00069f13_fill_pattern_2_3: 5730000 rects
+caravel_00069f13_fill_pattern_2_3: 5740000 rects
+caravel_00069f13_fill_pattern_1_4: 3660000 rects
+caravel_00069f13_fill_pattern_2_3: 5750000 rects
+caravel_00069f13_fill_pattern_2_3: 5760000 rects
+caravel_00069f13_fill_pattern_1_4: 3670000 rects
+caravel_00069f13_fill_pattern_2_3: 5770000 rects
+caravel_00069f13_fill_pattern_1_4: 3680000 rects
+caravel_00069f13_fill_pattern_2_3: 5780000 rects
+caravel_00069f13_fill_pattern_2_3: 5790000 rects
+caravel_00069f13_fill_pattern_1_4: 3690000 rects
+caravel_00069f13_fill_pattern_2_3: 5800000 rects
+caravel_00069f13_fill_pattern_2_3: 5810000 rects
+caravel_00069f13_fill_pattern_1_4: 3700000 rects
+caravel_00069f13_fill_pattern_2_3: 5820000 rects
+caravel_00069f13_fill_pattern_2_3: 5830000 rects
+caravel_00069f13_fill_pattern_1_4: 3710000 rects
+caravel_00069f13_fill_pattern_2_3: 5840000 rects
+caravel_00069f13_fill_pattern_2_3: 5850000 rects
+caravel_00069f13_fill_pattern_1_4: 3720000 rects
+caravel_00069f13_fill_pattern_2_3: 5860000 rects
+caravel_00069f13_fill_pattern_2_3: 5870000 rects
+caravel_00069f13_fill_pattern_1_4: 3730000 rects
+caravel_00069f13_fill_pattern_2_3: 5880000 rects
+caravel_00069f13_fill_pattern_2_3: 5890000 rects
+caravel_00069f13_fill_pattern_1_4: 3740000 rects
+caravel_00069f13_fill_pattern_2_3: 5900000 rects
+caravel_00069f13_fill_pattern_1_4: 3750000 rects
+caravel_00069f13_fill_pattern_2_3: 5910000 rects
+caravel_00069f13_fill_pattern_2_3: 5920000 rects
+caravel_00069f13_fill_pattern_1_4: 3760000 rects
+caravel_00069f13_fill_pattern_2_3: 5930000 rects
+caravel_00069f13_fill_pattern_2_3: 5940000 rects
+caravel_00069f13_fill_pattern_1_4: 3770000 rects
+caravel_00069f13_fill_pattern_2_3: 5950000 rects
+caravel_00069f13_fill_pattern_2_3: 5960000 rects
+caravel_00069f13_fill_pattern_1_4: 3780000 rects
+caravel_00069f13_fill_pattern_2_3: 5970000 rects
+caravel_00069f13_fill_pattern_2_3: 5980000 rects
+caravel_00069f13_fill_pattern_1_4: 3790000 rects
+caravel_00069f13_fill_pattern_2_3: 5990000 rects
+caravel_00069f13_fill_pattern_2_3: 6000000 rects
+caravel_00069f13_fill_pattern_1_4: 3800000 rects
+caravel_00069f13_fill_pattern_2_3: 6010000 rects
+caravel_00069f13_fill_pattern_2_3: 6020000 rects
+caravel_00069f13_fill_pattern_1_4: 3810000 rects
+caravel_00069f13_fill_pattern_2_3: 6030000 rects
+caravel_00069f13_fill_pattern_1_4: 3820000 rects
+caravel_00069f13_fill_pattern_2_3: 6040000 rects
+caravel_00069f13_fill_pattern_2_3: 6050000 rects
+caravel_00069f13_fill_pattern_1_4: 3830000 rects
+caravel_00069f13_fill_pattern_2_3: 6060000 rects
+caravel_00069f13_fill_pattern_2_3: 6070000 rects
+caravel_00069f13_fill_pattern_1_4: 3840000 rects
+caravel_00069f13_fill_pattern_2_3: 6080000 rects
+caravel_00069f13_fill_pattern_2_3: 6090000 rects
+caravel_00069f13_fill_pattern_1_4: 3850000 rects
+caravel_00069f13_fill_pattern_2_3: 6100000 rects
+caravel_00069f13_fill_pattern_2_3: 6110000 rects
+caravel_00069f13_fill_pattern_1_4: 3860000 rects
+caravel_00069f13_fill_pattern_2_3: 6120000 rects
+caravel_00069f13_fill_pattern_1_4: 3870000 rects
+caravel_00069f13_fill_pattern_2_3: 6130000 rects
+caravel_00069f13_fill_pattern_2_3: 6140000 rects
+caravel_00069f13_fill_pattern_1_4: 3880000 rects
+caravel_00069f13_fill_pattern_2_3: 6150000 rects
+caravel_00069f13_fill_pattern_2_3: 6160000 rects
+caravel_00069f13_fill_pattern_1_4: 3890000 rects
+caravel_00069f13_fill_pattern_2_3: 6170000 rects
+caravel_00069f13_fill_pattern_2_3: 6180000 rects
+caravel_00069f13_fill_pattern_1_4: 3900000 rects
+caravel_00069f13_fill_pattern_2_3: 6190000 rects
+caravel_00069f13_fill_pattern_1_4: 3910000 rects
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+caravel_00069f13_fill_pattern_2_3: 6760000 rects
+caravel_00069f13_fill_pattern_1_4: 4230000 rects
+Ended: 11/15/2022 21:25:02
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+caravel_00069f13_fill_pattern_2_3: 6920000 rects
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+Ended: 11/15/2022 21:25:03
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+CIF output style is now "wafflefill(tiled)"
+caravel_00069f13_fill_pattern_1_4: 5090000 rects
+ Generating output for cell caravel_00069f13_fill_pattern_2_3
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+caravel_00069f13_fill_pattern_1_4: 5110000 rects
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+caravel_00069f13_fill_pattern_1_4: 5890000 rects
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+caravel_00069f13_fill_pattern_1_4: 5930000 rects
+caravel_00069f13_fill_pattern_1_4: 5940000 rects
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+caravel_00069f13_fill_pattern_1_4: 5960000 rects
+caravel_00069f13_fill_pattern_1_4: 5970000 rects
+caravel_00069f13_fill_pattern_1_4: 5980000 rects
+caravel_00069f13_fill_pattern_1_4: 5990000 rects
+Ended: 11/15/2022 21:25:21
+caravel_00069f13_fill_pattern_1_4: 6000000 rects
+caravel_00069f13_fill_pattern_1_4: 6010000 rects
+caravel_00069f13_fill_pattern_1_4: 6020000 rects
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+caravel_00069f13_fill_pattern_1_4: 6120000 rects
+caravel_00069f13_fill_pattern_1_4: 6130000 rects
+caravel_00069f13_fill_pattern_1_4: 6140000 rects
+caravel_00069f13_fill_pattern_1_4: 6150000 rects
+caravel_00069f13_fill_pattern_1_4: 6160000 rects
+caravel_00069f13_fill_pattern_1_4: 6170000 rects
+caravel_00069f13_fill_pattern_1_4: 6180000 rects
+caravel_00069f13_fill_pattern_1_4: 6190000 rects
+caravel_00069f13_fill_pattern_1_4: 6200000 rects
+caravel_00069f13_fill_pattern_1_4: 6210000 rects
+caravel_00069f13_fill_pattern_1_4: 6220000 rects
+caravel_00069f13_fill_pattern_1_4: 6230000 rects
+caravel_00069f13_fill_pattern_1_4: 6240000 rects
+caravel_00069f13_fill_pattern_1_4: 6250000 rects
+caravel_00069f13_fill_pattern_1_4: 6260000 rects
+CIF output style is now "wafflefill(tiled)"
+ Generating output for cell caravel_00069f13_fill_pattern_1_4
+Ended: 11/15/2022 21:25:43
+Ended: 11/15/2022 21:25:44
+Ended: 11/15/2022 21:25:45
+Ended: 11/15/2022 21:25:50
+Ended: 11/15/2022 21:25:51
+Ended: 11/15/2022 21:26:05
+Ended: 11/15/2022 21:26:17
+Ended: 11/15/2022 21:26:26
+Ended: 11/15/2022 21:26:38
+Ended: 11/15/2022 21:26:39
+Ended: 11/15/2022 21:26:49
+Ended: 11/15/2022 21:26:51
+Ended: 11/15/2022 21:26:51
+Ended: 11/15/2022 21:26:56
+Ended: 11/15/2022 21:27:07
+Ended: 11/15/2022 21:27:15
+Ended: 11/15/2022 21:27:20
+Ended: 11/15/2022 21:27:39
+Ended: 11/15/2022 21:27:48
+Ended: 11/15/2022 21:27:49
+Ended: 11/15/2022 21:27:52
+Ended: 11/15/2022 21:27:54
+Ended: 11/15/2022 21:27:57
+Ended: 11/15/2022 21:28:05
+Ended: 11/15/2022 21:28:06
+Ended: 11/15/2022 21:28:19
+Ended: 11/15/2022 21:28:27
+Ended: 11/15/2022 21:28:41
+Ended: 11/15/2022 21:29:19
+Ended: 11/15/2022 21:30:44
+Ended: 11/15/2022 21:32:00
+Ended: 11/15/2022 21:34:38
diff --git a/tapeout/logs/gds.info b/tapeout/logs/gds.info
new file mode 100644
index 0000000..3d11973
--- /dev/null
+++ b/tapeout/logs/gds.info
@@ -0,0 +1 @@
+user_project_wrapper.gds: 0507457456d10a63886f8f85f5ef273429ebec32
\ No newline at end of file
diff --git a/tapeout/logs/gen_gpio_defaults.log b/tapeout/logs/gen_gpio_defaults.log
new file mode 100644
index 0000000..15add75
--- /dev/null
+++ b/tapeout/logs/gen_gpio_defaults.log
@@ -0,0 +1,80 @@
+/root/project/verilog/rtl/user_defines.v not found, using default /opt/caravel/verilog/rtl/user_defines.v
+Step 1: Create new cells for new GPIO default vectors.
+Creating new layout file /root/project/mag/gpio_defaults_block_1803.mag
+Creating new gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1803.v
+Layout file /root/project/mag/gpio_defaults_block_1803.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1803.v already exists and does not need to be generated.
+Creating new layout file /root/project/mag/gpio_defaults_block_0403.mag
+Creating new gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0403.v
+Creating new layout file /root/project/mag/gpio_defaults_block_0801.mag
+Creating new gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0801.v
+Layout file /root/project/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Layout file /root/project/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
+Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
+Step 2: Modify top-level layouts to use the specified defaults.
+Done.
diff --git a/tapeout/logs/git_clone.log b/tapeout/logs/git_clone.log
new file mode 100644
index 0000000..eb5fc56
--- /dev/null
+++ b/tapeout/logs/git_clone.log
@@ -0,0 +1,2 @@
+https://github.com/gitercn/riscduino_qcore_folk.git
+Cloning into '/root/project'...
diff --git a/tapeout/logs/klayout_beol.log b/tapeout/logs/klayout_beol.log
new file mode 100644
index 0000000..8a92028
--- /dev/null
+++ b/tapeout/logs/klayout_beol.log
@@ -0,0 +1,1005 @@
+/opt/scripts/tech/sky130A_mr.drc:50: warning: already initialized constant DRC::DRCEngine::FEOL
+/opt/scripts/tech/sky130A_mr.drc:40: warning: previous definition of FEOL was here
+/opt/scripts/tech/sky130A_mr.drc:54: warning: already initialized constant DRC::DRCEngine::BEOL
+/opt/scripts/tech/sky130A_mr.drc:41: warning: previous definition of BEOL was here
+/opt/scripts/tech/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/opt/scripts/tech/sky130A_mr.drc:42: warning: previous definition of OFFGRID was here
+/opt/scripts/tech/sky130A_mr.drc:68: warning: already initialized constant DRC::DRCEngine::SEAL
+/opt/scripts/tech/sky130A_mr.drc:43: warning: previous definition of SEAL was here
+/opt/scripts/tech/sky130A_mr.drc:74: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/opt/scripts/tech/sky130A_mr.drc:44: warning: previous definition of FLOATING_MET was here
+"input" in: sky130A_mr.drc:124
+ Polygons (raw): 2434574 (flat) 4649 (hierarchical)
+ Elapsed: 0.360s Memory: 2497.00M
+"polygons" in: sky130A_mr.drc:125
+ Polygons (raw): 401999 (flat) 1031 (hierarchical)
+ Elapsed: 0.270s Memory: 2497.00M
+"polygons" in: sky130A_mr.drc:126
+ Polygons (raw): 1215087 (flat) 1457 (hierarchical)
+ Elapsed: 0.230s Memory: 2497.00M
+"polygons" in: sky130A_mr.drc:127
+ Polygons (raw): 856 (flat) 37 (hierarchical)
+ Elapsed: 0.010s Memory: 2497.00M
+"polygons" in: sky130A_mr.drc:128
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 2497.00M
+"polygons" in: sky130A_mr.drc:129
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 2497.00M
+"polygons" in: sky130A_mr.drc:130
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 2497.00M
+"polygons" in: sky130A_mr.drc:131
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 2497.00M
+"polygons" in: sky130A_mr.drc:132
+ Polygons (raw): 1092318 (flat) 699 (hierarchical)
+ Elapsed: 0.210s Memory: 2497.00M
+"polygons" in: sky130A_mr.drc:133
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 2497.00M
+"polygons" in: sky130A_mr.drc:134
+ Polygons (raw): 54311 (flat) 575 (hierarchical)
+ Elapsed: 0.020s Memory: 2497.00M
+"polygons" in: sky130A_mr.drc:135
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 2497.00M
+"polygons" in: sky130A_mr.drc:136
+ Polygons (raw): 5945 (flat) 38 (hierarchical)
+ Elapsed: 0.010s Memory: 2497.00M
+"polygons" in: sky130A_mr.drc:137
+ Polygons (raw): 3870987 (flat) 11437 (hierarchical)
+ Elapsed: 0.290s Memory: 2498.00M
+"polygons" in: sky130A_mr.drc:138
+ Polygons (raw): 33 (flat) 16 (hierarchical)
+ Elapsed: 0.020s Memory: 2498.00M
+"polygons" in: sky130A_mr.drc:139
+ Polygons (raw): 1566542 (flat) 1989 (hierarchical)
+ Elapsed: 0.220s Memory: 2498.00M
+"polygons" in: sky130A_mr.drc:140
+ Polygons (raw): 1435553 (flat) 1794 (hierarchical)
+ Elapsed: 0.220s Memory: 2498.00M
+"polygons" in: sky130A_mr.drc:141
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 2498.00M
+"polygons" in: sky130A_mr.drc:142
+ Polygons (raw): 1 (flat) 1 (hierarchical)
+ Elapsed: 0.000s Memory: 2498.00M
+"polygons" in: sky130A_mr.drc:143
+ Polygons (raw): 1054290 (flat) 2398 (hierarchical)
+ Elapsed: 0.250s Memory: 2498.00M
+"polygons" in: sky130A_mr.drc:144
+ Polygons (raw): 15579408 (flat) 164522 (hierarchical)
+ Elapsed: 0.320s Memory: 2502.00M
+"polygons" in: sky130A_mr.drc:146
+ Polygons (raw): 9076197 (flat) 625036 (hierarchical)
+ Elapsed: 0.600s Memory: 2519.00M
+"polygons" in: sky130A_mr.drc:147
+ Polygons (raw): 15766382 (flat) 771228 (hierarchical)
+ Elapsed: 0.650s Memory: 2535.00M
+"polygons" in: sky130A_mr.drc:149
+ Polygons (raw): 9208325 (flat) 3491803 (hierarchical)
+ Elapsed: 2.250s Memory: 2618.00M
+"polygons" in: sky130A_mr.drc:150
+ Polygons (raw): 2729515 (flat) 1063170 (hierarchical)
+ Elapsed: 0.830s Memory: 2638.00M
+"polygons" in: sky130A_mr.drc:152
+ Polygons (raw): 3809439 (flat) 1778716 (hierarchical)
+ Elapsed: 1.350s Memory: 2679.00M
+"polygons" in: sky130A_mr.drc:153
+ Polygons (raw): 1063006 (flat) 330932 (hierarchical)
+ Elapsed: 0.470s Memory: 2685.00M
+"polygons" in: sky130A_mr.drc:155
+ Polygons (raw): 825154 (flat) 546571 (hierarchical)
+ Elapsed: 0.580s Memory: 2700.00M
+"polygons" in: sky130A_mr.drc:156
+ Polygons (raw): 884016 (flat) 285479 (hierarchical)
+ Elapsed: 0.430s Memory: 2705.00M
+"polygons" in: sky130A_mr.drc:158
+ Polygons (raw): 168612 (flat) 65112 (hierarchical)
+ Elapsed: 0.310s Memory: 2707.00M
+"polygons" in: sky130A_mr.drc:159
+ Polygons (raw): 240422 (flat) 24348 (hierarchical)
+ Elapsed: 0.100s Memory: 2707.00M
+"polygons" in: sky130A_mr.drc:161
+ Polygons (raw): 27013 (flat) 2506 (hierarchical)
+ Elapsed: 0.090s Memory: 2707.00M
+"polygons" in: sky130A_mr.drc:163
+ Polygons (raw): 107 (flat) 1 (hierarchical)
+ Elapsed: 0.010s Memory: 2707.00M
+"polygons" in: sky130A_mr.drc:164
+ Polygons (raw): 36 (flat) 9 (hierarchical)
+ Elapsed: 0.010s Memory: 2707.00M
+"polygons" in: sky130A_mr.drc:165
+ Polygons (raw): 1 (flat) 1 (hierarchical)
+ Elapsed: 0.010s Memory: 2707.00M
+"polygons" in: sky130A_mr.drc:166
+ Polygons (raw): 1 (flat) 1 (hierarchical)
+ Elapsed: 0.010s Memory: 2707.00M
+"polygons" in: sky130A_mr.drc:167
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 2707.00M
+"polygons" in: sky130A_mr.drc:168
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 2707.00M
+"polygons" in: sky130A_mr.drc:169
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 2707.00M
+"polygons" in: sky130A_mr.drc:170
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 2707.00M
+"polygons" in: sky130A_mr.drc:171
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 2707.00M
+"polygons" in: sky130A_mr.drc:172
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 2707.00M
+"polygons" in: sky130A_mr.drc:173
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 2707.00M
+"polygons" in: sky130A_mr.drc:174
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 2707.00M
+"polygons" in: sky130A_mr.drc:175
+ Polygons (raw): 107 (flat) 1 (hierarchical)
+ Elapsed: 0.010s Memory: 2707.00M
+"polygons" in: sky130A_mr.drc:176
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 2707.00M
+"polygons" in: sky130A_mr.drc:177
+ Polygons (raw): 24 (flat) 6 (hierarchical)
+ Elapsed: 0.000s Memory: 2707.00M
+"polygons" in: sky130A_mr.drc:178
+ Polygons (raw): 51480 (flat) 4 (hierarchical)
+ Elapsed: 0.010s Memory: 2707.00M
+"polygons" in: sky130A_mr.drc:179
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 2707.00M
+"polygons" in: sky130A_mr.drc:180
+ Polygons (raw): 1149783 (flat) 832 (hierarchical)
+ Elapsed: 0.220s Memory: 2708.00M
+"polygons" in: sky130A_mr.drc:181
+ Polygons (raw): 3799 (flat) 133 (hierarchical)
+ Elapsed: 0.010s Memory: 2708.00M
+"polygons" in: sky130A_mr.drc:182
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 2708.00M
+"polygons" in: sky130A_mr.drc:183
+ Polygons (raw): 2520 (flat) 112 (hierarchical)
+ Elapsed: 0.010s Memory: 2708.00M
+"polygons" in: sky130A_mr.drc:184
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 2708.00M
+"polygons" in: sky130A_mr.drc:185
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 2708.00M
+"polygons" in: sky130A_mr.drc:186
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 2708.00M
+"polygons" in: sky130A_mr.drc:187
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 2708.00M
+"polygons" in: sky130A_mr.drc:188
+ Polygons (raw): 11 (flat) 8 (hierarchical)
+ Elapsed: 0.160s Memory: 2708.00M
+"polygons" in: sky130A_mr.drc:189
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 2708.00M
+"polygons" in: sky130A_mr.drc:190
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 2708.00M
+"polygons" in: sky130A_mr.drc:191
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 2708.00M
+"polygons" in: sky130A_mr.drc:192
+ Polygons (raw): 981 (flat) 4 (hierarchical)
+ Elapsed: 0.010s Memory: 2708.00M
+"polygons" in: sky130A_mr.drc:193
+ Polygons (raw): 96717 (flat) 5 (hierarchical)
+ Elapsed: 0.250s Memory: 2708.00M
+"polygons" in: sky130A_mr.drc:194
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 2708.00M
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+Writing report database: /mnt/uffs/user/u7829_giters/design/riscduino_qcore_folk/jobs/tapeout/46f7672d-9431-426f-876e-5e8f96e58cc4/outputs/klayout_beol_report.xml ..
+Total elapsed: 6903.440s Memory: 17489.00M
+
+Cell exclusion list:
+ rule | cell
+ nwell.6 | sky130_fd_io__gpiov2_amux, sky130_fd_io__simple_pad_and_busses, sram
+ nsd.1 | sram
+ nsd.2 | sram
+ psd.1 | sram
+ psd.2 | sram
+
+release 2022.6.30_01.07
diff --git a/tapeout/logs/klayout_feol.log b/tapeout/logs/klayout_feol.log
new file mode 100644
index 0000000..9722239
--- /dev/null
+++ b/tapeout/logs/klayout_feol.log
@@ -0,0 +1,817 @@
+/opt/scripts/tech/sky130A_mr.drc:48: warning: already initialized constant DRC::DRCEngine::FEOL
+/opt/scripts/tech/sky130A_mr.drc:40: warning: previous definition of FEOL was here
+/opt/scripts/tech/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::BEOL
+/opt/scripts/tech/sky130A_mr.drc:41: warning: previous definition of BEOL was here
+/opt/scripts/tech/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/opt/scripts/tech/sky130A_mr.drc:42: warning: previous definition of OFFGRID was here
+/opt/scripts/tech/sky130A_mr.drc:68: warning: already initialized constant DRC::DRCEngine::SEAL
+/opt/scripts/tech/sky130A_mr.drc:43: warning: previous definition of SEAL was here
+/opt/scripts/tech/sky130A_mr.drc:74: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/opt/scripts/tech/sky130A_mr.drc:44: warning: previous definition of FLOATING_MET was here
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+"output" in: sky130A_mr.drc:343
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 8082.00M
+"not" in: sky130A_mr.drc:344
+ Polygons (raw): 1256924 (flat) 1699 (hierarchical)
+ Elapsed: 2.780s Memory: 8082.00M
+"space" in: sky130A_mr.drc:344
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 27.890s Memory: 8086.00M
+"output" in: sky130A_mr.drc:344
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 8086.00M
+END: 94/20 (psdm)
+START: 66/44 (licon)
+"not" in: sky130A_mr.drc:355
+ Polygons (raw): 6491870 (flat) 172408 (hierarchical)
+ Elapsed: 88.820s Memory: 8726.00M
+"and" in: sky130A_mr.drc:356
+ Polygons (raw): 11655138 (flat) 147905 (hierarchical)
+ Elapsed: 13.580s Memory: 8662.00M
+"interacting" in: sky130A_mr.drc:356
+ Polygons (raw): 11412734 (flat) 199417 (hierarchical)
+ Elapsed: 21.330s Memory: 8689.00M
+"not" in: sky130A_mr.drc:357
+ Polygons (raw): 10682996 (flat) 157456 (hierarchical)
+ Elapsed: 2.890s Memory: 8689.00M
+"non_rectangles" in: sky130A_mr.drc:358
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.080s Memory: 8689.00M
+"output" in: sky130A_mr.drc:358
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 8689.00M
+"or" in: sky130A_mr.drc:359
+ Polygons (raw): 1 (flat) 1 (hierarchical)
+ Elapsed: 0.010s Memory: 8689.00M
+"not" in: sky130A_mr.drc:359
+ Polygons (raw): 15579352 (flat) 164466 (hierarchical)
+ Elapsed: 2.650s Memory: 8689.00M
+"edges" in: sky130A_mr.drc:359
+ Edges: 60605992 (flat) 657778 (hierarchical)
+ Elapsed: 7.100s Memory: 8689.00M
+"without_length" in: sky130A_mr.drc:359
+ Edges: 0 (flat) 0 (hierarchical)
+ Elapsed: 18.890s Memory: 9024.00M
+"output" in: sky130A_mr.drc:359
+ Edges: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 9024.00M
+"separation" in: sky130A_mr.drc:360
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 15.790s Memory: 9024.00M
+"output" in: sky130A_mr.drc:360
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 9024.00M
+"and" in: sky130A_mr.drc:361
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 4.460s Memory: 9024.00M
+"output" in: sky130A_mr.drc:361
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 9024.00M
+"interacting" in: sky130A_mr.drc:362
+ Polygons (raw): 3041962 (flat) 25802 (hierarchical)
+ Elapsed: 5.350s Memory: 9024.00M
+"interacting" in: sky130A_mr.drc:362
+ Polygons (raw): 11412734 (flat) 199417 (hierarchical)
+ Elapsed: 1522.760s Memory: 9024.00M
+"and" in: sky130A_mr.drc:362
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 4.860s Memory: 9024.00M
+"output" in: sky130A_mr.drc:362
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 9024.00M
+END: 66/44 (licon)
+START: 89/44 (capm)
+"width" in: sky130A_mr.drc:367
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.310s Memory: 9024.00M
+"output" in: sky130A_mr.drc:367
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 9024.00M
+"space" in: sky130A_mr.drc:368
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.080s Memory: 9024.00M
+"output" in: sky130A_mr.drc:368
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 9024.00M
+"interacting" in: sky130A_mr.drc:369
+ Polygons (raw): 1 (flat) 1 (hierarchical)
+ Elapsed: 4.940s Memory: 9024.00M
+"isolated" in: sky130A_mr.drc:369
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.430s Memory: 9024.00M
+"output" in: sky130A_mr.drc:369
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 9024.00M
+"interacting" in: sky130A_mr.drc:370
+ Polygons (raw): 1 (flat) 1 (hierarchical)
+ Elapsed: 0.380s Memory: 9024.00M
+"isolated" in: sky130A_mr.drc:370
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.420s Memory: 9024.00M
+"output" in: sky130A_mr.drc:370
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 9024.00M
+"and" in: sky130A_mr.drc:371
+ Polygons (raw): 1 (flat) 1 (hierarchical)
+ Elapsed: 0.110s Memory: 9024.00M
+"enclosing" in: sky130A_mr.drc:371
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.430s Memory: 9024.00M
+"output" in: sky130A_mr.drc:371
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 9024.00M
+"enclosing" in: sky130A_mr.drc:372
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.370s Memory: 9024.00M
+"output" in: sky130A_mr.drc:372
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 9024.00M
+"enclosing" in: sky130A_mr.drc:373
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.080s Memory: 9024.00M
+"output" in: sky130A_mr.drc:373
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 9024.00M
+"separation" in: sky130A_mr.drc:374
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.080s Memory: 9024.00M
+"output" in: sky130A_mr.drc:374
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 9024.00M
+"not_interacting" in: sky130A_mr.drc:375
+ Polygons (raw): 160162 (flat) 115568 (hierarchical)
+ Elapsed: 1.210s Memory: 9024.00M
+"separation" in: sky130A_mr.drc:375
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 3.040s Memory: 9024.00M
+"output" in: sky130A_mr.drc:375
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 9024.00M
+END: 89/44 (capm)
+START: 97/44 (cap2m)
+"width" in: sky130A_mr.drc:380
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.320s Memory: 9024.00M
+"output" in: sky130A_mr.drc:380
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 9024.00M
+"space" in: sky130A_mr.drc:381
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.090s Memory: 9024.00M
+"output" in: sky130A_mr.drc:381
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 9024.00M
+"interacting" in: sky130A_mr.drc:382
+ Polygons (raw): 1 (flat) 1 (hierarchical)
+ Elapsed: 1.880s Memory: 9024.00M
+"isolated" in: sky130A_mr.drc:382
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.420s Memory: 9024.00M
+"output" in: sky130A_mr.drc:382
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 9024.00M
+"interacting" in: sky130A_mr.drc:383
+ Polygons (raw): 1 (flat) 1 (hierarchical)
+ Elapsed: 0.360s Memory: 9024.00M
+"isolated" in: sky130A_mr.drc:383
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.430s Memory: 9024.00M
+"output" in: sky130A_mr.drc:383
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 9024.00M
+"and" in: sky130A_mr.drc:384
+ Polygons (raw): 1 (flat) 1 (hierarchical)
+ Elapsed: 0.120s Memory: 9024.00M
+"enclosing" in: sky130A_mr.drc:384
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.420s Memory: 9024.00M
+"output" in: sky130A_mr.drc:384
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 9024.00M
+"enclosing" in: sky130A_mr.drc:385
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.380s Memory: 9024.00M
+"output" in: sky130A_mr.drc:385
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 9024.00M
+"enclosing" in: sky130A_mr.drc:386
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.080s Memory: 9024.00M
+"output" in: sky130A_mr.drc:386
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 9024.00M
+"separation" in: sky130A_mr.drc:387
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.070s Memory: 9024.00M
+"output" in: sky130A_mr.drc:387
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 9024.00M
+"not_interacting" in: sky130A_mr.drc:388
+ Polygons (raw): 32128 (flat) 19319 (hierarchical)
+ Elapsed: 0.700s Memory: 9024.00M
+"separation" in: sky130A_mr.drc:388
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 4.230s Memory: 9024.00M
+"output" in: sky130A_mr.drc:388
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 9024.00M
+END: 97/44 (cap2m)
+FEOL section
+START: 75/20 (hvi)
+"not" in: sky130A_mr.drc:688
+ Polygons (raw): 54311 (flat) 575 (hierarchical)
+ Elapsed: 0.280s Memory: 9024.00M
+"width" in: sky130A_mr.drc:689
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.360s Memory: 9024.00M
+"output" in: sky130A_mr.drc:689
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 9024.00M
+"space" in: sky130A_mr.drc:690
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.120s Memory: 9024.00M
+"output" in: sky130A_mr.drc:690
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 9024.00M
+END: 75/20 (hvi)
+START: 125/20 (hvntm)
+"not" in: sky130A_mr.drc:695
+ Polygons (raw): 33 (flat) 16 (hierarchical)
+ Elapsed: 0.150s Memory: 9024.00M
+"width" in: sky130A_mr.drc:696
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.310s Memory: 9024.00M
+"output" in: sky130A_mr.drc:696
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 9024.00M
+"space" in: sky130A_mr.drc:697
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.090s Memory: 9024.00M
+"output" in: sky130A_mr.drc:697
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 9024.00M
+END: 125/20 (hvntm)
+Writing report database: /mnt/uffs/user/u7829_giters/design/riscduino_qcore_folk/jobs/tapeout/46f7672d-9431-426f-876e-5e8f96e58cc4/outputs/klayout_feol_report.xml ..
+Total elapsed: 2542.890s Memory: 9008.00M
+
+Cell exclusion list:
+ rule | cell
+ nwell.6 | sky130_fd_io__gpiov2_amux, sky130_fd_io__simple_pad_and_busses, sram
+ nsd.1 | sram
+ nsd.2 | sram
+ psd.1 | sram
+ psd.2 | sram
+
+release 2022.6.30_01.07
diff --git a/tapeout/logs/klayout_fom_density.log b/tapeout/logs/klayout_fom_density.log
new file mode 100644
index 0000000..f7e880d
--- /dev/null
+++ b/tapeout/logs/klayout_fom_density.log
@@ -0,0 +1,58 @@
+fom_density.drc:: sourcing design file=/mnt/uffs/user/u7829_giters/design/riscduino_qcore_folk/jobs/tapeout/46f7672d-9431-426f-876e-5e8f96e58cc4/outputs/caravel_00069f13.oas topcell=caravel_00069f13 ...
+done.
+flattening chip boundary...
+done.
+step size = 70.0
+llx=5.964999999999999 lly=5.999999999999999 urx=3594.0349999999994 ury=5193.999999999999
+x_cnt = 51
+y_cnt = 74
+dbu = 0.0009999999999999998
+bbox_area = 18614907.159999993
+calculating subtile areas (= 3774)...
+tiles per step = 10
+calculating window step densities (= 2730)...
+{{ CHECK }} 0/2730
+{{ CHECK }} 65/2730
+{{ CHECK }} 130/2730
+{{ CHECK }} 195/2730
+{{ CHECK }} 260/2730
+{{ CHECK }} 325/2730
+{{ CHECK }} 390/2730
+{{ CHECK }} 455/2730
+{{ CHECK }} 520/2730
+{{ CHECK }} 585/2730
+{{ CHECK }} 650/2730
+{{ CHECK }} 715/2730
+{{ CHECK }} 780/2730
+{{ CHECK }} 845/2730
+{{ CHECK }} 910/2730
+{{ CHECK }} 975/2730
+{{ CHECK }} 1040/2730
+{{ CHECK }} 1105/2730
+{{ CHECK }} 1170/2730
+{{ CHECK }} 1235/2730
+{{ CHECK }} 1300/2730
+{{ CHECK }} 1365/2730
+{{ CHECK }} 1430/2730
+{{ CHECK }} 1495/2730
+{{ CHECK }} 1560/2730
+{{ CHECK }} 1625/2730
+{{ CHECK }} 1690/2730
+{{ CHECK }} 1755/2730
+{{ CHECK }} 1820/2730
+{{ CHECK }} 1885/2730
+{{ CHECK }} 1950/2730
+{{ CHECK }} 2015/2730
+{{ CHECK }} 2080/2730
+{{ CHECK }} 2145/2730
+{{ CHECK }} 2210/2730
+{{ CHECK }} 2275/2730
+{{ CHECK }} 2340/2730
+{{ CHECK }} 2405/2730
+{{ CHECK }} 2470/2730
+{{ CHECK }} 2535/2730
+{{ CHECK }} 2600/2730
+{{ CHECK }} 2665/2730
+minimum fom density = 0.3556
+maximum fom density = 0.5095
+finish received: success = true
diff --git a/tapeout/logs/klayout_gds2oas.log b/tapeout/logs/klayout_gds2oas.log
new file mode 100644
index 0000000..1063fdc
--- /dev/null
+++ b/tapeout/logs/klayout_gds2oas.log
@@ -0,0 +1 @@
+[INFO] Changing from /mnt/uffs/user/u7829_giters/design/riscduino_qcore_folk/jobs/tapeout/46f7672d-9431-426f-876e-5e8f96e58cc4/outputs/caravel_00069f13.gds to /mnt/uffs/user/u7829_giters/design/riscduino_qcore_folk/jobs/tapeout/46f7672d-9431-426f-876e-5e8f96e58cc4/outputs/caravel_00069f13.oas
diff --git a/tapeout/logs/klayout_met_density.log b/tapeout/logs/klayout_met_density.log
new file mode 100644
index 0000000..5a3c9b2
--- /dev/null
+++ b/tapeout/logs/klayout_met_density.log
@@ -0,0 +1,6 @@
+li1_ca_density is 0.45670289152399624
+m1_ca_density is 0.5497980825123412
+m2_ca_density is 0.5926433339014021
+m3_ca_density is 0.5469892647455603
+m4_ca_density is 0.49231863957471733
+m5_ca_density is 0.44565322193054435
diff --git a/tapeout/logs/klayout_missing_cells.log b/tapeout/logs/klayout_missing_cells.log
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/tapeout/logs/klayout_missing_cells.log
diff --git a/tapeout/logs/klayout_zero_area.log b/tapeout/logs/klayout_zero_area.log
new file mode 100644
index 0000000..04c6596
--- /dev/null
+++ b/tapeout/logs/klayout_zero_area.log
@@ -0,0 +1,4 @@
+0 zero-length paths, 0 zero-length paths deleted.
+0 total zero-area objects, 0 total objects deleted.
+VmPeak: 3467164 kB
+VmHWM: 2910196 kB
diff --git a/tapeout/logs/oasis.info b/tapeout/logs/oasis.info
new file mode 100644
index 0000000..5796160
--- /dev/null
+++ b/tapeout/logs/oasis.info
@@ -0,0 +1 @@
+caravel_00069f13.oas: f756049dc82bc2ae17dfeb6ead7d17e33169b3ee
\ No newline at end of file
diff --git a/tapeout/logs/pdks.info b/tapeout/logs/pdks.info
new file mode 100644
index 0000000..3bb11c6
--- /dev/null
+++ b/tapeout/logs/pdks.info
@@ -0,0 +1,2 @@
+Open PDKs: 0059588eebfc704681dc2368bd1d33d96281d10f
+Skywater PDK: f70d8ca46961ff92719d8870a18a076370b85f6c
\ No newline at end of file
diff --git a/tapeout/logs/set_user_id.log b/tapeout/logs/set_user_id.log
new file mode 100644
index 0000000..1c942a0
--- /dev/null
+++ b/tapeout/logs/set_user_id.log
@@ -0,0 +1,10 @@
+Project Chip ID is: 433939
+Setting Project Chip ID to: 00069f13
+Step 1: Modify Layout of the user_id_programming subcell
+Done!
+Step 2: Add user project ID parameter to source verilog.
+Done!
+Step 3: Add user project ID parameter to gate-level verilog.
+Done!
+Step 4: Add user project ID text to top level layout.
+Done!
diff --git a/tapeout/logs/ship_truck.log b/tapeout/logs/ship_truck.log
new file mode 100644
index 0000000..564da87
--- /dev/null
+++ b/tapeout/logs/ship_truck.log
@@ -0,0 +1,2948 @@
+
+Magic 8.3 revision 339 - Compiled on Sat Nov 12 14:25:26 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+ ubm
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/scripts/mag2gds.tcl" from command line.
+Scaled magic input cell user_project_wrapper geometry by factor of 2
+user_project_wrapper: 10000 rects
+user_project_wrapper: 20000 rects
+user_project_wrapper: 30000 rects
+user_project_wrapper: 40000 rects
+user_project_wrapper: 50000 rects
+Scaled magic input cell user_id_textblock geometry by factor of 2
+caravel: 10000 rects
+caravel: 20000 rects
+caravel: 30000 rects
+caravel: 40000 rects
+caravel: 50000 rects
+caravel: 60000 rects
+caravel: 70000 rects
+caravel: 80000 rects
+Processing timestamp mismatches: simple_por.
+Warning: Parent cell lists instance of "caravel_logo" at bad file path /root/project/mag/caravel_logo.mag.
+The cell exists in the search paths at ../mag/caravel_logo.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "caravel_motto" at bad file path /root/project/mag/caravel_motto.mag.
+The cell exists in the search paths at ../mag/caravel_motto.mag.
+The discovered version will be used.
+Scaled magic input cell caravel_motto geometry by factor of 2
+Warning: Parent cell lists instance of "font_22" at bad file path ../mag/font_22.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_22.mag.
+The discovered version will be used.
+Scaled magic input cell font_22 geometry by factor of 24
+Warning: Parent cell lists instance of "font_73" at bad file path ../mag/font_73.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_73.mag.
+The discovered version will be used.
+Scaled magic input cell font_73 geometry by factor of 24
+Warning: Parent cell lists instance of "font_43" at bad file path ../mag/font_43.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_43.mag.
+The discovered version will be used.
+Scaled magic input cell font_43 geometry by factor of 24
+Warning: Parent cell lists instance of "font_49" at bad file path ../mag/font_49.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_49.mag.
+The discovered version will be used.
+Scaled magic input cell font_49 geometry by factor of 24
+Warning: Parent cell lists instance of "font_65" at bad file path ../mag/font_65.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_65.mag.
+The discovered version will be used.
+Scaled magic input cell font_65 geometry by factor of 24
+Warning: Parent cell lists instance of "font_68" at bad file path ../mag/font_68.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_68.mag.
+The discovered version will be used.
+Scaled magic input cell font_68 geometry by factor of 24
+Warning: Parent cell lists instance of "font_54" at bad file path ../mag/font_54.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_54.mag.
+The discovered version will be used.
+Scaled magic input cell font_54 geometry by factor of 24
+Warning: Parent cell lists instance of "font_67" at bad file path ../mag/font_67.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_67.mag.
+The discovered version will be used.
+Scaled magic input cell font_67 geometry by factor of 24
+Warning: Parent cell lists instance of "font_6E" at bad file path ../mag/font_6E.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_6E.mag.
+The discovered version will be used.
+Scaled magic input cell font_6E geometry by factor of 24
+Warning: Parent cell lists instance of "font_69" at bad file path ../mag/font_69.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_69.mag.
+The discovered version will be used.
+Scaled magic input cell font_69 geometry by factor of 24
+Warning: Parent cell lists instance of "font_6C" at bad file path ../mag/font_6C.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_6C.mag.
+The discovered version will be used.
+Scaled magic input cell font_6C geometry by factor of 24
+Warning: Parent cell lists instance of "font_61" at bad file path ../mag/font_61.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_61.mag.
+The discovered version will be used.
+Scaled magic input cell font_61 geometry by factor of 24
+Warning: Parent cell lists instance of "font_53" at bad file path ../mag/font_53.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_53.mag.
+The discovered version will be used.
+Scaled magic input cell font_53 geometry by factor of 24
+Warning: Parent cell lists instance of "copyright_block" at bad file path /root/project/mag/copyright_block.mag.
+The cell exists in the search paths at ../mag/copyright_block.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "font_79" at bad file path ../mag/font_79.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_79.mag.
+The discovered version will be used.
+Scaled magic input cell font_79 geometry by factor of 24
+Warning: Parent cell lists instance of "font_76" at bad file path ../mag/font_76.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_76.mag.
+The discovered version will be used.
+Scaled magic input cell font_76 geometry by factor of 24
+Warning: Parent cell lists instance of "font_74" at bad file path ../mag/font_74.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_74.mag.
+The discovered version will be used.
+Scaled magic input cell font_74 geometry by factor of 24
+Warning: Parent cell lists instance of "font_72" at bad file path ../mag/font_72.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_72.mag.
+The discovered version will be used.
+Scaled magic input cell font_72 geometry by factor of 24
+Warning: Parent cell lists instance of "font_70" at bad file path ../mag/font_70.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_70.mag.
+The discovered version will be used.
+Scaled magic input cell font_70 geometry by factor of 24
+Warning: Parent cell lists instance of "font_66" at bad file path ../mag/font_66.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_66.mag.
+The discovered version will be used.
+Scaled magic input cell font_66 geometry by factor of 24
+Warning: Parent cell lists instance of "font_63" at bad file path ../mag/font_63.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_63.mag.
+The discovered version will be used.
+Scaled magic input cell font_63 geometry by factor of 24
+Warning: Parent cell lists instance of "font_62" at bad file path ../mag/font_62.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_62.mag.
+The discovered version will be used.
+Scaled magic input cell font_62 geometry by factor of 24
+Warning: Parent cell lists instance of "font_57" at bad file path ../mag/font_57.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_57.mag.
+The discovered version will be used.
+Scaled magic input cell font_57 geometry by factor of 24
+Warning: Parent cell lists instance of "font_56" at bad file path ../mag/font_56.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_56.mag.
+The discovered version will be used.
+Scaled magic input cell font_56 geometry by factor of 24
+Warning: Parent cell lists instance of "font_50" at bad file path ../mag/font_50.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_50.mag.
+The discovered version will be used.
+Scaled magic input cell font_50 geometry by factor of 24
+Warning: Parent cell lists instance of "font_47" at bad file path ../mag/font_47.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_47.mag.
+The discovered version will be used.
+Scaled magic input cell font_47 geometry by factor of 24
+Warning: Parent cell lists instance of "font_44" at bad file path ../mag/font_44.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_44.mag.
+The discovered version will be used.
+Scaled magic input cell font_44 geometry by factor of 24
+Warning: Parent cell lists instance of "font_35" at bad file path ../mag/font_35.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_35.mag.
+The discovered version will be used.
+Scaled magic input cell font_35 geometry by factor of 24
+Warning: Parent cell lists instance of "font_32" at bad file path ../mag/font_32.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_32.mag.
+The discovered version will be used.
+Scaled magic input cell font_32 geometry by factor of 24
+Warning: Parent cell lists instance of "font_30" at bad file path ../mag/font_30.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_30.mag.
+The discovered version will be used.
+Scaled magic input cell font_30 geometry by factor of 24
+Warning: Parent cell lists instance of "font_29" at bad file path ../mag/font_29.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_29.mag.
+The discovered version will be used.
+Scaled magic input cell font_29 geometry by factor of 24
+Warning: Parent cell lists instance of "font_28" at bad file path ../mag/font_28.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_28.mag.
+The discovered version will be used.
+Scaled magic input cell font_28 geometry by factor of 24
+Warning: Parent cell lists instance of "font_20" at bad file path ../mag/font_20.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_20.mag.
+The discovered version will be used.
+Scaled magic input cell font_20 geometry by factor of 24
+Warning: Parent cell lists instance of "font_6F" at bad file path ../mag/font_6F.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_6F.mag.
+The discovered version will be used.
+Scaled magic input cell font_6F geometry by factor of 24
+Warning: Parent cell lists instance of "font_6B" at bad file path ../mag/font_6B.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_6B.mag.
+The discovered version will be used.
+Scaled magic input cell font_6B geometry by factor of 24
+Warning: Parent cell lists instance of "font_4F" at bad file path ../mag/font_4F.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_4F.mag.
+The discovered version will be used.
+Scaled magic input cell font_4F geometry by factor of 24
+Warning: Parent cell lists instance of "font_4B" at bad file path ../mag/font_4B.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_4B.mag.
+The discovered version will be used.
+Scaled magic input cell font_4B geometry by factor of 24
+Warning: Parent cell lists instance of "font_2D" at bad file path ../mag/font_2D.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_ml_xx_hd/mag/font_2D.mag.
+The discovered version will be used.
+Scaled magic input cell font_2D geometry by factor of 24
+Warning: Parent cell lists instance of "open_source" at bad file path /root/project/mag/open_source.mag.
+The cell exists in the search paths at ../mag/open_source.mag.
+The discovered version will be used.
+Scaled magic input cell open_source geometry by factor of 2
+Warning: Parent cell lists instance of "xres_buf" at bad file path /root/project/mag/xres_buf.mag.
+The cell exists in the search paths at ../mag/xres_buf.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hvl__lsbufhv2lv_1" at bad file path ../mag/sky130_fd_sc_hvl__lsbufhv2lv_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/mag/sky130_fd_sc_hvl__lsbufhv2lv_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hvl__fill_1" at bad file path ../mag/sky130_fd_sc_hvl__fill_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/mag/sky130_fd_sc_hvl__fill_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hvl__fill_2" at bad file path ../mag/sky130_fd_sc_hvl__fill_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/mag/sky130_fd_sc_hvl__fill_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hvl__decap_8" at bad file path ../mag/sky130_fd_sc_hvl__decap_8.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/mag/sky130_fd_sc_hvl__decap_8.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hvl__decap_4" at bad file path ../mag/sky130_fd_sc_hvl__decap_4.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/mag/sky130_fd_sc_hvl__decap_4.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hvl__diode_2" at bad file path ../mag/sky130_fd_sc_hvl__diode_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/mag/sky130_fd_sc_hvl__diode_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "alpha_0" at bad file path /root/project/mag/hexdigits/alpha_0.mag.
+The cell exists in the search paths at hexdigits/alpha_0.mag.
+The discovered version will be used.
+Scaled magic input cell alpha_0 geometry by factor of 2
+Warning: Parent cell lists instance of "alpha_6" at bad file path /root/project/mag/hexdigits/alpha_6.mag.
+The cell exists in the search paths at hexdigits/alpha_6.mag.
+The discovered version will be used.
+Scaled magic input cell alpha_6 geometry by factor of 72
+Warning: Parent cell lists instance of "alpha_9" at bad file path /root/project/mag/hexdigits/alpha_9.mag.
+The cell exists in the search paths at hexdigits/alpha_9.mag.
+The discovered version will be used.
+Scaled magic input cell alpha_9 geometry by factor of 72
+Warning: Parent cell lists instance of "alpha_F" at bad file path /root/project/mag/hexdigits/alpha_F.mag.
+The cell exists in the search paths at hexdigits/alpha_F.mag.
+The discovered version will be used.
+Scaled magic input cell alpha_F geometry by factor of 72
+Warning: Parent cell lists instance of "alpha_1" at bad file path /root/project/mag/hexdigits/alpha_1.mag.
+The cell exists in the search paths at hexdigits/alpha_1.mag.
+The discovered version will be used.
+Scaled magic input cell alpha_1 geometry by factor of 72
+Warning: Parent cell lists instance of "alpha_3" at bad file path /root/project/mag/hexdigits/alpha_3.mag.
+The cell exists in the search paths at hexdigits/alpha_3.mag.
+The discovered version will be used.
+Scaled magic input cell alpha_3 geometry by factor of 72
+Warning: Parent cell lists instance of "caravel_clocking" at bad file path /root/project/mag/caravel_clocking.mag.
+The cell exists in the search paths at ../mag/caravel_clocking.mag.
+The discovered version will be used.
+caravel_clocking: 10000 rects
+caravel_clocking: 20000 rects
+caravel_clocking: 30000 rects
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__clkbuf_16" at bad file path ../mag/sky130_fd_sc_hd__clkbuf_16.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__clkbuf_16.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__buf_12" at bad file path ../mag/sky130_fd_sc_hd__buf_12.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__buf_12.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__clkbuf_1" at bad file path ../mag/sky130_fd_sc_hd__clkbuf_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__clkbuf_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__dlymetal6s2s_1" at bad file path ../mag/sky130_fd_sc_hd__dlymetal6s2s_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__dlymetal6s2s_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__buf_2" at bad file path ../mag/sky130_fd_sc_hd__buf_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__buf_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__buf_4" at bad file path ../mag/sky130_fd_sc_hd__buf_4.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__buf_4.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__clkbuf_4" at bad file path ../mag/sky130_fd_sc_hd__clkbuf_4.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__clkbuf_4.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__clkbuf_2" at bad file path ../mag/sky130_fd_sc_hd__clkbuf_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__clkbuf_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__dfrtp_1" at bad file path ../mag/sky130_fd_sc_hd__dfrtp_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__dfrtp_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__dfstp_1" at bad file path ../mag/sky130_fd_sc_hd__dfstp_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__dfstp_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__dfstp_2" at bad file path ../mag/sky130_fd_sc_hd__dfstp_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__dfstp_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__dfrtp_2" at bad file path ../mag/sky130_fd_sc_hd__dfrtp_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__dfrtp_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__dfrtp_4" at bad file path ../mag/sky130_fd_sc_hd__dfrtp_4.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__dfrtp_4.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__dfrtn_1" at bad file path ../mag/sky130_fd_sc_hd__dfrtn_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__dfrtn_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__dfxtp_1" at bad file path ../mag/sky130_fd_sc_hd__dfxtp_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__dfxtp_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__inv_4" at bad file path ../mag/sky130_fd_sc_hd__inv_4.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__inv_4.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__nand2b_1" at bad file path ../mag/sky130_fd_sc_hd__nand2b_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nand2b_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__o31ai_1" at bad file path ../mag/sky130_fd_sc_hd__o31ai_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o31ai_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__nor4_1" at bad file path ../mag/sky130_fd_sc_hd__nor4_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nor4_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__mux2_1" at bad file path ../mag/sky130_fd_sc_hd__mux2_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__mux2_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__o21ai_1" at bad file path ../mag/sky130_fd_sc_hd__o21ai_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o21ai_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__a21oi_1" at bad file path ../mag/sky130_fd_sc_hd__a21oi_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a21oi_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__o2111ai_1" at bad file path ../mag/sky130_fd_sc_hd__o2111ai_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o2111ai_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__o31a_1" at bad file path ../mag/sky130_fd_sc_hd__o31a_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o31a_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__o21bai_1" at bad file path ../mag/sky130_fd_sc_hd__o21bai_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o21bai_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__nand3b_1" at bad file path ../mag/sky130_fd_sc_hd__nand3b_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nand3b_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__o22a_1" at bad file path ../mag/sky130_fd_sc_hd__o22a_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o22a_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__and2_1" at bad file path ../mag/sky130_fd_sc_hd__and2_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and2_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__nor2_1" at bad file path ../mag/sky130_fd_sc_hd__nor2_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nor2_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__nand3_1" at bad file path ../mag/sky130_fd_sc_hd__nand3_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nand3_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__nand2_1" at bad file path ../mag/sky130_fd_sc_hd__nand2_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nand2_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__nand4bb_1" at bad file path ../mag/sky130_fd_sc_hd__nand4bb_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nand4bb_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__a2bb2o_1" at bad file path ../mag/sky130_fd_sc_hd__a2bb2o_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a2bb2o_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__o2111ai_2" at bad file path ../mag/sky130_fd_sc_hd__o2111ai_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o2111ai_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__xnor2_1" at bad file path ../mag/sky130_fd_sc_hd__xnor2_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__xnor2_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__nor3_1" at bad file path ../mag/sky130_fd_sc_hd__nor3_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nor3_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__a21o_1" at bad file path ../mag/sky130_fd_sc_hd__a21o_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a21o_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__o21a_1" at bad file path ../mag/sky130_fd_sc_hd__o21a_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o21a_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__o31ai_2" at bad file path ../mag/sky130_fd_sc_hd__o31ai_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o31ai_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__nand2b_2" at bad file path ../mag/sky130_fd_sc_hd__nand2b_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nand2b_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__nor3_2" at bad file path ../mag/sky130_fd_sc_hd__nor3_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nor3_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__o2bb2ai_1" at bad file path ../mag/sky130_fd_sc_hd__o2bb2ai_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o2bb2ai_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__a41oi_1" at bad file path ../mag/sky130_fd_sc_hd__a41oi_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a41oi_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__a31o_1" at bad file path ../mag/sky130_fd_sc_hd__a31o_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a31o_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__inv_2" at bad file path ../mag/sky130_fd_sc_hd__inv_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__inv_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__o211ai_4" at bad file path ../mag/sky130_fd_sc_hd__o211ai_4.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o211ai_4.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__o21ai_2" at bad file path ../mag/sky130_fd_sc_hd__o21ai_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o21ai_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__nor2_2" at bad file path ../mag/sky130_fd_sc_hd__nor2_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nor2_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__nor3b_2" at bad file path ../mag/sky130_fd_sc_hd__nor3b_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nor3b_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__o21a_2" at bad file path ../mag/sky130_fd_sc_hd__o21a_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o21a_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__clkinv_4" at bad file path ../mag/sky130_fd_sc_hd__clkinv_4.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__clkinv_4.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__clkinv_2" at bad file path ../mag/sky130_fd_sc_hd__clkinv_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__clkinv_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_ef_sc_hd__decap_12" at bad file path ../mag/sky130_ef_sc_hd__decap_12.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_ef_sc_hd__decap_12.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__diode_2" at bad file path ../mag/sky130_fd_sc_hd__diode_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__diode_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "buff_flash_clkrst" at bad file path /root/project/mag/buff_flash_clkrst.mag.
+The cell exists in the search paths at ../mag/buff_flash_clkrst.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__clkbuf_8" at bad file path ../mag/sky130_fd_sc_hd__clkbuf_8.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__clkbuf_8.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "gpio_control_block" at bad file path /root/project/mag/gpio_control_block.mag.
+The cell exists in the search paths at ../mag/gpio_control_block.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__buf_16" at bad file path ../mag/sky130_fd_sc_hd__buf_16.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__buf_16.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__macro_sparecell" at bad file path ../mag/sky130_fd_sc_hd__macro_sparecell.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__macro_sparecell.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__dlygate4sd3_1" at bad file path ../mag/sky130_fd_sc_hd__dlygate4sd3_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__dlygate4sd3_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__dfbbn_2" at bad file path ../mag/sky130_fd_sc_hd__dfbbn_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__dfbbn_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__or2_0" at bad file path ../mag/sky130_fd_sc_hd__or2_0.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__or2_0.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__and2_2" at bad file path ../mag/sky130_fd_sc_hd__and2_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and2_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__o21ai_4" at bad file path ../mag/sky130_fd_sc_hd__o21ai_4.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o21ai_4.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__and2b_2" at bad file path ../mag/sky130_fd_sc_hd__and2b_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and2b_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__and3b_2" at bad file path ../mag/sky130_fd_sc_hd__and3b_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and3b_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__mux2_4" at bad file path ../mag/sky130_fd_sc_hd__mux2_4.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__mux2_4.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__and2_0" at bad file path ../mag/sky130_fd_sc_hd__and2_0.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and2_0.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "housekeeping" at bad file path /root/project/mag/housekeeping.mag.
+The cell exists in the search paths at ../mag/housekeeping.mag.
+The discovered version will be used.
+housekeeping: 10000 rects
+housekeeping: 20000 rects
+housekeeping: 30000 rects
+housekeeping: 40000 rects
+housekeeping: 50000 rects
+housekeeping: 60000 rects
+housekeeping: 70000 rects
+housekeeping: 80000 rects
+housekeeping: 90000 rects
+housekeeping: 100000 rects
+housekeeping: 110000 rects
+housekeeping: 120000 rects
+housekeeping: 130000 rects
+housekeeping: 140000 rects
+housekeeping: 150000 rects
+housekeeping: 160000 rects
+housekeeping: 170000 rects
+housekeeping: 180000 rects
+housekeeping: 190000 rects
+housekeeping: 200000 rects
+housekeeping: 210000 rects
+housekeeping: 220000 rects
+housekeeping: 230000 rects
+housekeeping: 240000 rects
+housekeeping: 250000 rects
+housekeeping: 260000 rects
+housekeeping: 270000 rects
+housekeeping: 280000 rects
+housekeeping: 290000 rects
+housekeeping: 300000 rects
+housekeeping: 310000 rects
+housekeeping: 320000 rects
+housekeeping: 330000 rects
+housekeeping: 340000 rects
+housekeeping: 350000 rects
+housekeeping: 360000 rects
+housekeeping: 370000 rects
+housekeeping: 380000 rects
+housekeeping: 390000 rects
+housekeeping: 400000 rects
+housekeeping: 410000 rects
+housekeeping: 420000 rects
+housekeeping: 430000 rects
+housekeeping: 440000 rects
+housekeeping: 450000 rects
+housekeeping: 460000 rects
+housekeeping: 470000 rects
+housekeeping: 480000 rects
+housekeeping: 490000 rects
+housekeeping: 500000 rects
+housekeeping: 510000 rects
+housekeeping: 520000 rects
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__buf_8" at bad file path ../mag/sky130_fd_sc_hd__buf_8.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__buf_8.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__buf_6" at bad file path ../mag/sky130_fd_sc_hd__buf_6.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__buf_6.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__dfstp_4" at bad file path ../mag/sky130_fd_sc_hd__dfstp_4.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__dfstp_4.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__a32o_1" at bad file path ../mag/sky130_fd_sc_hd__a32o_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a32o_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__a22o_1" at bad file path ../mag/sky130_fd_sc_hd__a22o_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a22o_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__o211a_2" at bad file path ../mag/sky130_fd_sc_hd__o211a_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o211a_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__a221o_1" at bad file path ../mag/sky130_fd_sc_hd__a221o_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a221o_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__a211o_4" at bad file path ../mag/sky130_fd_sc_hd__a211o_4.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a211o_4.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__a21bo_1" at bad file path ../mag/sky130_fd_sc_hd__a21bo_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a21bo_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__nand2_4" at bad file path ../mag/sky130_fd_sc_hd__nand2_4.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nand2_4.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__mux2_2" at bad file path ../mag/sky130_fd_sc_hd__mux2_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__mux2_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__o2bb2a_1" at bad file path ../mag/sky130_fd_sc_hd__o2bb2a_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o2bb2a_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__and3b_1" at bad file path ../mag/sky130_fd_sc_hd__and3b_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and3b_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__a221o_2" at bad file path ../mag/sky130_fd_sc_hd__a221o_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a221o_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__a211o_1" at bad file path ../mag/sky130_fd_sc_hd__a211o_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a211o_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__o21ba_1" at bad file path ../mag/sky130_fd_sc_hd__o21ba_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o21ba_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__and4b_2" at bad file path ../mag/sky130_fd_sc_hd__and4b_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and4b_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__a22o_2" at bad file path ../mag/sky130_fd_sc_hd__a22o_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a22o_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__a211o_2" at bad file path ../mag/sky130_fd_sc_hd__a211o_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a211o_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__and4b_1" at bad file path ../mag/sky130_fd_sc_hd__and4b_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and4b_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__and4bb_1" at bad file path ../mag/sky130_fd_sc_hd__and4bb_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and4bb_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__and4bb_2" at bad file path ../mag/sky130_fd_sc_hd__and4bb_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and4bb_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__and3_4" at bad file path ../mag/sky130_fd_sc_hd__and3_4.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and3_4.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__nand3_4" at bad file path ../mag/sky130_fd_sc_hd__nand3_4.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nand3_4.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__a311o_1" at bad file path ../mag/sky130_fd_sc_hd__a311o_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a311o_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__and2_4" at bad file path ../mag/sky130_fd_sc_hd__and2_4.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and2_4.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__nor2_4" at bad file path ../mag/sky130_fd_sc_hd__nor2_4.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nor2_4.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__nor2_8" at bad file path ../mag/sky130_fd_sc_hd__nor2_8.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nor2_8.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__o221a_1" at bad file path ../mag/sky130_fd_sc_hd__o221a_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o221a_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__a2111o_1" at bad file path ../mag/sky130_fd_sc_hd__a2111o_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a2111o_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__nor4_2" at bad file path ../mag/sky130_fd_sc_hd__nor4_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nor4_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__a2111o_4" at bad file path ../mag/sky130_fd_sc_hd__a2111o_4.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a2111o_4.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__nor4_4" at bad file path ../mag/sky130_fd_sc_hd__nor4_4.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nor4_4.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__a2111o_2" at bad file path ../mag/sky130_fd_sc_hd__a2111o_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a2111o_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__and3b_4" at bad file path ../mag/sky130_fd_sc_hd__and3b_4.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and3b_4.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__nand2b_4" at bad file path ../mag/sky130_fd_sc_hd__nand2b_4.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nand2b_4.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__nand2_8" at bad file path ../mag/sky130_fd_sc_hd__nand2_8.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nand2_8.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__a21o_2" at bad file path ../mag/sky130_fd_sc_hd__a21o_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a21o_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__and3_1" at bad file path ../mag/sky130_fd_sc_hd__and3_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and3_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__o32a_1" at bad file path ../mag/sky130_fd_sc_hd__o32a_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o32a_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__and2b_4" at bad file path ../mag/sky130_fd_sc_hd__and2b_4.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and2b_4.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__a21boi_1" at bad file path ../mag/sky130_fd_sc_hd__a21boi_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a21boi_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__nand4_1" at bad file path ../mag/sky130_fd_sc_hd__nand4_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nand4_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__o311a_1" at bad file path ../mag/sky130_fd_sc_hd__o311a_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o311a_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__o211a_1" at bad file path ../mag/sky130_fd_sc_hd__o211a_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o211a_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__nand3_2" at bad file path ../mag/sky130_fd_sc_hd__nand3_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nand3_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__o2111a_1" at bad file path ../mag/sky130_fd_sc_hd__o2111a_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o2111a_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__nand4b_1" at bad file path ../mag/sky130_fd_sc_hd__nand4b_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nand4b_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__a31oi_1" at bad file path ../mag/sky130_fd_sc_hd__a31oi_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a31oi_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__and4_1" at bad file path ../mag/sky130_fd_sc_hd__and4_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and4_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__a41o_1" at bad file path ../mag/sky130_fd_sc_hd__a41o_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a41o_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__and2b_1" at bad file path ../mag/sky130_fd_sc_hd__and2b_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and2b_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__and3_2" at bad file path ../mag/sky130_fd_sc_hd__and3_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and3_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__a311oi_2" at bad file path ../mag/sky130_fd_sc_hd__a311oi_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a311oi_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__o41a_1" at bad file path ../mag/sky130_fd_sc_hd__o41a_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o41a_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__nor3b_1" at bad file path ../mag/sky130_fd_sc_hd__nor3b_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nor3b_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__a21oi_2" at bad file path ../mag/sky130_fd_sc_hd__a21oi_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a21oi_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__nand4_2" at bad file path ../mag/sky130_fd_sc_hd__nand4_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nand4_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__a2111oi_1" at bad file path ../mag/sky130_fd_sc_hd__a2111oi_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a2111oi_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__nand4b_4" at bad file path ../mag/sky130_fd_sc_hd__nand4b_4.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nand4b_4.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__xnor2_2" at bad file path ../mag/sky130_fd_sc_hd__xnor2_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__xnor2_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__a31oi_4" at bad file path ../mag/sky130_fd_sc_hd__a31oi_4.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a31oi_4.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__and4b_4" at bad file path ../mag/sky130_fd_sc_hd__and4b_4.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and4b_4.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__nand3b_4" at bad file path ../mag/sky130_fd_sc_hd__nand3b_4.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nand3b_4.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__o21a_4" at bad file path ../mag/sky130_fd_sc_hd__o21a_4.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o21a_4.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__a31o_2" at bad file path ../mag/sky130_fd_sc_hd__a31o_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a31o_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__xor2_1" at bad file path ../mag/sky130_fd_sc_hd__xor2_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__xor2_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__nor3_4" at bad file path ../mag/sky130_fd_sc_hd__nor3_4.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nor3_4.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__o221a_4" at bad file path ../mag/sky130_fd_sc_hd__o221a_4.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o221a_4.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__mux2_8" at bad file path ../mag/sky130_fd_sc_hd__mux2_8.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__mux2_8.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__o31a_4" at bad file path ../mag/sky130_fd_sc_hd__o31a_4.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o31a_4.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__and4_2" at bad file path ../mag/sky130_fd_sc_hd__and4_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__and4_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__a221oi_1" at bad file path ../mag/sky130_fd_sc_hd__a221oi_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a221oi_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__a221o_4" at bad file path ../mag/sky130_fd_sc_hd__a221o_4.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a221o_4.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__o31a_2" at bad file path ../mag/sky130_fd_sc_hd__o31a_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o31a_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__a21oi_4" at bad file path ../mag/sky130_fd_sc_hd__a21oi_4.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a21oi_4.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__a21o_4" at bad file path ../mag/sky130_fd_sc_hd__a21o_4.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a21o_4.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__inv_6" at bad file path ../mag/sky130_fd_sc_hd__inv_6.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__inv_6.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "digital_pll" at bad file path /root/project/mag/digital_pll.mag.
+The cell exists in the search paths at ../mag/digital_pll.mag.
+The discovered version will be used.
+digital_pll: 10000 rects
+digital_pll: 20000 rects
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__einvp_1" at bad file path ../mag/sky130_fd_sc_hd__einvp_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__einvp_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__clkinv_1" at bad file path ../mag/sky130_fd_sc_hd__clkinv_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__clkinv_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__einvn_4" at bad file path ../mag/sky130_fd_sc_hd__einvn_4.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__einvn_4.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__einvn_8" at bad file path ../mag/sky130_fd_sc_hd__einvn_8.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__einvn_8.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__einvp_2" at bad file path ../mag/sky130_fd_sc_hd__einvp_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__einvp_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__or2_2" at bad file path ../mag/sky130_fd_sc_hd__or2_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__or2_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__clkinv_8" at bad file path ../mag/sky130_fd_sc_hd__clkinv_8.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__clkinv_8.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__a32o_2" at bad file path ../mag/sky130_fd_sc_hd__a32o_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a32o_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__o2111a_2" at bad file path ../mag/sky130_fd_sc_hd__o2111a_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o2111a_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__o22a_2" at bad file path ../mag/sky130_fd_sc_hd__o22a_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o22a_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__o221a_2" at bad file path ../mag/sky130_fd_sc_hd__o221a_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o221a_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__nand3b_2" at bad file path ../mag/sky130_fd_sc_hd__nand3b_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nand3b_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__a21boi_2" at bad file path ../mag/sky130_fd_sc_hd__a21boi_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__a21boi_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__xor2_2" at bad file path ../mag/sky130_fd_sc_hd__xor2_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__xor2_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__o2bb2a_2" at bad file path ../mag/sky130_fd_sc_hd__o2bb2a_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o2bb2a_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__nand4b_2" at bad file path ../mag/sky130_fd_sc_hd__nand4b_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__nand4b_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__o21ba_2" at bad file path ../mag/sky130_fd_sc_hd__o21ba_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o21ba_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__o32a_2" at bad file path ../mag/sky130_fd_sc_hd__o32a_2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__o32a_2.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "spare_logic_block" at bad file path /root/project/mag/spare_logic_block.mag.
+The cell exists in the search paths at ../mag/spare_logic_block.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__inv_8" at bad file path ../mag/sky130_fd_sc_hd__inv_8.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__inv_8.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__dfbbp_1" at bad file path ../mag/sky130_fd_sc_hd__dfbbp_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__dfbbp_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "mgmt_protect" at bad file path /root/project/mag/mgmt_protect.mag.
+The cell exists in the search paths at ../mag/mgmt_protect.mag.
+The discovered version will be used.
+mgmt_protect: 10000 rects
+mgmt_protect: 20000 rects
+mgmt_protect: 30000 rects
+mgmt_protect: 40000 rects
+mgmt_protect: 50000 rects
+mgmt_protect: 60000 rects
+mgmt_protect: 70000 rects
+mgmt_protect: 80000 rects
+mgmt_protect: 90000 rects
+mgmt_protect: 100000 rects
+mgmt_protect: 110000 rects
+mgmt_protect: 120000 rects
+mgmt_protect: 130000 rects
+mgmt_protect: 140000 rects
+mgmt_protect: 150000 rects
+mgmt_protect: 160000 rects
+mgmt_protect: 170000 rects
+mgmt_protect: 180000 rects
+mgmt_protect: 190000 rects
+mgmt_protect: 200000 rects
+mgmt_protect: 210000 rects
+mgmt_protect: 220000 rects
+mgmt_protect: 230000 rects
+mgmt_protect: 240000 rects
+mgmt_protect: 250000 rects
+mgmt_protect: 260000 rects
+mgmt_protect: 270000 rects
+mgmt_protect: 280000 rects
+mgmt_protect: 290000 rects
+mgmt_protect: 300000 rects
+mgmt_protect: 310000 rects
+mgmt_protect: 320000 rects
+mgmt_protect: 330000 rects
+mgmt_protect: 340000 rects
+mgmt_protect: 350000 rects
+mgmt_protect: 360000 rects
+mgmt_protect: 370000 rects
+mgmt_protect: 380000 rects
+mgmt_protect: 390000 rects
+mgmt_protect: 400000 rects
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__bufbuf_8" at bad file path ../mag/sky130_fd_sc_hd__bufbuf_8.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__bufbuf_8.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hvl__conb_1" at bad file path ../mag/sky130_fd_sc_hvl__conb_1.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/mag/sky130_fd_sc_hvl__conb_1.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__inv_12" at bad file path ../mag/sky130_fd_sc_hd__inv_12.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__inv_12.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "caravel_power_routing" at bad file path /root/project/mag/caravel_power_routing.mag.
+The cell exists in the search paths at ../mag/caravel_power_routing.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "chip_io" at bad file path /root/project/mag/chip_io.mag.
+The cell exists in the search paths at ../mag/chip_io.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_ef_io__com_bus_slice_20um" at bad file path ../mag/sky130_ef_io__com_bus_slice_20um.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__com_bus_slice_20um.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_ef_io__corner_pad" at bad file path ../mag/sky130_ef_io__corner_pad.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__corner_pad.mag.
+The discovered version will be used.
+sky130_fd_io__corner_bus_overlay: 10000 rects
+Warning: Parent cell lists instance of "sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um" at bad file path ../mag/sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_ef_io__com_bus_slice_1um" at bad file path ../mag/sky130_ef_io__com_bus_slice_1um.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__com_bus_slice_1um.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_ef_io__com_bus_slice_5um" at bad file path ../mag/sky130_ef_io__com_bus_slice_5um.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__com_bus_slice_5um.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_ef_io__com_bus_slice_10um" at bad file path ../mag/sky130_ef_io__com_bus_slice_10um.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__com_bus_slice_10um.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_ef_io__vssa_hvc_clamped_pad" at bad file path ../mag/sky130_ef_io__vssa_hvc_clamped_pad.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__vssa_hvc_clamped_pad.mag.
+The discovered version will be used.
+sky130_fd_io__top_ground_hvc_wpad: 10000 rects
+sky130_fd_io__top_ground_hvc_wpad: 20000 rects
+sky130_fd_io__top_ground_hvc_wpad: 30000 rects
+sky130_fd_io__top_ground_hvc_wpad: 40000 rects
+sky130_fd_io__top_ground_hvc_wpad: 50000 rects
+sky130_fd_io__top_ground_hvc_wpad: 60000 rects
+sky130_fd_io__top_ground_hvc_wpad: 70000 rects
+sky130_fd_io__top_ground_hvc_wpad: 80000 rects
+sky130_fd_io__top_ground_hvc_wpad: 90000 rects
+sky130_fd_io__top_ground_hvc_wpad: 100000 rects
+sky130_fd_io__top_ground_hvc_wpad: 110000 rects
+sky130_fd_io__top_ground_hvc_wpad: 120000 rects
+sky130_fd_io__top_ground_hvc_wpad: 130000 rects
+sky130_fd_io__top_ground_hvc_wpad: 140000 rects
+sky130_fd_io__top_ground_hvc_wpad: 150000 rects
+sky130_fd_io__top_ground_hvc_wpad: 160000 rects
+sky130_fd_io__top_ground_hvc_wpad: 170000 rects
+sky130_fd_io__top_ground_hvc_wpad: 180000 rects
+sky130_fd_io__top_ground_hvc_wpad: 190000 rects
+sky130_fd_io__top_ground_hvc_wpad: 200000 rects
+sky130_fd_io__top_ground_hvc_wpad: 210000 rects
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_5595914180851 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_55959141808336 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_55959141808666 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_55959141808678 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_55959141808679 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_5595914180839 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdftpl1s__example_55959141808671 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdftpl1s2__example_55959141808672 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1__example_55959141808663 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808660 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdftpl1s__example_55959141808675 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdftpl1s2__example_55959141808676 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1__example_55959141808662 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808661 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_559591418084 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__genrivetdlring__example_559591418082 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__gendlring__example_559591418081 geometry by factor of 2
+Warning: Parent cell lists instance of "sky130_fd_io__top_xres4v2" at bad file path ../mag/sky130_fd_io__top_xres4v2.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_fd_io__top_xres4v2.mag.
+The discovered version will be used.
+sky130_fd_io__top_xres4v2: 10000 rects
+sky130_fd_io__top_xres4v2: 20000 rects
+sky130_fd_io__top_xres4v2: 30000 rects
+sky130_fd_io__top_xres4v2: 40000 rects
+sky130_fd_io__top_xres4v2: 50000 rects
+sky130_fd_io__top_xres4v2: 60000 rects
+sky130_fd_io__top_xres4v2: 70000 rects
+sky130_fd_io__top_xres4v2: 80000 rects
+sky130_fd_io__top_xres4v2: 90000 rects
+sky130_fd_io__top_xres4v2: 100000 rects
+sky130_fd_io__top_xres4v2: 110000 rects
+sky130_fd_io__top_xres4v2: 120000 rects
+sky130_fd_io__top_xres4v2: 130000 rects
+sky130_fd_io__top_xres4v2: 140000 rects
+sky130_fd_io__top_xres4v2: 150000 rects
+sky130_fd_io__top_xres4v2: 160000 rects
+sky130_fd_io__top_xres4v2: 170000 rects
+sky130_fd_io__top_xres4v2: 180000 rects
+sky130_fd_io__top_xres4v2: 190000 rects
+sky130_fd_io__top_xres4v2: 200000 rects
+sky130_fd_io__top_xres4v2: 210000 rects
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_55959141808719 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_55959141808765 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_55959141808717 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_55959141808243 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_5595914180890 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808264 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_5595914180858 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_5595914180833 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em1s_cdns_55959141808288 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em1s_cdns_5595914180859 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em1o_cdns_55959141808289 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808274 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808728 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808727 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808726 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808725 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808724 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808554 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808553 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808552 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808551 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808402 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808350 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808261 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808260 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808259 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808400 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808372 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808326 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808290 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808128 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808127 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_5595914180897 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_5595914180819 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808147 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808157 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808156 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808155 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808154 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808153 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808152 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808151 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808150 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808149 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808148 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1__example_55959141808158 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_559591418083 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808137 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_559591418086 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808370 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808316 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808385 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_559591418088 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808612 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_5595914180848 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_5595914180849 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m2m3__example_55959141808714 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1_centered__example_559591418081 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em2s_cdns_55959141808652 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em2o_cdns_55959141808653 geometry by factor of 2
+sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2: 10000 rects
+sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2: 20000 rects
+sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2: 30000 rects
+sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2: 40000 rects
+Scaled magic input cell sky130_fd_pr__via_l1m1_centered__example_5595914180812 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1_centered__example_5595914180811 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1_centered__example_559591418086 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1_centered__example_559591418084 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdftpm1s2__example_55959141808659 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__pfet_01v8__example_55959141808657 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808202 geometry by factor of 2
+sky130_fd_io__xres2v2_rcfilter_lpfv2: 10000 rects
+sky130_fd_io__xres2v2_rcfilter_lpfv2: 20000 rects
+sky130_fd_io__xres2v2_rcfilter_lpfv2: 30000 rects
+sky130_fd_io__xres2v2_rcfilter_lpfv2: 40000 rects
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808273 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808740 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808739 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808738 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808737 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808736 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808735 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808734 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808733 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808732 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808731 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808730 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808752 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808751 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808750 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808749 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808748 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808747 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808746 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808745 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808744 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808743 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808742 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808741 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808324 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808270 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1__example_55959141808187 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808338 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808337 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808700 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808559 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1__example_55959141808729 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__xres_tk_p_em1o_cdns_55959141808758 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__xres_tk_p_em1o_cdns_55959141808757 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__xres_tk_p_em1o_cdns_55959141808756 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__xres_tk_p_em1c_cdns_55959141808761 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__xres_tk_p_em1c_cdns_55959141808760 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__xres_tk_p_em1c_cdns_55959141808759 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__xres_p_em1c_cdns_55959141808753 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em1o_cdns_5595914180860 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_5595914180857 geometry by factor of 2
+sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2: 10000 rects
+sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2: 20000 rects
+sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2: 30000 rects
+sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2: 40000 rects
+sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2: 50000 rects
+Scaled magic input cell sky130_fd_pr__hvdftpm1s2__example_55959141808649 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdftpl1s__example_55959141808646 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808378 geometry by factor of 2
+sky130_fd_io__xres4v2_in_buf: 10000 rects
+sky130_fd_io__xres4v2_in_buf: 20000 rects
+sky130_fd_io__xres4v2_in_buf: 30000 rects
+sky130_fd_io__xres4v2_in_buf: 40000 rects
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_55959141808782 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_55959141808449 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_55959141808452 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_55959141808233 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_5595914180827 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_5595914180835 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_55959141808242 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_5595914180829 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_55959141808237 geometry by factor of 2
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__fill_4" at bad file path ../mag/sky130_fd_sc_hd__fill_4.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__fill_4.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_fd_sc_hd__fill_8" at bad file path ../mag/sky130_fd_sc_hd__fill_8.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__fill_8.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_ef_io__gpiov2_pad_wrapped" at bad file path ../mag/sky130_ef_io__gpiov2_pad_wrapped.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__gpiov2_pad_wrapped.mag.
+The discovered version will be used.
+sky130_fd_io__top_gpiov2: 10000 rects
+sky130_fd_io__top_gpiov2: 20000 rects
+sky130_fd_io__top_gpiov2: 30000 rects
+sky130_fd_io__top_gpiov2: 40000 rects
+sky130_fd_io__top_gpiov2: 50000 rects
+sky130_fd_io__top_gpiov2: 60000 rects
+sky130_fd_io__top_gpiov2: 70000 rects
+sky130_fd_io__top_gpiov2: 80000 rects
+sky130_fd_io__top_gpiov2: 90000 rects
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808418 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_55959141808190 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_5595914180811 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_55959141808191 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_55959141808517 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_55959141808518 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_5595914180815 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_5595914180816 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_5595914180884 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_55959141808106 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_55959141808504 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_5595914180812 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_5595914180875 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em2s_cdns_55959141808438 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em2o_cdns_55959141808439 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em1s_cdns_5595914180882 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em1s_cdns_5595914180881 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em1o_cdns_5595914180880 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em1o_cdns_5595914180879 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_5595914180823 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_55959141808510 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808394 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808298 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808440 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_5595914180878 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808434 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808102 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808115 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808100 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808140 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808280 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808425 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808306 geometry by factor of 2
+sky130_fd_io__gpiov2_amux: 10000 rects
+sky130_fd_io__gpiov2_amux: 20000 rects
+sky130_fd_io__gpiov2_amux: 30000 rects
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808178 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808488 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808122 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_55959141808123 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808476 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd__example_5595914180868 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_5595914180869 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_55959141808581 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808278 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808462 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_55959141808200 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_5595914180894 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfm1sd__example_55959141808258 geometry by factor of 2
+sky130_fd_io__amux_switch_1v2b: 10000 rects
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_55959141808563 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfm1sd2__example_55959141808251 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfm1sd2__example_55959141808561 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808267 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808266 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1sd2__example_55959141808633 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808322 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808321 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808320 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808294 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808325 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808323 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808291 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__pfet_01v8__example_55959141808640 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd__example_55959141808194 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em1o_cdns_55959141808328 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em1o_cdns_55959141808327 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808272 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808271 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__hvdfl1sd2__example_55959141808143 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808275 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_m1m2__example_55959141808276 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808297 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808296 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808295 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808293 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808292 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808300 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808299 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__nfet_01v8__example_55959141808308 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em1s_cdns_55959141808301 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em1o_cdns_55959141808302 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_5595914180854 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808368 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808625 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808373 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808374 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808398 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808397 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808396 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_pol1__example_55959141808395 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808401 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808399 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808269 geometry by factor of 2
+sky130_fd_io__gpio_odrvr_subv2: 10000 rects
+sky130_fd_io__gpio_odrvr_subv2: 20000 rects
+sky130_fd_io__gpio_odrvr_subv2: 30000 rects
+Scaled magic input cell sky130_fd_pr__via_pol1_centered__example_559591418080 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_5595914180832 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__tk_em1s_cdns_5595914180852 geometry by factor of 2
+sky130_fd_io__nfet_con_diff_wo_abt_270v2: 10000 rects
+sky130_fd_io__nfet_con_diff_wo_abt_270v2: 20000 rects
+sky130_fd_io__nfet_con_diff_wo_abt_270v2: 30000 rects
+Scaled magic input cell sky130_fd_pr__via_l1m1_centered__example_559591418083 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1_centered__example_559591418082 geometry by factor of 2
+sky130_fd_io__pfet_con_diff_wo_abt_270v2: 10000 rects
+sky130_fd_io__pfet_con_diff_wo_abt_270v2: 20000 rects
+sky130_fd_io__pfet_con_diff_wo_abt_270v2: 30000 rects
+sky130_fd_io__pfet_con_diff_wo_abt_270v2: 40000 rects
+Scaled magic input cell sky130_fd_pr__via_l1m1_centered__example_559591418085 geometry by factor of 2
+sky130_fd_io__gpio_pddrvr_strong_slowv2: 10000 rects
+sky130_fd_io__gpio_pddrvr_strong_slowv2: 20000 rects
+Scaled magic input cell sky130_fd_pr__hvdfm1sd__example_55959141808655 geometry by factor of 2
+Warning: Parent cell lists instance of "sky130_ef_io__vssd_lvc_clamped_pad" at bad file path ../mag/sky130_ef_io__vssd_lvc_clamped_pad.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__vssd_lvc_clamped_pad.mag.
+The discovered version will be used.
+sky130_fd_io__top_ground_lvc_wpad: 10000 rects
+sky130_fd_io__top_ground_lvc_wpad: 20000 rects
+sky130_fd_io__top_ground_lvc_wpad: 30000 rects
+sky130_fd_io__top_ground_lvc_wpad: 40000 rects
+sky130_fd_io__top_ground_lvc_wpad: 50000 rects
+sky130_fd_io__top_ground_lvc_wpad: 60000 rects
+sky130_fd_io__top_ground_lvc_wpad: 70000 rects
+sky130_fd_io__top_ground_lvc_wpad: 80000 rects
+sky130_fd_io__top_ground_lvc_wpad: 90000 rects
+sky130_fd_io__top_ground_lvc_wpad: 100000 rects
+sky130_fd_io__top_ground_lvc_wpad: 110000 rects
+sky130_fd_io__top_ground_lvc_wpad: 120000 rects
+sky130_fd_io__top_ground_lvc_wpad: 130000 rects
+sky130_fd_io__top_ground_lvc_wpad: 140000 rects
+sky130_fd_io__top_ground_lvc_wpad: 150000 rects
+sky130_fd_io__top_ground_lvc_wpad: 160000 rects
+sky130_fd_io__top_ground_lvc_wpad: 170000 rects
+sky130_fd_io__top_ground_lvc_wpad: 180000 rects
+sky130_fd_io__top_ground_lvc_wpad: 190000 rects
+sky130_fd_io__top_ground_lvc_wpad: 200000 rects
+sky130_fd_io__top_ground_lvc_wpad: 210000 rects
+sky130_fd_io__top_ground_lvc_wpad: 220000 rects
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808684 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808686 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__tpl1__example_55959141808685 geometry by factor of 2
+Scaled magic input cell sky130_fd_io__gnd2gnd_tap geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__via_l1m1__example_55959141808683 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dftpl1s2__example_55959141808702 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1__example_55959141808682 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dftpl1s2__example_55959141808694 geometry by factor of 2
+Scaled magic input cell sky130_fd_pr__dfl1__example_55959141808681 geometry by factor of 2
+Warning: Parent cell lists instance of "sky130_ef_io__vssio_hvc_clamped_pad" at bad file path ../mag/sky130_ef_io__vssio_hvc_clamped_pad.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__vssio_hvc_clamped_pad.mag.
+The discovered version will be used.
+sky130_fd_io__overlay_vssio_hvc: 10000 rects
+Warning: Parent cell lists instance of "sky130_ef_io__vdda_hvc_clamped_pad" at bad file path ../mag/sky130_ef_io__vdda_hvc_clamped_pad.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__vdda_hvc_clamped_pad.mag.
+The discovered version will be used.
+sky130_fd_io__hvc_clampv2: 10000 rects
+sky130_fd_io__hvc_clampv2: 20000 rects
+sky130_fd_io__hvc_clampv2: 30000 rects
+sky130_fd_io__hvc_clampv2: 40000 rects
+sky130_fd_io__hvc_clampv2: 50000 rects
+sky130_fd_io__hvc_clampv2: 60000 rects
+sky130_fd_io__hvc_clampv2: 70000 rects
+sky130_fd_io__hvc_clampv2: 80000 rects
+sky130_fd_io__hvc_clampv2: 90000 rects
+sky130_fd_io__hvc_clampv2: 100000 rects
+sky130_fd_io__hvc_clampv2: 110000 rects
+sky130_fd_io__hvc_clampv2: 120000 rects
+sky130_fd_io__hvc_clampv2: 130000 rects
+sky130_fd_io__hvc_clampv2: 140000 rects
+sky130_fd_io__hvc_clampv2: 150000 rects
+sky130_fd_io__hvc_clampv2: 160000 rects
+sky130_fd_io__hvc_clampv2: 170000 rects
+sky130_fd_io__hvc_clampv2: 180000 rects
+sky130_fd_io__hvc_clampv2: 190000 rects
+sky130_fd_io__hvc_clampv2: 200000 rects
+sky130_fd_io__hvc_clampv2: 210000 rects
+sky130_fd_io__hvc_clampv2: 220000 rects
+sky130_fd_io__hvc_clampv2: 230000 rects
+sky130_fd_io__hvc_clampv2: 240000 rects
+sky130_fd_io__hvc_clampv2: 250000 rects
+sky130_fd_io__hvc_clampv2: 260000 rects
+sky130_fd_io__hvc_clampv2: 270000 rects
+sky130_fd_io__hvc_clampv2: 280000 rects
+Warning: Parent cell lists instance of "sky130_ef_io__vccd_lvc_clamped_pad" at bad file path ../mag/sky130_ef_io__vccd_lvc_clamped_pad.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__vccd_lvc_clamped_pad.mag.
+The discovered version will be used.
+sky130_fd_io__top_power_lvc_wpad: 10000 rects
+sky130_fd_io__top_power_lvc_wpad: 20000 rects
+sky130_fd_io__top_power_lvc_wpad: 30000 rects
+sky130_fd_io__top_power_lvc_wpad: 40000 rects
+sky130_fd_io__top_power_lvc_wpad: 50000 rects
+sky130_fd_io__top_power_lvc_wpad: 60000 rects
+sky130_fd_io__top_power_lvc_wpad: 70000 rects
+sky130_fd_io__top_power_lvc_wpad: 80000 rects
+sky130_fd_io__top_power_lvc_wpad: 90000 rects
+sky130_fd_io__top_power_lvc_wpad: 100000 rects
+sky130_fd_io__top_power_lvc_wpad: 110000 rects
+sky130_fd_io__top_power_lvc_wpad: 120000 rects
+sky130_fd_io__top_power_lvc_wpad: 130000 rects
+sky130_fd_io__top_power_lvc_wpad: 140000 rects
+sky130_fd_io__top_power_lvc_wpad: 150000 rects
+sky130_fd_io__top_power_lvc_wpad: 160000 rects
+sky130_fd_io__top_power_lvc_wpad: 170000 rects
+sky130_fd_io__top_power_lvc_wpad: 180000 rects
+sky130_fd_io__top_power_lvc_wpad: 190000 rects
+sky130_fd_io__top_power_lvc_wpad: 200000 rects
+sky130_fd_io__top_power_lvc_wpad: 210000 rects
+sky130_fd_io__top_power_lvc_wpad: 220000 rects
+sky130_fd_io__top_power_lvc_wpad: 230000 rects
+Warning: Parent cell lists instance of "sky130_ef_io__disconnect_vdda_slice_5um" at bad file path ../mag/sky130_ef_io__disconnect_vdda_slice_5um.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__disconnect_vdda_slice_5um.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_ef_io__vddio_hvc_clamped_pad" at bad file path ../mag/sky130_ef_io__vddio_hvc_clamped_pad.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__vddio_hvc_clamped_pad.mag.
+The discovered version will be used.
+sky130_fd_io__overlay_vddio_hvc: 10000 rects
+Warning: Parent cell lists instance of "sky130_ef_io__vssd_lvc_clamped3_pad" at bad file path ../mag/sky130_ef_io__vssd_lvc_clamped3_pad.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__vssd_lvc_clamped3_pad.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "sky130_ef_io__vccd_lvc_clamped3_pad" at bad file path ../mag/sky130_ef_io__vccd_lvc_clamped3_pad.mag.
+The cell exists in the search paths at /opt/pdks/sky130A/libs.ref/sky130_fd_io/mag/sky130_ef_io__vccd_lvc_clamped3_pad.mag.
+The discovered version will be used.
+Warning: Parent cell lists instance of "gpio_signal_buffering" at bad file path /root/project/mag/gpio_signal_buffering.mag.
+The cell exists in the search paths at ../mag/gpio_signal_buffering.mag.
+The discovered version will be used.
+Processing timestamp mismatches: sky130_fd_sc_hd__tapvpwrvgnd_1, sky130_fd_sc_hd__buf_8, sky130_ef_sc_hd__decap_12, sky130_ef_io__vccd_lvc_clamped3_pad, sky130_ef_io__vssd_lvc_clamped3_pad, sky130_ef_io__vddio_hvc_clamped_pad, sky130_ef_io__disconnect_vdda_slice_5um, sky130_ef_io__vccd_lvc_clamped_pad, sky130_ef_io__vdda_hvc_clamped_pad, sky130_ef_io__vssio_hvc_clamped_pad, sky130_ef_io__vssd_lvc_clamped_pad, sky130_ef_io__gpiov2_pad_wrapped, sky130_fd_sc_hd__fill_8, sky130_fd_sc_hd__fill_4, constant_block, sky130_fd_sc_hd__buf_16, sky130_fd_sc_hd__conb_1, sky130_fd_sc_hd__fill_1, sky130_fd_sc_hd__fill_2, sky130_fd_io__top_xres4v2, sky130_ef_io__vssa_hvc_clamped_pad, sky130_ef_io__com_bus_slice_10um, sky130_ef_io__com_bus_slice_5um, sky130_ef_io__com_bus_slice_1um, sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um, sky130_ef_io__corner_pad, sky130_ef_io__com_bus_slice_20um, gpio_control_power_routing, gpio_control_power_routing_right, gpio_control_power_routing_top, gpio_defaults_block_0801, sky130_fd_sc_hd__decap_3, sky130_fd_sc_hd__decap_4, sky130_fd_sc_hd__decap_12, sky130_fd_sc_hd__decap_6, sky130_fd_sc_hd__inv_12, mprj2_logic_high, mprj_logic_high, sky130_fd_sc_hd__decap_8, sky130_fd_sc_hvl__conb_1, mgmt_protect_hv, sky130_fd_sc_hvl__lsbufhv2lv_1, sky130_fd_sc_hvl__fill_2, sky130_fd_sc_hvl__fill_1, sky130_fd_sc_hd__bufbuf_8, sky130_fd_sc_hd__buf_6, sky130_fd_sc_hd__buf_4, sky130_fd_sc_hd__nand2_8, sky130_fd_sc_hd__nand2_4, sky130_fd_sc_hd__nand2_2, sky130_fd_sc_hd__nand2_1, sky130_fd_sc_hd__clkbuf_4, sky130_fd_sc_hd__clkbuf_8, sky130_fd_sc_hd__and2_1, sky130_fd_sc_hd__and2_2, sky130_fd_sc_hd__and2_4, sky130_fd_sc_hd__and3b_4, sky130_fd_sc_hd__and3b_2, sky130_fd_sc_hd__and3b_1, sky130_fd_sc_hd__and2b_4, sky130_fd_sc_hd__clkinv_2, sky130_fd_sc_hd__inv_2, sky130_fd_sc_hd__clkinv_8, sky130_fd_sc_hd__clkinv_4, sky130_fd_sc_hd__inv_4, sky130_fd_sc_hd__diode_2, sky130_fd_sc_hd__dfbbp_1, sky130_fd_sc_hd__inv_8, sky130_fd_sc_hd__nor2_2, sky130_fd_sc_hd__mux2_2, gpio_defaults_block_0403, sky130_fd_sc_hd__o32a_2, sky130_fd_sc_hd__o21ba_2, sky130_fd_sc_hd__nand4b_2, sky130_fd_sc_hd__o2bb2a_2, sky130_fd_sc_hd__xor2_2, sky130_fd_sc_hd__a21boi_2, sky130_fd_sc_hd__nand3b_2, sky130_fd_sc_hd__o221a_2, sky130_fd_sc_hd__o22a_2, sky130_fd_sc_hd__o2111a_2, sky130_fd_sc_hd__a32o_2, sky130_fd_sc_hd__or2_2, sky130_fd_sc_hd__einvp_2, sky130_fd_sc_hd__einvn_8, sky130_fd_sc_hd__einvn_4, sky130_fd_sc_hd__clkinv_1, sky130_fd_sc_hd__einvp_1, sky130_fd_sc_hd__clkbuf_1, sky130_fd_sc_hd__clkbuf_2, sky130_fd_sc_hd__clkbuf_16, sky130_fd_sc_hd__dfrtp_2, sky130_fd_sc_hd__buf_2, sky130_fd_sc_hd__a22o_2, sky130_fd_sc_hd__a21o_2, sky130_fd_sc_hd__nand3_2, sky130_fd_sc_hd__o31a_2, sky130_fd_sc_hd__o21ai_2, sky130_fd_sc_hd__o211a_2, sky130_fd_sc_hd__and3_2, sky130_fd_sc_hd__nand2b_2, sky130_fd_sc_hd__a211o_2, sky130_fd_sc_hd__o21a_2, sky130_fd_sc_hd__a21oi_2, sky130_fd_sc_hd__and2b_2, sky130_fd_sc_hd__xnor2_2, sky130_fd_sc_hd__and4b_2, sky130_fd_sc_hd__nand4_2, sky130_fd_sc_hd__a31o_2, sky130_fd_sc_hd__inv_6, sky130_fd_sc_hd__a21o_4, sky130_fd_sc_hd__a21oi_4, sky130_fd_sc_hd__a221o_4, sky130_fd_sc_hd__a221oi_1, sky130_fd_sc_hd__and4_2, sky130_fd_sc_hd__o31a_4, sky130_fd_sc_hd__mux2_8, sky130_fd_sc_hd__o221a_4, sky130_fd_sc_hd__nor3_4, sky130_fd_sc_hd__xor2_1, sky130_fd_sc_hd__o21a_4, sky130_fd_sc_hd__nand3b_4, sky130_fd_sc_hd__and4b_4, sky130_fd_sc_hd__a31oi_4, sky130_fd_sc_hd__nand4b_4, sky130_fd_sc_hd__a2111oi_1, sky130_fd_sc_hd__nor3b_1, sky130_fd_sc_hd__o41a_1, sky130_fd_sc_hd__a311oi_2, sky130_fd_sc_hd__and2b_1, sky130_fd_sc_hd__a41o_1, sky130_fd_sc_hd__and4_1, sky130_fd_sc_hd__a31oi_1, sky130_fd_sc_hd__nand4b_1, sky130_fd_sc_hd__o2111a_1, sky130_fd_sc_hd__o211a_1, sky130_fd_sc_hd__o311a_1, sky130_fd_sc_hd__nand4_1, sky130_fd_sc_hd__a21boi_1, sky130_fd_sc_hd__o32a_1, sky130_fd_sc_hd__and3_1, sky130_fd_sc_hd__nand2b_4, sky130_fd_sc_hd__a2111o_2, sky130_fd_sc_hd__nor4_4, sky130_fd_sc_hd__a2111o_4, sky130_fd_sc_hd__nor4_2, sky130_fd_sc_hd__a2111o_1, sky130_fd_sc_hd__o221a_1, sky130_fd_sc_hd__nor2_8, sky130_fd_sc_hd__nor2_4, sky130_fd_sc_hd__a311o_1, sky130_fd_sc_hd__nand3_4, sky130_fd_sc_hd__and3_4, sky130_fd_sc_hd__and4bb_2, sky130_fd_sc_hd__and4bb_1, sky130_fd_sc_hd__and4b_1, sky130_fd_sc_hd__o21ba_1, sky130_fd_sc_hd__a211o_1, sky130_fd_sc_hd__a221o_2, sky130_fd_sc_hd__o2bb2a_1, sky130_fd_sc_hd__a21bo_1, sky130_fd_sc_hd__a211o_4, sky130_fd_sc_hd__a221o_1, sky130_fd_sc_hd__a22o_1, sky130_fd_sc_hd__a32o_1, sky130_fd_sc_hd__dfstp_4, sky130_fd_sc_hd__buf_12, sky130_fd_sc_hd__dlymetal6s2s_1, sky130_fd_sc_hd__dlygate4sd3_1, sky130_fd_sc_hd__dfrtp_1, sky130_fd_sc_hd__dfstp_2, sky130_fd_sc_hd__dfrtn_1, sky130_fd_sc_hd__dfrtp_4, sky130_fd_sc_hd__dfstp_1, sky130_fd_sc_hd__dfxtp_1, sky130_fd_sc_hd__mux2_1, sky130_fd_sc_hd__o31a_1, sky130_fd_sc_hd__a21o_1, sky130_fd_sc_hd__o31ai_1, sky130_fd_sc_hd__nor4_1, sky130_fd_sc_hd__nor3_1, sky130_fd_sc_hd__nor3_2, sky130_fd_sc_hd__a21oi_1, sky130_fd_sc_hd__nor2_1, sky130_fd_sc_hd__a2bb2o_1, sky130_fd_sc_hd__o21ai_1, sky130_fd_sc_hd__o22a_1, sky130_fd_sc_hd__nand2b_1, sky130_fd_sc_hd__o21a_1, sky130_fd_sc_hd__a31o_1, sky130_fd_sc_hd__nand3_1, sky130_fd_sc_hd__o2111ai_1, sky130_fd_sc_hd__xnor2_1, sky130_fd_sc_hd__mux2_4, gpio_defaults_block_1803, sky130_fd_sc_hd__and2_0, sky130_fd_sc_hd__o21ai_4, sky130_fd_sc_hd__or2_0, sky130_fd_sc_hd__dfbbn_2, sky130_fd_sc_hd__macro_sparecell, sky130_fd_sc_hd__nor3b_2, sky130_fd_sc_hd__o211ai_4, sky130_fd_sc_hd__a41oi_1, sky130_fd_sc_hd__o2bb2ai_1, sky130_fd_sc_hd__o31ai_2, sky130_fd_sc_hd__o2111ai_2, sky130_fd_sc_hd__nand4bb_1, sky130_fd_sc_hd__nand3b_1, sky130_fd_sc_hd__o21bai_1, alpha_3, alpha_1, alpha_F, alpha_9, alpha_6, sky130_fd_sc_hvl__diode_2, sky130_fd_sc_hvl__decap_4, sky130_fd_sc_hvl__decap_8.
+ Generating output for cell caravel_logo
+ Generating output for cell font_22
+ Generating output for cell font_73
+ Generating output for cell font_43
+ Generating output for cell font_49
+ Generating output for cell font_65
+ Generating output for cell font_68
+ Generating output for cell font_54
+ Generating output for cell font_67
+ Generating output for cell font_6E
+ Generating output for cell font_69
+ Generating output for cell font_6C
+ Generating output for cell font_61
+ Generating output for cell font_53
+ Generating output for cell caravel_motto
+ Generating output for cell font_79
+ Generating output for cell font_76
+ Generating output for cell font_74
+ Generating output for cell font_72
+ Generating output for cell font_70
+ Generating output for cell font_66
+ Generating output for cell font_63
+ Generating output for cell font_62
+ Generating output for cell font_57
+ Generating output for cell font_56
+ Generating output for cell font_50
+ Generating output for cell font_47
+ Generating output for cell font_44
+ Generating output for cell font_35
+ Generating output for cell font_32
+ Generating output for cell font_30
+ Generating output for cell font_29
+ Generating output for cell font_28
+ Generating output for cell font_20
+ Generating output for cell font_6F
+ Generating output for cell font_6B
+ Generating output for cell font_4F
+ Generating output for cell font_4B
+ Generating output for cell font_2D
+ Generating output for cell copyright_block
+ Generating output for cell open_source
+ Generating output for cell sky130_fd_sc_hvl__decap_8
+ Generating output for cell sky130_fd_sc_hvl__decap_4
+ Generating output for cell sky130_fd_sc_hvl__diode_2
+ Generating output for cell sky130_fd_sc_hvl__fill_1
+ Generating output for cell sky130_fd_sc_hvl__fill_2
+ Generating output for cell sky130_fd_sc_hvl__lsbufhv2lv_1
+ Generating output for cell xres_buf
+ Generating output for cell alpha_6
+ Generating output for cell alpha_9
+ Generating output for cell alpha_F
+ Generating output for cell alpha_1
+ Generating output for cell alpha_3
+ Generating output for cell alpha_0
+ Generating output for cell user_id_textblock
+ Generating output for cell sky130_fd_sc_hd__decap_6
+ Generating output for cell sky130_fd_sc_hd__decap_12
+ Generating output for cell sky130_fd_sc_hd__decap_4
+ Generating output for cell sky130_fd_sc_hd__decap_3
+ Generating output for cell sky130_fd_sc_hd__fill_2
+ Generating output for cell sky130_fd_sc_hd__fill_1
+ Generating output for cell sky130_fd_sc_hd__conb_1
+ Generating output for cell sky130_fd_sc_hd__tapvpwrvgnd_1
+ Generating output for cell gpio_defaults_block_1803
+ Generating output for cell sky130_fd_sc_hd__o21bai_1
+ Generating output for cell sky130_fd_sc_hd__nand3b_1
+ Generating output for cell sky130_fd_sc_hd__nand4bb_1
+ Generating output for cell sky130_fd_sc_hd__o2111ai_2
+ Generating output for cell sky130_fd_sc_hd__o31ai_2
+ Generating output for cell sky130_fd_sc_hd__o2bb2ai_1
+ Generating output for cell sky130_fd_sc_hd__a41oi_1
+ Generating output for cell sky130_fd_sc_hd__o211ai_4
+ Generating output for cell sky130_fd_sc_hd__nor3b_2
+ Generating output for cell sky130_fd_sc_hd__xnor2_1
+ Generating output for cell sky130_fd_sc_hd__o2111ai_1
+ Generating output for cell sky130_fd_sc_hd__nand3_1
+ Generating output for cell sky130_fd_sc_hd__a31o_1
+ Generating output for cell sky130_fd_sc_hd__o21a_1
+ Generating output for cell sky130_fd_sc_hd__nand2b_1
+ Generating output for cell sky130_fd_sc_hd__o22a_1
+ Generating output for cell sky130_fd_sc_hd__o21ai_1
+ Generating output for cell sky130_fd_sc_hd__a2bb2o_1
+ Generating output for cell sky130_fd_sc_hd__nor2_1
+ Generating output for cell sky130_fd_sc_hd__a21oi_1
+ Generating output for cell sky130_fd_sc_hd__nor3_2
+ Generating output for cell sky130_fd_sc_hd__nor3_1
+ Generating output for cell sky130_fd_sc_hd__nor4_1
+ Generating output for cell sky130_fd_sc_hd__o31ai_1
+ Generating output for cell sky130_fd_sc_hd__a21o_1
+ Generating output for cell sky130_fd_sc_hd__o31a_1
+ Generating output for cell sky130_fd_sc_hd__mux2_1
+ Generating output for cell sky130_fd_sc_hd__dfxtp_1
+ Generating output for cell sky130_fd_sc_hd__dfstp_1
+ Generating output for cell sky130_fd_sc_hd__dfrtp_4
+ Generating output for cell sky130_fd_sc_hd__dfrtn_1
+ Generating output for cell sky130_fd_sc_hd__dfstp_2
+ Generating output for cell sky130_fd_sc_hd__dfrtp_1
+ Generating output for cell sky130_fd_sc_hd__dlymetal6s2s_1
+ Generating output for cell sky130_fd_sc_hd__buf_12
+ Generating output for cell sky130_fd_sc_hd__o21a_2
+ Generating output for cell sky130_fd_sc_hd__nand2b_2
+ Generating output for cell sky130_fd_sc_hd__o21ai_2
+ Generating output for cell sky130_fd_sc_hd__buf_2
+ Generating output for cell sky130_fd_sc_hd__dfrtp_2
+ Generating output for cell sky130_fd_sc_hd__clkbuf_16
+ Generating output for cell sky130_fd_sc_hd__clkbuf_2
+ Generating output for cell sky130_fd_sc_hd__clkbuf_1
+ Generating output for cell sky130_fd_sc_hd__nor2_2
+ Generating output for cell sky130_fd_sc_hd__diode_2
+ Generating output for cell sky130_fd_sc_hd__inv_4
+ Generating output for cell sky130_fd_sc_hd__clkinv_4
+ Generating output for cell sky130_fd_sc_hd__inv_2
+ Generating output for cell sky130_fd_sc_hd__clkinv_2
+ Generating output for cell sky130_fd_sc_hd__and2_1
+ Generating output for cell sky130_fd_sc_hd__clkbuf_4
+ Generating output for cell sky130_fd_sc_hd__nand2_1
+ Generating output for cell sky130_fd_sc_hd__buf_4
+ Generating output for cell sky130_fd_sc_hd__decap_8
+ Generating output for cell sky130_ef_sc_hd__decap_12
+ Generating output for cell caravel_clocking
+ Generating output for cell sky130_fd_sc_hd__clkbuf_8
+ Generating output for cell buff_flash_clkrst
+ Generating output for cell sky130_fd_sc_hd__nand2_2
+ Generating output for cell sky130_fd_sc_hd__macro_sparecell
+ Generating output for cell sky130_fd_sc_hd__dfbbn_2
+ Generating output for cell sky130_fd_sc_hd__or2_0
+ Generating output for cell sky130_fd_sc_hd__o21ai_4
+ Generating output for cell sky130_fd_sc_hd__and2_0
+ Generating output for cell sky130_fd_sc_hd__mux2_4
+ Generating output for cell sky130_fd_sc_hd__dlygate4sd3_1
+ Generating output for cell sky130_fd_sc_hd__and2b_2
+ Generating output for cell sky130_fd_sc_hd__and3b_2
+ Generating output for cell sky130_fd_sc_hd__and2_2
+ Generating output for cell sky130_fd_sc_hd__buf_16
+ Generating output for cell gpio_logic_high
+ Generating output for cell gpio_control_block
+ Generating output for cell sky130_fd_sc_hd__dfstp_4
+ Generating output for cell sky130_fd_sc_hd__a32o_1
+ Generating output for cell sky130_fd_sc_hd__a22o_1
+ Generating output for cell sky130_fd_sc_hd__a221o_1
+ Generating output for cell sky130_fd_sc_hd__a211o_4
+ Generating output for cell sky130_fd_sc_hd__a21bo_1
+ Generating output for cell sky130_fd_sc_hd__o2bb2a_1
+ Generating output for cell sky130_fd_sc_hd__a221o_2
+ Generating output for cell sky130_fd_sc_hd__a211o_1
+ Generating output for cell sky130_fd_sc_hd__o21ba_1
+ Generating output for cell sky130_fd_sc_hd__and4b_1
+ Generating output for cell sky130_fd_sc_hd__and4bb_1
+ Generating output for cell sky130_fd_sc_hd__and4bb_2
+ Generating output for cell sky130_fd_sc_hd__and3_4
+ Generating output for cell sky130_fd_sc_hd__nand3_4
+ Generating output for cell sky130_fd_sc_hd__a311o_1
+ Generating output for cell sky130_fd_sc_hd__nor2_4
+ Generating output for cell sky130_fd_sc_hd__nor2_8
+ Generating output for cell sky130_fd_sc_hd__o221a_1
+ Generating output for cell sky130_fd_sc_hd__a2111o_1
+ Generating output for cell sky130_fd_sc_hd__nor4_2
+ Generating output for cell sky130_fd_sc_hd__a2111o_4
+ Generating output for cell sky130_fd_sc_hd__nor4_4
+ Generating output for cell sky130_fd_sc_hd__a2111o_2
+ Generating output for cell sky130_fd_sc_hd__nand2b_4
+ Generating output for cell sky130_fd_sc_hd__and3_1
+ Generating output for cell sky130_fd_sc_hd__o32a_1
+ Generating output for cell sky130_fd_sc_hd__a21boi_1
+ Generating output for cell sky130_fd_sc_hd__nand4_1
+ Generating output for cell sky130_fd_sc_hd__o311a_1
+ Generating output for cell sky130_fd_sc_hd__o211a_1
+ Generating output for cell sky130_fd_sc_hd__o2111a_1
+ Generating output for cell sky130_fd_sc_hd__nand4b_1
+ Generating output for cell sky130_fd_sc_hd__a31oi_1
+ Generating output for cell sky130_fd_sc_hd__and4_1
+ Generating output for cell sky130_fd_sc_hd__a41o_1
+ Generating output for cell sky130_fd_sc_hd__and2b_1
+ Generating output for cell sky130_fd_sc_hd__a311oi_2
+ Generating output for cell sky130_fd_sc_hd__o41a_1
+ Generating output for cell sky130_fd_sc_hd__nor3b_1
+ Generating output for cell sky130_fd_sc_hd__a2111oi_1
+ Generating output for cell sky130_fd_sc_hd__nand4b_4
+ Generating output for cell sky130_fd_sc_hd__a31oi_4
+ Generating output for cell sky130_fd_sc_hd__and4b_4
+ Generating output for cell sky130_fd_sc_hd__nand3b_4
+ Generating output for cell sky130_fd_sc_hd__o21a_4
+ Generating output for cell sky130_fd_sc_hd__xor2_1
+ Generating output for cell sky130_fd_sc_hd__nor3_4
+ Generating output for cell sky130_fd_sc_hd__o221a_4
+ Generating output for cell sky130_fd_sc_hd__mux2_8
+ Generating output for cell sky130_fd_sc_hd__o31a_4
+ Generating output for cell sky130_fd_sc_hd__and4_2
+ Generating output for cell sky130_fd_sc_hd__a221oi_1
+ Generating output for cell sky130_fd_sc_hd__a221o_4
+ Generating output for cell sky130_fd_sc_hd__a21oi_4
+ Generating output for cell sky130_fd_sc_hd__a21o_4
+ Generating output for cell sky130_fd_sc_hd__inv_6
+ Generating output for cell sky130_fd_sc_hd__a31o_2
+ Generating output for cell sky130_fd_sc_hd__nand4_2
+ Generating output for cell sky130_fd_sc_hd__and4b_2
+ Generating output for cell sky130_fd_sc_hd__xnor2_2
+ Generating output for cell sky130_fd_sc_hd__a21oi_2
+ Generating output for cell sky130_fd_sc_hd__a211o_2
+ Generating output for cell sky130_fd_sc_hd__and3_2
+ Generating output for cell sky130_fd_sc_hd__o211a_2
+ Generating output for cell sky130_fd_sc_hd__o31a_2
+ Generating output for cell sky130_fd_sc_hd__nand3_2
+ Generating output for cell sky130_fd_sc_hd__a21o_2
+ Generating output for cell sky130_fd_sc_hd__a22o_2
+ Generating output for cell sky130_fd_sc_hd__mux2_2
+ Generating output for cell sky130_fd_sc_hd__and2b_4
+ Generating output for cell sky130_fd_sc_hd__and3b_1
+ Generating output for cell sky130_fd_sc_hd__and3b_4
+ Generating output for cell sky130_fd_sc_hd__and2_4
+ Generating output for cell sky130_fd_sc_hd__nand2_4
+ Generating output for cell sky130_fd_sc_hd__nand2_8
+ Generating output for cell sky130_fd_sc_hd__buf_6
+ Generating output for cell sky130_fd_sc_hd__buf_8
+ Generating output for cell housekeeping
+ Generating output for cell sky130_fd_sc_hd__einvp_1
+ Generating output for cell sky130_fd_sc_hd__clkinv_1
+ Generating output for cell sky130_fd_sc_hd__einvn_4
+ Generating output for cell sky130_fd_sc_hd__einvn_8
+ Generating output for cell sky130_fd_sc_hd__einvp_2
+ Generating output for cell sky130_fd_sc_hd__or2_2
+ Generating output for cell sky130_fd_sc_hd__a32o_2
+ Generating output for cell sky130_fd_sc_hd__o2111a_2
+ Generating output for cell sky130_fd_sc_hd__o22a_2
+ Generating output for cell sky130_fd_sc_hd__o221a_2
+ Generating output for cell sky130_fd_sc_hd__nand3b_2
+ Generating output for cell sky130_fd_sc_hd__a21boi_2
+ Generating output for cell sky130_fd_sc_hd__xor2_2
+ Generating output for cell sky130_fd_sc_hd__o2bb2a_2
+ Generating output for cell sky130_fd_sc_hd__nand4b_2
+ Generating output for cell sky130_fd_sc_hd__o21ba_2
+ Generating output for cell sky130_fd_sc_hd__o32a_2
+ Generating output for cell sky130_fd_sc_hd__clkinv_8
+ Generating output for cell digital_pll
+ Generating output for cell user_id_programming
+ Generating output for cell simple_por
+Reading "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ".
+Reading "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB".
+Reading "sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC".
+Reading "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS".
+Reading "sky130_fd_pr__pfet_g5v0d10v5_YUHPBG".
+Reading "sky130_fd_pr__pfet_g5v0d10v5_YEUEBV".
+Reading "sky130_fd_pr__nfet_g5v0d10v5_PKVMTM".
+Reading "sky130_fd_pr__pfet_g5v0d10v5_YUHPXE".
+Reading "sky130_fd_sc_hvl__schmittbuf_1".
+Reading "sky130_fd_sc_hvl__buf_8".
+Reading "sky130_fd_sc_hvl__inv_8".
+Reading "sky130_fd_sc_hvl__fill_4".
+Reading "sky130_fd_pr__cap_mim_m3_1_WRT4AW".
+Reading "sky130_fd_pr__cap_mim_m3_2_W5U4AW".
+Reading "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3".
+Reading "simple_por".
+ Generating output for cell mgmt_core_wrapper
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_ef_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__o211a_1".
+Reading "sky130_fd_sc_hd__dfxtp_2".
+Reading "sky130_fd_sc_hd__o21a_1".
+Reading "sky130_fd_sc_hd__mux2_1".
+Reading "sky130_fd_sc_hd__or2_1".
+Reading "sky130_fd_sc_hd__dfxtp_1".
+Reading "sky130_fd_sc_hd__a22o_1".
+Reading "sky130_fd_sc_hd__a21o_2".
+Reading "sky130_fd_sc_hd__a21o_1".
+Reading "sky130_fd_sc_hd__a22o_4".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "sky130_fd_sc_hd__o21a_2".
+Reading "sky130_fd_sc_hd__mux2_2".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__clkbuf_8".
+Reading "sky130_fd_sc_hd__buf_6".
+Reading "sky130_fd_sc_hd__dfxtp_4".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "sky130_fd_sc_hd__o21ai_1".
+Reading "sky130_fd_sc_hd__mux4_1".
+Reading "sky130_fd_sc_hd__buf_12".
+Reading "sky130_fd_sc_hd__mux4_2".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__and3_2".
+Reading "sky130_fd_sc_hd__nand2_1".
+Reading "sky130_fd_sc_hd__a2bb2o_1".
+Reading "sky130_fd_sc_hd__or3b_1".
+Reading "sky130_fd_sc_hd__o32a_1".
+Reading "sky130_fd_sc_hd__a2bb2o_2".
+Reading "sky130_fd_sc_hd__o311a_1".
+Reading "sky130_fd_sc_hd__o221a_1".
+Reading "sky130_fd_sc_hd__o31a_1".
+Reading "sky130_fd_sc_hd__o211a_2".
+Reading "sky130_fd_sc_hd__and3_1".
+Reading "sky130_fd_sc_hd__a211oi_1".
+Reading "sky130_fd_sc_hd__and4_4".
+Reading "sky130_fd_sc_hd__and4_1".
+Reading "sky130_fd_sc_hd__clkbuf_4".
+Reading "sky130_fd_sc_hd__and3b_1".
+Reading "sky130_fd_sc_hd__a211o_4".
+Reading "sky130_fd_sc_hd__a211o_1".
+Reading "sky130_fd_sc_hd__o21ba_1".
+Reading "sky130_fd_sc_hd__a21oi_1".
+Reading "sky130_fd_sc_hd__nor2_1".
+Reading "sky130_fd_sc_hd__nand2_8".
+Reading "sky130_fd_sc_hd__a311o_1".
+Reading "sky130_fd_sc_hd__nor2_2".
+Reading "sky130_fd_sc_hd__a41o_1".
+Reading "sky130_fd_sc_hd__nor3_2".
+Reading "sky130_fd_sc_hd__or4bb_4".
+Reading "sky130_fd_sc_hd__nor3_1".
+Reading "sky130_fd_sc_hd__or4b_4".
+Reading "sky130_fd_sc_hd__or3b_4".
+Reading "sky130_fd_sc_hd__a31o_1".
+Reading "sky130_fd_sc_hd__a211o_2".
+Reading "sky130_fd_sc_hd__or2_2".
+Reading "sky130_fd_sc_hd__a31o_2".
+Reading "sky130_fd_sc_hd__a221o_1".
+Reading "sky130_fd_sc_hd__and4b_4".
+Reading "sky130_fd_sc_hd__and3_4".
+Reading "sky130_fd_sc_hd__mux2_8".
+Reading "sky130_fd_sc_hd__o21ai_2".
+Reading "sky130_fd_sc_hd__and4b_1".
+Reading "sky130_fd_sc_hd__or4b_1".
+Reading "sky130_fd_sc_hd__o211a_4".
+Reading "sky130_fd_sc_hd__a32o_1".
+Reading "sky130_fd_sc_hd__a21boi_1".
+Reading "sky130_fd_sc_hd__o41ai_4".
+Reading "sky130_fd_sc_hd__o31a_2".
+Reading "sky130_fd_sc_hd__nand2_4".
+Reading "sky130_fd_sc_hd__a31oi_4".
+Reading "sky130_fd_sc_hd__and4_2".
+Reading "sky130_fd_sc_hd__nand3_4".
+Reading "sky130_fd_sc_hd__and4b_2".
+Reading "sky130_fd_sc_hd__o41a_4".
+Reading "sky130_fd_sc_hd__and4bb_2".
+Reading "sky130_fd_sc_hd__clkinv_2".
+Reading "sky130_fd_sc_hd__and2b_2".
+Reading "sky130_fd_sc_hd__or4bb_1".
+Reading "sky130_fd_sc_hd__a21oi_2".
+Reading "sky130_fd_sc_hd__a221oi_1".
+Reading "sky130_fd_sc_hd__a31oi_1".
+Reading "sky130_fd_sc_hd__xor2_4".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__nand3b_4".
+Reading "sky130_fd_sc_hd__nand2_2".
+Reading "sky130_fd_sc_hd__xnor2_1".
+Reading "sky130_fd_sc_hd__and2_1".
+Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__nand4_4".
+Reading "sky130_fd_sc_hd__a32o_2".
+Reading "sky130_fd_sc_hd__nor4_1".
+Reading "sky130_fd_sc_hd__nand4_1".
+Reading "sky130_fd_sc_hd__xor2_1".
+Reading "sky130_fd_sc_hd__and4bb_4".
+Reading "sky130_fd_sc_hd__a41o_2".
+Reading "sky130_fd_sc_hd__o2bb2a_1".
+Reading "sky130_fd_sc_hd__xnor2_2".
+Reading "sky130_fd_sc_hd__xor2_2".
+Reading "sky130_fd_sc_hd__or2_4".
+Reading "sky130_fd_sc_hd__a2111oi_2".
+Reading "sky130_fd_sc_hd__nor4_4".
+Reading "sky130_fd_sc_hd__mux2_4".
+Reading "sky130_fd_sc_hd__and2b_1".
+Reading "sky130_fd_sc_hd__and2_2".
+Reading "sky130_fd_sc_hd__nor4b_1".
+Reading "sky130_fd_sc_hd__o2111ai_4".
+Reading "sky130_fd_sc_hd__nor4_2".
+Reading "sky130_fd_sc_hd__nand3b_2".
+Reading "sky130_fd_sc_hd__nand3_1".
+Reading "sky130_fd_sc_hd__nand2b_2".
+Reading "sky130_fd_sc_hd__o31ai_1".
+Reading "sky130_fd_sc_hd__o41a_1".
+Reading "sky130_fd_sc_hd__a21bo_1".
+Reading "sky130_fd_sc_hd__o41ai_1".
+Reading "sky130_fd_sc_hd__nand3b_1".
+Reading "sky130_fd_sc_hd__o2111a_1".
+Reading "sky130_fd_sc_hd__o21a_4".
+Reading "sky130_fd_sc_hd__o22a_1".
+Reading "sky130_fd_sc_hd__or3b_2".
+Reading "sky130_fd_sc_hd__nand2b_1".
+Reading "sky130_fd_sc_hd__nor4b_4".
+Reading "sky130_fd_sc_hd__o21bai_1".
+Reading "sky130_fd_sc_hd__nor3_4".
+Reading "sky130_fd_sc_hd__o41a_2".
+Reading "sky130_fd_sc_hd__or4b_2".
+Reading "sky130_fd_sc_hd__a221o_4".
+Reading "sky130_fd_sc_hd__a2111oi_1".
+Reading "sky130_fd_sc_hd__o31a_4".
+Reading "sky130_fd_sc_hd__nor2_8".
+Reading "sky130_fd_sc_hd__clkinv_4".
+Reading "sky130_fd_sc_hd__a221o_2".
+Reading "sky130_fd_sc_hd__o21ai_4".
+Reading "sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "sky130_fd_sc_hd__clkbuf_2".
+Reading "sky130_fd_sc_hd__a31o_4".
+Reading "sky130_fd_sc_hd__ebufn_4".
+Reading "sky130_fd_sc_hd__dlxtp_1".
+Reading "sky130_fd_sc_hd__dlclkp_1".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__inv_1".
+Reading "sky130_fd_sc_hd__nor4b_2".
+Reading "sky130_fd_sc_hd__and3b_2".
+Reading "sky130_fd_sc_hd__nor3b_2".
+Reading "RAM256".
+Reading "sky130_fd_sc_hd__a21o_4".
+Reading "sky130_fd_sc_hd__o2111a_4".
+Reading "sky130_fd_sc_hd__a22o_2".
+Reading "sky130_fd_sc_hd__o211ai_4".
+Reading "sky130_fd_sc_hd__o22ai_4".
+Reading "sky130_fd_sc_hd__a221oi_4".
+Reading "sky130_fd_sc_hd__and2b_4".
+Reading "sky130_fd_sc_hd__and3b_4".
+Reading "sky130_fd_sc_hd__and4bb_1".
+Reading "sky130_fd_sc_hd__a21oi_4".
+Reading "sky130_fd_sc_hd__o22ai_1".
+Reading "sky130_fd_sc_hd__inv_4".
+Reading "sky130_fd_sc_hd__a311o_2".
+Reading "sky130_fd_sc_hd__a2111o_1".
+Reading "sky130_fd_sc_hd__o311a_4".
+Reading "sky130_fd_sc_hd__o2111ai_1".
+Reading "sky130_fd_sc_hd__clkinv_8".
+Reading "sky130_fd_sc_hd__nand3_2".
+Reading "sky130_fd_sc_hd__a22oi_1".
+Reading "sky130_fd_sc_hd__nand4b_4".
+Reading "sky130_fd_sc_hd__o221ai_4".
+Reading "sky130_fd_sc_hd__nand4_2".
+Reading "sky130_fd_sc_hd__inv_6".
+Reading "sky130_fd_sc_hd__o2bb2ai_1".
+Reading "sky130_fd_sc_hd__a311oi_4".
+Reading "sky130_fd_sc_hd__o32ai_4".
+Reading "sky130_fd_sc_hd__o211ai_1".
+Reading "sky130_fd_sc_hd__nand4b_1".
+Reading "sky130_fd_sc_hd__o211ai_2".
+Reading "sky130_fd_sc_hd__a22oi_4".
+Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hd__a211oi_4".
+Reading "sky130_fd_sc_hd__nor3b_4".
+Reading "sky130_fd_sc_hd__o22a_2".
+Reading "sky130_fd_sc_hd__a2111oi_4".
+Reading "sky130_fd_sc_hd__nand2b_4".
+Reading "sky130_fd_sc_hd__a2bb2o_4".
+Reading "sky130_fd_sc_hd__o2bb2a_2".
+Reading "sky130_fd_sc_hd__o2111ai_2".
+Reading "sky130_fd_sc_hd__a22oi_2".
+Reading "sky130_fd_sc_hd__nor3b_1".
+Reading "sky130_fd_sc_hd__o2bb2a_4".
+Reading "sky130_fd_sc_hd__o21bai_4".
+Reading "sky130_fd_sc_hd__o311ai_1".
+Reading "sky130_fd_sc_hd__a32oi_2".
+Reading "sky130_fd_sc_hd__o2bb2ai_2".
+Reading "sky130_fd_sc_hd__o311ai_4".
+Reading "sky130_fd_sc_hd__o2bb2ai_4".
+Reading "sky130_fd_sc_hd__o31ai_4".
+Reading "sky130_fd_sc_hd__o221a_2".
+Reading "sky130_fd_sc_hd__o2111a_2".
+Reading "sky130_fd_sc_hd__a31oi_2".
+Reading "sky130_fd_sc_hd__o311a_2".
+Reading "sky130_fd_sc_hd__o22a_4".
+Reading "sky130_fd_sc_hd__a32oi_4".
+Reading "sky130_fd_sc_hd__a211oi_2".
+Reading "sky130_fd_sc_hd__o31ai_2".
+Reading "sky130_fd_sc_hd__o221ai_1".
+Reading "sky130_fd_sc_hd__clkinv_16".
+Reading "sky130_fd_sc_hd__or4bb_2".
+Reading "sky130_fd_sc_hd__a221oi_2".
+Reading "sky130_fd_sc_hd__inv_8".
+Reading "sky130_fd_sc_hd__a311oi_2".
+Reading "sky130_fd_sc_hd__a311oi_1".
+Reading "sky130_fd_sc_hd__o311ai_2".
+Reading "sky130_fd_sc_hd__a32oi_1".
+Reading "sky130_fd_sc_hd__a2bb2oi_2".
+Reading "sky130_fd_sc_hd__a2bb2oi_1".
+Reading "sky130_fd_sc_hd__a2bb2oi_4".
+Reading "sky130_fd_sc_hd__xnor2_4".
+Reading "sky130_fd_sc_hd__inv_12".
+Reading "sky130_fd_sc_hd__a2111o_4".
+Reading "sky130_fd_sc_hd__a32o_4".
+Reading "sky130_fd_sc_hd__o21ba_2".
+Reading "sky130_fd_sc_hd__a41oi_2".
+Reading "sky130_fd_sc_hd__o22ai_2".
+Reading "sky130_fd_sc_hd__o21bai_2".
+Reading "sky130_fd_sc_hd__a41oi_4".
+Reading "sky130_fd_sc_hd__a41o_4".
+Reading "sky130_fd_sc_hd__a311o_4".
+Reading "sky130_fd_sc_hd__o32ai_1".
+Reading "sky130_fd_sc_hd__a21boi_4".
+Reading "sky130_fd_sc_hd__o32ai_2".
+Reading "sky130_fd_sc_hd__a21bo_2".
+Reading "RAM128".
+Reading "mgmt_core_wrapper".
+ Generating output for cell gpio_defaults_block_0403
+ Generating output for cell sky130_fd_sc_hd__inv_8
+ Generating output for cell sky130_fd_sc_hd__dfbbp_1
+ Generating output for cell spare_logic_block
+ Generating output for cell sky130_fd_sc_hd__bufbuf_8
+ Generating output for cell sky130_fd_sc_hvl__conb_1
+ Generating output for cell mgmt_protect_hv
+ Generating output for cell mprj_logic_high
+ Generating output for cell mprj2_logic_high
+ Generating output for cell sky130_fd_sc_hd__inv_12
+ Generating output for cell mgmt_protect
+ Generating output for cell gpio_defaults_block_0801
+ Generating output for cell gpio_control_power_routing_top
+ Generating output for cell gpio_control_power_routing_right
+ Generating output for cell gpio_control_power_routing
+ Generating output for cell caravel_power_routing
+ Generating output for cell user_project_wrapper
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_39".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_19".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_14".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_13".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_7".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_38".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_33".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_32".
+Reading "sky130_fd_bd_sram__openram_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_addr_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wmask_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_addr_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_data_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_16".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_29".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_28".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_11".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_360_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_12".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sli_dactive".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w0_740_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w1_260_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m7_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m7_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m24_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m24_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_14".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m8_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m8_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_13".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_12".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_11".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_17".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_delay_chain".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m18_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m18_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_16".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_5".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dactive".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand3_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m22_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m22_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_15".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m42_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m42_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_10".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m15_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m15_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_9".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m5_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_8".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w1_260_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_7".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_rw".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_5".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m41_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m41_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_20".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m14_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m14_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_19".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_18".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_6".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_r".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_20".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_17".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_15".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w7_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w7_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec_0".
+Reading "sky130_fd_bd_sram__openram_dp_nand2_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec".
+Reading "sky130_fd_bd_sram__openram_dp_nand3_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and3_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode3x8".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_decoder".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_address_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_address".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_27".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_26".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_25".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_24".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w2_880_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array_0".
+Reading "sky130_fd_bd_sram__openram_sense_amp".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_sense_amp_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_23".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_21".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_22".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w0_550_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_data_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_write_mask_and_array".
+Reading "sky130_fd_bd_sram__openram_write_driver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_write_driver_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_data".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_9".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_8".
+Reading "sky130_fd_bd_sram__openram_dp_cell_cap_row".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array".
+Reading "sky130_fd_bd_sram__openram_dp_cell_cap_col".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array_0".
+Reading "sky130_fd_bd_sram__openram_dp_cell_dummy".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dummy_array".
+Reading "sky130_fd_bd_sram__openram_dp_cell_replica".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_column_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_column".
+Reading "sky130_fd_bd_sram__openram_dp_cell".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_bitcell_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_bitcell_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_bank".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8".
+Reading "sky130_fd_sc_hd__and2_2".
+Reading "sky130_fd_sc_hd__or4_2".
+Reading "sky130_fd_sc_hd__o41a_2".
+Reading "sky130_fd_sc_hd__o311a_2".
+Reading "sky130_fd_sc_hd__and3_2".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__clkbuf_2".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__clkinv_2".
+Reading "sky130_fd_sc_hd__mux2_1".
+Reading "sky130_fd_sc_hd__o32a_2".
+Reading "sky130_fd_sc_hd__clkinv_8".
+Reading "sky130_fd_sc_hd__a221o_2".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_fd_sc_hd__o31a_2".
+Reading "sky130_fd_sc_hd__a22oi_2".
+Reading "sky130_fd_sc_hd__a21bo_2".
+Reading "sky130_fd_sc_hd__a21o_2".
+Reading "sky130_fd_sc_hd__o22a_2".
+Reading "sky130_fd_sc_hd__o211a_2".
+Reading "sky130_fd_sc_hd__and4_2".
+Reading "sky130_fd_sc_hd__a31o_2".
+Reading "sky130_fd_sc_hd__nand2_2".
+Reading "sky130_fd_sc_hd__o2bb2ai_2".
+Reading "sky130_fd_sc_hd__o21ai_2".
+Reading "sky130_fd_sc_hd__o221a_2".
+Reading "sky130_fd_sc_hd__a2bb2o_2".
+Reading "sky130_fd_sc_hd__or2_2".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__or3_2".
+Reading "sky130_fd_sc_hd__a21oi_2".
+Reading "sky130_fd_sc_hd__nor2_2".
+Reading "sky130_fd_sc_hd__a22o_2".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "sky130_fd_sc_hd__dfrtp_2".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__buf_1".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_ef_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__dfrtp_4".
+Reading "sky130_fd_sc_hd__dfrtp_1".
+Reading "sky130_fd_sc_hd__dfstp_2".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__xnor2_1".
+Reading "sky130_fd_sc_hd__xor2_1".
+Reading "sky130_fd_sc_hd__o21ai_1".
+Reading "sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "sky130_fd_sc_hd__or2b_1".
+Reading "sky130_fd_sc_hd__o211a_1".
+Reading "sky130_fd_sc_hd__or2_1".
+Reading "sky130_fd_sc_hd__dfstp_1".
+Reading "sky130_fd_sc_hd__a21oi_1".
+Reading "sky130_fd_sc_hd__a221o_1".
+Reading "sky130_fd_sc_hd__a31o_1".
+Reading "sky130_fd_sc_hd__nand2_1".
+Reading "sky130_fd_sc_hd__o21a_1".
+Reading "sky130_fd_sc_hd__o2bb2a_1".
+Reading "sky130_fd_sc_hd__nor2_1".
+Reading "sky130_fd_sc_hd__o21ai_4".
+Reading "sky130_fd_sc_hd__clkbuf_4".
+Reading "sky130_fd_sc_hd__and3_1".
+Reading "sky130_fd_sc_hd__nand3_2".
+Reading "sky130_fd_sc_hd__and2_1".
+Reading "sky130_fd_sc_hd__a21o_1".
+Reading "sky130_fd_sc_hd__a311o_1".
+Reading "sky130_fd_sc_hd__a21bo_1".
+Reading "sky130_fd_sc_hd__a2bb2o_1".
+Reading "sky130_fd_sc_hd__o22a_1".
+Reading "sky130_fd_sc_hd__a211o_1".
+Reading "sky130_fd_sc_hd__a22oi_1".
+Reading "sky130_fd_sc_hd__a22o_1".
+Reading "sky130_fd_sc_hd__and4bb_2".
+Reading "sky130_fd_sc_hd__or2_4".
+Reading "sky130_fd_sc_hd__or4b_1".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "sky130_fd_sc_hd__mux2_2".
+Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hd__a32o_1".
+Reading "sky130_fd_sc_hd__and2b_1".
+Reading "sky130_fd_sc_hd__a22o_4".
+Reading "sky130_fd_sc_hd__or3_1".
+Reading "sky130_fd_sc_hd__buf_12".
+Reading "sky130_fd_sc_hd__o221a_1".
+Reading "sky130_fd_sc_hd__xor2_2".
+Reading "sky130_fd_sc_hd__nand3_1".
+Reading "sky130_fd_sc_hd__or4b_4".
+Reading "sky130_fd_sc_hd__o211ai_4".
+Reading "sky130_fd_sc_hd__mux4_1".
+Reading "sky130_fd_sc_hd__or3b_1".
+Reading "sky130_fd_sc_hd__mux4_2".
+Reading "sky130_fd_sc_hd__or2b_4".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__nand2_8".
+Reading "sky130_fd_sc_hd__or4_1".
+Reading "sky130_fd_sc_hd__clkbuf_8".
+Reading "sky130_fd_sc_hd__buf_6".
+Reading "sky130_fd_sc_hd__a221o_4".
+Reading "sky130_fd_sc_hd__mux2_8".
+Reading "sky130_fd_sc_hd__a22oi_4".
+Reading "sky130_fd_sc_hd__a221oi_4".
+Reading "sky130_fd_sc_hd__a21o_4".
+Reading "sky130_fd_sc_hd__o221ai_4".
+Reading "sky130_fd_sc_hd__a41o_4".
+Reading "sky130_fd_sc_hd__a211o_4".
+Reading "sky130_fd_sc_hd__o31a_1".
+Reading "sky130_fd_sc_hd__nor4_4".
+Reading "sky130_fd_sc_hd__or4_4".
+Reading "sky130_fd_sc_hd__o211ai_1".
+Reading "sky130_fd_sc_hd__o221a_4".
+Reading "sky130_fd_sc_hd__o31a_4".
+Reading "sky130_fd_sc_hd__o311a_1".
+Reading "sky130_fd_sc_hd__nand4_1".
+Reading "sky130_fd_sc_hd__o211ai_2".
+Reading "sky130_fd_sc_hd__nand4b_1".
+Reading "sky130_fd_sc_hd__and4_1".
+Reading "sky130_fd_sc_hd__or3_4".
+Reading "sky130_fd_sc_hd__and4_4".
+Reading "sky130_fd_sc_hd__o31ai_1".
+Reading "sky130_fd_sc_hd__or4bb_1".
+Reading "sky130_fd_sc_hd__o21ba_1".
+Reading "sky130_fd_sc_hd__and4b_2".
+Reading "sky130_fd_sc_hd__a221oi_1".
+Reading "sky130_fd_sc_hd__nand4_4".
+Reading "sky130_fd_sc_hd__and4b_4".
+Reading "sky130_fd_sc_hd__and4bb_4".
+Reading "sky130_fd_sc_hd__nand2_4".
+Reading "sky130_fd_sc_hd__or4bb_4".
+Reading "sky130_fd_sc_hd__and4b_1".
+Reading "sky130_fd_sc_hd__a32o_4".
+Reading "sky130_fd_sc_hd__dlygate4sd1_1".
+Reading "sky130_fd_sc_hd__o32a_1".
+Reading "sky130_fd_sc_hd__nor4b_4".
+Reading "sky130_fd_sc_hd__nor3_4".
+Reading "sky130_fd_sc_hd__o31ai_4".
+Reading "sky130_fd_sc_hd__and3b_4".
+Reading "sky130_fd_sc_hd__and3_4".
+Reading "sky130_fd_sc_hd__o31ai_2".
+Reading "sky130_fd_sc_hd__a211oi_4".
+Reading "sky130_fd_sc_hd__o22a_4".
+Reading "sky130_fd_sc_hd__nor4_2".
+Reading "sky130_fd_sc_hd__a41o_2".
+Reading "sky130_fd_sc_hd__inv_6".
+Reading "sky130_fd_sc_hd__nand3_4".
+Reading "sky130_fd_sc_hd__o2bb2ai_1".
+Reading "sky130_fd_sc_hd__clkinv_4".
+Reading "sky130_fd_sc_hd__a2111o_4".
+Reading "sky130_fd_sc_hd__and2b_4".
+Reading "sky130_fd_sc_hd__a2bb2o_4".
+Reading "sky130_fd_sc_hd__o21a_4".
+Reading "sky130_fd_sc_hd__o211a_4".
+Reading "sky130_fd_sc_hd__a21oi_4".
+Reading "sky130_fd_sc_hd__o311a_4".
+Reading "sky130_fd_sc_hd__a211o_2".
+Reading "sky130_fd_sc_hd__a32oi_4".
+Reading "sky130_fd_sc_hd__and3b_2".
+Reading "sky130_fd_sc_hd__and3b_1".
+Reading "sky130_fd_sc_hd__nor4_1".
+Reading "sky130_fd_sc_hd__and4bb_1".
+Reading "sky130_fd_sc_hd__a211oi_1".
+Reading "sky130_fd_sc_hd__mux2_4".
+Reading "sky130_fd_sc_hd__nor3_2".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "sky130_fd_sc_hd__or4b_2".
+Reading "ycr4_iconnect".
+Reading "sky130_fd_sc_hd__o21a_2".
+Reading "sky130_fd_sc_hd__a32o_2".
+Reading "sky130_fd_sc_hd__o22ai_2".
+Reading "sky130_fd_sc_hd__a311o_2".
+Reading "sky130_fd_sc_hd__a41o_1".
+Reading "sky130_fd_sc_hd__o21bai_2".
+Reading "sky130_fd_sc_hd__nor3_1".
+Reading "sky130_fd_sc_hd__a21boi_1".
+Reading "sky130_fd_sc_hd__xnor2_2".
+Reading "sky130_fd_sc_hd__a2111o_2".
+Reading "sky130_fd_sc_hd__o21bai_1".
+Reading "sky130_fd_sc_hd__o2111a_1".
+Reading "sky130_fd_sc_hd__a31oi_4".
+Reading "sky130_fd_sc_hd__a2111oi_4".
+Reading "sky130_fd_sc_hd__nand4_2".
+Reading "sky130_fd_sc_hd__o22ai_1".
+Reading "sky130_fd_sc_hd__a31oi_1".
+Reading "sky130_fd_sc_hd__a311oi_1".
+Reading "sky130_fd_sc_hd__or2b_2".
+Reading "sky130_fd_sc_hd__xnor2_4".
+Reading "sky130_fd_sc_hd__or3b_2".
+Reading "sky130_fd_sc_hd__o41a_1".
+Reading "sky130_fd_sc_hd__nor3b_2".
+Reading "sky130_fd_sc_hd__nand2b_2".
+Reading "sky130_fd_sc_hd__nor4b_2".
+Reading "sky130_fd_sc_hd__nand3b_1".
+Reading "sky130_fd_sc_hd__a211oi_2".
+Reading "sky130_fd_sc_hd__o21ba_2".
+Reading "sky130_fd_sc_hd__nand3b_2".
+Reading "sky130_fd_sc_hd__o22ai_4".
+Reading "sky130_fd_sc_hd__a2111o_1".
+Reading "sky130_fd_sc_hd__a31oi_2".
+Reading "sky130_fd_sc_hd__nor2b_1".
+Reading "sky130_fd_sc_hd__nor3b_1".
+Reading "sky130_fd_sc_hd__a2111oi_1".
+Reading "sky130_fd_sc_hd__and2b_2".
+Reading "sky130_fd_sc_hd__dfxtp_1".
+Reading "sky130_fd_sc_hd__nor4b_1".
+Reading "sky130_fd_sc_hd__a311oi_2".
+Reading "sky130_fd_sc_hd__xor2_4".
+Reading "sky130_fd_sc_hd__dfxtp_2".
+Reading "sky130_fd_sc_hd__a21bo_4".
+Reading "sky130_fd_sc_hd__or3b_4".
+Reading "sky130_fd_sc_hd__or4bb_2".
+Reading "sky130_fd_sc_hd__nor2_8".
+Reading "sky130_fd_sc_hd__inv_4".
+Reading "sky130_fd_sc_hd__o2111ai_4".
+Reading "ycr_core_top".
+Reading "sky130_fd_sc_hd__o221ai_2".
+Reading "sky130_fd_sc_hd__o2111ai_2".
+Reading "sky130_fd_sc_hd__o2bb2a_2".
+Reading "sky130_fd_sc_hd__o2111ai_1".
+Reading "sky130_fd_sc_hd__a2111oi_2".
+Reading "sky130_fd_sc_hd__a221oi_2".
+Reading "sky130_fd_sc_hd__o221ai_1".
+Reading "sky130_fd_sc_hd__o21bai_4".
+Reading "sky130_fd_sc_hd__o32ai_1".
+Reading "sky130_fd_sc_hd__dfstp_4".
+Reading "sky130_fd_sc_hd__o41a_4".
+Reading "sky130_fd_sc_hd__o2bb2a_4".
+Reading "sky130_fd_sc_hd__a21boi_2".
+Reading "sky130_fd_sc_hd__nand2b_1".
+Reading "sky130_fd_sc_hd__o2111a_2".
+Reading "sky130_fd_sc_hd__clkdlybuf4s15_2".
+Reading "ycr_intf".
+Reading "sky130_fd_sc_hd__einvp_2".
+Reading "sky130_fd_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__clkinv_1".
+Reading "sky130_fd_sc_hd__einvn_8".
+Reading "sky130_fd_sc_hd__einvn_4".
+Reading "sky130_fd_sc_hd__einvp_1".
+Reading "digital_pll".
+Reading "sky130_fd_sc_hd__clkdlybuf4s25_1".
+Reading "sky130_fd_sc_hd__nand4b_2".
+Reading "wb_host".
+Reading "sky130_fd_sc_hd__a31o_4".
+Reading "sky130_fd_sc_hd__nor2b_2".
+Reading "sky130_fd_sc_hd__nor3b_4".
+Reading "uart_i2c_usb_spi_top".
+Reading "sky130_fd_sc_hd__a41oi_1".
+Reading "sky130_fd_sc_hd__a2bb2oi_4".
+Reading "wb_interconnect".
+Reading "pinmux".
+Reading "qspim_top".
+Reading "user_project_wrapper".
+ Generating output for cell sky130_ef_io__com_bus_slice_20um
+ Generating output for cell sky130_fd_io__corner_bus_overlay
+ Generating output for cell sky130_ef_io__corner_pad
+ Generating output for cell sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um
+ Generating output for cell sky130_ef_io__com_bus_slice_1um
+ Generating output for cell sky130_ef_io__com_bus_slice_5um
+ Generating output for cell sky130_ef_io__com_bus_slice_10um
+ Generating output for cell sky130_fd_pr__hvdfl1sd__example_5595914180851
+ Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808664
+ Generating output for cell sky130_fd_io__sio_clamp_pcap_4x5
+ Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808680
+ Generating output for cell sky130_fd_io__esd_rcclamp_nfetcap
+ Generating output for cell sky130_fd_pr__dfl1sd__example_55959141808336
+ Generating output for cell sky130_fd_pr__dfl1sd2__example_55959141808666
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808665
+ Generating output for cell sky130_fd_pr__dfl1sd__example_55959141808678
+ Generating output for cell sky130_fd_pr__dfl1sd2__example_55959141808679
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808677
+ Generating output for cell sky130_fd_pr__via_pol1__example_5595914180839
+ Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808667
+ Generating output for cell sky130_fd_pr__hvdftpl1s__example_55959141808671
+ Generating output for cell sky130_fd_pr__hvdftpl1s2__example_55959141808672
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808673
+ Generating output for cell sky130_fd_pr__dfl1__example_55959141808663
+ Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808660
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808670
+ Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808668
+ Generating output for cell sky130_fd_pr__hvdftpl1s__example_55959141808675
+ Generating output for cell sky130_fd_pr__hvdftpl1s2__example_55959141808676
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808674
+ Generating output for cell sky130_fd_pr__dfl1__example_55959141808662
+ Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808661
+ Generating output for cell sky130_fd_pr__via_l1m1__example_559591418084
+ Generating output for cell sky130_fd_pr__genrivetdlring__example_559591418082
+ Generating output for cell sky130_fd_pr__gendlring__example_559591418081
+ Generating output for cell sky130_fd_pr__padplhp__example_559591418080
+ Generating output for cell sky130_fd_io__pad_esd
+ Generating output for cell sky130_fd_io__com_bus_slice
+ Generating output for cell sky130_fd_io__com_bus_hookup
+ Generating output for cell sky130_fd_io__com_busses_esd
+ Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808669
+ Generating output for cell sky130_fd_io__top_ground_hvc_wpad
+ Generating output for cell sky130_fd_io__overlay_vssa_hvc
+ Generating output for cell sky130_ef_io__hvc_vdda_overlay
+ Generating output for cell sky130_ef_io__vssa_hvc_clamped_pad
+ Generating output for cell sky130_fd_pr__hvdfm1sd2__example_55959141808719
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808767
+ Generating output for cell sky130_fd_pr__hvdfm1sd2__example_55959141808765
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808764
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808720
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808718
+ Generating output for cell sky130_fd_pr__hvdfm1sd2__example_55959141808717
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808716
+ Generating output for cell sky130_fd_pr__hvdfm1sd2__example_55959141808243
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808723
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808722
+ Generating output for cell sky130_fd_pr__hvdfm1sd2__example_5595914180890
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808721
+ Generating output for cell sky130_fd_io__xres_inv_hysv2
+ Generating output for cell sky130_fd_pr__res_generic_po__example_5595914180838
+ Generating output for cell sky130_fd_io__tk_tie_r_out_esd
+ Generating output for cell sky130_fd_io__res250_sub_small
+ Generating output for cell sky130_fd_io__res250only_small
+ Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808264
+ Generating output for cell sky130_fd_pr__via_l1m1__example_5595914180858
+ Generating output for cell sky130_fd_pr__via_pol1__example_5595914180833
+ Generating output for cell sky130_fd_pr__res_generic_po__example_5595914180864
+ Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808715
+ Generating output for cell sky130_fd_pr__res_bent_po__example_5595914180863
+ Generating output for cell sky130_fd_pr__res_bent_po__example_5595914180862
+ Generating output for cell sky130_fd_io__tk_em1s_cdns_55959141808288
+ Generating output for cell sky130_fd_io__tk_em1s_cdns_5595914180859
+ Generating output for cell sky130_fd_io__tk_em1o_cdns_55959141808289
+ Generating output for cell sky130_fd_io__com_res_weak_v2
+ Generating output for cell sky130_fd_pr__via_pol1__example_55959141808274
+ Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808728
+ Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808727
+ Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808726
+ Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808725
+ Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808724
+ Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808554
+ Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808553
+ Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808552
+ Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808551
+ Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808402
+ Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808350
+ Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808261
+ Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808260
+ Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808259
+ Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808400
+ Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808372
+ Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808326
+ Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808290
+ Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808128
+ Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808127
+ Generating output for cell sky130_fd_pr__via_l1m1__example_5595914180897
+ Generating output for cell sky130_fd_pr__dfl1sd__example_5595914180819
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808555
+ Generating output for cell sky130_fd_pr__via_pol1__example_55959141808147
+ Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808157
+ Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808156
+ Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808155
+ Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808154
+ Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808153
+ Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808152
+ Generating output for cell sky130_fd_pr__tpl1__example_55959141808151
+ Generating output for cell sky130_fd_pr__tpl1__example_55959141808150
+ Generating output for cell sky130_fd_pr__tpl1__example_55959141808149
+ Generating output for cell sky130_fd_pr__tpl1__example_55959141808148
+ Generating output for cell sky130_fd_pr__dfl1__example_55959141808158
+ Generating output for cell sky130_fd_io__signal_5_sym_hv_local_5term
+ Generating output for cell sky130_fd_io__gpio_buf_localesdv2
+ Generating output for cell sky130_fd_pr__via_pol1__example_559591418083
+ Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808137
+ Generating output for cell sky130_fd_pr__dfl1sd__example_559591418086
+ Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808371
+ Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808370
+ Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808369
+ Generating output for cell sky130_fd_io__hvsbt_inv_x1
+ Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808316
+ Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808421
+ Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808385
+ Generating output for cell sky130_fd_pr__dfl1sd__example_559591418088
+ Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808422
+ Generating output for cell sky130_fd_io__hvsbt_inv_x2
+ Generating output for cell sky130_fd_pr__via_pol1__example_55959141808612
+ Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808616
+ Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808615
+ Generating output for cell sky130_fd_io__hvsbt_inv_x4
+ Generating output for cell sky130_fd_pr__hvdfm1sd__example_5595914180848
+ Generating output for cell sky130_fd_pr__hvdfm1sd2__example_5595914180849
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808766
+ Generating output for cell sky130_fd_pr__via_m2m3__example_55959141808714
+ Generating output for cell sky130_fd_pr__via_pol1_centered__example_559591418081
+ Generating output for cell sky130_fd_io__tk_em2s_cdns_55959141808652
+ Generating output for cell sky130_fd_io__tk_em2o_cdns_55959141808653
+ Generating output for cell sky130_fd_pr__via_l1m1_centered__example_5595914180812
+ Generating output for cell sky130_fd_pr__via_l1m1_centered__example_5595914180811
+ Generating output for cell sky130_fd_pr__via_l1m1_centered__example_559591418086
+ Generating output for cell sky130_fd_pr__via_l1m1_centered__example_559591418084
+ Generating output for cell sky130_fd_pr__hvdftpm1s2__example_55959141808659
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808658
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808657
+ Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808202
+ Generating output for cell sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2
+ Generating output for cell sky130_fd_io__gpio_pudrvr_strong_axres4v2
+ Generating output for cell sky130_fd_pr__via_pol1__example_55959141808273
+ Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808740
+ Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808739
+ Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808738
+ Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808737
+ Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808736
+ Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808735
+ Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808734
+ Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808733
+ Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808732
+ Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808731
+ Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808730
+ Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808752
+ Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808751
+ Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808750
+ Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808749
+ Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808748
+ Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808747
+ Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808746
+ Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808745
+ Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808744
+ Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808743
+ Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808742
+ Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808741
+ Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808324
+ Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808270
+ Generating output for cell sky130_fd_pr__dfl1__example_55959141808187
+ Generating output for cell sky130_fd_pr__res_generic_nd__example_55959141808755
+ Generating output for cell sky130_fd_pr__res_generic_nd__example_55959141808754
+ Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808338
+ Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808337
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808763
+ Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808700
+ Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808559
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808762
+ Generating output for cell sky130_fd_pr__dfl1__example_55959141808729
+ Generating output for cell sky130_fd_io__xres_tk_p_em1o_cdns_55959141808758
+ Generating output for cell sky130_fd_io__xres_tk_p_em1o_cdns_55959141808757
+ Generating output for cell sky130_fd_io__xres_tk_p_em1o_cdns_55959141808756
+ Generating output for cell sky130_fd_io__xres_tk_p_em1c_cdns_55959141808761
+ Generating output for cell sky130_fd_io__xres_tk_p_em1c_cdns_55959141808760
+ Generating output for cell sky130_fd_io__xres_tk_p_em1c_cdns_55959141808759
+ Generating output for cell sky130_fd_io__xres_p_em1c_cdns_55959141808753
+ Generating output for cell sky130_fd_io__xres2v2_rcfilter_lpfv2
+ Generating output for cell sky130_fd_io__tk_em1o_cdns_5595914180860
+ Generating output for cell sky130_fd_pr__res_bent_po__example_5595914180861
+ Generating output for cell sky130_fd_io__com_res_weak_bentbigres
+ Generating output for cell sky130_fd_io__com_res_weak
+ Generating output for cell sky130_fd_pr__via_l1m1__example_5595914180857
+ Generating output for cell sky130_fd_pr__hvdftpm1s2__example_55959141808649
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808651
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808650
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808648
+ Generating output for cell sky130_fd_pr__hvdftpl1s__example_55959141808646
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808647
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808645
+ Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808378
+ Generating output for cell sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2
+ Generating output for cell sky130_fd_io__gpio_pddrvr_strong_xres4v2
+ Generating output for cell sky130_fd_io__top_gpio_pad
+ Generating output for cell sky130_fd_io__com_busses
+ Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808768
+ Generating output for cell sky130_fd_pr__res_bent_nd__example_55959141808769
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808787
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808786
+ Generating output for cell sky130_fd_pr__hvdfm1sd__example_55959141808782
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808785
+ Generating output for cell sky130_fd_pr__hvdfm1sd2__example_55959141808449
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808784
+ Generating output for cell sky130_fd_pr__hvdfm1sd__example_55959141808452
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808783
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808781
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808780
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808779
+ Generating output for cell sky130_fd_pr__hvdfm1sd__example_55959141808233
+ Generating output for cell sky130_fd_pr__hvdfm1sd2__example_5595914180827
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808778
+ Generating output for cell sky130_fd_pr__hvdfm1sd__example_5595914180835
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808777
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808776
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808775
+ Generating output for cell sky130_fd_pr__hvdfm1sd__example_55959141808242
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808774
+ Generating output for cell sky130_fd_pr__hvdfm1sd2__example_5595914180829
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808773
+ Generating output for cell sky130_fd_pr__hvdfm1sd__example_55959141808237
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808772
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808771
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808770
+ Generating output for cell sky130_fd_io__tap_1
+ Generating output for cell sky130_fd_io__inv_1
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_559591418085
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_559591418089
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_559591418087
+ Generating output for cell sky130_fd_io__hvsbt_nand2
+ Generating output for cell sky130_fd_io__xres4v2_in_buf
+ Generating output for cell sky130_fd_io__top_xres4v2
+ Generating output for cell sky130_fd_sc_hd__fill_4
+ Generating output for cell sky130_fd_sc_hd__fill_8
+ Generating output for cell constant_block
+ Generating output for cell sky130_fd_io__res75only_small
+ Generating output for cell sky130_fd_io__com_bus_slice_m4
+ Generating output for cell sky130_fd_io__overlay_gpiov2_m4
+ Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808420
+ Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808419
+ Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808418
+ Generating output for cell sky130_fd_io__hvsbt_nor
+ Generating output for cell sky130_fd_io__hvsbt_nand2v2
+ Generating output for cell sky130_fd_io__gpiov2_ictl_logic
+ Generating output for cell sky130_fd_pr__dfl1sd__example_55959141808190
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808611
+ Generating output for cell sky130_fd_pr__dfl1sd__example_5595914180811
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808549
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808548
+ Generating output for cell sky130_fd_pr__dfl1sd2__example_55959141808191
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808189
+ Generating output for cell sky130_fd_pr__dfl1sd__example_55959141808517
+ Generating output for cell sky130_fd_pr__dfl1sd2__example_55959141808518
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808610
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808609
+ Generating output for cell sky130_fd_pr__dfl1sd__example_5595914180815
+ Generating output for cell sky130_fd_pr__dfl1sd2__example_5595914180816
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808608
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808604
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808533
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808529
+ Generating output for cell sky130_fd_pr__dfl1sd2__example_5595914180884
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808230
+ Generating output for cell sky130_fd_io__gpiov2_in_buf
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808537
+ Generating output for cell sky130_fd_pr__dfl1sd__example_55959141808106
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808481
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808607
+ Generating output for cell sky130_fd_pr__dfl1sd__example_55959141808504
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808600
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808550
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808528
+ Generating output for cell sky130_fd_io__gpiov2_ipath_hvls
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808595
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_5595914180825
+ Generating output for cell sky130_fd_io__gpiov2_inbuf_lvinv_x1
+ Generating output for cell sky130_fd_pr__dfl1sd2__example_5595914180812
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808599
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808598
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808597
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808596
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808547
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808546
+ Generating output for cell sky130_fd_io__gpiov2_ipath_lvls
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808606
+ Generating output for cell sky130_fd_pr__dfl1sd2__example_5595914180875
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808605
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808540
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808603
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808602
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808601
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808535
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808527
+ Generating output for cell sky130_fd_io__gpiov2_vcchib_in_buf
+ Generating output for cell sky130_fd_io__gpiov2_ibuf_se
+ Generating output for cell sky130_fd_io__gpiov2_buf_localesd
+ Generating output for cell sky130_fd_io__gpiov2_ipath
+ Generating output for cell sky130_fd_io__tk_em2s_cdns_55959141808438
+ Generating output for cell sky130_fd_io__tk_em2o_cdns_55959141808439
+ Generating output for cell sky130_fd_io__tk_em1s_cdns_5595914180882
+ Generating output for cell sky130_fd_io__tk_em1s_cdns_5595914180881
+ Generating output for cell sky130_fd_io__tk_em1o_cdns_5595914180880
+ Generating output for cell sky130_fd_io__tk_em1o_cdns_5595914180879
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808430
+ Generating output for cell sky130_fd_pr__dfl1sd__example_5595914180823
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_5595914180822
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_5595914180813
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808624
+ Generating output for cell sky130_fd_pr__dfl1sd__example_55959141808510
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808623
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808622
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808621
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808620
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808619
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808618
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808116
+ Generating output for cell sky130_fd_io__com_ctl_lsv2
+ Generating output for cell sky130_fd_pr__via_pol1__example_55959141808394
+ Generating output for cell sky130_fd_pr__via_pol1__example_55959141808298
+ Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808440
+ Generating output for cell sky130_fd_pr__via_l1m1__example_5595914180878
+ Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808434
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808435
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808433
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808432
+ Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808102
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808431
+ Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808115
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808429
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808428
+ Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808100
+ Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808140
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808427
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808426
+ Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808280
+ Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808425
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808424
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808423
+ Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808306
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808383
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808382
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808380
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808379
+ Generating output for cell sky130_fd_io__com_ctl_ls_v2
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808617
+ Generating output for cell sky130_fd_io__com_ctl_ls_en_1_v2
+ Generating output for cell sky130_fd_io__com_ctl_ls_1v2
+ Generating output for cell sky130_fd_io__gpiov2_ctl_lsbank
+ Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808614
+ Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808613
+ Generating output for cell sky130_fd_io__hvsbt_inv_x8v2
+ Generating output for cell sky130_fd_io__hvsbt_inv_x8
+ Generating output for cell sky130_fd_io__com_ctl_ls
+ Generating output for cell sky130_fd_io__com_ctl_hldv2
+ Generating output for cell sky130_fd_io__gpiov2_ctl
+ Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808178
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808591
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808594
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808593
+ Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808488
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808592
+ Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808586
+ Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808122
+ Generating output for cell sky130_fd_pr__dfl1sd__example_55959141808123
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808477
+ Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808476
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808475
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808589
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808570
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808569
+ Generating output for cell sky130_fd_io__gpiov2_amux_ctl_lshv2hv
+ Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808588
+ Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808587
+ Generating output for cell sky130_fd_io__gpiov2_amux_ctl_lshv2hv2
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808590
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808460
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808468
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808467
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808466
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808465
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808464
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808463
+ Generating output for cell sky130_fd_io__gpiov2_amux_ctl_ls
+ Generating output for cell sky130_fd_io__gpiov2_amux_ctl_inv_1
+ Generating output for cell sky130_fd_io__gpiov2_amux_ls
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808573
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808572
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808579
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808578
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808577
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808576
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808566
+ Generating output for cell sky130_fd_pr__dfl1sd__example_5595914180868
+ Generating output for cell sky130_fd_pr__dfl1sd2__example_5595914180869
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808565
+ Generating output for cell sky130_fd_io__gpiov2_amx_pucsd_inv
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808441
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808571
+ Generating output for cell sky130_fd_io__gpiov2_amx_inv4
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808567
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808568
+ Generating output for cell sky130_fd_io__gpiov2_amux_drvr_lshv2hv
+ Generating output for cell sky130_fd_io__gpiov2_amux_drvr_lshv2hv2
+ Generating output for cell sky130_fd_pr__hvdfm1sd__example_55959141808581
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808580
+ Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808278
+ Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808462
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808583
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808582
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808498
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808497
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808496
+ Generating output for cell sky130_fd_io__gpiov2_amux_drvr_ls
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808574
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808575
+ Generating output for cell sky130_fd_io__amx_inv1
+ Generating output for cell sky130_fd_io__gpiov2_amux_drvr
+ Generating output for cell sky130_fd_io__xor2_1
+ Generating output for cell sky130_fd_io__nor2_1
+ Generating output for cell sky130_fd_io__nand2_1
+ Generating output for cell sky130_fd_pr__hvdfm1sd__example_55959141808200
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808457
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808451
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808450
+ Generating output for cell sky130_fd_pr__hvdfl1sd__example_5595914180894
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808584
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808455
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808447
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808445
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808248
+ Generating output for cell sky130_fd_io__gpiov2_amux_nand5
+ Generating output for cell sky130_fd_pr__dfm1sd__example_55959141808258
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808585
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808446
+ Generating output for cell sky130_fd_io__gpiov2_amux_nand4
+ Generating output for cell sky130_fd_io__gpiov2_amux_decoder
+ Generating output for cell sky130_fd_io__gpiov2_amux_ctl_logic
+ Generating output for cell sky130_fd_pr__hvdfm1sd2__example_55959141808563
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808564
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808562
+ Generating output for cell sky130_fd_pr__hvdfm1sd2__example_55959141808251
+ Generating output for cell sky130_fd_pr__dfm1sd2__example_55959141808561
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808560
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808558
+ Generating output for cell sky130_fd_io__amux_switch_1v2b
+ Generating output for cell sky130_fd_io__gpiov2_amux
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808416
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808417
+ Generating output for cell sky130_fd_io__hvsbt_xorv2
+ Generating output for cell sky130_fd_io__hvsbt_xor
+ Generating output for cell sky130_fd_io__com_ctl_ls_octl
+ Generating output for cell sky130_fd_io__gpiov2_octl
+ Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808267
+ Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808266
+ Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808642
+ Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808184
+ Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808141
+ Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808643
+ Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808183
+ Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808139
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808636
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808635
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808634
+ Generating output for cell sky130_fd_pr__dfl1sd2__example_55959141808633
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808632
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808630
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808638
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808637
+ Generating output for cell sky130_fd_io__gpiov2_pdpredrvr_strong_nr3
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808629
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808628
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808627
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808626
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808354
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808631
+ Generating output for cell sky130_fd_io__gpiov2_pdpredrvr_strong_nr2
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_5595914180888
+ Generating output for cell sky130_fd_io__gpiov2_octl_mux
+ Generating output for cell sky130_fd_pr__via_pol1__example_55959141808322
+ Generating output for cell sky130_fd_pr__via_pol1__example_55959141808321
+ Generating output for cell sky130_fd_pr__via_pol1__example_55959141808320
+ Generating output for cell sky130_fd_pr__via_pol1__example_55959141808294
+ Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808325
+ Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808323
+ Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808291
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808641
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808640
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808639
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808348
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808347
+ Generating output for cell sky130_fd_pr__hvdfl1sd__example_55959141808194
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808346
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808345
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808344
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808343
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808334
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808333
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808332
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808331
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808330
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808329
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808304
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808134
+ Generating output for cell sky130_fd_io__tk_em1o_cdns_55959141808328
+ Generating output for cell sky130_fd_io__tk_em1o_cdns_55959141808327
+ Generating output for cell sky130_fd_io__com_pdpredrvr_pbiasv2
+ Generating output for cell sky130_fd_io__gpiov2_pdpredrvr_strong
+ Generating output for cell sky130_fd_pr__via_pol1__example_55959141808272
+ Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808271
+ Generating output for cell sky130_fd_pr__hvdfl1sd2__example_55959141808143
+ Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808142
+ Generating output for cell sky130_fd_pr__model__pfet_highvoltage__example_55959141808101
+ Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_55959141808144
+ Generating output for cell sky130_fd_pr__model__nfet_highvoltage__example_5595914180899
+ Generating output for cell sky130_fd_pr__via_pol1__example_55959141808275
+ Generating output for cell sky130_fd_pr__via_m1m2__example_55959141808276
+ Generating output for cell sky130_fd_pr__res_generic_po__example_55959141808286
+ Generating output for cell sky130_fd_pr__res_generic_po__example_55959141808285
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808284
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808283
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808644
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808287
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808282
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808281
+ Generating output for cell sky130_fd_io__gpiov2_pupredrvr_strong_nd2_a
+ Generating output for cell sky130_fd_io__gpiov2_pupredrvr_strong_nd2
+ Generating output for cell sky130_fd_pr__via_pol1__example_55959141808297
+ Generating output for cell sky130_fd_pr__via_pol1__example_55959141808296
+ Generating output for cell sky130_fd_pr__via_pol1__example_55959141808295
+ Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808293
+ Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808292
+ Generating output for cell sky130_fd_pr__tpl1__example_55959141808300
+ Generating output for cell sky130_fd_pr__tpl1__example_55959141808299
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808319
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808318
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808317
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808315
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808314
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808313
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808312
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808311
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808310
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808309
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808308
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808307
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808305
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808303
+ Generating output for cell sky130_fd_io__tk_em1s_cdns_55959141808301
+ Generating output for cell sky130_fd_io__tk_em1o_cdns_55959141808302
+ Generating output for cell sky130_fd_io__feascom_pupredrvr_nbiasv2
+ Generating output for cell sky130_fd_io__gpio_pupredrvr_strongv2
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808361
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808360
+ Generating output for cell sky130_fd_io__feas_com_pupredrvr_weak
+ Generating output for cell sky130_fd_pr__via_pol1__example_5595914180854
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808363
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808362
+ Generating output for cell sky130_fd_io__com_pupredrvr_strong_slowv2
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808366
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808365
+ Generating output for cell sky130_fd_io__com_pdpredrvr_weakv2
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808364
+ Generating output for cell sky130_fd_io__com_pdpredrvr_strong_slowv2
+ Generating output for cell sky130_fd_io__gpiov2_obpredrvr
+ Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808368
+ Generating output for cell sky130_fd_pr__tpl1__example_55959141808625
+ Generating output for cell sky130_fd_pr__via_pol1__example_55959141808373
+ Generating output for cell sky130_fd_pr__tpl1__example_55959141808374
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808393
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808392
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808391
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808390
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808389
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808388
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808387
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808386
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808384
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808381
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808377
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808376
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808375
+ Generating output for cell sky130_fd_io__gpio_dat_lsv2
+ Generating output for cell sky130_fd_io__gpio_dat_ls_1v2
+ Generating output for cell sky130_fd_pr__via_pol1__example_55959141808398
+ Generating output for cell sky130_fd_pr__via_pol1__example_55959141808397
+ Generating output for cell sky130_fd_pr__via_pol1__example_55959141808396
+ Generating output for cell sky130_fd_pr__via_pol1__example_55959141808395
+ Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808401
+ Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808399
+ Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808269
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808410
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808409
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808408
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808407
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808406
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808405
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808404
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808403
+ Generating output for cell sky130_fd_io__com_cclat
+ Generating output for cell sky130_fd_io__com_opath_datoev2
+ Generating output for cell sky130_fd_io__gpiov2_octl_dat
+ Generating output for cell sky130_fd_pr__via_pol1_centered__example_559591418080
+ Generating output for cell sky130_fd_pr__via_l1m1__example_5595914180832
+ Generating output for cell sky130_fd_pr__res_generic_po__example_5595914180856
+ Generating output for cell sky130_fd_pr__res_generic_po__example_5595914180855
+ Generating output for cell sky130_fd_pr__res_generic_po__example_5595914180853
+ Generating output for cell sky130_fd_io__tk_em1s_cdns_5595914180852
+ Generating output for cell sky130_fd_pr__via_l1m1_centered__example_559591418083
+ Generating output for cell sky130_fd_pr__via_l1m1_centered__example_559591418082
+ Generating output for cell sky130_fd_io__nfet_con_diff_wo_abt_270v2
+ Generating output for cell sky130_fd_io__gpiov2_pddrvr_strong
+ Generating output for cell sky130_fd_pr__via_l1m1_centered__example_559591418085
+ Generating output for cell sky130_fd_io__pfet_con_diff_wo_abt_270v2
+ Generating output for cell sky130_fd_io__gpio_pudrvr_strongv2
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_5595914180850
+ Generating output for cell sky130_fd_io__gpio_pddrvr_weakv2
+ Generating output for cell sky130_fd_io__gpio_pddrvr_strong_slowv2
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808656
+ Generating output for cell sky130_fd_pr__hvdfm1sd__example_55959141808655
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808654
+ Generating output for cell sky130_fd_io__com_pudrvr_weakv2
+ Generating output for cell sky130_fd_io__com_pudrvr_strong_slowv2
+ Generating output for cell sky130_fd_io__gpio_odrvr_subv2
+ Generating output for cell sky130_fd_io__gpio_odrvrv2
+ Generating output for cell sky130_fd_io__gpio_opathv2
+ Generating output for cell sky130_fd_io__top_gpiov2
+ Generating output for cell sky130_fd_io__overlay_gpiov2
+ Generating output for cell sky130_ef_io__gpiov2_pad
+ Generating output for cell sky130_ef_io__gpiov2_pad_wrapped
+ Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808691
+ Generating output for cell sky130_fd_pr__pfet_01v8__example_55959141808687
+ Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808684
+ Generating output for cell sky130_fd_pr__tpl1__example_55959141808686
+ Generating output for cell sky130_fd_pr__tpl1__example_55959141808685
+ Generating output for cell sky130_fd_pr__via_l1m1__example_55959141808683
+ Generating output for cell sky130_fd_io__gnd2gnd_strap
+ Generating output for cell sky130_fd_io__gnd2gnd_tap
+ Generating output for cell sky130_fd_io__gnd2gnd_diff
+ Generating output for cell sky130_fd_io__gnd2gnd_sub_dnwl
+ Generating output for cell sky130_fd_io__gnd2gnd_120x2_lv_isosub
+ Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808690
+ Generating output for cell sky130_fd_pr__dftpl1s2__example_55959141808702
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808705
+ Generating output for cell sky130_fd_pr__dfl1__example_55959141808682
+ Generating output for cell sky130_fd_pr__dftpl1s2__example_55959141808694
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808693
+ Generating output for cell sky130_fd_pr__dfl1__example_55959141808681
+ Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808688
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808699
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808698
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808697
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808696
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808695
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808704
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808703
+ Generating output for cell sky130_fd_pr__nfet_01v8__example_55959141808701
+ Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808689
+ Generating output for cell sky130_fd_pr__res_bent_po__example_55959141808692
+ Generating output for cell sky130_fd_io__top_ground_lvc_wpad
+ Generating output for cell sky130_fd_io__overlay_vssd_lvc
+ Generating output for cell sky130_ef_io__lvc_vccdx_overlay
+ Generating output for cell sky130_ef_io__vssd_lvc_clamped_pad
+ Generating output for cell sky130_fd_io__overlay_vssio_hvc
+ Generating output for cell sky130_ef_io__hvc_vssio_overlay
+ Generating output for cell sky130_ef_io__vssio_hvc_clamped_pad
+ Generating output for cell sky130_fd_io__hvc_clampv2
+ Generating output for cell sky130_fd_io__top_power_hvc_wpadv2
+ Generating output for cell sky130_fd_io__overlay_vdda_hvc
+ Generating output for cell sky130_ef_io__vdda_hvc_clamped_pad
+ Generating output for cell sky130_fd_io__top_power_lvc_wpad
+ Generating output for cell sky130_fd_io__overlay_vccd_lvc
+ Generating output for cell sky130_ef_io__vccd_lvc_clamped_pad
+ Generating output for cell sky130_ef_io__disconnect_vdda_slice_5um
+ Generating output for cell sky130_fd_io__overlay_vddio_hvc
+ Generating output for cell sky130_ef_io__hvc_vddio_overlay
+ Generating output for cell sky130_ef_io__vddio_hvc_clamped_pad
+ Generating output for cell chip_io_gpio_connects
+ Generating output for cell sky130_ef_io__lvc_vccdy_overlay
+ Generating output for cell sky130_ef_io__vssd_lvc_clamped3_pad
+ Generating output for cell sky130_ef_io__vccd_lvc_clamped3_pad
+ Generating output for cell chip_io
+ Generating output for cell gpio_signal_buffering
+ Generating output for cell caravel
diff --git a/tapeout/logs/tools.info b/tapeout/logs/tools.info
new file mode 100644
index 0000000..b630e4e
--- /dev/null
+++ b/tapeout/logs/tools.info
@@ -0,0 +1,2 @@
+KLayout: 0.27.12
+Magic: 8.3.339
\ No newline at end of file
diff --git a/tapeout/logs/uncompress.log b/tapeout/logs/uncompress.log
new file mode 100644
index 0000000..6a05f6e
--- /dev/null
+++ b/tapeout/logs/uncompress.log
@@ -0,0 +1,42 @@
+make: Nothing to be done for `check-env'.
+gds/digital_pll.gds.gz -> gds/digital_pll.gds
+gds/pinmux.gds.gz -> gds/pinmux.gds
+gds/qspim_top.gds.gz -> gds/qspim_top.gds
+gds/uart_i2c_usb_spi_top.gds.gz -> gds/uart_i2c_usb_spi_top.gds
+gds/user_project_wrapper.gds.gz -> gds/user_project_wrapper.gds
+gds/wb_host.gds.gz -> gds/wb_host.gds
+gds/wb_interconnect.gds.gz -> gds/wb_interconnect.gds
+gds/ycr4_iconnect.gds.gz -> gds/ycr4_iconnect.gds
+gds/ycr_core_top.gds.gz -> gds/ycr_core_top.gds
+gds/ycr_intf.gds.gz -> gds/ycr_intf.gds
+lef/digital_pll.lef.gz -> lef/digital_pll.lef
+lef/pinmux.lef.gz -> lef/pinmux.lef
+lef/qspim_top.lef.gz -> lef/qspim_top.lef
+lef/uart_i2c_usb_spi_top.lef.gz -> lef/uart_i2c_usb_spi_top.lef
+lef/user_project_wrapper.lef.gz -> lef/user_project_wrapper.lef
+lef/wb_host.lef.gz -> lef/wb_host.lef
+lef/wb_interconnect.lef.gz -> lef/wb_interconnect.lef
+lef/ycr4_iconnect.lef.gz -> lef/ycr4_iconnect.lef
+lef/ycr_core_top.lef.gz -> lef/ycr_core_top.lef
+lef/ycr_intf.lef.gz -> lef/ycr_intf.lef
+spef/digital_pll.spef.gz -> spef/digital_pll.spef
+spef/pinmux.spef.gz -> spef/pinmux.spef
+spef/qspim_top.spef.gz -> spef/qspim_top.spef
+spef/uart_i2c_usb_spi_top.spef.gz -> spef/uart_i2c_usb_spi_top.spef
+spef/user_project_wrapper.spef.gz -> spef/user_project_wrapper.spef
+spef/wb_host.spef.gz -> spef/wb_host.spef
+spef/wb_interconnect.spef.gz -> spef/wb_interconnect.spef
+spef/ycr4_iconnect.spef.gz -> spef/ycr4_iconnect.spef
+spef/ycr_core_top.spef.gz -> spef/ycr_core_top.spef
+spef/ycr_intf.spef.gz -> spef/ycr_intf.spef
+spi/lvs/pinmux.spice.gz -> spi/lvs/pinmux.spice
+spi/lvs/qspim_top.spice.gz -> spi/lvs/qspim_top.spice
+spi/lvs/uart_i2c_usb_spi_top.spice.gz -> spi/lvs/uart_i2c_usb_spi_top.spice
+spi/lvs/uart_i2cm_usb_spi.spice.gz -> spi/lvs/uart_i2cm_usb_spi.spice
+spi/lvs/user_project_wrapper.spice.gz -> spi/lvs/user_project_wrapper.spice
+spi/lvs/wb_host.spice.gz -> spi/lvs/wb_host.spice
+spi/lvs/wb_interconnect.spice.gz -> spi/lvs/wb_interconnect.spice
+spi/lvs/ycr4_iconnect.spice.gz -> spi/lvs/ycr4_iconnect.spice
+spi/lvs/ycr_core_top.spice.gz -> spi/lvs/ycr_core_top.spice
+spi/lvs/ycr_intf.spice.gz -> spi/lvs/ycr_intf.spice
+All files are uncompressed!
diff --git a/tapeout/outputs/gds/caravel_00069f13.gds.gz.00.split b/tapeout/outputs/gds/caravel_00069f13.gds.gz.00.split
new file mode 100644
index 0000000..9e883f8
--- /dev/null
+++ b/tapeout/outputs/gds/caravel_00069f13.gds.gz.00.split
Binary files differ
diff --git a/tapeout/outputs/gds/caravel_00069f13.gds.gz.01.split b/tapeout/outputs/gds/caravel_00069f13.gds.gz.01.split
new file mode 100644
index 0000000..b85d083
--- /dev/null
+++ b/tapeout/outputs/gds/caravel_00069f13.gds.gz.01.split
Binary files differ
diff --git a/tapeout/outputs/gds/caravel_00069f13.gds.gz.02.split b/tapeout/outputs/gds/caravel_00069f13.gds.gz.02.split
new file mode 100644
index 0000000..e74c1f1
--- /dev/null
+++ b/tapeout/outputs/gds/caravel_00069f13.gds.gz.02.split
Binary files differ
diff --git a/tapeout/outputs/gds/caravel_00069f13.gds.gz.03.split b/tapeout/outputs/gds/caravel_00069f13.gds.gz.03.split
new file mode 100644
index 0000000..3fb5e0f
--- /dev/null
+++ b/tapeout/outputs/gds/caravel_00069f13.gds.gz.03.split
Binary files differ
diff --git a/tapeout/outputs/gds/caravel_00069f13.gds.gz.04.split b/tapeout/outputs/gds/caravel_00069f13.gds.gz.04.split
new file mode 100644
index 0000000..285c411
--- /dev/null
+++ b/tapeout/outputs/gds/caravel_00069f13.gds.gz.04.split
Binary files differ
diff --git a/tapeout/outputs/gds/caravel_00069f13.gds.gz.05.split b/tapeout/outputs/gds/caravel_00069f13.gds.gz.05.split
new file mode 100644
index 0000000..ba0688c
--- /dev/null
+++ b/tapeout/outputs/gds/caravel_00069f13.gds.gz.05.split
Binary files differ
diff --git a/tapeout/outputs/klayout_beol_report.xml b/tapeout/outputs/klayout_beol_report.xml
new file mode 100644
index 0000000..67bce19
--- /dev/null
+++ b/tapeout/outputs/klayout_beol_report.xml
@@ -0,0 +1,447 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/opt/scripts/tech/sky130A_mr.drc'</generator>
+ <top-cell>caravel_00069f13</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ <category>
+ <name>li.1</name>
+ <description>li.1 : min. li width : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li.3</name>
+ <description>li.3 : min. li spacing : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li.5</name>
+ <description>li.5 : min. li enclosure of licon of 2 adjacent edges : 0.08um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li.6</name>
+ <description>li.6 : min. li area : 0.0561um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.1</name>
+ <description>ct.1: non-ring mcon should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.1_a</name>
+ <description>ct.1_a : minimum width of mcon : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.1_b</name>
+ <description>ct.1_b : maximum length of mcon : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.2</name>
+ <description>ct.2 : min. mcon spacing : 0.19um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.4</name>
+ <description>ct.4 : mcon should covered by li</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.1</name>
+ <description>m1.1 : min. m1 width : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.2</name>
+ <description>m1.2 : min. m1 spacing : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.3ab</name>
+ <description>m1.3ab : min. 3um.m1 spacing m1 : 0.28um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>791_m1.4</name>
+ <description>791_m1.4 : min. m1 enclosure of mcon : 0.03um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.4</name>
+ <description>m1.4 : mcon periphery must be enclosed by m1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.4a</name>
+ <description>m1.4a : min. m1 enclosure of mcon for specific cells : 0.005um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.4a_a</name>
+ <description>m1.4a_a : mcon periph must be enclosed by met1 for specific cells</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.6</name>
+ <description>m1.6 : min. m1 area : 0.083um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.7</name>
+ <description>m1.7 : min. m1 with holes area : 0.14um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.5</name>
+ <description>m1.5 : min. m1 enclosure of mcon of 2 adjacent edges : 0.06um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.1a</name>
+ <description>via.1a : via outside of moduleCut should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.1a_a</name>
+ <description>via.1a_a : min. width of via outside of moduleCut : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.1a_b</name>
+ <description>via.1a_b : maximum length of via : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.2</name>
+ <description>via.2 : min. via spacing : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.4a</name>
+ <description>via.4a : min. m1 enclosure of 0.15um via : 0.055um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.4a_a</name>
+ <description>via.4a_a : 0.15um via must be enclosed by met1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.5a</name>
+ <description>via.5a : min. m1 enclosure of 0.15um via of 2 adjacent edges : 0.085um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.1</name>
+ <description>m2.1 : min. m2 width : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.2</name>
+ <description>m2.2 : min. m2 spacing : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.3ab</name>
+ <description>m2.3ab : min. 3um.m2 spacing m2 : 0.28um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.6</name>
+ <description>m2.6 : min. m2 area : 0.0676um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.7</name>
+ <description>m2.7 : min. m2 holes area : 0.14um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.4</name>
+ <description>m2.4 : min. m2 enclosure of via : 0.055um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.4_a</name>
+ <description>m2.4_a : via in periphery must be enclosed by met2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.5</name>
+ <description>m2.5 : min. m2 enclosure of via of 2 adjacent edges : 0.085um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.1a</name>
+ <description>via2.1a : via2 outside of moduleCut should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.1a_a</name>
+ <description>via2.1a_a : min. width of via2 outside of moduleCut : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.1a_b</name>
+ <description>via2.1a_b : maximum length of via2 : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.2</name>
+ <description>via2.2 : min. via2 spacing : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.4</name>
+ <description>via2.4 : min. m2 enclosure of via2 : 0.04um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.4_a</name>
+ <description>via2.4_a : via must be enclosed by met2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.5</name>
+ <description>via2.5 : min. m3 enclosure of via2 of 2 adjacent edges : 0.085um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.1</name>
+ <description>m3.1 : min. m3 width : 0.3um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.2</name>
+ <description>m3.2 : min. m3 spacing : 0.3um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.3cd</name>
+ <description>m3.3cd : min. 3um.m3 spacing m3 : 0.4um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.4</name>
+ <description>m3.4 : min. m3 enclosure of via2 : 0.065um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.4_a</name>
+ <description>m3.4_a : via2 must be enclosed by met3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.1</name>
+ <description>via3.1 : via3 outside of moduleCut should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.1_a</name>
+ <description>via3.1_a : min. width of via3 outside of moduleCut : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.1_b</name>
+ <description>via3.1_b : maximum length of via3 : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.2</name>
+ <description>via3.2 : min. via3 spacing : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.4</name>
+ <description>via3.4 : min. m3 enclosure of via3 : 0.06um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.4_a</name>
+ <description>via3.4_a : non-ring via3 must be enclosed by met3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.5</name>
+ <description>via3.5 : min. m3 enclosure of via3 of 2 adjacent edges : 0.09um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.1</name>
+ <description>m4.1 : min. m4 width : 0.3um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.2</name>
+ <description>m4.2 : min. m4 spacing : 0.3um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.4a</name>
+ <description>m4.4a : min. m4 area : 0.240um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.5ab</name>
+ <description>m4.5ab : min. 3um.m4 spacing m4 : 0.4um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.3</name>
+ <description>m4.3 : min. m4 enclosure of via3 : 0.065um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.3_a</name>
+ <description>m4.3_a : via3 must be enclosed by met4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.1</name>
+ <description>via4.1 : via4 outside of moduleCut should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.1_a</name>
+ <description>via4.1_a : min. width of via4 outside of moduleCut : 0.8um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.1_b</name>
+ <description>via4.1_b : maximum length of via4 : 0.8um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.2</name>
+ <description>via4.2 : min. via4 spacing : 0.8um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.4</name>
+ <description>via4.4 : min. m4 enclosure of via4 : 0.19um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.4_a</name>
+ <description>via4.4_a : m4 must enclose all via4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.1</name>
+ <description>m5.1 : min. m5 width : 1.6um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.2</name>
+ <description>m5.2 : min. m5 spacing : 1.6um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.3</name>
+ <description>m5.3 : min. m5 enclosure of via4 : 0.31um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.3_a</name>
+ <description>m5.3_a : via must be enclosed by m5</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.4</name>
+ <description>m5.4 : min. m5 area : 4.0um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pad.2</name>
+ <description>pad.2 : min. pad spacing : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ </categories>
+ <cells>
+ <cell>
+ <name>caravel_00069f13</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/tapeout/outputs/klayout_beol_report.xml.summary b/tapeout/outputs/klayout_beol_report.xml.summary
new file mode 100644
index 0000000..79b5c11
--- /dev/null
+++ b/tapeout/outputs/klayout_beol_report.xml.summary
@@ -0,0 +1,72 @@
+ 0 791_m1.4 : min. m1 enclosure of mcon : 0.03um
+ 0 ct.1: non-ring mcon should be rectangular
+ 0 ct.1_a : minimum width of mcon : 0.17um
+ 0 ct.1_b : maximum length of mcon : 0.17um
+ 0 ct.2 : min. mcon spacing : 0.19um
+ 0 ct.4 : mcon should covered by li
+ 0 li.1 : min. li width : 0.17um
+ 0 li.3 : min. li spacing : 0.17um
+ 0 li.5 : min. li enclosure of licon of 2 adjacent edges : 0.08um
+ 0 li.6 : min. li area : 0.0561um²
+ 0 m1.1 : min. m1 width : 0.14um
+ 0 m1.2 : min. m1 spacing : 0.14um
+ 0 m1.3ab : min. 3um.m1 spacing m1 : 0.28um
+ 0 m1.4 : mcon periphery must be enclosed by m1
+ 0 m1.4a : min. m1 enclosure of mcon for specific cells : 0.005um
+ 0 m1.4a_a : mcon periph must be enclosed by met1 for specific cells
+ 0 m1.5 : min. m1 enclosure of mcon of 2 adjacent edges : 0.06um
+ 0 m1.6 : min. m1 area : 0.083um²
+ 0 m1.7 : min. m1 with holes area : 0.14um²
+ 0 m2.1 : min. m2 width : 0.14um
+ 0 m2.2 : min. m2 spacing : 0.14um
+ 0 m2.3ab : min. 3um.m2 spacing m2 : 0.28um
+ 0 m2.4 : min. m2 enclosure of via : 0.055um
+ 0 m2.4_a : via in periphery must be enclosed by met2
+ 0 m2.5 : min. m2 enclosure of via of 2 adjacent edges : 0.085um
+ 0 m2.6 : min. m2 area : 0.0676um²
+ 0 m2.7 : min. m2 holes area : 0.14um²
+ 0 m3.1 : min. m3 width : 0.3um
+ 0 m3.2 : min. m3 spacing : 0.3um
+ 0 m3.3cd : min. 3um.m3 spacing m3 : 0.4um
+ 0 m3.4 : min. m3 enclosure of via2 : 0.065um
+ 0 m3.4_a : via2 must be enclosed by met3
+ 0 m4.1 : min. m4 width : 0.3um
+ 0 m4.2 : min. m4 spacing : 0.3um
+ 0 m4.3 : min. m4 enclosure of via3 : 0.065um
+ 0 m4.3_a : via3 must be enclosed by met4
+ 0 m4.4a : min. m4 area : 0.240um²
+ 0 m4.5ab : min. 3um.m4 spacing m4 : 0.4um
+ 0 m5.1 : min. m5 width : 1.6um
+ 0 m5.2 : min. m5 spacing : 1.6um
+ 0 m5.3 : min. m5 enclosure of via4 : 0.31um
+ 0 m5.3_a : via must be enclosed by m5
+ 0 m5.4 : min. m5 area : 4.0um²
+ 0 pad.2 : min. pad spacing : 1.27um
+ 0 via2.1a : via2 outside of moduleCut should be rectangular
+ 0 via2.1a_a : min. width of via2 outside of moduleCut : 0.2um
+ 0 via2.1a_b : maximum length of via2 : 0.2um
+ 0 via2.2 : min. via2 spacing : 0.2um
+ 0 via2.4 : min. m2 enclosure of via2 : 0.04um
+ 0 via2.4_a : via must be enclosed by met2
+ 0 via2.5 : min. m3 enclosure of via2 of 2 adjacent edges : 0.085um
+ 0 via3.1 : via3 outside of moduleCut should be rectangular
+ 0 via3.1_a : min. width of via3 outside of moduleCut : 0.2um
+ 0 via3.1_b : maximum length of via3 : 0.2um
+ 0 via3.2 : min. via3 spacing : 0.2um
+ 0 via3.4 : min. m3 enclosure of via3 : 0.06um
+ 0 via3.4_a : non-ring via3 must be enclosed by met3
+ 0 via3.5 : min. m3 enclosure of via3 of 2 adjacent edges : 0.09um
+ 0 via4.1 : via4 outside of moduleCut should be rectangular
+ 0 via4.1_a : min. width of via4 outside of moduleCut : 0.8um
+ 0 via4.1_b : maximum length of via4 : 0.8um
+ 0 via4.2 : min. via4 spacing : 0.8um
+ 0 via4.4 : min. m4 enclosure of via4 : 0.19um
+ 0 via4.4_a : m4 must enclose all via4
+ 0 via.1a : via outside of moduleCut should be rectangular
+ 0 via.1a_a : min. width of via outside of moduleCut : 0.15um
+ 0 via.1a_b : maximum length of via : 0.15um
+ 0 via.2 : min. via spacing : 0.17um
+ 0 via.4a : min. m1 enclosure of 0.15um via : 0.055um
+ 0 via.4a_a : 0.15um via must be enclosed by met1
+ 0 via.5a : min. m1 enclosure of 0.15um via of 2 adjacent edges : 0.085um
+ 0 total error(s) among 71 error type(s), 0 non-zero type(s)
diff --git a/tapeout/outputs/klayout_feol_report.xml b/tapeout/outputs/klayout_feol_report.xml
new file mode 100644
index 0000000..c0328d8
--- /dev/null
+++ b/tapeout/outputs/klayout_feol_report.xml
@@ -0,0 +1,375 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/opt/scripts/tech/sky130A_mr.drc'</generator>
+ <top-cell>caravel_00069f13</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ <category>
+ <name>dnwell.2</name>
+ <description>dnwell.2 : min. dnwell width : 3.0um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell.1</name>
+ <description>nwell.1 : min. nwell width : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell.2a</name>
+ <description>nwell.2a : min. nwell spacing (merged if less) : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell.6</name>
+ <description>nwell.6 : min enclosure of nwellHole by dnwell : 1.03um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp.1</name>
+ <description>hvtp.1 : min. hvtp width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp.2</name>
+ <description>hvtp.2 : min. hvtp spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr.1</name>
+ <description>hvtr.1 : min. hvtr width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr.2</name>
+ <description>hvtr.2 : min. hvtr spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr.2_a</name>
+ <description>hvtr.2_a : hvtr must not overlap hvtp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn.1a</name>
+ <description>lvtn.1a : min. lvtn width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn.2</name>
+ <description>lvtn.2 : min. lvtn spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm.1</name>
+ <description>ncm.1 : min. ncm width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm.2a</name>
+ <description>ncm.2a : min. ncm spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1</name>
+ <description>difftap.1 : min. diff width across areaid:ce : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1_a</name>
+ <description>difftap.1_a : min. diff width in periphery : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1_b</name>
+ <description>difftap.1_b : min. tap width across areaid:ce : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1_c</name>
+ <description>difftap.1_c : min. tap width in periphery : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.3</name>
+ <description>difftap.3 : min. difftap spacing : 0.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm.1</name>
+ <description>tunm.1 : min. tunm width : 0.41um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm.2</name>
+ <description>tunm.2 : min. tunm spacing : 0.5um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly.1a</name>
+ <description>poly.1a : min. poly width : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly.2</name>
+ <description>poly.2 : min. poly spacing : 0.21um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm.1a</name>
+ <description>rpm.1a : min. rpm width : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm.2</name>
+ <description>rpm.2 : min. rpm spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>urpm.1a</name>
+ <description>urpm.1a : min. rpm width : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>urpm.2</name>
+ <description>urpm.2 : min. rpm spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc.1</name>
+ <description>npc.1 : min. npc width : 0.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc.2</name>
+ <description>npc.2 : min. npc spacing, should be manually merged if less than : 0.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsd.1</name>
+ <description>nsd.1 : min. nsdm width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsd.2</name>
+ <description>nsd.2 : min. nsdm spacing, should be manually merged if less than : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psd.1</name>
+ <description>psd.1 : min. psdm width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psd.2</name>
+ <description>psd.2 : min. psdm spacing, should be manually merged if less than : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.1</name>
+ <description>licon.1 : licon should be rectangle</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.1_a/b</name>
+ <description>licon.1_a/b : minimum/maximum width of licon : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.13</name>
+ <description>licon.13 : min. difftap licon spacing to npc : 0.09um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.13_a</name>
+ <description>licon.13_a : licon of diffTap in periphery must not overlap npc</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.17</name>
+ <description>licon.17 : Licons may not overlap both poly and (diff or tap)</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.1</name>
+ <description>capm.1 : min. capm width : 1.0um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.2a</name>
+ <description>capm.2a : min. capm spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.2b</name>
+ <description>capm.2b : min. capm spacing : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.2b_a</name>
+ <description>capm.2b_a : min. spacing of m3_bot_plate : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.3</name>
+ <description>capm.3 : min. capm and m3 enclosure of m3 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.3_a</name>
+ <description>capm.3_a : min. m3 enclosure of capm : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.4</name>
+ <description>capm.4 : min. capm enclosure of via3 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.5</name>
+ <description>capm.5 : min. capm spacing to via3 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.11</name>
+ <description>capm.11 : Min spacing of capm and met3 not overlapping capm : 0.5um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.1</name>
+ <description>cap2m.1 : min. cap2m width : 1.0um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.2a</name>
+ <description>cap2m.2a : min. cap2m spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.2b</name>
+ <description>cap2m.2b : min. cap2m spacing : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.2b_a</name>
+ <description>cap2m.2b_a : min. spacing of m4_bot_plate : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.3</name>
+ <description>cap2m.3 : min. m4 enclosure of cap2m : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.3_a</name>
+ <description>cap2m.3_a : min. m4 enclosure of cap2m : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.4</name>
+ <description>cap2m.4 : min. cap2m enclosure of via4 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.5</name>
+ <description>cap2m.5 : min. cap2m spacing to via4 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.11</name>
+ <description>cap2m.11 : Min spacing of cap2m and met4 not overlapping cap2m : 0.5um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi.1</name>
+ <description>hvi.1 : min. hvi width : 0.6um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi.2a</name>
+ <description>hvi.2a : min. hvi spacing : 0.7um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm.1</name>
+ <description>hvntm.1 : min. hvntm width : 0.7um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm.2</name>
+ <description>hvntm.2 : min. hvntm spacing : 0.7um</description>
+ <categories>
+ </categories>
+ </category>
+ </categories>
+ <cells>
+ <cell>
+ <name>caravel_00069f13</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/tapeout/outputs/klayout_feol_report.xml.summary b/tapeout/outputs/klayout_feol_report.xml.summary
new file mode 100644
index 0000000..2a7a007
--- /dev/null
+++ b/tapeout/outputs/klayout_feol_report.xml.summary
@@ -0,0 +1,60 @@
+ 0 cap2m.1 : min. cap2m width : 1.0um
+ 0 cap2m.2a : min. cap2m spacing : 0.84um
+ 0 cap2m.2b : min. cap2m spacing : 1.2um
+ 0 cap2m.2b_a : min. spacing of m4_bot_plate : 1.2um
+ 0 cap2m.3 : min. m4 enclosure of cap2m : 0.14um
+ 0 cap2m.3_a : min. m4 enclosure of cap2m : 0.14um
+ 0 cap2m.4 : min. cap2m enclosure of via4 : 0.14um
+ 0 cap2m.5 : min. cap2m spacing to via4 : 0.14um
+ 0 cap2m.11 : Min spacing of cap2m and met4 not overlapping cap2m : 0.5um
+ 0 capm.1 : min. capm width : 1.0um
+ 0 capm.2a : min. capm spacing : 0.84um
+ 0 capm.2b : min. capm spacing : 1.2um
+ 0 capm.2b_a : min. spacing of m3_bot_plate : 1.2um
+ 0 capm.3 : min. capm and m3 enclosure of m3 : 0.14um
+ 0 capm.3_a : min. m3 enclosure of capm : 0.14um
+ 0 capm.4 : min. capm enclosure of via3 : 0.14um
+ 0 capm.5 : min. capm spacing to via3 : 0.14um
+ 0 capm.11 : Min spacing of capm and met3 not overlapping capm : 0.5um
+ 0 difftap.1 : min. diff width across areaid:ce : 0.15um
+ 0 difftap.1_a : min. diff width in periphery : 0.15um
+ 0 difftap.1_b : min. tap width across areaid:ce : 0.15um
+ 0 difftap.1_c : min. tap width in periphery : 0.15um
+ 0 difftap.3 : min. difftap spacing : 0.27um
+ 0 dnwell.2 : min. dnwell width : 3.0um
+ 0 hvi.1 : min. hvi width : 0.6um
+ 0 hvi.2a : min. hvi spacing : 0.7um
+ 0 hvntm.1 : min. hvntm width : 0.7um
+ 0 hvntm.2 : min. hvntm spacing : 0.7um
+ 0 hvtp.1 : min. hvtp width : 0.38um
+ 0 hvtp.2 : min. hvtp spacing : 0.38um
+ 0 hvtr.1 : min. hvtr width : 0.38um
+ 0 hvtr.2 : min. hvtr spacing : 0.38um
+ 0 hvtr.2_a : hvtr must not overlap hvtp
+ 0 licon.1 : licon should be rectangle
+ 0 licon.1_a/b : minimum/maximum width of licon : 0.17um
+ 0 licon.13 : min. difftap licon spacing to npc : 0.09um
+ 0 licon.13_a : licon of diffTap in periphery must not overlap npc
+ 0 licon.17 : Licons may not overlap both poly and (diff or tap)
+ 0 lvtn.1a : min. lvtn width : 0.38um
+ 0 lvtn.2 : min. lvtn spacing : 0.38um
+ 0 ncm.1 : min. ncm width : 0.38um
+ 0 ncm.2a : min. ncm spacing : 0.38um
+ 0 npc.1 : min. npc width : 0.27um
+ 0 npc.2 : min. npc spacing, should be manually merged if less than : 0.27um
+ 0 nsd.1 : min. nsdm width : 0.38um
+ 0 nsd.2 : min. nsdm spacing, should be manually merged if less than : 0.38um
+ 0 nwell.1 : min. nwell width : 0.84um
+ 0 nwell.2a : min. nwell spacing (merged if less) : 1.27um
+ 0 nwell.6 : min enclosure of nwellHole by dnwell : 1.03um
+ 0 poly.1a : min. poly width : 0.15um
+ 0 poly.2 : min. poly spacing : 0.21um
+ 0 psd.1 : min. psdm width : 0.38um
+ 0 psd.2 : min. psdm spacing, should be manually merged if less than : 0.38um
+ 0 rpm.1a : min. rpm width : 1.27um
+ 0 rpm.2 : min. rpm spacing : 0.84um
+ 0 tunm.1 : min. tunm width : 0.41um
+ 0 tunm.2 : min. tunm spacing : 0.5um
+ 0 urpm.1a : min. rpm width : 1.27um
+ 0 urpm.2 : min. rpm spacing : 0.84um
+ 0 total error(s) among 59 error type(s), 0 non-zero type(s)
diff --git a/tapeout/outputs/klayout_fom_density_report.xml b/tapeout/outputs/klayout_fom_density_report.xml
new file mode 100644
index 0000000..7200e22
--- /dev/null
+++ b/tapeout/outputs/klayout_fom_density_report.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>Density Checks</description>
+ <original-file/>
+ <generator>drc: script='/opt/scripts/tech/fom_density.drc'</generator>
+ <top-cell>caravel_00069f13</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+ <cell>
+ <name>caravel_00069f13</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/tapeout/outputs/klayout_fom_density_report.xml.summary b/tapeout/outputs/klayout_fom_density_report.xml.summary
new file mode 100644
index 0000000..8d461a0
--- /dev/null
+++ b/tapeout/outputs/klayout_fom_density_report.xml.summary
@@ -0,0 +1 @@
+ 0 total error(s) among 0 error type(s), 0 non-zero type(s)
diff --git a/tapeout/outputs/klayout_met_density_report.xml b/tapeout/outputs/klayout_met_density_report.xml
new file mode 100644
index 0000000..9f31210
--- /dev/null
+++ b/tapeout/outputs/klayout_met_density_report.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>Density Checks</description>
+ <original-file/>
+ <generator>drc: script='/opt/scripts/tech/met_density.lydrc'</generator>
+ <top-cell>caravel_00069f13</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+ <cell>
+ <name>caravel_00069f13</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/tapeout/outputs/klayout_met_density_report.xml.summary b/tapeout/outputs/klayout_met_density_report.xml.summary
new file mode 100644
index 0000000..8d461a0
--- /dev/null
+++ b/tapeout/outputs/klayout_met_density_report.xml.summary
@@ -0,0 +1 @@
+ 0 total error(s) among 0 error type(s), 0 non-zero type(s)
diff --git a/tapeout/outputs/mag/.magicrc b/tapeout/outputs/mag/.magicrc
new file mode 100755
index 0000000..7ec699d
--- /dev/null
+++ b/tapeout/outputs/mag/.magicrc
@@ -0,0 +1,109 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# Allow override of PDK path from environment variable PDKPATH. Failing
+# that, fall back on definitions of PDK_ROOT and PDK. If either of those
+# fails, substitute a default. If PDKPATH has been specified, then get
+# PDK_VARIANT from the tail of PDKPATH.
+
+if {[catch {set PDKPATH $env(PDKPATH)}]} {
+ if {[catch {set PDK_ROOT $env(PDK_ROOT)}]} {
+ set PDK_ROOT /usr/share/pdk
+ }
+ if {[catch {set PDK_VARIANT $env(PDK)}]} {
+ set PDK_VARIANT sky130A
+ }
+ set PDKPATH ${PDK_ROOT}/${PDK_VARIANT}
+} else {
+ set PDK_VARIANT [file tail ${PDKPATH}]
+}
+
+puts stdout "Sourcing design .magicrc for technology $PDK_VARIANT ..."
+
+# Put grid on 0.005 pitch. This is important, as some commands don't
+# rescale the grid automatically (such as lef read?).
+
+set scalefac [tech lambda]
+if {[lindex $scalefac 1] < 2} {
+ scalegrid 1 2
+}
+
+drc off
+drc euclidean on
+
+# loading technology
+tech load $PDKPATH/libs.tech/magic/${PDK_VARIANT}.tech
+
+# load device generator
+source $PDKPATH/libs.tech/magic/${PDK_VARIANT}.tcl
+
+# load bind keys (optional)
+# source $PDKPATH/libs.tech/magic/${PDK_VARIANT}-BindKeys
+
+# set units to lambda grid
+snap lambda
+
+# set sky130 standard power, ground, and substrate names
+set VDD VPWR
+set GND VGND
+set SUB VSUBS
+
+# Allow override of type of magic library views used, "mag" or "maglef",
+# from environment variable MAGTYPE
+
+if {[catch {set MAGTYPE $env(MAGTYPE)}]} {
+ set MAGTYPE maglef
+}
+
+ path search [concat "../$MAGTYPE" [path search]]
+
+
+# add path to reference cells
+if {[file isdir ${PDKPATH}/libs.ref/${MAGTYPE}]} {
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_pr
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_io
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hd
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hdll
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hs
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hvl
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_lp
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ls
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ms
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc
+ addpath ${PDKPATH}/libs.ref/mag/sky130_ml_xx_hd
+} else {
+ addpath ${PDKPATH}/libs.ref/sky130_fd_pr/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_io/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hd/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hdll/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hs/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hvl/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_lp/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ls/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ms/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_osu_sc/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_ml_xx_hd/mag
+}
+
+addpath hexdigits
+addpath ../subcells/simple_por/mag
+
+# add path to GDS cells
+
+# add path to IP from catalog. This procedure defined in the PDK script.
+catch {magic::query_mylib_ip}
+# add path to local IP from user design space. Defined in the PDK script.
+catch {magic::query_my_projects}
diff --git a/tapeout/outputs/mag/caravel.mag b/tapeout/outputs/mag/caravel.mag
new file mode 100644
index 0000000..82f18c9
--- /dev/null
+++ b/tapeout/outputs/mag/caravel.mag
@@ -0,0 +1,83878 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1667299471
+<< checkpaint >>
+rect -1260 -1260 718860 1038860
+<< metal1 >>
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+rect 657937 234292 657978 234528
+rect 657658 231072 657978 234292
+rect 657658 230836 657688 231072
+rect 657924 230836 657978 231072
+rect 657658 230762 657978 230836
+rect 6598 183840 19088 196360
+rect 698512 191440 711002 203960
+rect 662713 150879 663033 150996
+rect 662713 150643 662756 150879
+rect 662992 150643 663033 150879
+rect 662713 147423 663033 150643
+rect 662713 147187 662743 147423
+rect 662979 147187 663033 147423
+rect 662713 147113 663033 147187
+rect 698512 146440 711002 158960
+rect 663597 143165 663917 143282
+rect 663597 142929 663640 143165
+rect 663876 142929 663917 143165
+rect 663597 139709 663917 142929
+rect 663597 139473 663627 139709
+rect 663863 139473 663917 139709
+rect 663597 139399 663917 139473
+rect 664538 133389 664858 133506
+rect 664538 133153 664581 133389
+rect 664817 133153 664858 133389
+rect 664538 129933 664858 133153
+rect 664538 129697 664568 129933
+rect 664804 129697 664858 129933
+rect 664538 129623 664858 129697
+rect 6811 111610 18976 123778
+rect 698512 101240 711002 113760
+rect 647060 94298 647748 94340
+rect 647060 94062 647102 94298
+rect 647338 94062 647748 94298
+rect 647060 94020 647748 94062
+rect 647428 93660 647748 94020
+rect 647428 93618 650508 93660
+rect 647428 93382 650230 93618
+rect 650466 93382 650508 93618
+rect 647428 93340 650508 93382
+rect 6167 70054 19620 80934
+rect 361860 41938 403120 41980
+rect 361860 41702 361902 41938
+rect 362138 41702 403120 41938
+rect 361860 41660 403120 41702
+rect 402800 41300 403120 41660
+rect 403444 41660 412044 41980
+rect 403444 41300 403764 41660
+rect 365356 41258 402476 41300
+rect 365356 41022 365398 41258
+rect 365634 41022 402198 41258
+rect 402434 41022 402476 41258
+rect 365356 40980 402476 41022
+rect 402800 40980 403764 41300
+rect 411724 41300 412044 41660
+rect 412460 41660 421796 41980
+rect 422120 41938 423820 41980
+rect 422120 41702 422162 41938
+rect 422398 41702 423820 41938
+rect 422120 41660 423820 41702
+rect 424972 41938 441668 41980
+rect 424972 41702 425014 41938
+rect 425250 41702 441390 41938
+rect 441626 41702 441668 41938
+rect 424972 41660 441668 41702
+rect 442084 41660 450684 41980
+rect 412460 41300 412780 41660
+rect 411724 40980 412780 41300
+rect 421476 41300 421796 41660
+rect 423500 41300 423820 41660
+rect 442084 41300 442404 41660
+rect 421476 40980 422440 41300
+rect 423500 40980 442404 41300
+rect 450364 41300 450684 41660
+rect 451100 41938 463932 41980
+rect 451100 41702 463654 41938
+rect 463890 41702 463932 41938
+rect 451100 41660 463932 41702
+rect 451100 41300 451420 41660
+rect 450364 40980 451420 41300
+rect 422120 40620 422440 40980
+rect 422120 40578 425292 40620
+rect 422120 40342 425014 40578
+rect 425250 40342 425292 40578
+rect 422120 40300 425292 40342
+rect 80222 6811 92390 18976
+rect 136713 7143 144150 18309
+rect 187640 6598 200160 19088
+rect 243266 6167 254146 19620
+rect 296240 6598 308760 19088
+rect 351040 6598 363560 19088
+rect 405840 6598 418360 19088
+rect 460640 6598 473160 19088
+rect 515440 6598 527960 19088
+rect 570422 6811 582590 18976
+rect 624222 6811 636390 18976
+use caravel_logo caravel_logo
+timestamp 1638586901
+transform 1 0 269370 0 1 5100
+box -2520 0 15000 15560
+use caravel_motto caravel_motto
+timestamp 1637698310
+transform 1 0 -54372 0 1 -4446
+box 373080 14838 395618 19242
+use caravel_power_routing caravel_power_routing
+timestamp 1666994345
+transform 1 0 0 0 1 0
+box 6022 30806 711814 1031696
+use caravel_clocking clock_ctrl
+timestamp 1666097791
+transform 1 0 626764 0 1 55284
+box 136 496 20000 20000
+use copyright_block copyright_block
+timestamp 1665519328
+transform 1 0 149582 0 1 16298
+box -262 -10348 35048 2764
+use buff_flash_clkrst flash_clkrst_buffers
+timestamp 1665682149
+transform 1 0 458400 0 1 47600
+box 330 0 7699 5000
+use gpio_control_block gpio_control_bidir_1\[0\]
+timestamp 1666126335
+transform -1 0 710203 0 1 121000
+box 872 416 34000 13000
+use gpio_control_block gpio_control_bidir_1\[1\]
+timestamp 1666126335
+transform -1 0 710203 0 1 166200
+box 872 416 34000 13000
+use gpio_control_block gpio_control_bidir_2\[0\]
+timestamp 1666126335
+transform 1 0 7631 0 1 289000
+box 872 416 34000 13000
+use gpio_control_block gpio_control_bidir_2\[1\]
+timestamp 1666126335
+transform 1 0 7631 0 1 245800
+box 872 416 34000 13000
+use gpio_control_block gpio_control_bidir_2\[2\]
+timestamp 1666126335
+transform 1 0 7631 0 1 202600
+box 872 416 34000 13000
+use gpio_control_block gpio_control_in_1\[0\]
+timestamp 1666126335
+transform -1 0 710203 0 1 523800
+box 872 416 34000 13000
+use gpio_control_block gpio_control_in_1\[1\]
+timestamp 1666126335
+transform -1 0 710203 0 1 568800
+box 872 416 34000 13000
+use gpio_control_block gpio_control_in_1\[2\]
+timestamp 1666126335
+transform -1 0 710203 0 1 614000
+box 872 416 34000 13000
+use gpio_control_block gpio_control_in_1\[3\]
+timestamp 1666126335
+transform -1 0 710203 0 1 659000
+box 872 416 34000 13000
+use gpio_control_block gpio_control_in_1\[4\]
+timestamp 1666126335
+transform -1 0 710203 0 1 704200
+box 872 416 34000 13000
+use gpio_control_block gpio_control_in_1\[5\]
+timestamp 1666126335
+transform -1 0 710203 0 1 749200
+box 872 416 34000 13000
+use gpio_control_block gpio_control_in_1\[6\]
+timestamp 1666126335
+transform -1 0 710203 0 1 927600
+box 872 416 34000 13000
+use gpio_control_block gpio_control_in_1\[7\]
+timestamp 1666126335
+transform 0 1 549200 -1 0 1030077
+box 872 416 34000 13000
+use gpio_control_block gpio_control_in_1\[8\]
+timestamp 1666126335
+transform 0 1 497800 -1 0 1030077
+box 872 416 34000 13000
+use gpio_control_block gpio_control_in_1\[9\]
+timestamp 1666126335
+transform 0 1 420800 -1 0 1030077
+box 872 416 34000 13000
+use gpio_control_block gpio_control_in_1\[10\]
+timestamp 1666126335
+transform 0 1 353400 -1 0 1030077
+box 872 416 34000 13000
+use gpio_control_block gpio_control_in_1a\[0\]
+timestamp 1666126335
+transform -1 0 710203 0 1 211200
+box 872 416 34000 13000
+use gpio_control_block gpio_control_in_1a\[1\]
+timestamp 1666126335
+transform -1 0 710203 0 1 256400
+box 872 416 34000 13000
+use gpio_control_block gpio_control_in_1a\[2\]
+timestamp 1666126335
+transform -1 0 710203 0 1 301400
+box 872 416 34000 13000
+use gpio_control_block gpio_control_in_1a\[3\]
+timestamp 1666126335
+transform -1 0 710203 0 1 346400
+box 872 416 34000 13000
+use gpio_control_block gpio_control_in_1a\[4\]
+timestamp 1666126335
+transform -1 0 710203 0 1 391600
+box 872 416 34000 13000
+use gpio_control_block gpio_control_in_1a\[5\]
+timestamp 1666126335
+transform -1 0 710203 0 1 479800
+box 872 416 34000 13000
+use gpio_control_block gpio_control_in_2\[0\]
+timestamp 1666126335
+transform 0 1 303000 -1 0 1030077
+box 872 416 34000 13000
+use gpio_control_block gpio_control_in_2\[1\]
+timestamp 1666126335
+transform 0 1 251400 -1 0 1030077
+box 872 416 34000 13000
+use gpio_control_block gpio_control_in_2\[2\]
+timestamp 1666126335
+transform 0 1 200000 -1 0 1030077
+box 872 416 34000 13000
+use gpio_control_block gpio_control_in_2\[3\]
+timestamp 1666126335
+transform 0 1 148600 -1 0 1030077
+box 872 416 34000 13000
+use gpio_control_block gpio_control_in_2\[4\]
+timestamp 1666126335
+transform 0 1 97200 -1 0 1030077
+box 872 416 34000 13000
+use gpio_control_block gpio_control_in_2\[5\]
+timestamp 1666126335
+transform 1 0 7631 0 1 931200
+box 872 416 34000 13000
+use gpio_control_block gpio_control_in_2\[6\]
+timestamp 1666126335
+transform 1 0 7631 0 1 805400
+box 872 416 34000 13000
+use gpio_control_block gpio_control_in_2\[7\]
+timestamp 1666126335
+transform 1 0 7631 0 1 762200
+box 872 416 34000 13000
+use gpio_control_block gpio_control_in_2\[8\]
+timestamp 1666126335
+transform 1 0 7631 0 1 719000
+box 872 416 34000 13000
+use gpio_control_block gpio_control_in_2\[9\]
+timestamp 1666126335
+transform 1 0 7631 0 1 675800
+box 872 416 34000 13000
+use gpio_control_block gpio_control_in_2\[10\]
+timestamp 1666126335
+transform 1 0 7631 0 1 632600
+box 872 416 34000 13000
+use gpio_control_block gpio_control_in_2\[11\]
+timestamp 1666126335
+transform 1 0 7631 0 1 589400
+box 872 416 34000 13000
+use gpio_control_block gpio_control_in_2\[12\]
+timestamp 1666126335
+transform 1 0 7631 0 1 546200
+box 872 416 34000 13000
+use gpio_control_block gpio_control_in_2\[13\]
+timestamp 1666126335
+transform 1 0 7631 0 1 418600
+box 872 416 34000 13000
+use gpio_control_block gpio_control_in_2\[14\]
+timestamp 1666126335
+transform 1 0 7631 0 1 375400
+box 872 416 34000 13000
+use gpio_control_block gpio_control_in_2\[15\]
+timestamp 1666126335
+transform 1 0 7631 0 1 332200
+box 872 416 34000 13000
+use gpio_defaults_block_1803 gpio_defaults_block_0 ~/caravel_top_level/mag
+timestamp 1666360185
+transform -1 0 709467 0 1 134000
+box -38 0 6018 2224
+use gpio_defaults_block_1803 gpio_defaults_block_1
+timestamp 1666360185
+transform -1 0 709467 0 1 179200
+box -38 0 6018 2224
+use gpio_defaults_block_0403 gpio_defaults_block_2
+timestamp 1666360185
+transform -1 0 709467 0 1 224200
+box -38 0 6018 2224
+use gpio_defaults_block_0801 gpio_defaults_block_3
+timestamp 1666360185
+transform -1 0 709467 0 1 269400
+box -38 0 6018 2224
+use gpio_defaults_block_0403 gpio_defaults_block_4
+timestamp 1666360185
+transform -1 0 709467 0 1 314400
+box -38 0 6018 2224
+use gpio_defaults_block_0403 gpio_defaults_block_5
+timestamp 1666360185
+transform -1 0 709467 0 1 359400
+box -38 0 6018 2224
+use gpio_defaults_block_0403 gpio_defaults_block_6
+timestamp 1666360185
+transform -1 0 709467 0 1 404600
+box -38 0 6018 2224
+use gpio_defaults_block_0403 gpio_defaults_block_7
+timestamp 1666360185
+transform -1 0 709467 0 1 492800
+box -38 0 6018 2224
+use gpio_defaults_block_0403 gpio_defaults_block_8
+timestamp 1666360185
+transform -1 0 709467 0 1 536800
+box -38 0 6018 2224
+use gpio_defaults_block_0403 gpio_defaults_block_9
+timestamp 1666360185
+transform -1 0 709467 0 1 581800
+box -38 0 6018 2224
+use gpio_defaults_block_0403 gpio_defaults_block_10
+timestamp 1666360185
+transform -1 0 709467 0 1 627000
+box -38 0 6018 2224
+use gpio_defaults_block_0403 gpio_defaults_block_11
+timestamp 1666360185
+transform -1 0 709467 0 1 672000
+box -38 0 6018 2224
+use gpio_defaults_block_0403 gpio_defaults_block_12
+timestamp 1666360185
+transform -1 0 709467 0 1 717200
+box -38 0 6018 2224
+use gpio_defaults_block_0403 gpio_defaults_block_13
+timestamp 1666360185
+transform -1 0 709467 0 1 762200
+box -38 0 6018 2224
+use gpio_defaults_block_0403 gpio_defaults_block_14
+timestamp 1666360185
+transform -1 0 709467 0 1 940600
+box -38 0 6018 2224
+use gpio_defaults_block_0403 gpio_defaults_block_15
+timestamp 1666360185
+transform 0 1 562194 -1 0 1029341
+box -38 0 6018 2224
+use gpio_defaults_block_0403 gpio_defaults_block_16
+timestamp 1666360185
+transform 0 1 510794 -1 0 1029341
+box -38 0 6018 2224
+use gpio_defaults_block_0403 gpio_defaults_block_17
+timestamp 1666360185
+transform 0 1 433794 -1 0 1029341
+box -38 0 6018 2224
+use gpio_defaults_block_0403 gpio_defaults_block_18
+timestamp 1666360185
+transform 0 1 366394 -1 0 1029341
+box -38 0 6018 2224
+use gpio_defaults_block_0403 gpio_defaults_block_19
+timestamp 1666360185
+transform 0 1 315994 -1 0 1029341
+box -38 0 6018 2224
+use gpio_defaults_block_0403 gpio_defaults_block_20
+timestamp 1666360185
+transform 0 1 264394 -1 0 1029341
+box -38 0 6018 2224
+use gpio_defaults_block_0403 gpio_defaults_block_21
+timestamp 1666360185
+transform 0 1 212994 -1 0 1029341
+box -38 0 6018 2224
+use gpio_defaults_block_0403 gpio_defaults_block_22
+timestamp 1666360185
+transform 0 1 161594 -1 0 1029341
+box -38 0 6018 2224
+use gpio_defaults_block_0403 gpio_defaults_block_23
+timestamp 1666360185
+transform 0 1 110194 -1 0 1029341
+box -38 0 6018 2224
+use gpio_defaults_block_0403 gpio_defaults_block_24
+timestamp 1666360185
+transform 1 0 8367 0 1 944200
+box -38 0 6018 2224
+use gpio_defaults_block_0403 gpio_defaults_block_25
+timestamp 1666360185
+transform 1 0 8367 0 1 818400
+box -38 0 6018 2224
+use gpio_defaults_block_0403 gpio_defaults_block_26
+timestamp 1666360185
+transform 1 0 8367 0 1 775200
+box -38 0 6018 2224
+use gpio_defaults_block_0403 gpio_defaults_block_27
+timestamp 1666360185
+transform 1 0 8367 0 1 732000
+box -38 0 6018 2224
+use gpio_defaults_block_0403 gpio_defaults_block_28
+timestamp 1666360185
+transform 1 0 8367 0 1 688800
+box -38 0 6018 2224
+use gpio_defaults_block_0403 gpio_defaults_block_29
+timestamp 1666360185
+transform 1 0 8367 0 1 645600
+box -38 0 6018 2224
+use gpio_defaults_block_0403 gpio_defaults_block_30
+timestamp 1666360185
+transform 1 0 8367 0 1 602400
+box -38 0 6018 2224
+use gpio_defaults_block_0403 gpio_defaults_block_31
+timestamp 1666360185
+transform 1 0 8367 0 1 559200
+box -38 0 6018 2224
+use gpio_defaults_block_0403 gpio_defaults_block_32
+timestamp 1666360185
+transform 1 0 8367 0 1 431600
+box -38 0 6018 2224
+use gpio_defaults_block_0403 gpio_defaults_block_33
+timestamp 1666360185
+transform 1 0 8367 0 1 388400
+box -38 0 6018 2224
+use gpio_defaults_block_0403 gpio_defaults_block_34
+timestamp 1666360185
+transform 1 0 8367 0 1 345200
+box -38 0 6018 2224
+use gpio_defaults_block_0403 gpio_defaults_block_35
+timestamp 1666360185
+transform 1 0 8367 0 1 302000
+box -38 0 6018 2224
+use gpio_defaults_block_0403 gpio_defaults_block_36
+timestamp 1666360185
+transform 1 0 8367 0 1 258800
+box -38 0 6018 2224
+use gpio_defaults_block_0403 gpio_defaults_block_37
+timestamp 1666360185
+transform 1 0 8367 0 1 215600
+box -38 0 6018 2224
+use housekeeping housekeeping
+timestamp 1666084955
+transform 1 0 592434 0 1 100002
+box 0 0 74046 110190
+use mgmt_protect mgmt_buffers
+timestamp 1666987233
+transform 1 0 128180 0 1 232036
+box 1066 -400 424400 32400
+use user_project_wrapper mprj
+timestamp 1637147503
+transform 1 0 65308 0 1 278718
+box -8726 -7654 592650 711590
+use open_source open_source
+timestamp 1666123577
+transform 1 0 206098 0 1 2054
+box 752 5164 29030 16242
+use chip_io padframe
+timestamp 1666101711
+transform 1 0 0 0 1 0
+box 0 0 717600 1037600
+use digital_pll pll
+timestamp 1666101174
+transform 1 0 628146 0 1 80944
+box 0 0 20000 15000
+use simple_por por
+timestamp 1650914729
+transform 1 0 650146 0 -1 55282
+box -52 -62 11344 8684
+use xres_buf rstb_level
+timestamp 1649268499
+transform -1 0 145710 0 -1 50488
+box 374 -400 3540 3800
+use gpio_signal_buffering sigbuf
+timestamp 1666028385
+transform 1 0 0 0 1 0
+box 39992 41960 677583 997915
+use mgmt_core_wrapper soc
+timestamp 1668034664
+transform 1 0 52034 0 1 53002
+box -156 0 524096 164000
+use spare_logic_block spare_logic\[0\]
+timestamp 1638030917
+transform 1 0 88632 0 1 232528
+box 0 0 9000 9000
+use spare_logic_block spare_logic\[1\]
+timestamp 1638030917
+transform 1 0 108632 0 1 232528
+box 0 0 9000 9000
+use spare_logic_block spare_logic\[2\]
+timestamp 1638030917
+transform 1 0 640874 0 1 220592
+box 0 0 9000 9000
+use spare_logic_block spare_logic\[3\]
+timestamp 1638030917
+transform 1 0 578632 0 1 232528
+box 0 0 9000 9000
+use user_id_textblock user_id_textblock
+timestamp 1608324878
+transform 1 0 96272 0 1 6890
+box -656 1508 33720 10344
+use user_id_programming user_id_value
+timestamp 1650371074
+transform 1 0 656624 0 1 88126
+box 0 0 7109 7077
+<< labels >>
+flabel metal5 s 187640 6598 200160 19088 0 FreeSans 16000 0 0 0 clock
+port 1 nsew signal input
+flabel metal5 s 351040 6598 363560 19088 0 FreeSans 16000 0 0 0 flash_clk
+port 2 nsew signal output
+flabel metal5 s 296240 6598 308760 19088 0 FreeSans 16000 0 0 0 flash_csb
+port 3 nsew signal output
+flabel metal5 s 405840 6598 418360 19088 0 FreeSans 16000 0 0 0 flash_io0
+port 4 nsew signal output
+flabel metal5 s 460640 6598 473160 19088 0 FreeSans 16000 0 0 0 flash_io1
+port 5 nsew signal output
+flabel metal5 s 515440 6598 527960 19088 0 FreeSans 16000 0 0 0 gpio
+port 6 nsew signal bidirectional
+flabel metal5 s 698512 101240 711002 113760 0 FreeSans 16000 0 0 0 mprj_io[0]
+port 7 nsew signal bidirectional
+flabel metal5 s 698512 684440 711002 696960 0 FreeSans 16000 0 0 0 mprj_io[10]
+port 8 nsew signal bidirectional
+flabel metal5 s 698512 729440 711002 741960 0 FreeSans 16000 0 0 0 mprj_io[11]
+port 9 nsew signal bidirectional
+flabel metal5 s 698512 774440 711002 786960 0 FreeSans 16000 0 0 0 mprj_io[12]
+port 10 nsew signal bidirectional
+flabel metal5 s 698512 863640 711002 876160 0 FreeSans 16000 0 0 0 mprj_io[13]
+port 11 nsew signal bidirectional
+flabel metal5 s 698512 952840 711002 965360 0 FreeSans 16000 0 0 0 mprj_io[14]
+port 12 nsew signal bidirectional
+flabel metal5 s 628240 1018512 640760 1031002 0 FreeSans 16000 0 0 0 mprj_io[15]
+port 13 nsew signal bidirectional
+flabel metal5 s 526440 1018512 538960 1031002 0 FreeSans 16000 0 0 0 mprj_io[16]
+port 14 nsew signal bidirectional
+flabel metal5 s 475040 1018512 487560 1031002 0 FreeSans 16000 0 0 0 mprj_io[17]
+port 15 nsew signal bidirectional
+flabel metal5 s 386040 1018512 398560 1031002 0 FreeSans 16000 0 0 0 mprj_io[18]
+port 16 nsew signal bidirectional
+flabel metal5 s 284240 1018512 296760 1031002 0 FreeSans 16000 0 0 0 mprj_io[19]
+port 17 nsew signal bidirectional
+flabel metal5 s 698512 146440 711002 158960 0 FreeSans 16000 0 0 0 mprj_io[1]
+port 18 nsew signal bidirectional
+flabel metal5 s 232640 1018512 245160 1031002 0 FreeSans 16000 0 0 0 mprj_io[20]
+port 19 nsew signal bidirectional
+flabel metal5 s 181240 1018512 193760 1031002 0 FreeSans 16000 0 0 0 mprj_io[21]
+port 20 nsew signal bidirectional
+flabel metal5 s 129840 1018512 142360 1031002 0 FreeSans 16000 0 0 0 mprj_io[22]
+port 21 nsew signal bidirectional
+flabel metal5 s 78440 1018512 90960 1031002 0 FreeSans 16000 0 0 0 mprj_io[23]
+port 22 nsew signal bidirectional
+flabel metal5 s 6598 956440 19088 968960 0 FreeSans 16000 0 0 0 mprj_io[24]
+port 23 nsew signal bidirectional
+flabel metal5 s 6598 786640 19088 799160 0 FreeSans 16000 0 0 0 mprj_io[25]
+port 24 nsew signal bidirectional
+flabel metal5 s 6598 743440 19088 755960 0 FreeSans 16000 0 0 0 mprj_io[26]
+port 25 nsew signal bidirectional
+flabel metal5 s 6598 700240 19088 712760 0 FreeSans 16000 0 0 0 mprj_io[27]
+port 26 nsew signal bidirectional
+flabel metal5 s 6598 657040 19088 669560 0 FreeSans 16000 0 0 0 mprj_io[28]
+port 27 nsew signal bidirectional
+flabel metal5 s 6598 613840 19088 626360 0 FreeSans 16000 0 0 0 mprj_io[29]
+port 28 nsew signal bidirectional
+flabel metal5 s 698512 191440 711002 203960 0 FreeSans 16000 0 0 0 mprj_io[2]
+port 29 nsew signal bidirectional
+flabel metal5 s 6598 570640 19088 583160 0 FreeSans 16000 0 0 0 mprj_io[30]
+port 30 nsew signal bidirectional
+flabel metal5 s 6598 527440 19088 539960 0 FreeSans 16000 0 0 0 mprj_io[31]
+port 31 nsew signal bidirectional
+flabel metal5 s 6598 399840 19088 412360 0 FreeSans 16000 0 0 0 mprj_io[32]
+port 32 nsew signal bidirectional
+flabel metal5 s 6598 356640 19088 369160 0 FreeSans 16000 0 0 0 mprj_io[33]
+port 33 nsew signal bidirectional
+flabel metal5 s 6598 313440 19088 325960 0 FreeSans 16000 0 0 0 mprj_io[34]
+port 34 nsew signal bidirectional
+flabel metal5 s 6598 270240 19088 282760 0 FreeSans 16000 0 0 0 mprj_io[35]
+port 35 nsew signal bidirectional
+flabel metal5 s 6598 227040 19088 239560 0 FreeSans 16000 0 0 0 mprj_io[36]
+port 36 nsew signal bidirectional
+flabel metal5 s 6598 183840 19088 196360 0 FreeSans 16000 0 0 0 mprj_io[37]
+port 37 nsew signal bidirectional
+flabel metal5 s 698512 236640 711002 249160 0 FreeSans 16000 0 0 0 mprj_io[3]
+port 38 nsew signal bidirectional
+flabel metal5 s 698512 281640 711002 294160 0 FreeSans 16000 0 0 0 mprj_io[4]
+port 39 nsew signal bidirectional
+flabel metal5 s 698512 326640 711002 339160 0 FreeSans 16000 0 0 0 mprj_io[5]
+port 40 nsew signal bidirectional
+flabel metal5 s 698512 371840 711002 384360 0 FreeSans 16000 0 0 0 mprj_io[6]
+port 41 nsew signal bidirectional
+flabel metal5 s 698512 549040 711002 561560 0 FreeSans 16000 0 0 0 mprj_io[7]
+port 42 nsew signal bidirectional
+flabel metal5 s 698512 594240 711002 606760 0 FreeSans 16000 0 0 0 mprj_io[8]
+port 43 nsew signal bidirectional
+flabel metal5 s 698512 639240 711002 651760 0 FreeSans 16000 0 0 0 mprj_io[9]
+port 44 nsew signal bidirectional
+flabel metal5 s 136713 7143 144150 18309 0 FreeSans 16000 0 0 0 resetb
+port 45 nsew signal input
+flabel metal5 s 6167 70054 19620 80934 0 FreeSans 16000 0 0 0 vccd
+port 46 nsew power input
+flabel metal5 s 697980 909666 711433 920546 0 FreeSans 16000 0 0 0 vccd1
+port 47 nsew power input
+flabel metal5 s 6167 914054 19620 924934 0 FreeSans 16000 0 0 0 vccd2
+port 48 nsew power input
+flabel metal5 s 624222 6811 636390 18976 0 FreeSans 16000 0 0 0 vdda
+port 49 nsew power input
+flabel metal5 s 698624 819822 710789 831990 0 FreeSans 16000 0 0 0 vdda1
+port 50 nsew power input
+flabel metal5 s 698624 505222 710789 517390 0 FreeSans 16000 0 0 0 vdda1_2
+port 51 nsew power input
+flabel metal5 s 6811 484410 18976 496578 0 FreeSans 16000 0 0 0 vdda2
+port 52 nsew power input
+flabel metal5 s 6811 111610 18976 123778 0 FreeSans 16000 0 0 0 vddio
+port 53 nsew power input
+flabel metal5 s 6811 871210 18976 883378 0 FreeSans 16000 0 0 0 vddio_2
+port 54 nsew power input
+flabel metal5 s 80222 6811 92390 18976 0 FreeSans 16000 0 0 0 vssa
+port 55 nsew ground input
+flabel metal5 s 577010 1018624 589178 1030789 0 FreeSans 16000 0 0 0 vssa1
+port 56 nsew ground input
+flabel metal5 s 698624 417022 710789 429190 0 FreeSans 16000 0 0 0 vssa1_2
+port 57 nsew ground input
+flabel metal5 s 6811 829010 18976 841178 0 FreeSans 16000 0 0 0 vssa2
+port 58 nsew ground input
+flabel metal5 s 243266 6167 254146 19620 0 FreeSans 16000 0 0 0 vssd
+port 59 nsew ground input
+flabel metal5 s 697980 461866 711433 472746 0 FreeSans 16000 0 0 0 vssd1
+port 60 nsew ground input
+flabel metal5 s 6167 442854 19620 453734 0 FreeSans 16000 0 0 0 vssd2
+port 61 nsew ground input
+flabel metal5 s 570422 6811 582590 18976 0 FreeSans 16000 0 0 0 vssio
+port 62 nsew ground input
+flabel metal5 s 334810 1018624 346978 1030789 0 FreeSans 16000 0 0 0 vssio_2
+port 63 nsew ground input
+<< properties >>
+string FIXED_BBOX 0 0 717600 1037600
+string LEFclass BLOCK
+<< end >>
diff --git a/tapeout/outputs/mag/gpio_defaults_block_0403.mag b/tapeout/outputs/mag/gpio_defaults_block_0403.mag
new file mode 100644
index 0000000..e15b2ba
--- /dev/null
+++ b/tapeout/outputs/mag/gpio_defaults_block_0403.mag
@@ -0,0 +1,1461 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1638587925
+<< viali >>
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+<< via2 >>
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+<< metal3 >>
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+rect 4960 511 5240 512
+<< via3 >>
+rect 88 2204 152 2208
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+rect 88 2144 152 2148
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+rect 5148 572 5212 576
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+<< metal4 >>
+rect 60 2208 340 2224
+rect 60 2144 88 2208
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+rect 312 2144 340 2208
+rect 60 1120 340 2144
+rect 60 1056 88 1120
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+rect 4260 2208 4540 2224
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+rect 4960 1714 5240 2224
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+rect 4960 576 5240 1478
+rect 4960 512 4988 576
+rect 5052 512 5068 576
+rect 5132 512 5148 576
+rect 5212 512 5240 576
+rect 4960 496 5240 512
+<< via4 >>
+rect 82 778 318 1014
+rect 782 1664 1018 1714
+rect 782 1600 788 1664
+rect 788 1600 852 1664
+rect 852 1600 868 1664
+rect 868 1600 932 1664
+rect 932 1600 948 1664
+rect 948 1600 1012 1664
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+rect 2182 1664 2418 1714
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+rect 2182 1478 2418 1600
+rect 2882 778 3118 1014
+rect 3582 1664 3818 1714
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+rect 3582 1478 3818 1600
+rect 4282 778 4518 1014
+rect 4982 1664 5218 1714
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+rect 4988 1600 5052 1664
+rect 5052 1600 5068 1664
+rect 5068 1600 5132 1664
+rect 5132 1600 5148 1664
+rect 5148 1600 5212 1664
+rect 5212 1600 5218 1664
+rect 4982 1478 5218 1600
+<< metal5 >>
+rect 0 1714 5980 1756
+rect 0 1478 782 1714
+rect 1018 1478 2182 1714
+rect 2418 1478 3582 1714
+rect 3818 1478 4982 1714
+rect 5218 1478 5980 1714
+rect 0 1436 5980 1478
+rect 0 1014 5980 1056
+rect 0 778 82 1014
+rect 318 778 1482 1014
+rect 1718 778 2882 1014
+rect 3118 778 4282 1014
+rect 4518 778 5980 1014
+rect 0 736 5980 778
+use sky130_fd_sc_hd__fill_1 FILLER_0_9 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 828 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_3 PHY_2 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 0 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_0
+timestamp 1638322937
+transform 1 0 0 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12 FILLER_1_3 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 276 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_6 FILLER_0_3 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 276 0 1 544
+box -38 -48 590 592
+use sky130_fd_sc_hd__conb_1 gpio_default_value\[0\] $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 920 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12 FILLER_1_15
+timestamp 1638322937
+transform 1 0 1380 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__conb_1 gpio_default_value\[5\]
+timestamp 1638322937
+transform 1 0 2300 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 gpio_default_value\[1\]
+timestamp 1638322937
+transform 1 0 1196 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 gpio_default_value\[4\]
+timestamp 1638322937
+transform 1 0 2024 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 gpio_default_value\[3\]
+timestamp 1638322937
+transform 1 0 1748 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 gpio_default_value\[2\]
+timestamp 1638322937
+transform 1 0 1472 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_6 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 2576 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_2 FILLER_0_38 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 3496 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__fill_2 FILLER_0_33
+timestamp 1638322937
+transform 1 0 3036 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__fill_1 FILLER_0_29
+timestamp 1638322937
+transform 1 0 2668 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_12 FILLER_1_27
+timestamp 1638322937
+transform 1 0 2484 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__conb_1 gpio_default_value\[7\]
+timestamp 1638322937
+transform 1 0 3220 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 gpio_default_value\[6\]
+timestamp 1638322937
+transform 1 0 2760 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2 FILLER_0_43
+timestamp 1638322937
+transform 1 0 3956 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4 FILLER_1_51 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 4692 0 -1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1 FILLER_0_48
+timestamp 1638322937
+transform 1 0 4416 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_12 FILLER_1_39
+timestamp 1638322937
+transform 1 0 3588 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__conb_1 gpio_default_value\[9\]
+timestamp 1638322937
+transform 1 0 4140 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 gpio_default_value\[8\]
+timestamp 1638322937
+transform 1 0 3680 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 gpio_default_value\[12\]
+timestamp 1638322937
+transform 1 0 4508 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_8
+timestamp 1638322937
+transform 1 0 5152 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_7
+timestamp 1638322937
+transform 1 0 5152 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1 FILLER_1_55
+timestamp 1638322937
+transform 1 0 5060 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1 FILLER_0_55
+timestamp 1638322937
+transform 1 0 5060 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__conb_1 gpio_default_value\[10\]
+timestamp 1638322937
+transform 1 0 4784 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2 FILLER_0_60
+timestamp 1638322937
+transform 1 0 5520 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4 FILLER_1_57
+timestamp 1638322937
+transform 1 0 5244 0 -1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1 FILLER_1_61
+timestamp 1638322937
+transform 1 0 5612 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__conb_1 gpio_default_value\[11\]
+timestamp 1638322937
+transform 1 0 5244 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_3
+timestamp 1638322937
+transform -1 0 5980 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_1
+timestamp 1638322937
+transform -1 0 5980 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_4
+timestamp 1638322937
+transform 1 0 0 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12 FILLER_2_3
+timestamp 1638322937
+transform 1 0 276 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12 FILLER_2_15
+timestamp 1638322937
+transform 1 0 1380 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_9
+timestamp 1638322937
+transform 1 0 2576 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1 FILLER_2_27
+timestamp 1638322937
+transform 1 0 2484 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_12 FILLER_2_29
+timestamp 1638322937
+transform 1 0 2668 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12 FILLER_2_41
+timestamp 1638322937
+transform 1 0 3772 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_10
+timestamp 1638322937
+transform 1 0 5152 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_4 FILLER_2_57
+timestamp 1638322937
+transform 1 0 5244 0 1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1 FILLER_2_61
+timestamp 1638322937
+transform 1 0 5612 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_3 PHY_5
+timestamp 1638322937
+transform -1 0 5980 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 FILLER_2_53
+timestamp 1638322937
+transform 1 0 4876 0 1 1632
+box -38 -48 314 592
+<< labels >>
+rlabel metal5 s 0 1436 5980 1756 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 760 496 1040 2224 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 2160 496 2440 2224 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 3560 496 3840 2224 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 4960 496 5240 2224 6 VGND
+port 0 nsew ground input
+rlabel metal5 s 0 736 5980 1056 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 60 496 340 2224 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 1460 496 1740 2224 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 2860 496 3140 2224 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 4260 496 4540 2224 6 VPWR
+port 1 nsew power input
+rlabel metal2 s 202 0 258 400 6 gpio_defaults[0]
+port 2 nsew signal tristate
+rlabel metal2 s 4802 0 4858 400 6 gpio_defaults[10]
+port 3 nsew signal tristate
+rlabel metal2 s 5262 0 5318 400 6 gpio_defaults[11]
+port 4 nsew signal tristate
+rlabel metal2 s 5722 0 5778 400 6 gpio_defaults[12]
+port 5 nsew signal tristate
+rlabel metal2 s 662 0 718 400 6 gpio_defaults[1]
+port 6 nsew signal tristate
+rlabel metal2 s 1122 0 1178 400 6 gpio_defaults[2]
+port 7 nsew signal tristate
+rlabel metal2 s 1582 0 1638 400 6 gpio_defaults[3]
+port 8 nsew signal tristate
+rlabel metal2 s 2042 0 2098 400 6 gpio_defaults[4]
+port 9 nsew signal tristate
+rlabel metal2 s 2502 0 2558 400 6 gpio_defaults[5]
+port 10 nsew signal tristate
+rlabel metal2 s 2962 0 3018 400 6 gpio_defaults[6]
+port 11 nsew signal tristate
+rlabel metal2 s 3422 0 3478 400 6 gpio_defaults[7]
+port 12 nsew signal tristate
+rlabel metal2 s 3882 0 3938 400 6 gpio_defaults[8]
+port 13 nsew signal tristate
+rlabel metal2 s 4342 0 4398 400 6 gpio_defaults[9]
+port 14 nsew signal tristate
+<< properties >>
+string FIXED_BBOX 0 0 6000 2200
+<< end >>
diff --git a/tapeout/outputs/mag/gpio_defaults_block_0801.mag b/tapeout/outputs/mag/gpio_defaults_block_0801.mag
new file mode 100644
index 0000000..a5d837d
--- /dev/null
+++ b/tapeout/outputs/mag/gpio_defaults_block_0801.mag
@@ -0,0 +1,1461 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1638587925
+<< viali >>
+rect 949 833 983 867
+rect 1639 833 1673 867
+rect 4721 833 4755 867
+rect 1363 765 1397 799
+rect 1915 765 1949 799
+rect 2191 765 2225 799
+rect 2513 765 2547 799
+rect 2973 765 3007 799
+rect 3433 765 3467 799
+rect 3893 765 3927 799
+rect 4353 765 4387 799
+rect 4951 765 4985 799
+rect 5273 765 5307 799
+<< metal1 >>
+rect 0 2202 5980 2224
+rect 0 2150 78 2202
+rect 130 2150 142 2202
+rect 194 2150 206 2202
+rect 258 2150 270 2202
+rect 322 2150 1478 2202
+rect 1530 2150 1542 2202
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+rect 0 2128 5980 2150
+rect 0 1658 5980 1680
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+rect 1636 728 1722 756
+rect 1636 716 1642 728
+rect 716 688 722 700
+rect 0 570 5980 592
+rect 0 518 778 570
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+rect 0 496 5980 518
+<< via1 >>
+rect 78 2150 130 2202
+rect 142 2150 194 2202
+rect 206 2150 258 2202
+rect 270 2150 322 2202
+rect 1478 2150 1530 2202
+rect 1542 2150 1594 2202
+rect 1606 2150 1658 2202
+rect 1670 2150 1722 2202
+rect 2878 2150 2930 2202
+rect 2942 2150 2994 2202
+rect 3006 2150 3058 2202
+rect 3070 2150 3122 2202
+rect 4278 2150 4330 2202
+rect 4342 2150 4394 2202
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+rect 4470 2150 4522 2202
+rect 778 1606 830 1658
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+rect 2178 1606 2230 1658
+rect 2242 1606 2294 1658
+rect 2306 1606 2358 1658
+rect 2370 1606 2422 1658
+rect 3578 1606 3630 1658
+rect 3642 1606 3694 1658
+rect 3706 1606 3758 1658
+rect 3770 1606 3822 1658
+rect 4978 1606 5030 1658
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+rect 78 1062 130 1114
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+rect 4470 1062 4522 1114
+rect 204 824 256 876
+rect 1262 864 1314 916
+rect 5724 824 5776 876
+rect 664 688 716 740
+rect 1584 716 1636 768
+rect 2044 756 2096 808
+rect 2504 756 2556 808
+rect 2964 756 3016 808
+rect 3424 756 3476 808
+rect 3884 756 3936 808
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+rect 4804 756 4856 808
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+rect 778 518 830 570
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+rect 4978 518 5030 570
+rect 5042 518 5094 570
+rect 5106 518 5158 570
+rect 5170 518 5222 570
+<< metal2 >>
+rect 78 2204 322 2224
+rect 78 2202 92 2204
+rect 148 2202 172 2204
+rect 228 2202 252 2204
+rect 308 2202 322 2204
+rect 78 2148 92 2150
+rect 148 2148 172 2150
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+rect 4278 2204 4522 2224
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+rect 778 1660 1022 1680
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+rect 5276 400 5304 750
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+rect 202 0 258 400
+rect 662 0 718 400
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+rect 3882 0 3938 400
+rect 4342 0 4398 400
+rect 4802 0 4858 400
+rect 5262 0 5318 400
+rect 5722 0 5778 400
+<< via2 >>
+rect 92 2202 148 2204
+rect 172 2202 228 2204
+rect 252 2202 308 2204
+rect 92 2150 130 2202
+rect 130 2150 142 2202
+rect 142 2150 148 2202
+rect 172 2150 194 2202
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+rect 92 2148 148 2150
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+<< metal3 >>
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+<< via3 >>
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+<< metal4 >>
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+<< via4 >>
+rect 82 778 318 1014
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+<< metal5 >>
+rect 0 1714 5980 1756
+rect 0 1478 782 1714
+rect 1018 1478 2182 1714
+rect 2418 1478 3582 1714
+rect 3818 1478 4982 1714
+rect 5218 1478 5980 1714
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+rect 1718 778 2882 1014
+rect 3118 778 4282 1014
+rect 4518 778 5980 1014
+rect 0 736 5980 778
+use sky130_fd_sc_hd__fill_1 FILLER_0_9 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 828 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_3 PHY_2 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 0 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_0
+timestamp 1638322937
+transform 1 0 0 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12 FILLER_1_3 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 276 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_6 FILLER_0_3 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 276 0 1 544
+box -38 -48 590 592
+use sky130_fd_sc_hd__conb_1 gpio_default_value\[0\] $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 920 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12 FILLER_1_15
+timestamp 1638322937
+transform 1 0 1380 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__conb_1 gpio_default_value\[5\]
+timestamp 1638322937
+transform 1 0 2300 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 gpio_default_value\[1\]
+timestamp 1638322937
+transform 1 0 1196 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 gpio_default_value\[4\]
+timestamp 1638322937
+transform 1 0 2024 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 gpio_default_value\[3\]
+timestamp 1638322937
+transform 1 0 1748 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 gpio_default_value\[2\]
+timestamp 1638322937
+transform 1 0 1472 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_6 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 2576 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_2 FILLER_0_38 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 3496 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__fill_2 FILLER_0_33
+timestamp 1638322937
+transform 1 0 3036 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__fill_1 FILLER_0_29
+timestamp 1638322937
+transform 1 0 2668 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_12 FILLER_1_27
+timestamp 1638322937
+transform 1 0 2484 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__conb_1 gpio_default_value\[7\]
+timestamp 1638322937
+transform 1 0 3220 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 gpio_default_value\[6\]
+timestamp 1638322937
+transform 1 0 2760 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2 FILLER_0_43
+timestamp 1638322937
+transform 1 0 3956 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4 FILLER_1_51 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 4692 0 -1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1 FILLER_0_48
+timestamp 1638322937
+transform 1 0 4416 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_12 FILLER_1_39
+timestamp 1638322937
+transform 1 0 3588 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__conb_1 gpio_default_value\[9\]
+timestamp 1638322937
+transform 1 0 4140 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 gpio_default_value\[8\]
+timestamp 1638322937
+transform 1 0 3680 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 gpio_default_value\[12\]
+timestamp 1638322937
+transform 1 0 4508 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_8
+timestamp 1638322937
+transform 1 0 5152 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_7
+timestamp 1638322937
+transform 1 0 5152 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1 FILLER_1_55
+timestamp 1638322937
+transform 1 0 5060 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1 FILLER_0_55
+timestamp 1638322937
+transform 1 0 5060 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__conb_1 gpio_default_value\[10\]
+timestamp 1638322937
+transform 1 0 4784 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2 FILLER_0_60
+timestamp 1638322937
+transform 1 0 5520 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4 FILLER_1_57
+timestamp 1638322937
+transform 1 0 5244 0 -1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1 FILLER_1_61
+timestamp 1638322937
+transform 1 0 5612 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__conb_1 gpio_default_value\[11\]
+timestamp 1638322937
+transform 1 0 5244 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_3
+timestamp 1638322937
+transform -1 0 5980 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_1
+timestamp 1638322937
+transform -1 0 5980 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_4
+timestamp 1638322937
+transform 1 0 0 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12 FILLER_2_3
+timestamp 1638322937
+transform 1 0 276 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12 FILLER_2_15
+timestamp 1638322937
+transform 1 0 1380 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_9
+timestamp 1638322937
+transform 1 0 2576 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1 FILLER_2_27
+timestamp 1638322937
+transform 1 0 2484 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_12 FILLER_2_29
+timestamp 1638322937
+transform 1 0 2668 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12 FILLER_2_41
+timestamp 1638322937
+transform 1 0 3772 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_10
+timestamp 1638322937
+transform 1 0 5152 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_4 FILLER_2_57
+timestamp 1638322937
+transform 1 0 5244 0 1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1 FILLER_2_61
+timestamp 1638322937
+transform 1 0 5612 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_3 PHY_5
+timestamp 1638322937
+transform -1 0 5980 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 FILLER_2_53
+timestamp 1638322937
+transform 1 0 4876 0 1 1632
+box -38 -48 314 592
+<< labels >>
+rlabel metal5 s 0 1436 5980 1756 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 760 496 1040 2224 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 2160 496 2440 2224 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 3560 496 3840 2224 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 4960 496 5240 2224 6 VGND
+port 0 nsew ground input
+rlabel metal5 s 0 736 5980 1056 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 60 496 340 2224 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 1460 496 1740 2224 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 2860 496 3140 2224 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 4260 496 4540 2224 6 VPWR
+port 1 nsew power input
+rlabel metal2 s 202 0 258 400 6 gpio_defaults[0]
+port 2 nsew signal tristate
+rlabel metal2 s 4802 0 4858 400 6 gpio_defaults[10]
+port 3 nsew signal tristate
+rlabel metal2 s 5262 0 5318 400 6 gpio_defaults[11]
+port 4 nsew signal tristate
+rlabel metal2 s 5722 0 5778 400 6 gpio_defaults[12]
+port 5 nsew signal tristate
+rlabel metal2 s 662 0 718 400 6 gpio_defaults[1]
+port 6 nsew signal tristate
+rlabel metal2 s 1122 0 1178 400 6 gpio_defaults[2]
+port 7 nsew signal tristate
+rlabel metal2 s 1582 0 1638 400 6 gpio_defaults[3]
+port 8 nsew signal tristate
+rlabel metal2 s 2042 0 2098 400 6 gpio_defaults[4]
+port 9 nsew signal tristate
+rlabel metal2 s 2502 0 2558 400 6 gpio_defaults[5]
+port 10 nsew signal tristate
+rlabel metal2 s 2962 0 3018 400 6 gpio_defaults[6]
+port 11 nsew signal tristate
+rlabel metal2 s 3422 0 3478 400 6 gpio_defaults[7]
+port 12 nsew signal tristate
+rlabel metal2 s 3882 0 3938 400 6 gpio_defaults[8]
+port 13 nsew signal tristate
+rlabel metal2 s 4342 0 4398 400 6 gpio_defaults[9]
+port 14 nsew signal tristate
+<< properties >>
+string FIXED_BBOX 0 0 6000 2200
+<< end >>
diff --git a/tapeout/outputs/mag/gpio_defaults_block_1803.mag b/tapeout/outputs/mag/gpio_defaults_block_1803.mag
new file mode 100644
index 0000000..39a381a
--- /dev/null
+++ b/tapeout/outputs/mag/gpio_defaults_block_1803.mag
@@ -0,0 +1,1461 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1638587925
+<< viali >>
+rect 949 833 983 867
+rect 1639 833 1673 867
+rect 4583 833 4617 867
+rect 1225 765 1259 799
+rect 1915 765 1949 799
+rect 2191 765 2225 799
+rect 2513 765 2547 799
+rect 2973 765 3007 799
+rect 3433 765 3467 799
+rect 3893 765 3927 799
+rect 4353 765 4387 799
+rect 4951 765 4985 799
+rect 5273 765 5307 799
+<< metal1 >>
+rect 0 2202 5980 2224
+rect 0 2150 78 2202
+rect 130 2150 142 2202
+rect 194 2150 206 2202
+rect 258 2150 270 2202
+rect 322 2150 1478 2202
+rect 1530 2150 1542 2202
+rect 1594 2150 1606 2202
+rect 1658 2150 1670 2202
+rect 1722 2150 2878 2202
+rect 2930 2150 2942 2202
+rect 2994 2150 3006 2202
+rect 3058 2150 3070 2202
+rect 3122 2150 4278 2202
+rect 4330 2150 4342 2202
+rect 4394 2150 4406 2202
+rect 4458 2150 4470 2202
+rect 4522 2150 5980 2202
+rect 0 2128 5980 2150
+rect 0 1658 5980 1680
+rect 0 1606 778 1658
+rect 830 1606 842 1658
+rect 894 1606 906 1658
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+rect 1022 1606 2178 1658
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+rect 5222 1606 5980 1658
+rect 0 1584 5980 1606
+rect 0 1114 5980 1136
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+rect 2038 796 2044 808
+rect 1038 768 1409 796
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+rect 658 688 664 740
+rect 716 728 722 740
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+rect 4161 768 4344 796
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+rect 4396 756 4402 808
+rect 4798 796 4804 808
+rect 4759 768 4804 796
+rect 4798 756 4804 768
+rect 4856 796 4862 808
+rect 4936 796 5000 808
+rect 5258 796 5264 808
+rect 4856 768 5000 796
+rect 5219 768 5264 796
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+rect 5396 796 5460 808
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+rect 5316 756 5322 768
+rect 5396 756 5460 768
+rect 1636 728 1722 756
+rect 1636 716 1642 728
+rect 716 688 722 700
+rect 0 570 5980 592
+rect 0 518 778 570
+rect 830 518 842 570
+rect 894 518 906 570
+rect 958 518 970 570
+rect 1022 518 2178 570
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+rect 5030 518 5042 570
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+rect 5158 518 5170 570
+rect 5222 518 5980 570
+rect 0 496 5980 518
+<< via1 >>
+rect 78 2150 130 2202
+rect 142 2150 194 2202
+rect 206 2150 258 2202
+rect 270 2150 322 2202
+rect 1478 2150 1530 2202
+rect 1542 2150 1594 2202
+rect 1606 2150 1658 2202
+rect 1670 2150 1722 2202
+rect 2878 2150 2930 2202
+rect 2942 2150 2994 2202
+rect 3006 2150 3058 2202
+rect 3070 2150 3122 2202
+rect 4278 2150 4330 2202
+rect 4342 2150 4394 2202
+rect 4406 2150 4458 2202
+rect 4470 2150 4522 2202
+rect 778 1606 830 1658
+rect 842 1606 894 1658
+rect 906 1606 958 1658
+rect 970 1606 1022 1658
+rect 2178 1606 2230 1658
+rect 2242 1606 2294 1658
+rect 2306 1606 2358 1658
+rect 2370 1606 2422 1658
+rect 3578 1606 3630 1658
+rect 3642 1606 3694 1658
+rect 3706 1606 3758 1658
+rect 3770 1606 3822 1658
+rect 4978 1606 5030 1658
+rect 5042 1606 5094 1658
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+rect 5170 1606 5222 1658
+rect 78 1062 130 1114
+rect 142 1062 194 1114
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+rect 270 1062 322 1114
+rect 1478 1062 1530 1114
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+rect 3006 1062 3058 1114
+rect 3070 1062 3122 1114
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+rect 4406 1062 4458 1114
+rect 4470 1062 4522 1114
+rect 204 824 256 876
+rect 1262 864 1314 916
+rect 5724 824 5776 876
+rect 664 688 716 740
+rect 1584 716 1636 768
+rect 2044 756 2096 808
+rect 2504 756 2556 808
+rect 2964 756 3016 808
+rect 3424 756 3476 808
+rect 3884 756 3936 808
+rect 4344 756 4396 808
+rect 4804 756 4856 808
+rect 5264 756 5316 808
+rect 778 518 830 570
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+rect 4978 518 5030 570
+rect 5042 518 5094 570
+rect 5106 518 5158 570
+rect 5170 518 5222 570
+<< metal2 >>
+rect 78 2204 322 2224
+rect 78 2202 92 2204
+rect 148 2202 172 2204
+rect 228 2202 252 2204
+rect 308 2202 322 2204
+rect 78 2148 92 2150
+rect 148 2148 172 2150
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+rect 78 2128 322 2148
+rect 1478 2204 1722 2224
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+rect 1548 2202 1572 2204
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+rect 1708 2202 1722 2204
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+rect 1548 2148 1572 2150
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+rect 1478 2128 1722 2148
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+rect 3028 2202 3052 2204
+rect 3108 2202 3122 2204
+rect 2878 2148 2892 2150
+rect 2948 2148 2972 2150
+rect 3028 2148 3052 2150
+rect 3108 2148 3122 2150
+rect 2878 2128 3122 2148
+rect 4278 2204 4522 2224
+rect 4278 2202 4292 2204
+rect 4348 2202 4372 2204
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+rect 4278 2148 4292 2150
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+rect 4278 2128 4522 2148
+rect 778 1660 1022 1680
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+rect 4518 778 4540 1014
+rect 4260 496 4540 778
+rect 4960 1714 5240 2224
+rect 4960 1478 4982 1714
+rect 5218 1478 5240 1714
+rect 4960 576 5240 1478
+rect 4960 512 4988 576
+rect 5052 512 5068 576
+rect 5132 512 5148 576
+rect 5212 512 5240 576
+rect 4960 496 5240 512
+<< via4 >>
+rect 82 778 318 1014
+rect 782 1664 1018 1714
+rect 782 1600 788 1664
+rect 788 1600 852 1664
+rect 852 1600 868 1664
+rect 868 1600 932 1664
+rect 932 1600 948 1664
+rect 948 1600 1012 1664
+rect 1012 1600 1018 1664
+rect 782 1478 1018 1600
+rect 1482 778 1718 1014
+rect 2182 1664 2418 1714
+rect 2182 1600 2188 1664
+rect 2188 1600 2252 1664
+rect 2252 1600 2268 1664
+rect 2268 1600 2332 1664
+rect 2332 1600 2348 1664
+rect 2348 1600 2412 1664
+rect 2412 1600 2418 1664
+rect 2182 1478 2418 1600
+rect 2882 778 3118 1014
+rect 3582 1664 3818 1714
+rect 3582 1600 3588 1664
+rect 3588 1600 3652 1664
+rect 3652 1600 3668 1664
+rect 3668 1600 3732 1664
+rect 3732 1600 3748 1664
+rect 3748 1600 3812 1664
+rect 3812 1600 3818 1664
+rect 3582 1478 3818 1600
+rect 4282 778 4518 1014
+rect 4982 1664 5218 1714
+rect 4982 1600 4988 1664
+rect 4988 1600 5052 1664
+rect 5052 1600 5068 1664
+rect 5068 1600 5132 1664
+rect 5132 1600 5148 1664
+rect 5148 1600 5212 1664
+rect 5212 1600 5218 1664
+rect 4982 1478 5218 1600
+<< metal5 >>
+rect 0 1714 5980 1756
+rect 0 1478 782 1714
+rect 1018 1478 2182 1714
+rect 2418 1478 3582 1714
+rect 3818 1478 4982 1714
+rect 5218 1478 5980 1714
+rect 0 1436 5980 1478
+rect 0 1014 5980 1056
+rect 0 778 82 1014
+rect 318 778 1482 1014
+rect 1718 778 2882 1014
+rect 3118 778 4282 1014
+rect 4518 778 5980 1014
+rect 0 736 5980 778
+use sky130_fd_sc_hd__fill_1 FILLER_0_9 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 828 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_3 PHY_2 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 0 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_0
+timestamp 1638322937
+transform 1 0 0 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12 FILLER_1_3 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 276 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_6 FILLER_0_3 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 276 0 1 544
+box -38 -48 590 592
+use sky130_fd_sc_hd__conb_1 gpio_default_value\[0\] $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 920 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12 FILLER_1_15
+timestamp 1638322937
+transform 1 0 1380 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__conb_1 gpio_default_value\[5\]
+timestamp 1638322937
+transform 1 0 2300 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 gpio_default_value\[1\]
+timestamp 1638322937
+transform 1 0 1196 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 gpio_default_value\[4\]
+timestamp 1638322937
+transform 1 0 2024 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 gpio_default_value\[3\]
+timestamp 1638322937
+transform 1 0 1748 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 gpio_default_value\[2\]
+timestamp 1638322937
+transform 1 0 1472 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_6 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 2576 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_2 FILLER_0_38 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 3496 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__fill_2 FILLER_0_33
+timestamp 1638322937
+transform 1 0 3036 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__fill_1 FILLER_0_29
+timestamp 1638322937
+transform 1 0 2668 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_12 FILLER_1_27
+timestamp 1638322937
+transform 1 0 2484 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__conb_1 gpio_default_value\[7\]
+timestamp 1638322937
+transform 1 0 3220 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 gpio_default_value\[6\]
+timestamp 1638322937
+transform 1 0 2760 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2 FILLER_0_43
+timestamp 1638322937
+transform 1 0 3956 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4 FILLER_1_51 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638322937
+transform 1 0 4692 0 -1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1 FILLER_0_48
+timestamp 1638322937
+transform 1 0 4416 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_12 FILLER_1_39
+timestamp 1638322937
+transform 1 0 3588 0 -1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__conb_1 gpio_default_value\[9\]
+timestamp 1638322937
+transform 1 0 4140 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 gpio_default_value\[8\]
+timestamp 1638322937
+transform 1 0 3680 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 gpio_default_value\[12\]
+timestamp 1638322937
+transform 1 0 4508 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_8
+timestamp 1638322937
+transform 1 0 5152 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_7
+timestamp 1638322937
+transform 1 0 5152 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1 FILLER_1_55
+timestamp 1638322937
+transform 1 0 5060 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1 FILLER_0_55
+timestamp 1638322937
+transform 1 0 5060 0 1 544
+box -38 -48 130 592
+use sky130_fd_sc_hd__conb_1 gpio_default_value\[10\]
+timestamp 1638322937
+transform 1 0 4784 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2 FILLER_0_60
+timestamp 1638322937
+transform 1 0 5520 0 1 544
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4 FILLER_1_57
+timestamp 1638322937
+transform 1 0 5244 0 -1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1 FILLER_1_61
+timestamp 1638322937
+transform 1 0 5612 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__conb_1 gpio_default_value\[11\]
+timestamp 1638322937
+transform 1 0 5244 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_3
+timestamp 1638322937
+transform -1 0 5980 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_1
+timestamp 1638322937
+transform -1 0 5980 0 1 544
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_4
+timestamp 1638322937
+transform 1 0 0 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12 FILLER_2_3
+timestamp 1638322937
+transform 1 0 276 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12 FILLER_2_15
+timestamp 1638322937
+transform 1 0 1380 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_9
+timestamp 1638322937
+transform 1 0 2576 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1 FILLER_2_27
+timestamp 1638322937
+transform 1 0 2484 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_12 FILLER_2_29
+timestamp 1638322937
+transform 1 0 2668 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12 FILLER_2_41
+timestamp 1638322937
+transform 1 0 3772 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_10
+timestamp 1638322937
+transform 1 0 5152 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_4 FILLER_2_57
+timestamp 1638322937
+transform 1 0 5244 0 1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1 FILLER_2_61
+timestamp 1638322937
+transform 1 0 5612 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_3 PHY_5
+timestamp 1638322937
+transform -1 0 5980 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 FILLER_2_53
+timestamp 1638322937
+transform 1 0 4876 0 1 1632
+box -38 -48 314 592
+<< labels >>
+rlabel metal5 s 0 1436 5980 1756 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 760 496 1040 2224 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 2160 496 2440 2224 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 3560 496 3840 2224 6 VGND
+port 0 nsew ground input
+rlabel metal4 s 4960 496 5240 2224 6 VGND
+port 0 nsew ground input
+rlabel metal5 s 0 736 5980 1056 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 60 496 340 2224 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 1460 496 1740 2224 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 2860 496 3140 2224 6 VPWR
+port 1 nsew power input
+rlabel metal4 s 4260 496 4540 2224 6 VPWR
+port 1 nsew power input
+rlabel metal2 s 202 0 258 400 6 gpio_defaults[0]
+port 2 nsew signal tristate
+rlabel metal2 s 4802 0 4858 400 6 gpio_defaults[10]
+port 3 nsew signal tristate
+rlabel metal2 s 5262 0 5318 400 6 gpio_defaults[11]
+port 4 nsew signal tristate
+rlabel metal2 s 5722 0 5778 400 6 gpio_defaults[12]
+port 5 nsew signal tristate
+rlabel metal2 s 662 0 718 400 6 gpio_defaults[1]
+port 6 nsew signal tristate
+rlabel metal2 s 1122 0 1178 400 6 gpio_defaults[2]
+port 7 nsew signal tristate
+rlabel metal2 s 1582 0 1638 400 6 gpio_defaults[3]
+port 8 nsew signal tristate
+rlabel metal2 s 2042 0 2098 400 6 gpio_defaults[4]
+port 9 nsew signal tristate
+rlabel metal2 s 2502 0 2558 400 6 gpio_defaults[5]
+port 10 nsew signal tristate
+rlabel metal2 s 2962 0 3018 400 6 gpio_defaults[6]
+port 11 nsew signal tristate
+rlabel metal2 s 3422 0 3478 400 6 gpio_defaults[7]
+port 12 nsew signal tristate
+rlabel metal2 s 3882 0 3938 400 6 gpio_defaults[8]
+port 13 nsew signal tristate
+rlabel metal2 s 4342 0 4398 400 6 gpio_defaults[9]
+port 14 nsew signal tristate
+<< properties >>
+string FIXED_BBOX 0 0 6000 2200
+<< end >>
diff --git a/tapeout/outputs/mag/user_id_prog_zero.mag b/tapeout/outputs/mag/user_id_prog_zero.mag
new file mode 100644
index 0000000..6ad139c
--- /dev/null
+++ b/tapeout/outputs/mag/user_id_prog_zero.mag
@@ -0,0 +1,3074 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1650371074
+<< nwell >>
+rect 2304 2369 2397 2389
+<< viali >>
+rect 4353 5117 4387 5151
+rect 5273 5117 5307 5151
+rect 2145 4641 2179 4675
+rect 3249 4641 3283 4675
+rect 3617 4641 3651 4675
+rect 4721 4641 4755 4675
+rect 1593 4029 1627 4063
+rect 2053 4029 2087 4063
+rect 4445 4029 4479 4063
+rect 4721 4029 4755 4063
+rect 5549 4029 5583 4063
+rect 1685 3553 1719 3587
+rect 1961 3553 1995 3587
+rect 2697 3553 2731 3587
+rect 3157 3553 3191 3587
+rect 3433 3553 3467 3587
+rect 4261 3553 4295 3587
+rect 4813 3553 4847 3587
+rect 5273 3553 5307 3587
+rect 1593 2941 1627 2975
+rect 4813 2397 4847 2431
+rect 5089 2397 5123 2431
+rect 1593 1853 1627 1887
+rect 2145 1853 2179 1887
+rect 2605 1853 2639 1887
+rect 2881 1853 2915 1887
+rect 3249 1853 3283 1887
+rect 4077 1853 4111 1887
+rect 5641 1853 5675 1887
+rect 1685 1377 1719 1411
+rect 2973 1377 3007 1411
+rect 4629 1377 4663 1411
+<< locali >>
+rect 4353 5117 4387 5151
+rect 5273 5117 5307 5151
+rect 2145 4641 2179 4675
+rect 3249 4641 3283 4675
+rect 3617 4641 3651 4675
+rect 4721 4641 4755 4675
+rect 1593 4029 1627 4063
+rect 2053 4029 2087 4063
+rect 4445 4029 4479 4063
+rect 4721 4029 4755 4063
+rect 5549 4029 5583 4063
+rect 1685 3553 1719 3587
+rect 1961 3553 1995 3587
+rect 2697 3553 2731 3587
+rect 3157 3553 3191 3587
+rect 3433 3553 3467 3587
+rect 4261 3553 4295 3587
+rect 4813 3553 4847 3587
+rect 5273 3553 5307 3587
+rect 1593 2941 1627 2975
+rect 4813 2397 4847 2431
+rect 5089 2397 5123 2431
+rect 1593 1853 1627 1887
+rect 2145 1853 2179 1887
+rect 2605 1853 2639 1887
+rect 2881 1853 2915 1887
+rect 3249 1853 3283 1887
+rect 4077 1853 4111 1887
+rect 5641 1853 5675 1887
+rect 1685 1377 1719 1411
+rect 2973 1377 3007 1411
+rect 4629 1377 4663 1411
+<< metal1 >>
+rect 1104 6010 5980 6032
+rect 1104 5958 2607 6010
+rect 2659 5958 2671 6010
+rect 2723 5958 2735 6010
+rect 2787 5958 2799 6010
+rect 2851 5958 4232 6010
+rect 4284 5958 4296 6010
+rect 4348 5958 4360 6010
+rect 4412 5958 4424 6010
+rect 4476 5958 5980 6010
+rect 1104 5936 5980 5958
+rect 1104 5466 5980 5488
+rect 1104 5414 1794 5466
+rect 1846 5414 1858 5466
+rect 1910 5414 1922 5466
+rect 1974 5414 1986 5466
+rect 2038 5414 3420 5466
+rect 3472 5414 3484 5466
+rect 3536 5414 3548 5466
+rect 3600 5414 3612 5466
+rect 3664 5414 5045 5466
+rect 5097 5414 5109 5466
+rect 5161 5414 5173 5466
+rect 5225 5414 5237 5466
+rect 5289 5414 5980 5466
+rect 1104 5392 5980 5414
+rect 4062 5108 4068 5160
+rect 4120 5148 4126 5160
+rect 4157 5148 4215 5157
+rect 4341 5148 4399 5157
+rect 4120 5120 4399 5148
+rect 4120 5108 4126 5120
+rect 4157 5111 4215 5120
+rect 4341 5111 4399 5120
+rect 4614 5108 4620 5160
+rect 4672 5148 4678 5160
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+rect 4672 5120 5319 5148
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+rect 3600 4326 3612 4378
+rect 3664 4326 5045 4378
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+rect 5161 4326 5173 4378
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+rect 5289 4326 5980 4378
+rect 1104 4304 5980 4326
+rect 3050 4224 3056 4276
+rect 3108 4264 3114 4276
+rect 3108 4236 4568 4264
+rect 3108 4224 3114 4236
+rect 1394 4156 1400 4208
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+rect 5077 3547 5135 3556
+rect 5261 3547 5319 3556
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+rect 3614 2144 3630 2208
+rect 3694 2144 3702 2208
+rect 3382 1974 3702 2144
+rect 3382 1738 3424 1974
+rect 3660 1738 3702 1974
+rect 3382 1120 3702 1738
+rect 3382 1056 3390 1120
+rect 3454 1056 3470 1120
+rect 3534 1056 3550 1120
+rect 3614 1056 3630 1120
+rect 3694 1056 3702 1120
+rect 3382 1040 3702 1056
+rect 4194 6016 4514 6032
+rect 4194 5952 4202 6016
+rect 4266 5952 4282 6016
+rect 4346 5952 4362 6016
+rect 4426 5952 4442 6016
+rect 4506 5952 4514 6016
+rect 4194 4928 4514 5952
+rect 4194 4864 4202 4928
+rect 4266 4864 4282 4928
+rect 4346 4864 4362 4928
+rect 4426 4864 4442 4928
+rect 4506 4864 4514 4928
+rect 4194 4422 4514 4864
+rect 4194 4186 4236 4422
+rect 4472 4186 4514 4422
+rect 4194 3840 4514 4186
+rect 4194 3776 4202 3840
+rect 4266 3776 4282 3840
+rect 4346 3776 4362 3840
+rect 4426 3776 4442 3840
+rect 4506 3776 4514 3840
+rect 4194 2790 4514 3776
+rect 4194 2752 4236 2790
+rect 4472 2752 4514 2790
+rect 4194 2688 4202 2752
+rect 4506 2688 4514 2752
+rect 4194 2554 4236 2688
+rect 4472 2554 4514 2688
+rect 4194 1664 4514 2554
+rect 4194 1600 4202 1664
+rect 4266 1600 4282 1664
+rect 4346 1600 4362 1664
+rect 4426 1600 4442 1664
+rect 4506 1600 4514 1664
+rect 4194 1040 4514 1600
+rect 5007 5472 5327 6032
+rect 5007 5408 5015 5472
+rect 5079 5408 5095 5472
+rect 5159 5408 5175 5472
+rect 5239 5408 5255 5472
+rect 5319 5408 5327 5472
+rect 5007 5238 5327 5408
+rect 5007 5002 5049 5238
+rect 5285 5002 5327 5238
+rect 5007 4384 5327 5002
+rect 5007 4320 5015 4384
+rect 5079 4320 5095 4384
+rect 5159 4320 5175 4384
+rect 5239 4320 5255 4384
+rect 5319 4320 5327 4384
+rect 5007 3606 5327 4320
+rect 5007 3370 5049 3606
+rect 5285 3370 5327 3606
+rect 5007 3296 5327 3370
+rect 5007 3232 5015 3296
+rect 5079 3232 5095 3296
+rect 5159 3232 5175 3296
+rect 5239 3232 5255 3296
+rect 5319 3232 5327 3296
+rect 5007 2208 5327 3232
+rect 5007 2144 5015 2208
+rect 5079 2144 5095 2208
+rect 5159 2144 5175 2208
+rect 5239 2144 5255 2208
+rect 5319 2144 5327 2208
+rect 5007 1974 5327 2144
+rect 5007 1738 5049 1974
+rect 5285 1738 5327 1974
+rect 5007 1120 5327 1738
+rect 5007 1056 5015 1120
+rect 5079 1056 5095 1120
+rect 5159 1056 5175 1120
+rect 5239 1056 5255 1120
+rect 5319 1056 5327 1120
+rect 5007 1040 5327 1056
+<< via4 >>
+rect 1798 5002 2034 5238
+rect 1798 3370 2034 3606
+rect 1798 1738 2034 1974
+rect 2611 4186 2847 4422
+rect 2611 2752 2847 2790
+rect 2611 2688 2641 2752
+rect 2641 2688 2657 2752
+rect 2657 2688 2721 2752
+rect 2721 2688 2737 2752
+rect 2737 2688 2801 2752
+rect 2801 2688 2817 2752
+rect 2817 2688 2847 2752
+rect 2611 2554 2847 2688
+rect 3424 5002 3660 5238
+rect 3424 3370 3660 3606
+rect 3424 1738 3660 1974
+rect 4236 4186 4472 4422
+rect 4236 2752 4472 2790
+rect 4236 2688 4266 2752
+rect 4266 2688 4282 2752
+rect 4282 2688 4346 2752
+rect 4346 2688 4362 2752
+rect 4362 2688 4426 2752
+rect 4426 2688 4442 2752
+rect 4442 2688 4472 2752
+rect 4236 2554 4472 2688
+rect 5049 5002 5285 5238
+rect 5049 3370 5285 3606
+rect 5049 1738 5285 1974
+<< metal5 >>
+rect 1104 5238 5980 5280
+rect 1104 5002 1798 5238
+rect 2034 5002 3424 5238
+rect 3660 5002 5049 5238
+rect 5285 5002 5980 5238
+rect 1104 4960 5980 5002
+rect 1104 4422 5980 4464
+rect 1104 4186 2611 4422
+rect 2847 4186 4236 4422
+rect 4472 4186 5980 4422
+rect 1104 4144 5980 4186
+rect 1104 3606 5980 3648
+rect 1104 3370 1798 3606
+rect 2034 3370 3424 3606
+rect 3660 3370 5049 3606
+rect 5285 3370 5980 3606
+rect 1104 3328 5980 3370
+rect 1104 2790 5980 2832
+rect 1104 2554 2611 2790
+rect 2847 2554 4236 2790
+rect 4472 2554 5980 2790
+rect 1104 2512 5980 2554
+rect 1104 1974 5980 2016
+rect 1104 1738 1798 1974
+rect 2034 1738 3424 1974
+rect 3660 1738 5049 1974
+rect 5285 1738 5980 1974
+rect 1104 1696 5980 1738
+use sky130_fd_sc_hd__fill_1 FILLER_0_3 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 1380 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_8 FILLER_0_7 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1648946573
+transform 1 0 1748 0 -1 1632
+box -38 -48 774 592
+use sky130_fd_sc_hd__decap_3 FILLER_0_15 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 2484 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_8 FILLER_0_21
+timestamp 1648946573
+transform 1 0 3036 0 -1 1632
+box -38 -48 774 592
+use sky130_fd_sc_hd__fill_2 FILLER_0_29 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 3772 0 -1 1632
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4 FILLER_0_32 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 4048 0 -1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_8 FILLER_0_39
+timestamp 1648946573
+transform 1 0 4692 0 -1 1632
+box -38 -48 774 592
+use sky130_fd_sc_hd__decap_3 FILLER_0_47
+timestamp 1638025753
+transform 1 0 5428 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 FILLER_1_6
+timestamp 1638025753
+transform 1 0 1656 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2 FILLER_1_12
+timestamp 1638025753
+transform 1 0 2208 0 1 1632
+box -38 -48 222 592
+use sky130_fd_sc_hd__fill_1 FILLER_1_20
+timestamp 1638025753
+transform 1 0 2944 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_6 FILLER_1_24 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 3312 0 1 1632
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_12 FILLER_1_33 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 4140 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__fill_2 FILLER_1_45
+timestamp 1638025753
+transform 1 0 5244 0 1 1632
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_12 FILLER_2_3
+timestamp 1638025753
+transform 1 0 1380 0 -1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12 FILLER_2_15
+timestamp 1638025753
+transform 1 0 2484 0 -1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_4 FILLER_2_27
+timestamp 1638025753
+transform 1 0 3588 0 -1 2720
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_6 FILLER_2_32
+timestamp 1638025753
+transform 1 0 4048 0 -1 2720
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_6 FILLER_2_44
+timestamp 1638025753
+transform 1 0 5152 0 -1 2720
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_12 FILLER_3_6
+timestamp 1638025753
+transform 1 0 1656 0 1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12 FILLER_3_18
+timestamp 1638025753
+transform 1 0 2760 0 1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12 FILLER_3_30
+timestamp 1638025753
+transform 1 0 3864 0 1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_8 FILLER_3_42
+timestamp 1648946573
+transform 1 0 4968 0 1 2720
+box -38 -48 774 592
+use sky130_fd_sc_hd__fill_1 FILLER_4_3
+timestamp 1638025753
+transform 1 0 1380 0 -1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_4 FILLER_4_10
+timestamp 1638025753
+transform 1 0 2024 0 -1 3808
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1 FILLER_4_14
+timestamp 1638025753
+transform 1 0 2392 0 -1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_2 FILLER_4_18
+timestamp 1638025753
+transform 1 0 2760 0 -1 3808
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4 FILLER_4_26
+timestamp 1638025753
+transform 1 0 3496 0 -1 3808
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1 FILLER_4_30
+timestamp 1638025753
+transform 1 0 3864 0 -1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_3 FILLER_4_35
+timestamp 1638025753
+transform 1 0 4324 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2 FILLER_4_41
+timestamp 1638025753
+transform 1 0 4876 0 -1 3808
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4 FILLER_4_46
+timestamp 1638025753
+transform 1 0 5336 0 -1 3808
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_2 FILLER_5_6
+timestamp 1638025753
+transform 1 0 1656 0 1 3808
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_12 FILLER_5_11
+timestamp 1638025753
+transform 1 0 2116 0 1 3808
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_8 FILLER_5_23
+timestamp 1648946573
+transform 1 0 3220 0 1 3808
+box -38 -48 774 592
+use sky130_fd_sc_hd__decap_3 FILLER_5_31
+timestamp 1638025753
+transform 1 0 3956 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_6 FILLER_5_40
+timestamp 1638025753
+transform 1 0 4784 0 1 3808
+box -38 -48 590 592
+use sky130_fd_sc_hd__fill_1 FILLER_5_49
+timestamp 1638025753
+transform 1 0 5612 0 1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_6 FILLER_6_3
+timestamp 1638025753
+transform 1 0 1380 0 -1 4896
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_8 FILLER_6_12
+timestamp 1648946573
+transform 1 0 2208 0 -1 4896
+box -38 -48 774 592
+use sky130_fd_sc_hd__fill_1 FILLER_6_20
+timestamp 1638025753
+transform 1 0 2944 0 -1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1 FILLER_6_24
+timestamp 1638025753
+transform 1 0 3312 0 -1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_3 FILLER_6_28
+timestamp 1638025753
+transform 1 0 3680 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_4 FILLER_6_32
+timestamp 1638025753
+transform 1 0 4048 0 -1 4896
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1 FILLER_6_36
+timestamp 1638025753
+transform 1 0 4416 0 -1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_8 FILLER_6_40
+timestamp 1648946573
+transform 1 0 4784 0 -1 4896
+box -38 -48 774 592
+use sky130_fd_sc_hd__fill_2 FILLER_6_48
+timestamp 1638025753
+transform 1 0 5520 0 -1 4896
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_12 FILLER_7_3
+timestamp 1638025753
+transform 1 0 1380 0 1 4896
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12 FILLER_7_15
+timestamp 1638025753
+transform 1 0 2484 0 1 4896
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_6 FILLER_7_27
+timestamp 1638025753
+transform 1 0 3588 0 1 4896
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_6 FILLER_7_36
+timestamp 1638025753
+transform 1 0 4416 0 1 4896
+box -38 -48 590 592
+use sky130_fd_sc_hd__fill_1 FILLER_7_42
+timestamp 1638025753
+transform 1 0 4968 0 1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_4 FILLER_7_46
+timestamp 1638025753
+transform 1 0 5336 0 1 4896
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_12 FILLER_8_3
+timestamp 1638025753
+transform 1 0 1380 0 -1 5984
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12 FILLER_8_15
+timestamp 1638025753
+transform 1 0 2484 0 -1 5984
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_4 FILLER_8_27
+timestamp 1638025753
+transform 1 0 3588 0 -1 5984
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_12 FILLER_8_32
+timestamp 1638025753
+transform 1 0 4048 0 -1 5984
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_6 FILLER_8_44
+timestamp 1638025753
+transform 1 0 5152 0 -1 5984
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_3 PHY_0
+timestamp 1638025753
+transform 1 0 1104 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_1
+timestamp 1638025753
+transform -1 0 5980 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_2
+timestamp 1638025753
+transform 1 0 1104 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_3
+timestamp 1638025753
+transform -1 0 5980 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_4
+timestamp 1638025753
+transform 1 0 1104 0 -1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_5
+timestamp 1638025753
+transform -1 0 5980 0 -1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_6
+timestamp 1638025753
+transform 1 0 1104 0 1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_7
+timestamp 1638025753
+transform -1 0 5980 0 1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_8
+timestamp 1638025753
+transform 1 0 1104 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_9
+timestamp 1638025753
+transform -1 0 5980 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_10
+timestamp 1638025753
+transform 1 0 1104 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_11
+timestamp 1638025753
+transform -1 0 5980 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_12
+timestamp 1638025753
+transform 1 0 1104 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_13
+timestamp 1638025753
+transform -1 0 5980 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_14
+timestamp 1638025753
+transform 1 0 1104 0 1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_15
+timestamp 1638025753
+transform -1 0 5980 0 1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_16
+timestamp 1638025753
+transform 1 0 1104 0 -1 5984
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_17
+timestamp 1638025753
+transform -1 0 5980 0 -1 5984
+box -38 -48 314 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_18 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 3956 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_19
+timestamp 1638025753
+transform 1 0 3956 0 -1 2720
+box -38 -48 130 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_20
+timestamp 1638025753
+transform 1 0 3956 0 -1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_21
+timestamp 1638025753
+transform 1 0 3956 0 -1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_22
+timestamp 1638025753
+transform 1 0 3956 0 -1 5984
+box -38 -48 130 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[0\] $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1648946573
+transform 1 0 2392 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[1\]
+timestamp 1648946573
+transform 1 0 3036 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[2\]
+timestamp 1648946573
+transform 1 0 1840 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[3\]
+timestamp 1648946573
+transform 1 0 1380 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[4\]
+timestamp 1648946573
+transform 1 0 5428 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[5\]
+timestamp 1648946573
+transform 1 0 4140 0 1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[6\]
+timestamp 1648946573
+transform 1 0 1380 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[7\]
+timestamp 1648946573
+transform 1 0 3864 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[8\]
+timestamp 1648946573
+transform 1 0 3220 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[9\]
+timestamp 1648946573
+transform 1 0 4876 0 -1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[10\]
+timestamp 1648946573
+transform 1 0 4232 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[11\]
+timestamp 1648946573
+transform 1 0 2668 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[12\]
+timestamp 1648946573
+transform 1 0 4508 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[13\]
+timestamp 1648946573
+transform 1 0 4600 0 -1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[14\]
+timestamp 1648946573
+transform 1 0 2484 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[15\]
+timestamp 1648946573
+transform 1 0 4416 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[16\]
+timestamp 1648946573
+transform 1 0 4600 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[17\]
+timestamp 1648946573
+transform 1 0 1472 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[18\]
+timestamp 1648946573
+transform 1 0 4508 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[19\]
+timestamp 1648946573
+transform 1 0 1932 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[20\]
+timestamp 1648946573
+transform 1 0 2760 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[21\]
+timestamp 1648946573
+transform 1 0 3404 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[22\]
+timestamp 1648946573
+transform 1 0 4048 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[23\]
+timestamp 1648946573
+transform 1 0 5060 0 1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[24\]
+timestamp 1648946573
+transform 1 0 1748 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[25\]
+timestamp 1648946573
+transform 1 0 2944 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[26\]
+timestamp 1648946573
+transform 1 0 5060 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[27\]
+timestamp 1648946573
+transform 1 0 1472 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[28\]
+timestamp 1648946573
+transform 1 0 1932 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[29\]
+timestamp 1648946573
+transform 1 0 5336 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[30\]
+timestamp 1648946573
+transform 1 0 3036 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[31\]
+timestamp 1648946573
+transform 1 0 1380 0 1 2720
+box -38 -48 314 592
+<< labels >>
+rlabel metal2 s 4066 6277 4122 7077 4 mask_rev[0]
+port 1 nsew
+rlabel metal2 s 4066 0 4122 800 4 mask_rev[10]
+port 2 nsew
+rlabel metal2 s 1122 0 1178 800 4 mask_rev[11]
+port 3 nsew
+rlabel metal2 s 570 0 626 800 4 mask_rev[12]
+port 4 nsew
+rlabel metal2 s 5354 6277 5410 7077 4 mask_rev[13]
+port 5 nsew
+rlabel metal2 s 5906 0 5962 800 4 mask_rev[14]
+port 6 nsew
+rlabel metal3 s 6309 1640 7109 1760 4 mask_rev[15]
+port 7 nsew
+rlabel metal2 s 2226 0 2282 800 4 mask_rev[16]
+port 8 nsew
+rlabel metal2 s 1674 6277 1730 7077 4 mask_rev[17]
+port 9 nsew
+rlabel metal3 s 0 5176 800 5296 4 mask_rev[18]
+port 10 nsew
+rlabel metal2 s 2962 6277 3018 7077 4 mask_rev[19]
+port 11 nsew
+rlabel metal3 s 0 3272 800 3392 4 mask_rev[1]
+port 12 nsew
+rlabel metal3 s 6309 2456 7109 2576 4 mask_rev[20]
+port 13 nsew
+rlabel metal3 s 6309 824 7109 944 4 mask_rev[21]
+port 14 nsew
+rlabel metal3 s 0 5992 800 6112 4 mask_rev[22]
+port 15 nsew
+rlabel metal2 s 1674 0 1730 800 4 mask_rev[23]
+port 16 nsew
+rlabel metal2 s 5906 6277 5962 7077 4 mask_rev[24]
+port 17 nsew
+rlabel metal3 s 0 1640 800 1760 4 mask_rev[25]
+port 18 nsew
+rlabel metal2 s 4802 6277 4858 7077 4 mask_rev[26]
+port 19 nsew
+rlabel metal2 s 1122 6277 1178 7077 4 mask_rev[27]
+port 20 nsew
+rlabel metal2 s 6458 6277 6514 7077 4 mask_rev[28]
+port 21 nsew
+rlabel metal2 s 5354 0 5410 800 4 mask_rev[29]
+port 22 nsew
+rlabel metal3 s 0 2456 800 2576 4 mask_rev[2]
+port 23 nsew
+rlabel metal3 s 6309 5176 7109 5296 4 mask_rev[30]
+port 24 nsew
+rlabel metal2 s 2962 0 3018 800 4 mask_rev[31]
+port 25 nsew
+rlabel metal2 s 3514 0 3570 800 4 mask_rev[3]
+port 26 nsew
+rlabel metal3 s 6309 3544 7109 3664 4 mask_rev[4]
+port 27 nsew
+rlabel metal3 s 6309 4360 7109 4480 4 mask_rev[5]
+port 28 nsew
+rlabel metal3 s 0 4360 800 4480 4 mask_rev[6]
+port 29 nsew
+rlabel metal2 s 3514 6277 3570 7077 4 mask_rev[7]
+port 30 nsew
+rlabel metal2 s 4802 0 4858 800 4 mask_rev[8]
+port 31 nsew
+rlabel metal2 s 2226 6277 2282 7077 4 mask_rev[9]
+port 32 nsew
+rlabel metal5 s 1104 1696 5980 2016 4 VPWR
+port 33 nsew
+rlabel metal5 s 1104 2512 5980 2832 4 VGND
+port 34 nsew
+<< properties >>
+string FIXED_BBOX 0 0 7109 7077
+<< end >>
diff --git a/tapeout/outputs/mag/user_id_programming.mag b/tapeout/outputs/mag/user_id_programming.mag
new file mode 100644
index 0000000..50f0cec
--- /dev/null
+++ b/tapeout/outputs/mag/user_id_programming.mag
@@ -0,0 +1,3074 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1650371074
+<< nwell >>
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+<< viali >>
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+<< metal4 >>
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+<< via4 >>
+rect 1798 5002 2034 5238
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+rect 2611 4186 2847 4422
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+<< metal5 >>
+rect 1104 5238 5980 5280
+rect 1104 5002 1798 5238
+rect 2034 5002 3424 5238
+rect 3660 5002 5049 5238
+rect 5285 5002 5980 5238
+rect 1104 4960 5980 5002
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+rect 1104 1738 1798 1974
+rect 2034 1738 3424 1974
+rect 3660 1738 5049 1974
+rect 5285 1738 5980 1974
+rect 1104 1696 5980 1738
+use sky130_fd_sc_hd__fill_1 FILLER_0_3 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 1380 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_8 FILLER_0_7 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1648946573
+transform 1 0 1748 0 -1 1632
+box -38 -48 774 592
+use sky130_fd_sc_hd__decap_3 FILLER_0_15 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 2484 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_8 FILLER_0_21
+timestamp 1648946573
+transform 1 0 3036 0 -1 1632
+box -38 -48 774 592
+use sky130_fd_sc_hd__fill_2 FILLER_0_29 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 3772 0 -1 1632
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4 FILLER_0_32 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 4048 0 -1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_8 FILLER_0_39
+timestamp 1648946573
+transform 1 0 4692 0 -1 1632
+box -38 -48 774 592
+use sky130_fd_sc_hd__decap_3 FILLER_0_47
+timestamp 1638025753
+transform 1 0 5428 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 FILLER_1_6
+timestamp 1638025753
+transform 1 0 1656 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2 FILLER_1_12
+timestamp 1638025753
+transform 1 0 2208 0 1 1632
+box -38 -48 222 592
+use sky130_fd_sc_hd__fill_1 FILLER_1_20
+timestamp 1638025753
+transform 1 0 2944 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_6 FILLER_1_24 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 3312 0 1 1632
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_12 FILLER_1_33 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 4140 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__fill_2 FILLER_1_45
+timestamp 1638025753
+transform 1 0 5244 0 1 1632
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_12 FILLER_2_3
+timestamp 1638025753
+transform 1 0 1380 0 -1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12 FILLER_2_15
+timestamp 1638025753
+transform 1 0 2484 0 -1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_4 FILLER_2_27
+timestamp 1638025753
+transform 1 0 3588 0 -1 2720
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_6 FILLER_2_32
+timestamp 1638025753
+transform 1 0 4048 0 -1 2720
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_6 FILLER_2_44
+timestamp 1638025753
+transform 1 0 5152 0 -1 2720
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_12 FILLER_3_6
+timestamp 1638025753
+transform 1 0 1656 0 1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12 FILLER_3_18
+timestamp 1638025753
+transform 1 0 2760 0 1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12 FILLER_3_30
+timestamp 1638025753
+transform 1 0 3864 0 1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_8 FILLER_3_42
+timestamp 1648946573
+transform 1 0 4968 0 1 2720
+box -38 -48 774 592
+use sky130_fd_sc_hd__fill_1 FILLER_4_3
+timestamp 1638025753
+transform 1 0 1380 0 -1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_4 FILLER_4_10
+timestamp 1638025753
+transform 1 0 2024 0 -1 3808
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1 FILLER_4_14
+timestamp 1638025753
+transform 1 0 2392 0 -1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_2 FILLER_4_18
+timestamp 1638025753
+transform 1 0 2760 0 -1 3808
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4 FILLER_4_26
+timestamp 1638025753
+transform 1 0 3496 0 -1 3808
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1 FILLER_4_30
+timestamp 1638025753
+transform 1 0 3864 0 -1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_3 FILLER_4_35
+timestamp 1638025753
+transform 1 0 4324 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2 FILLER_4_41
+timestamp 1638025753
+transform 1 0 4876 0 -1 3808
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4 FILLER_4_46
+timestamp 1638025753
+transform 1 0 5336 0 -1 3808
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_2 FILLER_5_6
+timestamp 1638025753
+transform 1 0 1656 0 1 3808
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_12 FILLER_5_11
+timestamp 1638025753
+transform 1 0 2116 0 1 3808
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_8 FILLER_5_23
+timestamp 1648946573
+transform 1 0 3220 0 1 3808
+box -38 -48 774 592
+use sky130_fd_sc_hd__decap_3 FILLER_5_31
+timestamp 1638025753
+transform 1 0 3956 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_6 FILLER_5_40
+timestamp 1638025753
+transform 1 0 4784 0 1 3808
+box -38 -48 590 592
+use sky130_fd_sc_hd__fill_1 FILLER_5_49
+timestamp 1638025753
+transform 1 0 5612 0 1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_6 FILLER_6_3
+timestamp 1638025753
+transform 1 0 1380 0 -1 4896
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_8 FILLER_6_12
+timestamp 1648946573
+transform 1 0 2208 0 -1 4896
+box -38 -48 774 592
+use sky130_fd_sc_hd__fill_1 FILLER_6_20
+timestamp 1638025753
+transform 1 0 2944 0 -1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1 FILLER_6_24
+timestamp 1638025753
+transform 1 0 3312 0 -1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_3 FILLER_6_28
+timestamp 1638025753
+transform 1 0 3680 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_4 FILLER_6_32
+timestamp 1638025753
+transform 1 0 4048 0 -1 4896
+box -38 -48 406 592
+use sky130_fd_sc_hd__fill_1 FILLER_6_36
+timestamp 1638025753
+transform 1 0 4416 0 -1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_8 FILLER_6_40
+timestamp 1648946573
+transform 1 0 4784 0 -1 4896
+box -38 -48 774 592
+use sky130_fd_sc_hd__fill_2 FILLER_6_48
+timestamp 1638025753
+transform 1 0 5520 0 -1 4896
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_12 FILLER_7_3
+timestamp 1638025753
+transform 1 0 1380 0 1 4896
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12 FILLER_7_15
+timestamp 1638025753
+transform 1 0 2484 0 1 4896
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_6 FILLER_7_27
+timestamp 1638025753
+transform 1 0 3588 0 1 4896
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_6 FILLER_7_36
+timestamp 1638025753
+transform 1 0 4416 0 1 4896
+box -38 -48 590 592
+use sky130_fd_sc_hd__fill_1 FILLER_7_42
+timestamp 1638025753
+transform 1 0 4968 0 1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_4 FILLER_7_46
+timestamp 1638025753
+transform 1 0 5336 0 1 4896
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_12 FILLER_8_3
+timestamp 1638025753
+transform 1 0 1380 0 -1 5984
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12 FILLER_8_15
+timestamp 1638025753
+transform 1 0 2484 0 -1 5984
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_4 FILLER_8_27
+timestamp 1638025753
+transform 1 0 3588 0 -1 5984
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_12 FILLER_8_32
+timestamp 1638025753
+transform 1 0 4048 0 -1 5984
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_6 FILLER_8_44
+timestamp 1638025753
+transform 1 0 5152 0 -1 5984
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_3 PHY_0
+timestamp 1638025753
+transform 1 0 1104 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_1
+timestamp 1638025753
+transform -1 0 5980 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_2
+timestamp 1638025753
+transform 1 0 1104 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_3
+timestamp 1638025753
+transform -1 0 5980 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_4
+timestamp 1638025753
+transform 1 0 1104 0 -1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_5
+timestamp 1638025753
+transform -1 0 5980 0 -1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_6
+timestamp 1638025753
+transform 1 0 1104 0 1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_7
+timestamp 1638025753
+transform -1 0 5980 0 1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_8
+timestamp 1638025753
+transform 1 0 1104 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_9
+timestamp 1638025753
+transform -1 0 5980 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_10
+timestamp 1638025753
+transform 1 0 1104 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_11
+timestamp 1638025753
+transform -1 0 5980 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_12
+timestamp 1638025753
+transform 1 0 1104 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_13
+timestamp 1638025753
+transform -1 0 5980 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_14
+timestamp 1638025753
+transform 1 0 1104 0 1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_15
+timestamp 1638025753
+transform -1 0 5980 0 1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_16
+timestamp 1638025753
+transform 1 0 1104 0 -1 5984
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_17
+timestamp 1638025753
+transform -1 0 5980 0 -1 5984
+box -38 -48 314 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_18 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1638025753
+transform 1 0 3956 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_19
+timestamp 1638025753
+transform 1 0 3956 0 -1 2720
+box -38 -48 130 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_20
+timestamp 1638025753
+transform 1 0 3956 0 -1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_21
+timestamp 1638025753
+transform 1 0 3956 0 -1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_22
+timestamp 1638025753
+transform 1 0 3956 0 -1 5984
+box -38 -48 130 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[0\] $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1648946573
+transform 1 0 2392 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[1\]
+timestamp 1648946573
+transform 1 0 3036 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[2\]
+timestamp 1648946573
+transform 1 0 1840 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[3\]
+timestamp 1648946573
+transform 1 0 1380 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[4\]
+timestamp 1648946573
+transform 1 0 5428 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[5\]
+timestamp 1648946573
+transform 1 0 4140 0 1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[6\]
+timestamp 1648946573
+transform 1 0 1380 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[7\]
+timestamp 1648946573
+transform 1 0 3864 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[8\]
+timestamp 1648946573
+transform 1 0 3220 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[9\]
+timestamp 1648946573
+transform 1 0 4876 0 -1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[10\]
+timestamp 1648946573
+transform 1 0 4232 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[11\]
+timestamp 1648946573
+transform 1 0 2668 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[12\]
+timestamp 1648946573
+transform 1 0 4508 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[13\]
+timestamp 1648946573
+transform 1 0 4600 0 -1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[14\]
+timestamp 1648946573
+transform 1 0 2484 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[15\]
+timestamp 1648946573
+transform 1 0 4416 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[16\]
+timestamp 1648946573
+transform 1 0 4600 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[17\]
+timestamp 1648946573
+transform 1 0 1472 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[18\]
+timestamp 1648946573
+transform 1 0 4508 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[19\]
+timestamp 1648946573
+transform 1 0 1932 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[20\]
+timestamp 1648946573
+transform 1 0 2760 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[21\]
+timestamp 1648946573
+transform 1 0 3404 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[22\]
+timestamp 1648946573
+transform 1 0 4048 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[23\]
+timestamp 1648946573
+transform 1 0 5060 0 1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[24\]
+timestamp 1648946573
+transform 1 0 1748 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[25\]
+timestamp 1648946573
+transform 1 0 2944 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[26\]
+timestamp 1648946573
+transform 1 0 5060 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[27\]
+timestamp 1648946573
+transform 1 0 1472 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[28\]
+timestamp 1648946573
+transform 1 0 1932 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[29\]
+timestamp 1648946573
+transform 1 0 5336 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[30\]
+timestamp 1648946573
+transform 1 0 3036 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[31\]
+timestamp 1648946573
+transform 1 0 1380 0 1 2720
+box -38 -48 314 592
+<< labels >>
+rlabel metal2 s 4066 6277 4122 7077 4 mask_rev[0]
+port 1 nsew
+rlabel metal2 s 4066 0 4122 800 4 mask_rev[10]
+port 2 nsew
+rlabel metal2 s 1122 0 1178 800 4 mask_rev[11]
+port 3 nsew
+rlabel metal2 s 570 0 626 800 4 mask_rev[12]
+port 4 nsew
+rlabel metal2 s 5354 6277 5410 7077 4 mask_rev[13]
+port 5 nsew
+rlabel metal2 s 5906 0 5962 800 4 mask_rev[14]
+port 6 nsew
+rlabel metal3 s 6309 1640 7109 1760 4 mask_rev[15]
+port 7 nsew
+rlabel metal2 s 2226 0 2282 800 4 mask_rev[16]
+port 8 nsew
+rlabel metal2 s 1674 6277 1730 7077 4 mask_rev[17]
+port 9 nsew
+rlabel metal3 s 0 5176 800 5296 4 mask_rev[18]
+port 10 nsew
+rlabel metal2 s 2962 6277 3018 7077 4 mask_rev[19]
+port 11 nsew
+rlabel metal3 s 0 3272 800 3392 4 mask_rev[1]
+port 12 nsew
+rlabel metal3 s 6309 2456 7109 2576 4 mask_rev[20]
+port 13 nsew
+rlabel metal3 s 6309 824 7109 944 4 mask_rev[21]
+port 14 nsew
+rlabel metal3 s 0 5992 800 6112 4 mask_rev[22]
+port 15 nsew
+rlabel metal2 s 1674 0 1730 800 4 mask_rev[23]
+port 16 nsew
+rlabel metal2 s 5906 6277 5962 7077 4 mask_rev[24]
+port 17 nsew
+rlabel metal3 s 0 1640 800 1760 4 mask_rev[25]
+port 18 nsew
+rlabel metal2 s 4802 6277 4858 7077 4 mask_rev[26]
+port 19 nsew
+rlabel metal2 s 1122 6277 1178 7077 4 mask_rev[27]
+port 20 nsew
+rlabel metal2 s 6458 6277 6514 7077 4 mask_rev[28]
+port 21 nsew
+rlabel metal2 s 5354 0 5410 800 4 mask_rev[29]
+port 22 nsew
+rlabel metal3 s 0 2456 800 2576 4 mask_rev[2]
+port 23 nsew
+rlabel metal3 s 6309 5176 7109 5296 4 mask_rev[30]
+port 24 nsew
+rlabel metal2 s 2962 0 3018 800 4 mask_rev[31]
+port 25 nsew
+rlabel metal2 s 3514 0 3570 800 4 mask_rev[3]
+port 26 nsew
+rlabel metal3 s 6309 3544 7109 3664 4 mask_rev[4]
+port 27 nsew
+rlabel metal3 s 6309 4360 7109 4480 4 mask_rev[5]
+port 28 nsew
+rlabel metal3 s 0 4360 800 4480 4 mask_rev[6]
+port 29 nsew
+rlabel metal2 s 3514 6277 3570 7077 4 mask_rev[7]
+port 30 nsew
+rlabel metal2 s 4802 0 4858 800 4 mask_rev[8]
+port 31 nsew
+rlabel metal2 s 2226 6277 2282 7077 4 mask_rev[9]
+port 32 nsew
+rlabel metal5 s 1104 1696 5980 2016 4 VPWR
+port 33 nsew
+rlabel metal5 s 1104 2512 5980 2832 4 VGND
+port 34 nsew
+<< properties >>
+string FIXED_BBOX 0 0 7109 7077
+<< end >>
diff --git a/tapeout/outputs/mag/user_id_textblock.mag b/tapeout/outputs/mag/user_id_textblock.mag
new file mode 100644
index 0000000..ac955b7
--- /dev/null
+++ b/tapeout/outputs/mag/user_id_textblock.mag
@@ -0,0 +1,43 @@
+magic
+tech sky130A
+timestamp 1608324878
+<< checkpaint >>
+rect 1495 5490 6500 6570
+rect -630 428 19262 5490
+rect -630 -630 6210 428
+rect 16092 356 18972 428
+<< fillblock >>
+rect -328 754 16860 5172
+use alpha_3 alphaX_0 hexdigits
+timestamp 1598786981
+transform 1 0 14887 0 1 1080
+box 0 0 1620 3780
+use alpha_1 alphaX_1 hexdigits
+timestamp 1598786981
+transform 1 0 12750 0 1 1080
+box 0 0 1620 3780
+use alpha_F alphaX_2 hexdigits
+timestamp 1598786981
+transform 1 0 10625 0 1 1080
+box 0 0 1620 3780
+use alpha_9 alphaX_3 hexdigits
+timestamp 1598786981
+transform 1 0 8500 0 1 1080
+box 0 0 1620 3780
+use alpha_6 alphaX_4 hexdigits
+timestamp 1598786981
+transform 1 0 6375 0 1 1080
+box 0 0 1620 3780
+use alpha_0 alphaX_5 hexdigits
+timestamp 1598786981
+transform 1 0 4250 0 1 1080
+box 0 0 1620 3780
+use alpha_0 alphaX_6
+timestamp 1598786981
+transform 1 0 2125 0 1 1080
+box 0 0 1620 3780
+use alpha_0 alphaX_7
+timestamp 1598786981
+transform 1 0 0 0 1 1080
+box 0 0 1620 3780
+<< end >>
diff --git a/tapeout/outputs/oas/caravel_00069f13.oas b/tapeout/outputs/oas/caravel_00069f13.oas
new file mode 100644
index 0000000..799b3a0
--- /dev/null
+++ b/tapeout/outputs/oas/caravel_00069f13.oas
Binary files differ
diff --git a/tapeout/outputs/verilog/gl/caravel.v b/tapeout/outputs/verilog/gl/caravel.v
new file mode 100644
index 0000000..d6f5e90
--- /dev/null
+++ b/tapeout/outputs/verilog/gl/caravel.v
@@ -0,0 +1,5435 @@
+/* Generated by Yosys 0.9+4052 (git sha1 d061b0e, gcc 8.3.1 -fPIC -Os) */
+
+module caravel(vddio, vddio_2, vssio, vssio_2, vdda, vssa, vccd, vssd, vdda1, vdda1_2, vdda2, vssa1, vssa1_2, vssa2, vccd1, vccd2, vssd1, vssd2, gpio, mprj_io, clock, resetb, flash_csb, flash_clk, flash_io0, flash_io1);
+ wire caravel_clk;
+ wire caravel_clk2;
+ wire caravel_clk_buf;
+ wire caravel_rstn;
+ wire caravel_rstn_buf;
+ wire clk_passthru;
+ input clock;
+ wire clock_core;
+ wire clock_core_buf;
+ wire debug_in;
+ wire debug_mode;
+ wire debug_oeb;
+ wire debug_out;
+ wire ext_clk_sel;
+ wire ext_reset;
+ output flash_clk;
+ wire flash_clk_core;
+ wire flash_clk_frame;
+ wire flash_clk_frame_buf;
+ wire flash_clk_ieb;
+ wire flash_clk_ieb_buf;
+ wire flash_clk_oeb;
+ wire flash_clk_oeb_buf;
+ wire flash_clk_oeb_core;
+ output flash_csb;
+ wire flash_csb_core;
+ wire flash_csb_frame;
+ wire flash_csb_frame_buf;
+ wire flash_csb_ieb;
+ wire flash_csb_ieb_buf;
+ wire flash_csb_oeb;
+ wire flash_csb_oeb_buf;
+ wire flash_csb_oeb_core;
+ output flash_io0;
+ wire flash_io0_di;
+ wire flash_io0_di_buf;
+ wire flash_io0_di_core;
+ wire flash_io0_do;
+ wire flash_io0_do_buf;
+ wire flash_io0_do_core;
+ wire flash_io0_ieb;
+ wire flash_io0_ieb_buf;
+ wire flash_io0_ieb_core;
+ wire flash_io0_oeb;
+ wire flash_io0_oeb_buf;
+ wire flash_io0_oeb_core;
+ output flash_io1;
+ wire flash_io1_di;
+ wire flash_io1_di_buf;
+ wire flash_io1_di_core;
+ wire flash_io1_do;
+ wire flash_io1_do_buf;
+ wire flash_io1_do_core;
+ wire flash_io1_ieb;
+ wire flash_io1_ieb_buf;
+ wire flash_io1_ieb_core;
+ wire flash_io1_oeb;
+ wire flash_io1_oeb_buf;
+ wire flash_io1_oeb_core;
+ wire flash_io2_di_core;
+ wire flash_io2_do_core;
+ wire flash_io2_ieb_core;
+ wire flash_io2_oeb_core;
+ wire flash_io3_di_core;
+ wire flash_io3_do_core;
+ wire flash_io3_ieb_core;
+ wire flash_io3_oeb_core;
+ inout gpio;
+ wire \gpio_clock_1[0] ;
+ wire \gpio_clock_1[10] ;
+ wire \gpio_clock_1[11] ;
+ wire \gpio_clock_1[12] ;
+ wire \gpio_clock_1[13] ;
+ wire \gpio_clock_1[14] ;
+ wire \gpio_clock_1[15] ;
+ wire \gpio_clock_1[16] ;
+ wire \gpio_clock_1[17] ;
+ wire \gpio_clock_1[18] ;
+ wire \gpio_clock_1[1] ;
+ wire \gpio_clock_1[2] ;
+ wire \gpio_clock_1[3] ;
+ wire \gpio_clock_1[4] ;
+ wire \gpio_clock_1[5] ;
+ wire \gpio_clock_1[6] ;
+ wire \gpio_clock_1[7] ;
+ wire \gpio_clock_1[8] ;
+ wire \gpio_clock_1[9] ;
+ wire \gpio_clock_1_shifted[0] ;
+ wire \gpio_clock_1_shifted[10] ;
+ wire \gpio_clock_1_shifted[11] ;
+ wire \gpio_clock_1_shifted[12] ;
+ wire \gpio_clock_1_shifted[13] ;
+ wire \gpio_clock_1_shifted[14] ;
+ wire \gpio_clock_1_shifted[15] ;
+ wire \gpio_clock_1_shifted[16] ;
+ wire \gpio_clock_1_shifted[17] ;
+ wire \gpio_clock_1_shifted[18] ;
+ wire \gpio_clock_1_shifted[1] ;
+ wire \gpio_clock_1_shifted[2] ;
+ wire \gpio_clock_1_shifted[3] ;
+ wire \gpio_clock_1_shifted[4] ;
+ wire \gpio_clock_1_shifted[5] ;
+ wire \gpio_clock_1_shifted[6] ;
+ wire \gpio_clock_1_shifted[7] ;
+ wire \gpio_clock_1_shifted[8] ;
+ wire \gpio_clock_1_shifted[9] ;
+ wire \gpio_clock_2[0] ;
+ wire \gpio_clock_2[10] ;
+ wire \gpio_clock_2[11] ;
+ wire \gpio_clock_2[12] ;
+ wire \gpio_clock_2[13] ;
+ wire \gpio_clock_2[14] ;
+ wire \gpio_clock_2[15] ;
+ wire \gpio_clock_2[16] ;
+ wire \gpio_clock_2[17] ;
+ wire \gpio_clock_2[18] ;
+ wire \gpio_clock_2[1] ;
+ wire \gpio_clock_2[2] ;
+ wire \gpio_clock_2[3] ;
+ wire \gpio_clock_2[4] ;
+ wire \gpio_clock_2[5] ;
+ wire \gpio_clock_2[6] ;
+ wire \gpio_clock_2[7] ;
+ wire \gpio_clock_2[8] ;
+ wire \gpio_clock_2[9] ;
+ wire \gpio_clock_2_shifted[0] ;
+ wire \gpio_clock_2_shifted[10] ;
+ wire \gpio_clock_2_shifted[11] ;
+ wire \gpio_clock_2_shifted[12] ;
+ wire \gpio_clock_2_shifted[13] ;
+ wire \gpio_clock_2_shifted[14] ;
+ wire \gpio_clock_2_shifted[15] ;
+ wire \gpio_clock_2_shifted[16] ;
+ wire \gpio_clock_2_shifted[17] ;
+ wire \gpio_clock_2_shifted[18] ;
+ wire \gpio_clock_2_shifted[1] ;
+ wire \gpio_clock_2_shifted[2] ;
+ wire \gpio_clock_2_shifted[3] ;
+ wire \gpio_clock_2_shifted[4] ;
+ wire \gpio_clock_2_shifted[5] ;
+ wire \gpio_clock_2_shifted[6] ;
+ wire \gpio_clock_2_shifted[7] ;
+ wire \gpio_clock_2_shifted[8] ;
+ wire \gpio_clock_2_shifted[9] ;
+ wire \gpio_defaults[0] ;
+ wire \gpio_defaults[100] ;
+ wire \gpio_defaults[101] ;
+ wire \gpio_defaults[102] ;
+ wire \gpio_defaults[103] ;
+ wire \gpio_defaults[104] ;
+ wire \gpio_defaults[105] ;
+ wire \gpio_defaults[106] ;
+ wire \gpio_defaults[107] ;
+ wire \gpio_defaults[108] ;
+ wire \gpio_defaults[109] ;
+ wire \gpio_defaults[10] ;
+ wire \gpio_defaults[110] ;
+ wire \gpio_defaults[111] ;
+ wire \gpio_defaults[112] ;
+ wire \gpio_defaults[113] ;
+ wire \gpio_defaults[114] ;
+ wire \gpio_defaults[115] ;
+ wire \gpio_defaults[116] ;
+ wire \gpio_defaults[117] ;
+ wire \gpio_defaults[118] ;
+ wire \gpio_defaults[119] ;
+ wire \gpio_defaults[11] ;
+ wire \gpio_defaults[120] ;
+ wire \gpio_defaults[121] ;
+ wire \gpio_defaults[122] ;
+ wire \gpio_defaults[123] ;
+ wire \gpio_defaults[124] ;
+ wire \gpio_defaults[125] ;
+ wire \gpio_defaults[126] ;
+ wire \gpio_defaults[127] ;
+ wire \gpio_defaults[128] ;
+ wire \gpio_defaults[129] ;
+ wire \gpio_defaults[12] ;
+ wire \gpio_defaults[130] ;
+ wire \gpio_defaults[131] ;
+ wire \gpio_defaults[132] ;
+ wire \gpio_defaults[133] ;
+ wire \gpio_defaults[134] ;
+ wire \gpio_defaults[135] ;
+ wire \gpio_defaults[136] ;
+ wire \gpio_defaults[137] ;
+ wire \gpio_defaults[138] ;
+ wire \gpio_defaults[139] ;
+ wire \gpio_defaults[13] ;
+ wire \gpio_defaults[140] ;
+ wire \gpio_defaults[141] ;
+ wire \gpio_defaults[142] ;
+ wire \gpio_defaults[143] ;
+ wire \gpio_defaults[144] ;
+ wire \gpio_defaults[145] ;
+ wire \gpio_defaults[146] ;
+ wire \gpio_defaults[147] ;
+ wire \gpio_defaults[148] ;
+ wire \gpio_defaults[149] ;
+ wire \gpio_defaults[14] ;
+ wire \gpio_defaults[150] ;
+ wire \gpio_defaults[151] ;
+ wire \gpio_defaults[152] ;
+ wire \gpio_defaults[153] ;
+ wire \gpio_defaults[154] ;
+ wire \gpio_defaults[155] ;
+ wire \gpio_defaults[156] ;
+ wire \gpio_defaults[157] ;
+ wire \gpio_defaults[158] ;
+ wire \gpio_defaults[159] ;
+ wire \gpio_defaults[15] ;
+ wire \gpio_defaults[160] ;
+ wire \gpio_defaults[161] ;
+ wire \gpio_defaults[162] ;
+ wire \gpio_defaults[163] ;
+ wire \gpio_defaults[164] ;
+ wire \gpio_defaults[165] ;
+ wire \gpio_defaults[166] ;
+ wire \gpio_defaults[167] ;
+ wire \gpio_defaults[168] ;
+ wire \gpio_defaults[169] ;
+ wire \gpio_defaults[16] ;
+ wire \gpio_defaults[170] ;
+ wire \gpio_defaults[171] ;
+ wire \gpio_defaults[172] ;
+ wire \gpio_defaults[173] ;
+ wire \gpio_defaults[174] ;
+ wire \gpio_defaults[175] ;
+ wire \gpio_defaults[176] ;
+ wire \gpio_defaults[177] ;
+ wire \gpio_defaults[178] ;
+ wire \gpio_defaults[179] ;
+ wire \gpio_defaults[17] ;
+ wire \gpio_defaults[180] ;
+ wire \gpio_defaults[181] ;
+ wire \gpio_defaults[182] ;
+ wire \gpio_defaults[183] ;
+ wire \gpio_defaults[184] ;
+ wire \gpio_defaults[185] ;
+ wire \gpio_defaults[186] ;
+ wire \gpio_defaults[187] ;
+ wire \gpio_defaults[188] ;
+ wire \gpio_defaults[189] ;
+ wire \gpio_defaults[18] ;
+ wire \gpio_defaults[190] ;
+ wire \gpio_defaults[191] ;
+ wire \gpio_defaults[192] ;
+ wire \gpio_defaults[193] ;
+ wire \gpio_defaults[194] ;
+ wire \gpio_defaults[195] ;
+ wire \gpio_defaults[196] ;
+ wire \gpio_defaults[197] ;
+ wire \gpio_defaults[198] ;
+ wire \gpio_defaults[199] ;
+ wire \gpio_defaults[19] ;
+ wire \gpio_defaults[1] ;
+ wire \gpio_defaults[200] ;
+ wire \gpio_defaults[201] ;
+ wire \gpio_defaults[202] ;
+ wire \gpio_defaults[203] ;
+ wire \gpio_defaults[204] ;
+ wire \gpio_defaults[205] ;
+ wire \gpio_defaults[206] ;
+ wire \gpio_defaults[207] ;
+ wire \gpio_defaults[208] ;
+ wire \gpio_defaults[209] ;
+ wire \gpio_defaults[20] ;
+ wire \gpio_defaults[210] ;
+ wire \gpio_defaults[211] ;
+ wire \gpio_defaults[212] ;
+ wire \gpio_defaults[213] ;
+ wire \gpio_defaults[214] ;
+ wire \gpio_defaults[215] ;
+ wire \gpio_defaults[216] ;
+ wire \gpio_defaults[217] ;
+ wire \gpio_defaults[218] ;
+ wire \gpio_defaults[219] ;
+ wire \gpio_defaults[21] ;
+ wire \gpio_defaults[220] ;
+ wire \gpio_defaults[221] ;
+ wire \gpio_defaults[222] ;
+ wire \gpio_defaults[223] ;
+ wire \gpio_defaults[224] ;
+ wire \gpio_defaults[225] ;
+ wire \gpio_defaults[226] ;
+ wire \gpio_defaults[227] ;
+ wire \gpio_defaults[228] ;
+ wire \gpio_defaults[229] ;
+ wire \gpio_defaults[22] ;
+ wire \gpio_defaults[230] ;
+ wire \gpio_defaults[231] ;
+ wire \gpio_defaults[232] ;
+ wire \gpio_defaults[233] ;
+ wire \gpio_defaults[234] ;
+ wire \gpio_defaults[235] ;
+ wire \gpio_defaults[236] ;
+ wire \gpio_defaults[237] ;
+ wire \gpio_defaults[238] ;
+ wire \gpio_defaults[239] ;
+ wire \gpio_defaults[23] ;
+ wire \gpio_defaults[240] ;
+ wire \gpio_defaults[241] ;
+ wire \gpio_defaults[242] ;
+ wire \gpio_defaults[243] ;
+ wire \gpio_defaults[244] ;
+ wire \gpio_defaults[245] ;
+ wire \gpio_defaults[246] ;
+ wire \gpio_defaults[247] ;
+ wire \gpio_defaults[248] ;
+ wire \gpio_defaults[249] ;
+ wire \gpio_defaults[24] ;
+ wire \gpio_defaults[250] ;
+ wire \gpio_defaults[251] ;
+ wire \gpio_defaults[252] ;
+ wire \gpio_defaults[253] ;
+ wire \gpio_defaults[254] ;
+ wire \gpio_defaults[255] ;
+ wire \gpio_defaults[256] ;
+ wire \gpio_defaults[257] ;
+ wire \gpio_defaults[258] ;
+ wire \gpio_defaults[259] ;
+ wire \gpio_defaults[25] ;
+ wire \gpio_defaults[260] ;
+ wire \gpio_defaults[261] ;
+ wire \gpio_defaults[262] ;
+ wire \gpio_defaults[263] ;
+ wire \gpio_defaults[264] ;
+ wire \gpio_defaults[265] ;
+ wire \gpio_defaults[266] ;
+ wire \gpio_defaults[267] ;
+ wire \gpio_defaults[268] ;
+ wire \gpio_defaults[269] ;
+ wire \gpio_defaults[26] ;
+ wire \gpio_defaults[270] ;
+ wire \gpio_defaults[271] ;
+ wire \gpio_defaults[272] ;
+ wire \gpio_defaults[273] ;
+ wire \gpio_defaults[274] ;
+ wire \gpio_defaults[275] ;
+ wire \gpio_defaults[276] ;
+ wire \gpio_defaults[277] ;
+ wire \gpio_defaults[278] ;
+ wire \gpio_defaults[279] ;
+ wire \gpio_defaults[27] ;
+ wire \gpio_defaults[280] ;
+ wire \gpio_defaults[281] ;
+ wire \gpio_defaults[282] ;
+ wire \gpio_defaults[283] ;
+ wire \gpio_defaults[284] ;
+ wire \gpio_defaults[285] ;
+ wire \gpio_defaults[286] ;
+ wire \gpio_defaults[287] ;
+ wire \gpio_defaults[288] ;
+ wire \gpio_defaults[289] ;
+ wire \gpio_defaults[28] ;
+ wire \gpio_defaults[290] ;
+ wire \gpio_defaults[291] ;
+ wire \gpio_defaults[292] ;
+ wire \gpio_defaults[293] ;
+ wire \gpio_defaults[294] ;
+ wire \gpio_defaults[295] ;
+ wire \gpio_defaults[296] ;
+ wire \gpio_defaults[297] ;
+ wire \gpio_defaults[298] ;
+ wire \gpio_defaults[299] ;
+ wire \gpio_defaults[29] ;
+ wire \gpio_defaults[2] ;
+ wire \gpio_defaults[300] ;
+ wire \gpio_defaults[301] ;
+ wire \gpio_defaults[302] ;
+ wire \gpio_defaults[303] ;
+ wire \gpio_defaults[304] ;
+ wire \gpio_defaults[305] ;
+ wire \gpio_defaults[306] ;
+ wire \gpio_defaults[307] ;
+ wire \gpio_defaults[308] ;
+ wire \gpio_defaults[309] ;
+ wire \gpio_defaults[30] ;
+ wire \gpio_defaults[310] ;
+ wire \gpio_defaults[311] ;
+ wire \gpio_defaults[312] ;
+ wire \gpio_defaults[313] ;
+ wire \gpio_defaults[314] ;
+ wire \gpio_defaults[315] ;
+ wire \gpio_defaults[316] ;
+ wire \gpio_defaults[317] ;
+ wire \gpio_defaults[318] ;
+ wire \gpio_defaults[319] ;
+ wire \gpio_defaults[31] ;
+ wire \gpio_defaults[320] ;
+ wire \gpio_defaults[321] ;
+ wire \gpio_defaults[322] ;
+ wire \gpio_defaults[323] ;
+ wire \gpio_defaults[324] ;
+ wire \gpio_defaults[325] ;
+ wire \gpio_defaults[326] ;
+ wire \gpio_defaults[327] ;
+ wire \gpio_defaults[328] ;
+ wire \gpio_defaults[329] ;
+ wire \gpio_defaults[32] ;
+ wire \gpio_defaults[330] ;
+ wire \gpio_defaults[331] ;
+ wire \gpio_defaults[332] ;
+ wire \gpio_defaults[333] ;
+ wire \gpio_defaults[334] ;
+ wire \gpio_defaults[335] ;
+ wire \gpio_defaults[336] ;
+ wire \gpio_defaults[337] ;
+ wire \gpio_defaults[338] ;
+ wire \gpio_defaults[339] ;
+ wire \gpio_defaults[33] ;
+ wire \gpio_defaults[340] ;
+ wire \gpio_defaults[341] ;
+ wire \gpio_defaults[342] ;
+ wire \gpio_defaults[343] ;
+ wire \gpio_defaults[344] ;
+ wire \gpio_defaults[345] ;
+ wire \gpio_defaults[346] ;
+ wire \gpio_defaults[347] ;
+ wire \gpio_defaults[348] ;
+ wire \gpio_defaults[349] ;
+ wire \gpio_defaults[34] ;
+ wire \gpio_defaults[350] ;
+ wire \gpio_defaults[351] ;
+ wire \gpio_defaults[352] ;
+ wire \gpio_defaults[353] ;
+ wire \gpio_defaults[354] ;
+ wire \gpio_defaults[355] ;
+ wire \gpio_defaults[356] ;
+ wire \gpio_defaults[357] ;
+ wire \gpio_defaults[358] ;
+ wire \gpio_defaults[359] ;
+ wire \gpio_defaults[35] ;
+ wire \gpio_defaults[360] ;
+ wire \gpio_defaults[361] ;
+ wire \gpio_defaults[362] ;
+ wire \gpio_defaults[363] ;
+ wire \gpio_defaults[364] ;
+ wire \gpio_defaults[365] ;
+ wire \gpio_defaults[366] ;
+ wire \gpio_defaults[367] ;
+ wire \gpio_defaults[368] ;
+ wire \gpio_defaults[369] ;
+ wire \gpio_defaults[36] ;
+ wire \gpio_defaults[370] ;
+ wire \gpio_defaults[371] ;
+ wire \gpio_defaults[372] ;
+ wire \gpio_defaults[373] ;
+ wire \gpio_defaults[374] ;
+ wire \gpio_defaults[375] ;
+ wire \gpio_defaults[376] ;
+ wire \gpio_defaults[377] ;
+ wire \gpio_defaults[378] ;
+ wire \gpio_defaults[379] ;
+ wire \gpio_defaults[37] ;
+ wire \gpio_defaults[380] ;
+ wire \gpio_defaults[381] ;
+ wire \gpio_defaults[382] ;
+ wire \gpio_defaults[383] ;
+ wire \gpio_defaults[384] ;
+ wire \gpio_defaults[385] ;
+ wire \gpio_defaults[386] ;
+ wire \gpio_defaults[387] ;
+ wire \gpio_defaults[388] ;
+ wire \gpio_defaults[389] ;
+ wire \gpio_defaults[38] ;
+ wire \gpio_defaults[390] ;
+ wire \gpio_defaults[391] ;
+ wire \gpio_defaults[392] ;
+ wire \gpio_defaults[393] ;
+ wire \gpio_defaults[394] ;
+ wire \gpio_defaults[395] ;
+ wire \gpio_defaults[396] ;
+ wire \gpio_defaults[397] ;
+ wire \gpio_defaults[398] ;
+ wire \gpio_defaults[399] ;
+ wire \gpio_defaults[39] ;
+ wire \gpio_defaults[3] ;
+ wire \gpio_defaults[400] ;
+ wire \gpio_defaults[401] ;
+ wire \gpio_defaults[402] ;
+ wire \gpio_defaults[403] ;
+ wire \gpio_defaults[404] ;
+ wire \gpio_defaults[405] ;
+ wire \gpio_defaults[406] ;
+ wire \gpio_defaults[407] ;
+ wire \gpio_defaults[408] ;
+ wire \gpio_defaults[409] ;
+ wire \gpio_defaults[40] ;
+ wire \gpio_defaults[410] ;
+ wire \gpio_defaults[411] ;
+ wire \gpio_defaults[412] ;
+ wire \gpio_defaults[413] ;
+ wire \gpio_defaults[414] ;
+ wire \gpio_defaults[415] ;
+ wire \gpio_defaults[416] ;
+ wire \gpio_defaults[417] ;
+ wire \gpio_defaults[418] ;
+ wire \gpio_defaults[419] ;
+ wire \gpio_defaults[41] ;
+ wire \gpio_defaults[420] ;
+ wire \gpio_defaults[421] ;
+ wire \gpio_defaults[422] ;
+ wire \gpio_defaults[423] ;
+ wire \gpio_defaults[424] ;
+ wire \gpio_defaults[425] ;
+ wire \gpio_defaults[426] ;
+ wire \gpio_defaults[427] ;
+ wire \gpio_defaults[428] ;
+ wire \gpio_defaults[429] ;
+ wire \gpio_defaults[42] ;
+ wire \gpio_defaults[430] ;
+ wire \gpio_defaults[431] ;
+ wire \gpio_defaults[432] ;
+ wire \gpio_defaults[433] ;
+ wire \gpio_defaults[434] ;
+ wire \gpio_defaults[435] ;
+ wire \gpio_defaults[436] ;
+ wire \gpio_defaults[437] ;
+ wire \gpio_defaults[438] ;
+ wire \gpio_defaults[439] ;
+ wire \gpio_defaults[43] ;
+ wire \gpio_defaults[440] ;
+ wire \gpio_defaults[441] ;
+ wire \gpio_defaults[442] ;
+ wire \gpio_defaults[443] ;
+ wire \gpio_defaults[444] ;
+ wire \gpio_defaults[445] ;
+ wire \gpio_defaults[446] ;
+ wire \gpio_defaults[447] ;
+ wire \gpio_defaults[448] ;
+ wire \gpio_defaults[449] ;
+ wire \gpio_defaults[44] ;
+ wire \gpio_defaults[450] ;
+ wire \gpio_defaults[451] ;
+ wire \gpio_defaults[452] ;
+ wire \gpio_defaults[453] ;
+ wire \gpio_defaults[454] ;
+ wire \gpio_defaults[455] ;
+ wire \gpio_defaults[456] ;
+ wire \gpio_defaults[457] ;
+ wire \gpio_defaults[458] ;
+ wire \gpio_defaults[459] ;
+ wire \gpio_defaults[45] ;
+ wire \gpio_defaults[460] ;
+ wire \gpio_defaults[461] ;
+ wire \gpio_defaults[462] ;
+ wire \gpio_defaults[463] ;
+ wire \gpio_defaults[464] ;
+ wire \gpio_defaults[465] ;
+ wire \gpio_defaults[466] ;
+ wire \gpio_defaults[467] ;
+ wire \gpio_defaults[468] ;
+ wire \gpio_defaults[469] ;
+ wire \gpio_defaults[46] ;
+ wire \gpio_defaults[470] ;
+ wire \gpio_defaults[471] ;
+ wire \gpio_defaults[472] ;
+ wire \gpio_defaults[473] ;
+ wire \gpio_defaults[474] ;
+ wire \gpio_defaults[475] ;
+ wire \gpio_defaults[476] ;
+ wire \gpio_defaults[477] ;
+ wire \gpio_defaults[478] ;
+ wire \gpio_defaults[479] ;
+ wire \gpio_defaults[47] ;
+ wire \gpio_defaults[480] ;
+ wire \gpio_defaults[481] ;
+ wire \gpio_defaults[482] ;
+ wire \gpio_defaults[483] ;
+ wire \gpio_defaults[484] ;
+ wire \gpio_defaults[485] ;
+ wire \gpio_defaults[486] ;
+ wire \gpio_defaults[487] ;
+ wire \gpio_defaults[488] ;
+ wire \gpio_defaults[489] ;
+ wire \gpio_defaults[48] ;
+ wire \gpio_defaults[490] ;
+ wire \gpio_defaults[491] ;
+ wire \gpio_defaults[492] ;
+ wire \gpio_defaults[493] ;
+ wire \gpio_defaults[49] ;
+ wire \gpio_defaults[4] ;
+ wire \gpio_defaults[50] ;
+ wire \gpio_defaults[51] ;
+ wire \gpio_defaults[52] ;
+ wire \gpio_defaults[53] ;
+ wire \gpio_defaults[54] ;
+ wire \gpio_defaults[55] ;
+ wire \gpio_defaults[56] ;
+ wire \gpio_defaults[57] ;
+ wire \gpio_defaults[58] ;
+ wire \gpio_defaults[59] ;
+ wire \gpio_defaults[5] ;
+ wire \gpio_defaults[60] ;
+ wire \gpio_defaults[61] ;
+ wire \gpio_defaults[62] ;
+ wire \gpio_defaults[63] ;
+ wire \gpio_defaults[64] ;
+ wire \gpio_defaults[65] ;
+ wire \gpio_defaults[66] ;
+ wire \gpio_defaults[67] ;
+ wire \gpio_defaults[68] ;
+ wire \gpio_defaults[69] ;
+ wire \gpio_defaults[6] ;
+ wire \gpio_defaults[70] ;
+ wire \gpio_defaults[71] ;
+ wire \gpio_defaults[72] ;
+ wire \gpio_defaults[73] ;
+ wire \gpio_defaults[74] ;
+ wire \gpio_defaults[75] ;
+ wire \gpio_defaults[76] ;
+ wire \gpio_defaults[77] ;
+ wire \gpio_defaults[78] ;
+ wire \gpio_defaults[79] ;
+ wire \gpio_defaults[7] ;
+ wire \gpio_defaults[80] ;
+ wire \gpio_defaults[81] ;
+ wire \gpio_defaults[82] ;
+ wire \gpio_defaults[83] ;
+ wire \gpio_defaults[84] ;
+ wire \gpio_defaults[85] ;
+ wire \gpio_defaults[86] ;
+ wire \gpio_defaults[87] ;
+ wire \gpio_defaults[88] ;
+ wire \gpio_defaults[89] ;
+ wire \gpio_defaults[8] ;
+ wire \gpio_defaults[90] ;
+ wire \gpio_defaults[91] ;
+ wire \gpio_defaults[92] ;
+ wire \gpio_defaults[93] ;
+ wire \gpio_defaults[94] ;
+ wire \gpio_defaults[95] ;
+ wire \gpio_defaults[96] ;
+ wire \gpio_defaults[97] ;
+ wire \gpio_defaults[98] ;
+ wire \gpio_defaults[99] ;
+ wire \gpio_defaults[9] ;
+ wire gpio_in_core;
+ wire gpio_inenb_core;
+ wire \gpio_load_1[0] ;
+ wire \gpio_load_1[10] ;
+ wire \gpio_load_1[11] ;
+ wire \gpio_load_1[12] ;
+ wire \gpio_load_1[13] ;
+ wire \gpio_load_1[14] ;
+ wire \gpio_load_1[15] ;
+ wire \gpio_load_1[16] ;
+ wire \gpio_load_1[17] ;
+ wire \gpio_load_1[18] ;
+ wire \gpio_load_1[1] ;
+ wire \gpio_load_1[2] ;
+ wire \gpio_load_1[3] ;
+ wire \gpio_load_1[4] ;
+ wire \gpio_load_1[5] ;
+ wire \gpio_load_1[6] ;
+ wire \gpio_load_1[7] ;
+ wire \gpio_load_1[8] ;
+ wire \gpio_load_1[9] ;
+ wire \gpio_load_1_shifted[0] ;
+ wire \gpio_load_1_shifted[10] ;
+ wire \gpio_load_1_shifted[11] ;
+ wire \gpio_load_1_shifted[12] ;
+ wire \gpio_load_1_shifted[13] ;
+ wire \gpio_load_1_shifted[14] ;
+ wire \gpio_load_1_shifted[15] ;
+ wire \gpio_load_1_shifted[16] ;
+ wire \gpio_load_1_shifted[17] ;
+ wire \gpio_load_1_shifted[18] ;
+ wire \gpio_load_1_shifted[1] ;
+ wire \gpio_load_1_shifted[2] ;
+ wire \gpio_load_1_shifted[3] ;
+ wire \gpio_load_1_shifted[4] ;
+ wire \gpio_load_1_shifted[5] ;
+ wire \gpio_load_1_shifted[6] ;
+ wire \gpio_load_1_shifted[7] ;
+ wire \gpio_load_1_shifted[8] ;
+ wire \gpio_load_1_shifted[9] ;
+ wire \gpio_load_2[0] ;
+ wire \gpio_load_2[10] ;
+ wire \gpio_load_2[11] ;
+ wire \gpio_load_2[12] ;
+ wire \gpio_load_2[13] ;
+ wire \gpio_load_2[14] ;
+ wire \gpio_load_2[15] ;
+ wire \gpio_load_2[16] ;
+ wire \gpio_load_2[17] ;
+ wire \gpio_load_2[18] ;
+ wire \gpio_load_2[1] ;
+ wire \gpio_load_2[2] ;
+ wire \gpio_load_2[3] ;
+ wire \gpio_load_2[4] ;
+ wire \gpio_load_2[5] ;
+ wire \gpio_load_2[6] ;
+ wire \gpio_load_2[7] ;
+ wire \gpio_load_2[8] ;
+ wire \gpio_load_2[9] ;
+ wire \gpio_load_2_shifted[0] ;
+ wire \gpio_load_2_shifted[10] ;
+ wire \gpio_load_2_shifted[11] ;
+ wire \gpio_load_2_shifted[12] ;
+ wire \gpio_load_2_shifted[13] ;
+ wire \gpio_load_2_shifted[14] ;
+ wire \gpio_load_2_shifted[15] ;
+ wire \gpio_load_2_shifted[16] ;
+ wire \gpio_load_2_shifted[17] ;
+ wire \gpio_load_2_shifted[18] ;
+ wire \gpio_load_2_shifted[1] ;
+ wire \gpio_load_2_shifted[2] ;
+ wire \gpio_load_2_shifted[3] ;
+ wire \gpio_load_2_shifted[4] ;
+ wire \gpio_load_2_shifted[5] ;
+ wire \gpio_load_2_shifted[6] ;
+ wire \gpio_load_2_shifted[7] ;
+ wire \gpio_load_2_shifted[8] ;
+ wire \gpio_load_2_shifted[9] ;
+ wire gpio_mode0_core;
+ wire gpio_mode1_core;
+ wire gpio_out_core;
+ wire gpio_outenb_core;
+ wire \gpio_resetn_1[0] ;
+ wire \gpio_resetn_1[10] ;
+ wire \gpio_resetn_1[11] ;
+ wire \gpio_resetn_1[12] ;
+ wire \gpio_resetn_1[13] ;
+ wire \gpio_resetn_1[14] ;
+ wire \gpio_resetn_1[15] ;
+ wire \gpio_resetn_1[16] ;
+ wire \gpio_resetn_1[17] ;
+ wire \gpio_resetn_1[18] ;
+ wire \gpio_resetn_1[1] ;
+ wire \gpio_resetn_1[2] ;
+ wire \gpio_resetn_1[3] ;
+ wire \gpio_resetn_1[4] ;
+ wire \gpio_resetn_1[5] ;
+ wire \gpio_resetn_1[6] ;
+ wire \gpio_resetn_1[7] ;
+ wire \gpio_resetn_1[8] ;
+ wire \gpio_resetn_1[9] ;
+ wire \gpio_resetn_1_shifted[0] ;
+ wire \gpio_resetn_1_shifted[10] ;
+ wire \gpio_resetn_1_shifted[11] ;
+ wire \gpio_resetn_1_shifted[12] ;
+ wire \gpio_resetn_1_shifted[13] ;
+ wire \gpio_resetn_1_shifted[14] ;
+ wire \gpio_resetn_1_shifted[15] ;
+ wire \gpio_resetn_1_shifted[16] ;
+ wire \gpio_resetn_1_shifted[17] ;
+ wire \gpio_resetn_1_shifted[18] ;
+ wire \gpio_resetn_1_shifted[1] ;
+ wire \gpio_resetn_1_shifted[2] ;
+ wire \gpio_resetn_1_shifted[3] ;
+ wire \gpio_resetn_1_shifted[4] ;
+ wire \gpio_resetn_1_shifted[5] ;
+ wire \gpio_resetn_1_shifted[6] ;
+ wire \gpio_resetn_1_shifted[7] ;
+ wire \gpio_resetn_1_shifted[8] ;
+ wire \gpio_resetn_1_shifted[9] ;
+ wire \gpio_resetn_2[0] ;
+ wire \gpio_resetn_2[10] ;
+ wire \gpio_resetn_2[11] ;
+ wire \gpio_resetn_2[12] ;
+ wire \gpio_resetn_2[13] ;
+ wire \gpio_resetn_2[14] ;
+ wire \gpio_resetn_2[15] ;
+ wire \gpio_resetn_2[16] ;
+ wire \gpio_resetn_2[17] ;
+ wire \gpio_resetn_2[18] ;
+ wire \gpio_resetn_2[1] ;
+ wire \gpio_resetn_2[2] ;
+ wire \gpio_resetn_2[3] ;
+ wire \gpio_resetn_2[4] ;
+ wire \gpio_resetn_2[5] ;
+ wire \gpio_resetn_2[6] ;
+ wire \gpio_resetn_2[7] ;
+ wire \gpio_resetn_2[8] ;
+ wire \gpio_resetn_2[9] ;
+ wire \gpio_resetn_2_shifted[0] ;
+ wire \gpio_resetn_2_shifted[10] ;
+ wire \gpio_resetn_2_shifted[11] ;
+ wire \gpio_resetn_2_shifted[12] ;
+ wire \gpio_resetn_2_shifted[13] ;
+ wire \gpio_resetn_2_shifted[14] ;
+ wire \gpio_resetn_2_shifted[15] ;
+ wire \gpio_resetn_2_shifted[16] ;
+ wire \gpio_resetn_2_shifted[17] ;
+ wire \gpio_resetn_2_shifted[18] ;
+ wire \gpio_resetn_2_shifted[1] ;
+ wire \gpio_resetn_2_shifted[2] ;
+ wire \gpio_resetn_2_shifted[3] ;
+ wire \gpio_resetn_2_shifted[4] ;
+ wire \gpio_resetn_2_shifted[5] ;
+ wire \gpio_resetn_2_shifted[6] ;
+ wire \gpio_resetn_2_shifted[7] ;
+ wire \gpio_resetn_2_shifted[8] ;
+ wire \gpio_resetn_2_shifted[9] ;
+ wire \gpio_serial_link_1[0] ;
+ wire \gpio_serial_link_1[10] ;
+ wire \gpio_serial_link_1[11] ;
+ wire \gpio_serial_link_1[12] ;
+ wire \gpio_serial_link_1[13] ;
+ wire \gpio_serial_link_1[14] ;
+ wire \gpio_serial_link_1[15] ;
+ wire \gpio_serial_link_1[16] ;
+ wire \gpio_serial_link_1[17] ;
+ wire \gpio_serial_link_1[18] ;
+ wire \gpio_serial_link_1[1] ;
+ wire \gpio_serial_link_1[2] ;
+ wire \gpio_serial_link_1[3] ;
+ wire \gpio_serial_link_1[4] ;
+ wire \gpio_serial_link_1[5] ;
+ wire \gpio_serial_link_1[6] ;
+ wire \gpio_serial_link_1[7] ;
+ wire \gpio_serial_link_1[8] ;
+ wire \gpio_serial_link_1[9] ;
+ wire \gpio_serial_link_1_shifted[0] ;
+ wire \gpio_serial_link_1_shifted[10] ;
+ wire \gpio_serial_link_1_shifted[11] ;
+ wire \gpio_serial_link_1_shifted[12] ;
+ wire \gpio_serial_link_1_shifted[13] ;
+ wire \gpio_serial_link_1_shifted[14] ;
+ wire \gpio_serial_link_1_shifted[15] ;
+ wire \gpio_serial_link_1_shifted[16] ;
+ wire \gpio_serial_link_1_shifted[17] ;
+ wire \gpio_serial_link_1_shifted[18] ;
+ wire \gpio_serial_link_1_shifted[1] ;
+ wire \gpio_serial_link_1_shifted[2] ;
+ wire \gpio_serial_link_1_shifted[3] ;
+ wire \gpio_serial_link_1_shifted[4] ;
+ wire \gpio_serial_link_1_shifted[5] ;
+ wire \gpio_serial_link_1_shifted[6] ;
+ wire \gpio_serial_link_1_shifted[7] ;
+ wire \gpio_serial_link_1_shifted[8] ;
+ wire \gpio_serial_link_1_shifted[9] ;
+ wire \gpio_serial_link_2[0] ;
+ wire \gpio_serial_link_2[10] ;
+ wire \gpio_serial_link_2[11] ;
+ wire \gpio_serial_link_2[12] ;
+ wire \gpio_serial_link_2[13] ;
+ wire \gpio_serial_link_2[14] ;
+ wire \gpio_serial_link_2[15] ;
+ wire \gpio_serial_link_2[16] ;
+ wire \gpio_serial_link_2[17] ;
+ wire \gpio_serial_link_2[18] ;
+ wire \gpio_serial_link_2[1] ;
+ wire \gpio_serial_link_2[2] ;
+ wire \gpio_serial_link_2[3] ;
+ wire \gpio_serial_link_2[4] ;
+ wire \gpio_serial_link_2[5] ;
+ wire \gpio_serial_link_2[6] ;
+ wire \gpio_serial_link_2[7] ;
+ wire \gpio_serial_link_2[8] ;
+ wire \gpio_serial_link_2[9] ;
+ wire \gpio_serial_link_2_shifted[0] ;
+ wire \gpio_serial_link_2_shifted[10] ;
+ wire \gpio_serial_link_2_shifted[11] ;
+ wire \gpio_serial_link_2_shifted[12] ;
+ wire \gpio_serial_link_2_shifted[13] ;
+ wire \gpio_serial_link_2_shifted[14] ;
+ wire \gpio_serial_link_2_shifted[15] ;
+ wire \gpio_serial_link_2_shifted[16] ;
+ wire \gpio_serial_link_2_shifted[17] ;
+ wire \gpio_serial_link_2_shifted[18] ;
+ wire \gpio_serial_link_2_shifted[1] ;
+ wire \gpio_serial_link_2_shifted[2] ;
+ wire \gpio_serial_link_2_shifted[3] ;
+ wire \gpio_serial_link_2_shifted[4] ;
+ wire \gpio_serial_link_2_shifted[5] ;
+ wire \gpio_serial_link_2_shifted[6] ;
+ wire \gpio_serial_link_2_shifted[7] ;
+ wire \gpio_serial_link_2_shifted[8] ;
+ wire \gpio_serial_link_2_shifted[9] ;
+ wire hk_ack_i;
+ wire hk_cyc_o;
+ wire \hk_dat_i[0] ;
+ wire \hk_dat_i[10] ;
+ wire \hk_dat_i[11] ;
+ wire \hk_dat_i[12] ;
+ wire \hk_dat_i[13] ;
+ wire \hk_dat_i[14] ;
+ wire \hk_dat_i[15] ;
+ wire \hk_dat_i[16] ;
+ wire \hk_dat_i[17] ;
+ wire \hk_dat_i[18] ;
+ wire \hk_dat_i[19] ;
+ wire \hk_dat_i[1] ;
+ wire \hk_dat_i[20] ;
+ wire \hk_dat_i[21] ;
+ wire \hk_dat_i[22] ;
+ wire \hk_dat_i[23] ;
+ wire \hk_dat_i[24] ;
+ wire \hk_dat_i[25] ;
+ wire \hk_dat_i[26] ;
+ wire \hk_dat_i[27] ;
+ wire \hk_dat_i[28] ;
+ wire \hk_dat_i[29] ;
+ wire \hk_dat_i[2] ;
+ wire \hk_dat_i[30] ;
+ wire \hk_dat_i[31] ;
+ wire \hk_dat_i[3] ;
+ wire \hk_dat_i[4] ;
+ wire \hk_dat_i[5] ;
+ wire \hk_dat_i[6] ;
+ wire \hk_dat_i[7] ;
+ wire \hk_dat_i[8] ;
+ wire \hk_dat_i[9] ;
+ wire hk_stb_o;
+ wire \irq_spi[0] ;
+ wire \irq_spi[1] ;
+ wire \irq_spi[2] ;
+ wire \la_data_in_mprj[0] ;
+ wire \la_data_in_mprj[100] ;
+ wire \la_data_in_mprj[101] ;
+ wire \la_data_in_mprj[102] ;
+ wire \la_data_in_mprj[103] ;
+ wire \la_data_in_mprj[104] ;
+ wire \la_data_in_mprj[105] ;
+ wire \la_data_in_mprj[106] ;
+ wire \la_data_in_mprj[107] ;
+ wire \la_data_in_mprj[108] ;
+ wire \la_data_in_mprj[109] ;
+ wire \la_data_in_mprj[10] ;
+ wire \la_data_in_mprj[110] ;
+ wire \la_data_in_mprj[111] ;
+ wire \la_data_in_mprj[112] ;
+ wire \la_data_in_mprj[113] ;
+ wire \la_data_in_mprj[114] ;
+ wire \la_data_in_mprj[115] ;
+ wire \la_data_in_mprj[116] ;
+ wire \la_data_in_mprj[117] ;
+ wire \la_data_in_mprj[118] ;
+ wire \la_data_in_mprj[119] ;
+ wire \la_data_in_mprj[11] ;
+ wire \la_data_in_mprj[120] ;
+ wire \la_data_in_mprj[121] ;
+ wire \la_data_in_mprj[122] ;
+ wire \la_data_in_mprj[123] ;
+ wire \la_data_in_mprj[124] ;
+ wire \la_data_in_mprj[125] ;
+ wire \la_data_in_mprj[126] ;
+ wire \la_data_in_mprj[127] ;
+ wire \la_data_in_mprj[12] ;
+ wire \la_data_in_mprj[13] ;
+ wire \la_data_in_mprj[14] ;
+ wire \la_data_in_mprj[15] ;
+ wire \la_data_in_mprj[16] ;
+ wire \la_data_in_mprj[17] ;
+ wire \la_data_in_mprj[18] ;
+ wire \la_data_in_mprj[19] ;
+ wire \la_data_in_mprj[1] ;
+ wire \la_data_in_mprj[20] ;
+ wire \la_data_in_mprj[21] ;
+ wire \la_data_in_mprj[22] ;
+ wire \la_data_in_mprj[23] ;
+ wire \la_data_in_mprj[24] ;
+ wire \la_data_in_mprj[25] ;
+ wire \la_data_in_mprj[26] ;
+ wire \la_data_in_mprj[27] ;
+ wire \la_data_in_mprj[28] ;
+ wire \la_data_in_mprj[29] ;
+ wire \la_data_in_mprj[2] ;
+ wire \la_data_in_mprj[30] ;
+ wire \la_data_in_mprj[31] ;
+ wire \la_data_in_mprj[32] ;
+ wire \la_data_in_mprj[33] ;
+ wire \la_data_in_mprj[34] ;
+ wire \la_data_in_mprj[35] ;
+ wire \la_data_in_mprj[36] ;
+ wire \la_data_in_mprj[37] ;
+ wire \la_data_in_mprj[38] ;
+ wire \la_data_in_mprj[39] ;
+ wire \la_data_in_mprj[3] ;
+ wire \la_data_in_mprj[40] ;
+ wire \la_data_in_mprj[41] ;
+ wire \la_data_in_mprj[42] ;
+ wire \la_data_in_mprj[43] ;
+ wire \la_data_in_mprj[44] ;
+ wire \la_data_in_mprj[45] ;
+ wire \la_data_in_mprj[46] ;
+ wire \la_data_in_mprj[47] ;
+ wire \la_data_in_mprj[48] ;
+ wire \la_data_in_mprj[49] ;
+ wire \la_data_in_mprj[4] ;
+ wire \la_data_in_mprj[50] ;
+ wire \la_data_in_mprj[51] ;
+ wire \la_data_in_mprj[52] ;
+ wire \la_data_in_mprj[53] ;
+ wire \la_data_in_mprj[54] ;
+ wire \la_data_in_mprj[55] ;
+ wire \la_data_in_mprj[56] ;
+ wire \la_data_in_mprj[57] ;
+ wire \la_data_in_mprj[58] ;
+ wire \la_data_in_mprj[59] ;
+ wire \la_data_in_mprj[5] ;
+ wire \la_data_in_mprj[60] ;
+ wire \la_data_in_mprj[61] ;
+ wire \la_data_in_mprj[62] ;
+ wire \la_data_in_mprj[63] ;
+ wire \la_data_in_mprj[64] ;
+ wire \la_data_in_mprj[65] ;
+ wire \la_data_in_mprj[66] ;
+ wire \la_data_in_mprj[67] ;
+ wire \la_data_in_mprj[68] ;
+ wire \la_data_in_mprj[69] ;
+ wire \la_data_in_mprj[6] ;
+ wire \la_data_in_mprj[70] ;
+ wire \la_data_in_mprj[71] ;
+ wire \la_data_in_mprj[72] ;
+ wire \la_data_in_mprj[73] ;
+ wire \la_data_in_mprj[74] ;
+ wire \la_data_in_mprj[75] ;
+ wire \la_data_in_mprj[76] ;
+ wire \la_data_in_mprj[77] ;
+ wire \la_data_in_mprj[78] ;
+ wire \la_data_in_mprj[79] ;
+ wire \la_data_in_mprj[7] ;
+ wire \la_data_in_mprj[80] ;
+ wire \la_data_in_mprj[81] ;
+ wire \la_data_in_mprj[82] ;
+ wire \la_data_in_mprj[83] ;
+ wire \la_data_in_mprj[84] ;
+ wire \la_data_in_mprj[85] ;
+ wire \la_data_in_mprj[86] ;
+ wire \la_data_in_mprj[87] ;
+ wire \la_data_in_mprj[88] ;
+ wire \la_data_in_mprj[89] ;
+ wire \la_data_in_mprj[8] ;
+ wire \la_data_in_mprj[90] ;
+ wire \la_data_in_mprj[91] ;
+ wire \la_data_in_mprj[92] ;
+ wire \la_data_in_mprj[93] ;
+ wire \la_data_in_mprj[94] ;
+ wire \la_data_in_mprj[95] ;
+ wire \la_data_in_mprj[96] ;
+ wire \la_data_in_mprj[97] ;
+ wire \la_data_in_mprj[98] ;
+ wire \la_data_in_mprj[99] ;
+ wire \la_data_in_mprj[9] ;
+ wire \la_data_in_user[0] ;
+ wire \la_data_in_user[100] ;
+ wire \la_data_in_user[101] ;
+ wire \la_data_in_user[102] ;
+ wire \la_data_in_user[103] ;
+ wire \la_data_in_user[104] ;
+ wire \la_data_in_user[105] ;
+ wire \la_data_in_user[106] ;
+ wire \la_data_in_user[107] ;
+ wire \la_data_in_user[108] ;
+ wire \la_data_in_user[109] ;
+ wire \la_data_in_user[10] ;
+ wire \la_data_in_user[110] ;
+ wire \la_data_in_user[111] ;
+ wire \la_data_in_user[112] ;
+ wire \la_data_in_user[113] ;
+ wire \la_data_in_user[114] ;
+ wire \la_data_in_user[115] ;
+ wire \la_data_in_user[116] ;
+ wire \la_data_in_user[117] ;
+ wire \la_data_in_user[118] ;
+ wire \la_data_in_user[119] ;
+ wire \la_data_in_user[11] ;
+ wire \la_data_in_user[120] ;
+ wire \la_data_in_user[121] ;
+ wire \la_data_in_user[122] ;
+ wire \la_data_in_user[123] ;
+ wire \la_data_in_user[124] ;
+ wire \la_data_in_user[125] ;
+ wire \la_data_in_user[126] ;
+ wire \la_data_in_user[127] ;
+ wire \la_data_in_user[12] ;
+ wire \la_data_in_user[13] ;
+ wire \la_data_in_user[14] ;
+ wire \la_data_in_user[15] ;
+ wire \la_data_in_user[16] ;
+ wire \la_data_in_user[17] ;
+ wire \la_data_in_user[18] ;
+ wire \la_data_in_user[19] ;
+ wire \la_data_in_user[1] ;
+ wire \la_data_in_user[20] ;
+ wire \la_data_in_user[21] ;
+ wire \la_data_in_user[22] ;
+ wire \la_data_in_user[23] ;
+ wire \la_data_in_user[24] ;
+ wire \la_data_in_user[25] ;
+ wire \la_data_in_user[26] ;
+ wire \la_data_in_user[27] ;
+ wire \la_data_in_user[28] ;
+ wire \la_data_in_user[29] ;
+ wire \la_data_in_user[2] ;
+ wire \la_data_in_user[30] ;
+ wire \la_data_in_user[31] ;
+ wire \la_data_in_user[32] ;
+ wire \la_data_in_user[33] ;
+ wire \la_data_in_user[34] ;
+ wire \la_data_in_user[35] ;
+ wire \la_data_in_user[36] ;
+ wire \la_data_in_user[37] ;
+ wire \la_data_in_user[38] ;
+ wire \la_data_in_user[39] ;
+ wire \la_data_in_user[3] ;
+ wire \la_data_in_user[40] ;
+ wire \la_data_in_user[41] ;
+ wire \la_data_in_user[42] ;
+ wire \la_data_in_user[43] ;
+ wire \la_data_in_user[44] ;
+ wire \la_data_in_user[45] ;
+ wire \la_data_in_user[46] ;
+ wire \la_data_in_user[47] ;
+ wire \la_data_in_user[48] ;
+ wire \la_data_in_user[49] ;
+ wire \la_data_in_user[4] ;
+ wire \la_data_in_user[50] ;
+ wire \la_data_in_user[51] ;
+ wire \la_data_in_user[52] ;
+ wire \la_data_in_user[53] ;
+ wire \la_data_in_user[54] ;
+ wire \la_data_in_user[55] ;
+ wire \la_data_in_user[56] ;
+ wire \la_data_in_user[57] ;
+ wire \la_data_in_user[58] ;
+ wire \la_data_in_user[59] ;
+ wire \la_data_in_user[5] ;
+ wire \la_data_in_user[60] ;
+ wire \la_data_in_user[61] ;
+ wire \la_data_in_user[62] ;
+ wire \la_data_in_user[63] ;
+ wire \la_data_in_user[64] ;
+ wire \la_data_in_user[65] ;
+ wire \la_data_in_user[66] ;
+ wire \la_data_in_user[67] ;
+ wire \la_data_in_user[68] ;
+ wire \la_data_in_user[69] ;
+ wire \la_data_in_user[6] ;
+ wire \la_data_in_user[70] ;
+ wire \la_data_in_user[71] ;
+ wire \la_data_in_user[72] ;
+ wire \la_data_in_user[73] ;
+ wire \la_data_in_user[74] ;
+ wire \la_data_in_user[75] ;
+ wire \la_data_in_user[76] ;
+ wire \la_data_in_user[77] ;
+ wire \la_data_in_user[78] ;
+ wire \la_data_in_user[79] ;
+ wire \la_data_in_user[7] ;
+ wire \la_data_in_user[80] ;
+ wire \la_data_in_user[81] ;
+ wire \la_data_in_user[82] ;
+ wire \la_data_in_user[83] ;
+ wire \la_data_in_user[84] ;
+ wire \la_data_in_user[85] ;
+ wire \la_data_in_user[86] ;
+ wire \la_data_in_user[87] ;
+ wire \la_data_in_user[88] ;
+ wire \la_data_in_user[89] ;
+ wire \la_data_in_user[8] ;
+ wire \la_data_in_user[90] ;
+ wire \la_data_in_user[91] ;
+ wire \la_data_in_user[92] ;
+ wire \la_data_in_user[93] ;
+ wire \la_data_in_user[94] ;
+ wire \la_data_in_user[95] ;
+ wire \la_data_in_user[96] ;
+ wire \la_data_in_user[97] ;
+ wire \la_data_in_user[98] ;
+ wire \la_data_in_user[99] ;
+ wire \la_data_in_user[9] ;
+ wire \la_data_out_mprj[0] ;
+ wire \la_data_out_mprj[100] ;
+ wire \la_data_out_mprj[101] ;
+ wire \la_data_out_mprj[102] ;
+ wire \la_data_out_mprj[103] ;
+ wire \la_data_out_mprj[104] ;
+ wire \la_data_out_mprj[105] ;
+ wire \la_data_out_mprj[106] ;
+ wire \la_data_out_mprj[107] ;
+ wire \la_data_out_mprj[108] ;
+ wire \la_data_out_mprj[109] ;
+ wire \la_data_out_mprj[10] ;
+ wire \la_data_out_mprj[110] ;
+ wire \la_data_out_mprj[111] ;
+ wire \la_data_out_mprj[112] ;
+ wire \la_data_out_mprj[113] ;
+ wire \la_data_out_mprj[114] ;
+ wire \la_data_out_mprj[115] ;
+ wire \la_data_out_mprj[116] ;
+ wire \la_data_out_mprj[117] ;
+ wire \la_data_out_mprj[118] ;
+ wire \la_data_out_mprj[119] ;
+ wire \la_data_out_mprj[11] ;
+ wire \la_data_out_mprj[120] ;
+ wire \la_data_out_mprj[121] ;
+ wire \la_data_out_mprj[122] ;
+ wire \la_data_out_mprj[123] ;
+ wire \la_data_out_mprj[124] ;
+ wire \la_data_out_mprj[125] ;
+ wire \la_data_out_mprj[126] ;
+ wire \la_data_out_mprj[127] ;
+ wire \la_data_out_mprj[12] ;
+ wire \la_data_out_mprj[13] ;
+ wire \la_data_out_mprj[14] ;
+ wire \la_data_out_mprj[15] ;
+ wire \la_data_out_mprj[16] ;
+ wire \la_data_out_mprj[17] ;
+ wire \la_data_out_mprj[18] ;
+ wire \la_data_out_mprj[19] ;
+ wire \la_data_out_mprj[1] ;
+ wire \la_data_out_mprj[20] ;
+ wire \la_data_out_mprj[21] ;
+ wire \la_data_out_mprj[22] ;
+ wire \la_data_out_mprj[23] ;
+ wire \la_data_out_mprj[24] ;
+ wire \la_data_out_mprj[25] ;
+ wire \la_data_out_mprj[26] ;
+ wire \la_data_out_mprj[27] ;
+ wire \la_data_out_mprj[28] ;
+ wire \la_data_out_mprj[29] ;
+ wire \la_data_out_mprj[2] ;
+ wire \la_data_out_mprj[30] ;
+ wire \la_data_out_mprj[31] ;
+ wire \la_data_out_mprj[32] ;
+ wire \la_data_out_mprj[33] ;
+ wire \la_data_out_mprj[34] ;
+ wire \la_data_out_mprj[35] ;
+ wire \la_data_out_mprj[36] ;
+ wire \la_data_out_mprj[37] ;
+ wire \la_data_out_mprj[38] ;
+ wire \la_data_out_mprj[39] ;
+ wire \la_data_out_mprj[3] ;
+ wire \la_data_out_mprj[40] ;
+ wire \la_data_out_mprj[41] ;
+ wire \la_data_out_mprj[42] ;
+ wire \la_data_out_mprj[43] ;
+ wire \la_data_out_mprj[44] ;
+ wire \la_data_out_mprj[45] ;
+ wire \la_data_out_mprj[46] ;
+ wire \la_data_out_mprj[47] ;
+ wire \la_data_out_mprj[48] ;
+ wire \la_data_out_mprj[49] ;
+ wire \la_data_out_mprj[4] ;
+ wire \la_data_out_mprj[50] ;
+ wire \la_data_out_mprj[51] ;
+ wire \la_data_out_mprj[52] ;
+ wire \la_data_out_mprj[53] ;
+ wire \la_data_out_mprj[54] ;
+ wire \la_data_out_mprj[55] ;
+ wire \la_data_out_mprj[56] ;
+ wire \la_data_out_mprj[57] ;
+ wire \la_data_out_mprj[58] ;
+ wire \la_data_out_mprj[59] ;
+ wire \la_data_out_mprj[5] ;
+ wire \la_data_out_mprj[60] ;
+ wire \la_data_out_mprj[61] ;
+ wire \la_data_out_mprj[62] ;
+ wire \la_data_out_mprj[63] ;
+ wire \la_data_out_mprj[64] ;
+ wire \la_data_out_mprj[65] ;
+ wire \la_data_out_mprj[66] ;
+ wire \la_data_out_mprj[67] ;
+ wire \la_data_out_mprj[68] ;
+ wire \la_data_out_mprj[69] ;
+ wire \la_data_out_mprj[6] ;
+ wire \la_data_out_mprj[70] ;
+ wire \la_data_out_mprj[71] ;
+ wire \la_data_out_mprj[72] ;
+ wire \la_data_out_mprj[73] ;
+ wire \la_data_out_mprj[74] ;
+ wire \la_data_out_mprj[75] ;
+ wire \la_data_out_mprj[76] ;
+ wire \la_data_out_mprj[77] ;
+ wire \la_data_out_mprj[78] ;
+ wire \la_data_out_mprj[79] ;
+ wire \la_data_out_mprj[7] ;
+ wire \la_data_out_mprj[80] ;
+ wire \la_data_out_mprj[81] ;
+ wire \la_data_out_mprj[82] ;
+ wire \la_data_out_mprj[83] ;
+ wire \la_data_out_mprj[84] ;
+ wire \la_data_out_mprj[85] ;
+ wire \la_data_out_mprj[86] ;
+ wire \la_data_out_mprj[87] ;
+ wire \la_data_out_mprj[88] ;
+ wire \la_data_out_mprj[89] ;
+ wire \la_data_out_mprj[8] ;
+ wire \la_data_out_mprj[90] ;
+ wire \la_data_out_mprj[91] ;
+ wire \la_data_out_mprj[92] ;
+ wire \la_data_out_mprj[93] ;
+ wire \la_data_out_mprj[94] ;
+ wire \la_data_out_mprj[95] ;
+ wire \la_data_out_mprj[96] ;
+ wire \la_data_out_mprj[97] ;
+ wire \la_data_out_mprj[98] ;
+ wire \la_data_out_mprj[99] ;
+ wire \la_data_out_mprj[9] ;
+ wire \la_data_out_user[0] ;
+ wire \la_data_out_user[100] ;
+ wire \la_data_out_user[101] ;
+ wire \la_data_out_user[102] ;
+ wire \la_data_out_user[103] ;
+ wire \la_data_out_user[104] ;
+ wire \la_data_out_user[105] ;
+ wire \la_data_out_user[106] ;
+ wire \la_data_out_user[107] ;
+ wire \la_data_out_user[108] ;
+ wire \la_data_out_user[109] ;
+ wire \la_data_out_user[10] ;
+ wire \la_data_out_user[110] ;
+ wire \la_data_out_user[111] ;
+ wire \la_data_out_user[112] ;
+ wire \la_data_out_user[113] ;
+ wire \la_data_out_user[114] ;
+ wire \la_data_out_user[115] ;
+ wire \la_data_out_user[116] ;
+ wire \la_data_out_user[117] ;
+ wire \la_data_out_user[118] ;
+ wire \la_data_out_user[119] ;
+ wire \la_data_out_user[11] ;
+ wire \la_data_out_user[120] ;
+ wire \la_data_out_user[121] ;
+ wire \la_data_out_user[122] ;
+ wire \la_data_out_user[123] ;
+ wire \la_data_out_user[124] ;
+ wire \la_data_out_user[125] ;
+ wire \la_data_out_user[126] ;
+ wire \la_data_out_user[127] ;
+ wire \la_data_out_user[12] ;
+ wire \la_data_out_user[13] ;
+ wire \la_data_out_user[14] ;
+ wire \la_data_out_user[15] ;
+ wire \la_data_out_user[16] ;
+ wire \la_data_out_user[17] ;
+ wire \la_data_out_user[18] ;
+ wire \la_data_out_user[19] ;
+ wire \la_data_out_user[1] ;
+ wire \la_data_out_user[20] ;
+ wire \la_data_out_user[21] ;
+ wire \la_data_out_user[22] ;
+ wire \la_data_out_user[23] ;
+ wire \la_data_out_user[24] ;
+ wire \la_data_out_user[25] ;
+ wire \la_data_out_user[26] ;
+ wire \la_data_out_user[27] ;
+ wire \la_data_out_user[28] ;
+ wire \la_data_out_user[29] ;
+ wire \la_data_out_user[2] ;
+ wire \la_data_out_user[30] ;
+ wire \la_data_out_user[31] ;
+ wire \la_data_out_user[32] ;
+ wire \la_data_out_user[33] ;
+ wire \la_data_out_user[34] ;
+ wire \la_data_out_user[35] ;
+ wire \la_data_out_user[36] ;
+ wire \la_data_out_user[37] ;
+ wire \la_data_out_user[38] ;
+ wire \la_data_out_user[39] ;
+ wire \la_data_out_user[3] ;
+ wire \la_data_out_user[40] ;
+ wire \la_data_out_user[41] ;
+ wire \la_data_out_user[42] ;
+ wire \la_data_out_user[43] ;
+ wire \la_data_out_user[44] ;
+ wire \la_data_out_user[45] ;
+ wire \la_data_out_user[46] ;
+ wire \la_data_out_user[47] ;
+ wire \la_data_out_user[48] ;
+ wire \la_data_out_user[49] ;
+ wire \la_data_out_user[4] ;
+ wire \la_data_out_user[50] ;
+ wire \la_data_out_user[51] ;
+ wire \la_data_out_user[52] ;
+ wire \la_data_out_user[53] ;
+ wire \la_data_out_user[54] ;
+ wire \la_data_out_user[55] ;
+ wire \la_data_out_user[56] ;
+ wire \la_data_out_user[57] ;
+ wire \la_data_out_user[58] ;
+ wire \la_data_out_user[59] ;
+ wire \la_data_out_user[5] ;
+ wire \la_data_out_user[60] ;
+ wire \la_data_out_user[61] ;
+ wire \la_data_out_user[62] ;
+ wire \la_data_out_user[63] ;
+ wire \la_data_out_user[64] ;
+ wire \la_data_out_user[65] ;
+ wire \la_data_out_user[66] ;
+ wire \la_data_out_user[67] ;
+ wire \la_data_out_user[68] ;
+ wire \la_data_out_user[69] ;
+ wire \la_data_out_user[6] ;
+ wire \la_data_out_user[70] ;
+ wire \la_data_out_user[71] ;
+ wire \la_data_out_user[72] ;
+ wire \la_data_out_user[73] ;
+ wire \la_data_out_user[74] ;
+ wire \la_data_out_user[75] ;
+ wire \la_data_out_user[76] ;
+ wire \la_data_out_user[77] ;
+ wire \la_data_out_user[78] ;
+ wire \la_data_out_user[79] ;
+ wire \la_data_out_user[7] ;
+ wire \la_data_out_user[80] ;
+ wire \la_data_out_user[81] ;
+ wire \la_data_out_user[82] ;
+ wire \la_data_out_user[83] ;
+ wire \la_data_out_user[84] ;
+ wire \la_data_out_user[85] ;
+ wire \la_data_out_user[86] ;
+ wire \la_data_out_user[87] ;
+ wire \la_data_out_user[88] ;
+ wire \la_data_out_user[89] ;
+ wire \la_data_out_user[8] ;
+ wire \la_data_out_user[90] ;
+ wire \la_data_out_user[91] ;
+ wire \la_data_out_user[92] ;
+ wire \la_data_out_user[93] ;
+ wire \la_data_out_user[94] ;
+ wire \la_data_out_user[95] ;
+ wire \la_data_out_user[96] ;
+ wire \la_data_out_user[97] ;
+ wire \la_data_out_user[98] ;
+ wire \la_data_out_user[99] ;
+ wire \la_data_out_user[9] ;
+ wire \la_iena_mprj[0] ;
+ wire \la_iena_mprj[100] ;
+ wire \la_iena_mprj[101] ;
+ wire \la_iena_mprj[102] ;
+ wire \la_iena_mprj[103] ;
+ wire \la_iena_mprj[104] ;
+ wire \la_iena_mprj[105] ;
+ wire \la_iena_mprj[106] ;
+ wire \la_iena_mprj[107] ;
+ wire \la_iena_mprj[108] ;
+ wire \la_iena_mprj[109] ;
+ wire \la_iena_mprj[10] ;
+ wire \la_iena_mprj[110] ;
+ wire \la_iena_mprj[111] ;
+ wire \la_iena_mprj[112] ;
+ wire \la_iena_mprj[113] ;
+ wire \la_iena_mprj[114] ;
+ wire \la_iena_mprj[115] ;
+ wire \la_iena_mprj[116] ;
+ wire \la_iena_mprj[117] ;
+ wire \la_iena_mprj[118] ;
+ wire \la_iena_mprj[119] ;
+ wire \la_iena_mprj[11] ;
+ wire \la_iena_mprj[120] ;
+ wire \la_iena_mprj[121] ;
+ wire \la_iena_mprj[122] ;
+ wire \la_iena_mprj[123] ;
+ wire \la_iena_mprj[124] ;
+ wire \la_iena_mprj[125] ;
+ wire \la_iena_mprj[126] ;
+ wire \la_iena_mprj[127] ;
+ wire \la_iena_mprj[12] ;
+ wire \la_iena_mprj[13] ;
+ wire \la_iena_mprj[14] ;
+ wire \la_iena_mprj[15] ;
+ wire \la_iena_mprj[16] ;
+ wire \la_iena_mprj[17] ;
+ wire \la_iena_mprj[18] ;
+ wire \la_iena_mprj[19] ;
+ wire \la_iena_mprj[1] ;
+ wire \la_iena_mprj[20] ;
+ wire \la_iena_mprj[21] ;
+ wire \la_iena_mprj[22] ;
+ wire \la_iena_mprj[23] ;
+ wire \la_iena_mprj[24] ;
+ wire \la_iena_mprj[25] ;
+ wire \la_iena_mprj[26] ;
+ wire \la_iena_mprj[27] ;
+ wire \la_iena_mprj[28] ;
+ wire \la_iena_mprj[29] ;
+ wire \la_iena_mprj[2] ;
+ wire \la_iena_mprj[30] ;
+ wire \la_iena_mprj[31] ;
+ wire \la_iena_mprj[32] ;
+ wire \la_iena_mprj[33] ;
+ wire \la_iena_mprj[34] ;
+ wire \la_iena_mprj[35] ;
+ wire \la_iena_mprj[36] ;
+ wire \la_iena_mprj[37] ;
+ wire \la_iena_mprj[38] ;
+ wire \la_iena_mprj[39] ;
+ wire \la_iena_mprj[3] ;
+ wire \la_iena_mprj[40] ;
+ wire \la_iena_mprj[41] ;
+ wire \la_iena_mprj[42] ;
+ wire \la_iena_mprj[43] ;
+ wire \la_iena_mprj[44] ;
+ wire \la_iena_mprj[45] ;
+ wire \la_iena_mprj[46] ;
+ wire \la_iena_mprj[47] ;
+ wire \la_iena_mprj[48] ;
+ wire \la_iena_mprj[49] ;
+ wire \la_iena_mprj[4] ;
+ wire \la_iena_mprj[50] ;
+ wire \la_iena_mprj[51] ;
+ wire \la_iena_mprj[52] ;
+ wire \la_iena_mprj[53] ;
+ wire \la_iena_mprj[54] ;
+ wire \la_iena_mprj[55] ;
+ wire \la_iena_mprj[56] ;
+ wire \la_iena_mprj[57] ;
+ wire \la_iena_mprj[58] ;
+ wire \la_iena_mprj[59] ;
+ wire \la_iena_mprj[5] ;
+ wire \la_iena_mprj[60] ;
+ wire \la_iena_mprj[61] ;
+ wire \la_iena_mprj[62] ;
+ wire \la_iena_mprj[63] ;
+ wire \la_iena_mprj[64] ;
+ wire \la_iena_mprj[65] ;
+ wire \la_iena_mprj[66] ;
+ wire \la_iena_mprj[67] ;
+ wire \la_iena_mprj[68] ;
+ wire \la_iena_mprj[69] ;
+ wire \la_iena_mprj[6] ;
+ wire \la_iena_mprj[70] ;
+ wire \la_iena_mprj[71] ;
+ wire \la_iena_mprj[72] ;
+ wire \la_iena_mprj[73] ;
+ wire \la_iena_mprj[74] ;
+ wire \la_iena_mprj[75] ;
+ wire \la_iena_mprj[76] ;
+ wire \la_iena_mprj[77] ;
+ wire \la_iena_mprj[78] ;
+ wire \la_iena_mprj[79] ;
+ wire \la_iena_mprj[7] ;
+ wire \la_iena_mprj[80] ;
+ wire \la_iena_mprj[81] ;
+ wire \la_iena_mprj[82] ;
+ wire \la_iena_mprj[83] ;
+ wire \la_iena_mprj[84] ;
+ wire \la_iena_mprj[85] ;
+ wire \la_iena_mprj[86] ;
+ wire \la_iena_mprj[87] ;
+ wire \la_iena_mprj[88] ;
+ wire \la_iena_mprj[89] ;
+ wire \la_iena_mprj[8] ;
+ wire \la_iena_mprj[90] ;
+ wire \la_iena_mprj[91] ;
+ wire \la_iena_mprj[92] ;
+ wire \la_iena_mprj[93] ;
+ wire \la_iena_mprj[94] ;
+ wire \la_iena_mprj[95] ;
+ wire \la_iena_mprj[96] ;
+ wire \la_iena_mprj[97] ;
+ wire \la_iena_mprj[98] ;
+ wire \la_iena_mprj[99] ;
+ wire \la_iena_mprj[9] ;
+ wire \la_oenb_mprj[0] ;
+ wire \la_oenb_mprj[100] ;
+ wire \la_oenb_mprj[101] ;
+ wire \la_oenb_mprj[102] ;
+ wire \la_oenb_mprj[103] ;
+ wire \la_oenb_mprj[104] ;
+ wire \la_oenb_mprj[105] ;
+ wire \la_oenb_mprj[106] ;
+ wire \la_oenb_mprj[107] ;
+ wire \la_oenb_mprj[108] ;
+ wire \la_oenb_mprj[109] ;
+ wire \la_oenb_mprj[10] ;
+ wire \la_oenb_mprj[110] ;
+ wire \la_oenb_mprj[111] ;
+ wire \la_oenb_mprj[112] ;
+ wire \la_oenb_mprj[113] ;
+ wire \la_oenb_mprj[114] ;
+ wire \la_oenb_mprj[115] ;
+ wire \la_oenb_mprj[116] ;
+ wire \la_oenb_mprj[117] ;
+ wire \la_oenb_mprj[118] ;
+ wire \la_oenb_mprj[119] ;
+ wire \la_oenb_mprj[11] ;
+ wire \la_oenb_mprj[120] ;
+ wire \la_oenb_mprj[121] ;
+ wire \la_oenb_mprj[122] ;
+ wire \la_oenb_mprj[123] ;
+ wire \la_oenb_mprj[124] ;
+ wire \la_oenb_mprj[125] ;
+ wire \la_oenb_mprj[126] ;
+ wire \la_oenb_mprj[127] ;
+ wire \la_oenb_mprj[12] ;
+ wire \la_oenb_mprj[13] ;
+ wire \la_oenb_mprj[14] ;
+ wire \la_oenb_mprj[15] ;
+ wire \la_oenb_mprj[16] ;
+ wire \la_oenb_mprj[17] ;
+ wire \la_oenb_mprj[18] ;
+ wire \la_oenb_mprj[19] ;
+ wire \la_oenb_mprj[1] ;
+ wire \la_oenb_mprj[20] ;
+ wire \la_oenb_mprj[21] ;
+ wire \la_oenb_mprj[22] ;
+ wire \la_oenb_mprj[23] ;
+ wire \la_oenb_mprj[24] ;
+ wire \la_oenb_mprj[25] ;
+ wire \la_oenb_mprj[26] ;
+ wire \la_oenb_mprj[27] ;
+ wire \la_oenb_mprj[28] ;
+ wire \la_oenb_mprj[29] ;
+ wire \la_oenb_mprj[2] ;
+ wire \la_oenb_mprj[30] ;
+ wire \la_oenb_mprj[31] ;
+ wire \la_oenb_mprj[32] ;
+ wire \la_oenb_mprj[33] ;
+ wire \la_oenb_mprj[34] ;
+ wire \la_oenb_mprj[35] ;
+ wire \la_oenb_mprj[36] ;
+ wire \la_oenb_mprj[37] ;
+ wire \la_oenb_mprj[38] ;
+ wire \la_oenb_mprj[39] ;
+ wire \la_oenb_mprj[3] ;
+ wire \la_oenb_mprj[40] ;
+ wire \la_oenb_mprj[41] ;
+ wire \la_oenb_mprj[42] ;
+ wire \la_oenb_mprj[43] ;
+ wire \la_oenb_mprj[44] ;
+ wire \la_oenb_mprj[45] ;
+ wire \la_oenb_mprj[46] ;
+ wire \la_oenb_mprj[47] ;
+ wire \la_oenb_mprj[48] ;
+ wire \la_oenb_mprj[49] ;
+ wire \la_oenb_mprj[4] ;
+ wire \la_oenb_mprj[50] ;
+ wire \la_oenb_mprj[51] ;
+ wire \la_oenb_mprj[52] ;
+ wire \la_oenb_mprj[53] ;
+ wire \la_oenb_mprj[54] ;
+ wire \la_oenb_mprj[55] ;
+ wire \la_oenb_mprj[56] ;
+ wire \la_oenb_mprj[57] ;
+ wire \la_oenb_mprj[58] ;
+ wire \la_oenb_mprj[59] ;
+ wire \la_oenb_mprj[5] ;
+ wire \la_oenb_mprj[60] ;
+ wire \la_oenb_mprj[61] ;
+ wire \la_oenb_mprj[62] ;
+ wire \la_oenb_mprj[63] ;
+ wire \la_oenb_mprj[64] ;
+ wire \la_oenb_mprj[65] ;
+ wire \la_oenb_mprj[66] ;
+ wire \la_oenb_mprj[67] ;
+ wire \la_oenb_mprj[68] ;
+ wire \la_oenb_mprj[69] ;
+ wire \la_oenb_mprj[6] ;
+ wire \la_oenb_mprj[70] ;
+ wire \la_oenb_mprj[71] ;
+ wire \la_oenb_mprj[72] ;
+ wire \la_oenb_mprj[73] ;
+ wire \la_oenb_mprj[74] ;
+ wire \la_oenb_mprj[75] ;
+ wire \la_oenb_mprj[76] ;
+ wire \la_oenb_mprj[77] ;
+ wire \la_oenb_mprj[78] ;
+ wire \la_oenb_mprj[79] ;
+ wire \la_oenb_mprj[7] ;
+ wire \la_oenb_mprj[80] ;
+ wire \la_oenb_mprj[81] ;
+ wire \la_oenb_mprj[82] ;
+ wire \la_oenb_mprj[83] ;
+ wire \la_oenb_mprj[84] ;
+ wire \la_oenb_mprj[85] ;
+ wire \la_oenb_mprj[86] ;
+ wire \la_oenb_mprj[87] ;
+ wire \la_oenb_mprj[88] ;
+ wire \la_oenb_mprj[89] ;
+ wire \la_oenb_mprj[8] ;
+ wire \la_oenb_mprj[90] ;
+ wire \la_oenb_mprj[91] ;
+ wire \la_oenb_mprj[92] ;
+ wire \la_oenb_mprj[93] ;
+ wire \la_oenb_mprj[94] ;
+ wire \la_oenb_mprj[95] ;
+ wire \la_oenb_mprj[96] ;
+ wire \la_oenb_mprj[97] ;
+ wire \la_oenb_mprj[98] ;
+ wire \la_oenb_mprj[99] ;
+ wire \la_oenb_mprj[9] ;
+ wire \la_oenb_user[0] ;
+ wire \la_oenb_user[100] ;
+ wire \la_oenb_user[101] ;
+ wire \la_oenb_user[102] ;
+ wire \la_oenb_user[103] ;
+ wire \la_oenb_user[104] ;
+ wire \la_oenb_user[105] ;
+ wire \la_oenb_user[106] ;
+ wire \la_oenb_user[107] ;
+ wire \la_oenb_user[108] ;
+ wire \la_oenb_user[109] ;
+ wire \la_oenb_user[10] ;
+ wire \la_oenb_user[110] ;
+ wire \la_oenb_user[111] ;
+ wire \la_oenb_user[112] ;
+ wire \la_oenb_user[113] ;
+ wire \la_oenb_user[114] ;
+ wire \la_oenb_user[115] ;
+ wire \la_oenb_user[116] ;
+ wire \la_oenb_user[117] ;
+ wire \la_oenb_user[118] ;
+ wire \la_oenb_user[119] ;
+ wire \la_oenb_user[11] ;
+ wire \la_oenb_user[120] ;
+ wire \la_oenb_user[121] ;
+ wire \la_oenb_user[122] ;
+ wire \la_oenb_user[123] ;
+ wire \la_oenb_user[124] ;
+ wire \la_oenb_user[125] ;
+ wire \la_oenb_user[126] ;
+ wire \la_oenb_user[127] ;
+ wire \la_oenb_user[12] ;
+ wire \la_oenb_user[13] ;
+ wire \la_oenb_user[14] ;
+ wire \la_oenb_user[15] ;
+ wire \la_oenb_user[16] ;
+ wire \la_oenb_user[17] ;
+ wire \la_oenb_user[18] ;
+ wire \la_oenb_user[19] ;
+ wire \la_oenb_user[1] ;
+ wire \la_oenb_user[20] ;
+ wire \la_oenb_user[21] ;
+ wire \la_oenb_user[22] ;
+ wire \la_oenb_user[23] ;
+ wire \la_oenb_user[24] ;
+ wire \la_oenb_user[25] ;
+ wire \la_oenb_user[26] ;
+ wire \la_oenb_user[27] ;
+ wire \la_oenb_user[28] ;
+ wire \la_oenb_user[29] ;
+ wire \la_oenb_user[2] ;
+ wire \la_oenb_user[30] ;
+ wire \la_oenb_user[31] ;
+ wire \la_oenb_user[32] ;
+ wire \la_oenb_user[33] ;
+ wire \la_oenb_user[34] ;
+ wire \la_oenb_user[35] ;
+ wire \la_oenb_user[36] ;
+ wire \la_oenb_user[37] ;
+ wire \la_oenb_user[38] ;
+ wire \la_oenb_user[39] ;
+ wire \la_oenb_user[3] ;
+ wire \la_oenb_user[40] ;
+ wire \la_oenb_user[41] ;
+ wire \la_oenb_user[42] ;
+ wire \la_oenb_user[43] ;
+ wire \la_oenb_user[44] ;
+ wire \la_oenb_user[45] ;
+ wire \la_oenb_user[46] ;
+ wire \la_oenb_user[47] ;
+ wire \la_oenb_user[48] ;
+ wire \la_oenb_user[49] ;
+ wire \la_oenb_user[4] ;
+ wire \la_oenb_user[50] ;
+ wire \la_oenb_user[51] ;
+ wire \la_oenb_user[52] ;
+ wire \la_oenb_user[53] ;
+ wire \la_oenb_user[54] ;
+ wire \la_oenb_user[55] ;
+ wire \la_oenb_user[56] ;
+ wire \la_oenb_user[57] ;
+ wire \la_oenb_user[58] ;
+ wire \la_oenb_user[59] ;
+ wire \la_oenb_user[5] ;
+ wire \la_oenb_user[60] ;
+ wire \la_oenb_user[61] ;
+ wire \la_oenb_user[62] ;
+ wire \la_oenb_user[63] ;
+ wire \la_oenb_user[64] ;
+ wire \la_oenb_user[65] ;
+ wire \la_oenb_user[66] ;
+ wire \la_oenb_user[67] ;
+ wire \la_oenb_user[68] ;
+ wire \la_oenb_user[69] ;
+ wire \la_oenb_user[6] ;
+ wire \la_oenb_user[70] ;
+ wire \la_oenb_user[71] ;
+ wire \la_oenb_user[72] ;
+ wire \la_oenb_user[73] ;
+ wire \la_oenb_user[74] ;
+ wire \la_oenb_user[75] ;
+ wire \la_oenb_user[76] ;
+ wire \la_oenb_user[77] ;
+ wire \la_oenb_user[78] ;
+ wire \la_oenb_user[79] ;
+ wire \la_oenb_user[7] ;
+ wire \la_oenb_user[80] ;
+ wire \la_oenb_user[81] ;
+ wire \la_oenb_user[82] ;
+ wire \la_oenb_user[83] ;
+ wire \la_oenb_user[84] ;
+ wire \la_oenb_user[85] ;
+ wire \la_oenb_user[86] ;
+ wire \la_oenb_user[87] ;
+ wire \la_oenb_user[88] ;
+ wire \la_oenb_user[89] ;
+ wire \la_oenb_user[8] ;
+ wire \la_oenb_user[90] ;
+ wire \la_oenb_user[91] ;
+ wire \la_oenb_user[92] ;
+ wire \la_oenb_user[93] ;
+ wire \la_oenb_user[94] ;
+ wire \la_oenb_user[95] ;
+ wire \la_oenb_user[96] ;
+ wire \la_oenb_user[97] ;
+ wire \la_oenb_user[98] ;
+ wire \la_oenb_user[99] ;
+ wire \la_oenb_user[9] ;
+ wire \mask_rev[0] ;
+ wire \mask_rev[10] ;
+ wire \mask_rev[11] ;
+ wire \mask_rev[12] ;
+ wire \mask_rev[13] ;
+ wire \mask_rev[14] ;
+ wire \mask_rev[15] ;
+ wire \mask_rev[16] ;
+ wire \mask_rev[17] ;
+ wire \mask_rev[18] ;
+ wire \mask_rev[19] ;
+ wire \mask_rev[1] ;
+ wire \mask_rev[20] ;
+ wire \mask_rev[21] ;
+ wire \mask_rev[22] ;
+ wire \mask_rev[23] ;
+ wire \mask_rev[24] ;
+ wire \mask_rev[25] ;
+ wire \mask_rev[26] ;
+ wire \mask_rev[27] ;
+ wire \mask_rev[28] ;
+ wire \mask_rev[29] ;
+ wire \mask_rev[2] ;
+ wire \mask_rev[30] ;
+ wire \mask_rev[31] ;
+ wire \mask_rev[3] ;
+ wire \mask_rev[4] ;
+ wire \mask_rev[5] ;
+ wire \mask_rev[6] ;
+ wire \mask_rev[7] ;
+ wire \mask_rev[8] ;
+ wire \mask_rev[9] ;
+ wire \mgmt_io_in[0] ;
+ wire \mgmt_io_in[10] ;
+ wire \mgmt_io_in[11] ;
+ wire \mgmt_io_in[12] ;
+ wire \mgmt_io_in[13] ;
+ wire \mgmt_io_in[14] ;
+ wire \mgmt_io_in[15] ;
+ wire \mgmt_io_in[16] ;
+ wire \mgmt_io_in[17] ;
+ wire \mgmt_io_in[18] ;
+ wire \mgmt_io_in[19] ;
+ wire \mgmt_io_in[1] ;
+ wire \mgmt_io_in[20] ;
+ wire \mgmt_io_in[21] ;
+ wire \mgmt_io_in[22] ;
+ wire \mgmt_io_in[23] ;
+ wire \mgmt_io_in[24] ;
+ wire \mgmt_io_in[25] ;
+ wire \mgmt_io_in[26] ;
+ wire \mgmt_io_in[27] ;
+ wire \mgmt_io_in[28] ;
+ wire \mgmt_io_in[29] ;
+ wire \mgmt_io_in[2] ;
+ wire \mgmt_io_in[30] ;
+ wire \mgmt_io_in[31] ;
+ wire \mgmt_io_in[32] ;
+ wire \mgmt_io_in[33] ;
+ wire \mgmt_io_in[34] ;
+ wire \mgmt_io_in[35] ;
+ wire \mgmt_io_in[36] ;
+ wire \mgmt_io_in[37] ;
+ wire \mgmt_io_in[3] ;
+ wire \mgmt_io_in[4] ;
+ wire \mgmt_io_in[5] ;
+ wire \mgmt_io_in[6] ;
+ wire \mgmt_io_in[7] ;
+ wire \mgmt_io_in[8] ;
+ wire \mgmt_io_in[9] ;
+ wire \mgmt_io_in_hk[0] ;
+ wire \mgmt_io_in_hk[10] ;
+ wire \mgmt_io_in_hk[11] ;
+ wire \mgmt_io_in_hk[12] ;
+ wire \mgmt_io_in_hk[13] ;
+ wire \mgmt_io_in_hk[14] ;
+ wire \mgmt_io_in_hk[15] ;
+ wire \mgmt_io_in_hk[16] ;
+ wire \mgmt_io_in_hk[17] ;
+ wire \mgmt_io_in_hk[18] ;
+ wire \mgmt_io_in_hk[19] ;
+ wire \mgmt_io_in_hk[1] ;
+ wire \mgmt_io_in_hk[20] ;
+ wire \mgmt_io_in_hk[21] ;
+ wire \mgmt_io_in_hk[22] ;
+ wire \mgmt_io_in_hk[23] ;
+ wire \mgmt_io_in_hk[24] ;
+ wire \mgmt_io_in_hk[25] ;
+ wire \mgmt_io_in_hk[26] ;
+ wire \mgmt_io_in_hk[27] ;
+ wire \mgmt_io_in_hk[28] ;
+ wire \mgmt_io_in_hk[29] ;
+ wire \mgmt_io_in_hk[2] ;
+ wire \mgmt_io_in_hk[30] ;
+ wire \mgmt_io_in_hk[31] ;
+ wire \mgmt_io_in_hk[32] ;
+ wire \mgmt_io_in_hk[33] ;
+ wire \mgmt_io_in_hk[34] ;
+ wire \mgmt_io_in_hk[35] ;
+ wire \mgmt_io_in_hk[36] ;
+ wire \mgmt_io_in_hk[37] ;
+ wire \mgmt_io_in_hk[3] ;
+ wire \mgmt_io_in_hk[4] ;
+ wire \mgmt_io_in_hk[5] ;
+ wire \mgmt_io_in_hk[6] ;
+ wire \mgmt_io_in_hk[7] ;
+ wire \mgmt_io_in_hk[8] ;
+ wire \mgmt_io_in_hk[9] ;
+ wire \mgmt_io_oeb[0] ;
+ wire \mgmt_io_oeb[10] ;
+ wire \mgmt_io_oeb[11] ;
+ wire \mgmt_io_oeb[12] ;
+ wire \mgmt_io_oeb[13] ;
+ wire \mgmt_io_oeb[14] ;
+ wire \mgmt_io_oeb[15] ;
+ wire \mgmt_io_oeb[16] ;
+ wire \mgmt_io_oeb[17] ;
+ wire \mgmt_io_oeb[18] ;
+ wire \mgmt_io_oeb[19] ;
+ wire \mgmt_io_oeb[1] ;
+ wire \mgmt_io_oeb[20] ;
+ wire \mgmt_io_oeb[21] ;
+ wire \mgmt_io_oeb[22] ;
+ wire \mgmt_io_oeb[23] ;
+ wire \mgmt_io_oeb[24] ;
+ wire \mgmt_io_oeb[25] ;
+ wire \mgmt_io_oeb[26] ;
+ wire \mgmt_io_oeb[27] ;
+ wire \mgmt_io_oeb[28] ;
+ wire \mgmt_io_oeb[29] ;
+ wire \mgmt_io_oeb[2] ;
+ wire \mgmt_io_oeb[30] ;
+ wire \mgmt_io_oeb[31] ;
+ wire \mgmt_io_oeb[32] ;
+ wire \mgmt_io_oeb[33] ;
+ wire \mgmt_io_oeb[34] ;
+ wire \mgmt_io_oeb[35] ;
+ wire \mgmt_io_oeb[36] ;
+ wire \mgmt_io_oeb[37] ;
+ wire \mgmt_io_oeb[3] ;
+ wire \mgmt_io_oeb[4] ;
+ wire \mgmt_io_oeb[5] ;
+ wire \mgmt_io_oeb[6] ;
+ wire \mgmt_io_oeb[7] ;
+ wire \mgmt_io_oeb[8] ;
+ wire \mgmt_io_oeb[9] ;
+ wire \mgmt_io_oeb_hk[0] ;
+ wire \mgmt_io_oeb_hk[10] ;
+ wire \mgmt_io_oeb_hk[11] ;
+ wire \mgmt_io_oeb_hk[12] ;
+ wire \mgmt_io_oeb_hk[13] ;
+ wire \mgmt_io_oeb_hk[14] ;
+ wire \mgmt_io_oeb_hk[15] ;
+ wire \mgmt_io_oeb_hk[16] ;
+ wire \mgmt_io_oeb_hk[17] ;
+ wire \mgmt_io_oeb_hk[18] ;
+ wire \mgmt_io_oeb_hk[19] ;
+ wire \mgmt_io_oeb_hk[1] ;
+ wire \mgmt_io_oeb_hk[20] ;
+ wire \mgmt_io_oeb_hk[21] ;
+ wire \mgmt_io_oeb_hk[22] ;
+ wire \mgmt_io_oeb_hk[23] ;
+ wire \mgmt_io_oeb_hk[24] ;
+ wire \mgmt_io_oeb_hk[25] ;
+ wire \mgmt_io_oeb_hk[26] ;
+ wire \mgmt_io_oeb_hk[27] ;
+ wire \mgmt_io_oeb_hk[28] ;
+ wire \mgmt_io_oeb_hk[29] ;
+ wire \mgmt_io_oeb_hk[2] ;
+ wire \mgmt_io_oeb_hk[30] ;
+ wire \mgmt_io_oeb_hk[31] ;
+ wire \mgmt_io_oeb_hk[32] ;
+ wire \mgmt_io_oeb_hk[33] ;
+ wire \mgmt_io_oeb_hk[34] ;
+ wire \mgmt_io_oeb_hk[35] ;
+ wire \mgmt_io_oeb_hk[36] ;
+ wire \mgmt_io_oeb_hk[37] ;
+ wire \mgmt_io_oeb_hk[3] ;
+ wire \mgmt_io_oeb_hk[4] ;
+ wire \mgmt_io_oeb_hk[5] ;
+ wire \mgmt_io_oeb_hk[6] ;
+ wire \mgmt_io_oeb_hk[7] ;
+ wire \mgmt_io_oeb_hk[8] ;
+ wire \mgmt_io_oeb_hk[9] ;
+ wire \mgmt_io_out[0] ;
+ wire \mgmt_io_out[10] ;
+ wire \mgmt_io_out[11] ;
+ wire \mgmt_io_out[12] ;
+ wire \mgmt_io_out[13] ;
+ wire \mgmt_io_out[14] ;
+ wire \mgmt_io_out[15] ;
+ wire \mgmt_io_out[16] ;
+ wire \mgmt_io_out[17] ;
+ wire \mgmt_io_out[18] ;
+ wire \mgmt_io_out[19] ;
+ wire \mgmt_io_out[1] ;
+ wire \mgmt_io_out[20] ;
+ wire \mgmt_io_out[21] ;
+ wire \mgmt_io_out[22] ;
+ wire \mgmt_io_out[23] ;
+ wire \mgmt_io_out[24] ;
+ wire \mgmt_io_out[25] ;
+ wire \mgmt_io_out[26] ;
+ wire \mgmt_io_out[27] ;
+ wire \mgmt_io_out[28] ;
+ wire \mgmt_io_out[29] ;
+ wire \mgmt_io_out[2] ;
+ wire \mgmt_io_out[30] ;
+ wire \mgmt_io_out[31] ;
+ wire \mgmt_io_out[32] ;
+ wire \mgmt_io_out[33] ;
+ wire \mgmt_io_out[34] ;
+ wire \mgmt_io_out[35] ;
+ wire \mgmt_io_out[36] ;
+ wire \mgmt_io_out[37] ;
+ wire \mgmt_io_out[3] ;
+ wire \mgmt_io_out[4] ;
+ wire \mgmt_io_out[5] ;
+ wire \mgmt_io_out[6] ;
+ wire \mgmt_io_out[7] ;
+ wire \mgmt_io_out[8] ;
+ wire \mgmt_io_out[9] ;
+ wire \mgmt_io_out_hk[0] ;
+ wire \mgmt_io_out_hk[10] ;
+ wire \mgmt_io_out_hk[11] ;
+ wire \mgmt_io_out_hk[12] ;
+ wire \mgmt_io_out_hk[13] ;
+ wire \mgmt_io_out_hk[14] ;
+ wire \mgmt_io_out_hk[15] ;
+ wire \mgmt_io_out_hk[16] ;
+ wire \mgmt_io_out_hk[17] ;
+ wire \mgmt_io_out_hk[18] ;
+ wire \mgmt_io_out_hk[19] ;
+ wire \mgmt_io_out_hk[1] ;
+ wire \mgmt_io_out_hk[20] ;
+ wire \mgmt_io_out_hk[21] ;
+ wire \mgmt_io_out_hk[22] ;
+ wire \mgmt_io_out_hk[23] ;
+ wire \mgmt_io_out_hk[24] ;
+ wire \mgmt_io_out_hk[25] ;
+ wire \mgmt_io_out_hk[26] ;
+ wire \mgmt_io_out_hk[27] ;
+ wire \mgmt_io_out_hk[28] ;
+ wire \mgmt_io_out_hk[29] ;
+ wire \mgmt_io_out_hk[2] ;
+ wire \mgmt_io_out_hk[30] ;
+ wire \mgmt_io_out_hk[31] ;
+ wire \mgmt_io_out_hk[32] ;
+ wire \mgmt_io_out_hk[33] ;
+ wire \mgmt_io_out_hk[34] ;
+ wire \mgmt_io_out_hk[35] ;
+ wire \mgmt_io_out_hk[36] ;
+ wire \mgmt_io_out_hk[37] ;
+ wire \mgmt_io_out_hk[3] ;
+ wire \mgmt_io_out_hk[4] ;
+ wire \mgmt_io_out_hk[5] ;
+ wire \mgmt_io_out_hk[6] ;
+ wire \mgmt_io_out_hk[7] ;
+ wire \mgmt_io_out_hk[8] ;
+ wire \mgmt_io_out_hk[9] ;
+ wire mprj2_vcc_pwrgood;
+ wire mprj2_vdd_pwrgood;
+ wire mprj_ack_i_core;
+ wire mprj_ack_i_user;
+ wire \mprj_adr_o_core[0] ;
+ wire \mprj_adr_o_core[10] ;
+ wire \mprj_adr_o_core[11] ;
+ wire \mprj_adr_o_core[12] ;
+ wire \mprj_adr_o_core[13] ;
+ wire \mprj_adr_o_core[14] ;
+ wire \mprj_adr_o_core[15] ;
+ wire \mprj_adr_o_core[16] ;
+ wire \mprj_adr_o_core[17] ;
+ wire \mprj_adr_o_core[18] ;
+ wire \mprj_adr_o_core[19] ;
+ wire \mprj_adr_o_core[1] ;
+ wire \mprj_adr_o_core[20] ;
+ wire \mprj_adr_o_core[21] ;
+ wire \mprj_adr_o_core[22] ;
+ wire \mprj_adr_o_core[23] ;
+ wire \mprj_adr_o_core[24] ;
+ wire \mprj_adr_o_core[25] ;
+ wire \mprj_adr_o_core[26] ;
+ wire \mprj_adr_o_core[27] ;
+ wire \mprj_adr_o_core[28] ;
+ wire \mprj_adr_o_core[29] ;
+ wire \mprj_adr_o_core[2] ;
+ wire \mprj_adr_o_core[30] ;
+ wire \mprj_adr_o_core[31] ;
+ wire \mprj_adr_o_core[3] ;
+ wire \mprj_adr_o_core[4] ;
+ wire \mprj_adr_o_core[5] ;
+ wire \mprj_adr_o_core[6] ;
+ wire \mprj_adr_o_core[7] ;
+ wire \mprj_adr_o_core[8] ;
+ wire \mprj_adr_o_core[9] ;
+ wire \mprj_adr_o_user[0] ;
+ wire \mprj_adr_o_user[10] ;
+ wire \mprj_adr_o_user[11] ;
+ wire \mprj_adr_o_user[12] ;
+ wire \mprj_adr_o_user[13] ;
+ wire \mprj_adr_o_user[14] ;
+ wire \mprj_adr_o_user[15] ;
+ wire \mprj_adr_o_user[16] ;
+ wire \mprj_adr_o_user[17] ;
+ wire \mprj_adr_o_user[18] ;
+ wire \mprj_adr_o_user[19] ;
+ wire \mprj_adr_o_user[1] ;
+ wire \mprj_adr_o_user[20] ;
+ wire \mprj_adr_o_user[21] ;
+ wire \mprj_adr_o_user[22] ;
+ wire \mprj_adr_o_user[23] ;
+ wire \mprj_adr_o_user[24] ;
+ wire \mprj_adr_o_user[25] ;
+ wire \mprj_adr_o_user[26] ;
+ wire \mprj_adr_o_user[27] ;
+ wire \mprj_adr_o_user[28] ;
+ wire \mprj_adr_o_user[29] ;
+ wire \mprj_adr_o_user[2] ;
+ wire \mprj_adr_o_user[30] ;
+ wire \mprj_adr_o_user[31] ;
+ wire \mprj_adr_o_user[3] ;
+ wire \mprj_adr_o_user[4] ;
+ wire \mprj_adr_o_user[5] ;
+ wire \mprj_adr_o_user[6] ;
+ wire \mprj_adr_o_user[7] ;
+ wire \mprj_adr_o_user[8] ;
+ wire \mprj_adr_o_user[9] ;
+ wire mprj_clock;
+ wire mprj_clock2;
+ wire mprj_cyc_o_core;
+ wire mprj_cyc_o_user;
+ wire \mprj_dat_i_core[0] ;
+ wire \mprj_dat_i_core[10] ;
+ wire \mprj_dat_i_core[11] ;
+ wire \mprj_dat_i_core[12] ;
+ wire \mprj_dat_i_core[13] ;
+ wire \mprj_dat_i_core[14] ;
+ wire \mprj_dat_i_core[15] ;
+ wire \mprj_dat_i_core[16] ;
+ wire \mprj_dat_i_core[17] ;
+ wire \mprj_dat_i_core[18] ;
+ wire \mprj_dat_i_core[19] ;
+ wire \mprj_dat_i_core[1] ;
+ wire \mprj_dat_i_core[20] ;
+ wire \mprj_dat_i_core[21] ;
+ wire \mprj_dat_i_core[22] ;
+ wire \mprj_dat_i_core[23] ;
+ wire \mprj_dat_i_core[24] ;
+ wire \mprj_dat_i_core[25] ;
+ wire \mprj_dat_i_core[26] ;
+ wire \mprj_dat_i_core[27] ;
+ wire \mprj_dat_i_core[28] ;
+ wire \mprj_dat_i_core[29] ;
+ wire \mprj_dat_i_core[2] ;
+ wire \mprj_dat_i_core[30] ;
+ wire \mprj_dat_i_core[31] ;
+ wire \mprj_dat_i_core[3] ;
+ wire \mprj_dat_i_core[4] ;
+ wire \mprj_dat_i_core[5] ;
+ wire \mprj_dat_i_core[6] ;
+ wire \mprj_dat_i_core[7] ;
+ wire \mprj_dat_i_core[8] ;
+ wire \mprj_dat_i_core[9] ;
+ wire \mprj_dat_i_user[0] ;
+ wire \mprj_dat_i_user[10] ;
+ wire \mprj_dat_i_user[11] ;
+ wire \mprj_dat_i_user[12] ;
+ wire \mprj_dat_i_user[13] ;
+ wire \mprj_dat_i_user[14] ;
+ wire \mprj_dat_i_user[15] ;
+ wire \mprj_dat_i_user[16] ;
+ wire \mprj_dat_i_user[17] ;
+ wire \mprj_dat_i_user[18] ;
+ wire \mprj_dat_i_user[19] ;
+ wire \mprj_dat_i_user[1] ;
+ wire \mprj_dat_i_user[20] ;
+ wire \mprj_dat_i_user[21] ;
+ wire \mprj_dat_i_user[22] ;
+ wire \mprj_dat_i_user[23] ;
+ wire \mprj_dat_i_user[24] ;
+ wire \mprj_dat_i_user[25] ;
+ wire \mprj_dat_i_user[26] ;
+ wire \mprj_dat_i_user[27] ;
+ wire \mprj_dat_i_user[28] ;
+ wire \mprj_dat_i_user[29] ;
+ wire \mprj_dat_i_user[2] ;
+ wire \mprj_dat_i_user[30] ;
+ wire \mprj_dat_i_user[31] ;
+ wire \mprj_dat_i_user[3] ;
+ wire \mprj_dat_i_user[4] ;
+ wire \mprj_dat_i_user[5] ;
+ wire \mprj_dat_i_user[6] ;
+ wire \mprj_dat_i_user[7] ;
+ wire \mprj_dat_i_user[8] ;
+ wire \mprj_dat_i_user[9] ;
+ wire \mprj_dat_o_core[0] ;
+ wire \mprj_dat_o_core[10] ;
+ wire \mprj_dat_o_core[11] ;
+ wire \mprj_dat_o_core[12] ;
+ wire \mprj_dat_o_core[13] ;
+ wire \mprj_dat_o_core[14] ;
+ wire \mprj_dat_o_core[15] ;
+ wire \mprj_dat_o_core[16] ;
+ wire \mprj_dat_o_core[17] ;
+ wire \mprj_dat_o_core[18] ;
+ wire \mprj_dat_o_core[19] ;
+ wire \mprj_dat_o_core[1] ;
+ wire \mprj_dat_o_core[20] ;
+ wire \mprj_dat_o_core[21] ;
+ wire \mprj_dat_o_core[22] ;
+ wire \mprj_dat_o_core[23] ;
+ wire \mprj_dat_o_core[24] ;
+ wire \mprj_dat_o_core[25] ;
+ wire \mprj_dat_o_core[26] ;
+ wire \mprj_dat_o_core[27] ;
+ wire \mprj_dat_o_core[28] ;
+ wire \mprj_dat_o_core[29] ;
+ wire \mprj_dat_o_core[2] ;
+ wire \mprj_dat_o_core[30] ;
+ wire \mprj_dat_o_core[31] ;
+ wire \mprj_dat_o_core[3] ;
+ wire \mprj_dat_o_core[4] ;
+ wire \mprj_dat_o_core[5] ;
+ wire \mprj_dat_o_core[6] ;
+ wire \mprj_dat_o_core[7] ;
+ wire \mprj_dat_o_core[8] ;
+ wire \mprj_dat_o_core[9] ;
+ wire \mprj_dat_o_user[0] ;
+ wire \mprj_dat_o_user[10] ;
+ wire \mprj_dat_o_user[11] ;
+ wire \mprj_dat_o_user[12] ;
+ wire \mprj_dat_o_user[13] ;
+ wire \mprj_dat_o_user[14] ;
+ wire \mprj_dat_o_user[15] ;
+ wire \mprj_dat_o_user[16] ;
+ wire \mprj_dat_o_user[17] ;
+ wire \mprj_dat_o_user[18] ;
+ wire \mprj_dat_o_user[19] ;
+ wire \mprj_dat_o_user[1] ;
+ wire \mprj_dat_o_user[20] ;
+ wire \mprj_dat_o_user[21] ;
+ wire \mprj_dat_o_user[22] ;
+ wire \mprj_dat_o_user[23] ;
+ wire \mprj_dat_o_user[24] ;
+ wire \mprj_dat_o_user[25] ;
+ wire \mprj_dat_o_user[26] ;
+ wire \mprj_dat_o_user[27] ;
+ wire \mprj_dat_o_user[28] ;
+ wire \mprj_dat_o_user[29] ;
+ wire \mprj_dat_o_user[2] ;
+ wire \mprj_dat_o_user[30] ;
+ wire \mprj_dat_o_user[31] ;
+ wire \mprj_dat_o_user[3] ;
+ wire \mprj_dat_o_user[4] ;
+ wire \mprj_dat_o_user[5] ;
+ wire \mprj_dat_o_user[6] ;
+ wire \mprj_dat_o_user[7] ;
+ wire \mprj_dat_o_user[8] ;
+ wire \mprj_dat_o_user[9] ;
+ wire mprj_iena_wb;
+ inout [37:0] mprj_io;
+ wire \mprj_io_analog_en[0] ;
+ wire \mprj_io_analog_en[10] ;
+ wire \mprj_io_analog_en[11] ;
+ wire \mprj_io_analog_en[12] ;
+ wire \mprj_io_analog_en[13] ;
+ wire \mprj_io_analog_en[14] ;
+ wire \mprj_io_analog_en[15] ;
+ wire \mprj_io_analog_en[16] ;
+ wire \mprj_io_analog_en[17] ;
+ wire \mprj_io_analog_en[18] ;
+ wire \mprj_io_analog_en[19] ;
+ wire \mprj_io_analog_en[1] ;
+ wire \mprj_io_analog_en[20] ;
+ wire \mprj_io_analog_en[21] ;
+ wire \mprj_io_analog_en[22] ;
+ wire \mprj_io_analog_en[23] ;
+ wire \mprj_io_analog_en[24] ;
+ wire \mprj_io_analog_en[25] ;
+ wire \mprj_io_analog_en[26] ;
+ wire \mprj_io_analog_en[27] ;
+ wire \mprj_io_analog_en[28] ;
+ wire \mprj_io_analog_en[29] ;
+ wire \mprj_io_analog_en[2] ;
+ wire \mprj_io_analog_en[30] ;
+ wire \mprj_io_analog_en[31] ;
+ wire \mprj_io_analog_en[32] ;
+ wire \mprj_io_analog_en[33] ;
+ wire \mprj_io_analog_en[34] ;
+ wire \mprj_io_analog_en[35] ;
+ wire \mprj_io_analog_en[36] ;
+ wire \mprj_io_analog_en[37] ;
+ wire \mprj_io_analog_en[3] ;
+ wire \mprj_io_analog_en[4] ;
+ wire \mprj_io_analog_en[5] ;
+ wire \mprj_io_analog_en[6] ;
+ wire \mprj_io_analog_en[7] ;
+ wire \mprj_io_analog_en[8] ;
+ wire \mprj_io_analog_en[9] ;
+ wire \mprj_io_analog_pol[0] ;
+ wire \mprj_io_analog_pol[10] ;
+ wire \mprj_io_analog_pol[11] ;
+ wire \mprj_io_analog_pol[12] ;
+ wire \mprj_io_analog_pol[13] ;
+ wire \mprj_io_analog_pol[14] ;
+ wire \mprj_io_analog_pol[15] ;
+ wire \mprj_io_analog_pol[16] ;
+ wire \mprj_io_analog_pol[17] ;
+ wire \mprj_io_analog_pol[18] ;
+ wire \mprj_io_analog_pol[19] ;
+ wire \mprj_io_analog_pol[1] ;
+ wire \mprj_io_analog_pol[20] ;
+ wire \mprj_io_analog_pol[21] ;
+ wire \mprj_io_analog_pol[22] ;
+ wire \mprj_io_analog_pol[23] ;
+ wire \mprj_io_analog_pol[24] ;
+ wire \mprj_io_analog_pol[25] ;
+ wire \mprj_io_analog_pol[26] ;
+ wire \mprj_io_analog_pol[27] ;
+ wire \mprj_io_analog_pol[28] ;
+ wire \mprj_io_analog_pol[29] ;
+ wire \mprj_io_analog_pol[2] ;
+ wire \mprj_io_analog_pol[30] ;
+ wire \mprj_io_analog_pol[31] ;
+ wire \mprj_io_analog_pol[32] ;
+ wire \mprj_io_analog_pol[33] ;
+ wire \mprj_io_analog_pol[34] ;
+ wire \mprj_io_analog_pol[35] ;
+ wire \mprj_io_analog_pol[36] ;
+ wire \mprj_io_analog_pol[37] ;
+ wire \mprj_io_analog_pol[3] ;
+ wire \mprj_io_analog_pol[4] ;
+ wire \mprj_io_analog_pol[5] ;
+ wire \mprj_io_analog_pol[6] ;
+ wire \mprj_io_analog_pol[7] ;
+ wire \mprj_io_analog_pol[8] ;
+ wire \mprj_io_analog_pol[9] ;
+ wire \mprj_io_analog_sel[0] ;
+ wire \mprj_io_analog_sel[10] ;
+ wire \mprj_io_analog_sel[11] ;
+ wire \mprj_io_analog_sel[12] ;
+ wire \mprj_io_analog_sel[13] ;
+ wire \mprj_io_analog_sel[14] ;
+ wire \mprj_io_analog_sel[15] ;
+ wire \mprj_io_analog_sel[16] ;
+ wire \mprj_io_analog_sel[17] ;
+ wire \mprj_io_analog_sel[18] ;
+ wire \mprj_io_analog_sel[19] ;
+ wire \mprj_io_analog_sel[1] ;
+ wire \mprj_io_analog_sel[20] ;
+ wire \mprj_io_analog_sel[21] ;
+ wire \mprj_io_analog_sel[22] ;
+ wire \mprj_io_analog_sel[23] ;
+ wire \mprj_io_analog_sel[24] ;
+ wire \mprj_io_analog_sel[25] ;
+ wire \mprj_io_analog_sel[26] ;
+ wire \mprj_io_analog_sel[27] ;
+ wire \mprj_io_analog_sel[28] ;
+ wire \mprj_io_analog_sel[29] ;
+ wire \mprj_io_analog_sel[2] ;
+ wire \mprj_io_analog_sel[30] ;
+ wire \mprj_io_analog_sel[31] ;
+ wire \mprj_io_analog_sel[32] ;
+ wire \mprj_io_analog_sel[33] ;
+ wire \mprj_io_analog_sel[34] ;
+ wire \mprj_io_analog_sel[35] ;
+ wire \mprj_io_analog_sel[36] ;
+ wire \mprj_io_analog_sel[37] ;
+ wire \mprj_io_analog_sel[3] ;
+ wire \mprj_io_analog_sel[4] ;
+ wire \mprj_io_analog_sel[5] ;
+ wire \mprj_io_analog_sel[6] ;
+ wire \mprj_io_analog_sel[7] ;
+ wire \mprj_io_analog_sel[8] ;
+ wire \mprj_io_analog_sel[9] ;
+ wire \mprj_io_dm[0] ;
+ wire \mprj_io_dm[100] ;
+ wire \mprj_io_dm[101] ;
+ wire \mprj_io_dm[102] ;
+ wire \mprj_io_dm[103] ;
+ wire \mprj_io_dm[104] ;
+ wire \mprj_io_dm[105] ;
+ wire \mprj_io_dm[106] ;
+ wire \mprj_io_dm[107] ;
+ wire \mprj_io_dm[108] ;
+ wire \mprj_io_dm[109] ;
+ wire \mprj_io_dm[10] ;
+ wire \mprj_io_dm[110] ;
+ wire \mprj_io_dm[111] ;
+ wire \mprj_io_dm[112] ;
+ wire \mprj_io_dm[113] ;
+ wire \mprj_io_dm[11] ;
+ wire \mprj_io_dm[12] ;
+ wire \mprj_io_dm[13] ;
+ wire \mprj_io_dm[14] ;
+ wire \mprj_io_dm[15] ;
+ wire \mprj_io_dm[16] ;
+ wire \mprj_io_dm[17] ;
+ wire \mprj_io_dm[18] ;
+ wire \mprj_io_dm[19] ;
+ wire \mprj_io_dm[1] ;
+ wire \mprj_io_dm[20] ;
+ wire \mprj_io_dm[21] ;
+ wire \mprj_io_dm[22] ;
+ wire \mprj_io_dm[23] ;
+ wire \mprj_io_dm[24] ;
+ wire \mprj_io_dm[25] ;
+ wire \mprj_io_dm[26] ;
+ wire \mprj_io_dm[27] ;
+ wire \mprj_io_dm[28] ;
+ wire \mprj_io_dm[29] ;
+ wire \mprj_io_dm[2] ;
+ wire \mprj_io_dm[30] ;
+ wire \mprj_io_dm[31] ;
+ wire \mprj_io_dm[32] ;
+ wire \mprj_io_dm[33] ;
+ wire \mprj_io_dm[34] ;
+ wire \mprj_io_dm[35] ;
+ wire \mprj_io_dm[36] ;
+ wire \mprj_io_dm[37] ;
+ wire \mprj_io_dm[38] ;
+ wire \mprj_io_dm[39] ;
+ wire \mprj_io_dm[3] ;
+ wire \mprj_io_dm[40] ;
+ wire \mprj_io_dm[41] ;
+ wire \mprj_io_dm[42] ;
+ wire \mprj_io_dm[43] ;
+ wire \mprj_io_dm[44] ;
+ wire \mprj_io_dm[45] ;
+ wire \mprj_io_dm[46] ;
+ wire \mprj_io_dm[47] ;
+ wire \mprj_io_dm[48] ;
+ wire \mprj_io_dm[49] ;
+ wire \mprj_io_dm[4] ;
+ wire \mprj_io_dm[50] ;
+ wire \mprj_io_dm[51] ;
+ wire \mprj_io_dm[52] ;
+ wire \mprj_io_dm[53] ;
+ wire \mprj_io_dm[54] ;
+ wire \mprj_io_dm[55] ;
+ wire \mprj_io_dm[56] ;
+ wire \mprj_io_dm[57] ;
+ wire \mprj_io_dm[58] ;
+ wire \mprj_io_dm[59] ;
+ wire \mprj_io_dm[5] ;
+ wire \mprj_io_dm[60] ;
+ wire \mprj_io_dm[61] ;
+ wire \mprj_io_dm[62] ;
+ wire \mprj_io_dm[63] ;
+ wire \mprj_io_dm[64] ;
+ wire \mprj_io_dm[65] ;
+ wire \mprj_io_dm[66] ;
+ wire \mprj_io_dm[67] ;
+ wire \mprj_io_dm[68] ;
+ wire \mprj_io_dm[69] ;
+ wire \mprj_io_dm[6] ;
+ wire \mprj_io_dm[70] ;
+ wire \mprj_io_dm[71] ;
+ wire \mprj_io_dm[72] ;
+ wire \mprj_io_dm[73] ;
+ wire \mprj_io_dm[74] ;
+ wire \mprj_io_dm[75] ;
+ wire \mprj_io_dm[76] ;
+ wire \mprj_io_dm[77] ;
+ wire \mprj_io_dm[78] ;
+ wire \mprj_io_dm[79] ;
+ wire \mprj_io_dm[7] ;
+ wire \mprj_io_dm[80] ;
+ wire \mprj_io_dm[81] ;
+ wire \mprj_io_dm[82] ;
+ wire \mprj_io_dm[83] ;
+ wire \mprj_io_dm[84] ;
+ wire \mprj_io_dm[85] ;
+ wire \mprj_io_dm[86] ;
+ wire \mprj_io_dm[87] ;
+ wire \mprj_io_dm[88] ;
+ wire \mprj_io_dm[89] ;
+ wire \mprj_io_dm[8] ;
+ wire \mprj_io_dm[90] ;
+ wire \mprj_io_dm[91] ;
+ wire \mprj_io_dm[92] ;
+ wire \mprj_io_dm[93] ;
+ wire \mprj_io_dm[94] ;
+ wire \mprj_io_dm[95] ;
+ wire \mprj_io_dm[96] ;
+ wire \mprj_io_dm[97] ;
+ wire \mprj_io_dm[98] ;
+ wire \mprj_io_dm[99] ;
+ wire \mprj_io_dm[9] ;
+ wire \mprj_io_holdover[0] ;
+ wire \mprj_io_holdover[10] ;
+ wire \mprj_io_holdover[11] ;
+ wire \mprj_io_holdover[12] ;
+ wire \mprj_io_holdover[13] ;
+ wire \mprj_io_holdover[14] ;
+ wire \mprj_io_holdover[15] ;
+ wire \mprj_io_holdover[16] ;
+ wire \mprj_io_holdover[17] ;
+ wire \mprj_io_holdover[18] ;
+ wire \mprj_io_holdover[19] ;
+ wire \mprj_io_holdover[1] ;
+ wire \mprj_io_holdover[20] ;
+ wire \mprj_io_holdover[21] ;
+ wire \mprj_io_holdover[22] ;
+ wire \mprj_io_holdover[23] ;
+ wire \mprj_io_holdover[24] ;
+ wire \mprj_io_holdover[25] ;
+ wire \mprj_io_holdover[26] ;
+ wire \mprj_io_holdover[27] ;
+ wire \mprj_io_holdover[28] ;
+ wire \mprj_io_holdover[29] ;
+ wire \mprj_io_holdover[2] ;
+ wire \mprj_io_holdover[30] ;
+ wire \mprj_io_holdover[31] ;
+ wire \mprj_io_holdover[32] ;
+ wire \mprj_io_holdover[33] ;
+ wire \mprj_io_holdover[34] ;
+ wire \mprj_io_holdover[35] ;
+ wire \mprj_io_holdover[36] ;
+ wire \mprj_io_holdover[37] ;
+ wire \mprj_io_holdover[3] ;
+ wire \mprj_io_holdover[4] ;
+ wire \mprj_io_holdover[5] ;
+ wire \mprj_io_holdover[6] ;
+ wire \mprj_io_holdover[7] ;
+ wire \mprj_io_holdover[8] ;
+ wire \mprj_io_holdover[9] ;
+ wire \mprj_io_ib_mode_sel[0] ;
+ wire \mprj_io_ib_mode_sel[10] ;
+ wire \mprj_io_ib_mode_sel[11] ;
+ wire \mprj_io_ib_mode_sel[12] ;
+ wire \mprj_io_ib_mode_sel[13] ;
+ wire \mprj_io_ib_mode_sel[14] ;
+ wire \mprj_io_ib_mode_sel[15] ;
+ wire \mprj_io_ib_mode_sel[16] ;
+ wire \mprj_io_ib_mode_sel[17] ;
+ wire \mprj_io_ib_mode_sel[18] ;
+ wire \mprj_io_ib_mode_sel[19] ;
+ wire \mprj_io_ib_mode_sel[1] ;
+ wire \mprj_io_ib_mode_sel[20] ;
+ wire \mprj_io_ib_mode_sel[21] ;
+ wire \mprj_io_ib_mode_sel[22] ;
+ wire \mprj_io_ib_mode_sel[23] ;
+ wire \mprj_io_ib_mode_sel[24] ;
+ wire \mprj_io_ib_mode_sel[25] ;
+ wire \mprj_io_ib_mode_sel[26] ;
+ wire \mprj_io_ib_mode_sel[27] ;
+ wire \mprj_io_ib_mode_sel[28] ;
+ wire \mprj_io_ib_mode_sel[29] ;
+ wire \mprj_io_ib_mode_sel[2] ;
+ wire \mprj_io_ib_mode_sel[30] ;
+ wire \mprj_io_ib_mode_sel[31] ;
+ wire \mprj_io_ib_mode_sel[32] ;
+ wire \mprj_io_ib_mode_sel[33] ;
+ wire \mprj_io_ib_mode_sel[34] ;
+ wire \mprj_io_ib_mode_sel[35] ;
+ wire \mprj_io_ib_mode_sel[36] ;
+ wire \mprj_io_ib_mode_sel[37] ;
+ wire \mprj_io_ib_mode_sel[3] ;
+ wire \mprj_io_ib_mode_sel[4] ;
+ wire \mprj_io_ib_mode_sel[5] ;
+ wire \mprj_io_ib_mode_sel[6] ;
+ wire \mprj_io_ib_mode_sel[7] ;
+ wire \mprj_io_ib_mode_sel[8] ;
+ wire \mprj_io_ib_mode_sel[9] ;
+ wire \mprj_io_in[0] ;
+ wire \mprj_io_in[10] ;
+ wire \mprj_io_in[11] ;
+ wire \mprj_io_in[12] ;
+ wire \mprj_io_in[13] ;
+ wire \mprj_io_in[14] ;
+ wire \mprj_io_in[15] ;
+ wire \mprj_io_in[16] ;
+ wire \mprj_io_in[17] ;
+ wire \mprj_io_in[18] ;
+ wire \mprj_io_in[19] ;
+ wire \mprj_io_in[1] ;
+ wire \mprj_io_in[20] ;
+ wire \mprj_io_in[21] ;
+ wire \mprj_io_in[22] ;
+ wire \mprj_io_in[23] ;
+ wire \mprj_io_in[24] ;
+ wire \mprj_io_in[25] ;
+ wire \mprj_io_in[26] ;
+ wire \mprj_io_in[27] ;
+ wire \mprj_io_in[28] ;
+ wire \mprj_io_in[29] ;
+ wire \mprj_io_in[2] ;
+ wire \mprj_io_in[30] ;
+ wire \mprj_io_in[31] ;
+ wire \mprj_io_in[32] ;
+ wire \mprj_io_in[33] ;
+ wire \mprj_io_in[34] ;
+ wire \mprj_io_in[35] ;
+ wire \mprj_io_in[36] ;
+ wire \mprj_io_in[37] ;
+ wire \mprj_io_in[3] ;
+ wire \mprj_io_in[4] ;
+ wire \mprj_io_in[5] ;
+ wire \mprj_io_in[6] ;
+ wire \mprj_io_in[7] ;
+ wire \mprj_io_in[8] ;
+ wire \mprj_io_in[9] ;
+ wire \mprj_io_inp_dis[0] ;
+ wire \mprj_io_inp_dis[10] ;
+ wire \mprj_io_inp_dis[11] ;
+ wire \mprj_io_inp_dis[12] ;
+ wire \mprj_io_inp_dis[13] ;
+ wire \mprj_io_inp_dis[14] ;
+ wire \mprj_io_inp_dis[15] ;
+ wire \mprj_io_inp_dis[16] ;
+ wire \mprj_io_inp_dis[17] ;
+ wire \mprj_io_inp_dis[18] ;
+ wire \mprj_io_inp_dis[19] ;
+ wire \mprj_io_inp_dis[1] ;
+ wire \mprj_io_inp_dis[20] ;
+ wire \mprj_io_inp_dis[21] ;
+ wire \mprj_io_inp_dis[22] ;
+ wire \mprj_io_inp_dis[23] ;
+ wire \mprj_io_inp_dis[24] ;
+ wire \mprj_io_inp_dis[25] ;
+ wire \mprj_io_inp_dis[26] ;
+ wire \mprj_io_inp_dis[27] ;
+ wire \mprj_io_inp_dis[28] ;
+ wire \mprj_io_inp_dis[29] ;
+ wire \mprj_io_inp_dis[2] ;
+ wire \mprj_io_inp_dis[30] ;
+ wire \mprj_io_inp_dis[31] ;
+ wire \mprj_io_inp_dis[32] ;
+ wire \mprj_io_inp_dis[33] ;
+ wire \mprj_io_inp_dis[34] ;
+ wire \mprj_io_inp_dis[35] ;
+ wire \mprj_io_inp_dis[36] ;
+ wire \mprj_io_inp_dis[37] ;
+ wire \mprj_io_inp_dis[3] ;
+ wire \mprj_io_inp_dis[4] ;
+ wire \mprj_io_inp_dis[5] ;
+ wire \mprj_io_inp_dis[6] ;
+ wire \mprj_io_inp_dis[7] ;
+ wire \mprj_io_inp_dis[8] ;
+ wire \mprj_io_inp_dis[9] ;
+ wire mprj_io_loader_clock;
+ wire mprj_io_loader_clock_buf;
+ wire mprj_io_loader_data_1;
+ wire mprj_io_loader_data_2;
+ wire mprj_io_loader_data_2_buf;
+ wire mprj_io_loader_resetn;
+ wire mprj_io_loader_resetn_buf;
+ wire mprj_io_loader_strobe;
+ wire mprj_io_loader_strobe_buf;
+ wire \mprj_io_oeb[0] ;
+ wire \mprj_io_oeb[10] ;
+ wire \mprj_io_oeb[11] ;
+ wire \mprj_io_oeb[12] ;
+ wire \mprj_io_oeb[13] ;
+ wire \mprj_io_oeb[14] ;
+ wire \mprj_io_oeb[15] ;
+ wire \mprj_io_oeb[16] ;
+ wire \mprj_io_oeb[17] ;
+ wire \mprj_io_oeb[18] ;
+ wire \mprj_io_oeb[19] ;
+ wire \mprj_io_oeb[1] ;
+ wire \mprj_io_oeb[20] ;
+ wire \mprj_io_oeb[21] ;
+ wire \mprj_io_oeb[22] ;
+ wire \mprj_io_oeb[23] ;
+ wire \mprj_io_oeb[24] ;
+ wire \mprj_io_oeb[25] ;
+ wire \mprj_io_oeb[26] ;
+ wire \mprj_io_oeb[27] ;
+ wire \mprj_io_oeb[28] ;
+ wire \mprj_io_oeb[29] ;
+ wire \mprj_io_oeb[2] ;
+ wire \mprj_io_oeb[30] ;
+ wire \mprj_io_oeb[31] ;
+ wire \mprj_io_oeb[32] ;
+ wire \mprj_io_oeb[33] ;
+ wire \mprj_io_oeb[34] ;
+ wire \mprj_io_oeb[35] ;
+ wire \mprj_io_oeb[36] ;
+ wire \mprj_io_oeb[37] ;
+ wire \mprj_io_oeb[3] ;
+ wire \mprj_io_oeb[4] ;
+ wire \mprj_io_oeb[5] ;
+ wire \mprj_io_oeb[6] ;
+ wire \mprj_io_oeb[7] ;
+ wire \mprj_io_oeb[8] ;
+ wire \mprj_io_oeb[9] ;
+ wire \mprj_io_one[0] ;
+ wire \mprj_io_one[10] ;
+ wire \mprj_io_one[11] ;
+ wire \mprj_io_one[12] ;
+ wire \mprj_io_one[13] ;
+ wire \mprj_io_one[14] ;
+ wire \mprj_io_one[15] ;
+ wire \mprj_io_one[16] ;
+ wire \mprj_io_one[17] ;
+ wire \mprj_io_one[18] ;
+ wire \mprj_io_one[19] ;
+ wire \mprj_io_one[1] ;
+ wire \mprj_io_one[20] ;
+ wire \mprj_io_one[21] ;
+ wire \mprj_io_one[22] ;
+ wire \mprj_io_one[23] ;
+ wire \mprj_io_one[24] ;
+ wire \mprj_io_one[25] ;
+ wire \mprj_io_one[26] ;
+ wire \mprj_io_one[27] ;
+ wire \mprj_io_one[28] ;
+ wire \mprj_io_one[29] ;
+ wire \mprj_io_one[2] ;
+ wire \mprj_io_one[30] ;
+ wire \mprj_io_one[31] ;
+ wire \mprj_io_one[32] ;
+ wire \mprj_io_one[33] ;
+ wire \mprj_io_one[34] ;
+ wire \mprj_io_one[35] ;
+ wire \mprj_io_one[36] ;
+ wire \mprj_io_one[37] ;
+ wire \mprj_io_one[3] ;
+ wire \mprj_io_one[4] ;
+ wire \mprj_io_one[5] ;
+ wire \mprj_io_one[6] ;
+ wire \mprj_io_one[7] ;
+ wire \mprj_io_one[8] ;
+ wire \mprj_io_one[9] ;
+ wire \mprj_io_out[0] ;
+ wire \mprj_io_out[10] ;
+ wire \mprj_io_out[11] ;
+ wire \mprj_io_out[12] ;
+ wire \mprj_io_out[13] ;
+ wire \mprj_io_out[14] ;
+ wire \mprj_io_out[15] ;
+ wire \mprj_io_out[16] ;
+ wire \mprj_io_out[17] ;
+ wire \mprj_io_out[18] ;
+ wire \mprj_io_out[19] ;
+ wire \mprj_io_out[1] ;
+ wire \mprj_io_out[20] ;
+ wire \mprj_io_out[21] ;
+ wire \mprj_io_out[22] ;
+ wire \mprj_io_out[23] ;
+ wire \mprj_io_out[24] ;
+ wire \mprj_io_out[25] ;
+ wire \mprj_io_out[26] ;
+ wire \mprj_io_out[27] ;
+ wire \mprj_io_out[28] ;
+ wire \mprj_io_out[29] ;
+ wire \mprj_io_out[2] ;
+ wire \mprj_io_out[30] ;
+ wire \mprj_io_out[31] ;
+ wire \mprj_io_out[32] ;
+ wire \mprj_io_out[33] ;
+ wire \mprj_io_out[34] ;
+ wire \mprj_io_out[35] ;
+ wire \mprj_io_out[36] ;
+ wire \mprj_io_out[37] ;
+ wire \mprj_io_out[3] ;
+ wire \mprj_io_out[4] ;
+ wire \mprj_io_out[5] ;
+ wire \mprj_io_out[6] ;
+ wire \mprj_io_out[7] ;
+ wire \mprj_io_out[8] ;
+ wire \mprj_io_out[9] ;
+ wire \mprj_io_slow_sel[0] ;
+ wire \mprj_io_slow_sel[10] ;
+ wire \mprj_io_slow_sel[11] ;
+ wire \mprj_io_slow_sel[12] ;
+ wire \mprj_io_slow_sel[13] ;
+ wire \mprj_io_slow_sel[14] ;
+ wire \mprj_io_slow_sel[15] ;
+ wire \mprj_io_slow_sel[16] ;
+ wire \mprj_io_slow_sel[17] ;
+ wire \mprj_io_slow_sel[18] ;
+ wire \mprj_io_slow_sel[19] ;
+ wire \mprj_io_slow_sel[1] ;
+ wire \mprj_io_slow_sel[20] ;
+ wire \mprj_io_slow_sel[21] ;
+ wire \mprj_io_slow_sel[22] ;
+ wire \mprj_io_slow_sel[23] ;
+ wire \mprj_io_slow_sel[24] ;
+ wire \mprj_io_slow_sel[25] ;
+ wire \mprj_io_slow_sel[26] ;
+ wire \mprj_io_slow_sel[27] ;
+ wire \mprj_io_slow_sel[28] ;
+ wire \mprj_io_slow_sel[29] ;
+ wire \mprj_io_slow_sel[2] ;
+ wire \mprj_io_slow_sel[30] ;
+ wire \mprj_io_slow_sel[31] ;
+ wire \mprj_io_slow_sel[32] ;
+ wire \mprj_io_slow_sel[33] ;
+ wire \mprj_io_slow_sel[34] ;
+ wire \mprj_io_slow_sel[35] ;
+ wire \mprj_io_slow_sel[36] ;
+ wire \mprj_io_slow_sel[37] ;
+ wire \mprj_io_slow_sel[3] ;
+ wire \mprj_io_slow_sel[4] ;
+ wire \mprj_io_slow_sel[5] ;
+ wire \mprj_io_slow_sel[6] ;
+ wire \mprj_io_slow_sel[7] ;
+ wire \mprj_io_slow_sel[8] ;
+ wire \mprj_io_slow_sel[9] ;
+ wire \mprj_io_vtrip_sel[0] ;
+ wire \mprj_io_vtrip_sel[10] ;
+ wire \mprj_io_vtrip_sel[11] ;
+ wire \mprj_io_vtrip_sel[12] ;
+ wire \mprj_io_vtrip_sel[13] ;
+ wire \mprj_io_vtrip_sel[14] ;
+ wire \mprj_io_vtrip_sel[15] ;
+ wire \mprj_io_vtrip_sel[16] ;
+ wire \mprj_io_vtrip_sel[17] ;
+ wire \mprj_io_vtrip_sel[18] ;
+ wire \mprj_io_vtrip_sel[19] ;
+ wire \mprj_io_vtrip_sel[1] ;
+ wire \mprj_io_vtrip_sel[20] ;
+ wire \mprj_io_vtrip_sel[21] ;
+ wire \mprj_io_vtrip_sel[22] ;
+ wire \mprj_io_vtrip_sel[23] ;
+ wire \mprj_io_vtrip_sel[24] ;
+ wire \mprj_io_vtrip_sel[25] ;
+ wire \mprj_io_vtrip_sel[26] ;
+ wire \mprj_io_vtrip_sel[27] ;
+ wire \mprj_io_vtrip_sel[28] ;
+ wire \mprj_io_vtrip_sel[29] ;
+ wire \mprj_io_vtrip_sel[2] ;
+ wire \mprj_io_vtrip_sel[30] ;
+ wire \mprj_io_vtrip_sel[31] ;
+ wire \mprj_io_vtrip_sel[32] ;
+ wire \mprj_io_vtrip_sel[33] ;
+ wire \mprj_io_vtrip_sel[34] ;
+ wire \mprj_io_vtrip_sel[35] ;
+ wire \mprj_io_vtrip_sel[36] ;
+ wire \mprj_io_vtrip_sel[37] ;
+ wire \mprj_io_vtrip_sel[3] ;
+ wire \mprj_io_vtrip_sel[4] ;
+ wire \mprj_io_vtrip_sel[5] ;
+ wire \mprj_io_vtrip_sel[6] ;
+ wire \mprj_io_vtrip_sel[7] ;
+ wire \mprj_io_vtrip_sel[8] ;
+ wire \mprj_io_vtrip_sel[9] ;
+ wire mprj_reset;
+ wire \mprj_sel_o_core[0] ;
+ wire \mprj_sel_o_core[1] ;
+ wire \mprj_sel_o_core[2] ;
+ wire \mprj_sel_o_core[3] ;
+ wire \mprj_sel_o_user[0] ;
+ wire \mprj_sel_o_user[1] ;
+ wire \mprj_sel_o_user[2] ;
+ wire \mprj_sel_o_user[3] ;
+ wire mprj_stb_o_core;
+ wire mprj_stb_o_user;
+ wire mprj_vcc_pwrgood;
+ wire mprj_vdd_pwrgood;
+ wire mprj_we_o_core;
+ wire mprj_we_o_user;
+ wire pll_clk;
+ wire pll_clk90;
+ wire por_l;
+ wire por_l_buf;
+ wire porb_h;
+ wire porb_h_buf;
+ wire porb_h_in_nc;
+ wire porb_h_out_nc;
+ wire porb_l;
+ wire \pwr_ctrl_nc[0] ;
+ wire \pwr_ctrl_nc[1] ;
+ wire \pwr_ctrl_nc[2] ;
+ wire \pwr_ctrl_nc[3] ;
+ wire qspi_enabled;
+ input resetb;
+ wire resetn_passthru;
+ wire rstb_h;
+ wire rstb_l;
+ wire rstb_l_buf;
+ wire ser_rx;
+ wire ser_tx;
+ wire \spare_xfq_nc[0] ;
+ wire \spare_xfq_nc[1] ;
+ wire \spare_xfq_nc[2] ;
+ wire \spare_xfq_nc[3] ;
+ wire \spare_xfq_nc[4] ;
+ wire \spare_xfq_nc[5] ;
+ wire \spare_xfq_nc[6] ;
+ wire \spare_xfq_nc[7] ;
+ wire \spare_xfqn_nc[0] ;
+ wire \spare_xfqn_nc[1] ;
+ wire \spare_xfqn_nc[2] ;
+ wire \spare_xfqn_nc[3] ;
+ wire \spare_xfqn_nc[4] ;
+ wire \spare_xfqn_nc[5] ;
+ wire \spare_xfqn_nc[6] ;
+ wire \spare_xfqn_nc[7] ;
+ wire \spare_xi_nc[0] ;
+ wire \spare_xi_nc[10] ;
+ wire \spare_xi_nc[11] ;
+ wire \spare_xi_nc[12] ;
+ wire \spare_xi_nc[13] ;
+ wire \spare_xi_nc[14] ;
+ wire \spare_xi_nc[15] ;
+ wire \spare_xi_nc[1] ;
+ wire \spare_xi_nc[2] ;
+ wire \spare_xi_nc[3] ;
+ wire \spare_xi_nc[4] ;
+ wire \spare_xi_nc[5] ;
+ wire \spare_xi_nc[6] ;
+ wire \spare_xi_nc[7] ;
+ wire \spare_xi_nc[8] ;
+ wire \spare_xi_nc[9] ;
+ wire \spare_xib_nc[0] ;
+ wire \spare_xib_nc[1] ;
+ wire \spare_xib_nc[2] ;
+ wire \spare_xib_nc[3] ;
+ wire \spare_xmx_nc[0] ;
+ wire \spare_xmx_nc[1] ;
+ wire \spare_xmx_nc[2] ;
+ wire \spare_xmx_nc[3] ;
+ wire \spare_xmx_nc[4] ;
+ wire \spare_xmx_nc[5] ;
+ wire \spare_xmx_nc[6] ;
+ wire \spare_xmx_nc[7] ;
+ wire \spare_xna_nc[0] ;
+ wire \spare_xna_nc[1] ;
+ wire \spare_xna_nc[2] ;
+ wire \spare_xna_nc[3] ;
+ wire \spare_xna_nc[4] ;
+ wire \spare_xna_nc[5] ;
+ wire \spare_xna_nc[6] ;
+ wire \spare_xna_nc[7] ;
+ wire \spare_xno_nc[0] ;
+ wire \spare_xno_nc[1] ;
+ wire \spare_xno_nc[2] ;
+ wire \spare_xno_nc[3] ;
+ wire \spare_xno_nc[4] ;
+ wire \spare_xno_nc[5] ;
+ wire \spare_xno_nc[6] ;
+ wire \spare_xno_nc[7] ;
+ wire \spare_xz_nc[0] ;
+ wire \spare_xz_nc[100] ;
+ wire \spare_xz_nc[101] ;
+ wire \spare_xz_nc[102] ;
+ wire \spare_xz_nc[103] ;
+ wire \spare_xz_nc[104] ;
+ wire \spare_xz_nc[105] ;
+ wire \spare_xz_nc[106] ;
+ wire \spare_xz_nc[107] ;
+ wire \spare_xz_nc[10] ;
+ wire \spare_xz_nc[11] ;
+ wire \spare_xz_nc[12] ;
+ wire \spare_xz_nc[13] ;
+ wire \spare_xz_nc[14] ;
+ wire \spare_xz_nc[15] ;
+ wire \spare_xz_nc[16] ;
+ wire \spare_xz_nc[17] ;
+ wire \spare_xz_nc[18] ;
+ wire \spare_xz_nc[19] ;
+ wire \spare_xz_nc[1] ;
+ wire \spare_xz_nc[20] ;
+ wire \spare_xz_nc[21] ;
+ wire \spare_xz_nc[22] ;
+ wire \spare_xz_nc[23] ;
+ wire \spare_xz_nc[24] ;
+ wire \spare_xz_nc[25] ;
+ wire \spare_xz_nc[26] ;
+ wire \spare_xz_nc[27] ;
+ wire \spare_xz_nc[28] ;
+ wire \spare_xz_nc[29] ;
+ wire \spare_xz_nc[2] ;
+ wire \spare_xz_nc[30] ;
+ wire \spare_xz_nc[31] ;
+ wire \spare_xz_nc[32] ;
+ wire \spare_xz_nc[33] ;
+ wire \spare_xz_nc[34] ;
+ wire \spare_xz_nc[35] ;
+ wire \spare_xz_nc[36] ;
+ wire \spare_xz_nc[37] ;
+ wire \spare_xz_nc[38] ;
+ wire \spare_xz_nc[39] ;
+ wire \spare_xz_nc[3] ;
+ wire \spare_xz_nc[40] ;
+ wire \spare_xz_nc[41] ;
+ wire \spare_xz_nc[42] ;
+ wire \spare_xz_nc[43] ;
+ wire \spare_xz_nc[44] ;
+ wire \spare_xz_nc[45] ;
+ wire \spare_xz_nc[46] ;
+ wire \spare_xz_nc[47] ;
+ wire \spare_xz_nc[48] ;
+ wire \spare_xz_nc[49] ;
+ wire \spare_xz_nc[4] ;
+ wire \spare_xz_nc[50] ;
+ wire \spare_xz_nc[51] ;
+ wire \spare_xz_nc[52] ;
+ wire \spare_xz_nc[53] ;
+ wire \spare_xz_nc[54] ;
+ wire \spare_xz_nc[55] ;
+ wire \spare_xz_nc[56] ;
+ wire \spare_xz_nc[57] ;
+ wire \spare_xz_nc[58] ;
+ wire \spare_xz_nc[59] ;
+ wire \spare_xz_nc[5] ;
+ wire \spare_xz_nc[60] ;
+ wire \spare_xz_nc[61] ;
+ wire \spare_xz_nc[62] ;
+ wire \spare_xz_nc[63] ;
+ wire \spare_xz_nc[64] ;
+ wire \spare_xz_nc[65] ;
+ wire \spare_xz_nc[66] ;
+ wire \spare_xz_nc[67] ;
+ wire \spare_xz_nc[68] ;
+ wire \spare_xz_nc[69] ;
+ wire \spare_xz_nc[6] ;
+ wire \spare_xz_nc[70] ;
+ wire \spare_xz_nc[71] ;
+ wire \spare_xz_nc[72] ;
+ wire \spare_xz_nc[73] ;
+ wire \spare_xz_nc[74] ;
+ wire \spare_xz_nc[75] ;
+ wire \spare_xz_nc[76] ;
+ wire \spare_xz_nc[77] ;
+ wire \spare_xz_nc[78] ;
+ wire \spare_xz_nc[79] ;
+ wire \spare_xz_nc[7] ;
+ wire \spare_xz_nc[80] ;
+ wire \spare_xz_nc[81] ;
+ wire \spare_xz_nc[82] ;
+ wire \spare_xz_nc[83] ;
+ wire \spare_xz_nc[84] ;
+ wire \spare_xz_nc[85] ;
+ wire \spare_xz_nc[86] ;
+ wire \spare_xz_nc[87] ;
+ wire \spare_xz_nc[88] ;
+ wire \spare_xz_nc[89] ;
+ wire \spare_xz_nc[8] ;
+ wire \spare_xz_nc[90] ;
+ wire \spare_xz_nc[91] ;
+ wire \spare_xz_nc[92] ;
+ wire \spare_xz_nc[93] ;
+ wire \spare_xz_nc[94] ;
+ wire \spare_xz_nc[95] ;
+ wire \spare_xz_nc[96] ;
+ wire \spare_xz_nc[97] ;
+ wire \spare_xz_nc[98] ;
+ wire \spare_xz_nc[99] ;
+ wire \spare_xz_nc[9] ;
+ wire spi_csb;
+ wire spi_enabled;
+ wire \spi_pll90_sel[0] ;
+ wire \spi_pll90_sel[1] ;
+ wire \spi_pll90_sel[2] ;
+ wire spi_pll_dco_ena;
+ wire \spi_pll_div[0] ;
+ wire \spi_pll_div[1] ;
+ wire \spi_pll_div[2] ;
+ wire \spi_pll_div[3] ;
+ wire \spi_pll_div[4] ;
+ wire spi_pll_ena;
+ wire \spi_pll_sel[0] ;
+ wire \spi_pll_sel[1] ;
+ wire \spi_pll_sel[2] ;
+ wire \spi_pll_trim[0] ;
+ wire \spi_pll_trim[10] ;
+ wire \spi_pll_trim[11] ;
+ wire \spi_pll_trim[12] ;
+ wire \spi_pll_trim[13] ;
+ wire \spi_pll_trim[14] ;
+ wire \spi_pll_trim[15] ;
+ wire \spi_pll_trim[16] ;
+ wire \spi_pll_trim[17] ;
+ wire \spi_pll_trim[18] ;
+ wire \spi_pll_trim[19] ;
+ wire \spi_pll_trim[1] ;
+ wire \spi_pll_trim[20] ;
+ wire \spi_pll_trim[21] ;
+ wire \spi_pll_trim[22] ;
+ wire \spi_pll_trim[23] ;
+ wire \spi_pll_trim[24] ;
+ wire \spi_pll_trim[25] ;
+ wire \spi_pll_trim[2] ;
+ wire \spi_pll_trim[3] ;
+ wire \spi_pll_trim[4] ;
+ wire \spi_pll_trim[5] ;
+ wire \spi_pll_trim[6] ;
+ wire \spi_pll_trim[7] ;
+ wire \spi_pll_trim[8] ;
+ wire \spi_pll_trim[9] ;
+ wire spi_sck;
+ wire spi_sdi;
+ wire spi_sdo;
+ wire spi_sdoenb;
+ wire trap;
+ wire uart_enabled;
+ wire \user_analog_io[0] ;
+ wire \user_analog_io[10] ;
+ wire \user_analog_io[11] ;
+ wire \user_analog_io[12] ;
+ wire \user_analog_io[13] ;
+ wire \user_analog_io[14] ;
+ wire \user_analog_io[15] ;
+ wire \user_analog_io[16] ;
+ wire \user_analog_io[17] ;
+ wire \user_analog_io[18] ;
+ wire \user_analog_io[19] ;
+ wire \user_analog_io[1] ;
+ wire \user_analog_io[20] ;
+ wire \user_analog_io[21] ;
+ wire \user_analog_io[22] ;
+ wire \user_analog_io[23] ;
+ wire \user_analog_io[24] ;
+ wire \user_analog_io[25] ;
+ wire \user_analog_io[26] ;
+ wire \user_analog_io[27] ;
+ wire \user_analog_io[28] ;
+ wire \user_analog_io[2] ;
+ wire \user_analog_io[3] ;
+ wire \user_analog_io[4] ;
+ wire \user_analog_io[5] ;
+ wire \user_analog_io[6] ;
+ wire \user_analog_io[7] ;
+ wire \user_analog_io[8] ;
+ wire \user_analog_io[9] ;
+ wire \user_io_in[0] ;
+ wire \user_io_in[10] ;
+ wire \user_io_in[11] ;
+ wire \user_io_in[12] ;
+ wire \user_io_in[13] ;
+ wire \user_io_in[14] ;
+ wire \user_io_in[15] ;
+ wire \user_io_in[16] ;
+ wire \user_io_in[17] ;
+ wire \user_io_in[18] ;
+ wire \user_io_in[19] ;
+ wire \user_io_in[1] ;
+ wire \user_io_in[20] ;
+ wire \user_io_in[21] ;
+ wire \user_io_in[22] ;
+ wire \user_io_in[23] ;
+ wire \user_io_in[24] ;
+ wire \user_io_in[25] ;
+ wire \user_io_in[26] ;
+ wire \user_io_in[27] ;
+ wire \user_io_in[28] ;
+ wire \user_io_in[29] ;
+ wire \user_io_in[2] ;
+ wire \user_io_in[30] ;
+ wire \user_io_in[31] ;
+ wire \user_io_in[32] ;
+ wire \user_io_in[33] ;
+ wire \user_io_in[34] ;
+ wire \user_io_in[35] ;
+ wire \user_io_in[36] ;
+ wire \user_io_in[37] ;
+ wire \user_io_in[3] ;
+ wire \user_io_in[4] ;
+ wire \user_io_in[5] ;
+ wire \user_io_in[6] ;
+ wire \user_io_in[7] ;
+ wire \user_io_in[8] ;
+ wire \user_io_in[9] ;
+ wire \user_io_oeb[0] ;
+ wire \user_io_oeb[10] ;
+ wire \user_io_oeb[11] ;
+ wire \user_io_oeb[12] ;
+ wire \user_io_oeb[13] ;
+ wire \user_io_oeb[14] ;
+ wire \user_io_oeb[15] ;
+ wire \user_io_oeb[16] ;
+ wire \user_io_oeb[17] ;
+ wire \user_io_oeb[18] ;
+ wire \user_io_oeb[19] ;
+ wire \user_io_oeb[1] ;
+ wire \user_io_oeb[20] ;
+ wire \user_io_oeb[21] ;
+ wire \user_io_oeb[22] ;
+ wire \user_io_oeb[23] ;
+ wire \user_io_oeb[24] ;
+ wire \user_io_oeb[25] ;
+ wire \user_io_oeb[26] ;
+ wire \user_io_oeb[27] ;
+ wire \user_io_oeb[28] ;
+ wire \user_io_oeb[29] ;
+ wire \user_io_oeb[2] ;
+ wire \user_io_oeb[30] ;
+ wire \user_io_oeb[31] ;
+ wire \user_io_oeb[32] ;
+ wire \user_io_oeb[33] ;
+ wire \user_io_oeb[34] ;
+ wire \user_io_oeb[35] ;
+ wire \user_io_oeb[36] ;
+ wire \user_io_oeb[37] ;
+ wire \user_io_oeb[3] ;
+ wire \user_io_oeb[4] ;
+ wire \user_io_oeb[5] ;
+ wire \user_io_oeb[6] ;
+ wire \user_io_oeb[7] ;
+ wire \user_io_oeb[8] ;
+ wire \user_io_oeb[9] ;
+ wire \user_io_out[0] ;
+ wire \user_io_out[10] ;
+ wire \user_io_out[11] ;
+ wire \user_io_out[12] ;
+ wire \user_io_out[13] ;
+ wire \user_io_out[14] ;
+ wire \user_io_out[15] ;
+ wire \user_io_out[16] ;
+ wire \user_io_out[17] ;
+ wire \user_io_out[18] ;
+ wire \user_io_out[19] ;
+ wire \user_io_out[1] ;
+ wire \user_io_out[20] ;
+ wire \user_io_out[21] ;
+ wire \user_io_out[22] ;
+ wire \user_io_out[23] ;
+ wire \user_io_out[24] ;
+ wire \user_io_out[25] ;
+ wire \user_io_out[26] ;
+ wire \user_io_out[27] ;
+ wire \user_io_out[28] ;
+ wire \user_io_out[29] ;
+ wire \user_io_out[2] ;
+ wire \user_io_out[30] ;
+ wire \user_io_out[31] ;
+ wire \user_io_out[32] ;
+ wire \user_io_out[33] ;
+ wire \user_io_out[34] ;
+ wire \user_io_out[35] ;
+ wire \user_io_out[36] ;
+ wire \user_io_out[37] ;
+ wire \user_io_out[3] ;
+ wire \user_io_out[4] ;
+ wire \user_io_out[5] ;
+ wire \user_io_out[6] ;
+ wire \user_io_out[7] ;
+ wire \user_io_out[8] ;
+ wire \user_io_out[9] ;
+ wire \user_irq[0] ;
+ wire \user_irq[1] ;
+ wire \user_irq[2] ;
+ wire \user_irq_core[0] ;
+ wire \user_irq_core[1] ;
+ wire \user_irq_core[2] ;
+ wire \user_irq_ena[0] ;
+ wire \user_irq_ena[1] ;
+ wire \user_irq_ena[2] ;
+ inout vccd;
+ inout vccd1;
+ wire vccd1_core;
+ inout vccd2;
+ wire vccd2_core;
+ wire vccd_core;
+ inout vdda;
+ inout vdda1;
+ inout vdda1_2;
+ wire vdda1_core;
+ inout vdda2;
+ wire vdda2_core;
+ wire vdda_core;
+ inout vddio;
+ inout vddio_2;
+ wire vddio_core;
+ inout vssa;
+ inout vssa1;
+ inout vssa1_2;
+ wire vssa1_core;
+ inout vssa2;
+ wire vssa2_core;
+ wire vssa_core;
+ inout vssd;
+ inout vssd1;
+ wire vssd1_core;
+ inout vssd2;
+ wire vssd2_core;
+ wire vssd_core;
+ inout vssio;
+ inout vssio_2;
+ wire vssio_core;
+ caravel_clocking clock_ctrl (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .core_clk(caravel_clk),
+ .ext_clk(clock_core_buf),
+ .ext_clk_sel(ext_clk_sel),
+ .ext_reset(ext_reset),
+ .pll_clk(pll_clk),
+ .pll_clk90(pll_clk90),
+ .resetb(rstb_l_buf),
+ .resetb_sync(caravel_rstn),
+ .sel({ \spi_pll_sel[2] , \spi_pll_sel[1] , \spi_pll_sel[0] }),
+ .sel2({ \spi_pll90_sel[2] , \spi_pll90_sel[1] , \spi_pll90_sel[0] }),
+ .user_clk(caravel_clk2)
+ );
+ buff_flash_clkrst flash_clkrst_buffers (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .in_n({ caravel_clk, caravel_rstn, flash_clk_frame, flash_csb_frame, flash_clk_oeb, flash_csb_oeb, flash_io0_oeb, flash_io1_oeb, flash_io0_ieb, flash_io1_ieb, flash_io0_do, flash_io1_do }),
+ .in_s({ clock_core, flash_io1_di, flash_io0_di }),
+ .out_n({ clock_core_buf, flash_io1_di_buf, flash_io0_di_buf }),
+ .out_s({ caravel_clk_buf, caravel_rstn_buf, flash_clk_frame_buf, flash_csb_frame_buf, flash_clk_oeb_buf, flash_csb_oeb_buf, flash_io0_oeb_buf, flash_io1_oeb_buf, flash_io0_ieb_buf, flash_io1_ieb_buf, flash_io0_do_buf, flash_io1_do_buf })
+ );
+ gpio_control_block \gpio_control_bidir_1[0] (
+ .gpio_defaults({ \gpio_defaults[12] , \gpio_defaults[11] , \gpio_defaults[10] , \gpio_defaults[9] , \gpio_defaults[8] , \gpio_defaults[7] , \gpio_defaults[6] , \gpio_defaults[5] , \gpio_defaults[4] , \gpio_defaults[3] , \gpio_defaults[2] , \gpio_defaults[1] , \gpio_defaults[0] }),
+ .mgmt_gpio_in(\mgmt_io_in[0] ),
+ .mgmt_gpio_oeb(\mgmt_io_oeb[0] ),
+ .mgmt_gpio_out(\mgmt_io_out[0] ),
+ .one(\mprj_io_one[0] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[0] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[0] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[0] ),
+ .pad_gpio_dm({ \mprj_io_dm[2] , \mprj_io_dm[1] , \mprj_io_dm[0] }),
+ .pad_gpio_holdover(\mprj_io_holdover[0] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[0] ),
+ .pad_gpio_in(\mprj_io_in[0] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[0] ),
+ .pad_gpio_out(\mprj_io_out[0] ),
+ .pad_gpio_outenb(\mprj_io_oeb[0] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[0] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[0] ),
+ .resetn(\gpio_resetn_1_shifted[0] ),
+ .resetn_out(\gpio_resetn_1[0] ),
+ .serial_clock(\gpio_clock_1_shifted[0] ),
+ .serial_clock_out(\gpio_clock_1[0] ),
+ .serial_data_in(\gpio_serial_link_1_shifted[0] ),
+ .serial_data_out(\gpio_serial_link_1[0] ),
+ .serial_load(\gpio_load_1_shifted[0] ),
+ .serial_load_out(\gpio_load_1[0] ),
+ .user_gpio_in(\user_io_in[0] ),
+ .user_gpio_oeb(\user_io_oeb[0] ),
+ .user_gpio_out(\user_io_out[0] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_bidir_1[1] (
+ .gpio_defaults({ \gpio_defaults[25] , \gpio_defaults[24] , \gpio_defaults[23] , \gpio_defaults[22] , \gpio_defaults[21] , \gpio_defaults[20] , \gpio_defaults[19] , \gpio_defaults[18] , \gpio_defaults[17] , \gpio_defaults[16] , \gpio_defaults[15] , \gpio_defaults[14] , \gpio_defaults[13] }),
+ .mgmt_gpio_in(\mgmt_io_in[1] ),
+ .mgmt_gpio_oeb(\mgmt_io_oeb[1] ),
+ .mgmt_gpio_out(\mgmt_io_out[1] ),
+ .one(\mprj_io_one[1] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[1] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[1] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[1] ),
+ .pad_gpio_dm({ \mprj_io_dm[5] , \mprj_io_dm[4] , \mprj_io_dm[3] }),
+ .pad_gpio_holdover(\mprj_io_holdover[1] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[1] ),
+ .pad_gpio_in(\mprj_io_in[1] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[1] ),
+ .pad_gpio_out(\mprj_io_out[1] ),
+ .pad_gpio_outenb(\mprj_io_oeb[1] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[1] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[1] ),
+ .resetn(\gpio_resetn_1[0] ),
+ .resetn_out(\gpio_resetn_1[1] ),
+ .serial_clock(\gpio_clock_1[0] ),
+ .serial_clock_out(\gpio_clock_1[1] ),
+ .serial_data_in(\gpio_serial_link_1[0] ),
+ .serial_data_out(\gpio_serial_link_1[1] ),
+ .serial_load(\gpio_load_1[0] ),
+ .serial_load_out(\gpio_load_1[1] ),
+ .user_gpio_in(\user_io_in[1] ),
+ .user_gpio_oeb(\user_io_oeb[1] ),
+ .user_gpio_out(\user_io_out[1] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_bidir_2[0] (
+ .gpio_defaults({ \gpio_defaults[467] , \gpio_defaults[466] , \gpio_defaults[465] , \gpio_defaults[464] , \gpio_defaults[463] , \gpio_defaults[462] , \gpio_defaults[461] , \gpio_defaults[460] , \gpio_defaults[459] , \gpio_defaults[458] , \gpio_defaults[457] , \gpio_defaults[456] , \gpio_defaults[455] }),
+ .mgmt_gpio_in(\mgmt_io_in[35] ),
+ .mgmt_gpio_oeb(\mgmt_io_oeb[35] ),
+ .mgmt_gpio_out(\mgmt_io_out[35] ),
+ .one(\mprj_io_one[35] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[35] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[35] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[35] ),
+ .pad_gpio_dm({ \mprj_io_dm[107] , \mprj_io_dm[106] , \mprj_io_dm[105] }),
+ .pad_gpio_holdover(\mprj_io_holdover[35] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[35] ),
+ .pad_gpio_in(\mprj_io_in[35] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[35] ),
+ .pad_gpio_out(\mprj_io_out[35] ),
+ .pad_gpio_outenb(\mprj_io_oeb[35] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[35] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[35] ),
+ .resetn(\gpio_resetn_2[17] ),
+ .resetn_out(\gpio_resetn_2[16] ),
+ .serial_clock(\gpio_clock_2[17] ),
+ .serial_clock_out(\gpio_clock_2[16] ),
+ .serial_data_in(\gpio_serial_link_2[17] ),
+ .serial_data_out(\gpio_serial_link_2[16] ),
+ .serial_load(\gpio_load_2[17] ),
+ .serial_load_out(\gpio_load_2[16] ),
+ .user_gpio_in(\user_io_in[35] ),
+ .user_gpio_oeb(\user_io_oeb[35] ),
+ .user_gpio_out(\user_io_out[35] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_bidir_2[1] (
+ .gpio_defaults({ \gpio_defaults[480] , \gpio_defaults[479] , \gpio_defaults[478] , \gpio_defaults[477] , \gpio_defaults[476] , \gpio_defaults[475] , \gpio_defaults[474] , \gpio_defaults[473] , \gpio_defaults[472] , \gpio_defaults[471] , \gpio_defaults[470] , \gpio_defaults[469] , \gpio_defaults[468] }),
+ .mgmt_gpio_in(\mgmt_io_in[36] ),
+ .mgmt_gpio_oeb(\mgmt_io_oeb[36] ),
+ .mgmt_gpio_out(\mgmt_io_out[36] ),
+ .one(\mprj_io_one[36] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[36] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[36] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[36] ),
+ .pad_gpio_dm({ \mprj_io_dm[110] , \mprj_io_dm[109] , \mprj_io_dm[108] }),
+ .pad_gpio_holdover(\mprj_io_holdover[36] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[36] ),
+ .pad_gpio_in(\mprj_io_in[36] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[36] ),
+ .pad_gpio_out(\mprj_io_out[36] ),
+ .pad_gpio_outenb(\mprj_io_oeb[36] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[36] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[36] ),
+ .resetn(\gpio_resetn_2[18] ),
+ .resetn_out(\gpio_resetn_2[17] ),
+ .serial_clock(\gpio_clock_2[18] ),
+ .serial_clock_out(\gpio_clock_2[17] ),
+ .serial_data_in(\gpio_serial_link_2[18] ),
+ .serial_data_out(\gpio_serial_link_2[17] ),
+ .serial_load(\gpio_load_2[18] ),
+ .serial_load_out(\gpio_load_2[17] ),
+ .user_gpio_in(\user_io_in[36] ),
+ .user_gpio_oeb(\user_io_oeb[36] ),
+ .user_gpio_out(\user_io_out[36] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_bidir_2[2] (
+ .gpio_defaults({ \gpio_defaults[493] , \gpio_defaults[492] , \gpio_defaults[491] , \gpio_defaults[490] , \gpio_defaults[489] , \gpio_defaults[488] , \gpio_defaults[487] , \gpio_defaults[486] , \gpio_defaults[485] , \gpio_defaults[484] , \gpio_defaults[483] , \gpio_defaults[482] , \gpio_defaults[481] }),
+ .mgmt_gpio_in(\mgmt_io_in[37] ),
+ .mgmt_gpio_oeb(\mgmt_io_oeb[37] ),
+ .mgmt_gpio_out(\mgmt_io_out[37] ),
+ .one(\mprj_io_one[37] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[37] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[37] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[37] ),
+ .pad_gpio_dm({ \mprj_io_dm[113] , \mprj_io_dm[112] , \mprj_io_dm[111] }),
+ .pad_gpio_holdover(\mprj_io_holdover[37] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[37] ),
+ .pad_gpio_in(\mprj_io_in[37] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[37] ),
+ .pad_gpio_out(\mprj_io_out[37] ),
+ .pad_gpio_outenb(\mprj_io_oeb[37] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[37] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[37] ),
+ .resetn(\gpio_resetn_2_shifted[18] ),
+ .resetn_out(\gpio_resetn_2[18] ),
+ .serial_clock(\gpio_clock_2_shifted[18] ),
+ .serial_clock_out(\gpio_clock_2[18] ),
+ .serial_data_in(\gpio_serial_link_2_shifted[18] ),
+ .serial_data_out(\gpio_serial_link_2[18] ),
+ .serial_load(\gpio_load_2_shifted[18] ),
+ .serial_load_out(\gpio_load_2[18] ),
+ .user_gpio_in(\user_io_in[37] ),
+ .user_gpio_oeb(\user_io_oeb[37] ),
+ .user_gpio_out(\user_io_out[37] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1[0] (
+ .gpio_defaults({ \gpio_defaults[116] , \gpio_defaults[115] , \gpio_defaults[114] , \gpio_defaults[113] , \gpio_defaults[112] , \gpio_defaults[111] , \gpio_defaults[110] , \gpio_defaults[109] , \gpio_defaults[108] , \gpio_defaults[107] , \gpio_defaults[106] , \gpio_defaults[105] , \gpio_defaults[104] }),
+ .mgmt_gpio_in(\mgmt_io_in[8] ),
+ .mgmt_gpio_oeb(\mprj_io_one[8] ),
+ .mgmt_gpio_out(\mgmt_io_out[8] ),
+ .one(\mprj_io_one[8] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[8] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[8] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[8] ),
+ .pad_gpio_dm({ \mprj_io_dm[26] , \mprj_io_dm[25] , \mprj_io_dm[24] }),
+ .pad_gpio_holdover(\mprj_io_holdover[8] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[8] ),
+ .pad_gpio_in(\mprj_io_in[8] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[8] ),
+ .pad_gpio_out(\mprj_io_out[8] ),
+ .pad_gpio_outenb(\mprj_io_oeb[8] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[8] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[8] ),
+ .resetn(\gpio_resetn_1[7] ),
+ .resetn_out(\gpio_resetn_1[8] ),
+ .serial_clock(\gpio_clock_1[7] ),
+ .serial_clock_out(\gpio_clock_1[8] ),
+ .serial_data_in(\gpio_serial_link_1[7] ),
+ .serial_data_out(\gpio_serial_link_1[8] ),
+ .serial_load(\gpio_load_1[7] ),
+ .serial_load_out(\gpio_load_1[8] ),
+ .user_gpio_in(\user_io_in[8] ),
+ .user_gpio_oeb(\user_io_oeb[8] ),
+ .user_gpio_out(\user_io_out[8] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1[10] (
+ .gpio_defaults({ \gpio_defaults[246] , \gpio_defaults[245] , \gpio_defaults[244] , \gpio_defaults[243] , \gpio_defaults[242] , \gpio_defaults[241] , \gpio_defaults[240] , \gpio_defaults[239] , \gpio_defaults[238] , \gpio_defaults[237] , \gpio_defaults[236] , \gpio_defaults[235] , \gpio_defaults[234] }),
+ .mgmt_gpio_in(\mgmt_io_in[18] ),
+ .mgmt_gpio_oeb(\mprj_io_one[18] ),
+ .mgmt_gpio_out(\mgmt_io_out[18] ),
+ .one(\mprj_io_one[18] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[18] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[18] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[18] ),
+ .pad_gpio_dm({ \mprj_io_dm[56] , \mprj_io_dm[55] , \mprj_io_dm[54] }),
+ .pad_gpio_holdover(\mprj_io_holdover[18] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[18] ),
+ .pad_gpio_in(\mprj_io_in[18] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[18] ),
+ .pad_gpio_out(\mprj_io_out[18] ),
+ .pad_gpio_outenb(\mprj_io_oeb[18] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[18] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[18] ),
+ .resetn(\gpio_resetn_1[17] ),
+ .resetn_out(\gpio_resetn_1[18] ),
+ .serial_clock(\gpio_clock_1[17] ),
+ .serial_clock_out(\gpio_clock_1[18] ),
+ .serial_data_in(\gpio_serial_link_1[17] ),
+ .serial_data_out(\gpio_serial_link_1[18] ),
+ .serial_load(\gpio_load_1[17] ),
+ .serial_load_out(\gpio_load_1[18] ),
+ .user_gpio_in(\user_io_in[18] ),
+ .user_gpio_oeb(\user_io_oeb[18] ),
+ .user_gpio_out(\user_io_out[18] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1[1] (
+ .gpio_defaults({ \gpio_defaults[129] , \gpio_defaults[128] , \gpio_defaults[127] , \gpio_defaults[126] , \gpio_defaults[125] , \gpio_defaults[124] , \gpio_defaults[123] , \gpio_defaults[122] , \gpio_defaults[121] , \gpio_defaults[120] , \gpio_defaults[119] , \gpio_defaults[118] , \gpio_defaults[117] }),
+ .mgmt_gpio_in(\mgmt_io_in[9] ),
+ .mgmt_gpio_oeb(\mprj_io_one[9] ),
+ .mgmt_gpio_out(\mgmt_io_out[9] ),
+ .one(\mprj_io_one[9] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[9] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[9] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[9] ),
+ .pad_gpio_dm({ \mprj_io_dm[29] , \mprj_io_dm[28] , \mprj_io_dm[27] }),
+ .pad_gpio_holdover(\mprj_io_holdover[9] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[9] ),
+ .pad_gpio_in(\mprj_io_in[9] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[9] ),
+ .pad_gpio_out(\mprj_io_out[9] ),
+ .pad_gpio_outenb(\mprj_io_oeb[9] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[9] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[9] ),
+ .resetn(\gpio_resetn_1[8] ),
+ .resetn_out(\gpio_resetn_1[9] ),
+ .serial_clock(\gpio_clock_1[8] ),
+ .serial_clock_out(\gpio_clock_1[9] ),
+ .serial_data_in(\gpio_serial_link_1[8] ),
+ .serial_data_out(\gpio_serial_link_1[9] ),
+ .serial_load(\gpio_load_1[8] ),
+ .serial_load_out(\gpio_load_1[9] ),
+ .user_gpio_in(\user_io_in[9] ),
+ .user_gpio_oeb(\user_io_oeb[9] ),
+ .user_gpio_out(\user_io_out[9] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1[2] (
+ .gpio_defaults({ \gpio_defaults[142] , \gpio_defaults[141] , \gpio_defaults[140] , \gpio_defaults[139] , \gpio_defaults[138] , \gpio_defaults[137] , \gpio_defaults[136] , \gpio_defaults[135] , \gpio_defaults[134] , \gpio_defaults[133] , \gpio_defaults[132] , \gpio_defaults[131] , \gpio_defaults[130] }),
+ .mgmt_gpio_in(\mgmt_io_in[10] ),
+ .mgmt_gpio_oeb(\mprj_io_one[10] ),
+ .mgmt_gpio_out(\mgmt_io_out[10] ),
+ .one(\mprj_io_one[10] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[10] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[10] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[10] ),
+ .pad_gpio_dm({ \mprj_io_dm[32] , \mprj_io_dm[31] , \mprj_io_dm[30] }),
+ .pad_gpio_holdover(\mprj_io_holdover[10] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[10] ),
+ .pad_gpio_in(\mprj_io_in[10] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[10] ),
+ .pad_gpio_out(\mprj_io_out[10] ),
+ .pad_gpio_outenb(\mprj_io_oeb[10] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[10] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[10] ),
+ .resetn(\gpio_resetn_1[9] ),
+ .resetn_out(\gpio_resetn_1[10] ),
+ .serial_clock(\gpio_clock_1[9] ),
+ .serial_clock_out(\gpio_clock_1[10] ),
+ .serial_data_in(\gpio_serial_link_1[9] ),
+ .serial_data_out(\gpio_serial_link_1[10] ),
+ .serial_load(\gpio_load_1[9] ),
+ .serial_load_out(\gpio_load_1[10] ),
+ .user_gpio_in(\user_io_in[10] ),
+ .user_gpio_oeb(\user_io_oeb[10] ),
+ .user_gpio_out(\user_io_out[10] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1[3] (
+ .gpio_defaults({ \gpio_defaults[155] , \gpio_defaults[154] , \gpio_defaults[153] , \gpio_defaults[152] , \gpio_defaults[151] , \gpio_defaults[150] , \gpio_defaults[149] , \gpio_defaults[148] , \gpio_defaults[147] , \gpio_defaults[146] , \gpio_defaults[145] , \gpio_defaults[144] , \gpio_defaults[143] }),
+ .mgmt_gpio_in(\mgmt_io_in[11] ),
+ .mgmt_gpio_oeb(\mprj_io_one[11] ),
+ .mgmt_gpio_out(\mgmt_io_out[11] ),
+ .one(\mprj_io_one[11] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[11] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[11] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[11] ),
+ .pad_gpio_dm({ \mprj_io_dm[35] , \mprj_io_dm[34] , \mprj_io_dm[33] }),
+ .pad_gpio_holdover(\mprj_io_holdover[11] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[11] ),
+ .pad_gpio_in(\mprj_io_in[11] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[11] ),
+ .pad_gpio_out(\mprj_io_out[11] ),
+ .pad_gpio_outenb(\mprj_io_oeb[11] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[11] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[11] ),
+ .resetn(\gpio_resetn_1[10] ),
+ .resetn_out(\gpio_resetn_1[11] ),
+ .serial_clock(\gpio_clock_1[10] ),
+ .serial_clock_out(\gpio_clock_1[11] ),
+ .serial_data_in(\gpio_serial_link_1[10] ),
+ .serial_data_out(\gpio_serial_link_1[11] ),
+ .serial_load(\gpio_load_1[10] ),
+ .serial_load_out(\gpio_load_1[11] ),
+ .user_gpio_in(\user_io_in[11] ),
+ .user_gpio_oeb(\user_io_oeb[11] ),
+ .user_gpio_out(\user_io_out[11] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1[4] (
+ .gpio_defaults({ \gpio_defaults[168] , \gpio_defaults[167] , \gpio_defaults[166] , \gpio_defaults[165] , \gpio_defaults[164] , \gpio_defaults[163] , \gpio_defaults[162] , \gpio_defaults[161] , \gpio_defaults[160] , \gpio_defaults[159] , \gpio_defaults[158] , \gpio_defaults[157] , \gpio_defaults[156] }),
+ .mgmt_gpio_in(\mgmt_io_in[12] ),
+ .mgmt_gpio_oeb(\mprj_io_one[12] ),
+ .mgmt_gpio_out(\mgmt_io_out[12] ),
+ .one(\mprj_io_one[12] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[12] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[12] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[12] ),
+ .pad_gpio_dm({ \mprj_io_dm[38] , \mprj_io_dm[37] , \mprj_io_dm[36] }),
+ .pad_gpio_holdover(\mprj_io_holdover[12] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[12] ),
+ .pad_gpio_in(\mprj_io_in[12] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[12] ),
+ .pad_gpio_out(\mprj_io_out[12] ),
+ .pad_gpio_outenb(\mprj_io_oeb[12] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[12] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[12] ),
+ .resetn(\gpio_resetn_1[11] ),
+ .resetn_out(\gpio_resetn_1[12] ),
+ .serial_clock(\gpio_clock_1[11] ),
+ .serial_clock_out(\gpio_clock_1[12] ),
+ .serial_data_in(\gpio_serial_link_1[11] ),
+ .serial_data_out(\gpio_serial_link_1[12] ),
+ .serial_load(\gpio_load_1[11] ),
+ .serial_load_out(\gpio_load_1[12] ),
+ .user_gpio_in(\user_io_in[12] ),
+ .user_gpio_oeb(\user_io_oeb[12] ),
+ .user_gpio_out(\user_io_out[12] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1[5] (
+ .gpio_defaults({ \gpio_defaults[181] , \gpio_defaults[180] , \gpio_defaults[179] , \gpio_defaults[178] , \gpio_defaults[177] , \gpio_defaults[176] , \gpio_defaults[175] , \gpio_defaults[174] , \gpio_defaults[173] , \gpio_defaults[172] , \gpio_defaults[171] , \gpio_defaults[170] , \gpio_defaults[169] }),
+ .mgmt_gpio_in(\mgmt_io_in[13] ),
+ .mgmt_gpio_oeb(\mprj_io_one[13] ),
+ .mgmt_gpio_out(\mgmt_io_out[13] ),
+ .one(\mprj_io_one[13] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[13] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[13] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[13] ),
+ .pad_gpio_dm({ \mprj_io_dm[41] , \mprj_io_dm[40] , \mprj_io_dm[39] }),
+ .pad_gpio_holdover(\mprj_io_holdover[13] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[13] ),
+ .pad_gpio_in(\mprj_io_in[13] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[13] ),
+ .pad_gpio_out(\mprj_io_out[13] ),
+ .pad_gpio_outenb(\mprj_io_oeb[13] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[13] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[13] ),
+ .resetn(\gpio_resetn_1[12] ),
+ .resetn_out(\gpio_resetn_1[13] ),
+ .serial_clock(\gpio_clock_1[12] ),
+ .serial_clock_out(\gpio_clock_1[13] ),
+ .serial_data_in(\gpio_serial_link_1[12] ),
+ .serial_data_out(\gpio_serial_link_1[13] ),
+ .serial_load(\gpio_load_1[12] ),
+ .serial_load_out(\gpio_load_1[13] ),
+ .user_gpio_in(\user_io_in[13] ),
+ .user_gpio_oeb(\user_io_oeb[13] ),
+ .user_gpio_out(\user_io_out[13] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1[6] (
+ .gpio_defaults({ \gpio_defaults[194] , \gpio_defaults[193] , \gpio_defaults[192] , \gpio_defaults[191] , \gpio_defaults[190] , \gpio_defaults[189] , \gpio_defaults[188] , \gpio_defaults[187] , \gpio_defaults[186] , \gpio_defaults[185] , \gpio_defaults[184] , \gpio_defaults[183] , \gpio_defaults[182] }),
+ .mgmt_gpio_in(\mgmt_io_in[14] ),
+ .mgmt_gpio_oeb(\mprj_io_one[14] ),
+ .mgmt_gpio_out(\mgmt_io_out[14] ),
+ .one(\mprj_io_one[14] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[14] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[14] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[14] ),
+ .pad_gpio_dm({ \mprj_io_dm[44] , \mprj_io_dm[43] , \mprj_io_dm[42] }),
+ .pad_gpio_holdover(\mprj_io_holdover[14] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[14] ),
+ .pad_gpio_in(\mprj_io_in[14] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[14] ),
+ .pad_gpio_out(\mprj_io_out[14] ),
+ .pad_gpio_outenb(\mprj_io_oeb[14] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[14] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[14] ),
+ .resetn(\gpio_resetn_1[13] ),
+ .resetn_out(\gpio_resetn_1[14] ),
+ .serial_clock(\gpio_clock_1[13] ),
+ .serial_clock_out(\gpio_clock_1[14] ),
+ .serial_data_in(\gpio_serial_link_1[13] ),
+ .serial_data_out(\gpio_serial_link_1[14] ),
+ .serial_load(\gpio_load_1[13] ),
+ .serial_load_out(\gpio_load_1[14] ),
+ .user_gpio_in(\user_io_in[14] ),
+ .user_gpio_oeb(\user_io_oeb[14] ),
+ .user_gpio_out(\user_io_out[14] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1[7] (
+ .gpio_defaults({ \gpio_defaults[207] , \gpio_defaults[206] , \gpio_defaults[205] , \gpio_defaults[204] , \gpio_defaults[203] , \gpio_defaults[202] , \gpio_defaults[201] , \gpio_defaults[200] , \gpio_defaults[199] , \gpio_defaults[198] , \gpio_defaults[197] , \gpio_defaults[196] , \gpio_defaults[195] }),
+ .mgmt_gpio_in(\mgmt_io_in[15] ),
+ .mgmt_gpio_oeb(\mprj_io_one[15] ),
+ .mgmt_gpio_out(\mgmt_io_out[15] ),
+ .one(\mprj_io_one[15] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[15] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[15] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[15] ),
+ .pad_gpio_dm({ \mprj_io_dm[47] , \mprj_io_dm[46] , \mprj_io_dm[45] }),
+ .pad_gpio_holdover(\mprj_io_holdover[15] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[15] ),
+ .pad_gpio_in(\mprj_io_in[15] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[15] ),
+ .pad_gpio_out(\mprj_io_out[15] ),
+ .pad_gpio_outenb(\mprj_io_oeb[15] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[15] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[15] ),
+ .resetn(\gpio_resetn_1[14] ),
+ .resetn_out(\gpio_resetn_1[15] ),
+ .serial_clock(\gpio_clock_1[14] ),
+ .serial_clock_out(\gpio_clock_1[15] ),
+ .serial_data_in(\gpio_serial_link_1[14] ),
+ .serial_data_out(\gpio_serial_link_1[15] ),
+ .serial_load(\gpio_load_1[14] ),
+ .serial_load_out(\gpio_load_1[15] ),
+ .user_gpio_in(\user_io_in[15] ),
+ .user_gpio_oeb(\user_io_oeb[15] ),
+ .user_gpio_out(\user_io_out[15] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1[8] (
+ .gpio_defaults({ \gpio_defaults[220] , \gpio_defaults[219] , \gpio_defaults[218] , \gpio_defaults[217] , \gpio_defaults[216] , \gpio_defaults[215] , \gpio_defaults[214] , \gpio_defaults[213] , \gpio_defaults[212] , \gpio_defaults[211] , \gpio_defaults[210] , \gpio_defaults[209] , \gpio_defaults[208] }),
+ .mgmt_gpio_in(\mgmt_io_in[16] ),
+ .mgmt_gpio_oeb(\mprj_io_one[16] ),
+ .mgmt_gpio_out(\mgmt_io_out[16] ),
+ .one(\mprj_io_one[16] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[16] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[16] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[16] ),
+ .pad_gpio_dm({ \mprj_io_dm[50] , \mprj_io_dm[49] , \mprj_io_dm[48] }),
+ .pad_gpio_holdover(\mprj_io_holdover[16] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[16] ),
+ .pad_gpio_in(\mprj_io_in[16] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[16] ),
+ .pad_gpio_out(\mprj_io_out[16] ),
+ .pad_gpio_outenb(\mprj_io_oeb[16] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[16] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[16] ),
+ .resetn(\gpio_resetn_1[15] ),
+ .resetn_out(\gpio_resetn_1[16] ),
+ .serial_clock(\gpio_clock_1[15] ),
+ .serial_clock_out(\gpio_clock_1[16] ),
+ .serial_data_in(\gpio_serial_link_1[15] ),
+ .serial_data_out(\gpio_serial_link_1[16] ),
+ .serial_load(\gpio_load_1[15] ),
+ .serial_load_out(\gpio_load_1[16] ),
+ .user_gpio_in(\user_io_in[16] ),
+ .user_gpio_oeb(\user_io_oeb[16] ),
+ .user_gpio_out(\user_io_out[16] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1[9] (
+ .gpio_defaults({ \gpio_defaults[233] , \gpio_defaults[232] , \gpio_defaults[231] , \gpio_defaults[230] , \gpio_defaults[229] , \gpio_defaults[228] , \gpio_defaults[227] , \gpio_defaults[226] , \gpio_defaults[225] , \gpio_defaults[224] , \gpio_defaults[223] , \gpio_defaults[222] , \gpio_defaults[221] }),
+ .mgmt_gpio_in(\mgmt_io_in[17] ),
+ .mgmt_gpio_oeb(\mprj_io_one[17] ),
+ .mgmt_gpio_out(\mgmt_io_out[17] ),
+ .one(\mprj_io_one[17] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[17] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[17] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[17] ),
+ .pad_gpio_dm({ \mprj_io_dm[53] , \mprj_io_dm[52] , \mprj_io_dm[51] }),
+ .pad_gpio_holdover(\mprj_io_holdover[17] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[17] ),
+ .pad_gpio_in(\mprj_io_in[17] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[17] ),
+ .pad_gpio_out(\mprj_io_out[17] ),
+ .pad_gpio_outenb(\mprj_io_oeb[17] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[17] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[17] ),
+ .resetn(\gpio_resetn_1[16] ),
+ .resetn_out(\gpio_resetn_1[17] ),
+ .serial_clock(\gpio_clock_1[16] ),
+ .serial_clock_out(\gpio_clock_1[17] ),
+ .serial_data_in(\gpio_serial_link_1[16] ),
+ .serial_data_out(\gpio_serial_link_1[17] ),
+ .serial_load(\gpio_load_1[16] ),
+ .serial_load_out(\gpio_load_1[17] ),
+ .user_gpio_in(\user_io_in[17] ),
+ .user_gpio_oeb(\user_io_oeb[17] ),
+ .user_gpio_out(\user_io_out[17] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1a[0] (
+ .gpio_defaults({ \gpio_defaults[38] , \gpio_defaults[37] , \gpio_defaults[36] , \gpio_defaults[35] , \gpio_defaults[34] , \gpio_defaults[33] , \gpio_defaults[32] , \gpio_defaults[31] , \gpio_defaults[30] , \gpio_defaults[29] , \gpio_defaults[28] , \gpio_defaults[27] , \gpio_defaults[26] }),
+ .mgmt_gpio_in(\mgmt_io_in[2] ),
+ .mgmt_gpio_oeb(\mprj_io_one[2] ),
+ .mgmt_gpio_out(\mgmt_io_out[2] ),
+ .one(\mprj_io_one[2] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[2] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[2] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[2] ),
+ .pad_gpio_dm({ \mprj_io_dm[8] , \mprj_io_dm[7] , \mprj_io_dm[6] }),
+ .pad_gpio_holdover(\mprj_io_holdover[2] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[2] ),
+ .pad_gpio_in(\mprj_io_in[2] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[2] ),
+ .pad_gpio_out(\mprj_io_out[2] ),
+ .pad_gpio_outenb(\mprj_io_oeb[2] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[2] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[2] ),
+ .resetn(\gpio_resetn_1[1] ),
+ .resetn_out(\gpio_resetn_1[2] ),
+ .serial_clock(\gpio_clock_1[1] ),
+ .serial_clock_out(\gpio_clock_1[2] ),
+ .serial_data_in(\gpio_serial_link_1[1] ),
+ .serial_data_out(\gpio_serial_link_1[2] ),
+ .serial_load(\gpio_load_1[1] ),
+ .serial_load_out(\gpio_load_1[2] ),
+ .user_gpio_in(\user_io_in[2] ),
+ .user_gpio_oeb(\user_io_oeb[2] ),
+ .user_gpio_out(\user_io_out[2] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1a[1] (
+ .gpio_defaults({ \gpio_defaults[51] , \gpio_defaults[50] , \gpio_defaults[49] , \gpio_defaults[48] , \gpio_defaults[47] , \gpio_defaults[46] , \gpio_defaults[45] , \gpio_defaults[44] , \gpio_defaults[43] , \gpio_defaults[42] , \gpio_defaults[41] , \gpio_defaults[40] , \gpio_defaults[39] }),
+ .mgmt_gpio_in(\mgmt_io_in[3] ),
+ .mgmt_gpio_oeb(\mprj_io_one[3] ),
+ .mgmt_gpio_out(\mgmt_io_out[3] ),
+ .one(\mprj_io_one[3] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[3] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[3] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[3] ),
+ .pad_gpio_dm({ \mprj_io_dm[11] , \mprj_io_dm[10] , \mprj_io_dm[9] }),
+ .pad_gpio_holdover(\mprj_io_holdover[3] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[3] ),
+ .pad_gpio_in(\mprj_io_in[3] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[3] ),
+ .pad_gpio_out(\mprj_io_out[3] ),
+ .pad_gpio_outenb(\mprj_io_oeb[3] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[3] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[3] ),
+ .resetn(\gpio_resetn_1[2] ),
+ .resetn_out(\gpio_resetn_1[3] ),
+ .serial_clock(\gpio_clock_1[2] ),
+ .serial_clock_out(\gpio_clock_1[3] ),
+ .serial_data_in(\gpio_serial_link_1[2] ),
+ .serial_data_out(\gpio_serial_link_1[3] ),
+ .serial_load(\gpio_load_1[2] ),
+ .serial_load_out(\gpio_load_1[3] ),
+ .user_gpio_in(\user_io_in[3] ),
+ .user_gpio_oeb(\user_io_oeb[3] ),
+ .user_gpio_out(\user_io_out[3] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1a[2] (
+ .gpio_defaults({ \gpio_defaults[64] , \gpio_defaults[63] , \gpio_defaults[62] , \gpio_defaults[61] , \gpio_defaults[60] , \gpio_defaults[59] , \gpio_defaults[58] , \gpio_defaults[57] , \gpio_defaults[56] , \gpio_defaults[55] , \gpio_defaults[54] , \gpio_defaults[53] , \gpio_defaults[52] }),
+ .mgmt_gpio_in(\mgmt_io_in[4] ),
+ .mgmt_gpio_oeb(\mprj_io_one[4] ),
+ .mgmt_gpio_out(\mgmt_io_out[4] ),
+ .one(\mprj_io_one[4] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[4] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[4] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[4] ),
+ .pad_gpio_dm({ \mprj_io_dm[14] , \mprj_io_dm[13] , \mprj_io_dm[12] }),
+ .pad_gpio_holdover(\mprj_io_holdover[4] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[4] ),
+ .pad_gpio_in(\mprj_io_in[4] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[4] ),
+ .pad_gpio_out(\mprj_io_out[4] ),
+ .pad_gpio_outenb(\mprj_io_oeb[4] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[4] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[4] ),
+ .resetn(\gpio_resetn_1[3] ),
+ .resetn_out(\gpio_resetn_1[4] ),
+ .serial_clock(\gpio_clock_1[3] ),
+ .serial_clock_out(\gpio_clock_1[4] ),
+ .serial_data_in(\gpio_serial_link_1[3] ),
+ .serial_data_out(\gpio_serial_link_1[4] ),
+ .serial_load(\gpio_load_1[3] ),
+ .serial_load_out(\gpio_load_1[4] ),
+ .user_gpio_in(\user_io_in[4] ),
+ .user_gpio_oeb(\user_io_oeb[4] ),
+ .user_gpio_out(\user_io_out[4] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1a[3] (
+ .gpio_defaults({ \gpio_defaults[77] , \gpio_defaults[76] , \gpio_defaults[75] , \gpio_defaults[74] , \gpio_defaults[73] , \gpio_defaults[72] , \gpio_defaults[71] , \gpio_defaults[70] , \gpio_defaults[69] , \gpio_defaults[68] , \gpio_defaults[67] , \gpio_defaults[66] , \gpio_defaults[65] }),
+ .mgmt_gpio_in(\mgmt_io_in[5] ),
+ .mgmt_gpio_oeb(\mprj_io_one[5] ),
+ .mgmt_gpio_out(\mgmt_io_out[5] ),
+ .one(\mprj_io_one[5] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[5] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[5] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[5] ),
+ .pad_gpio_dm({ \mprj_io_dm[17] , \mprj_io_dm[16] , \mprj_io_dm[15] }),
+ .pad_gpio_holdover(\mprj_io_holdover[5] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[5] ),
+ .pad_gpio_in(\mprj_io_in[5] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[5] ),
+ .pad_gpio_out(\mprj_io_out[5] ),
+ .pad_gpio_outenb(\mprj_io_oeb[5] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[5] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[5] ),
+ .resetn(\gpio_resetn_1[4] ),
+ .resetn_out(\gpio_resetn_1[5] ),
+ .serial_clock(\gpio_clock_1[4] ),
+ .serial_clock_out(\gpio_clock_1[5] ),
+ .serial_data_in(\gpio_serial_link_1[4] ),
+ .serial_data_out(\gpio_serial_link_1[5] ),
+ .serial_load(\gpio_load_1[4] ),
+ .serial_load_out(\gpio_load_1[5] ),
+ .user_gpio_in(\user_io_in[5] ),
+ .user_gpio_oeb(\user_io_oeb[5] ),
+ .user_gpio_out(\user_io_out[5] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1a[4] (
+ .gpio_defaults({ \gpio_defaults[90] , \gpio_defaults[89] , \gpio_defaults[88] , \gpio_defaults[87] , \gpio_defaults[86] , \gpio_defaults[85] , \gpio_defaults[84] , \gpio_defaults[83] , \gpio_defaults[82] , \gpio_defaults[81] , \gpio_defaults[80] , \gpio_defaults[79] , \gpio_defaults[78] }),
+ .mgmt_gpio_in(\mgmt_io_in[6] ),
+ .mgmt_gpio_oeb(\mprj_io_one[6] ),
+ .mgmt_gpio_out(\mgmt_io_out[6] ),
+ .one(\mprj_io_one[6] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[6] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[6] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[6] ),
+ .pad_gpio_dm({ \mprj_io_dm[20] , \mprj_io_dm[19] , \mprj_io_dm[18] }),
+ .pad_gpio_holdover(\mprj_io_holdover[6] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[6] ),
+ .pad_gpio_in(\mprj_io_in[6] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[6] ),
+ .pad_gpio_out(\mprj_io_out[6] ),
+ .pad_gpio_outenb(\mprj_io_oeb[6] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[6] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[6] ),
+ .resetn(\gpio_resetn_1[5] ),
+ .resetn_out(\gpio_resetn_1[6] ),
+ .serial_clock(\gpio_clock_1[5] ),
+ .serial_clock_out(\gpio_clock_1[6] ),
+ .serial_data_in(\gpio_serial_link_1[5] ),
+ .serial_data_out(\gpio_serial_link_1[6] ),
+ .serial_load(\gpio_load_1[5] ),
+ .serial_load_out(\gpio_load_1[6] ),
+ .user_gpio_in(\user_io_in[6] ),
+ .user_gpio_oeb(\user_io_oeb[6] ),
+ .user_gpio_out(\user_io_out[6] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_1a[5] (
+ .gpio_defaults({ \gpio_defaults[103] , \gpio_defaults[102] , \gpio_defaults[101] , \gpio_defaults[100] , \gpio_defaults[99] , \gpio_defaults[98] , \gpio_defaults[97] , \gpio_defaults[96] , \gpio_defaults[95] , \gpio_defaults[94] , \gpio_defaults[93] , \gpio_defaults[92] , \gpio_defaults[91] }),
+ .mgmt_gpio_in(\mgmt_io_in[7] ),
+ .mgmt_gpio_oeb(\mprj_io_one[7] ),
+ .mgmt_gpio_out(\mgmt_io_out[7] ),
+ .one(\mprj_io_one[7] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[7] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[7] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[7] ),
+ .pad_gpio_dm({ \mprj_io_dm[23] , \mprj_io_dm[22] , \mprj_io_dm[21] }),
+ .pad_gpio_holdover(\mprj_io_holdover[7] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[7] ),
+ .pad_gpio_in(\mprj_io_in[7] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[7] ),
+ .pad_gpio_out(\mprj_io_out[7] ),
+ .pad_gpio_outenb(\mprj_io_oeb[7] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[7] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[7] ),
+ .resetn(\gpio_resetn_1[6] ),
+ .resetn_out(\gpio_resetn_1[7] ),
+ .serial_clock(\gpio_clock_1[6] ),
+ .serial_clock_out(\gpio_clock_1[7] ),
+ .serial_data_in(\gpio_serial_link_1[6] ),
+ .serial_data_out(\gpio_serial_link_1[7] ),
+ .serial_load(\gpio_load_1[6] ),
+ .serial_load_out(\gpio_load_1[7] ),
+ .user_gpio_in(\user_io_in[7] ),
+ .user_gpio_oeb(\user_io_oeb[7] ),
+ .user_gpio_out(\user_io_out[7] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_2[0] (
+ .gpio_defaults({ \gpio_defaults[259] , \gpio_defaults[258] , \gpio_defaults[257] , \gpio_defaults[256] , \gpio_defaults[255] , \gpio_defaults[254] , \gpio_defaults[253] , \gpio_defaults[252] , \gpio_defaults[251] , \gpio_defaults[250] , \gpio_defaults[249] , \gpio_defaults[248] , \gpio_defaults[247] }),
+ .mgmt_gpio_in(\mgmt_io_in[19] ),
+ .mgmt_gpio_oeb(\mprj_io_one[19] ),
+ .mgmt_gpio_out(\mgmt_io_out[19] ),
+ .one(\mprj_io_one[19] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[19] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[19] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[19] ),
+ .pad_gpio_dm({ \mprj_io_dm[59] , \mprj_io_dm[58] , \mprj_io_dm[57] }),
+ .pad_gpio_holdover(\mprj_io_holdover[19] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[19] ),
+ .pad_gpio_in(\mprj_io_in[19] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[19] ),
+ .pad_gpio_out(\mprj_io_out[19] ),
+ .pad_gpio_outenb(\mprj_io_oeb[19] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[19] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[19] ),
+ .resetn(\gpio_resetn_2[1] ),
+ .resetn_out(\gpio_resetn_2[0] ),
+ .serial_clock(\gpio_clock_2[1] ),
+ .serial_clock_out(\gpio_clock_2[0] ),
+ .serial_data_in(\gpio_serial_link_2[1] ),
+ .serial_data_out(\gpio_serial_link_2[0] ),
+ .serial_load(\gpio_load_2[1] ),
+ .serial_load_out(\gpio_load_2[0] ),
+ .user_gpio_in(\user_io_in[19] ),
+ .user_gpio_oeb(\user_io_oeb[19] ),
+ .user_gpio_out(\user_io_out[19] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_2[10] (
+ .gpio_defaults({ \gpio_defaults[389] , \gpio_defaults[388] , \gpio_defaults[387] , \gpio_defaults[386] , \gpio_defaults[385] , \gpio_defaults[384] , \gpio_defaults[383] , \gpio_defaults[382] , \gpio_defaults[381] , \gpio_defaults[380] , \gpio_defaults[379] , \gpio_defaults[378] , \gpio_defaults[377] }),
+ .mgmt_gpio_in(\mgmt_io_in[29] ),
+ .mgmt_gpio_oeb(\mprj_io_one[29] ),
+ .mgmt_gpio_out(\mgmt_io_out[29] ),
+ .one(\mprj_io_one[29] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[29] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[29] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[29] ),
+ .pad_gpio_dm({ \mprj_io_dm[89] , \mprj_io_dm[88] , \mprj_io_dm[87] }),
+ .pad_gpio_holdover(\mprj_io_holdover[29] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[29] ),
+ .pad_gpio_in(\mprj_io_in[29] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[29] ),
+ .pad_gpio_out(\mprj_io_out[29] ),
+ .pad_gpio_outenb(\mprj_io_oeb[29] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[29] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[29] ),
+ .resetn(\gpio_resetn_2[11] ),
+ .resetn_out(\gpio_resetn_2[10] ),
+ .serial_clock(\gpio_clock_2[11] ),
+ .serial_clock_out(\gpio_clock_2[10] ),
+ .serial_data_in(\gpio_serial_link_2[11] ),
+ .serial_data_out(\gpio_serial_link_2[10] ),
+ .serial_load(\gpio_load_2[11] ),
+ .serial_load_out(\gpio_load_2[10] ),
+ .user_gpio_in(\user_io_in[29] ),
+ .user_gpio_oeb(\user_io_oeb[29] ),
+ .user_gpio_out(\user_io_out[29] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_2[11] (
+ .gpio_defaults({ \gpio_defaults[402] , \gpio_defaults[401] , \gpio_defaults[400] , \gpio_defaults[399] , \gpio_defaults[398] , \gpio_defaults[397] , \gpio_defaults[396] , \gpio_defaults[395] , \gpio_defaults[394] , \gpio_defaults[393] , \gpio_defaults[392] , \gpio_defaults[391] , \gpio_defaults[390] }),
+ .mgmt_gpio_in(\mgmt_io_in[30] ),
+ .mgmt_gpio_oeb(\mprj_io_one[30] ),
+ .mgmt_gpio_out(\mgmt_io_out[30] ),
+ .one(\mprj_io_one[30] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[30] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[30] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[30] ),
+ .pad_gpio_dm({ \mprj_io_dm[92] , \mprj_io_dm[91] , \mprj_io_dm[90] }),
+ .pad_gpio_holdover(\mprj_io_holdover[30] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[30] ),
+ .pad_gpio_in(\mprj_io_in[30] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[30] ),
+ .pad_gpio_out(\mprj_io_out[30] ),
+ .pad_gpio_outenb(\mprj_io_oeb[30] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[30] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[30] ),
+ .resetn(\gpio_resetn_2[12] ),
+ .resetn_out(\gpio_resetn_2[11] ),
+ .serial_clock(\gpio_clock_2[12] ),
+ .serial_clock_out(\gpio_clock_2[11] ),
+ .serial_data_in(\gpio_serial_link_2[12] ),
+ .serial_data_out(\gpio_serial_link_2[11] ),
+ .serial_load(\gpio_load_2[12] ),
+ .serial_load_out(\gpio_load_2[11] ),
+ .user_gpio_in(\user_io_in[30] ),
+ .user_gpio_oeb(\user_io_oeb[30] ),
+ .user_gpio_out(\user_io_out[30] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_2[12] (
+ .gpio_defaults({ \gpio_defaults[415] , \gpio_defaults[414] , \gpio_defaults[413] , \gpio_defaults[412] , \gpio_defaults[411] , \gpio_defaults[410] , \gpio_defaults[409] , \gpio_defaults[408] , \gpio_defaults[407] , \gpio_defaults[406] , \gpio_defaults[405] , \gpio_defaults[404] , \gpio_defaults[403] }),
+ .mgmt_gpio_in(\mgmt_io_in[31] ),
+ .mgmt_gpio_oeb(\mprj_io_one[31] ),
+ .mgmt_gpio_out(\mgmt_io_out[31] ),
+ .one(\mprj_io_one[31] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[31] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[31] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[31] ),
+ .pad_gpio_dm({ \mprj_io_dm[95] , \mprj_io_dm[94] , \mprj_io_dm[93] }),
+ .pad_gpio_holdover(\mprj_io_holdover[31] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[31] ),
+ .pad_gpio_in(\mprj_io_in[31] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[31] ),
+ .pad_gpio_out(\mprj_io_out[31] ),
+ .pad_gpio_outenb(\mprj_io_oeb[31] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[31] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[31] ),
+ .resetn(\gpio_resetn_2[13] ),
+ .resetn_out(\gpio_resetn_2[12] ),
+ .serial_clock(\gpio_clock_2[13] ),
+ .serial_clock_out(\gpio_clock_2[12] ),
+ .serial_data_in(\gpio_serial_link_2[13] ),
+ .serial_data_out(\gpio_serial_link_2[12] ),
+ .serial_load(\gpio_load_2[13] ),
+ .serial_load_out(\gpio_load_2[12] ),
+ .user_gpio_in(\user_io_in[31] ),
+ .user_gpio_oeb(\user_io_oeb[31] ),
+ .user_gpio_out(\user_io_out[31] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_2[13] (
+ .gpio_defaults({ \gpio_defaults[428] , \gpio_defaults[427] , \gpio_defaults[426] , \gpio_defaults[425] , \gpio_defaults[424] , \gpio_defaults[423] , \gpio_defaults[422] , \gpio_defaults[421] , \gpio_defaults[420] , \gpio_defaults[419] , \gpio_defaults[418] , \gpio_defaults[417] , \gpio_defaults[416] }),
+ .mgmt_gpio_in(\mgmt_io_in[32] ),
+ .mgmt_gpio_oeb(\mprj_io_one[32] ),
+ .mgmt_gpio_out(\mgmt_io_out[32] ),
+ .one(\mprj_io_one[32] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[32] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[32] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[32] ),
+ .pad_gpio_dm({ \mprj_io_dm[98] , \mprj_io_dm[97] , \mprj_io_dm[96] }),
+ .pad_gpio_holdover(\mprj_io_holdover[32] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[32] ),
+ .pad_gpio_in(\mprj_io_in[32] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[32] ),
+ .pad_gpio_out(\mprj_io_out[32] ),
+ .pad_gpio_outenb(\mprj_io_oeb[32] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[32] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[32] ),
+ .resetn(\gpio_resetn_2[14] ),
+ .resetn_out(\gpio_resetn_2[13] ),
+ .serial_clock(\gpio_clock_2[14] ),
+ .serial_clock_out(\gpio_clock_2[13] ),
+ .serial_data_in(\gpio_serial_link_2[14] ),
+ .serial_data_out(\gpio_serial_link_2[13] ),
+ .serial_load(\gpio_load_2[14] ),
+ .serial_load_out(\gpio_load_2[13] ),
+ .user_gpio_in(\user_io_in[32] ),
+ .user_gpio_oeb(\user_io_oeb[32] ),
+ .user_gpio_out(\user_io_out[32] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_2[14] (
+ .gpio_defaults({ \gpio_defaults[441] , \gpio_defaults[440] , \gpio_defaults[439] , \gpio_defaults[438] , \gpio_defaults[437] , \gpio_defaults[436] , \gpio_defaults[435] , \gpio_defaults[434] , \gpio_defaults[433] , \gpio_defaults[432] , \gpio_defaults[431] , \gpio_defaults[430] , \gpio_defaults[429] }),
+ .mgmt_gpio_in(\mgmt_io_in[33] ),
+ .mgmt_gpio_oeb(\mprj_io_one[33] ),
+ .mgmt_gpio_out(\mgmt_io_out[33] ),
+ .one(\mprj_io_one[33] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[33] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[33] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[33] ),
+ .pad_gpio_dm({ \mprj_io_dm[101] , \mprj_io_dm[100] , \mprj_io_dm[99] }),
+ .pad_gpio_holdover(\mprj_io_holdover[33] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[33] ),
+ .pad_gpio_in(\mprj_io_in[33] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[33] ),
+ .pad_gpio_out(\mprj_io_out[33] ),
+ .pad_gpio_outenb(\mprj_io_oeb[33] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[33] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[33] ),
+ .resetn(\gpio_resetn_2[15] ),
+ .resetn_out(\gpio_resetn_2[14] ),
+ .serial_clock(\gpio_clock_2[15] ),
+ .serial_clock_out(\gpio_clock_2[14] ),
+ .serial_data_in(\gpio_serial_link_2[15] ),
+ .serial_data_out(\gpio_serial_link_2[14] ),
+ .serial_load(\gpio_load_2[15] ),
+ .serial_load_out(\gpio_load_2[14] ),
+ .user_gpio_in(\user_io_in[33] ),
+ .user_gpio_oeb(\user_io_oeb[33] ),
+ .user_gpio_out(\user_io_out[33] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_2[15] (
+ .gpio_defaults({ \gpio_defaults[454] , \gpio_defaults[453] , \gpio_defaults[452] , \gpio_defaults[451] , \gpio_defaults[450] , \gpio_defaults[449] , \gpio_defaults[448] , \gpio_defaults[447] , \gpio_defaults[446] , \gpio_defaults[445] , \gpio_defaults[444] , \gpio_defaults[443] , \gpio_defaults[442] }),
+ .mgmt_gpio_in(\mgmt_io_in[34] ),
+ .mgmt_gpio_oeb(\mprj_io_one[34] ),
+ .mgmt_gpio_out(\mgmt_io_out[34] ),
+ .one(\mprj_io_one[34] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[34] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[34] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[34] ),
+ .pad_gpio_dm({ \mprj_io_dm[104] , \mprj_io_dm[103] , \mprj_io_dm[102] }),
+ .pad_gpio_holdover(\mprj_io_holdover[34] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[34] ),
+ .pad_gpio_in(\mprj_io_in[34] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[34] ),
+ .pad_gpio_out(\mprj_io_out[34] ),
+ .pad_gpio_outenb(\mprj_io_oeb[34] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[34] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[34] ),
+ .resetn(\gpio_resetn_2[16] ),
+ .resetn_out(\gpio_resetn_2[15] ),
+ .serial_clock(\gpio_clock_2[16] ),
+ .serial_clock_out(\gpio_clock_2[15] ),
+ .serial_data_in(\gpio_serial_link_2[16] ),
+ .serial_data_out(\gpio_serial_link_2[15] ),
+ .serial_load(\gpio_load_2[16] ),
+ .serial_load_out(\gpio_load_2[15] ),
+ .user_gpio_in(\user_io_in[34] ),
+ .user_gpio_oeb(\user_io_oeb[34] ),
+ .user_gpio_out(\user_io_out[34] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_2[1] (
+ .gpio_defaults({ \gpio_defaults[272] , \gpio_defaults[271] , \gpio_defaults[270] , \gpio_defaults[269] , \gpio_defaults[268] , \gpio_defaults[267] , \gpio_defaults[266] , \gpio_defaults[265] , \gpio_defaults[264] , \gpio_defaults[263] , \gpio_defaults[262] , \gpio_defaults[261] , \gpio_defaults[260] }),
+ .mgmt_gpio_in(\mgmt_io_in[20] ),
+ .mgmt_gpio_oeb(\mprj_io_one[20] ),
+ .mgmt_gpio_out(\mgmt_io_out[20] ),
+ .one(\mprj_io_one[20] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[20] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[20] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[20] ),
+ .pad_gpio_dm({ \mprj_io_dm[62] , \mprj_io_dm[61] , \mprj_io_dm[60] }),
+ .pad_gpio_holdover(\mprj_io_holdover[20] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[20] ),
+ .pad_gpio_in(\mprj_io_in[20] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[20] ),
+ .pad_gpio_out(\mprj_io_out[20] ),
+ .pad_gpio_outenb(\mprj_io_oeb[20] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[20] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[20] ),
+ .resetn(\gpio_resetn_2[2] ),
+ .resetn_out(\gpio_resetn_2[1] ),
+ .serial_clock(\gpio_clock_2[2] ),
+ .serial_clock_out(\gpio_clock_2[1] ),
+ .serial_data_in(\gpio_serial_link_2[2] ),
+ .serial_data_out(\gpio_serial_link_2[1] ),
+ .serial_load(\gpio_load_2[2] ),
+ .serial_load_out(\gpio_load_2[1] ),
+ .user_gpio_in(\user_io_in[20] ),
+ .user_gpio_oeb(\user_io_oeb[20] ),
+ .user_gpio_out(\user_io_out[20] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_2[2] (
+ .gpio_defaults({ \gpio_defaults[285] , \gpio_defaults[284] , \gpio_defaults[283] , \gpio_defaults[282] , \gpio_defaults[281] , \gpio_defaults[280] , \gpio_defaults[279] , \gpio_defaults[278] , \gpio_defaults[277] , \gpio_defaults[276] , \gpio_defaults[275] , \gpio_defaults[274] , \gpio_defaults[273] }),
+ .mgmt_gpio_in(\mgmt_io_in[21] ),
+ .mgmt_gpio_oeb(\mprj_io_one[21] ),
+ .mgmt_gpio_out(\mgmt_io_out[21] ),
+ .one(\mprj_io_one[21] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[21] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[21] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[21] ),
+ .pad_gpio_dm({ \mprj_io_dm[65] , \mprj_io_dm[64] , \mprj_io_dm[63] }),
+ .pad_gpio_holdover(\mprj_io_holdover[21] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[21] ),
+ .pad_gpio_in(\mprj_io_in[21] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[21] ),
+ .pad_gpio_out(\mprj_io_out[21] ),
+ .pad_gpio_outenb(\mprj_io_oeb[21] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[21] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[21] ),
+ .resetn(\gpio_resetn_2[3] ),
+ .resetn_out(\gpio_resetn_2[2] ),
+ .serial_clock(\gpio_clock_2[3] ),
+ .serial_clock_out(\gpio_clock_2[2] ),
+ .serial_data_in(\gpio_serial_link_2[3] ),
+ .serial_data_out(\gpio_serial_link_2[2] ),
+ .serial_load(\gpio_load_2[3] ),
+ .serial_load_out(\gpio_load_2[2] ),
+ .user_gpio_in(\user_io_in[21] ),
+ .user_gpio_oeb(\user_io_oeb[21] ),
+ .user_gpio_out(\user_io_out[21] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_2[3] (
+ .gpio_defaults({ \gpio_defaults[298] , \gpio_defaults[297] , \gpio_defaults[296] , \gpio_defaults[295] , \gpio_defaults[294] , \gpio_defaults[293] , \gpio_defaults[292] , \gpio_defaults[291] , \gpio_defaults[290] , \gpio_defaults[289] , \gpio_defaults[288] , \gpio_defaults[287] , \gpio_defaults[286] }),
+ .mgmt_gpio_in(\mgmt_io_in[22] ),
+ .mgmt_gpio_oeb(\mprj_io_one[22] ),
+ .mgmt_gpio_out(\mgmt_io_out[22] ),
+ .one(\mprj_io_one[22] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[22] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[22] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[22] ),
+ .pad_gpio_dm({ \mprj_io_dm[68] , \mprj_io_dm[67] , \mprj_io_dm[66] }),
+ .pad_gpio_holdover(\mprj_io_holdover[22] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[22] ),
+ .pad_gpio_in(\mprj_io_in[22] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[22] ),
+ .pad_gpio_out(\mprj_io_out[22] ),
+ .pad_gpio_outenb(\mprj_io_oeb[22] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[22] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[22] ),
+ .resetn(\gpio_resetn_2[4] ),
+ .resetn_out(\gpio_resetn_2[3] ),
+ .serial_clock(\gpio_clock_2[4] ),
+ .serial_clock_out(\gpio_clock_2[3] ),
+ .serial_data_in(\gpio_serial_link_2[4] ),
+ .serial_data_out(\gpio_serial_link_2[3] ),
+ .serial_load(\gpio_load_2[4] ),
+ .serial_load_out(\gpio_load_2[3] ),
+ .user_gpio_in(\user_io_in[22] ),
+ .user_gpio_oeb(\user_io_oeb[22] ),
+ .user_gpio_out(\user_io_out[22] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_2[4] (
+ .gpio_defaults({ \gpio_defaults[311] , \gpio_defaults[310] , \gpio_defaults[309] , \gpio_defaults[308] , \gpio_defaults[307] , \gpio_defaults[306] , \gpio_defaults[305] , \gpio_defaults[304] , \gpio_defaults[303] , \gpio_defaults[302] , \gpio_defaults[301] , \gpio_defaults[300] , \gpio_defaults[299] }),
+ .mgmt_gpio_in(\mgmt_io_in[23] ),
+ .mgmt_gpio_oeb(\mprj_io_one[23] ),
+ .mgmt_gpio_out(\mgmt_io_out[23] ),
+ .one(\mprj_io_one[23] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[23] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[23] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[23] ),
+ .pad_gpio_dm({ \mprj_io_dm[71] , \mprj_io_dm[70] , \mprj_io_dm[69] }),
+ .pad_gpio_holdover(\mprj_io_holdover[23] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[23] ),
+ .pad_gpio_in(\mprj_io_in[23] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[23] ),
+ .pad_gpio_out(\mprj_io_out[23] ),
+ .pad_gpio_outenb(\mprj_io_oeb[23] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[23] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[23] ),
+ .resetn(\gpio_resetn_2[5] ),
+ .resetn_out(\gpio_resetn_2[4] ),
+ .serial_clock(\gpio_clock_2[5] ),
+ .serial_clock_out(\gpio_clock_2[4] ),
+ .serial_data_in(\gpio_serial_link_2[5] ),
+ .serial_data_out(\gpio_serial_link_2[4] ),
+ .serial_load(\gpio_load_2[5] ),
+ .serial_load_out(\gpio_load_2[4] ),
+ .user_gpio_in(\user_io_in[23] ),
+ .user_gpio_oeb(\user_io_oeb[23] ),
+ .user_gpio_out(\user_io_out[23] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_2[5] (
+ .gpio_defaults({ \gpio_defaults[324] , \gpio_defaults[323] , \gpio_defaults[322] , \gpio_defaults[321] , \gpio_defaults[320] , \gpio_defaults[319] , \gpio_defaults[318] , \gpio_defaults[317] , \gpio_defaults[316] , \gpio_defaults[315] , \gpio_defaults[314] , \gpio_defaults[313] , \gpio_defaults[312] }),
+ .mgmt_gpio_in(\mgmt_io_in[24] ),
+ .mgmt_gpio_oeb(\mprj_io_one[24] ),
+ .mgmt_gpio_out(\mgmt_io_out[24] ),
+ .one(\mprj_io_one[24] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[24] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[24] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[24] ),
+ .pad_gpio_dm({ \mprj_io_dm[74] , \mprj_io_dm[73] , \mprj_io_dm[72] }),
+ .pad_gpio_holdover(\mprj_io_holdover[24] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[24] ),
+ .pad_gpio_in(\mprj_io_in[24] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[24] ),
+ .pad_gpio_out(\mprj_io_out[24] ),
+ .pad_gpio_outenb(\mprj_io_oeb[24] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[24] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[24] ),
+ .resetn(\gpio_resetn_2[6] ),
+ .resetn_out(\gpio_resetn_2[5] ),
+ .serial_clock(\gpio_clock_2[6] ),
+ .serial_clock_out(\gpio_clock_2[5] ),
+ .serial_data_in(\gpio_serial_link_2[6] ),
+ .serial_data_out(\gpio_serial_link_2[5] ),
+ .serial_load(\gpio_load_2[6] ),
+ .serial_load_out(\gpio_load_2[5] ),
+ .user_gpio_in(\user_io_in[24] ),
+ .user_gpio_oeb(\user_io_oeb[24] ),
+ .user_gpio_out(\user_io_out[24] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_2[6] (
+ .gpio_defaults({ \gpio_defaults[337] , \gpio_defaults[336] , \gpio_defaults[335] , \gpio_defaults[334] , \gpio_defaults[333] , \gpio_defaults[332] , \gpio_defaults[331] , \gpio_defaults[330] , \gpio_defaults[329] , \gpio_defaults[328] , \gpio_defaults[327] , \gpio_defaults[326] , \gpio_defaults[325] }),
+ .mgmt_gpio_in(\mgmt_io_in[25] ),
+ .mgmt_gpio_oeb(\mprj_io_one[25] ),
+ .mgmt_gpio_out(\mgmt_io_out[25] ),
+ .one(\mprj_io_one[25] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[25] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[25] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[25] ),
+ .pad_gpio_dm({ \mprj_io_dm[77] , \mprj_io_dm[76] , \mprj_io_dm[75] }),
+ .pad_gpio_holdover(\mprj_io_holdover[25] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[25] ),
+ .pad_gpio_in(\mprj_io_in[25] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[25] ),
+ .pad_gpio_out(\mprj_io_out[25] ),
+ .pad_gpio_outenb(\mprj_io_oeb[25] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[25] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[25] ),
+ .resetn(\gpio_resetn_2[7] ),
+ .resetn_out(\gpio_resetn_2[6] ),
+ .serial_clock(\gpio_clock_2[7] ),
+ .serial_clock_out(\gpio_clock_2[6] ),
+ .serial_data_in(\gpio_serial_link_2[7] ),
+ .serial_data_out(\gpio_serial_link_2[6] ),
+ .serial_load(\gpio_load_2[7] ),
+ .serial_load_out(\gpio_load_2[6] ),
+ .user_gpio_in(\user_io_in[25] ),
+ .user_gpio_oeb(\user_io_oeb[25] ),
+ .user_gpio_out(\user_io_out[25] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_2[7] (
+ .gpio_defaults({ \gpio_defaults[350] , \gpio_defaults[349] , \gpio_defaults[348] , \gpio_defaults[347] , \gpio_defaults[346] , \gpio_defaults[345] , \gpio_defaults[344] , \gpio_defaults[343] , \gpio_defaults[342] , \gpio_defaults[341] , \gpio_defaults[340] , \gpio_defaults[339] , \gpio_defaults[338] }),
+ .mgmt_gpio_in(\mgmt_io_in[26] ),
+ .mgmt_gpio_oeb(\mprj_io_one[26] ),
+ .mgmt_gpio_out(\mgmt_io_out[26] ),
+ .one(\mprj_io_one[26] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[26] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[26] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[26] ),
+ .pad_gpio_dm({ \mprj_io_dm[80] , \mprj_io_dm[79] , \mprj_io_dm[78] }),
+ .pad_gpio_holdover(\mprj_io_holdover[26] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[26] ),
+ .pad_gpio_in(\mprj_io_in[26] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[26] ),
+ .pad_gpio_out(\mprj_io_out[26] ),
+ .pad_gpio_outenb(\mprj_io_oeb[26] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[26] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[26] ),
+ .resetn(\gpio_resetn_2[8] ),
+ .resetn_out(\gpio_resetn_2[7] ),
+ .serial_clock(\gpio_clock_2[8] ),
+ .serial_clock_out(\gpio_clock_2[7] ),
+ .serial_data_in(\gpio_serial_link_2[8] ),
+ .serial_data_out(\gpio_serial_link_2[7] ),
+ .serial_load(\gpio_load_2[8] ),
+ .serial_load_out(\gpio_load_2[7] ),
+ .user_gpio_in(\user_io_in[26] ),
+ .user_gpio_oeb(\user_io_oeb[26] ),
+ .user_gpio_out(\user_io_out[26] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_2[8] (
+ .gpio_defaults({ \gpio_defaults[363] , \gpio_defaults[362] , \gpio_defaults[361] , \gpio_defaults[360] , \gpio_defaults[359] , \gpio_defaults[358] , \gpio_defaults[357] , \gpio_defaults[356] , \gpio_defaults[355] , \gpio_defaults[354] , \gpio_defaults[353] , \gpio_defaults[352] , \gpio_defaults[351] }),
+ .mgmt_gpio_in(\mgmt_io_in[27] ),
+ .mgmt_gpio_oeb(\mprj_io_one[27] ),
+ .mgmt_gpio_out(\mgmt_io_out[27] ),
+ .one(\mprj_io_one[27] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[27] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[27] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[27] ),
+ .pad_gpio_dm({ \mprj_io_dm[83] , \mprj_io_dm[82] , \mprj_io_dm[81] }),
+ .pad_gpio_holdover(\mprj_io_holdover[27] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[27] ),
+ .pad_gpio_in(\mprj_io_in[27] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[27] ),
+ .pad_gpio_out(\mprj_io_out[27] ),
+ .pad_gpio_outenb(\mprj_io_oeb[27] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[27] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[27] ),
+ .resetn(\gpio_resetn_2[9] ),
+ .resetn_out(\gpio_resetn_2[8] ),
+ .serial_clock(\gpio_clock_2[9] ),
+ .serial_clock_out(\gpio_clock_2[8] ),
+ .serial_data_in(\gpio_serial_link_2[9] ),
+ .serial_data_out(\gpio_serial_link_2[8] ),
+ .serial_load(\gpio_load_2[9] ),
+ .serial_load_out(\gpio_load_2[8] ),
+ .user_gpio_in(\user_io_in[27] ),
+ .user_gpio_oeb(\user_io_oeb[27] ),
+ .user_gpio_out(\user_io_out[27] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_control_block \gpio_control_in_2[9] (
+ .gpio_defaults({ \gpio_defaults[376] , \gpio_defaults[375] , \gpio_defaults[374] , \gpio_defaults[373] , \gpio_defaults[372] , \gpio_defaults[371] , \gpio_defaults[370] , \gpio_defaults[369] , \gpio_defaults[368] , \gpio_defaults[367] , \gpio_defaults[366] , \gpio_defaults[365] , \gpio_defaults[364] }),
+ .mgmt_gpio_in(\mgmt_io_in[28] ),
+ .mgmt_gpio_oeb(\mprj_io_one[28] ),
+ .mgmt_gpio_out(\mgmt_io_out[28] ),
+ .one(\mprj_io_one[28] ),
+ .pad_gpio_ana_en(\mprj_io_analog_en[28] ),
+ .pad_gpio_ana_pol(\mprj_io_analog_pol[28] ),
+ .pad_gpio_ana_sel(\mprj_io_analog_sel[28] ),
+ .pad_gpio_dm({ \mprj_io_dm[86] , \mprj_io_dm[85] , \mprj_io_dm[84] }),
+ .pad_gpio_holdover(\mprj_io_holdover[28] ),
+ .pad_gpio_ib_mode_sel(\mprj_io_ib_mode_sel[28] ),
+ .pad_gpio_in(\mprj_io_in[28] ),
+ .pad_gpio_inenb(\mprj_io_inp_dis[28] ),
+ .pad_gpio_out(\mprj_io_out[28] ),
+ .pad_gpio_outenb(\mprj_io_oeb[28] ),
+ .pad_gpio_slow_sel(\mprj_io_slow_sel[28] ),
+ .pad_gpio_vtrip_sel(\mprj_io_vtrip_sel[28] ),
+ .resetn(\gpio_resetn_2[10] ),
+ .resetn_out(\gpio_resetn_2[9] ),
+ .serial_clock(\gpio_clock_2[10] ),
+ .serial_clock_out(\gpio_clock_2[9] ),
+ .serial_data_in(\gpio_serial_link_2[10] ),
+ .serial_data_out(\gpio_serial_link_2[9] ),
+ .serial_load(\gpio_load_2[10] ),
+ .serial_load_out(\gpio_load_2[9] ),
+ .user_gpio_in(\user_io_in[28] ),
+ .user_gpio_oeb(\user_io_oeb[28] ),
+ .user_gpio_out(\user_io_out[28] ),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .zero()
+ );
+ gpio_defaults_block_1803 gpio_defaults_block_0 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[12] , \gpio_defaults[11] , \gpio_defaults[10] , \gpio_defaults[9] , \gpio_defaults[8] , \gpio_defaults[7] , \gpio_defaults[6] , \gpio_defaults[5] , \gpio_defaults[4] , \gpio_defaults[3] , \gpio_defaults[2] , \gpio_defaults[1] , \gpio_defaults[0] })
+ );
+ gpio_defaults_block_1803 gpio_defaults_block_1 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[25] , \gpio_defaults[24] , \gpio_defaults[23] , \gpio_defaults[22] , \gpio_defaults[21] , \gpio_defaults[20] , \gpio_defaults[19] , \gpio_defaults[18] , \gpio_defaults[17] , \gpio_defaults[16] , \gpio_defaults[15] , \gpio_defaults[14] , \gpio_defaults[13] })
+ );
+ gpio_defaults_block_0403 gpio_defaults_block_10 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[142] , \gpio_defaults[141] , \gpio_defaults[140] , \gpio_defaults[139] , \gpio_defaults[138] , \gpio_defaults[137] , \gpio_defaults[136] , \gpio_defaults[135] , \gpio_defaults[134] , \gpio_defaults[133] , \gpio_defaults[132] , \gpio_defaults[131] , \gpio_defaults[130] })
+ );
+ gpio_defaults_block_0403 gpio_defaults_block_11 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[155] , \gpio_defaults[154] , \gpio_defaults[153] , \gpio_defaults[152] , \gpio_defaults[151] , \gpio_defaults[150] , \gpio_defaults[149] , \gpio_defaults[148] , \gpio_defaults[147] , \gpio_defaults[146] , \gpio_defaults[145] , \gpio_defaults[144] , \gpio_defaults[143] })
+ );
+ gpio_defaults_block_0403 gpio_defaults_block_12 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[168] , \gpio_defaults[167] , \gpio_defaults[166] , \gpio_defaults[165] , \gpio_defaults[164] , \gpio_defaults[163] , \gpio_defaults[162] , \gpio_defaults[161] , \gpio_defaults[160] , \gpio_defaults[159] , \gpio_defaults[158] , \gpio_defaults[157] , \gpio_defaults[156] })
+ );
+ gpio_defaults_block_0403 gpio_defaults_block_13 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[181] , \gpio_defaults[180] , \gpio_defaults[179] , \gpio_defaults[178] , \gpio_defaults[177] , \gpio_defaults[176] , \gpio_defaults[175] , \gpio_defaults[174] , \gpio_defaults[173] , \gpio_defaults[172] , \gpio_defaults[171] , \gpio_defaults[170] , \gpio_defaults[169] })
+ );
+ gpio_defaults_block_0403 gpio_defaults_block_14 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[194] , \gpio_defaults[193] , \gpio_defaults[192] , \gpio_defaults[191] , \gpio_defaults[190] , \gpio_defaults[189] , \gpio_defaults[188] , \gpio_defaults[187] , \gpio_defaults[186] , \gpio_defaults[185] , \gpio_defaults[184] , \gpio_defaults[183] , \gpio_defaults[182] })
+ );
+ gpio_defaults_block_0403 gpio_defaults_block_15 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[207] , \gpio_defaults[206] , \gpio_defaults[205] , \gpio_defaults[204] , \gpio_defaults[203] , \gpio_defaults[202] , \gpio_defaults[201] , \gpio_defaults[200] , \gpio_defaults[199] , \gpio_defaults[198] , \gpio_defaults[197] , \gpio_defaults[196] , \gpio_defaults[195] })
+ );
+ gpio_defaults_block_0403 gpio_defaults_block_16 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[220] , \gpio_defaults[219] , \gpio_defaults[218] , \gpio_defaults[217] , \gpio_defaults[216] , \gpio_defaults[215] , \gpio_defaults[214] , \gpio_defaults[213] , \gpio_defaults[212] , \gpio_defaults[211] , \gpio_defaults[210] , \gpio_defaults[209] , \gpio_defaults[208] })
+ );
+ gpio_defaults_block_0403 gpio_defaults_block_17 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[233] , \gpio_defaults[232] , \gpio_defaults[231] , \gpio_defaults[230] , \gpio_defaults[229] , \gpio_defaults[228] , \gpio_defaults[227] , \gpio_defaults[226] , \gpio_defaults[225] , \gpio_defaults[224] , \gpio_defaults[223] , \gpio_defaults[222] , \gpio_defaults[221] })
+ );
+ gpio_defaults_block_0403 gpio_defaults_block_18 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[246] , \gpio_defaults[245] , \gpio_defaults[244] , \gpio_defaults[243] , \gpio_defaults[242] , \gpio_defaults[241] , \gpio_defaults[240] , \gpio_defaults[239] , \gpio_defaults[238] , \gpio_defaults[237] , \gpio_defaults[236] , \gpio_defaults[235] , \gpio_defaults[234] })
+ );
+ gpio_defaults_block_0403 gpio_defaults_block_19 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[259] , \gpio_defaults[258] , \gpio_defaults[257] , \gpio_defaults[256] , \gpio_defaults[255] , \gpio_defaults[254] , \gpio_defaults[253] , \gpio_defaults[252] , \gpio_defaults[251] , \gpio_defaults[250] , \gpio_defaults[249] , \gpio_defaults[248] , \gpio_defaults[247] })
+ );
+ gpio_defaults_block_0403 gpio_defaults_block_2 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[38] , \gpio_defaults[37] , \gpio_defaults[36] , \gpio_defaults[35] , \gpio_defaults[34] , \gpio_defaults[33] , \gpio_defaults[32] , \gpio_defaults[31] , \gpio_defaults[30] , \gpio_defaults[29] , \gpio_defaults[28] , \gpio_defaults[27] , \gpio_defaults[26] })
+ );
+ gpio_defaults_block_0403 gpio_defaults_block_20 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[272] , \gpio_defaults[271] , \gpio_defaults[270] , \gpio_defaults[269] , \gpio_defaults[268] , \gpio_defaults[267] , \gpio_defaults[266] , \gpio_defaults[265] , \gpio_defaults[264] , \gpio_defaults[263] , \gpio_defaults[262] , \gpio_defaults[261] , \gpio_defaults[260] })
+ );
+ gpio_defaults_block_0403 gpio_defaults_block_21 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[285] , \gpio_defaults[284] , \gpio_defaults[283] , \gpio_defaults[282] , \gpio_defaults[281] , \gpio_defaults[280] , \gpio_defaults[279] , \gpio_defaults[278] , \gpio_defaults[277] , \gpio_defaults[276] , \gpio_defaults[275] , \gpio_defaults[274] , \gpio_defaults[273] })
+ );
+ gpio_defaults_block_0403 gpio_defaults_block_22 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[298] , \gpio_defaults[297] , \gpio_defaults[296] , \gpio_defaults[295] , \gpio_defaults[294] , \gpio_defaults[293] , \gpio_defaults[292] , \gpio_defaults[291] , \gpio_defaults[290] , \gpio_defaults[289] , \gpio_defaults[288] , \gpio_defaults[287] , \gpio_defaults[286] })
+ );
+ gpio_defaults_block_0403 gpio_defaults_block_23 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[311] , \gpio_defaults[310] , \gpio_defaults[309] , \gpio_defaults[308] , \gpio_defaults[307] , \gpio_defaults[306] , \gpio_defaults[305] , \gpio_defaults[304] , \gpio_defaults[303] , \gpio_defaults[302] , \gpio_defaults[301] , \gpio_defaults[300] , \gpio_defaults[299] })
+ );
+ gpio_defaults_block_0403 gpio_defaults_block_24 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[324] , \gpio_defaults[323] , \gpio_defaults[322] , \gpio_defaults[321] , \gpio_defaults[320] , \gpio_defaults[319] , \gpio_defaults[318] , \gpio_defaults[317] , \gpio_defaults[316] , \gpio_defaults[315] , \gpio_defaults[314] , \gpio_defaults[313] , \gpio_defaults[312] })
+ );
+ gpio_defaults_block_0403 gpio_defaults_block_25 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[337] , \gpio_defaults[336] , \gpio_defaults[335] , \gpio_defaults[334] , \gpio_defaults[333] , \gpio_defaults[332] , \gpio_defaults[331] , \gpio_defaults[330] , \gpio_defaults[329] , \gpio_defaults[328] , \gpio_defaults[327] , \gpio_defaults[326] , \gpio_defaults[325] })
+ );
+ gpio_defaults_block_0403 gpio_defaults_block_26 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[350] , \gpio_defaults[349] , \gpio_defaults[348] , \gpio_defaults[347] , \gpio_defaults[346] , \gpio_defaults[345] , \gpio_defaults[344] , \gpio_defaults[343] , \gpio_defaults[342] , \gpio_defaults[341] , \gpio_defaults[340] , \gpio_defaults[339] , \gpio_defaults[338] })
+ );
+ gpio_defaults_block_0403 gpio_defaults_block_27 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[363] , \gpio_defaults[362] , \gpio_defaults[361] , \gpio_defaults[360] , \gpio_defaults[359] , \gpio_defaults[358] , \gpio_defaults[357] , \gpio_defaults[356] , \gpio_defaults[355] , \gpio_defaults[354] , \gpio_defaults[353] , \gpio_defaults[352] , \gpio_defaults[351] })
+ );
+ gpio_defaults_block_0403 gpio_defaults_block_28 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[376] , \gpio_defaults[375] , \gpio_defaults[374] , \gpio_defaults[373] , \gpio_defaults[372] , \gpio_defaults[371] , \gpio_defaults[370] , \gpio_defaults[369] , \gpio_defaults[368] , \gpio_defaults[367] , \gpio_defaults[366] , \gpio_defaults[365] , \gpio_defaults[364] })
+ );
+ gpio_defaults_block_0403 gpio_defaults_block_29 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[389] , \gpio_defaults[388] , \gpio_defaults[387] , \gpio_defaults[386] , \gpio_defaults[385] , \gpio_defaults[384] , \gpio_defaults[383] , \gpio_defaults[382] , \gpio_defaults[381] , \gpio_defaults[380] , \gpio_defaults[379] , \gpio_defaults[378] , \gpio_defaults[377] })
+ );
+ gpio_defaults_block_0801 gpio_defaults_block_3 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[51] , \gpio_defaults[50] , \gpio_defaults[49] , \gpio_defaults[48] , \gpio_defaults[47] , \gpio_defaults[46] , \gpio_defaults[45] , \gpio_defaults[44] , \gpio_defaults[43] , \gpio_defaults[42] , \gpio_defaults[41] , \gpio_defaults[40] , \gpio_defaults[39] })
+ );
+ gpio_defaults_block_0403 gpio_defaults_block_30 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[402] , \gpio_defaults[401] , \gpio_defaults[400] , \gpio_defaults[399] , \gpio_defaults[398] , \gpio_defaults[397] , \gpio_defaults[396] , \gpio_defaults[395] , \gpio_defaults[394] , \gpio_defaults[393] , \gpio_defaults[392] , \gpio_defaults[391] , \gpio_defaults[390] })
+ );
+ gpio_defaults_block_0403 gpio_defaults_block_31 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[415] , \gpio_defaults[414] , \gpio_defaults[413] , \gpio_defaults[412] , \gpio_defaults[411] , \gpio_defaults[410] , \gpio_defaults[409] , \gpio_defaults[408] , \gpio_defaults[407] , \gpio_defaults[406] , \gpio_defaults[405] , \gpio_defaults[404] , \gpio_defaults[403] })
+ );
+ gpio_defaults_block_0403 gpio_defaults_block_32 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[428] , \gpio_defaults[427] , \gpio_defaults[426] , \gpio_defaults[425] , \gpio_defaults[424] , \gpio_defaults[423] , \gpio_defaults[422] , \gpio_defaults[421] , \gpio_defaults[420] , \gpio_defaults[419] , \gpio_defaults[418] , \gpio_defaults[417] , \gpio_defaults[416] })
+ );
+ gpio_defaults_block_0403 gpio_defaults_block_33 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[441] , \gpio_defaults[440] , \gpio_defaults[439] , \gpio_defaults[438] , \gpio_defaults[437] , \gpio_defaults[436] , \gpio_defaults[435] , \gpio_defaults[434] , \gpio_defaults[433] , \gpio_defaults[432] , \gpio_defaults[431] , \gpio_defaults[430] , \gpio_defaults[429] })
+ );
+ gpio_defaults_block_0403 gpio_defaults_block_34 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[454] , \gpio_defaults[453] , \gpio_defaults[452] , \gpio_defaults[451] , \gpio_defaults[450] , \gpio_defaults[449] , \gpio_defaults[448] , \gpio_defaults[447] , \gpio_defaults[446] , \gpio_defaults[445] , \gpio_defaults[444] , \gpio_defaults[443] , \gpio_defaults[442] })
+ );
+ gpio_defaults_block_0403 gpio_defaults_block_35 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[467] , \gpio_defaults[466] , \gpio_defaults[465] , \gpio_defaults[464] , \gpio_defaults[463] , \gpio_defaults[462] , \gpio_defaults[461] , \gpio_defaults[460] , \gpio_defaults[459] , \gpio_defaults[458] , \gpio_defaults[457] , \gpio_defaults[456] , \gpio_defaults[455] })
+ );
+ gpio_defaults_block_0403 gpio_defaults_block_36 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[480] , \gpio_defaults[479] , \gpio_defaults[478] , \gpio_defaults[477] , \gpio_defaults[476] , \gpio_defaults[475] , \gpio_defaults[474] , \gpio_defaults[473] , \gpio_defaults[472] , \gpio_defaults[471] , \gpio_defaults[470] , \gpio_defaults[469] , \gpio_defaults[468] })
+ );
+ gpio_defaults_block_0403 gpio_defaults_block_37 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[493] , \gpio_defaults[492] , \gpio_defaults[491] , \gpio_defaults[490] , \gpio_defaults[489] , \gpio_defaults[488] , \gpio_defaults[487] , \gpio_defaults[486] , \gpio_defaults[485] , \gpio_defaults[484] , \gpio_defaults[483] , \gpio_defaults[482] , \gpio_defaults[481] })
+ );
+ gpio_defaults_block_0403 gpio_defaults_block_4 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[64] , \gpio_defaults[63] , \gpio_defaults[62] , \gpio_defaults[61] , \gpio_defaults[60] , \gpio_defaults[59] , \gpio_defaults[58] , \gpio_defaults[57] , \gpio_defaults[56] , \gpio_defaults[55] , \gpio_defaults[54] , \gpio_defaults[53] , \gpio_defaults[52] })
+ );
+ gpio_defaults_block_0403 gpio_defaults_block_5 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[77] , \gpio_defaults[76] , \gpio_defaults[75] , \gpio_defaults[74] , \gpio_defaults[73] , \gpio_defaults[72] , \gpio_defaults[71] , \gpio_defaults[70] , \gpio_defaults[69] , \gpio_defaults[68] , \gpio_defaults[67] , \gpio_defaults[66] , \gpio_defaults[65] })
+ );
+ gpio_defaults_block_0403 gpio_defaults_block_6 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[90] , \gpio_defaults[89] , \gpio_defaults[88] , \gpio_defaults[87] , \gpio_defaults[86] , \gpio_defaults[85] , \gpio_defaults[84] , \gpio_defaults[83] , \gpio_defaults[82] , \gpio_defaults[81] , \gpio_defaults[80] , \gpio_defaults[79] , \gpio_defaults[78] })
+ );
+ gpio_defaults_block_0403 gpio_defaults_block_7 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[103] , \gpio_defaults[102] , \gpio_defaults[101] , \gpio_defaults[100] , \gpio_defaults[99] , \gpio_defaults[98] , \gpio_defaults[97] , \gpio_defaults[96] , \gpio_defaults[95] , \gpio_defaults[94] , \gpio_defaults[93] , \gpio_defaults[92] , \gpio_defaults[91] })
+ );
+ gpio_defaults_block_0403 gpio_defaults_block_8 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[116] , \gpio_defaults[115] , \gpio_defaults[114] , \gpio_defaults[113] , \gpio_defaults[112] , \gpio_defaults[111] , \gpio_defaults[110] , \gpio_defaults[109] , \gpio_defaults[108] , \gpio_defaults[107] , \gpio_defaults[106] , \gpio_defaults[105] , \gpio_defaults[104] })
+ );
+ gpio_defaults_block_0403 gpio_defaults_block_9 (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .gpio_defaults({ \gpio_defaults[129] , \gpio_defaults[128] , \gpio_defaults[127] , \gpio_defaults[126] , \gpio_defaults[125] , \gpio_defaults[124] , \gpio_defaults[123] , \gpio_defaults[122] , \gpio_defaults[121] , \gpio_defaults[120] , \gpio_defaults[119] , \gpio_defaults[118] , \gpio_defaults[117] })
+ );
+ housekeeping housekeeping (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .debug_in(debug_in),
+ .debug_mode(debug_mode),
+ .debug_oeb(debug_oeb),
+ .debug_out(debug_out),
+ .irq({ \irq_spi[2] , \irq_spi[1] , \irq_spi[0] }),
+ .mask_rev_in({ \mask_rev[31] , \mask_rev[30] , \mask_rev[29] , \mask_rev[28] , \mask_rev[27] , \mask_rev[26] , \mask_rev[25] , \mask_rev[24] , \mask_rev[23] , \mask_rev[22] , \mask_rev[21] , \mask_rev[20] , \mask_rev[19] , \mask_rev[18] , \mask_rev[17] , \mask_rev[16] , \mask_rev[15] , \mask_rev[14] , \mask_rev[13] , \mask_rev[12] , \mask_rev[11] , \mask_rev[10] , \mask_rev[9] , \mask_rev[8] , \mask_rev[7] , \mask_rev[6] , \mask_rev[5] , \mask_rev[4] , \mask_rev[3] , \mask_rev[2] , \mask_rev[1] , \mask_rev[0] }),
+ .mgmt_gpio_in({ \mgmt_io_in_hk[37] , \mgmt_io_in_hk[36] , \mgmt_io_in_hk[35] , \mgmt_io_in_hk[34] , \mgmt_io_in_hk[33] , \mgmt_io_in_hk[32] , \mgmt_io_in_hk[31] , \mgmt_io_in_hk[30] , \mgmt_io_in_hk[29] , \mgmt_io_in_hk[28] , \mgmt_io_in_hk[27] , \mgmt_io_in_hk[26] , \mgmt_io_in_hk[25] , \mgmt_io_in_hk[24] , \mgmt_io_in_hk[23] , \mgmt_io_in_hk[22] , \mgmt_io_in_hk[21] , \mgmt_io_in_hk[20] , \mgmt_io_in_hk[19] , \mgmt_io_in_hk[18] , \mgmt_io_in_hk[17] , \mgmt_io_in_hk[16] , \mgmt_io_in_hk[15] , \mgmt_io_in_hk[14] , \mgmt_io_in_hk[13] , \mgmt_io_in_hk[12] , \mgmt_io_in_hk[11] , \mgmt_io_in_hk[10] , \mgmt_io_in_hk[9] , \mgmt_io_in_hk[8] , \mgmt_io_in_hk[7] , \mgmt_io_in[6] , \mgmt_io_in[5] , \mgmt_io_in[4] , \mgmt_io_in[3] , \mgmt_io_in[2] , \mgmt_io_in[1] , \mgmt_io_in[0] }),
+ .mgmt_gpio_oeb({ \mgmt_io_oeb_hk[37] , \mgmt_io_oeb_hk[36] , \mgmt_io_oeb_hk[35] , \mgmt_io_oeb[34] , \mgmt_io_oeb[33] , \mgmt_io_oeb[32] , \mgmt_io_oeb[31] , \mgmt_io_oeb[30] , \mgmt_io_oeb[29] , \mgmt_io_oeb[28] , \mgmt_io_oeb[27] , \mgmt_io_oeb[26] , \mgmt_io_oeb[25] , \mgmt_io_oeb[24] , \mgmt_io_oeb[23] , \mgmt_io_oeb[22] , \mgmt_io_oeb[21] , \mgmt_io_oeb[20] , \mgmt_io_oeb[19] , \mgmt_io_oeb[18] , \mgmt_io_oeb[17] , \mgmt_io_oeb[16] , \mgmt_io_oeb[15] , \mgmt_io_oeb[14] , \mgmt_io_oeb[13] , \mgmt_io_oeb[12] , \mgmt_io_oeb[11] , \mgmt_io_oeb[10] , \mgmt_io_oeb[9] , \mgmt_io_oeb[8] , \mgmt_io_oeb[7] , \mgmt_io_oeb[6] , \mgmt_io_oeb[5] , \mgmt_io_oeb[4] , \mgmt_io_oeb[3] , \mgmt_io_oeb[2] , \mgmt_io_oeb[1] , \mgmt_io_oeb[0] }),
+ .mgmt_gpio_out({ \mgmt_io_out_hk[37] , \mgmt_io_out_hk[36] , \mgmt_io_out_hk[35] , \mgmt_io_out_hk[34] , \mgmt_io_out_hk[33] , \mgmt_io_out_hk[32] , \mgmt_io_out_hk[31] , \mgmt_io_out_hk[30] , \mgmt_io_out_hk[29] , \mgmt_io_out_hk[28] , \mgmt_io_out_hk[27] , \mgmt_io_out_hk[26] , \mgmt_io_out_hk[25] , \mgmt_io_out_hk[24] , \mgmt_io_out_hk[23] , \mgmt_io_out_hk[22] , \mgmt_io_out_hk[21] , \mgmt_io_out_hk[20] , \mgmt_io_out_hk[19] , \mgmt_io_out_hk[18] , \mgmt_io_out_hk[17] , \mgmt_io_out_hk[16] , \mgmt_io_out_hk[15] , \mgmt_io_out_hk[14] , \mgmt_io_out_hk[13] , \mgmt_io_out_hk[12] , \mgmt_io_out_hk[11] , \mgmt_io_out_hk[10] , \mgmt_io_out_hk[9] , \mgmt_io_out_hk[8] , \mgmt_io_out_hk[7] , \mgmt_io_out[6] , \mgmt_io_out[5] , \mgmt_io_out[4] , \mgmt_io_out[3] , \mgmt_io_out[2] , \mgmt_io_out[1] , \mgmt_io_out[0] }),
+ .pad_flash_clk(flash_clk_frame),
+ .pad_flash_clk_oeb(flash_clk_oeb),
+ .pad_flash_csb(flash_csb_frame),
+ .pad_flash_csb_oeb(flash_csb_oeb),
+ .pad_flash_io0_di(flash_io0_di_buf),
+ .pad_flash_io0_do(flash_io0_do),
+ .pad_flash_io0_ieb(flash_io0_ieb),
+ .pad_flash_io0_oeb(flash_io0_oeb),
+ .pad_flash_io1_di(flash_io1_di_buf),
+ .pad_flash_io1_do(flash_io1_do),
+ .pad_flash_io1_ieb(flash_io1_ieb),
+ .pad_flash_io1_oeb(flash_io1_oeb),
+ .pll90_sel({ \spi_pll90_sel[2] , \spi_pll90_sel[1] , \spi_pll90_sel[0] }),
+ .pll_bypass(ext_clk_sel),
+ .pll_dco_ena(spi_pll_dco_ena),
+ .pll_div({ \spi_pll_div[4] , \spi_pll_div[3] , \spi_pll_div[2] , \spi_pll_div[1] , \spi_pll_div[0] }),
+ .pll_ena(spi_pll_ena),
+ .pll_sel({ \spi_pll_sel[2] , \spi_pll_sel[1] , \spi_pll_sel[0] }),
+ .pll_trim({ \spi_pll_trim[25] , \spi_pll_trim[24] , \spi_pll_trim[23] , \spi_pll_trim[22] , \spi_pll_trim[21] , \spi_pll_trim[20] , \spi_pll_trim[19] , \spi_pll_trim[18] , \spi_pll_trim[17] , \spi_pll_trim[16] , \spi_pll_trim[15] , \spi_pll_trim[14] , \spi_pll_trim[13] , \spi_pll_trim[12] , \spi_pll_trim[11] , \spi_pll_trim[10] , \spi_pll_trim[9] , \spi_pll_trim[8] , \spi_pll_trim[7] , \spi_pll_trim[6] , \spi_pll_trim[5] , \spi_pll_trim[4] , \spi_pll_trim[3] , \spi_pll_trim[2] , \spi_pll_trim[1] , \spi_pll_trim[0] }),
+ .porb(porb_l),
+ .pwr_ctrl_out({ \pwr_ctrl_nc[3] , \pwr_ctrl_nc[2] , \pwr_ctrl_nc[1] , \pwr_ctrl_nc[0] }),
+ .qspi_enabled(qspi_enabled),
+ .reset(ext_reset),
+ .ser_rx(ser_rx),
+ .ser_tx(ser_tx),
+ .serial_clock(\gpio_clock_1_shifted[0] ),
+ .serial_data_1(\gpio_serial_link_1_shifted[0] ),
+ .serial_data_2(mprj_io_loader_data_2),
+ .serial_load(\gpio_load_1_shifted[0] ),
+ .serial_resetn(\gpio_resetn_1_shifted[0] ),
+ .spi_csb(spi_csb),
+ .spi_enabled(spi_enabled),
+ .spi_sck(spi_sck),
+ .spi_sdi(spi_sdi),
+ .spi_sdo(spi_sdo),
+ .spi_sdoenb(spi_sdoenb),
+ .spimemio_flash_clk(flash_clk_core),
+ .spimemio_flash_csb(flash_csb_core),
+ .spimemio_flash_io0_di(flash_io0_di_core),
+ .spimemio_flash_io0_do(flash_io0_do_core),
+ .spimemio_flash_io0_oeb(flash_io0_oeb_core),
+ .spimemio_flash_io1_di(flash_io1_di_core),
+ .spimemio_flash_io1_do(flash_io1_do_core),
+ .spimemio_flash_io1_oeb(flash_io1_oeb_core),
+ .spimemio_flash_io2_di(flash_io2_di_core),
+ .spimemio_flash_io2_do(flash_io2_do_core),
+ .spimemio_flash_io2_oeb(flash_io2_oeb_core),
+ .spimemio_flash_io3_di(flash_io3_di_core),
+ .spimemio_flash_io3_do(flash_io3_do_core),
+ .spimemio_flash_io3_oeb(flash_io3_oeb_core),
+ .trap(trap),
+ .uart_enabled(uart_enabled),
+ .user_clock(caravel_clk2),
+ .usr1_vcc_pwrgood(mprj_vcc_pwrgood),
+ .usr1_vdd_pwrgood(mprj_vdd_pwrgood),
+ .usr2_vcc_pwrgood(mprj2_vcc_pwrgood),
+ .usr2_vdd_pwrgood(mprj2_vdd_pwrgood),
+ .wb_ack_o(hk_ack_i),
+ .wb_adr_i({ \mprj_adr_o_core[31] , \mprj_adr_o_core[30] , \mprj_adr_o_core[29] , \mprj_adr_o_core[28] , \mprj_adr_o_core[27] , \mprj_adr_o_core[26] , \mprj_adr_o_core[25] , \mprj_adr_o_core[24] , \mprj_adr_o_core[23] , \mprj_adr_o_core[22] , \mprj_adr_o_core[21] , \mprj_adr_o_core[20] , \mprj_adr_o_core[19] , \mprj_adr_o_core[18] , \mprj_adr_o_core[17] , \mprj_adr_o_core[16] , \mprj_adr_o_core[15] , \mprj_adr_o_core[14] , \mprj_adr_o_core[13] , \mprj_adr_o_core[12] , \mprj_adr_o_core[11] , \mprj_adr_o_core[10] , \mprj_adr_o_core[9] , \mprj_adr_o_core[8] , \mprj_adr_o_core[7] , \mprj_adr_o_core[6] , \mprj_adr_o_core[5] , \mprj_adr_o_core[4] , \mprj_adr_o_core[3] , \mprj_adr_o_core[2] , \mprj_adr_o_core[1] , \mprj_adr_o_core[0] }),
+ .wb_clk_i(caravel_clk),
+ .wb_cyc_i(hk_cyc_o),
+ .wb_dat_i({ \mprj_dat_o_core[31] , \mprj_dat_o_core[30] , \mprj_dat_o_core[29] , \mprj_dat_o_core[28] , \mprj_dat_o_core[27] , \mprj_dat_o_core[26] , \mprj_dat_o_core[25] , \mprj_dat_o_core[24] , \mprj_dat_o_core[23] , \mprj_dat_o_core[22] , \mprj_dat_o_core[21] , \mprj_dat_o_core[20] , \mprj_dat_o_core[19] , \mprj_dat_o_core[18] , \mprj_dat_o_core[17] , \mprj_dat_o_core[16] , \mprj_dat_o_core[15] , \mprj_dat_o_core[14] , \mprj_dat_o_core[13] , \mprj_dat_o_core[12] , \mprj_dat_o_core[11] , \mprj_dat_o_core[10] , \mprj_dat_o_core[9] , \mprj_dat_o_core[8] , \mprj_dat_o_core[7] , \mprj_dat_o_core[6] , \mprj_dat_o_core[5] , \mprj_dat_o_core[4] , \mprj_dat_o_core[3] , \mprj_dat_o_core[2] , \mprj_dat_o_core[1] , \mprj_dat_o_core[0] }),
+ .wb_dat_o({ \hk_dat_i[31] , \hk_dat_i[30] , \hk_dat_i[29] , \hk_dat_i[28] , \hk_dat_i[27] , \hk_dat_i[26] , \hk_dat_i[25] , \hk_dat_i[24] , \hk_dat_i[23] , \hk_dat_i[22] , \hk_dat_i[21] , \hk_dat_i[20] , \hk_dat_i[19] , \hk_dat_i[18] , \hk_dat_i[17] , \hk_dat_i[16] , \hk_dat_i[15] , \hk_dat_i[14] , \hk_dat_i[13] , \hk_dat_i[12] , \hk_dat_i[11] , \hk_dat_i[10] , \hk_dat_i[9] , \hk_dat_i[8] , \hk_dat_i[7] , \hk_dat_i[6] , \hk_dat_i[5] , \hk_dat_i[4] , \hk_dat_i[3] , \hk_dat_i[2] , \hk_dat_i[1] , \hk_dat_i[0] }),
+ .wb_rstn_i(caravel_rstn),
+ .wb_sel_i({ \mprj_sel_o_core[3] , \mprj_sel_o_core[2] , \mprj_sel_o_core[1] , \mprj_sel_o_core[0] }),
+ .wb_stb_i(hk_stb_o),
+ .wb_we_i(mprj_we_o_core)
+ );
+ mgmt_protect mgmt_buffers (
+ .caravel_clk(clk_passthru),
+ .caravel_clk2(caravel_clk2),
+ .caravel_rstn(resetn_passthru),
+ .la_data_in_core({ \la_data_in_user[127] , \la_data_in_user[126] , \la_data_in_user[125] , \la_data_in_user[124] , \la_data_in_user[123] , \la_data_in_user[122] , \la_data_in_user[121] , \la_data_in_user[120] , \la_data_in_user[119] , \la_data_in_user[118] , \la_data_in_user[117] , \la_data_in_user[116] , \la_data_in_user[115] , \la_data_in_user[114] , \la_data_in_user[113] , \la_data_in_user[112] , \la_data_in_user[111] , \la_data_in_user[110] , \la_data_in_user[109] , \la_data_in_user[108] , \la_data_in_user[107] , \la_data_in_user[106] , \la_data_in_user[105] , \la_data_in_user[104] , \la_data_in_user[103] , \la_data_in_user[102] , \la_data_in_user[101] , \la_data_in_user[100] , \la_data_in_user[99] , \la_data_in_user[98] , \la_data_in_user[97] , \la_data_in_user[96] , \la_data_in_user[95] , \la_data_in_user[94] , \la_data_in_user[93] , \la_data_in_user[92] , \la_data_in_user[91] , \la_data_in_user[90] , \la_data_in_user[89] , \la_data_in_user[88] , \la_data_in_user[87] , \la_data_in_user[86] , \la_data_in_user[85] , \la_data_in_user[84] , \la_data_in_user[83] , \la_data_in_user[82] , \la_data_in_user[81] , \la_data_in_user[80] , \la_data_in_user[79] , \la_data_in_user[78] , \la_data_in_user[77] , \la_data_in_user[76] , \la_data_in_user[75] , \la_data_in_user[74] , \la_data_in_user[73] , \la_data_in_user[72] , \la_data_in_user[71] , \la_data_in_user[70] , \la_data_in_user[69] , \la_data_in_user[68] , \la_data_in_user[67] , \la_data_in_user[66] , \la_data_in_user[65] , \la_data_in_user[64] , \la_data_in_user[63] , \la_data_in_user[62] , \la_data_in_user[61] , \la_data_in_user[60] , \la_data_in_user[59] , \la_data_in_user[58] , \la_data_in_user[57] , \la_data_in_user[56] , \la_data_in_user[55] , \la_data_in_user[54] , \la_data_in_user[53] , \la_data_in_user[52] , \la_data_in_user[51] , \la_data_in_user[50] , \la_data_in_user[49] , \la_data_in_user[48] , \la_data_in_user[47] , \la_data_in_user[46] , \la_data_in_user[45] , \la_data_in_user[44] , \la_data_in_user[43] , \la_data_in_user[42] , \la_data_in_user[41] , \la_data_in_user[40] , \la_data_in_user[39] , \la_data_in_user[38] , \la_data_in_user[37] , \la_data_in_user[36] , \la_data_in_user[35] , \la_data_in_user[34] , \la_data_in_user[33] , \la_data_in_user[32] , \la_data_in_user[31] , \la_data_in_user[30] , \la_data_in_user[29] , \la_data_in_user[28] , \la_data_in_user[27] , \la_data_in_user[26] , \la_data_in_user[25] , \la_data_in_user[24] , \la_data_in_user[23] , \la_data_in_user[22] , \la_data_in_user[21] , \la_data_in_user[20] , \la_data_in_user[19] , \la_data_in_user[18] , \la_data_in_user[17] , \la_data_in_user[16] , \la_data_in_user[15] , \la_data_in_user[14] , \la_data_in_user[13] , \la_data_in_user[12] , \la_data_in_user[11] , \la_data_in_user[10] , \la_data_in_user[9] , \la_data_in_user[8] , \la_data_in_user[7] , \la_data_in_user[6] , \la_data_in_user[5] , \la_data_in_user[4] , \la_data_in_user[3] , \la_data_in_user[2] , \la_data_in_user[1] , \la_data_in_user[0] }),
+ .la_data_in_mprj({ \la_data_in_mprj[127] , \la_data_in_mprj[126] , \la_data_in_mprj[125] , \la_data_in_mprj[124] , \la_data_in_mprj[123] , \la_data_in_mprj[122] , \la_data_in_mprj[121] , \la_data_in_mprj[120] , \la_data_in_mprj[119] , \la_data_in_mprj[118] , \la_data_in_mprj[117] , \la_data_in_mprj[116] , \la_data_in_mprj[115] , \la_data_in_mprj[114] , \la_data_in_mprj[113] , \la_data_in_mprj[112] , \la_data_in_mprj[111] , \la_data_in_mprj[110] , \la_data_in_mprj[109] , \la_data_in_mprj[108] , \la_data_in_mprj[107] , \la_data_in_mprj[106] , \la_data_in_mprj[105] , \la_data_in_mprj[104] , \la_data_in_mprj[103] , \la_data_in_mprj[102] , \la_data_in_mprj[101] , \la_data_in_mprj[100] , \la_data_in_mprj[99] , \la_data_in_mprj[98] , \la_data_in_mprj[97] , \la_data_in_mprj[96] , \la_data_in_mprj[95] , \la_data_in_mprj[94] , \la_data_in_mprj[93] , \la_data_in_mprj[92] , \la_data_in_mprj[91] , \la_data_in_mprj[90] , \la_data_in_mprj[89] , \la_data_in_mprj[88] , \la_data_in_mprj[87] , \la_data_in_mprj[86] , \la_data_in_mprj[85] , \la_data_in_mprj[84] , \la_data_in_mprj[83] , \la_data_in_mprj[82] , \la_data_in_mprj[81] , \la_data_in_mprj[80] , \la_data_in_mprj[79] , \la_data_in_mprj[78] , \la_data_in_mprj[77] , \la_data_in_mprj[76] , \la_data_in_mprj[75] , \la_data_in_mprj[74] , \la_data_in_mprj[73] , \la_data_in_mprj[72] , \la_data_in_mprj[71] , \la_data_in_mprj[70] , \la_data_in_mprj[69] , \la_data_in_mprj[68] , \la_data_in_mprj[67] , \la_data_in_mprj[66] , \la_data_in_mprj[65] , \la_data_in_mprj[64] , \la_data_in_mprj[63] , \la_data_in_mprj[62] , \la_data_in_mprj[61] , \la_data_in_mprj[60] , \la_data_in_mprj[59] , \la_data_in_mprj[58] , \la_data_in_mprj[57] , \la_data_in_mprj[56] , \la_data_in_mprj[55] , \la_data_in_mprj[54] , \la_data_in_mprj[53] , \la_data_in_mprj[52] , \la_data_in_mprj[51] , \la_data_in_mprj[50] , \la_data_in_mprj[49] , \la_data_in_mprj[48] , \la_data_in_mprj[47] , \la_data_in_mprj[46] , \la_data_in_mprj[45] , \la_data_in_mprj[44] , \la_data_in_mprj[43] , \la_data_in_mprj[42] , \la_data_in_mprj[41] , \la_data_in_mprj[40] , \la_data_in_mprj[39] , \la_data_in_mprj[38] , \la_data_in_mprj[37] , \la_data_in_mprj[36] , \la_data_in_mprj[35] , \la_data_in_mprj[34] , \la_data_in_mprj[33] , \la_data_in_mprj[32] , \la_data_in_mprj[31] , \la_data_in_mprj[30] , \la_data_in_mprj[29] , \la_data_in_mprj[28] , \la_data_in_mprj[27] , \la_data_in_mprj[26] , \la_data_in_mprj[25] , \la_data_in_mprj[24] , \la_data_in_mprj[23] , \la_data_in_mprj[22] , \la_data_in_mprj[21] , \la_data_in_mprj[20] , \la_data_in_mprj[19] , \la_data_in_mprj[18] , \la_data_in_mprj[17] , \la_data_in_mprj[16] , \la_data_in_mprj[15] , \la_data_in_mprj[14] , \la_data_in_mprj[13] , \la_data_in_mprj[12] , \la_data_in_mprj[11] , \la_data_in_mprj[10] , \la_data_in_mprj[9] , \la_data_in_mprj[8] , \la_data_in_mprj[7] , \la_data_in_mprj[6] , \la_data_in_mprj[5] , \la_data_in_mprj[4] , \la_data_in_mprj[3] , \la_data_in_mprj[2] , \la_data_in_mprj[1] , \la_data_in_mprj[0] }),
+ .la_data_out_core({ \la_data_out_user[127] , \la_data_out_user[126] , \la_data_out_user[125] , \la_data_out_user[124] , \la_data_out_user[123] , \la_data_out_user[122] , \la_data_out_user[121] , \la_data_out_user[120] , \la_data_out_user[119] , \la_data_out_user[118] , \la_data_out_user[117] , \la_data_out_user[116] , \la_data_out_user[115] , \la_data_out_user[114] , \la_data_out_user[113] , \la_data_out_user[112] , \la_data_out_user[111] , \la_data_out_user[110] , \la_data_out_user[109] , \la_data_out_user[108] , \la_data_out_user[107] , \la_data_out_user[106] , \la_data_out_user[105] , \la_data_out_user[104] , \la_data_out_user[103] , \la_data_out_user[102] , \la_data_out_user[101] , \la_data_out_user[100] , \la_data_out_user[99] , \la_data_out_user[98] , \la_data_out_user[97] , \la_data_out_user[96] , \la_data_out_user[95] , \la_data_out_user[94] , \la_data_out_user[93] , \la_data_out_user[92] , \la_data_out_user[91] , \la_data_out_user[90] , \la_data_out_user[89] , \la_data_out_user[88] , \la_data_out_user[87] , \la_data_out_user[86] , \la_data_out_user[85] , \la_data_out_user[84] , \la_data_out_user[83] , \la_data_out_user[82] , \la_data_out_user[81] , \la_data_out_user[80] , \la_data_out_user[79] , \la_data_out_user[78] , \la_data_out_user[77] , \la_data_out_user[76] , \la_data_out_user[75] , \la_data_out_user[74] , \la_data_out_user[73] , \la_data_out_user[72] , \la_data_out_user[71] , \la_data_out_user[70] , \la_data_out_user[69] , \la_data_out_user[68] , \la_data_out_user[67] , \la_data_out_user[66] , \la_data_out_user[65] , \la_data_out_user[64] , \la_data_out_user[63] , \la_data_out_user[62] , \la_data_out_user[61] , \la_data_out_user[60] , \la_data_out_user[59] , \la_data_out_user[58] , \la_data_out_user[57] , \la_data_out_user[56] , \la_data_out_user[55] , \la_data_out_user[54] , \la_data_out_user[53] , \la_data_out_user[52] , \la_data_out_user[51] , \la_data_out_user[50] , \la_data_out_user[49] , \la_data_out_user[48] , \la_data_out_user[47] , \la_data_out_user[46] , \la_data_out_user[45] , \la_data_out_user[44] , \la_data_out_user[43] , \la_data_out_user[42] , \la_data_out_user[41] , \la_data_out_user[40] , \la_data_out_user[39] , \la_data_out_user[38] , \la_data_out_user[37] , \la_data_out_user[36] , \la_data_out_user[35] , \la_data_out_user[34] , \la_data_out_user[33] , \la_data_out_user[32] , \la_data_out_user[31] , \la_data_out_user[30] , \la_data_out_user[29] , \la_data_out_user[28] , \la_data_out_user[27] , \la_data_out_user[26] , \la_data_out_user[25] , \la_data_out_user[24] , \la_data_out_user[23] , \la_data_out_user[22] , \la_data_out_user[21] , \la_data_out_user[20] , \la_data_out_user[19] , \la_data_out_user[18] , \la_data_out_user[17] , \la_data_out_user[16] , \la_data_out_user[15] , \la_data_out_user[14] , \la_data_out_user[13] , \la_data_out_user[12] , \la_data_out_user[11] , \la_data_out_user[10] , \la_data_out_user[9] , \la_data_out_user[8] , \la_data_out_user[7] , \la_data_out_user[6] , \la_data_out_user[5] , \la_data_out_user[4] , \la_data_out_user[3] , \la_data_out_user[2] , \la_data_out_user[1] , \la_data_out_user[0] }),
+ .la_data_out_mprj({ \la_data_out_mprj[127] , \la_data_out_mprj[126] , \la_data_out_mprj[125] , \la_data_out_mprj[124] , \la_data_out_mprj[123] , \la_data_out_mprj[122] , \la_data_out_mprj[121] , \la_data_out_mprj[120] , \la_data_out_mprj[119] , \la_data_out_mprj[118] , \la_data_out_mprj[117] , \la_data_out_mprj[116] , \la_data_out_mprj[115] , \la_data_out_mprj[114] , \la_data_out_mprj[113] , \la_data_out_mprj[112] , \la_data_out_mprj[111] , \la_data_out_mprj[110] , \la_data_out_mprj[109] , \la_data_out_mprj[108] , \la_data_out_mprj[107] , \la_data_out_mprj[106] , \la_data_out_mprj[105] , \la_data_out_mprj[104] , \la_data_out_mprj[103] , \la_data_out_mprj[102] , \la_data_out_mprj[101] , \la_data_out_mprj[100] , \la_data_out_mprj[99] , \la_data_out_mprj[98] , \la_data_out_mprj[97] , \la_data_out_mprj[96] , \la_data_out_mprj[95] , \la_data_out_mprj[94] , \la_data_out_mprj[93] , \la_data_out_mprj[92] , \la_data_out_mprj[91] , \la_data_out_mprj[90] , \la_data_out_mprj[89] , \la_data_out_mprj[88] , \la_data_out_mprj[87] , \la_data_out_mprj[86] , \la_data_out_mprj[85] , \la_data_out_mprj[84] , \la_data_out_mprj[83] , \la_data_out_mprj[82] , \la_data_out_mprj[81] , \la_data_out_mprj[80] , \la_data_out_mprj[79] , \la_data_out_mprj[78] , \la_data_out_mprj[77] , \la_data_out_mprj[76] , \la_data_out_mprj[75] , \la_data_out_mprj[74] , \la_data_out_mprj[73] , \la_data_out_mprj[72] , \la_data_out_mprj[71] , \la_data_out_mprj[70] , \la_data_out_mprj[69] , \la_data_out_mprj[68] , \la_data_out_mprj[67] , \la_data_out_mprj[66] , \la_data_out_mprj[65] , \la_data_out_mprj[64] , \la_data_out_mprj[63] , \la_data_out_mprj[62] , \la_data_out_mprj[61] , \la_data_out_mprj[60] , \la_data_out_mprj[59] , \la_data_out_mprj[58] , \la_data_out_mprj[57] , \la_data_out_mprj[56] , \la_data_out_mprj[55] , \la_data_out_mprj[54] , \la_data_out_mprj[53] , \la_data_out_mprj[52] , \la_data_out_mprj[51] , \la_data_out_mprj[50] , \la_data_out_mprj[49] , \la_data_out_mprj[48] , \la_data_out_mprj[47] , \la_data_out_mprj[46] , \la_data_out_mprj[45] , \la_data_out_mprj[44] , \la_data_out_mprj[43] , \la_data_out_mprj[42] , \la_data_out_mprj[41] , \la_data_out_mprj[40] , \la_data_out_mprj[39] , \la_data_out_mprj[38] , \la_data_out_mprj[37] , \la_data_out_mprj[36] , \la_data_out_mprj[35] , \la_data_out_mprj[34] , \la_data_out_mprj[33] , \la_data_out_mprj[32] , \la_data_out_mprj[31] , \la_data_out_mprj[30] , \la_data_out_mprj[29] , \la_data_out_mprj[28] , \la_data_out_mprj[27] , \la_data_out_mprj[26] , \la_data_out_mprj[25] , \la_data_out_mprj[24] , \la_data_out_mprj[23] , \la_data_out_mprj[22] , \la_data_out_mprj[21] , \la_data_out_mprj[20] , \la_data_out_mprj[19] , \la_data_out_mprj[18] , \la_data_out_mprj[17] , \la_data_out_mprj[16] , \la_data_out_mprj[15] , \la_data_out_mprj[14] , \la_data_out_mprj[13] , \la_data_out_mprj[12] , \la_data_out_mprj[11] , \la_data_out_mprj[10] , \la_data_out_mprj[9] , \la_data_out_mprj[8] , \la_data_out_mprj[7] , \la_data_out_mprj[6] , \la_data_out_mprj[5] , \la_data_out_mprj[4] , \la_data_out_mprj[3] , \la_data_out_mprj[2] , \la_data_out_mprj[1] , \la_data_out_mprj[0] }),
+ .la_iena_mprj({ \la_iena_mprj[127] , \la_iena_mprj[126] , \la_iena_mprj[125] , \la_iena_mprj[124] , \la_iena_mprj[123] , \la_iena_mprj[122] , \la_iena_mprj[121] , \la_iena_mprj[120] , \la_iena_mprj[119] , \la_iena_mprj[118] , \la_iena_mprj[117] , \la_iena_mprj[116] , \la_iena_mprj[115] , \la_iena_mprj[114] , \la_iena_mprj[113] , \la_iena_mprj[112] , \la_iena_mprj[111] , \la_iena_mprj[110] , \la_iena_mprj[109] , \la_iena_mprj[108] , \la_iena_mprj[107] , \la_iena_mprj[106] , \la_iena_mprj[105] , \la_iena_mprj[104] , \la_iena_mprj[103] , \la_iena_mprj[102] , \la_iena_mprj[101] , \la_iena_mprj[100] , \la_iena_mprj[99] , \la_iena_mprj[98] , \la_iena_mprj[97] , \la_iena_mprj[96] , \la_iena_mprj[95] , \la_iena_mprj[94] , \la_iena_mprj[93] , \la_iena_mprj[92] , \la_iena_mprj[91] , \la_iena_mprj[90] , \la_iena_mprj[89] , \la_iena_mprj[88] , \la_iena_mprj[87] , \la_iena_mprj[86] , \la_iena_mprj[85] , \la_iena_mprj[84] , \la_iena_mprj[83] , \la_iena_mprj[82] , \la_iena_mprj[81] , \la_iena_mprj[80] , \la_iena_mprj[79] , \la_iena_mprj[78] , \la_iena_mprj[77] , \la_iena_mprj[76] , \la_iena_mprj[75] , \la_iena_mprj[74] , \la_iena_mprj[73] , \la_iena_mprj[72] , \la_iena_mprj[71] , \la_iena_mprj[70] , \la_iena_mprj[69] , \la_iena_mprj[68] , \la_iena_mprj[67] , \la_iena_mprj[66] , \la_iena_mprj[65] , \la_iena_mprj[64] , \la_iena_mprj[63] , \la_iena_mprj[62] , \la_iena_mprj[61] , \la_iena_mprj[60] , \la_iena_mprj[59] , \la_iena_mprj[58] , \la_iena_mprj[57] , \la_iena_mprj[56] , \la_iena_mprj[55] , \la_iena_mprj[54] , \la_iena_mprj[53] , \la_iena_mprj[52] , \la_iena_mprj[51] , \la_iena_mprj[50] , \la_iena_mprj[49] , \la_iena_mprj[48] , \la_iena_mprj[47] , \la_iena_mprj[46] , \la_iena_mprj[45] , \la_iena_mprj[44] , \la_iena_mprj[43] , \la_iena_mprj[42] , \la_iena_mprj[41] , \la_iena_mprj[40] , \la_iena_mprj[39] , \la_iena_mprj[38] , \la_iena_mprj[37] , \la_iena_mprj[36] , \la_iena_mprj[35] , \la_iena_mprj[34] , \la_iena_mprj[33] , \la_iena_mprj[32] , \la_iena_mprj[31] , \la_iena_mprj[30] , \la_iena_mprj[29] , \la_iena_mprj[28] , \la_iena_mprj[27] , \la_iena_mprj[26] , \la_iena_mprj[25] , \la_iena_mprj[24] , \la_iena_mprj[23] , \la_iena_mprj[22] , \la_iena_mprj[21] , \la_iena_mprj[20] , \la_iena_mprj[19] , \la_iena_mprj[18] , \la_iena_mprj[17] , \la_iena_mprj[16] , \la_iena_mprj[15] , \la_iena_mprj[14] , \la_iena_mprj[13] , \la_iena_mprj[12] , \la_iena_mprj[11] , \la_iena_mprj[10] , \la_iena_mprj[9] , \la_iena_mprj[8] , \la_iena_mprj[7] , \la_iena_mprj[6] , \la_iena_mprj[5] , \la_iena_mprj[4] , \la_iena_mprj[3] , \la_iena_mprj[2] , \la_iena_mprj[1] , \la_iena_mprj[0] }),
+ .la_oenb_core({ \la_oenb_user[127] , \la_oenb_user[126] , \la_oenb_user[125] , \la_oenb_user[124] , \la_oenb_user[123] , \la_oenb_user[122] , \la_oenb_user[121] , \la_oenb_user[120] , \la_oenb_user[119] , \la_oenb_user[118] , \la_oenb_user[117] , \la_oenb_user[116] , \la_oenb_user[115] , \la_oenb_user[114] , \la_oenb_user[113] , \la_oenb_user[112] , \la_oenb_user[111] , \la_oenb_user[110] , \la_oenb_user[109] , \la_oenb_user[108] , \la_oenb_user[107] , \la_oenb_user[106] , \la_oenb_user[105] , \la_oenb_user[104] , \la_oenb_user[103] , \la_oenb_user[102] , \la_oenb_user[101] , \la_oenb_user[100] , \la_oenb_user[99] , \la_oenb_user[98] , \la_oenb_user[97] , \la_oenb_user[96] , \la_oenb_user[95] , \la_oenb_user[94] , \la_oenb_user[93] , \la_oenb_user[92] , \la_oenb_user[91] , \la_oenb_user[90] , \la_oenb_user[89] , \la_oenb_user[88] , \la_oenb_user[87] , \la_oenb_user[86] , \la_oenb_user[85] , \la_oenb_user[84] , \la_oenb_user[83] , \la_oenb_user[82] , \la_oenb_user[81] , \la_oenb_user[80] , \la_oenb_user[79] , \la_oenb_user[78] , \la_oenb_user[77] , \la_oenb_user[76] , \la_oenb_user[75] , \la_oenb_user[74] , \la_oenb_user[73] , \la_oenb_user[72] , \la_oenb_user[71] , \la_oenb_user[70] , \la_oenb_user[69] , \la_oenb_user[68] , \la_oenb_user[67] , \la_oenb_user[66] , \la_oenb_user[65] , \la_oenb_user[64] , \la_oenb_user[63] , \la_oenb_user[62] , \la_oenb_user[61] , \la_oenb_user[60] , \la_oenb_user[59] , \la_oenb_user[58] , \la_oenb_user[57] , \la_oenb_user[56] , \la_oenb_user[55] , \la_oenb_user[54] , \la_oenb_user[53] , \la_oenb_user[52] , \la_oenb_user[51] , \la_oenb_user[50] , \la_oenb_user[49] , \la_oenb_user[48] , \la_oenb_user[47] , \la_oenb_user[46] , \la_oenb_user[45] , \la_oenb_user[44] , \la_oenb_user[43] , \la_oenb_user[42] , \la_oenb_user[41] , \la_oenb_user[40] , \la_oenb_user[39] , \la_oenb_user[38] , \la_oenb_user[37] , \la_oenb_user[36] , \la_oenb_user[35] , \la_oenb_user[34] , \la_oenb_user[33] , \la_oenb_user[32] , \la_oenb_user[31] , \la_oenb_user[30] , \la_oenb_user[29] , \la_oenb_user[28] , \la_oenb_user[27] , \la_oenb_user[26] , \la_oenb_user[25] , \la_oenb_user[24] , \la_oenb_user[23] , \la_oenb_user[22] , \la_oenb_user[21] , \la_oenb_user[20] , \la_oenb_user[19] , \la_oenb_user[18] , \la_oenb_user[17] , \la_oenb_user[16] , \la_oenb_user[15] , \la_oenb_user[14] , \la_oenb_user[13] , \la_oenb_user[12] , \la_oenb_user[11] , \la_oenb_user[10] , \la_oenb_user[9] , \la_oenb_user[8] , \la_oenb_user[7] , \la_oenb_user[6] , \la_oenb_user[5] , \la_oenb_user[4] , \la_oenb_user[3] , \la_oenb_user[2] , \la_oenb_user[1] , \la_oenb_user[0] }),
+ .la_oenb_mprj({ \la_oenb_mprj[127] , \la_oenb_mprj[126] , \la_oenb_mprj[125] , \la_oenb_mprj[124] , \la_oenb_mprj[123] , \la_oenb_mprj[122] , \la_oenb_mprj[121] , \la_oenb_mprj[120] , \la_oenb_mprj[119] , \la_oenb_mprj[118] , \la_oenb_mprj[117] , \la_oenb_mprj[116] , \la_oenb_mprj[115] , \la_oenb_mprj[114] , \la_oenb_mprj[113] , \la_oenb_mprj[112] , \la_oenb_mprj[111] , \la_oenb_mprj[110] , \la_oenb_mprj[109] , \la_oenb_mprj[108] , \la_oenb_mprj[107] , \la_oenb_mprj[106] , \la_oenb_mprj[105] , \la_oenb_mprj[104] , \la_oenb_mprj[103] , \la_oenb_mprj[102] , \la_oenb_mprj[101] , \la_oenb_mprj[100] , \la_oenb_mprj[99] , \la_oenb_mprj[98] , \la_oenb_mprj[97] , \la_oenb_mprj[96] , \la_oenb_mprj[95] , \la_oenb_mprj[94] , \la_oenb_mprj[93] , \la_oenb_mprj[92] , \la_oenb_mprj[91] , \la_oenb_mprj[90] , \la_oenb_mprj[89] , \la_oenb_mprj[88] , \la_oenb_mprj[87] , \la_oenb_mprj[86] , \la_oenb_mprj[85] , \la_oenb_mprj[84] , \la_oenb_mprj[83] , \la_oenb_mprj[82] , \la_oenb_mprj[81] , \la_oenb_mprj[80] , \la_oenb_mprj[79] , \la_oenb_mprj[78] , \la_oenb_mprj[77] , \la_oenb_mprj[76] , \la_oenb_mprj[75] , \la_oenb_mprj[74] , \la_oenb_mprj[73] , \la_oenb_mprj[72] , \la_oenb_mprj[71] , \la_oenb_mprj[70] , \la_oenb_mprj[69] , \la_oenb_mprj[68] , \la_oenb_mprj[67] , \la_oenb_mprj[66] , \la_oenb_mprj[65] , \la_oenb_mprj[64] , \la_oenb_mprj[63] , \la_oenb_mprj[62] , \la_oenb_mprj[61] , \la_oenb_mprj[60] , \la_oenb_mprj[59] , \la_oenb_mprj[58] , \la_oenb_mprj[57] , \la_oenb_mprj[56] , \la_oenb_mprj[55] , \la_oenb_mprj[54] , \la_oenb_mprj[53] , \la_oenb_mprj[52] , \la_oenb_mprj[51] , \la_oenb_mprj[50] , \la_oenb_mprj[49] , \la_oenb_mprj[48] , \la_oenb_mprj[47] , \la_oenb_mprj[46] , \la_oenb_mprj[45] , \la_oenb_mprj[44] , \la_oenb_mprj[43] , \la_oenb_mprj[42] , \la_oenb_mprj[41] , \la_oenb_mprj[40] , \la_oenb_mprj[39] , \la_oenb_mprj[38] , \la_oenb_mprj[37] , \la_oenb_mprj[36] , \la_oenb_mprj[35] , \la_oenb_mprj[34] , \la_oenb_mprj[33] , \la_oenb_mprj[32] , \la_oenb_mprj[31] , \la_oenb_mprj[30] , \la_oenb_mprj[29] , \la_oenb_mprj[28] , \la_oenb_mprj[27] , \la_oenb_mprj[26] , \la_oenb_mprj[25] , \la_oenb_mprj[24] , \la_oenb_mprj[23] , \la_oenb_mprj[22] , \la_oenb_mprj[21] , \la_oenb_mprj[20] , \la_oenb_mprj[19] , \la_oenb_mprj[18] , \la_oenb_mprj[17] , \la_oenb_mprj[16] , \la_oenb_mprj[15] , \la_oenb_mprj[14] , \la_oenb_mprj[13] , \la_oenb_mprj[12] , \la_oenb_mprj[11] , \la_oenb_mprj[10] , \la_oenb_mprj[9] , \la_oenb_mprj[8] , \la_oenb_mprj[7] , \la_oenb_mprj[6] , \la_oenb_mprj[5] , \la_oenb_mprj[4] , \la_oenb_mprj[3] , \la_oenb_mprj[2] , \la_oenb_mprj[1] , \la_oenb_mprj[0] }),
+ .mprj_ack_i_core(mprj_ack_i_core),
+ .mprj_ack_i_user(mprj_ack_i_user),
+ .mprj_adr_o_core({ \mprj_adr_o_core[31] , \mprj_adr_o_core[30] , \mprj_adr_o_core[29] , \mprj_adr_o_core[28] , \mprj_adr_o_core[27] , \mprj_adr_o_core[26] , \mprj_adr_o_core[25] , \mprj_adr_o_core[24] , \mprj_adr_o_core[23] , \mprj_adr_o_core[22] , \mprj_adr_o_core[21] , \mprj_adr_o_core[20] , \mprj_adr_o_core[19] , \mprj_adr_o_core[18] , \mprj_adr_o_core[17] , \mprj_adr_o_core[16] , \mprj_adr_o_core[15] , \mprj_adr_o_core[14] , \mprj_adr_o_core[13] , \mprj_adr_o_core[12] , \mprj_adr_o_core[11] , \mprj_adr_o_core[10] , \mprj_adr_o_core[9] , \mprj_adr_o_core[8] , \mprj_adr_o_core[7] , \mprj_adr_o_core[6] , \mprj_adr_o_core[5] , \mprj_adr_o_core[4] , \mprj_adr_o_core[3] , \mprj_adr_o_core[2] , \mprj_adr_o_core[1] , \mprj_adr_o_core[0] }),
+ .mprj_adr_o_user({ \mprj_adr_o_user[31] , \mprj_adr_o_user[30] , \mprj_adr_o_user[29] , \mprj_adr_o_user[28] , \mprj_adr_o_user[27] , \mprj_adr_o_user[26] , \mprj_adr_o_user[25] , \mprj_adr_o_user[24] , \mprj_adr_o_user[23] , \mprj_adr_o_user[22] , \mprj_adr_o_user[21] , \mprj_adr_o_user[20] , \mprj_adr_o_user[19] , \mprj_adr_o_user[18] , \mprj_adr_o_user[17] , \mprj_adr_o_user[16] , \mprj_adr_o_user[15] , \mprj_adr_o_user[14] , \mprj_adr_o_user[13] , \mprj_adr_o_user[12] , \mprj_adr_o_user[11] , \mprj_adr_o_user[10] , \mprj_adr_o_user[9] , \mprj_adr_o_user[8] , \mprj_adr_o_user[7] , \mprj_adr_o_user[6] , \mprj_adr_o_user[5] , \mprj_adr_o_user[4] , \mprj_adr_o_user[3] , \mprj_adr_o_user[2] , \mprj_adr_o_user[1] , \mprj_adr_o_user[0] }),
+ .mprj_cyc_o_core(mprj_cyc_o_core),
+ .mprj_cyc_o_user(mprj_cyc_o_user),
+ .mprj_dat_i_core({ \mprj_dat_i_core[31] , \mprj_dat_i_core[30] , \mprj_dat_i_core[29] , \mprj_dat_i_core[28] , \mprj_dat_i_core[27] , \mprj_dat_i_core[26] , \mprj_dat_i_core[25] , \mprj_dat_i_core[24] , \mprj_dat_i_core[23] , \mprj_dat_i_core[22] , \mprj_dat_i_core[21] , \mprj_dat_i_core[20] , \mprj_dat_i_core[19] , \mprj_dat_i_core[18] , \mprj_dat_i_core[17] , \mprj_dat_i_core[16] , \mprj_dat_i_core[15] , \mprj_dat_i_core[14] , \mprj_dat_i_core[13] , \mprj_dat_i_core[12] , \mprj_dat_i_core[11] , \mprj_dat_i_core[10] , \mprj_dat_i_core[9] , \mprj_dat_i_core[8] , \mprj_dat_i_core[7] , \mprj_dat_i_core[6] , \mprj_dat_i_core[5] , \mprj_dat_i_core[4] , \mprj_dat_i_core[3] , \mprj_dat_i_core[2] , \mprj_dat_i_core[1] , \mprj_dat_i_core[0] }),
+ .mprj_dat_i_user({ \mprj_dat_i_user[31] , \mprj_dat_i_user[30] , \mprj_dat_i_user[29] , \mprj_dat_i_user[28] , \mprj_dat_i_user[27] , \mprj_dat_i_user[26] , \mprj_dat_i_user[25] , \mprj_dat_i_user[24] , \mprj_dat_i_user[23] , \mprj_dat_i_user[22] , \mprj_dat_i_user[21] , \mprj_dat_i_user[20] , \mprj_dat_i_user[19] , \mprj_dat_i_user[18] , \mprj_dat_i_user[17] , \mprj_dat_i_user[16] , \mprj_dat_i_user[15] , \mprj_dat_i_user[14] , \mprj_dat_i_user[13] , \mprj_dat_i_user[12] , \mprj_dat_i_user[11] , \mprj_dat_i_user[10] , \mprj_dat_i_user[9] , \mprj_dat_i_user[8] , \mprj_dat_i_user[7] , \mprj_dat_i_user[6] , \mprj_dat_i_user[5] , \mprj_dat_i_user[4] , \mprj_dat_i_user[3] , \mprj_dat_i_user[2] , \mprj_dat_i_user[1] , \mprj_dat_i_user[0] }),
+ .mprj_dat_o_core({ \mprj_dat_o_core[31] , \mprj_dat_o_core[30] , \mprj_dat_o_core[29] , \mprj_dat_o_core[28] , \mprj_dat_o_core[27] , \mprj_dat_o_core[26] , \mprj_dat_o_core[25] , \mprj_dat_o_core[24] , \mprj_dat_o_core[23] , \mprj_dat_o_core[22] , \mprj_dat_o_core[21] , \mprj_dat_o_core[20] , \mprj_dat_o_core[19] , \mprj_dat_o_core[18] , \mprj_dat_o_core[17] , \mprj_dat_o_core[16] , \mprj_dat_o_core[15] , \mprj_dat_o_core[14] , \mprj_dat_o_core[13] , \mprj_dat_o_core[12] , \mprj_dat_o_core[11] , \mprj_dat_o_core[10] , \mprj_dat_o_core[9] , \mprj_dat_o_core[8] , \mprj_dat_o_core[7] , \mprj_dat_o_core[6] , \mprj_dat_o_core[5] , \mprj_dat_o_core[4] , \mprj_dat_o_core[3] , \mprj_dat_o_core[2] , \mprj_dat_o_core[1] , \mprj_dat_o_core[0] }),
+ .mprj_dat_o_user({ \mprj_dat_o_user[31] , \mprj_dat_o_user[30] , \mprj_dat_o_user[29] , \mprj_dat_o_user[28] , \mprj_dat_o_user[27] , \mprj_dat_o_user[26] , \mprj_dat_o_user[25] , \mprj_dat_o_user[24] , \mprj_dat_o_user[23] , \mprj_dat_o_user[22] , \mprj_dat_o_user[21] , \mprj_dat_o_user[20] , \mprj_dat_o_user[19] , \mprj_dat_o_user[18] , \mprj_dat_o_user[17] , \mprj_dat_o_user[16] , \mprj_dat_o_user[15] , \mprj_dat_o_user[14] , \mprj_dat_o_user[13] , \mprj_dat_o_user[12] , \mprj_dat_o_user[11] , \mprj_dat_o_user[10] , \mprj_dat_o_user[9] , \mprj_dat_o_user[8] , \mprj_dat_o_user[7] , \mprj_dat_o_user[6] , \mprj_dat_o_user[5] , \mprj_dat_o_user[4] , \mprj_dat_o_user[3] , \mprj_dat_o_user[2] , \mprj_dat_o_user[1] , \mprj_dat_o_user[0] }),
+ .mprj_iena_wb(mprj_iena_wb),
+ .mprj_sel_o_core({ \mprj_sel_o_core[3] , \mprj_sel_o_core[2] , \mprj_sel_o_core[1] , \mprj_sel_o_core[0] }),
+ .mprj_sel_o_user({ \mprj_sel_o_user[3] , \mprj_sel_o_user[2] , \mprj_sel_o_user[1] , \mprj_sel_o_user[0] }),
+ .mprj_stb_o_core(mprj_stb_o_core),
+ .mprj_stb_o_user(mprj_stb_o_user),
+ .mprj_we_o_core(mprj_we_o_core),
+ .mprj_we_o_user(mprj_we_o_user),
+ .user1_vcc_powergood(mprj_vcc_pwrgood),
+ .user1_vdd_powergood(mprj_vdd_pwrgood),
+ .user2_vcc_powergood(mprj2_vcc_pwrgood),
+ .user2_vdd_powergood(mprj2_vdd_pwrgood),
+ .user_clock(mprj_clock),
+ .user_clock2(mprj_clock2),
+ .user_irq({ \user_irq[2] , \user_irq[1] , \user_irq[0] }),
+ .user_irq_core({ \user_irq_core[2] , \user_irq_core[1] , \user_irq_core[0] }),
+ .user_irq_ena({ \user_irq_ena[2] , \user_irq_ena[1] , \user_irq_ena[0] }),
+ .user_reset(mprj_reset),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vccd2(vccd2_core),
+ .vdda1(vdda1_core),
+ .vdda2(vdda2_core),
+ .vssa1(vssa1_core),
+ .vssa2(vssa2_core),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .vssd2(vssd2_core)
+ );
+ user_project_wrapper mprj (
+ .analog_io({ \user_analog_io[28] , \user_analog_io[27] , \user_analog_io[26] , \user_analog_io[25] , \user_analog_io[24] , \user_analog_io[23] , \user_analog_io[22] , \user_analog_io[21] , \user_analog_io[20] , \user_analog_io[19] , \user_analog_io[18] , \user_analog_io[17] , \user_analog_io[16] , \user_analog_io[15] , \user_analog_io[14] , \user_analog_io[13] , \user_analog_io[12] , \user_analog_io[11] , \user_analog_io[10] , \user_analog_io[9] , \user_analog_io[8] , \user_analog_io[7] , \user_analog_io[6] , \user_analog_io[5] , \user_analog_io[4] , \user_analog_io[3] , \user_analog_io[2] , \user_analog_io[1] , \user_analog_io[0] }),
+ .io_in({ \user_io_in[37] , \user_io_in[36] , \user_io_in[35] , \user_io_in[34] , \user_io_in[33] , \user_io_in[32] , \user_io_in[31] , \user_io_in[30] , \user_io_in[29] , \user_io_in[28] , \user_io_in[27] , \user_io_in[26] , \user_io_in[25] , \user_io_in[24] , \user_io_in[23] , \user_io_in[22] , \user_io_in[21] , \user_io_in[20] , \user_io_in[19] , \user_io_in[18] , \user_io_in[17] , \user_io_in[16] , \user_io_in[15] , \user_io_in[14] , \user_io_in[13] , \user_io_in[12] , \user_io_in[11] , \user_io_in[10] , \user_io_in[9] , \user_io_in[8] , \user_io_in[7] , \user_io_in[6] , \user_io_in[5] , \user_io_in[4] , \user_io_in[3] , \user_io_in[2] , \user_io_in[1] , \user_io_in[0] }),
+ .io_oeb({ \user_io_oeb[37] , \user_io_oeb[36] , \user_io_oeb[35] , \user_io_oeb[34] , \user_io_oeb[33] , \user_io_oeb[32] , \user_io_oeb[31] , \user_io_oeb[30] , \user_io_oeb[29] , \user_io_oeb[28] , \user_io_oeb[27] , \user_io_oeb[26] , \user_io_oeb[25] , \user_io_oeb[24] , \user_io_oeb[23] , \user_io_oeb[22] , \user_io_oeb[21] , \user_io_oeb[20] , \user_io_oeb[19] , \user_io_oeb[18] , \user_io_oeb[17] , \user_io_oeb[16] , \user_io_oeb[15] , \user_io_oeb[14] , \user_io_oeb[13] , \user_io_oeb[12] , \user_io_oeb[11] , \user_io_oeb[10] , \user_io_oeb[9] , \user_io_oeb[8] , \user_io_oeb[7] , \user_io_oeb[6] , \user_io_oeb[5] , \user_io_oeb[4] , \user_io_oeb[3] , \user_io_oeb[2] , \user_io_oeb[1] , \user_io_oeb[0] }),
+ .io_out({ \user_io_out[37] , \user_io_out[36] , \user_io_out[35] , \user_io_out[34] , \user_io_out[33] , \user_io_out[32] , \user_io_out[31] , \user_io_out[30] , \user_io_out[29] , \user_io_out[28] , \user_io_out[27] , \user_io_out[26] , \user_io_out[25] , \user_io_out[24] , \user_io_out[23] , \user_io_out[22] , \user_io_out[21] , \user_io_out[20] , \user_io_out[19] , \user_io_out[18] , \user_io_out[17] , \user_io_out[16] , \user_io_out[15] , \user_io_out[14] , \user_io_out[13] , \user_io_out[12] , \user_io_out[11] , \user_io_out[10] , \user_io_out[9] , \user_io_out[8] , \user_io_out[7] , \user_io_out[6] , \user_io_out[5] , \user_io_out[4] , \user_io_out[3] , \user_io_out[2] , \user_io_out[1] , \user_io_out[0] }),
+ .la_data_in({ \la_data_in_user[127] , \la_data_in_user[126] , \la_data_in_user[125] , \la_data_in_user[124] , \la_data_in_user[123] , \la_data_in_user[122] , \la_data_in_user[121] , \la_data_in_user[120] , \la_data_in_user[119] , \la_data_in_user[118] , \la_data_in_user[117] , \la_data_in_user[116] , \la_data_in_user[115] , \la_data_in_user[114] , \la_data_in_user[113] , \la_data_in_user[112] , \la_data_in_user[111] , \la_data_in_user[110] , \la_data_in_user[109] , \la_data_in_user[108] , \la_data_in_user[107] , \la_data_in_user[106] , \la_data_in_user[105] , \la_data_in_user[104] , \la_data_in_user[103] , \la_data_in_user[102] , \la_data_in_user[101] , \la_data_in_user[100] , \la_data_in_user[99] , \la_data_in_user[98] , \la_data_in_user[97] , \la_data_in_user[96] , \la_data_in_user[95] , \la_data_in_user[94] , \la_data_in_user[93] , \la_data_in_user[92] , \la_data_in_user[91] , \la_data_in_user[90] , \la_data_in_user[89] , \la_data_in_user[88] , \la_data_in_user[87] , \la_data_in_user[86] , \la_data_in_user[85] , \la_data_in_user[84] , \la_data_in_user[83] , \la_data_in_user[82] , \la_data_in_user[81] , \la_data_in_user[80] , \la_data_in_user[79] , \la_data_in_user[78] , \la_data_in_user[77] , \la_data_in_user[76] , \la_data_in_user[75] , \la_data_in_user[74] , \la_data_in_user[73] , \la_data_in_user[72] , \la_data_in_user[71] , \la_data_in_user[70] , \la_data_in_user[69] , \la_data_in_user[68] , \la_data_in_user[67] , \la_data_in_user[66] , \la_data_in_user[65] , \la_data_in_user[64] , \la_data_in_user[63] , \la_data_in_user[62] , \la_data_in_user[61] , \la_data_in_user[60] , \la_data_in_user[59] , \la_data_in_user[58] , \la_data_in_user[57] , \la_data_in_user[56] , \la_data_in_user[55] , \la_data_in_user[54] , \la_data_in_user[53] , \la_data_in_user[52] , \la_data_in_user[51] , \la_data_in_user[50] , \la_data_in_user[49] , \la_data_in_user[48] , \la_data_in_user[47] , \la_data_in_user[46] , \la_data_in_user[45] , \la_data_in_user[44] , \la_data_in_user[43] , \la_data_in_user[42] , \la_data_in_user[41] , \la_data_in_user[40] , \la_data_in_user[39] , \la_data_in_user[38] , \la_data_in_user[37] , \la_data_in_user[36] , \la_data_in_user[35] , \la_data_in_user[34] , \la_data_in_user[33] , \la_data_in_user[32] , \la_data_in_user[31] , \la_data_in_user[30] , \la_data_in_user[29] , \la_data_in_user[28] , \la_data_in_user[27] , \la_data_in_user[26] , \la_data_in_user[25] , \la_data_in_user[24] , \la_data_in_user[23] , \la_data_in_user[22] , \la_data_in_user[21] , \la_data_in_user[20] , \la_data_in_user[19] , \la_data_in_user[18] , \la_data_in_user[17] , \la_data_in_user[16] , \la_data_in_user[15] , \la_data_in_user[14] , \la_data_in_user[13] , \la_data_in_user[12] , \la_data_in_user[11] , \la_data_in_user[10] , \la_data_in_user[9] , \la_data_in_user[8] , \la_data_in_user[7] , \la_data_in_user[6] , \la_data_in_user[5] , \la_data_in_user[4] , \la_data_in_user[3] , \la_data_in_user[2] , \la_data_in_user[1] , \la_data_in_user[0] }),
+ .la_data_out({ \la_data_out_user[127] , \la_data_out_user[126] , \la_data_out_user[125] , \la_data_out_user[124] , \la_data_out_user[123] , \la_data_out_user[122] , \la_data_out_user[121] , \la_data_out_user[120] , \la_data_out_user[119] , \la_data_out_user[118] , \la_data_out_user[117] , \la_data_out_user[116] , \la_data_out_user[115] , \la_data_out_user[114] , \la_data_out_user[113] , \la_data_out_user[112] , \la_data_out_user[111] , \la_data_out_user[110] , \la_data_out_user[109] , \la_data_out_user[108] , \la_data_out_user[107] , \la_data_out_user[106] , \la_data_out_user[105] , \la_data_out_user[104] , \la_data_out_user[103] , \la_data_out_user[102] , \la_data_out_user[101] , \la_data_out_user[100] , \la_data_out_user[99] , \la_data_out_user[98] , \la_data_out_user[97] , \la_data_out_user[96] , \la_data_out_user[95] , \la_data_out_user[94] , \la_data_out_user[93] , \la_data_out_user[92] , \la_data_out_user[91] , \la_data_out_user[90] , \la_data_out_user[89] , \la_data_out_user[88] , \la_data_out_user[87] , \la_data_out_user[86] , \la_data_out_user[85] , \la_data_out_user[84] , \la_data_out_user[83] , \la_data_out_user[82] , \la_data_out_user[81] , \la_data_out_user[80] , \la_data_out_user[79] , \la_data_out_user[78] , \la_data_out_user[77] , \la_data_out_user[76] , \la_data_out_user[75] , \la_data_out_user[74] , \la_data_out_user[73] , \la_data_out_user[72] , \la_data_out_user[71] , \la_data_out_user[70] , \la_data_out_user[69] , \la_data_out_user[68] , \la_data_out_user[67] , \la_data_out_user[66] , \la_data_out_user[65] , \la_data_out_user[64] , \la_data_out_user[63] , \la_data_out_user[62] , \la_data_out_user[61] , \la_data_out_user[60] , \la_data_out_user[59] , \la_data_out_user[58] , \la_data_out_user[57] , \la_data_out_user[56] , \la_data_out_user[55] , \la_data_out_user[54] , \la_data_out_user[53] , \la_data_out_user[52] , \la_data_out_user[51] , \la_data_out_user[50] , \la_data_out_user[49] , \la_data_out_user[48] , \la_data_out_user[47] , \la_data_out_user[46] , \la_data_out_user[45] , \la_data_out_user[44] , \la_data_out_user[43] , \la_data_out_user[42] , \la_data_out_user[41] , \la_data_out_user[40] , \la_data_out_user[39] , \la_data_out_user[38] , \la_data_out_user[37] , \la_data_out_user[36] , \la_data_out_user[35] , \la_data_out_user[34] , \la_data_out_user[33] , \la_data_out_user[32] , \la_data_out_user[31] , \la_data_out_user[30] , \la_data_out_user[29] , \la_data_out_user[28] , \la_data_out_user[27] , \la_data_out_user[26] , \la_data_out_user[25] , \la_data_out_user[24] , \la_data_out_user[23] , \la_data_out_user[22] , \la_data_out_user[21] , \la_data_out_user[20] , \la_data_out_user[19] , \la_data_out_user[18] , \la_data_out_user[17] , \la_data_out_user[16] , \la_data_out_user[15] , \la_data_out_user[14] , \la_data_out_user[13] , \la_data_out_user[12] , \la_data_out_user[11] , \la_data_out_user[10] , \la_data_out_user[9] , \la_data_out_user[8] , \la_data_out_user[7] , \la_data_out_user[6] , \la_data_out_user[5] , \la_data_out_user[4] , \la_data_out_user[3] , \la_data_out_user[2] , \la_data_out_user[1] , \la_data_out_user[0] }),
+ .la_oenb({ \la_oenb_user[127] , \la_oenb_user[126] , \la_oenb_user[125] , \la_oenb_user[124] , \la_oenb_user[123] , \la_oenb_user[122] , \la_oenb_user[121] , \la_oenb_user[120] , \la_oenb_user[119] , \la_oenb_user[118] , \la_oenb_user[117] , \la_oenb_user[116] , \la_oenb_user[115] , \la_oenb_user[114] , \la_oenb_user[113] , \la_oenb_user[112] , \la_oenb_user[111] , \la_oenb_user[110] , \la_oenb_user[109] , \la_oenb_user[108] , \la_oenb_user[107] , \la_oenb_user[106] , \la_oenb_user[105] , \la_oenb_user[104] , \la_oenb_user[103] , \la_oenb_user[102] , \la_oenb_user[101] , \la_oenb_user[100] , \la_oenb_user[99] , \la_oenb_user[98] , \la_oenb_user[97] , \la_oenb_user[96] , \la_oenb_user[95] , \la_oenb_user[94] , \la_oenb_user[93] , \la_oenb_user[92] , \la_oenb_user[91] , \la_oenb_user[90] , \la_oenb_user[89] , \la_oenb_user[88] , \la_oenb_user[87] , \la_oenb_user[86] , \la_oenb_user[85] , \la_oenb_user[84] , \la_oenb_user[83] , \la_oenb_user[82] , \la_oenb_user[81] , \la_oenb_user[80] , \la_oenb_user[79] , \la_oenb_user[78] , \la_oenb_user[77] , \la_oenb_user[76] , \la_oenb_user[75] , \la_oenb_user[74] , \la_oenb_user[73] , \la_oenb_user[72] , \la_oenb_user[71] , \la_oenb_user[70] , \la_oenb_user[69] , \la_oenb_user[68] , \la_oenb_user[67] , \la_oenb_user[66] , \la_oenb_user[65] , \la_oenb_user[64] , \la_oenb_user[63] , \la_oenb_user[62] , \la_oenb_user[61] , \la_oenb_user[60] , \la_oenb_user[59] , \la_oenb_user[58] , \la_oenb_user[57] , \la_oenb_user[56] , \la_oenb_user[55] , \la_oenb_user[54] , \la_oenb_user[53] , \la_oenb_user[52] , \la_oenb_user[51] , \la_oenb_user[50] , \la_oenb_user[49] , \la_oenb_user[48] , \la_oenb_user[47] , \la_oenb_user[46] , \la_oenb_user[45] , \la_oenb_user[44] , \la_oenb_user[43] , \la_oenb_user[42] , \la_oenb_user[41] , \la_oenb_user[40] , \la_oenb_user[39] , \la_oenb_user[38] , \la_oenb_user[37] , \la_oenb_user[36] , \la_oenb_user[35] , \la_oenb_user[34] , \la_oenb_user[33] , \la_oenb_user[32] , \la_oenb_user[31] , \la_oenb_user[30] , \la_oenb_user[29] , \la_oenb_user[28] , \la_oenb_user[27] , \la_oenb_user[26] , \la_oenb_user[25] , \la_oenb_user[24] , \la_oenb_user[23] , \la_oenb_user[22] , \la_oenb_user[21] , \la_oenb_user[20] , \la_oenb_user[19] , \la_oenb_user[18] , \la_oenb_user[17] , \la_oenb_user[16] , \la_oenb_user[15] , \la_oenb_user[14] , \la_oenb_user[13] , \la_oenb_user[12] , \la_oenb_user[11] , \la_oenb_user[10] , \la_oenb_user[9] , \la_oenb_user[8] , \la_oenb_user[7] , \la_oenb_user[6] , \la_oenb_user[5] , \la_oenb_user[4] , \la_oenb_user[3] , \la_oenb_user[2] , \la_oenb_user[1] , \la_oenb_user[0] }),
+ .user_clock2(mprj_clock2),
+ .user_irq({ \user_irq_core[2] , \user_irq_core[1] , \user_irq_core[0] }),
+ .vccd1(vccd1_core),
+ .vccd2(vccd2_core),
+ .vdda1(vdda1_core),
+ .vdda2(vdda2_core),
+ .vssa1(vssa1_core),
+ .vssa2(vssa2_core),
+ .vssd1(vssd1_core),
+ .vssd2(vssd2_core),
+ .wb_clk_i(mprj_clock),
+ .wb_rst_i(mprj_reset),
+ .wbs_ack_o(mprj_ack_i_user),
+ .wbs_adr_i({ \mprj_adr_o_user[31] , \mprj_adr_o_user[30] , \mprj_adr_o_user[29] , \mprj_adr_o_user[28] , \mprj_adr_o_user[27] , \mprj_adr_o_user[26] , \mprj_adr_o_user[25] , \mprj_adr_o_user[24] , \mprj_adr_o_user[23] , \mprj_adr_o_user[22] , \mprj_adr_o_user[21] , \mprj_adr_o_user[20] , \mprj_adr_o_user[19] , \mprj_adr_o_user[18] , \mprj_adr_o_user[17] , \mprj_adr_o_user[16] , \mprj_adr_o_user[15] , \mprj_adr_o_user[14] , \mprj_adr_o_user[13] , \mprj_adr_o_user[12] , \mprj_adr_o_user[11] , \mprj_adr_o_user[10] , \mprj_adr_o_user[9] , \mprj_adr_o_user[8] , \mprj_adr_o_user[7] , \mprj_adr_o_user[6] , \mprj_adr_o_user[5] , \mprj_adr_o_user[4] , \mprj_adr_o_user[3] , \mprj_adr_o_user[2] , \mprj_adr_o_user[1] , \mprj_adr_o_user[0] }),
+ .wbs_cyc_i(mprj_cyc_o_user),
+ .wbs_dat_i({ \mprj_dat_o_user[31] , \mprj_dat_o_user[30] , \mprj_dat_o_user[29] , \mprj_dat_o_user[28] , \mprj_dat_o_user[27] , \mprj_dat_o_user[26] , \mprj_dat_o_user[25] , \mprj_dat_o_user[24] , \mprj_dat_o_user[23] , \mprj_dat_o_user[22] , \mprj_dat_o_user[21] , \mprj_dat_o_user[20] , \mprj_dat_o_user[19] , \mprj_dat_o_user[18] , \mprj_dat_o_user[17] , \mprj_dat_o_user[16] , \mprj_dat_o_user[15] , \mprj_dat_o_user[14] , \mprj_dat_o_user[13] , \mprj_dat_o_user[12] , \mprj_dat_o_user[11] , \mprj_dat_o_user[10] , \mprj_dat_o_user[9] , \mprj_dat_o_user[8] , \mprj_dat_o_user[7] , \mprj_dat_o_user[6] , \mprj_dat_o_user[5] , \mprj_dat_o_user[4] , \mprj_dat_o_user[3] , \mprj_dat_o_user[2] , \mprj_dat_o_user[1] , \mprj_dat_o_user[0] }),
+ .wbs_dat_o({ \mprj_dat_i_user[31] , \mprj_dat_i_user[30] , \mprj_dat_i_user[29] , \mprj_dat_i_user[28] , \mprj_dat_i_user[27] , \mprj_dat_i_user[26] , \mprj_dat_i_user[25] , \mprj_dat_i_user[24] , \mprj_dat_i_user[23] , \mprj_dat_i_user[22] , \mprj_dat_i_user[21] , \mprj_dat_i_user[20] , \mprj_dat_i_user[19] , \mprj_dat_i_user[18] , \mprj_dat_i_user[17] , \mprj_dat_i_user[16] , \mprj_dat_i_user[15] , \mprj_dat_i_user[14] , \mprj_dat_i_user[13] , \mprj_dat_i_user[12] , \mprj_dat_i_user[11] , \mprj_dat_i_user[10] , \mprj_dat_i_user[9] , \mprj_dat_i_user[8] , \mprj_dat_i_user[7] , \mprj_dat_i_user[6] , \mprj_dat_i_user[5] , \mprj_dat_i_user[4] , \mprj_dat_i_user[3] , \mprj_dat_i_user[2] , \mprj_dat_i_user[1] , \mprj_dat_i_user[0] }),
+ .wbs_sel_i({ \mprj_sel_o_user[3] , \mprj_sel_o_user[2] , \mprj_sel_o_user[1] , \mprj_sel_o_user[0] }),
+ .wbs_stb_i(mprj_stb_o_user),
+ .wbs_we_i(mprj_we_o_user)
+ );
+ chip_io padframe (
+ .clock(clock),
+ .clock_core(clock_core),
+ .flash_clk(flash_clk),
+ .flash_clk_core(flash_clk_frame_buf),
+ .flash_clk_oeb_core(flash_clk_oeb_buf),
+ .flash_csb(flash_csb),
+ .flash_csb_core(flash_csb_frame_buf),
+ .flash_csb_oeb_core(flash_csb_oeb_buf),
+ .flash_io0(flash_io0),
+ .flash_io0_di_core(flash_io0_di),
+ .flash_io0_do_core(flash_io0_do_buf),
+ .flash_io0_ieb_core(flash_io0_ieb_buf),
+ .flash_io0_oeb_core(flash_io0_oeb_buf),
+ .flash_io1(flash_io1),
+ .flash_io1_di_core(flash_io1_di),
+ .flash_io1_do_core(flash_io1_do_buf),
+ .flash_io1_ieb_core(flash_io1_ieb_buf),
+ .flash_io1_oeb_core(flash_io1_oeb_buf),
+ .gpio(gpio),
+ .gpio_in_core(gpio_in_core),
+ .gpio_inenb_core(gpio_inenb_core),
+ .gpio_mode0_core(gpio_mode0_core),
+ .gpio_mode1_core(gpio_mode1_core),
+ .gpio_out_core(gpio_out_core),
+ .gpio_outenb_core(gpio_outenb_core),
+ .mprj_analog_io({ \user_analog_io[28] , \user_analog_io[27] , \user_analog_io[26] , \user_analog_io[25] , \user_analog_io[24] , \user_analog_io[23] , \user_analog_io[22] , \user_analog_io[21] , \user_analog_io[20] , \user_analog_io[19] , \user_analog_io[18] , \user_analog_io[17] , \user_analog_io[16] , \user_analog_io[15] , \user_analog_io[14] , \user_analog_io[13] , \user_analog_io[12] , \user_analog_io[11] , \user_analog_io[10] , \user_analog_io[9] , \user_analog_io[8] , \user_analog_io[7] , \user_analog_io[6] , \user_analog_io[5] , \user_analog_io[4] , \user_analog_io[3] , \user_analog_io[2] , \user_analog_io[1] , \user_analog_io[0] }),
+ .mprj_io(mprj_io),
+ .mprj_io_analog_en({ \mprj_io_analog_en[37] , \mprj_io_analog_en[36] , \mprj_io_analog_en[35] , \mprj_io_analog_en[34] , \mprj_io_analog_en[33] , \mprj_io_analog_en[32] , \mprj_io_analog_en[31] , \mprj_io_analog_en[30] , \mprj_io_analog_en[29] , \mprj_io_analog_en[28] , \mprj_io_analog_en[27] , \mprj_io_analog_en[26] , \mprj_io_analog_en[25] , \mprj_io_analog_en[24] , \mprj_io_analog_en[23] , \mprj_io_analog_en[22] , \mprj_io_analog_en[21] , \mprj_io_analog_en[20] , \mprj_io_analog_en[19] , \mprj_io_analog_en[18] , \mprj_io_analog_en[17] , \mprj_io_analog_en[16] , \mprj_io_analog_en[15] , \mprj_io_analog_en[14] , \mprj_io_analog_en[13] , \mprj_io_analog_en[12] , \mprj_io_analog_en[11] , \mprj_io_analog_en[10] , \mprj_io_analog_en[9] , \mprj_io_analog_en[8] , \mprj_io_analog_en[7] , \mprj_io_analog_en[6] , \mprj_io_analog_en[5] , \mprj_io_analog_en[4] , \mprj_io_analog_en[3] , \mprj_io_analog_en[2] , \mprj_io_analog_en[1] , \mprj_io_analog_en[0] }),
+ .mprj_io_analog_pol({ \mprj_io_analog_pol[37] , \mprj_io_analog_pol[36] , \mprj_io_analog_pol[35] , \mprj_io_analog_pol[34] , \mprj_io_analog_pol[33] , \mprj_io_analog_pol[32] , \mprj_io_analog_pol[31] , \mprj_io_analog_pol[30] , \mprj_io_analog_pol[29] , \mprj_io_analog_pol[28] , \mprj_io_analog_pol[27] , \mprj_io_analog_pol[26] , \mprj_io_analog_pol[25] , \mprj_io_analog_pol[24] , \mprj_io_analog_pol[23] , \mprj_io_analog_pol[22] , \mprj_io_analog_pol[21] , \mprj_io_analog_pol[20] , \mprj_io_analog_pol[19] , \mprj_io_analog_pol[18] , \mprj_io_analog_pol[17] , \mprj_io_analog_pol[16] , \mprj_io_analog_pol[15] , \mprj_io_analog_pol[14] , \mprj_io_analog_pol[13] , \mprj_io_analog_pol[12] , \mprj_io_analog_pol[11] , \mprj_io_analog_pol[10] , \mprj_io_analog_pol[9] , \mprj_io_analog_pol[8] , \mprj_io_analog_pol[7] , \mprj_io_analog_pol[6] , \mprj_io_analog_pol[5] , \mprj_io_analog_pol[4] , \mprj_io_analog_pol[3] , \mprj_io_analog_pol[2] , \mprj_io_analog_pol[1] , \mprj_io_analog_pol[0] }),
+ .mprj_io_analog_sel({ \mprj_io_analog_sel[37] , \mprj_io_analog_sel[36] , \mprj_io_analog_sel[35] , \mprj_io_analog_sel[34] , \mprj_io_analog_sel[33] , \mprj_io_analog_sel[32] , \mprj_io_analog_sel[31] , \mprj_io_analog_sel[30] , \mprj_io_analog_sel[29] , \mprj_io_analog_sel[28] , \mprj_io_analog_sel[27] , \mprj_io_analog_sel[26] , \mprj_io_analog_sel[25] , \mprj_io_analog_sel[24] , \mprj_io_analog_sel[23] , \mprj_io_analog_sel[22] , \mprj_io_analog_sel[21] , \mprj_io_analog_sel[20] , \mprj_io_analog_sel[19] , \mprj_io_analog_sel[18] , \mprj_io_analog_sel[17] , \mprj_io_analog_sel[16] , \mprj_io_analog_sel[15] , \mprj_io_analog_sel[14] , \mprj_io_analog_sel[13] , \mprj_io_analog_sel[12] , \mprj_io_analog_sel[11] , \mprj_io_analog_sel[10] , \mprj_io_analog_sel[9] , \mprj_io_analog_sel[8] , \mprj_io_analog_sel[7] , \mprj_io_analog_sel[6] , \mprj_io_analog_sel[5] , \mprj_io_analog_sel[4] , \mprj_io_analog_sel[3] , \mprj_io_analog_sel[2] , \mprj_io_analog_sel[1] , \mprj_io_analog_sel[0] }),
+ .mprj_io_dm({ \mprj_io_dm[113] , \mprj_io_dm[112] , \mprj_io_dm[111] , \mprj_io_dm[110] , \mprj_io_dm[109] , \mprj_io_dm[108] , \mprj_io_dm[107] , \mprj_io_dm[106] , \mprj_io_dm[105] , \mprj_io_dm[104] , \mprj_io_dm[103] , \mprj_io_dm[102] , \mprj_io_dm[101] , \mprj_io_dm[100] , \mprj_io_dm[99] , \mprj_io_dm[98] , \mprj_io_dm[97] , \mprj_io_dm[96] , \mprj_io_dm[95] , \mprj_io_dm[94] , \mprj_io_dm[93] , \mprj_io_dm[92] , \mprj_io_dm[91] , \mprj_io_dm[90] , \mprj_io_dm[89] , \mprj_io_dm[88] , \mprj_io_dm[87] , \mprj_io_dm[86] , \mprj_io_dm[85] , \mprj_io_dm[84] , \mprj_io_dm[83] , \mprj_io_dm[82] , \mprj_io_dm[81] , \mprj_io_dm[80] , \mprj_io_dm[79] , \mprj_io_dm[78] , \mprj_io_dm[77] , \mprj_io_dm[76] , \mprj_io_dm[75] , \mprj_io_dm[74] , \mprj_io_dm[73] , \mprj_io_dm[72] , \mprj_io_dm[71] , \mprj_io_dm[70] , \mprj_io_dm[69] , \mprj_io_dm[68] , \mprj_io_dm[67] , \mprj_io_dm[66] , \mprj_io_dm[65] , \mprj_io_dm[64] , \mprj_io_dm[63] , \mprj_io_dm[62] , \mprj_io_dm[61] , \mprj_io_dm[60] , \mprj_io_dm[59] , \mprj_io_dm[58] , \mprj_io_dm[57] , \mprj_io_dm[56] , \mprj_io_dm[55] , \mprj_io_dm[54] , \mprj_io_dm[53] , \mprj_io_dm[52] , \mprj_io_dm[51] , \mprj_io_dm[50] , \mprj_io_dm[49] , \mprj_io_dm[48] , \mprj_io_dm[47] , \mprj_io_dm[46] , \mprj_io_dm[45] , \mprj_io_dm[44] , \mprj_io_dm[43] , \mprj_io_dm[42] , \mprj_io_dm[41] , \mprj_io_dm[40] , \mprj_io_dm[39] , \mprj_io_dm[38] , \mprj_io_dm[37] , \mprj_io_dm[36] , \mprj_io_dm[35] , \mprj_io_dm[34] , \mprj_io_dm[33] , \mprj_io_dm[32] , \mprj_io_dm[31] , \mprj_io_dm[30] , \mprj_io_dm[29] , \mprj_io_dm[28] , \mprj_io_dm[27] , \mprj_io_dm[26] , \mprj_io_dm[25] , \mprj_io_dm[24] , \mprj_io_dm[23] , \mprj_io_dm[22] , \mprj_io_dm[21] , \mprj_io_dm[20] , \mprj_io_dm[19] , \mprj_io_dm[18] , \mprj_io_dm[17] , \mprj_io_dm[16] , \mprj_io_dm[15] , \mprj_io_dm[14] , \mprj_io_dm[13] , \mprj_io_dm[12] , \mprj_io_dm[11] , \mprj_io_dm[10] , \mprj_io_dm[9] , \mprj_io_dm[8] , \mprj_io_dm[7] , \mprj_io_dm[6] , \mprj_io_dm[5] , \mprj_io_dm[4] , \mprj_io_dm[3] , \mprj_io_dm[2] , \mprj_io_dm[1] , \mprj_io_dm[0] }),
+ .mprj_io_holdover({ \mprj_io_holdover[37] , \mprj_io_holdover[36] , \mprj_io_holdover[35] , \mprj_io_holdover[34] , \mprj_io_holdover[33] , \mprj_io_holdover[32] , \mprj_io_holdover[31] , \mprj_io_holdover[30] , \mprj_io_holdover[29] , \mprj_io_holdover[28] , \mprj_io_holdover[27] , \mprj_io_holdover[26] , \mprj_io_holdover[25] , \mprj_io_holdover[24] , \mprj_io_holdover[23] , \mprj_io_holdover[22] , \mprj_io_holdover[21] , \mprj_io_holdover[20] , \mprj_io_holdover[19] , \mprj_io_holdover[18] , \mprj_io_holdover[17] , \mprj_io_holdover[16] , \mprj_io_holdover[15] , \mprj_io_holdover[14] , \mprj_io_holdover[13] , \mprj_io_holdover[12] , \mprj_io_holdover[11] , \mprj_io_holdover[10] , \mprj_io_holdover[9] , \mprj_io_holdover[8] , \mprj_io_holdover[7] , \mprj_io_holdover[6] , \mprj_io_holdover[5] , \mprj_io_holdover[4] , \mprj_io_holdover[3] , \mprj_io_holdover[2] , \mprj_io_holdover[1] , \mprj_io_holdover[0] }),
+ .mprj_io_ib_mode_sel({ \mprj_io_ib_mode_sel[37] , \mprj_io_ib_mode_sel[36] , \mprj_io_ib_mode_sel[35] , \mprj_io_ib_mode_sel[34] , \mprj_io_ib_mode_sel[33] , \mprj_io_ib_mode_sel[32] , \mprj_io_ib_mode_sel[31] , \mprj_io_ib_mode_sel[30] , \mprj_io_ib_mode_sel[29] , \mprj_io_ib_mode_sel[28] , \mprj_io_ib_mode_sel[27] , \mprj_io_ib_mode_sel[26] , \mprj_io_ib_mode_sel[25] , \mprj_io_ib_mode_sel[24] , \mprj_io_ib_mode_sel[23] , \mprj_io_ib_mode_sel[22] , \mprj_io_ib_mode_sel[21] , \mprj_io_ib_mode_sel[20] , \mprj_io_ib_mode_sel[19] , \mprj_io_ib_mode_sel[18] , \mprj_io_ib_mode_sel[17] , \mprj_io_ib_mode_sel[16] , \mprj_io_ib_mode_sel[15] , \mprj_io_ib_mode_sel[14] , \mprj_io_ib_mode_sel[13] , \mprj_io_ib_mode_sel[12] , \mprj_io_ib_mode_sel[11] , \mprj_io_ib_mode_sel[10] , \mprj_io_ib_mode_sel[9] , \mprj_io_ib_mode_sel[8] , \mprj_io_ib_mode_sel[7] , \mprj_io_ib_mode_sel[6] , \mprj_io_ib_mode_sel[5] , \mprj_io_ib_mode_sel[4] , \mprj_io_ib_mode_sel[3] , \mprj_io_ib_mode_sel[2] , \mprj_io_ib_mode_sel[1] , \mprj_io_ib_mode_sel[0] }),
+ .mprj_io_in({ \mprj_io_in[37] , \mprj_io_in[36] , \mprj_io_in[35] , \mprj_io_in[34] , \mprj_io_in[33] , \mprj_io_in[32] , \mprj_io_in[31] , \mprj_io_in[30] , \mprj_io_in[29] , \mprj_io_in[28] , \mprj_io_in[27] , \mprj_io_in[26] , \mprj_io_in[25] , \mprj_io_in[24] , \mprj_io_in[23] , \mprj_io_in[22] , \mprj_io_in[21] , \mprj_io_in[20] , \mprj_io_in[19] , \mprj_io_in[18] , \mprj_io_in[17] , \mprj_io_in[16] , \mprj_io_in[15] , \mprj_io_in[14] , \mprj_io_in[13] , \mprj_io_in[12] , \mprj_io_in[11] , \mprj_io_in[10] , \mprj_io_in[9] , \mprj_io_in[8] , \mprj_io_in[7] , \mprj_io_in[6] , \mprj_io_in[5] , \mprj_io_in[4] , \mprj_io_in[3] , \mprj_io_in[2] , \mprj_io_in[1] , \mprj_io_in[0] }),
+ .mprj_io_inp_dis({ \mprj_io_inp_dis[37] , \mprj_io_inp_dis[36] , \mprj_io_inp_dis[35] , \mprj_io_inp_dis[34] , \mprj_io_inp_dis[33] , \mprj_io_inp_dis[32] , \mprj_io_inp_dis[31] , \mprj_io_inp_dis[30] , \mprj_io_inp_dis[29] , \mprj_io_inp_dis[28] , \mprj_io_inp_dis[27] , \mprj_io_inp_dis[26] , \mprj_io_inp_dis[25] , \mprj_io_inp_dis[24] , \mprj_io_inp_dis[23] , \mprj_io_inp_dis[22] , \mprj_io_inp_dis[21] , \mprj_io_inp_dis[20] , \mprj_io_inp_dis[19] , \mprj_io_inp_dis[18] , \mprj_io_inp_dis[17] , \mprj_io_inp_dis[16] , \mprj_io_inp_dis[15] , \mprj_io_inp_dis[14] , \mprj_io_inp_dis[13] , \mprj_io_inp_dis[12] , \mprj_io_inp_dis[11] , \mprj_io_inp_dis[10] , \mprj_io_inp_dis[9] , \mprj_io_inp_dis[8] , \mprj_io_inp_dis[7] , \mprj_io_inp_dis[6] , \mprj_io_inp_dis[5] , \mprj_io_inp_dis[4] , \mprj_io_inp_dis[3] , \mprj_io_inp_dis[2] , \mprj_io_inp_dis[1] , \mprj_io_inp_dis[0] }),
+ .mprj_io_oeb({ \mprj_io_oeb[37] , \mprj_io_oeb[36] , \mprj_io_oeb[35] , \mprj_io_oeb[34] , \mprj_io_oeb[33] , \mprj_io_oeb[32] , \mprj_io_oeb[31] , \mprj_io_oeb[30] , \mprj_io_oeb[29] , \mprj_io_oeb[28] , \mprj_io_oeb[27] , \mprj_io_oeb[26] , \mprj_io_oeb[25] , \mprj_io_oeb[24] , \mprj_io_oeb[23] , \mprj_io_oeb[22] , \mprj_io_oeb[21] , \mprj_io_oeb[20] , \mprj_io_oeb[19] , \mprj_io_oeb[18] , \mprj_io_oeb[17] , \mprj_io_oeb[16] , \mprj_io_oeb[15] , \mprj_io_oeb[14] , \mprj_io_oeb[13] , \mprj_io_oeb[12] , \mprj_io_oeb[11] , \mprj_io_oeb[10] , \mprj_io_oeb[9] , \mprj_io_oeb[8] , \mprj_io_oeb[7] , \mprj_io_oeb[6] , \mprj_io_oeb[5] , \mprj_io_oeb[4] , \mprj_io_oeb[3] , \mprj_io_oeb[2] , \mprj_io_oeb[1] , \mprj_io_oeb[0] }),
+ .mprj_io_one({ \mprj_io_one[37] , \mprj_io_one[36] , \mprj_io_one[35] , \mprj_io_one[34] , \mprj_io_one[33] , \mprj_io_one[32] , \mprj_io_one[31] , \mprj_io_one[30] , \mprj_io_one[29] , \mprj_io_one[28] , \mprj_io_one[27] , \mprj_io_one[26] , \mprj_io_one[25] , \mprj_io_one[24] , \mprj_io_one[23] , \mprj_io_one[22] , \mprj_io_one[21] , \mprj_io_one[20] , \mprj_io_one[19] , \mprj_io_one[18] , \mprj_io_one[17] , \mprj_io_one[16] , \mprj_io_one[15] , \mprj_io_one[14] , \mprj_io_one[13] , \mprj_io_one[12] , \mprj_io_one[11] , \mprj_io_one[10] , \mprj_io_one[9] , \mprj_io_one[8] , \mprj_io_one[7] , \mprj_io_one[6] , \mprj_io_one[5] , \mprj_io_one[4] , \mprj_io_one[3] , \mprj_io_one[2] , \mprj_io_one[1] , \mprj_io_one[0] }),
+ .mprj_io_out({ \mprj_io_out[37] , \mprj_io_out[36] , \mprj_io_out[35] , \mprj_io_out[34] , \mprj_io_out[33] , \mprj_io_out[32] , \mprj_io_out[31] , \mprj_io_out[30] , \mprj_io_out[29] , \mprj_io_out[28] , \mprj_io_out[27] , \mprj_io_out[26] , \mprj_io_out[25] , \mprj_io_out[24] , \mprj_io_out[23] , \mprj_io_out[22] , \mprj_io_out[21] , \mprj_io_out[20] , \mprj_io_out[19] , \mprj_io_out[18] , \mprj_io_out[17] , \mprj_io_out[16] , \mprj_io_out[15] , \mprj_io_out[14] , \mprj_io_out[13] , \mprj_io_out[12] , \mprj_io_out[11] , \mprj_io_out[10] , \mprj_io_out[9] , \mprj_io_out[8] , \mprj_io_out[7] , \mprj_io_out[6] , \mprj_io_out[5] , \mprj_io_out[4] , \mprj_io_out[3] , \mprj_io_out[2] , \mprj_io_out[1] , \mprj_io_out[0] }),
+ .mprj_io_slow_sel({ \mprj_io_slow_sel[37] , \mprj_io_slow_sel[36] , \mprj_io_slow_sel[35] , \mprj_io_slow_sel[34] , \mprj_io_slow_sel[33] , \mprj_io_slow_sel[32] , \mprj_io_slow_sel[31] , \mprj_io_slow_sel[30] , \mprj_io_slow_sel[29] , \mprj_io_slow_sel[28] , \mprj_io_slow_sel[27] , \mprj_io_slow_sel[26] , \mprj_io_slow_sel[25] , \mprj_io_slow_sel[24] , \mprj_io_slow_sel[23] , \mprj_io_slow_sel[22] , \mprj_io_slow_sel[21] , \mprj_io_slow_sel[20] , \mprj_io_slow_sel[19] , \mprj_io_slow_sel[18] , \mprj_io_slow_sel[17] , \mprj_io_slow_sel[16] , \mprj_io_slow_sel[15] , \mprj_io_slow_sel[14] , \mprj_io_slow_sel[13] , \mprj_io_slow_sel[12] , \mprj_io_slow_sel[11] , \mprj_io_slow_sel[10] , \mprj_io_slow_sel[9] , \mprj_io_slow_sel[8] , \mprj_io_slow_sel[7] , \mprj_io_slow_sel[6] , \mprj_io_slow_sel[5] , \mprj_io_slow_sel[4] , \mprj_io_slow_sel[3] , \mprj_io_slow_sel[2] , \mprj_io_slow_sel[1] , \mprj_io_slow_sel[0] }),
+ .mprj_io_vtrip_sel({ \mprj_io_vtrip_sel[37] , \mprj_io_vtrip_sel[36] , \mprj_io_vtrip_sel[35] , \mprj_io_vtrip_sel[34] , \mprj_io_vtrip_sel[33] , \mprj_io_vtrip_sel[32] , \mprj_io_vtrip_sel[31] , \mprj_io_vtrip_sel[30] , \mprj_io_vtrip_sel[29] , \mprj_io_vtrip_sel[28] , \mprj_io_vtrip_sel[27] , \mprj_io_vtrip_sel[26] , \mprj_io_vtrip_sel[25] , \mprj_io_vtrip_sel[24] , \mprj_io_vtrip_sel[23] , \mprj_io_vtrip_sel[22] , \mprj_io_vtrip_sel[21] , \mprj_io_vtrip_sel[20] , \mprj_io_vtrip_sel[19] , \mprj_io_vtrip_sel[18] , \mprj_io_vtrip_sel[17] , \mprj_io_vtrip_sel[16] , \mprj_io_vtrip_sel[15] , \mprj_io_vtrip_sel[14] , \mprj_io_vtrip_sel[13] , \mprj_io_vtrip_sel[12] , \mprj_io_vtrip_sel[11] , \mprj_io_vtrip_sel[10] , \mprj_io_vtrip_sel[9] , \mprj_io_vtrip_sel[8] , \mprj_io_vtrip_sel[7] , \mprj_io_vtrip_sel[6] , \mprj_io_vtrip_sel[5] , \mprj_io_vtrip_sel[4] , \mprj_io_vtrip_sel[3] , \mprj_io_vtrip_sel[2] , \mprj_io_vtrip_sel[1] , \mprj_io_vtrip_sel[0] }),
+ .por(por_l_buf),
+ .porb_h(porb_h),
+ .resetb(resetb),
+ .resetb_core_h(rstb_h),
+ .vccd(vccd_core),
+ .vccd1(vccd1_core),
+ .vccd1_pad(vccd1),
+ .vccd2(vccd2_core),
+ .vccd2_pad(vccd2),
+ .vccd_pad(vccd),
+ .vdda(vdda_core),
+ .vdda1(vdda1_core),
+ .vdda1_pad(vdda1),
+ .vdda1_pad2(vdda1_2),
+ .vdda2(vdda2_core),
+ .vdda2_pad(vdda2),
+ .vdda_pad(vdda),
+ .vddio(vddio_core),
+ .vddio_pad(vddio),
+ .vddio_pad2(vddio_2),
+ .vssa(vssa_core),
+ .vssa1(vssa1_core),
+ .vssa1_pad(vssa1),
+ .vssa1_pad2(vssa1_2),
+ .vssa2(vssa2_core),
+ .vssa2_pad(vssa2),
+ .vssa_pad(vssa),
+ .vssd(vssd_core),
+ .vssd1(vssd1_core),
+ .vssd1_pad(vssd1),
+ .vssd2(vssd2_core),
+ .vssd2_pad(vssd2),
+ .vssd_pad(vssd),
+ .vssio(vssio_core),
+ .vssio_pad(vssio),
+ .vssio_pad2(vssio_2)
+ );
+ digital_pll pll (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .clockp({ pll_clk, pll_clk90 }),
+ .dco(spi_pll_dco_ena),
+ .div({ \spi_pll_div[4] , \spi_pll_div[3] , \spi_pll_div[2] , \spi_pll_div[1] , \spi_pll_div[0] }),
+ .enable(spi_pll_ena),
+ .ext_trim({ \spi_pll_trim[25] , \spi_pll_trim[24] , \spi_pll_trim[23] , \spi_pll_trim[22] , \spi_pll_trim[21] , \spi_pll_trim[20] , \spi_pll_trim[19] , \spi_pll_trim[18] , \spi_pll_trim[17] , \spi_pll_trim[16] , \spi_pll_trim[15] , \spi_pll_trim[14] , \spi_pll_trim[13] , \spi_pll_trim[12] , \spi_pll_trim[11] , \spi_pll_trim[10] , \spi_pll_trim[9] , \spi_pll_trim[8] , \spi_pll_trim[7] , \spi_pll_trim[6] , \spi_pll_trim[5] , \spi_pll_trim[4] , \spi_pll_trim[3] , \spi_pll_trim[2] , \spi_pll_trim[1] , \spi_pll_trim[0] }),
+ .osc(clock_core_buf),
+ .resetb(rstb_l_buf)
+ );
+ simple_por por (
+ .por_l(por_l),
+ .porb_h(porb_h),
+ .porb_l(porb_l),
+ .vdd1v8(vccd_core),
+ .vdd3v3(vddio_core),
+ .vss1v8(vssd_core),
+ .vss3v3(vssio_core)
+ );
+ xres_buf rstb_level (
+ .A(rstb_h),
+ .LVGND(vssd_core),
+ .LVPWR(vccd_core),
+ .VGND(vssio_core),
+ .VPWR(vddio_core),
+ .X(rstb_l)
+ );
+ gpio_signal_buffering sigbuf (
+ .mgmt_io_in_buf({ \mgmt_io_in_hk[37] , \mgmt_io_in_hk[36] , \mgmt_io_in_hk[35] , \mgmt_io_in_hk[34] , \mgmt_io_in_hk[33] , \mgmt_io_in_hk[32] , \mgmt_io_in_hk[31] , \mgmt_io_in_hk[30] , \mgmt_io_in_hk[29] , \mgmt_io_in_hk[28] , \mgmt_io_in_hk[27] , \mgmt_io_in_hk[26] , \mgmt_io_in_hk[25] , \mgmt_io_in_hk[24] , \mgmt_io_in_hk[23] , \mgmt_io_in_hk[22] , \mgmt_io_in_hk[21] , \mgmt_io_in_hk[20] , \mgmt_io_in_hk[19] , \mgmt_io_in_hk[18] , \mgmt_io_in_hk[17] , \mgmt_io_in_hk[16] , \mgmt_io_in_hk[15] , \mgmt_io_in_hk[14] , \mgmt_io_in_hk[13] , \mgmt_io_in_hk[12] , \mgmt_io_in_hk[11] , \mgmt_io_in_hk[10] , \mgmt_io_in_hk[9] , \mgmt_io_in_hk[8] , \mgmt_io_in_hk[7] }),
+ .mgmt_io_in_unbuf({ \mgmt_io_in[37] , \mgmt_io_in[36] , \mgmt_io_in[35] , \mgmt_io_in[34] , \mgmt_io_in[33] , \mgmt_io_in[32] , \mgmt_io_in[31] , \mgmt_io_in[30] , \mgmt_io_in[29] , \mgmt_io_in[28] , \mgmt_io_in[27] , \mgmt_io_in[26] , \mgmt_io_in[25] , \mgmt_io_in[24] , \mgmt_io_in[23] , \mgmt_io_in[22] , \mgmt_io_in[21] , \mgmt_io_in[20] , \mgmt_io_in[19] , \mgmt_io_in[18] , \mgmt_io_in[17] , \mgmt_io_in[16] , \mgmt_io_in[15] , \mgmt_io_in[14] , \mgmt_io_in[13] , \mgmt_io_in[12] , \mgmt_io_in[11] , \mgmt_io_in[10] , \mgmt_io_in[9] , \mgmt_io_in[8] , \mgmt_io_in[7] }),
+ .mgmt_io_oeb_buf({ \mgmt_io_oeb[37] , \mgmt_io_oeb[36] , \mgmt_io_oeb[35] }),
+ .mgmt_io_oeb_unbuf({ \mgmt_io_oeb_hk[37] , \mgmt_io_oeb_hk[36] , \mgmt_io_oeb_hk[35] }),
+ .mgmt_io_out_buf({ \mgmt_io_out[37] , \mgmt_io_out[36] , \mgmt_io_out[35] , \mgmt_io_out[34] , \mgmt_io_out[33] , \mgmt_io_out[32] , \mgmt_io_out[31] , \mgmt_io_out[30] , \mgmt_io_out[29] , \mgmt_io_out[28] , \mgmt_io_out[27] , \mgmt_io_out[26] , \mgmt_io_out[25] , \mgmt_io_out[24] , \mgmt_io_out[23] , \mgmt_io_out[22] , \mgmt_io_out[21] , \mgmt_io_out[20] , \mgmt_io_out[19] , \mgmt_io_out[18] , \mgmt_io_out[17] , \mgmt_io_out[16] , \mgmt_io_out[15] , \mgmt_io_out[14] , \mgmt_io_out[13] , \mgmt_io_out[12] , \mgmt_io_out[11] , \mgmt_io_out[10] , \mgmt_io_out[9] , \mgmt_io_out[8] , \mgmt_io_out[7] }),
+ .mgmt_io_out_unbuf({ \mgmt_io_out_hk[37] , \mgmt_io_out_hk[36] , \mgmt_io_out_hk[35] , \mgmt_io_out_hk[34] , \mgmt_io_out_hk[33] , \mgmt_io_out_hk[32] , \mgmt_io_out_hk[31] , \mgmt_io_out_hk[30] , \mgmt_io_out_hk[29] , \mgmt_io_out_hk[28] , \mgmt_io_out_hk[27] , \mgmt_io_out_hk[26] , \mgmt_io_out_hk[25] , \mgmt_io_out_hk[24] , \mgmt_io_out_hk[23] , \mgmt_io_out_hk[22] , \mgmt_io_out_hk[21] , \mgmt_io_out_hk[20] , \mgmt_io_out_hk[19] , \mgmt_io_out_hk[18] , \mgmt_io_out_hk[17] , \mgmt_io_out_hk[16] , \mgmt_io_out_hk[15] , \mgmt_io_out_hk[14] , \mgmt_io_out_hk[13] , \mgmt_io_out_hk[12] , \mgmt_io_out_hk[11] , \mgmt_io_out_hk[10] , \mgmt_io_out_hk[9] , \mgmt_io_out_hk[8] , \mgmt_io_out_hk[7] }),
+ .vccd(vccd_core),
+ .vssd(vssd_core)
+ );
+ mgmt_core_wrapper soc (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .clk_in(caravel_clk_buf),
+ .clk_out(clk_passthru),
+ .core_clk(caravel_clk_buf),
+ .core_rstn(caravel_rstn_buf),
+ .debug_in(debug_in),
+ .debug_mode(debug_mode),
+ .debug_oeb(debug_oeb),
+ .debug_out(debug_out),
+ .flash_clk(flash_clk_core),
+ .flash_csb(flash_csb_core),
+ .flash_io0_di(flash_io0_di_core),
+ .flash_io0_do(flash_io0_do_core),
+ .flash_io0_oeb(flash_io0_oeb_core),
+ .flash_io1_di(flash_io1_di_core),
+ .flash_io1_do(flash_io1_do_core),
+ .flash_io1_oeb(flash_io1_oeb_core),
+ .flash_io2_di(flash_io2_di_core),
+ .flash_io2_do(flash_io2_do_core),
+ .flash_io2_oeb(flash_io2_oeb_core),
+ .flash_io3_di(flash_io3_di_core),
+ .flash_io3_do(flash_io3_do_core),
+ .flash_io3_oeb(flash_io3_oeb_core),
+ .gpio_in_pad(gpio_in_core),
+ .gpio_inenb_pad(gpio_inenb_core),
+ .gpio_mode0_pad(gpio_mode0_core),
+ .gpio_mode1_pad(gpio_mode1_core),
+ .gpio_out_pad(gpio_out_core),
+ .gpio_outenb_pad(gpio_outenb_core),
+ .hk_ack_i(hk_ack_i),
+ .hk_cyc_o(hk_cyc_o),
+ .hk_dat_i({ \hk_dat_i[31] , \hk_dat_i[30] , \hk_dat_i[29] , \hk_dat_i[28] , \hk_dat_i[27] , \hk_dat_i[26] , \hk_dat_i[25] , \hk_dat_i[24] , \hk_dat_i[23] , \hk_dat_i[22] , \hk_dat_i[21] , \hk_dat_i[20] , \hk_dat_i[19] , \hk_dat_i[18] , \hk_dat_i[17] , \hk_dat_i[16] , \hk_dat_i[15] , \hk_dat_i[14] , \hk_dat_i[13] , \hk_dat_i[12] , \hk_dat_i[11] , \hk_dat_i[10] , \hk_dat_i[9] , \hk_dat_i[8] , \hk_dat_i[7] , \hk_dat_i[6] , \hk_dat_i[5] , \hk_dat_i[4] , \hk_dat_i[3] , \hk_dat_i[2] , \hk_dat_i[1] , \hk_dat_i[0] }),
+ .hk_stb_o(hk_stb_o),
+ .irq({ \irq_spi[2] , \irq_spi[1] , \irq_spi[0] , \user_irq[2] , \user_irq[1] , \user_irq[0] }),
+ .la_iena({ \la_iena_mprj[127] , \la_iena_mprj[126] , \la_iena_mprj[125] , \la_iena_mprj[124] , \la_iena_mprj[123] , \la_iena_mprj[122] , \la_iena_mprj[121] , \la_iena_mprj[120] , \la_iena_mprj[119] , \la_iena_mprj[118] , \la_iena_mprj[117] , \la_iena_mprj[116] , \la_iena_mprj[115] , \la_iena_mprj[114] , \la_iena_mprj[113] , \la_iena_mprj[112] , \la_iena_mprj[111] , \la_iena_mprj[110] , \la_iena_mprj[109] , \la_iena_mprj[108] , \la_iena_mprj[107] , \la_iena_mprj[106] , \la_iena_mprj[105] , \la_iena_mprj[104] , \la_iena_mprj[103] , \la_iena_mprj[102] , \la_iena_mprj[101] , \la_iena_mprj[100] , \la_iena_mprj[99] , \la_iena_mprj[98] , \la_iena_mprj[97] , \la_iena_mprj[96] , \la_iena_mprj[95] , \la_iena_mprj[94] , \la_iena_mprj[93] , \la_iena_mprj[92] , \la_iena_mprj[91] , \la_iena_mprj[90] , \la_iena_mprj[89] , \la_iena_mprj[88] , \la_iena_mprj[87] , \la_iena_mprj[86] , \la_iena_mprj[85] , \la_iena_mprj[84] , \la_iena_mprj[83] , \la_iena_mprj[82] , \la_iena_mprj[81] , \la_iena_mprj[80] , \la_iena_mprj[79] , \la_iena_mprj[78] , \la_iena_mprj[77] , \la_iena_mprj[76] , \la_iena_mprj[75] , \la_iena_mprj[74] , \la_iena_mprj[73] , \la_iena_mprj[72] , \la_iena_mprj[71] , \la_iena_mprj[70] , \la_iena_mprj[69] , \la_iena_mprj[68] , \la_iena_mprj[67] , \la_iena_mprj[66] , \la_iena_mprj[65] , \la_iena_mprj[64] , \la_iena_mprj[63] , \la_iena_mprj[62] , \la_iena_mprj[61] , \la_iena_mprj[60] , \la_iena_mprj[59] , \la_iena_mprj[58] , \la_iena_mprj[57] , \la_iena_mprj[56] , \la_iena_mprj[55] , \la_iena_mprj[54] , \la_iena_mprj[53] , \la_iena_mprj[52] , \la_iena_mprj[51] , \la_iena_mprj[50] , \la_iena_mprj[49] , \la_iena_mprj[48] , \la_iena_mprj[47] , \la_iena_mprj[46] , \la_iena_mprj[45] , \la_iena_mprj[44] , \la_iena_mprj[43] , \la_iena_mprj[42] , \la_iena_mprj[41] , \la_iena_mprj[40] , \la_iena_mprj[39] , \la_iena_mprj[38] , \la_iena_mprj[37] , \la_iena_mprj[36] , \la_iena_mprj[35] , \la_iena_mprj[34] , \la_iena_mprj[33] , \la_iena_mprj[32] , \la_iena_mprj[31] , \la_iena_mprj[30] , \la_iena_mprj[29] , \la_iena_mprj[28] , \la_iena_mprj[27] , \la_iena_mprj[26] , \la_iena_mprj[25] , \la_iena_mprj[24] , \la_iena_mprj[23] , \la_iena_mprj[22] , \la_iena_mprj[21] , \la_iena_mprj[20] , \la_iena_mprj[19] , \la_iena_mprj[18] , \la_iena_mprj[17] , \la_iena_mprj[16] , \la_iena_mprj[15] , \la_iena_mprj[14] , \la_iena_mprj[13] , \la_iena_mprj[12] , \la_iena_mprj[11] , \la_iena_mprj[10] , \la_iena_mprj[9] , \la_iena_mprj[8] , \la_iena_mprj[7] , \la_iena_mprj[6] , \la_iena_mprj[5] , \la_iena_mprj[4] , \la_iena_mprj[3] , \la_iena_mprj[2] , \la_iena_mprj[1] , \la_iena_mprj[0] }),
+ .la_input({ \la_data_in_mprj[127] , \la_data_in_mprj[126] , \la_data_in_mprj[125] , \la_data_in_mprj[124] , \la_data_in_mprj[123] , \la_data_in_mprj[122] , \la_data_in_mprj[121] , \la_data_in_mprj[120] , \la_data_in_mprj[119] , \la_data_in_mprj[118] , \la_data_in_mprj[117] , \la_data_in_mprj[116] , \la_data_in_mprj[115] , \la_data_in_mprj[114] , \la_data_in_mprj[113] , \la_data_in_mprj[112] , \la_data_in_mprj[111] , \la_data_in_mprj[110] , \la_data_in_mprj[109] , \la_data_in_mprj[108] , \la_data_in_mprj[107] , \la_data_in_mprj[106] , \la_data_in_mprj[105] , \la_data_in_mprj[104] , \la_data_in_mprj[103] , \la_data_in_mprj[102] , \la_data_in_mprj[101] , \la_data_in_mprj[100] , \la_data_in_mprj[99] , \la_data_in_mprj[98] , \la_data_in_mprj[97] , \la_data_in_mprj[96] , \la_data_in_mprj[95] , \la_data_in_mprj[94] , \la_data_in_mprj[93] , \la_data_in_mprj[92] , \la_data_in_mprj[91] , \la_data_in_mprj[90] , \la_data_in_mprj[89] , \la_data_in_mprj[88] , \la_data_in_mprj[87] , \la_data_in_mprj[86] , \la_data_in_mprj[85] , \la_data_in_mprj[84] , \la_data_in_mprj[83] , \la_data_in_mprj[82] , \la_data_in_mprj[81] , \la_data_in_mprj[80] , \la_data_in_mprj[79] , \la_data_in_mprj[78] , \la_data_in_mprj[77] , \la_data_in_mprj[76] , \la_data_in_mprj[75] , \la_data_in_mprj[74] , \la_data_in_mprj[73] , \la_data_in_mprj[72] , \la_data_in_mprj[71] , \la_data_in_mprj[70] , \la_data_in_mprj[69] , \la_data_in_mprj[68] , \la_data_in_mprj[67] , \la_data_in_mprj[66] , \la_data_in_mprj[65] , \la_data_in_mprj[64] , \la_data_in_mprj[63] , \la_data_in_mprj[62] , \la_data_in_mprj[61] , \la_data_in_mprj[60] , \la_data_in_mprj[59] , \la_data_in_mprj[58] , \la_data_in_mprj[57] , \la_data_in_mprj[56] , \la_data_in_mprj[55] , \la_data_in_mprj[54] , \la_data_in_mprj[53] , \la_data_in_mprj[52] , \la_data_in_mprj[51] , \la_data_in_mprj[50] , \la_data_in_mprj[49] , \la_data_in_mprj[48] , \la_data_in_mprj[47] , \la_data_in_mprj[46] , \la_data_in_mprj[45] , \la_data_in_mprj[44] , \la_data_in_mprj[43] , \la_data_in_mprj[42] , \la_data_in_mprj[41] , \la_data_in_mprj[40] , \la_data_in_mprj[39] , \la_data_in_mprj[38] , \la_data_in_mprj[37] , \la_data_in_mprj[36] , \la_data_in_mprj[35] , \la_data_in_mprj[34] , \la_data_in_mprj[33] , \la_data_in_mprj[32] , \la_data_in_mprj[31] , \la_data_in_mprj[30] , \la_data_in_mprj[29] , \la_data_in_mprj[28] , \la_data_in_mprj[27] , \la_data_in_mprj[26] , \la_data_in_mprj[25] , \la_data_in_mprj[24] , \la_data_in_mprj[23] , \la_data_in_mprj[22] , \la_data_in_mprj[21] , \la_data_in_mprj[20] , \la_data_in_mprj[19] , \la_data_in_mprj[18] , \la_data_in_mprj[17] , \la_data_in_mprj[16] , \la_data_in_mprj[15] , \la_data_in_mprj[14] , \la_data_in_mprj[13] , \la_data_in_mprj[12] , \la_data_in_mprj[11] , \la_data_in_mprj[10] , \la_data_in_mprj[9] , \la_data_in_mprj[8] , \la_data_in_mprj[7] , \la_data_in_mprj[6] , \la_data_in_mprj[5] , \la_data_in_mprj[4] , \la_data_in_mprj[3] , \la_data_in_mprj[2] , \la_data_in_mprj[1] , \la_data_in_mprj[0] }),
+ .la_oenb({ \la_oenb_mprj[127] , \la_oenb_mprj[126] , \la_oenb_mprj[125] , \la_oenb_mprj[124] , \la_oenb_mprj[123] , \la_oenb_mprj[122] , \la_oenb_mprj[121] , \la_oenb_mprj[120] , \la_oenb_mprj[119] , \la_oenb_mprj[118] , \la_oenb_mprj[117] , \la_oenb_mprj[116] , \la_oenb_mprj[115] , \la_oenb_mprj[114] , \la_oenb_mprj[113] , \la_oenb_mprj[112] , \la_oenb_mprj[111] , \la_oenb_mprj[110] , \la_oenb_mprj[109] , \la_oenb_mprj[108] , \la_oenb_mprj[107] , \la_oenb_mprj[106] , \la_oenb_mprj[105] , \la_oenb_mprj[104] , \la_oenb_mprj[103] , \la_oenb_mprj[102] , \la_oenb_mprj[101] , \la_oenb_mprj[100] , \la_oenb_mprj[99] , \la_oenb_mprj[98] , \la_oenb_mprj[97] , \la_oenb_mprj[96] , \la_oenb_mprj[95] , \la_oenb_mprj[94] , \la_oenb_mprj[93] , \la_oenb_mprj[92] , \la_oenb_mprj[91] , \la_oenb_mprj[90] , \la_oenb_mprj[89] , \la_oenb_mprj[88] , \la_oenb_mprj[87] , \la_oenb_mprj[86] , \la_oenb_mprj[85] , \la_oenb_mprj[84] , \la_oenb_mprj[83] , \la_oenb_mprj[82] , \la_oenb_mprj[81] , \la_oenb_mprj[80] , \la_oenb_mprj[79] , \la_oenb_mprj[78] , \la_oenb_mprj[77] , \la_oenb_mprj[76] , \la_oenb_mprj[75] , \la_oenb_mprj[74] , \la_oenb_mprj[73] , \la_oenb_mprj[72] , \la_oenb_mprj[71] , \la_oenb_mprj[70] , \la_oenb_mprj[69] , \la_oenb_mprj[68] , \la_oenb_mprj[67] , \la_oenb_mprj[66] , \la_oenb_mprj[65] , \la_oenb_mprj[64] , \la_oenb_mprj[63] , \la_oenb_mprj[62] , \la_oenb_mprj[61] , \la_oenb_mprj[60] , \la_oenb_mprj[59] , \la_oenb_mprj[58] , \la_oenb_mprj[57] , \la_oenb_mprj[56] , \la_oenb_mprj[55] , \la_oenb_mprj[54] , \la_oenb_mprj[53] , \la_oenb_mprj[52] , \la_oenb_mprj[51] , \la_oenb_mprj[50] , \la_oenb_mprj[49] , \la_oenb_mprj[48] , \la_oenb_mprj[47] , \la_oenb_mprj[46] , \la_oenb_mprj[45] , \la_oenb_mprj[44] , \la_oenb_mprj[43] , \la_oenb_mprj[42] , \la_oenb_mprj[41] , \la_oenb_mprj[40] , \la_oenb_mprj[39] , \la_oenb_mprj[38] , \la_oenb_mprj[37] , \la_oenb_mprj[36] , \la_oenb_mprj[35] , \la_oenb_mprj[34] , \la_oenb_mprj[33] , \la_oenb_mprj[32] , \la_oenb_mprj[31] , \la_oenb_mprj[30] , \la_oenb_mprj[29] , \la_oenb_mprj[28] , \la_oenb_mprj[27] , \la_oenb_mprj[26] , \la_oenb_mprj[25] , \la_oenb_mprj[24] , \la_oenb_mprj[23] , \la_oenb_mprj[22] , \la_oenb_mprj[21] , \la_oenb_mprj[20] , \la_oenb_mprj[19] , \la_oenb_mprj[18] , \la_oenb_mprj[17] , \la_oenb_mprj[16] , \la_oenb_mprj[15] , \la_oenb_mprj[14] , \la_oenb_mprj[13] , \la_oenb_mprj[12] , \la_oenb_mprj[11] , \la_oenb_mprj[10] , \la_oenb_mprj[9] , \la_oenb_mprj[8] , \la_oenb_mprj[7] , \la_oenb_mprj[6] , \la_oenb_mprj[5] , \la_oenb_mprj[4] , \la_oenb_mprj[3] , \la_oenb_mprj[2] , \la_oenb_mprj[1] , \la_oenb_mprj[0] }),
+ .la_output({ \la_data_out_mprj[127] , \la_data_out_mprj[126] , \la_data_out_mprj[125] , \la_data_out_mprj[124] , \la_data_out_mprj[123] , \la_data_out_mprj[122] , \la_data_out_mprj[121] , \la_data_out_mprj[120] , \la_data_out_mprj[119] , \la_data_out_mprj[118] , \la_data_out_mprj[117] , \la_data_out_mprj[116] , \la_data_out_mprj[115] , \la_data_out_mprj[114] , \la_data_out_mprj[113] , \la_data_out_mprj[112] , \la_data_out_mprj[111] , \la_data_out_mprj[110] , \la_data_out_mprj[109] , \la_data_out_mprj[108] , \la_data_out_mprj[107] , \la_data_out_mprj[106] , \la_data_out_mprj[105] , \la_data_out_mprj[104] , \la_data_out_mprj[103] , \la_data_out_mprj[102] , \la_data_out_mprj[101] , \la_data_out_mprj[100] , \la_data_out_mprj[99] , \la_data_out_mprj[98] , \la_data_out_mprj[97] , \la_data_out_mprj[96] , \la_data_out_mprj[95] , \la_data_out_mprj[94] , \la_data_out_mprj[93] , \la_data_out_mprj[92] , \la_data_out_mprj[91] , \la_data_out_mprj[90] , \la_data_out_mprj[89] , \la_data_out_mprj[88] , \la_data_out_mprj[87] , \la_data_out_mprj[86] , \la_data_out_mprj[85] , \la_data_out_mprj[84] , \la_data_out_mprj[83] , \la_data_out_mprj[82] , \la_data_out_mprj[81] , \la_data_out_mprj[80] , \la_data_out_mprj[79] , \la_data_out_mprj[78] , \la_data_out_mprj[77] , \la_data_out_mprj[76] , \la_data_out_mprj[75] , \la_data_out_mprj[74] , \la_data_out_mprj[73] , \la_data_out_mprj[72] , \la_data_out_mprj[71] , \la_data_out_mprj[70] , \la_data_out_mprj[69] , \la_data_out_mprj[68] , \la_data_out_mprj[67] , \la_data_out_mprj[66] , \la_data_out_mprj[65] , \la_data_out_mprj[64] , \la_data_out_mprj[63] , \la_data_out_mprj[62] , \la_data_out_mprj[61] , \la_data_out_mprj[60] , \la_data_out_mprj[59] , \la_data_out_mprj[58] , \la_data_out_mprj[57] , \la_data_out_mprj[56] , \la_data_out_mprj[55] , \la_data_out_mprj[54] , \la_data_out_mprj[53] , \la_data_out_mprj[52] , \la_data_out_mprj[51] , \la_data_out_mprj[50] , \la_data_out_mprj[49] , \la_data_out_mprj[48] , \la_data_out_mprj[47] , \la_data_out_mprj[46] , \la_data_out_mprj[45] , \la_data_out_mprj[44] , \la_data_out_mprj[43] , \la_data_out_mprj[42] , \la_data_out_mprj[41] , \la_data_out_mprj[40] , \la_data_out_mprj[39] , \la_data_out_mprj[38] , \la_data_out_mprj[37] , \la_data_out_mprj[36] , \la_data_out_mprj[35] , \la_data_out_mprj[34] , \la_data_out_mprj[33] , \la_data_out_mprj[32] , \la_data_out_mprj[31] , \la_data_out_mprj[30] , \la_data_out_mprj[29] , \la_data_out_mprj[28] , \la_data_out_mprj[27] , \la_data_out_mprj[26] , \la_data_out_mprj[25] , \la_data_out_mprj[24] , \la_data_out_mprj[23] , \la_data_out_mprj[22] , \la_data_out_mprj[21] , \la_data_out_mprj[20] , \la_data_out_mprj[19] , \la_data_out_mprj[18] , \la_data_out_mprj[17] , \la_data_out_mprj[16] , \la_data_out_mprj[15] , \la_data_out_mprj[14] , \la_data_out_mprj[13] , \la_data_out_mprj[12] , \la_data_out_mprj[11] , \la_data_out_mprj[10] , \la_data_out_mprj[9] , \la_data_out_mprj[8] , \la_data_out_mprj[7] , \la_data_out_mprj[6] , \la_data_out_mprj[5] , \la_data_out_mprj[4] , \la_data_out_mprj[3] , \la_data_out_mprj[2] , \la_data_out_mprj[1] , \la_data_out_mprj[0] }),
+ .mprj_ack_i(mprj_ack_i_core),
+ .mprj_adr_o({ \mprj_adr_o_core[31] , \mprj_adr_o_core[30] , \mprj_adr_o_core[29] , \mprj_adr_o_core[28] , \mprj_adr_o_core[27] , \mprj_adr_o_core[26] , \mprj_adr_o_core[25] , \mprj_adr_o_core[24] , \mprj_adr_o_core[23] , \mprj_adr_o_core[22] , \mprj_adr_o_core[21] , \mprj_adr_o_core[20] , \mprj_adr_o_core[19] , \mprj_adr_o_core[18] , \mprj_adr_o_core[17] , \mprj_adr_o_core[16] , \mprj_adr_o_core[15] , \mprj_adr_o_core[14] , \mprj_adr_o_core[13] , \mprj_adr_o_core[12] , \mprj_adr_o_core[11] , \mprj_adr_o_core[10] , \mprj_adr_o_core[9] , \mprj_adr_o_core[8] , \mprj_adr_o_core[7] , \mprj_adr_o_core[6] , \mprj_adr_o_core[5] , \mprj_adr_o_core[4] , \mprj_adr_o_core[3] , \mprj_adr_o_core[2] , \mprj_adr_o_core[1] , \mprj_adr_o_core[0] }),
+ .mprj_cyc_o(mprj_cyc_o_core),
+ .mprj_dat_i({ \mprj_dat_i_core[31] , \mprj_dat_i_core[30] , \mprj_dat_i_core[29] , \mprj_dat_i_core[28] , \mprj_dat_i_core[27] , \mprj_dat_i_core[26] , \mprj_dat_i_core[25] , \mprj_dat_i_core[24] , \mprj_dat_i_core[23] , \mprj_dat_i_core[22] , \mprj_dat_i_core[21] , \mprj_dat_i_core[20] , \mprj_dat_i_core[19] , \mprj_dat_i_core[18] , \mprj_dat_i_core[17] , \mprj_dat_i_core[16] , \mprj_dat_i_core[15] , \mprj_dat_i_core[14] , \mprj_dat_i_core[13] , \mprj_dat_i_core[12] , \mprj_dat_i_core[11] , \mprj_dat_i_core[10] , \mprj_dat_i_core[9] , \mprj_dat_i_core[8] , \mprj_dat_i_core[7] , \mprj_dat_i_core[6] , \mprj_dat_i_core[5] , \mprj_dat_i_core[4] , \mprj_dat_i_core[3] , \mprj_dat_i_core[2] , \mprj_dat_i_core[1] , \mprj_dat_i_core[0] }),
+ .mprj_dat_o({ \mprj_dat_o_core[31] , \mprj_dat_o_core[30] , \mprj_dat_o_core[29] , \mprj_dat_o_core[28] , \mprj_dat_o_core[27] , \mprj_dat_o_core[26] , \mprj_dat_o_core[25] , \mprj_dat_o_core[24] , \mprj_dat_o_core[23] , \mprj_dat_o_core[22] , \mprj_dat_o_core[21] , \mprj_dat_o_core[20] , \mprj_dat_o_core[19] , \mprj_dat_o_core[18] , \mprj_dat_o_core[17] , \mprj_dat_o_core[16] , \mprj_dat_o_core[15] , \mprj_dat_o_core[14] , \mprj_dat_o_core[13] , \mprj_dat_o_core[12] , \mprj_dat_o_core[11] , \mprj_dat_o_core[10] , \mprj_dat_o_core[9] , \mprj_dat_o_core[8] , \mprj_dat_o_core[7] , \mprj_dat_o_core[6] , \mprj_dat_o_core[5] , \mprj_dat_o_core[4] , \mprj_dat_o_core[3] , \mprj_dat_o_core[2] , \mprj_dat_o_core[1] , \mprj_dat_o_core[0] }),
+ .mprj_sel_o({ \mprj_sel_o_core[3] , \mprj_sel_o_core[2] , \mprj_sel_o_core[1] , \mprj_sel_o_core[0] }),
+ .mprj_stb_o(mprj_stb_o_core),
+ .mprj_wb_iena(mprj_iena_wb),
+ .mprj_we_o(mprj_we_o_core),
+ .por_l_in(por_l),
+ .por_l_out(por_l_buf),
+ .porb_h_in(por_l),
+ .porb_h_out(porb_h_out_nc),
+ .qspi_enabled(qspi_enabled),
+ .resetn_in(caravel_rstn_buf),
+ .resetn_out(resetn_passthru),
+ .rstb_l_in(rstb_l),
+ .rstb_l_out(rstb_l_buf),
+ .ser_rx(ser_rx),
+ .ser_tx(ser_tx),
+ .serial_clock_in(\gpio_clock_1_shifted[0] ),
+ .serial_clock_out(\gpio_clock_2_shifted[18] ),
+ .serial_data_2_in(mprj_io_loader_data_2),
+ .serial_data_2_out(\gpio_serial_link_2_shifted[18] ),
+ .serial_load_in(\gpio_load_1_shifted[0] ),
+ .serial_load_out(\gpio_load_2_shifted[18] ),
+ .serial_resetn_in(\gpio_resetn_1_shifted[0] ),
+ .serial_resetn_out(\gpio_resetn_2_shifted[18] ),
+ .spi_csb(spi_csb),
+ .spi_enabled(spi_enabled),
+ .spi_sck(spi_sck),
+ .spi_sdi(spi_sdi),
+ .spi_sdo(spi_sdo),
+ .spi_sdoenb(spi_sdoenb),
+ .trap(trap),
+ .uart_enabled(uart_enabled),
+ .user_irq_ena({ \user_irq_ena[2] , \user_irq_ena[1] , \user_irq_ena[0] })
+ );
+ spare_logic_block \spare_logic[0] (
+ .spare_xfq({ \spare_xfq_nc[1] , \spare_xfq_nc[0] }),
+ .spare_xfqn({ \spare_xfqn_nc[1] , \spare_xfqn_nc[0] }),
+ .spare_xi({ \spare_xi_nc[3] , \spare_xi_nc[2] , \spare_xi_nc[1] , \spare_xi_nc[0] }),
+ .spare_xib(\spare_xib_nc[0] ),
+ .spare_xmx({ \spare_xmx_nc[1] , \spare_xmx_nc[0] }),
+ .spare_xna({ \spare_xna_nc[1] , \spare_xna_nc[0] }),
+ .spare_xno({ \spare_xno_nc[1] , \spare_xno_nc[0] }),
+ .spare_xz({ \spare_xz_nc[26] , \spare_xz_nc[25] , \spare_xz_nc[24] , \spare_xz_nc[23] , \spare_xz_nc[22] , \spare_xz_nc[21] , \spare_xz_nc[20] , \spare_xz_nc[19] , \spare_xz_nc[18] , \spare_xz_nc[17] , \spare_xz_nc[16] , \spare_xz_nc[15] , \spare_xz_nc[14] , \spare_xz_nc[13] , \spare_xz_nc[12] , \spare_xz_nc[11] , \spare_xz_nc[10] , \spare_xz_nc[9] , \spare_xz_nc[8] , \spare_xz_nc[7] , \spare_xz_nc[6] , \spare_xz_nc[5] , \spare_xz_nc[4] , \spare_xz_nc[3] , \spare_xz_nc[2] , \spare_xz_nc[1] , \spare_xz_nc[0] }),
+ .vccd(vccd_core),
+ .vssd(vssd_core)
+ );
+ spare_logic_block \spare_logic[1] (
+ .spare_xfq({ \spare_xfq_nc[3] , \spare_xfq_nc[2] }),
+ .spare_xfqn({ \spare_xfqn_nc[3] , \spare_xfqn_nc[2] }),
+ .spare_xi({ \spare_xi_nc[7] , \spare_xi_nc[6] , \spare_xi_nc[5] , \spare_xi_nc[4] }),
+ .spare_xib(\spare_xib_nc[1] ),
+ .spare_xmx({ \spare_xmx_nc[3] , \spare_xmx_nc[2] }),
+ .spare_xna({ \spare_xna_nc[3] , \spare_xna_nc[2] }),
+ .spare_xno({ \spare_xno_nc[3] , \spare_xno_nc[2] }),
+ .spare_xz({ \spare_xz_nc[53] , \spare_xz_nc[52] , \spare_xz_nc[51] , \spare_xz_nc[50] , \spare_xz_nc[49] , \spare_xz_nc[48] , \spare_xz_nc[47] , \spare_xz_nc[46] , \spare_xz_nc[45] , \spare_xz_nc[44] , \spare_xz_nc[43] , \spare_xz_nc[42] , \spare_xz_nc[41] , \spare_xz_nc[40] , \spare_xz_nc[39] , \spare_xz_nc[38] , \spare_xz_nc[37] , \spare_xz_nc[36] , \spare_xz_nc[35] , \spare_xz_nc[34] , \spare_xz_nc[33] , \spare_xz_nc[32] , \spare_xz_nc[31] , \spare_xz_nc[30] , \spare_xz_nc[29] , \spare_xz_nc[28] , \spare_xz_nc[27] }),
+ .vccd(vccd_core),
+ .vssd(vssd_core)
+ );
+ spare_logic_block \spare_logic[2] (
+ .spare_xfq({ \spare_xfq_nc[5] , \spare_xfq_nc[4] }),
+ .spare_xfqn({ \spare_xfqn_nc[5] , \spare_xfqn_nc[4] }),
+ .spare_xi({ \spare_xi_nc[11] , \spare_xi_nc[10] , \spare_xi_nc[9] , \spare_xi_nc[8] }),
+ .spare_xib(\spare_xib_nc[2] ),
+ .spare_xmx({ \spare_xmx_nc[5] , \spare_xmx_nc[4] }),
+ .spare_xna({ \spare_xna_nc[5] , \spare_xna_nc[4] }),
+ .spare_xno({ \spare_xno_nc[5] , \spare_xno_nc[4] }),
+ .spare_xz({ \spare_xz_nc[80] , \spare_xz_nc[79] , \spare_xz_nc[78] , \spare_xz_nc[77] , \spare_xz_nc[76] , \spare_xz_nc[75] , \spare_xz_nc[74] , \spare_xz_nc[73] , \spare_xz_nc[72] , \spare_xz_nc[71] , \spare_xz_nc[70] , \spare_xz_nc[69] , \spare_xz_nc[68] , \spare_xz_nc[67] , \spare_xz_nc[66] , \spare_xz_nc[65] , \spare_xz_nc[64] , \spare_xz_nc[63] , \spare_xz_nc[62] , \spare_xz_nc[61] , \spare_xz_nc[60] , \spare_xz_nc[59] , \spare_xz_nc[58] , \spare_xz_nc[57] , \spare_xz_nc[56] , \spare_xz_nc[55] , \spare_xz_nc[54] }),
+ .vccd(vccd_core),
+ .vssd(vssd_core)
+ );
+ spare_logic_block \spare_logic[3] (
+ .spare_xfq({ \spare_xfq_nc[7] , \spare_xfq_nc[6] }),
+ .spare_xfqn({ \spare_xfqn_nc[7] , \spare_xfqn_nc[6] }),
+ .spare_xi({ \spare_xi_nc[15] , \spare_xi_nc[14] , \spare_xi_nc[13] , \spare_xi_nc[12] }),
+ .spare_xib(\spare_xib_nc[3] ),
+ .spare_xmx({ \spare_xmx_nc[7] , \spare_xmx_nc[6] }),
+ .spare_xna({ \spare_xna_nc[7] , \spare_xna_nc[6] }),
+ .spare_xno({ \spare_xno_nc[7] , \spare_xno_nc[6] }),
+ .spare_xz({ \spare_xz_nc[107] , \spare_xz_nc[106] , \spare_xz_nc[105] , \spare_xz_nc[104] , \spare_xz_nc[103] , \spare_xz_nc[102] , \spare_xz_nc[101] , \spare_xz_nc[100] , \spare_xz_nc[99] , \spare_xz_nc[98] , \spare_xz_nc[97] , \spare_xz_nc[96] , \spare_xz_nc[95] , \spare_xz_nc[94] , \spare_xz_nc[93] , \spare_xz_nc[92] , \spare_xz_nc[91] , \spare_xz_nc[90] , \spare_xz_nc[89] , \spare_xz_nc[88] , \spare_xz_nc[87] , \spare_xz_nc[86] , \spare_xz_nc[85] , \spare_xz_nc[84] , \spare_xz_nc[83] , \spare_xz_nc[82] , \spare_xz_nc[81] }),
+ .vccd(vccd_core),
+ .vssd(vssd_core)
+ );
+ user_id_programming user_id_value (
+ .VGND(vssd_core),
+ .VPWR(vccd_core),
+ .mask_rev({ \mask_rev[31] , \mask_rev[30] , \mask_rev[29] , \mask_rev[28] , \mask_rev[27] , \mask_rev[26] , \mask_rev[25] , \mask_rev[24] , \mask_rev[23] , \mask_rev[22] , \mask_rev[21] , \mask_rev[20] , \mask_rev[19] , \mask_rev[18] , \mask_rev[17] , \mask_rev[16] , \mask_rev[15] , \mask_rev[14] , \mask_rev[13] , \mask_rev[12] , \mask_rev[11] , \mask_rev[10] , \mask_rev[9] , \mask_rev[8] , \mask_rev[7] , \mask_rev[6] , \mask_rev[5] , \mask_rev[4] , \mask_rev[3] , \mask_rev[2] , \mask_rev[1] , \mask_rev[0] })
+ );
+ assign \gpio_serial_link_1_shifted[18] = \gpio_serial_link_1[17] ;
+ assign \gpio_serial_link_1_shifted[17] = \gpio_serial_link_1[16] ;
+ assign \gpio_serial_link_1_shifted[16] = \gpio_serial_link_1[15] ;
+ assign \gpio_serial_link_1_shifted[15] = \gpio_serial_link_1[14] ;
+ assign \gpio_serial_link_1_shifted[14] = \gpio_serial_link_1[13] ;
+ assign \gpio_serial_link_1_shifted[13] = \gpio_serial_link_1[12] ;
+ assign \gpio_serial_link_1_shifted[12] = \gpio_serial_link_1[11] ;
+ assign \gpio_serial_link_1_shifted[11] = \gpio_serial_link_1[10] ;
+ assign \gpio_serial_link_1_shifted[10] = \gpio_serial_link_1[9] ;
+ assign \gpio_serial_link_1_shifted[9] = \gpio_serial_link_1[8] ;
+ assign \gpio_serial_link_1_shifted[8] = \gpio_serial_link_1[7] ;
+ assign \gpio_serial_link_1_shifted[7] = \gpio_serial_link_1[6] ;
+ assign \gpio_serial_link_1_shifted[6] = \gpio_serial_link_1[5] ;
+ assign \gpio_serial_link_1_shifted[5] = \gpio_serial_link_1[4] ;
+ assign \gpio_serial_link_1_shifted[4] = \gpio_serial_link_1[3] ;
+ assign \gpio_serial_link_1_shifted[3] = \gpio_serial_link_1[2] ;
+ assign \gpio_serial_link_1_shifted[2] = \gpio_serial_link_1[1] ;
+ assign \gpio_serial_link_1_shifted[1] = \gpio_serial_link_1[0] ;
+ assign \gpio_load_2_shifted[17] = \gpio_load_2[18] ;
+ assign \gpio_load_2_shifted[16] = \gpio_load_2[17] ;
+ assign \gpio_load_2_shifted[15] = \gpio_load_2[16] ;
+ assign \gpio_load_2_shifted[14] = \gpio_load_2[15] ;
+ assign \gpio_load_2_shifted[13] = \gpio_load_2[14] ;
+ assign \gpio_load_2_shifted[12] = \gpio_load_2[13] ;
+ assign \gpio_load_2_shifted[11] = \gpio_load_2[12] ;
+ assign \gpio_load_2_shifted[10] = \gpio_load_2[11] ;
+ assign \gpio_load_2_shifted[9] = \gpio_load_2[10] ;
+ assign \gpio_load_2_shifted[8] = \gpio_load_2[9] ;
+ assign \gpio_load_2_shifted[7] = \gpio_load_2[8] ;
+ assign \gpio_load_2_shifted[6] = \gpio_load_2[7] ;
+ assign \gpio_load_2_shifted[5] = \gpio_load_2[6] ;
+ assign \gpio_load_2_shifted[4] = \gpio_load_2[5] ;
+ assign \gpio_load_2_shifted[3] = \gpio_load_2[4] ;
+ assign \gpio_load_2_shifted[2] = \gpio_load_2[3] ;
+ assign \gpio_load_2_shifted[1] = \gpio_load_2[2] ;
+ assign \gpio_load_2_shifted[0] = \gpio_load_2[1] ;
+ assign \gpio_clock_1_shifted[18] = \gpio_clock_1[17] ;
+ assign \gpio_clock_1_shifted[17] = \gpio_clock_1[16] ;
+ assign \gpio_clock_1_shifted[16] = \gpio_clock_1[15] ;
+ assign \gpio_clock_1_shifted[15] = \gpio_clock_1[14] ;
+ assign \gpio_clock_1_shifted[14] = \gpio_clock_1[13] ;
+ assign \gpio_clock_1_shifted[13] = \gpio_clock_1[12] ;
+ assign \gpio_clock_1_shifted[12] = \gpio_clock_1[11] ;
+ assign \gpio_clock_1_shifted[11] = \gpio_clock_1[10] ;
+ assign \gpio_clock_1_shifted[10] = \gpio_clock_1[9] ;
+ assign \gpio_clock_1_shifted[9] = \gpio_clock_1[8] ;
+ assign \gpio_clock_1_shifted[8] = \gpio_clock_1[7] ;
+ assign \gpio_clock_1_shifted[7] = \gpio_clock_1[6] ;
+ assign \gpio_clock_1_shifted[6] = \gpio_clock_1[5] ;
+ assign \gpio_clock_1_shifted[5] = \gpio_clock_1[4] ;
+ assign \gpio_clock_1_shifted[4] = \gpio_clock_1[3] ;
+ assign \gpio_clock_1_shifted[3] = \gpio_clock_1[2] ;
+ assign \gpio_clock_1_shifted[2] = \gpio_clock_1[1] ;
+ assign \gpio_clock_1_shifted[1] = \gpio_clock_1[0] ;
+ assign \gpio_resetn_1_shifted[18] = \gpio_resetn_1[17] ;
+ assign \gpio_resetn_1_shifted[17] = \gpio_resetn_1[16] ;
+ assign \gpio_resetn_1_shifted[16] = \gpio_resetn_1[15] ;
+ assign \gpio_resetn_1_shifted[15] = \gpio_resetn_1[14] ;
+ assign \gpio_resetn_1_shifted[14] = \gpio_resetn_1[13] ;
+ assign \gpio_resetn_1_shifted[13] = \gpio_resetn_1[12] ;
+ assign \gpio_resetn_1_shifted[12] = \gpio_resetn_1[11] ;
+ assign \gpio_resetn_1_shifted[11] = \gpio_resetn_1[10] ;
+ assign \gpio_resetn_1_shifted[10] = \gpio_resetn_1[9] ;
+ assign \gpio_resetn_1_shifted[9] = \gpio_resetn_1[8] ;
+ assign \gpio_resetn_1_shifted[8] = \gpio_resetn_1[7] ;
+ assign \gpio_resetn_1_shifted[7] = \gpio_resetn_1[6] ;
+ assign \gpio_resetn_1_shifted[6] = \gpio_resetn_1[5] ;
+ assign \gpio_resetn_1_shifted[5] = \gpio_resetn_1[4] ;
+ assign \gpio_resetn_1_shifted[4] = \gpio_resetn_1[3] ;
+ assign \gpio_resetn_1_shifted[3] = \gpio_resetn_1[2] ;
+ assign \gpio_resetn_1_shifted[2] = \gpio_resetn_1[1] ;
+ assign \gpio_resetn_1_shifted[1] = \gpio_resetn_1[0] ;
+ assign \gpio_clock_2_shifted[17] = \gpio_clock_2[18] ;
+ assign \gpio_clock_2_shifted[16] = \gpio_clock_2[17] ;
+ assign \gpio_clock_2_shifted[15] = \gpio_clock_2[16] ;
+ assign \gpio_clock_2_shifted[14] = \gpio_clock_2[15] ;
+ assign \gpio_clock_2_shifted[13] = \gpio_clock_2[14] ;
+ assign \gpio_clock_2_shifted[12] = \gpio_clock_2[13] ;
+ assign \gpio_clock_2_shifted[11] = \gpio_clock_2[12] ;
+ assign \gpio_clock_2_shifted[10] = \gpio_clock_2[11] ;
+ assign \gpio_clock_2_shifted[9] = \gpio_clock_2[10] ;
+ assign \gpio_clock_2_shifted[8] = \gpio_clock_2[9] ;
+ assign \gpio_clock_2_shifted[7] = \gpio_clock_2[8] ;
+ assign \gpio_clock_2_shifted[6] = \gpio_clock_2[7] ;
+ assign \gpio_clock_2_shifted[5] = \gpio_clock_2[6] ;
+ assign \gpio_clock_2_shifted[4] = \gpio_clock_2[5] ;
+ assign \gpio_clock_2_shifted[3] = \gpio_clock_2[4] ;
+ assign \gpio_clock_2_shifted[2] = \gpio_clock_2[3] ;
+ assign \gpio_clock_2_shifted[1] = \gpio_clock_2[2] ;
+ assign \gpio_clock_2_shifted[0] = \gpio_clock_2[1] ;
+ assign \gpio_load_1_shifted[18] = \gpio_load_1[17] ;
+ assign \gpio_load_1_shifted[17] = \gpio_load_1[16] ;
+ assign \gpio_load_1_shifted[16] = \gpio_load_1[15] ;
+ assign \gpio_load_1_shifted[15] = \gpio_load_1[14] ;
+ assign \gpio_load_1_shifted[14] = \gpio_load_1[13] ;
+ assign \gpio_load_1_shifted[13] = \gpio_load_1[12] ;
+ assign \gpio_load_1_shifted[12] = \gpio_load_1[11] ;
+ assign \gpio_load_1_shifted[11] = \gpio_load_1[10] ;
+ assign \gpio_load_1_shifted[10] = \gpio_load_1[9] ;
+ assign \gpio_load_1_shifted[9] = \gpio_load_1[8] ;
+ assign \gpio_load_1_shifted[8] = \gpio_load_1[7] ;
+ assign \gpio_load_1_shifted[7] = \gpio_load_1[6] ;
+ assign \gpio_load_1_shifted[6] = \gpio_load_1[5] ;
+ assign \gpio_load_1_shifted[5] = \gpio_load_1[4] ;
+ assign \gpio_load_1_shifted[4] = \gpio_load_1[3] ;
+ assign \gpio_load_1_shifted[3] = \gpio_load_1[2] ;
+ assign \gpio_load_1_shifted[2] = \gpio_load_1[1] ;
+ assign \gpio_load_1_shifted[1] = \gpio_load_1[0] ;
+ assign \gpio_serial_link_2_shifted[17] = \gpio_serial_link_2[18] ;
+ assign \gpio_serial_link_2_shifted[16] = \gpio_serial_link_2[17] ;
+ assign \gpio_serial_link_2_shifted[15] = \gpio_serial_link_2[16] ;
+ assign \gpio_serial_link_2_shifted[14] = \gpio_serial_link_2[15] ;
+ assign \gpio_serial_link_2_shifted[13] = \gpio_serial_link_2[14] ;
+ assign \gpio_serial_link_2_shifted[12] = \gpio_serial_link_2[13] ;
+ assign \gpio_serial_link_2_shifted[11] = \gpio_serial_link_2[12] ;
+ assign \gpio_serial_link_2_shifted[10] = \gpio_serial_link_2[11] ;
+ assign \gpio_serial_link_2_shifted[9] = \gpio_serial_link_2[10] ;
+ assign \gpio_serial_link_2_shifted[8] = \gpio_serial_link_2[9] ;
+ assign \gpio_serial_link_2_shifted[7] = \gpio_serial_link_2[8] ;
+ assign \gpio_serial_link_2_shifted[6] = \gpio_serial_link_2[7] ;
+ assign \gpio_serial_link_2_shifted[5] = \gpio_serial_link_2[6] ;
+ assign \gpio_serial_link_2_shifted[4] = \gpio_serial_link_2[5] ;
+ assign \gpio_serial_link_2_shifted[3] = \gpio_serial_link_2[4] ;
+ assign \gpio_serial_link_2_shifted[2] = \gpio_serial_link_2[3] ;
+ assign \gpio_serial_link_2_shifted[1] = \gpio_serial_link_2[2] ;
+ assign \gpio_serial_link_2_shifted[0] = \gpio_serial_link_2[1] ;
+ assign \gpio_resetn_2_shifted[17] = \gpio_resetn_2[18] ;
+ assign \gpio_resetn_2_shifted[16] = \gpio_resetn_2[17] ;
+ assign \gpio_resetn_2_shifted[15] = \gpio_resetn_2[16] ;
+ assign \gpio_resetn_2_shifted[14] = \gpio_resetn_2[15] ;
+ assign \gpio_resetn_2_shifted[13] = \gpio_resetn_2[14] ;
+ assign \gpio_resetn_2_shifted[12] = \gpio_resetn_2[13] ;
+ assign \gpio_resetn_2_shifted[11] = \gpio_resetn_2[12] ;
+ assign \gpio_resetn_2_shifted[10] = \gpio_resetn_2[11] ;
+ assign \gpio_resetn_2_shifted[9] = \gpio_resetn_2[10] ;
+ assign \gpio_resetn_2_shifted[8] = \gpio_resetn_2[9] ;
+ assign \gpio_resetn_2_shifted[7] = \gpio_resetn_2[8] ;
+ assign \gpio_resetn_2_shifted[6] = \gpio_resetn_2[7] ;
+ assign \gpio_resetn_2_shifted[5] = \gpio_resetn_2[6] ;
+ assign \gpio_resetn_2_shifted[4] = \gpio_resetn_2[5] ;
+ assign \gpio_resetn_2_shifted[3] = \gpio_resetn_2[4] ;
+ assign \gpio_resetn_2_shifted[2] = \gpio_resetn_2[3] ;
+ assign \gpio_resetn_2_shifted[1] = \gpio_resetn_2[2] ;
+ assign \gpio_resetn_2_shifted[0] = \gpio_resetn_2[1] ;
+ assign \mgmt_io_in_hk[6] = \mgmt_io_in[6] ;
+ assign \mgmt_io_in_hk[5] = \mgmt_io_in[5] ;
+ assign \mgmt_io_in_hk[4] = \mgmt_io_in[4] ;
+ assign \mgmt_io_in_hk[3] = \mgmt_io_in[3] ;
+ assign \mgmt_io_in_hk[2] = \mgmt_io_in[2] ;
+ assign \mgmt_io_in_hk[1] = \mgmt_io_in[1] ;
+ assign \mgmt_io_in_hk[0] = \mgmt_io_in[0] ;
+ assign \mgmt_io_out_hk[6] = \mgmt_io_out[6] ;
+ assign \mgmt_io_out_hk[5] = \mgmt_io_out[5] ;
+ assign \mgmt_io_out_hk[4] = \mgmt_io_out[4] ;
+ assign \mgmt_io_out_hk[3] = \mgmt_io_out[3] ;
+ assign \mgmt_io_out_hk[2] = \mgmt_io_out[2] ;
+ assign \mgmt_io_out_hk[1] = \mgmt_io_out[1] ;
+ assign \mgmt_io_out_hk[0] = \mgmt_io_out[0] ;
+ assign \mgmt_io_oeb_hk[34] = \mgmt_io_oeb[34] ;
+ assign \mgmt_io_oeb_hk[33] = \mgmt_io_oeb[33] ;
+ assign \mgmt_io_oeb_hk[32] = \mgmt_io_oeb[32] ;
+ assign \mgmt_io_oeb_hk[31] = \mgmt_io_oeb[31] ;
+ assign \mgmt_io_oeb_hk[30] = \mgmt_io_oeb[30] ;
+ assign \mgmt_io_oeb_hk[29] = \mgmt_io_oeb[29] ;
+ assign \mgmt_io_oeb_hk[28] = \mgmt_io_oeb[28] ;
+ assign \mgmt_io_oeb_hk[27] = \mgmt_io_oeb[27] ;
+ assign \mgmt_io_oeb_hk[26] = \mgmt_io_oeb[26] ;
+ assign \mgmt_io_oeb_hk[25] = \mgmt_io_oeb[25] ;
+ assign \mgmt_io_oeb_hk[24] = \mgmt_io_oeb[24] ;
+ assign \mgmt_io_oeb_hk[23] = \mgmt_io_oeb[23] ;
+ assign \mgmt_io_oeb_hk[22] = \mgmt_io_oeb[22] ;
+ assign \mgmt_io_oeb_hk[21] = \mgmt_io_oeb[21] ;
+ assign \mgmt_io_oeb_hk[20] = \mgmt_io_oeb[20] ;
+ assign \mgmt_io_oeb_hk[19] = \mgmt_io_oeb[19] ;
+ assign \mgmt_io_oeb_hk[18] = \mgmt_io_oeb[18] ;
+ assign \mgmt_io_oeb_hk[17] = \mgmt_io_oeb[17] ;
+ assign \mgmt_io_oeb_hk[16] = \mgmt_io_oeb[16] ;
+ assign \mgmt_io_oeb_hk[15] = \mgmt_io_oeb[15] ;
+ assign \mgmt_io_oeb_hk[14] = \mgmt_io_oeb[14] ;
+ assign \mgmt_io_oeb_hk[13] = \mgmt_io_oeb[13] ;
+ assign \mgmt_io_oeb_hk[12] = \mgmt_io_oeb[12] ;
+ assign \mgmt_io_oeb_hk[11] = \mgmt_io_oeb[11] ;
+ assign \mgmt_io_oeb_hk[10] = \mgmt_io_oeb[10] ;
+ assign \mgmt_io_oeb_hk[9] = \mgmt_io_oeb[9] ;
+ assign \mgmt_io_oeb_hk[8] = \mgmt_io_oeb[8] ;
+ assign \mgmt_io_oeb_hk[7] = \mgmt_io_oeb[7] ;
+ assign \mgmt_io_oeb_hk[6] = \mgmt_io_oeb[6] ;
+ assign \mgmt_io_oeb_hk[5] = \mgmt_io_oeb[5] ;
+ assign \mgmt_io_oeb_hk[4] = \mgmt_io_oeb[4] ;
+ assign \mgmt_io_oeb_hk[3] = \mgmt_io_oeb[3] ;
+ assign \mgmt_io_oeb_hk[2] = \mgmt_io_oeb[2] ;
+ assign \mgmt_io_oeb_hk[1] = \mgmt_io_oeb[1] ;
+ assign \mgmt_io_oeb_hk[0] = \mgmt_io_oeb[0] ;
+ assign mprj_io_loader_data_2_buf = \gpio_serial_link_2_shifted[18] ;
+ assign mprj_io_loader_resetn_buf = \gpio_resetn_2_shifted[18] ;
+ assign mprj_io_loader_strobe_buf = \gpio_load_2_shifted[18] ;
+ assign mprj_io_loader_clock_buf = \gpio_clock_2_shifted[18] ;
+ assign mprj_io_loader_data_1 = \gpio_serial_link_1_shifted[0] ;
+ assign mprj_io_loader_strobe = \gpio_load_1_shifted[0] ;
+ assign mprj_io_loader_clock = \gpio_clock_1_shifted[0] ;
+ assign mprj_io_loader_resetn = \gpio_resetn_1_shifted[0] ;
+endmodule
diff --git a/tapeout/outputs/verilog/gl/gpio_defaults_block_0403.v b/tapeout/outputs/verilog/gl/gpio_defaults_block_0403.v
new file mode 100644
index 0000000..33fbfde
--- /dev/null
+++ b/tapeout/outputs/verilog/gl/gpio_defaults_block_0403.v
@@ -0,0 +1,260 @@
+module gpio_defaults_block_0403 (VGND,
+ VPWR,
+ gpio_defaults);
+ input VGND;
+ input VPWR;
+ output [12:0] gpio_defaults;
+
+ wire \gpio_defaults_low[0] ;
+ wire \gpio_defaults_high[10] ;
+ wire \gpio_defaults_low[11] ;
+ wire \gpio_defaults_low[12] ;
+ wire \gpio_defaults_high[1] ;
+ wire \gpio_defaults_low[2] ;
+ wire \gpio_defaults_low[3] ;
+ wire \gpio_defaults_low[4] ;
+ wire \gpio_defaults_low[5] ;
+ wire \gpio_defaults_low[6] ;
+ wire \gpio_defaults_low[7] ;
+ wire \gpio_defaults_low[8] ;
+ wire \gpio_defaults_low[9] ;
+ wire \gpio_defaults_high[0] ;
+ wire \gpio_defaults_high[11] ;
+ wire \gpio_defaults_high[12] ;
+ wire \gpio_defaults_high[2] ;
+ wire \gpio_defaults_high[3] ;
+ wire \gpio_defaults_high[4] ;
+ wire \gpio_defaults_high[5] ;
+ wire \gpio_defaults_high[6] ;
+ wire \gpio_defaults_high[7] ;
+ wire \gpio_defaults_high[8] ;
+ wire \gpio_defaults_high[9] ;
+ wire \gpio_defaults_low[10] ;
+ wire \gpio_defaults_low[1] ;
+
+ sky130_fd_sc_hd__fill_1 FILLER_0_29 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_0_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_33 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_38 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_43 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_48 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_55 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_60 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_9 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_15 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_27 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_39 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_1_51 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_1_55 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_1_57 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_1_61 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_15 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_2_27 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_29 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_41 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_2_53 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_2_57 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_2_61 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_0 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_1 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_2 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_4 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_5 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_10 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_6 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_7 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_8 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_9 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[0] (.HI(\gpio_defaults_high[0] ),
+ .LO(\gpio_defaults_low[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[10] (.HI(\gpio_defaults_high[10] ),
+ .LO(\gpio_defaults_low[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[11] (.HI(\gpio_defaults_high[11] ),
+ .LO(\gpio_defaults_low[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[12] (.HI(\gpio_defaults_high[12] ),
+ .LO(\gpio_defaults_low[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[1] (.HI(\gpio_defaults_high[1] ),
+ .LO(\gpio_defaults_low[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[2] (.HI(\gpio_defaults_high[2] ),
+ .LO(\gpio_defaults_low[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[3] (.HI(\gpio_defaults_high[3] ),
+ .LO(\gpio_defaults_low[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[4] (.HI(\gpio_defaults_high[4] ),
+ .LO(\gpio_defaults_low[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[5] (.HI(\gpio_defaults_high[5] ),
+ .LO(\gpio_defaults_low[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[6] (.HI(\gpio_defaults_high[6] ),
+ .LO(\gpio_defaults_low[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[7] (.HI(\gpio_defaults_high[7] ),
+ .LO(\gpio_defaults_low[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[8] (.HI(\gpio_defaults_high[8] ),
+ .LO(\gpio_defaults_low[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[9] (.HI(\gpio_defaults_high[9] ),
+ .LO(\gpio_defaults_low[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ assign gpio_defaults[0] = \gpio_defaults_high[0] ;
+ assign gpio_defaults[1] = \gpio_defaults_high[1] ;
+ assign gpio_defaults[2] = \gpio_defaults_low[2] ;
+ assign gpio_defaults[3] = \gpio_defaults_low[3] ;
+ assign gpio_defaults[4] = \gpio_defaults_low[4] ;
+ assign gpio_defaults[5] = \gpio_defaults_low[5] ;
+ assign gpio_defaults[6] = \gpio_defaults_low[6] ;
+ assign gpio_defaults[7] = \gpio_defaults_low[7] ;
+ assign gpio_defaults[8] = \gpio_defaults_low[8] ;
+ assign gpio_defaults[9] = \gpio_defaults_low[9] ;
+ assign gpio_defaults[10] = \gpio_defaults_high[10] ;
+ assign gpio_defaults[11] = \gpio_defaults_low[11] ;
+ assign gpio_defaults[12] = \gpio_defaults_low[12] ;
+endmodule
diff --git a/tapeout/outputs/verilog/gl/gpio_defaults_block_0801.v b/tapeout/outputs/verilog/gl/gpio_defaults_block_0801.v
new file mode 100644
index 0000000..379ba1c
--- /dev/null
+++ b/tapeout/outputs/verilog/gl/gpio_defaults_block_0801.v
@@ -0,0 +1,260 @@
+module gpio_defaults_block_0801 (VGND,
+ VPWR,
+ gpio_defaults);
+ input VGND;
+ input VPWR;
+ output [12:0] gpio_defaults;
+
+ wire \gpio_defaults_low[0] ;
+ wire \gpio_defaults_high[10] ;
+ wire \gpio_defaults_low[11] ;
+ wire \gpio_defaults_low[12] ;
+ wire \gpio_defaults_high[1] ;
+ wire \gpio_defaults_low[2] ;
+ wire \gpio_defaults_low[3] ;
+ wire \gpio_defaults_low[4] ;
+ wire \gpio_defaults_low[5] ;
+ wire \gpio_defaults_low[6] ;
+ wire \gpio_defaults_low[7] ;
+ wire \gpio_defaults_low[8] ;
+ wire \gpio_defaults_low[9] ;
+ wire \gpio_defaults_high[0] ;
+ wire \gpio_defaults_high[11] ;
+ wire \gpio_defaults_high[12] ;
+ wire \gpio_defaults_high[2] ;
+ wire \gpio_defaults_high[3] ;
+ wire \gpio_defaults_high[4] ;
+ wire \gpio_defaults_high[5] ;
+ wire \gpio_defaults_high[6] ;
+ wire \gpio_defaults_high[7] ;
+ wire \gpio_defaults_high[8] ;
+ wire \gpio_defaults_high[9] ;
+ wire \gpio_defaults_low[10] ;
+ wire \gpio_defaults_low[1] ;
+
+ sky130_fd_sc_hd__fill_1 FILLER_0_29 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_0_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_33 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_38 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_43 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_48 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_55 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_60 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_9 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_15 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_27 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_39 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_1_51 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_1_55 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_1_57 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_1_61 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_15 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_2_27 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_29 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_41 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_2_53 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_2_57 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_2_61 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_0 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_1 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_2 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_4 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_5 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_10 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_6 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_7 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_8 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_9 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[0] (.HI(\gpio_defaults_high[0] ),
+ .LO(\gpio_defaults_low[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[10] (.HI(\gpio_defaults_high[10] ),
+ .LO(\gpio_defaults_low[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[11] (.HI(\gpio_defaults_high[11] ),
+ .LO(\gpio_defaults_low[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[12] (.HI(\gpio_defaults_high[12] ),
+ .LO(\gpio_defaults_low[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[1] (.HI(\gpio_defaults_high[1] ),
+ .LO(\gpio_defaults_low[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[2] (.HI(\gpio_defaults_high[2] ),
+ .LO(\gpio_defaults_low[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[3] (.HI(\gpio_defaults_high[3] ),
+ .LO(\gpio_defaults_low[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[4] (.HI(\gpio_defaults_high[4] ),
+ .LO(\gpio_defaults_low[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[5] (.HI(\gpio_defaults_high[5] ),
+ .LO(\gpio_defaults_low[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[6] (.HI(\gpio_defaults_high[6] ),
+ .LO(\gpio_defaults_low[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[7] (.HI(\gpio_defaults_high[7] ),
+ .LO(\gpio_defaults_low[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[8] (.HI(\gpio_defaults_high[8] ),
+ .LO(\gpio_defaults_low[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[9] (.HI(\gpio_defaults_high[9] ),
+ .LO(\gpio_defaults_low[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ assign gpio_defaults[0] = \gpio_defaults_high[0] ;
+ assign gpio_defaults[1] = \gpio_defaults_low[1] ;
+ assign gpio_defaults[2] = \gpio_defaults_low[2] ;
+ assign gpio_defaults[3] = \gpio_defaults_low[3] ;
+ assign gpio_defaults[4] = \gpio_defaults_low[4] ;
+ assign gpio_defaults[5] = \gpio_defaults_low[5] ;
+ assign gpio_defaults[6] = \gpio_defaults_low[6] ;
+ assign gpio_defaults[7] = \gpio_defaults_low[7] ;
+ assign gpio_defaults[8] = \gpio_defaults_low[8] ;
+ assign gpio_defaults[9] = \gpio_defaults_low[9] ;
+ assign gpio_defaults[10] = \gpio_defaults_low[10] ;
+ assign gpio_defaults[11] = \gpio_defaults_high[11] ;
+ assign gpio_defaults[12] = \gpio_defaults_low[12] ;
+endmodule
diff --git a/tapeout/outputs/verilog/gl/gpio_defaults_block_1803.v b/tapeout/outputs/verilog/gl/gpio_defaults_block_1803.v
new file mode 100644
index 0000000..13ad29a
--- /dev/null
+++ b/tapeout/outputs/verilog/gl/gpio_defaults_block_1803.v
@@ -0,0 +1,260 @@
+module gpio_defaults_block_1803 (VGND,
+ VPWR,
+ gpio_defaults);
+ input VGND;
+ input VPWR;
+ output [12:0] gpio_defaults;
+
+ wire \gpio_defaults_low[0] ;
+ wire \gpio_defaults_high[10] ;
+ wire \gpio_defaults_low[11] ;
+ wire \gpio_defaults_low[12] ;
+ wire \gpio_defaults_high[1] ;
+ wire \gpio_defaults_low[2] ;
+ wire \gpio_defaults_low[3] ;
+ wire \gpio_defaults_low[4] ;
+ wire \gpio_defaults_low[5] ;
+ wire \gpio_defaults_low[6] ;
+ wire \gpio_defaults_low[7] ;
+ wire \gpio_defaults_low[8] ;
+ wire \gpio_defaults_low[9] ;
+ wire \gpio_defaults_high[0] ;
+ wire \gpio_defaults_high[11] ;
+ wire \gpio_defaults_high[12] ;
+ wire \gpio_defaults_high[2] ;
+ wire \gpio_defaults_high[3] ;
+ wire \gpio_defaults_high[4] ;
+ wire \gpio_defaults_high[5] ;
+ wire \gpio_defaults_high[6] ;
+ wire \gpio_defaults_high[7] ;
+ wire \gpio_defaults_high[8] ;
+ wire \gpio_defaults_high[9] ;
+ wire \gpio_defaults_low[10] ;
+ wire \gpio_defaults_low[1] ;
+
+ sky130_fd_sc_hd__fill_1 FILLER_0_29 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_0_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_33 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_38 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_43 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_48 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_55 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_60 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_9 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_15 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_27 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_1_39 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_1_51 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_1_55 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_1_57 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_1_61 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_15 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_2_27 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_29 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_12 FILLER_2_41 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_2_53 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_2_57 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_2_61 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_0 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_1 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_2 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_3 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_4 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 PHY_5 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_10 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_6 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_7 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_8 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_9 (.VGND(VGND),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[0] (.HI(\gpio_defaults_high[0] ),
+ .LO(\gpio_defaults_low[0] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[10] (.HI(\gpio_defaults_high[10] ),
+ .LO(\gpio_defaults_low[10] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[11] (.HI(\gpio_defaults_high[11] ),
+ .LO(\gpio_defaults_low[11] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[12] (.HI(\gpio_defaults_high[12] ),
+ .LO(\gpio_defaults_low[12] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[1] (.HI(\gpio_defaults_high[1] ),
+ .LO(\gpio_defaults_low[1] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[2] (.HI(\gpio_defaults_high[2] ),
+ .LO(\gpio_defaults_low[2] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[3] (.HI(\gpio_defaults_high[3] ),
+ .LO(\gpio_defaults_low[3] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[4] (.HI(\gpio_defaults_high[4] ),
+ .LO(\gpio_defaults_low[4] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[5] (.HI(\gpio_defaults_high[5] ),
+ .LO(\gpio_defaults_low[5] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[6] (.HI(\gpio_defaults_high[6] ),
+ .LO(\gpio_defaults_low[6] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[7] (.HI(\gpio_defaults_high[7] ),
+ .LO(\gpio_defaults_low[7] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[8] (.HI(\gpio_defaults_high[8] ),
+ .LO(\gpio_defaults_low[8] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hd__conb_1 \gpio_default_value[9] (.HI(\gpio_defaults_high[9] ),
+ .LO(\gpio_defaults_low[9] ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ assign gpio_defaults[0] = \gpio_defaults_high[0] ;
+ assign gpio_defaults[1] = \gpio_defaults_high[1] ;
+ assign gpio_defaults[2] = \gpio_defaults_low[2] ;
+ assign gpio_defaults[3] = \gpio_defaults_low[3] ;
+ assign gpio_defaults[4] = \gpio_defaults_low[4] ;
+ assign gpio_defaults[5] = \gpio_defaults_low[5] ;
+ assign gpio_defaults[6] = \gpio_defaults_low[6] ;
+ assign gpio_defaults[7] = \gpio_defaults_low[7] ;
+ assign gpio_defaults[8] = \gpio_defaults_low[8] ;
+ assign gpio_defaults[9] = \gpio_defaults_low[9] ;
+ assign gpio_defaults[10] = \gpio_defaults_low[10] ;
+ assign gpio_defaults[11] = \gpio_defaults_high[11] ;
+ assign gpio_defaults[12] = \gpio_defaults_high[12] ;
+endmodule
diff --git a/tapeout/outputs/verilog/gl/user_id_programming.v b/tapeout/outputs/verilog/gl/user_id_programming.v
new file mode 100644
index 0000000..b7bc6c6
--- /dev/null
+++ b/tapeout/outputs/verilog/gl/user_id_programming.v
@@ -0,0 +1,786 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
+
+module user_id_programming(VPWR, VGND, mask_rev);
+ input VGND;
+ input VPWR;
+ output [31:0] mask_rev;
+ wire \user_proj_id_high[0] ;
+ wire \user_proj_id_high[10] ;
+ wire \user_proj_id_high[11] ;
+ wire \user_proj_id_high[12] ;
+ wire \user_proj_id_low[13] ;
+ wire \user_proj_id_low[14] ;
+ wire \user_proj_id_high[15] ;
+ wire \user_proj_id_low[16] ;
+ wire \user_proj_id_high[17] ;
+ wire \user_proj_id_high[18] ;
+ wire \user_proj_id_low[19] ;
+ wire \user_proj_id_high[1] ;
+ wire \user_proj_id_low[20] ;
+ wire \user_proj_id_low[21] ;
+ wire \user_proj_id_low[22] ;
+ wire \user_proj_id_low[23] ;
+ wire \user_proj_id_high[24] ;
+ wire \user_proj_id_high[25] ;
+ wire \user_proj_id_high[26] ;
+ wire \user_proj_id_low[27] ;
+ wire \user_proj_id_high[28] ;
+ wire \user_proj_id_high[29] ;
+ wire \user_proj_id_high[2] ;
+ wire \user_proj_id_low[30] ;
+ wire \user_proj_id_low[31] ;
+ wire \user_proj_id_high[3] ;
+ wire \user_proj_id_high[4] ;
+ wire \user_proj_id_high[5] ;
+ wire \user_proj_id_high[6] ;
+ wire \user_proj_id_high[7] ;
+ wire \user_proj_id_high[8] ;
+ wire \user_proj_id_high[9] ;
+ sky130_fd_sc_hd__decap_3 FILLER_0_15 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_8 FILLER_0_21 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__fill_2 FILLER_0_29 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__fill_1 FILLER_0_3 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_4 FILLER_0_32 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_8 FILLER_0_39 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 FILLER_0_47 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_8 FILLER_0_7 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__fill_2 FILLER_1_12 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__fill_1 FILLER_1_20 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_6 FILLER_1_24 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_12 FILLER_1_33 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__fill_2 FILLER_1_45 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 FILLER_1_6 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_12 FILLER_2_15 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_4 FILLER_2_27 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_12 FILLER_2_3 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_6 FILLER_2_32 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_6 FILLER_2_44 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_12 FILLER_3_18 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_12 FILLER_3_30 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_8 FILLER_3_42 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_12 FILLER_3_6 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_4 FILLER_4_10 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__fill_1 FILLER_4_14 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__fill_2 FILLER_4_18 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_4 FILLER_4_26 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__fill_1 FILLER_4_3 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__fill_1 FILLER_4_30 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 FILLER_4_35 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__fill_2 FILLER_4_41 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_4 FILLER_4_46 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_12 FILLER_5_11 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_8 FILLER_5_23 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 FILLER_5_31 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_6 FILLER_5_40 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__fill_1 FILLER_5_49 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__fill_2 FILLER_5_6 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_8 FILLER_6_12 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__fill_1 FILLER_6_20 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__fill_1 FILLER_6_24 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 FILLER_6_28 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_6 FILLER_6_3 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_4 FILLER_6_32 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__fill_1 FILLER_6_36 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_8 FILLER_6_40 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__fill_2 FILLER_6_48 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_12 FILLER_7_15 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_6 FILLER_7_27 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_12 FILLER_7_3 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_6 FILLER_7_36 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__fill_1 FILLER_7_42 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_4 FILLER_7_46 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_12 FILLER_8_15 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_4 FILLER_8_27 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_12 FILLER_8_3 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_12 FILLER_8_32 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_6 FILLER_8_44 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 PHY_0 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 PHY_1 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 PHY_10 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 PHY_11 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 PHY_12 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 PHY_13 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 PHY_14 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 PHY_15 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 PHY_16 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 PHY_17 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_18 (
+ .VGND(VGND),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_19 (
+ .VGND(VGND),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 PHY_2 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_20 (
+ .VGND(VGND),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_21 (
+ .VGND(VGND),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_22 (
+ .VGND(VGND),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 PHY_3 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 PHY_4 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 PHY_5 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 PHY_6 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 PHY_7 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 PHY_8 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__decap_3 PHY_9 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[0] (
+ .HI(\user_proj_id_high[0] ),
+ .LO(mask_rev[0]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[10] (
+ .HI(\user_proj_id_high[10] ),
+ .LO(mask_rev[10]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[11] (
+ .HI(\user_proj_id_high[11] ),
+ .LO(mask_rev[11]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[12] (
+ .HI(\user_proj_id_high[12] ),
+ .LO(mask_rev[12]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[13] (
+ .LO(\user_proj_id_low[13] ),
+ .HI(mask_rev[13]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[14] (
+ .LO(\user_proj_id_low[14] ),
+ .HI(mask_rev[14]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[15] (
+ .HI(\user_proj_id_high[15] ),
+ .LO(mask_rev[15]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[16] (
+ .LO(\user_proj_id_low[16] ),
+ .HI(mask_rev[16]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[17] (
+ .HI(\user_proj_id_high[17] ),
+ .LO(mask_rev[17]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[18] (
+ .HI(\user_proj_id_high[18] ),
+ .LO(mask_rev[18]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[19] (
+ .LO(\user_proj_id_low[19] ),
+ .HI(mask_rev[19]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[1] (
+ .HI(\user_proj_id_high[1] ),
+ .LO(mask_rev[1]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[20] (
+ .LO(\user_proj_id_low[20] ),
+ .HI(mask_rev[20]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[21] (
+ .LO(\user_proj_id_low[21] ),
+ .HI(mask_rev[21]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[22] (
+ .LO(\user_proj_id_low[22] ),
+ .HI(mask_rev[22]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[23] (
+ .LO(\user_proj_id_low[23] ),
+ .HI(mask_rev[23]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[24] (
+ .HI(\user_proj_id_high[24] ),
+ .LO(mask_rev[24]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[25] (
+ .HI(\user_proj_id_high[25] ),
+ .LO(mask_rev[25]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[26] (
+ .HI(\user_proj_id_high[26] ),
+ .LO(mask_rev[26]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[27] (
+ .LO(\user_proj_id_low[27] ),
+ .HI(mask_rev[27]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[28] (
+ .HI(\user_proj_id_high[28] ),
+ .LO(mask_rev[28]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[29] (
+ .HI(\user_proj_id_high[29] ),
+ .LO(mask_rev[29]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[2] (
+ .HI(\user_proj_id_high[2] ),
+ .LO(mask_rev[2]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[30] (
+ .LO(\user_proj_id_low[30] ),
+ .HI(mask_rev[30]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[31] (
+ .LO(\user_proj_id_low[31] ),
+ .HI(mask_rev[31]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[3] (
+ .HI(\user_proj_id_high[3] ),
+ .LO(mask_rev[3]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[4] (
+ .HI(\user_proj_id_high[4] ),
+ .LO(mask_rev[4]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[5] (
+ .HI(\user_proj_id_high[5] ),
+ .LO(mask_rev[5]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[6] (
+ .HI(\user_proj_id_high[6] ),
+ .LO(mask_rev[6]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[7] (
+ .HI(\user_proj_id_high[7] ),
+ .LO(mask_rev[7]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[8] (
+ .HI(\user_proj_id_high[8] ),
+ .LO(mask_rev[8]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__conb_1 \mask_rev_value[9] (
+ .HI(\user_proj_id_high[9] ),
+ .LO(mask_rev[9]),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+endmodule
diff --git a/tapeout/outputs/verilog/rtl/caravel.v b/tapeout/outputs/verilog/rtl/caravel.v
new file mode 100644
index 0000000..bcff3b7
--- /dev/null
+++ b/tapeout/outputs/verilog/rtl/caravel.v
@@ -0,0 +1,1635 @@
+ `ifdef SIM
+ `default_nettype wire
+ `endif
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+/*--------------------------------------------------------------*/
+/* caravel, a project harness for the Google/SkyWater sky130 */
+/* fabrication process and open source PDK */
+/* */
+/* Copyright 2020 efabless, Inc. */
+/* Written by Tim Edwards, December 2019 */
+/* and Mohamed Shalan, August 2020 */
+/* This file is open source hardware released under the */
+/* Apache 2.0 license. See file LICENSE. */
+/* */
+/* Updated 10/15/2021: Revised using the housekeeping module */
+/* from housekeeping.v (refactoring a number of functions from */
+/* the management SoC). */
+/* */
+/*--------------------------------------------------------------*/
+
+module caravel (
+
+ // All top-level I/O are package-facing pins
+
+ inout vddio, // Common 3.3V padframe/ESD power
+ inout vddio_2, // Common 3.3V padframe/ESD power
+ inout vssio, // Common padframe/ESD ground
+ inout vssio_2, // Common padframe/ESD ground
+ inout vdda, // Management 3.3V power
+ inout vssa, // Common analog ground
+ inout vccd, // Management/Common 1.8V power
+ inout vssd, // Common digital ground
+ inout vdda1, // User area 1 3.3V power
+ inout vdda1_2, // User area 1 3.3V power
+ inout vdda2, // User area 2 3.3V power
+ inout vssa1, // User area 1 analog ground
+ inout vssa1_2, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V power
+ inout vccd2, // User area 2 1.8V power
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+
+ inout gpio, // Used for external LDO control
+ inout [`MPRJ_IO_PADS-1:0] mprj_io,
+ input clock, // CMOS core clock input, not a crystal
+ input resetb, // Reset input (sense inverted)
+
+ // Note that only two flash data pins are dedicated to the
+ // management SoC wrapper. The management SoC exports the
+ // quad SPI mode status to make use of the top two mprj_io
+ // pins for io2 and io3.
+
+ output flash_csb,
+ output flash_clk,
+ output flash_io0,
+ output flash_io1
+);
+
+ //------------------------------------------------------------
+ // This value is uniquely defined for each user project.
+ //------------------------------------------------------------
+ parameter USER_PROJECT_ID = 32'h00069f13;
+
+ /*
+ *--------------------------------------------------------------------
+ *
+ * These pins are overlaid on mprj_io space. They have the function
+ * below when the management processor is in reset, or in the default
+ * configuration. They are assigned to uses in the user space by the
+ * configuration program running off of the SPI flash. Note that even
+ * when the user has taken control of these pins, they can be restored
+ * to the original use by setting the resetb pin low. The SPI pins and
+ * UART pins can be connected directly to an FTDI chip as long as the
+ * FTDI chip sets these lines to high impedence (input function) at
+ * all times except when holding the chip in reset.
+ *
+ * JTAG = mprj_io[0] (inout)
+ * SDO = mprj_io[1] (output)
+ * SDI = mprj_io[2] (input)
+ * CSB = mprj_io[3] (input)
+ * SCK = mprj_io[4] (input)
+ * ser_rx = mprj_io[5] (input)
+ * ser_tx = mprj_io[6] (output)
+ * irq = mprj_io[7] (input)
+ *
+ * spi_sck = mprj_io[32] (output)
+ * spi_csb = mprj_io[33] (output)
+ * spi_sdi = mprj_io[34] (input)
+ * spi_sdo = mprj_io[35] (output)
+ * flash_io2 = mprj_io[36] (inout)
+ * flash_io3 = mprj_io[37] (inout)
+ *
+ * These pins are reserved for any project that wants to incorporate
+ * its own processor and flash controller. While a user project can
+ * technically use any available I/O pins for the purpose, these
+ * four pins connect to a pass-through mode from the SPI slave (pins
+ * 1-4 above) so that any SPI flash connected to these specific pins
+ * can be accessed through the SPI slave even when the processor is in
+ * reset.
+ *
+ * user_flash_csb = mprj_io[8]
+ * user_flash_sck = mprj_io[9]
+ * user_flash_io0 = mprj_io[10]
+ * user_flash_io1 = mprj_io[11]
+ *
+ *--------------------------------------------------------------------
+ */
+
+ // One-bit GPIO dedicated to management SoC (outside of user control)
+ wire gpio_out_core;
+ wire gpio_in_core;
+ wire gpio_mode0_core;
+ wire gpio_mode1_core;
+ wire gpio_outenb_core;
+ wire gpio_inenb_core;
+
+ // User Project Control (pad-facing)
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_inp_dis;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_oeb;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_ib_mode_sel;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_vtrip_sel;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_slow_sel;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_holdover;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_en;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_sel;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_pol;
+ wire [`MPRJ_IO_PADS*3-1:0] mprj_io_dm;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_in;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_out;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_one;
+
+ // User Project Control (user-facing)
+ wire [`MPRJ_IO_PADS-1:0] user_io_oeb;
+ wire [`MPRJ_IO_PADS-1:0] user_io_in;
+ wire [`MPRJ_IO_PADS-1:0] user_io_out;
+ wire [`MPRJ_IO_PADS-10:0] user_analog_io;
+
+ /* Padframe control signals */
+ wire [`MPRJ_IO_PADS_1-1:0] gpio_serial_link_1;
+ wire [`MPRJ_IO_PADS_2-1:0] gpio_serial_link_2;
+ wire mprj_io_loader_resetn;
+ wire mprj_io_loader_clock;
+ wire mprj_io_loader_strobe;
+ wire mprj_io_loader_data_1; /* user1 side serial loader */
+ wire mprj_io_loader_data_2; /* user2 side serial loader */
+
+ // User Project Control management I/O
+ // There are two types of GPIO connections:
+ // (1) Full Bidirectional: Management connects to in, out, and oeb
+ // Uses: JTAG and SDO
+ // (2) Selectable bidirectional: Management connects to in and out,
+ // which are tied together. oeb is grounded (oeb from the
+ // configuration is used)
+
+ // SDI = mprj_io[2] (input)
+ // CSB = mprj_io[3] (input)
+ // SCK = mprj_io[4] (input)
+ // ser_rx = mprj_io[5] (input)
+ // ser_tx = mprj_io[6] (output)
+ // irq = mprj_io[7] (input)
+
+ wire [`MPRJ_IO_PADS-1:0] mgmt_io_in; /* two- and three-pin data in */
+ wire [`MPRJ_IO_PADS-1:0] mgmt_io_out; /* two- and three-pin data out */
+ wire [`MPRJ_IO_PADS-1:0] mgmt_io_oeb; /* output enable, used only by */
+ /* the three-pin interfaces */
+ wire [`MPRJ_PWR_PADS-1:0] pwr_ctrl_nc; /* no-connects */
+
+ /* Buffers are placed between housekeeping and gpio_control_block */
+ /* instances to mitigate timing issues on very long (> 1.5mm) wires. */
+ wire [`MPRJ_IO_PADS-1:0] mgmt_io_in_hk; /* mgmt_io_in at housekeeping */
+ wire [`MPRJ_IO_PADS-1:0] mgmt_io_out_hk; /* mgmt_io_out at housekeeping */
+ wire [`MPRJ_IO_PADS-1:0] mgmt_io_oeb_hk; /* mgmt_io_oeb at housekeeping */
+
+ wire clock_core;
+
+ // Power-on-reset signal. The reset pad generates the sense-inverted
+ // reset at 3.3V. The 1.8V signal and the inverted 1.8V signal are
+ // derived.
+
+ wire porb_h;
+ wire porb_l;
+ wire por_l;
+
+ wire rstb_h;
+ wire rstb_l;
+
+ // Flash SPI communication (management SoC to housekeeping)
+ wire flash_clk_core, flash_csb_core;
+ wire flash_clk_oeb_core, flash_csb_oeb_core;
+ wire flash_io0_oeb_core, flash_io1_oeb_core;
+ wire flash_io2_oeb_core, flash_io3_oeb_core;
+ wire flash_io0_ieb_core, flash_io1_ieb_core;
+ wire flash_io2_ieb_core, flash_io3_ieb_core;
+ wire flash_io0_do_core, flash_io1_do_core;
+ wire flash_io2_do_core, flash_io3_do_core;
+ wire flash_io0_di_core, flash_io1_di_core;
+ wire flash_io2_di_core, flash_io3_di_core;
+
+ // Flash SPI communication (
+ wire flash_clk_frame;
+ wire flash_csb_frame;
+ wire flash_clk_oeb, flash_csb_oeb;
+ wire flash_clk_ieb, flash_csb_ieb;
+ wire flash_io0_oeb, flash_io1_oeb;
+ wire flash_io0_ieb, flash_io1_ieb;
+ wire flash_io0_do, flash_io1_do;
+ wire flash_io0_di, flash_io1_di;
+
+ // Flash buffered signals
+ wire flash_clk_frame_buf;
+ wire flash_csb_frame_buf;
+ wire flash_clk_ieb_buf, flash_csb_ieb_buf;
+ wire flash_io0_oeb_buf, flash_io1_oeb_buf;
+ wire flash_io0_ieb_buf, flash_io1_ieb_buf;
+ wire flash_io0_do_buf, flash_io1_do_buf;
+ wire flash_io0_di_buf, flash_io1_di_buf;
+
+ // Clock and reset buffered signals
+ wire caravel_clk_buf;
+ wire caravel_rstn_buf;
+ wire clock_core_buf;
+
+ // SoC pass through buffered signals
+ wire mprj_io_loader_clock_buf;
+ wire mprj_io_loader_strobe_buf;
+ wire mprj_io_loader_resetn_buf;
+ wire mprj_io_loader_data_2_buf;
+ wire rstb_l_buf;
+ wire por_l_buf;
+ wire porb_h_buf;
+
+
+ // SoC core
+ wire caravel_clk;
+ wire caravel_clk2;
+ wire caravel_rstn;
+
+ // top-level buffers
+ buff_flash_clkrst flash_clkrst_buffers (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .in_n({
+ caravel_clk,
+ caravel_rstn,
+ flash_clk_frame,
+ flash_csb_frame,
+ flash_clk_oeb,
+ flash_csb_oeb,
+ flash_io0_oeb,
+ flash_io1_oeb,
+ flash_io0_ieb,
+ flash_io1_ieb,
+ flash_io0_do,
+ flash_io1_do }),
+ .in_s({
+ clock_core,
+ flash_io1_di,
+ flash_io0_di }),
+ .out_s({
+ caravel_clk_buf,
+ caravel_rstn_buf,
+ flash_clk_frame_buf,
+ flash_csb_frame_buf,
+ flash_clk_oeb_buf,
+ flash_csb_oeb_buf,
+ flash_io0_oeb_buf,
+ flash_io1_oeb_buf,
+ flash_io0_ieb_buf,
+ flash_io1_ieb_buf,
+ flash_io0_do_buf,
+ flash_io1_do_buf }),
+ .out_n({
+ clock_core_buf,
+ flash_io1_di_buf,
+ flash_io0_di_buf })
+ );
+
+ `ifdef NO_TOP_LEVEL_BUFFERING
+ assign mgmt_io_in_hk = mgmt_io_in;
+ assign mgmt_io_out = mgmt_io_out_hk;
+ assign mgmt_io_oeb = mgmt_io_oeb_hk;
+ `else
+
+ /* NOTE: The first 7 GPIO are unbuffered, and all
+ * OEB lines except the last three are unbuffered
+ * (most of these end up being no-connects from
+ * housekeeping).
+ */
+ assign mgmt_io_in_hk[6:0] = mgmt_io_in[6:0];
+ assign mgmt_io_out[6:0] = mgmt_io_out_hk[6:0];
+ assign mgmt_io_oeb[34:0] = mgmt_io_oeb_hk[34:0];
+
+ gpio_signal_buffering sigbuf (
+ `ifdef USE_POWER_PINS
+ .vccd(vccd_core),
+ .vssd(vssd_core),
+ `endif
+ .mgmt_io_in_unbuf(mgmt_io_in[37:7]),
+ .mgmt_io_out_unbuf(mgmt_io_out_hk[37:7]),
+ .mgmt_io_oeb_unbuf(mgmt_io_oeb_hk[37:35]),
+ .mgmt_io_in_buf(mgmt_io_in_hk[37:7]),
+ .mgmt_io_out_buf(mgmt_io_out[37:7]),
+ .mgmt_io_oeb_buf(mgmt_io_oeb[37:35])
+ );
+ `endif
+
+ chip_io padframe(
+ `ifndef TOP_ROUTING
+ // Package Pins
+ .vddio_pad (vddio), // Common padframe/ESD supply
+ .vddio_pad2 (vddio_2),
+ .vssio_pad (vssio), // Common padframe/ESD ground
+ .vssio_pad2 (vssio_2),
+ .vccd_pad (vccd), // Common 1.8V supply
+ .vssd_pad (vssd), // Common digital ground
+ .vdda_pad (vdda), // Management analog 3.3V supply
+ .vssa_pad (vssa), // Management analog ground
+ .vdda1_pad (vdda1), // User area 1 3.3V supply
+ .vdda1_pad2 (vdda1_2),
+ .vdda2_pad (vdda2), // User area 2 3.3V supply
+ .vssa1_pad (vssa1), // User area 1 analog ground
+ .vssa1_pad2 (vssa1_2),
+ .vssa2_pad (vssa2), // User area 2 analog ground
+ .vccd1_pad (vccd1), // User area 1 1.8V supply
+ .vccd2_pad (vccd2), // User area 2 1.8V supply
+ .vssd1_pad (vssd1), // User area 1 digital ground
+ .vssd2_pad (vssd2), // User area 2 digital ground
+ .vddio (vddio_core),
+ .vssio (vssio_core),
+ .vdda (vdda_core),
+ .vssa (vssa_core),
+ .vccd (vccd_core),
+ .vssd (vssd_core),
+ .vdda1 (vdda1_core),
+ .vdda2 (vdda2_core),
+ .vssa1 (vssa1_core),
+ .vssa2 (vssa2_core),
+ .vccd1 (vccd1_core),
+ .vccd2 (vccd2_core),
+ .vssd1 (vssd1_core),
+ .vssd2 (vssd2_core),
+ `endif
+ // Core Side Pins
+ .gpio(gpio),
+ .mprj_io(mprj_io),
+ .clock(clock),
+ .resetb(resetb),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ // SoC Core Interface
+ .porb_h(porb_h),
+ .por(por_l_buf),
+ .resetb_core_h(rstb_h),
+ .clock_core(clock_core),
+ .gpio_out_core(gpio_out_core),
+ .gpio_in_core(gpio_in_core),
+ .gpio_mode0_core(gpio_mode0_core),
+ .gpio_mode1_core(gpio_mode1_core),
+ .gpio_outenb_core(gpio_outenb_core),
+ .gpio_inenb_core(gpio_inenb_core),
+ .flash_csb_core(flash_csb_frame_buf),
+ .flash_clk_core(flash_clk_frame_buf),
+ .flash_csb_oeb_core(flash_csb_oeb_buf),
+ .flash_clk_oeb_core(flash_clk_oeb_buf),
+ .flash_io0_oeb_core(flash_io0_oeb_buf),
+ .flash_io1_oeb_core(flash_io1_oeb_buf),
+ .flash_io0_ieb_core(flash_io0_ieb_buf),
+ .flash_io1_ieb_core(flash_io1_ieb_buf),
+ .flash_io0_do_core(flash_io0_do_buf),
+ .flash_io1_do_core(flash_io1_do_buf),
+ .flash_io0_di_core(flash_io0_di),
+ .flash_io1_di_core(flash_io1_di),
+ .mprj_io_one(mprj_io_one),
+ .mprj_io_in(mprj_io_in),
+ .mprj_io_out(mprj_io_out),
+ .mprj_io_oeb(mprj_io_oeb),
+ .mprj_io_inp_dis(mprj_io_inp_dis),
+ .mprj_io_ib_mode_sel(mprj_io_ib_mode_sel),
+ .mprj_io_vtrip_sel(mprj_io_vtrip_sel),
+ .mprj_io_slow_sel(mprj_io_slow_sel),
+ .mprj_io_holdover(mprj_io_holdover),
+ .mprj_io_analog_en(mprj_io_analog_en),
+ .mprj_io_analog_sel(mprj_io_analog_sel),
+ .mprj_io_analog_pol(mprj_io_analog_pol),
+ .mprj_io_dm(mprj_io_dm),
+ .mprj_analog_io(user_analog_io)
+ );
+
+
+ // Logic analyzer signals
+ wire [127:0] la_data_in_user; // From CPU to MPRJ
+ wire [127:0] la_data_in_mprj; // From MPRJ to CPU
+ wire [127:0] la_data_out_mprj; // From CPU to MPRJ
+ wire [127:0] la_data_out_user; // From MPRJ to CPU
+ wire [127:0] la_oenb_user; // From CPU to MPRJ
+ wire [127:0] la_oenb_mprj; // From CPU to MPRJ
+ wire [127:0] la_iena_mprj; // From CPU only
+
+ wire [2:0] user_irq; // From MRPJ to CPU
+ wire [2:0] user_irq_core;
+ wire [2:0] user_irq_ena;
+ wire [2:0] irq_spi; // From SPI and external pins
+
+ // Exported Wishbone Bus (processor facing)
+ wire mprj_iena_wb;
+ wire mprj_cyc_o_core;
+ wire mprj_stb_o_core;
+ wire mprj_we_o_core;
+ wire [3:0] mprj_sel_o_core;
+ wire [31:0] mprj_adr_o_core;
+ wire [31:0] mprj_dat_o_core;
+ wire mprj_ack_i_core;
+ wire [31:0] mprj_dat_i_core;
+
+ wire [31:0] hk_dat_i;
+ wire hk_ack_i;
+ wire hk_stb_o;
+ wire hk_cyc_o;
+
+ // Exported Wishbone Bus (user area facing)
+ wire mprj_cyc_o_user;
+ wire mprj_stb_o_user;
+ wire mprj_we_o_user;
+ wire [3:0] mprj_sel_o_user;
+ wire [31:0] mprj_adr_o_user;
+ wire [31:0] mprj_dat_o_user;
+ wire [31:0] mprj_dat_i_user;
+ wire mprj_ack_i_user;
+
+ // Mask revision
+ wire [31:0] mask_rev;
+
+ wire mprj_clock;
+ wire mprj_clock2;
+ wire mprj_reset;
+
+ // Power monitoring
+ wire mprj_vcc_pwrgood;
+ wire mprj2_vcc_pwrgood;
+ wire mprj_vdd_pwrgood;
+ wire mprj2_vdd_pwrgood;
+
+`ifdef USE_SRAM_RO_INTERFACE
+ // SRAM read-only access from housekeeping
+ wire hkspi_sram_clk;
+ wire hkspi_sram_csb;
+ wire [7:0] hkspi_sram_addr;
+ wire [31:0] hkspi_sram_data;
+`endif
+
+ // Management processor (wrapper). Any management core
+ // implementation must match this pinout.
+
+ // Pass thru clock and reset
+ wire clk_passthru;
+ wire resetn_passthru;
+
+ // NC passthru signal porb_h
+ wire porb_h_in_nc;
+ wire porb_h_out_nc;
+
+ mgmt_core_wrapper soc (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+
+ // SoC pass through buffered signals
+ .serial_clock_in(mprj_io_loader_clock),
+ .serial_clock_out(mprj_io_loader_clock_buf),
+ .serial_load_in(mprj_io_loader_strobe),
+ .serial_load_out(mprj_io_loader_strobe_buf),
+ .serial_resetn_in(mprj_io_loader_resetn),
+ .serial_resetn_out(mprj_io_loader_resetn_buf),
+ .serial_data_2_in(mprj_io_loader_data_2),
+ .serial_data_2_out(mprj_io_loader_data_2_buf),
+ .rstb_l_in(rstb_l),
+ .rstb_l_out(rstb_l_buf),
+ .porb_h_in(porb_h_in_nc),
+ .porb_h_out(porb_h_out_nc),
+ .por_l_in(por_l),
+ .por_l_out(por_l_buf),
+
+ // Clock and reset
+ .core_clk(caravel_clk_buf),
+ .core_rstn(caravel_rstn_buf),
+
+ // Pass thru Clock and reset
+ .clk_in(caravel_clk_buf),
+ .resetn_in(caravel_rstn_buf),
+ .clk_out(clk_passthru),
+ .resetn_out(resetn_passthru),
+
+ // GPIO (1 pin)
+ .gpio_out_pad(gpio_out_core),
+ .gpio_in_pad(gpio_in_core),
+ .gpio_mode0_pad(gpio_mode0_core),
+ .gpio_mode1_pad(gpio_mode1_core),
+ .gpio_outenb_pad(gpio_outenb_core),
+ .gpio_inenb_pad(gpio_inenb_core),
+
+ // Primary SPI flash controller
+ .flash_csb(flash_csb_core),
+ .flash_clk(flash_clk_core),
+ .flash_io0_oeb(flash_io0_oeb_core),
+ .flash_io0_di(flash_io0_di_core),
+ .flash_io0_do(flash_io0_do_core),
+ .flash_io1_oeb(flash_io1_oeb_core),
+ .flash_io1_di(flash_io1_di_core),
+ .flash_io1_do(flash_io1_do_core),
+ .flash_io2_oeb(flash_io2_oeb_core),
+ .flash_io2_di(flash_io2_di_core),
+ .flash_io2_do(flash_io2_do_core),
+ .flash_io3_oeb(flash_io3_oeb_core),
+ .flash_io3_di(flash_io3_di_core),
+ .flash_io3_do(flash_io3_do_core),
+
+ // Exported Wishbone Bus
+ .mprj_wb_iena(mprj_iena_wb),
+ .mprj_cyc_o(mprj_cyc_o_core),
+ .mprj_stb_o(mprj_stb_o_core),
+ .mprj_we_o(mprj_we_o_core),
+ .mprj_sel_o(mprj_sel_o_core),
+ .mprj_adr_o(mprj_adr_o_core),
+ .mprj_dat_o(mprj_dat_o_core),
+ .mprj_ack_i(mprj_ack_i_core),
+ .mprj_dat_i(mprj_dat_i_core),
+
+ .hk_stb_o(hk_stb_o),
+ .hk_cyc_o(hk_cyc_o),
+ .hk_dat_i(hk_dat_i),
+ .hk_ack_i(hk_ack_i),
+
+ // IRQ
+ .irq({irq_spi, user_irq}),
+ .user_irq_ena(user_irq_ena),
+
+ // Module status (these may or may not be implemented)
+ .qspi_enabled(qspi_enabled),
+ .uart_enabled(uart_enabled),
+ .spi_enabled(spi_enabled),
+ .debug_mode(debug_mode),
+
+ // Module I/O (these may or may not be implemented)
+ // UART
+ .ser_tx(ser_tx),
+ .ser_rx(ser_rx),
+ // SPI master
+ .spi_sdi(spi_sdi),
+ .spi_csb(spi_csb),
+ .spi_sck(spi_sck),
+ .spi_sdo(spi_sdo),
+ .spi_sdoenb(spi_sdoenb),
+ // Debug
+ .debug_in(debug_in),
+ .debug_out(debug_out),
+ .debug_oeb(debug_oeb),
+ // Logic analyzer
+ .la_input(la_data_in_mprj),
+ .la_output(la_data_out_mprj),
+ .la_oenb(la_oenb_mprj),
+ .la_iena(la_iena_mprj),
+
+`ifdef USE_SRAM_RO_INTERFACE
+ // SRAM Read-only access from housekeeping
+ .sram_ro_clk(hkspi_sram_clk),
+ .sram_ro_csb(hkspi_sram_csb),
+ .sram_ro_addr(hkspi_sram_addr),
+ .sram_ro_data(hkspi_sram_data),
+`endif
+
+ // Trap status
+ .trap(trap)
+ );
+
+ /* Clock and reset to user space are passed through a tristate */
+ /* buffer like the above, but since they are intended to be */
+ /* always active, connect the enable to the logic-1 output from */
+ /* the vccd1 domain. */
+
+ mgmt_protect mgmt_buffers (
+ `ifdef USE_POWER_PINS
+ .vccd(vccd_core),
+ .vssd(vssd_core),
+ .vccd1(vccd1_core),
+ .vssd1(vssd1_core),
+ .vccd2(vccd2_core),
+ .vssd2(vssd2_core),
+ .vdda1(vdda1_core),
+ .vssa1(vssa1_core),
+ .vdda2(vdda2_core),
+ .vssa2(vssa2_core),
+ `endif
+ .caravel_clk(clk_passthru),
+ .caravel_clk2(caravel_clk2),
+ .caravel_rstn(resetn_passthru),
+ .mprj_iena_wb(mprj_iena_wb),
+ .mprj_cyc_o_core(mprj_cyc_o_core),
+ .mprj_stb_o_core(mprj_stb_o_core),
+ .mprj_we_o_core(mprj_we_o_core),
+ .mprj_sel_o_core(mprj_sel_o_core),
+ .mprj_adr_o_core(mprj_adr_o_core),
+ .mprj_dat_o_core(mprj_dat_o_core),
+ .mprj_ack_i_core(mprj_ack_i_core),
+ .mprj_dat_i_core(mprj_dat_i_core),
+ .user_irq_core(user_irq_core),
+ .user_irq_ena(user_irq_ena),
+ .la_data_out_core(la_data_out_user),
+ .la_data_out_mprj(la_data_out_mprj),
+ .la_data_in_core(la_data_in_user),
+ .la_data_in_mprj(la_data_in_mprj),
+ .la_oenb_mprj(la_oenb_mprj),
+ .la_oenb_core(la_oenb_user),
+ .la_iena_mprj(la_iena_mprj),
+
+ .user_clock(mprj_clock),
+ .user_clock2(mprj_clock2),
+ .user_reset(mprj_reset),
+ .mprj_cyc_o_user(mprj_cyc_o_user),
+ .mprj_stb_o_user(mprj_stb_o_user),
+ .mprj_we_o_user(mprj_we_o_user),
+ .mprj_sel_o_user(mprj_sel_o_user),
+ .mprj_adr_o_user(mprj_adr_o_user),
+ .mprj_dat_o_user(mprj_dat_o_user),
+ .mprj_dat_i_user(mprj_dat_i_user),
+ .mprj_ack_i_user(mprj_ack_i_user),
+ .user_irq(user_irq),
+ .user1_vcc_powergood(mprj_vcc_pwrgood),
+ .user2_vcc_powergood(mprj2_vcc_pwrgood),
+ .user1_vdd_powergood(mprj_vdd_pwrgood),
+ .user2_vdd_powergood(mprj2_vdd_pwrgood)
+ );
+
+ /*--------------------------------------------------*/
+ /* Wrapper module around the user project */
+ /*--------------------------------------------------*/
+
+ user_project_wrapper mprj (
+ `ifdef USE_POWER_PINS
+ .vdda1(vdda1_core), // User area 1 3.3V power
+ .vdda2(vdda2_core), // User area 2 3.3V power
+ .vssa1(vssa1_core), // User area 1 analog ground
+ .vssa2(vssa2_core), // User area 2 analog ground
+ .vccd1(vccd1_core), // User area 1 1.8V power
+ .vccd2(vccd2_core), // User area 2 1.8V power
+ .vssd1(vssd1_core), // User area 1 digital ground
+ .vssd2(vssd2_core), // User area 2 digital ground
+ `endif
+
+ .wb_clk_i(mprj_clock),
+ .wb_rst_i(mprj_reset),
+
+ // Management SoC Wishbone bus (exported)
+ .wbs_cyc_i(mprj_cyc_o_user),
+ .wbs_stb_i(mprj_stb_o_user),
+ .wbs_we_i(mprj_we_o_user),
+ .wbs_sel_i(mprj_sel_o_user),
+ .wbs_adr_i(mprj_adr_o_user),
+ .wbs_dat_i(mprj_dat_o_user),
+ .wbs_ack_o(mprj_ack_i_user),
+ .wbs_dat_o(mprj_dat_i_user),
+
+ // GPIO pad 3-pin interface (plus analog)
+ .io_in (user_io_in),
+ .io_out(user_io_out),
+ .io_oeb(user_io_oeb),
+ .analog_io(user_analog_io),
+
+ // Logic analyzer
+ .la_data_in(la_data_in_user),
+ .la_data_out(la_data_out_user),
+ .la_oenb(la_oenb_user),
+
+ // Independent clock
+ .user_clock2(mprj_clock2),
+
+ // IRQ
+ .user_irq(user_irq_core)
+ );
+
+ /*------------------------------------------*/
+ /* End user project instantiation */
+ /*------------------------------------------*/
+
+ wire [`MPRJ_IO_PADS_1-1:0] gpio_serial_link_1_shifted;
+ wire [`MPRJ_IO_PADS_2-1:0] gpio_serial_link_2_shifted;
+
+ assign gpio_serial_link_1_shifted = {gpio_serial_link_1[`MPRJ_IO_PADS_1-2:0],
+ mprj_io_loader_data_1};
+ // Note that serial_link_2 is backwards compared to serial_link_1, so it
+ // shifts in the other direction.
+ assign gpio_serial_link_2_shifted = {mprj_io_loader_data_2_buf,
+ gpio_serial_link_2[`MPRJ_IO_PADS_2-1:1]};
+
+ // Propagating clock and reset to mitigate timing and fanout issues
+ wire [`MPRJ_IO_PADS_1-1:0] gpio_clock_1;
+ wire [`MPRJ_IO_PADS_2-1:0] gpio_clock_2;
+ wire [`MPRJ_IO_PADS_1-1:0] gpio_resetn_1;
+ wire [`MPRJ_IO_PADS_2-1:0] gpio_resetn_2;
+ wire [`MPRJ_IO_PADS_1-1:0] gpio_load_1;
+ wire [`MPRJ_IO_PADS_2-1:0] gpio_load_2;
+ wire [`MPRJ_IO_PADS_1-1:0] gpio_clock_1_shifted;
+ wire [`MPRJ_IO_PADS_2-1:0] gpio_clock_2_shifted;
+ wire [`MPRJ_IO_PADS_1-1:0] gpio_resetn_1_shifted;
+ wire [`MPRJ_IO_PADS_2-1:0] gpio_resetn_2_shifted;
+ wire [`MPRJ_IO_PADS_1-1:0] gpio_load_1_shifted;
+ wire [`MPRJ_IO_PADS_2-1:0] gpio_load_2_shifted;
+
+ assign gpio_clock_1_shifted = {gpio_clock_1[`MPRJ_IO_PADS_1-2:0],
+ mprj_io_loader_clock};
+ assign gpio_clock_2_shifted = {mprj_io_loader_clock_buf,
+ gpio_clock_2[`MPRJ_IO_PADS_2-1:1]};
+ assign gpio_resetn_1_shifted = {gpio_resetn_1[`MPRJ_IO_PADS_1-2:0],
+ mprj_io_loader_resetn};
+ assign gpio_resetn_2_shifted = {mprj_io_loader_resetn_buf,
+ gpio_resetn_2[`MPRJ_IO_PADS_2-1:1]};
+ assign gpio_load_1_shifted = {gpio_load_1[`MPRJ_IO_PADS_1-2:0],
+ mprj_io_loader_strobe};
+ assign gpio_load_2_shifted = {mprj_io_loader_strobe_buf,
+ gpio_load_2[`MPRJ_IO_PADS_2-1:1]};
+
+ wire [2:0] spi_pll_sel;
+ wire [2:0] spi_pll90_sel;
+ wire [4:0] spi_pll_div;
+ wire [25:0] spi_pll_trim;
+
+ // Clocking control
+
+ caravel_clocking clock_ctrl (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .ext_clk_sel(ext_clk_sel),
+ .ext_clk(clock_core_buf),
+ .pll_clk(pll_clk),
+ .pll_clk90(pll_clk90),
+ .resetb(rstb_l_buf),
+ .sel(spi_pll_sel),
+ .sel2(spi_pll90_sel),
+ .ext_reset(ext_reset), // From housekeeping SPI
+ .core_clk(caravel_clk),
+ .user_clk(caravel_clk2),
+ .resetb_sync(caravel_rstn)
+ );
+
+ // DCO/Digital Locked Loop
+
+ digital_pll pll (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .resetb(rstb_l_buf),
+ .enable(spi_pll_ena),
+ .osc(clock_core_buf),
+ .clockp({pll_clk, pll_clk90}),
+ .div(spi_pll_div),
+ .dco(spi_pll_dco_ena),
+ .ext_trim(spi_pll_trim)
+ );
+
+ // Housekeeping interface
+
+ housekeeping housekeeping (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+
+ .wb_clk_i(caravel_clk),
+ .wb_rstn_i(caravel_rstn),
+
+ .wb_adr_i(mprj_adr_o_core),
+ .wb_dat_i(mprj_dat_o_core),
+ .wb_sel_i(mprj_sel_o_core),
+ .wb_we_i(mprj_we_o_core),
+ .wb_cyc_i(hk_cyc_o),
+ .wb_stb_i(hk_stb_o),
+ .wb_ack_o(hk_ack_i),
+ .wb_dat_o(hk_dat_i),
+
+ .porb(porb_l),
+
+ .pll_ena(spi_pll_ena),
+ .pll_dco_ena(spi_pll_dco_ena),
+ .pll_div(spi_pll_div),
+ .pll_sel(spi_pll_sel),
+ .pll90_sel(spi_pll90_sel),
+ .pll_trim(spi_pll_trim),
+ .pll_bypass(ext_clk_sel),
+
+ .qspi_enabled(qspi_enabled),
+ .uart_enabled(uart_enabled),
+ .spi_enabled(spi_enabled),
+ .debug_mode(debug_mode),
+
+ .ser_tx(ser_tx),
+ .ser_rx(ser_rx),
+
+ .spi_sdi(spi_sdi),
+ .spi_csb(spi_csb),
+ .spi_sck(spi_sck),
+ .spi_sdo(spi_sdo),
+ .spi_sdoenb(spi_sdoenb),
+
+ .debug_in(debug_in),
+ .debug_out(debug_out),
+ .debug_oeb(debug_oeb),
+
+ .irq(irq_spi),
+ .reset(ext_reset),
+
+ .serial_clock(mprj_io_loader_clock),
+ .serial_load(mprj_io_loader_strobe),
+ .serial_resetn(mprj_io_loader_resetn),
+ .serial_data_1(mprj_io_loader_data_1),
+ .serial_data_2(mprj_io_loader_data_2),
+
+ .mgmt_gpio_in(mgmt_io_in_hk),
+ .mgmt_gpio_out(mgmt_io_out_hk),
+ .mgmt_gpio_oeb(mgmt_io_oeb_hk),
+
+ .pwr_ctrl_out(pwr_ctrl_nc), /* Not used in this version */
+
+ .trap(trap),
+
+ .user_clock(caravel_clk2),
+
+ .mask_rev_in(mask_rev),
+
+ .spimemio_flash_csb(flash_csb_core),
+ .spimemio_flash_clk(flash_clk_core),
+ .spimemio_flash_io0_oeb(flash_io0_oeb_core),
+ .spimemio_flash_io1_oeb(flash_io1_oeb_core),
+ .spimemio_flash_io2_oeb(flash_io2_oeb_core),
+ .spimemio_flash_io3_oeb(flash_io3_oeb_core),
+ .spimemio_flash_io0_do(flash_io0_do_core),
+ .spimemio_flash_io1_do(flash_io1_do_core),
+ .spimemio_flash_io2_do(flash_io2_do_core),
+ .spimemio_flash_io3_do(flash_io3_do_core),
+ .spimemio_flash_io0_di(flash_io0_di_core),
+ .spimemio_flash_io1_di(flash_io1_di_core),
+ .spimemio_flash_io2_di(flash_io2_di_core),
+ .spimemio_flash_io3_di(flash_io3_di_core),
+
+ .pad_flash_csb(flash_csb_frame),
+ .pad_flash_csb_oeb(flash_csb_oeb),
+ .pad_flash_clk(flash_clk_frame),
+ .pad_flash_clk_oeb(flash_clk_oeb),
+ .pad_flash_io0_oeb(flash_io0_oeb),
+ .pad_flash_io1_oeb(flash_io1_oeb),
+ .pad_flash_io0_ieb(flash_io0_ieb),
+ .pad_flash_io1_ieb(flash_io1_ieb),
+ .pad_flash_io0_do(flash_io0_do),
+ .pad_flash_io1_do(flash_io1_do),
+ .pad_flash_io0_di(flash_io0_di_buf),
+ .pad_flash_io1_di(flash_io1_di_buf),
+
+`ifdef USE_SRAM_RO_INTERFACE
+ .sram_ro_clk(hkspi_sram_clk),
+ .sram_ro_csb(hkspi_sram_csb),
+ .sram_ro_addr(hkspi_sram_addr),
+ .sram_ro_data(hkspi_sram_data),
+`endif
+
+ .usr1_vcc_pwrgood(mprj_vcc_pwrgood),
+ .usr2_vcc_pwrgood(mprj2_vcc_pwrgood),
+ .usr1_vdd_pwrgood(mprj_vdd_pwrgood),
+ .usr2_vdd_pwrgood(mprj2_vdd_pwrgood)
+ );
+
+ /* GPIO defaults (via programmed) */
+ wire [`MPRJ_IO_PADS*13-1:0] gpio_defaults;
+
+ /* Fixed defaults for the first 5 GPIO pins */
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(13'h1803)
+ ) gpio_defaults_block_0 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[12:0])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(13'h1803)
+ ) gpio_defaults_block_1 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[25:13])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(13'h0403)
+ ) gpio_defaults_block_2 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[38:26])
+ );
+
+ // CSB pin is set as an internal pull-up
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(13'h0801)
+ ) gpio_defaults_block_3 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[51:39])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(13'h0403)
+ ) gpio_defaults_block_4 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[64:52])
+ );
+
+ /* Via-programmable defaults for the rest of the GPIO pins */
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_5_INIT)
+ ) gpio_defaults_block_5 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[77:65])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_6_INIT)
+ ) gpio_defaults_block_6 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[90:78])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_7_INIT)
+ ) gpio_defaults_block_7 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[103:91])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_8_INIT)
+ ) gpio_defaults_block_8 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[116:104])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_9_INIT)
+ ) gpio_defaults_block_9 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[129:117])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_10_INIT)
+ ) gpio_defaults_block_10 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[142:130])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_11_INIT)
+ ) gpio_defaults_block_11 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[155:143])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_12_INIT)
+ ) gpio_defaults_block_12 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[168:156])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_13_INIT)
+ ) gpio_defaults_block_13 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[181:169])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_14_INIT)
+ ) gpio_defaults_block_14 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[194:182])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_15_INIT)
+ ) gpio_defaults_block_15 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[207:195])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_16_INIT)
+ ) gpio_defaults_block_16 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[220:208])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_17_INIT)
+ ) gpio_defaults_block_17 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[233:221])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_18_INIT)
+ ) gpio_defaults_block_18 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[246:234])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_19_INIT)
+ ) gpio_defaults_block_19 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[259:247])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_20_INIT)
+ ) gpio_defaults_block_20 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[272:260])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_21_INIT)
+ ) gpio_defaults_block_21 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[285:273])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_22_INIT)
+ ) gpio_defaults_block_22 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[298:286])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_23_INIT)
+ ) gpio_defaults_block_23 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[311:299])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_24_INIT)
+ ) gpio_defaults_block_24 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[324:312])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_25_INIT)
+ ) gpio_defaults_block_25 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[337:325])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_26_INIT)
+ ) gpio_defaults_block_26 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[350:338])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_27_INIT)
+ ) gpio_defaults_block_27 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[363:351])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_28_INIT)
+ ) gpio_defaults_block_28 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[376:364])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_29_INIT)
+ ) gpio_defaults_block_29 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[389:377])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_30_INIT)
+ ) gpio_defaults_block_30 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[402:390])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_31_INIT)
+ ) gpio_defaults_block_31 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[415:403])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_32_INIT)
+ ) gpio_defaults_block_32 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[428:416])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_33_INIT)
+ ) gpio_defaults_block_33 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[441:429])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_34_INIT)
+ ) gpio_defaults_block_34 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[454:442])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_35_INIT)
+ ) gpio_defaults_block_35 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[467:455])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_36_INIT)
+ ) gpio_defaults_block_36 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[480:468])
+ );
+
+ gpio_defaults_block #(
+ .GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_37_INIT)
+ ) gpio_defaults_block_37 (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .gpio_defaults(gpio_defaults[493:481])
+ );
+
+ // Each control block sits next to an I/O pad in the user area.
+ // It gets input through a serial chain from the previous control
+ // block and passes it to the next control block. Due to the nature
+ // of the shift register, bits are presented in reverse, as the first
+ // bit in ends up as the last bit of the last I/O pad control block.
+
+ // There are two types of block; the first two and the last two
+ // are configured to be full bidirectional under control of the
+ // management Soc (JTAG and SDO for the first two; flash_io2 and
+ // flash_io3 for the last two). The rest are configured to be default
+ // (input). Note that the first two and last two are the ones closest
+ // to the management SoC on either side, which minimizes the wire length
+ // of the extra signals those pads need.
+
+ /* First two GPIOs (JTAG and SDO) */
+
+ gpio_control_block gpio_control_bidir_1 [1:0] (
+ `ifdef USE_POWER_PINS
+ .vccd(vccd_core),
+ .vssd(vssd_core),
+ .vccd1(vccd1_core),
+ .vssd1(vssd1_core),
+ `endif
+
+ .gpio_defaults(gpio_defaults[25:0]),
+
+ // Management Soc-facing signals
+
+ .resetn(gpio_resetn_1_shifted[1:0]),
+ .serial_clock(gpio_clock_1_shifted[1:0]),
+ .serial_load(gpio_load_1_shifted[1:0]),
+
+ .resetn_out(gpio_resetn_1[1:0]),
+ .serial_clock_out(gpio_clock_1[1:0]),
+ .serial_load_out(gpio_load_1[1:0]),
+
+ .mgmt_gpio_in(mgmt_io_in[1:0]),
+ .mgmt_gpio_out(mgmt_io_out[1:0]),
+ .mgmt_gpio_oeb(mgmt_io_oeb[1:0]),
+
+ .one(mprj_io_one[1:0]),
+ .zero(),
+
+ // Serial data chain for pad configuration
+ .serial_data_in(gpio_serial_link_1_shifted[1:0]),
+ .serial_data_out(gpio_serial_link_1[1:0]),
+
+ // User-facing signals
+ .user_gpio_out(user_io_out[1:0]),
+ .user_gpio_oeb(user_io_oeb[1:0]),
+ .user_gpio_in(user_io_in[1:0]),
+
+ // Pad-facing signals (Pad GPIOv2)
+ .pad_gpio_inenb(mprj_io_inp_dis[1:0]),
+ .pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[1:0]),
+ .pad_gpio_vtrip_sel(mprj_io_vtrip_sel[1:0]),
+ .pad_gpio_slow_sel(mprj_io_slow_sel[1:0]),
+ .pad_gpio_holdover(mprj_io_holdover[1:0]),
+ .pad_gpio_ana_en(mprj_io_analog_en[1:0]),
+ .pad_gpio_ana_sel(mprj_io_analog_sel[1:0]),
+ .pad_gpio_ana_pol(mprj_io_analog_pol[1:0]),
+ .pad_gpio_dm(mprj_io_dm[5:0]),
+ .pad_gpio_outenb(mprj_io_oeb[1:0]),
+ .pad_gpio_out(mprj_io_out[1:0]),
+ .pad_gpio_in(mprj_io_in[1:0])
+ );
+
+ /* Section 1 GPIOs (GPIO 2 to 7) that start up under management control */
+
+ gpio_control_block gpio_control_in_1a [5:0] (
+ `ifdef USE_POWER_PINS
+ .vccd(vccd_core),
+ .vssd(vssd_core),
+ .vccd1(vccd1_core),
+ .vssd1(vssd1_core),
+ `endif
+
+ .gpio_defaults(gpio_defaults[103:26]),
+
+ // Management Soc-facing signals
+
+ .resetn(gpio_resetn_1_shifted[7:2]),
+ .serial_clock(gpio_clock_1_shifted[7:2]),
+ .serial_load(gpio_load_1_shifted[7:2]),
+
+ .resetn_out(gpio_resetn_1[7:2]),
+ .serial_clock_out(gpio_clock_1[7:2]),
+ .serial_load_out(gpio_load_1[7:2]),
+
+ .mgmt_gpio_in(mgmt_io_in[7:2]),
+ .mgmt_gpio_out(mgmt_io_out[7:2]),
+ .mgmt_gpio_oeb(mprj_io_one[7:2]),
+
+ .one(mprj_io_one[7:2]),
+ .zero(),
+
+ // Serial data chain for pad configuration
+ .serial_data_in(gpio_serial_link_1_shifted[7:2]),
+ .serial_data_out(gpio_serial_link_1[7:2]),
+
+ // User-facing signals
+ .user_gpio_out(user_io_out[7:2]),
+ .user_gpio_oeb(user_io_oeb[7:2]),
+ .user_gpio_in(user_io_in[7:2]),
+
+ // Pad-facing signals (Pad GPIOv2)
+ .pad_gpio_inenb(mprj_io_inp_dis[7:2]),
+ .pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[7:2]),
+ .pad_gpio_vtrip_sel(mprj_io_vtrip_sel[7:2]),
+ .pad_gpio_slow_sel(mprj_io_slow_sel[7:2]),
+ .pad_gpio_holdover(mprj_io_holdover[7:2]),
+ .pad_gpio_ana_en(mprj_io_analog_en[7:2]),
+ .pad_gpio_ana_sel(mprj_io_analog_sel[7:2]),
+ .pad_gpio_ana_pol(mprj_io_analog_pol[7:2]),
+ .pad_gpio_dm(mprj_io_dm[23:6]),
+ .pad_gpio_outenb(mprj_io_oeb[7:2]),
+ .pad_gpio_out(mprj_io_out[7:2]),
+ .pad_gpio_in(mprj_io_in[7:2])
+ );
+
+ /* Section 1 GPIOs (GPIO 8 to 18) */
+
+ gpio_control_block gpio_control_in_1 [`MPRJ_IO_PADS_1-9:0] (
+ `ifdef USE_POWER_PINS
+ .vccd(vccd_core),
+ .vssd(vssd_core),
+ .vccd1(vccd1_core),
+ .vssd1(vssd1_core),
+ `endif
+
+ .gpio_defaults(gpio_defaults[(`MPRJ_IO_PADS_1*13-1):104]),
+
+ // Management Soc-facing signals
+
+ .resetn(gpio_resetn_1_shifted[(`MPRJ_IO_PADS_1-1):8]),
+ .serial_clock(gpio_clock_1_shifted[(`MPRJ_IO_PADS_1-1):8]),
+ .serial_load(gpio_load_1_shifted[(`MPRJ_IO_PADS_1-1):8]),
+
+ .resetn_out(gpio_resetn_1[(`MPRJ_IO_PADS_1-1):8]),
+ .serial_clock_out(gpio_clock_1[(`MPRJ_IO_PADS_1-1):8]),
+ .serial_load_out(gpio_load_1[(`MPRJ_IO_PADS_1-1):8]),
+
+ .mgmt_gpio_in(mgmt_io_in[(`MPRJ_IO_PADS_1-1):8]),
+ .mgmt_gpio_out(mgmt_io_out[(`MPRJ_IO_PADS_1-1):8]),
+ .mgmt_gpio_oeb(mprj_io_one[(`MPRJ_IO_PADS_1-1):8]),
+
+ .one(mprj_io_one[(`MPRJ_IO_PADS_1-1):8]),
+ .zero(),
+
+ // Serial data chain for pad configuration
+ .serial_data_in(gpio_serial_link_1_shifted[(`MPRJ_IO_PADS_1-1):8]),
+ .serial_data_out(gpio_serial_link_1[(`MPRJ_IO_PADS_1-1):8]),
+
+ // User-facing signals
+ .user_gpio_out(user_io_out[(`MPRJ_IO_PADS_1-1):8]),
+ .user_gpio_oeb(user_io_oeb[(`MPRJ_IO_PADS_1-1):8]),
+ .user_gpio_in(user_io_in[(`MPRJ_IO_PADS_1-1):8]),
+
+ // Pad-facing signals (Pad GPIOv2)
+ .pad_gpio_inenb(mprj_io_inp_dis[(`MPRJ_IO_PADS_1-1):8]),
+ .pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[(`MPRJ_IO_PADS_1-1):8]),
+ .pad_gpio_vtrip_sel(mprj_io_vtrip_sel[(`MPRJ_IO_PADS_1-1):8]),
+ .pad_gpio_slow_sel(mprj_io_slow_sel[(`MPRJ_IO_PADS_1-1):8]),
+ .pad_gpio_holdover(mprj_io_holdover[(`MPRJ_IO_PADS_1-1):8]),
+ .pad_gpio_ana_en(mprj_io_analog_en[(`MPRJ_IO_PADS_1-1):8]),
+ .pad_gpio_ana_sel(mprj_io_analog_sel[(`MPRJ_IO_PADS_1-1):8]),
+ .pad_gpio_ana_pol(mprj_io_analog_pol[(`MPRJ_IO_PADS_1-1):8]),
+ .pad_gpio_dm(mprj_io_dm[(`MPRJ_IO_PADS_1*3-1):24]),
+ .pad_gpio_outenb(mprj_io_oeb[(`MPRJ_IO_PADS_1-1):8]),
+ .pad_gpio_out(mprj_io_out[(`MPRJ_IO_PADS_1-1):8]),
+ .pad_gpio_in(mprj_io_in[(`MPRJ_IO_PADS_1-1):8])
+ );
+
+ /* Last three GPIOs (spi_sdo, flash_io2, and flash_io3) */
+
+ gpio_control_block gpio_control_bidir_2 [2:0] (
+ `ifdef USE_POWER_PINS
+ .vccd(vccd_core),
+ .vssd(vssd_core),
+ .vccd1(vccd1_core),
+ .vssd1(vssd1_core),
+ `endif
+
+ .gpio_defaults(gpio_defaults[(`MPRJ_IO_PADS*13-1):(`MPRJ_IO_PADS*13-39)]),
+
+ // Management Soc-facing signals
+
+ .resetn(gpio_resetn_2_shifted[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+ .serial_clock(gpio_clock_2_shifted[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+ .serial_load(gpio_load_2_shifted[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+
+ .resetn_out(gpio_resetn_2[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+ .serial_clock_out(gpio_clock_2[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+ .serial_load_out(gpio_load_2[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+
+ .mgmt_gpio_in(mgmt_io_in[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+ .mgmt_gpio_out(mgmt_io_out[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+ .mgmt_gpio_oeb(mgmt_io_oeb[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+
+ .one(mprj_io_one[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+ .zero(),
+
+ // Serial data chain for pad configuration
+ .serial_data_in(gpio_serial_link_2_shifted[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+ .serial_data_out(gpio_serial_link_2[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-3)]),
+
+ // User-facing signals
+ .user_gpio_out(user_io_out[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+ .user_gpio_oeb(user_io_oeb[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+ .user_gpio_in(user_io_in[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+
+ // Pad-facing signals (Pad GPIOv2)
+ .pad_gpio_inenb(mprj_io_inp_dis[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+ .pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+ .pad_gpio_vtrip_sel(mprj_io_vtrip_sel[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+ .pad_gpio_slow_sel(mprj_io_slow_sel[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+ .pad_gpio_holdover(mprj_io_holdover[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+ .pad_gpio_ana_en(mprj_io_analog_en[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+ .pad_gpio_ana_sel(mprj_io_analog_sel[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+ .pad_gpio_ana_pol(mprj_io_analog_pol[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+ .pad_gpio_dm(mprj_io_dm[(`MPRJ_IO_PADS*3-1):(`MPRJ_IO_PADS*3-9)]),
+ .pad_gpio_outenb(mprj_io_oeb[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+ .pad_gpio_out(mprj_io_out[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)]),
+ .pad_gpio_in(mprj_io_in[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-3)])
+ );
+
+ /* Section 2 GPIOs (GPIO 19 to 34) */
+
+ gpio_control_block gpio_control_in_2 [`MPRJ_IO_PADS_2-4:0] (
+ `ifdef USE_POWER_PINS
+ .vccd(vccd_core),
+ .vssd(vssd_core),
+ .vccd1(vccd1_core),
+ .vssd1(vssd1_core),
+ `endif
+
+ .gpio_defaults(gpio_defaults[(`MPRJ_IO_PADS*13-40):(`MPRJ_IO_PADS_1*13)]),
+
+ // Management Soc-facing signals
+
+ .resetn(gpio_resetn_2_shifted[(`MPRJ_IO_PADS_2-4):0]),
+ .serial_clock(gpio_clock_2_shifted[(`MPRJ_IO_PADS_2-4):0]),
+ .serial_load(gpio_load_2_shifted[(`MPRJ_IO_PADS_2-4):0]),
+
+ .resetn_out(gpio_resetn_2[(`MPRJ_IO_PADS_2-4):0]),
+ .serial_clock_out(gpio_clock_2[(`MPRJ_IO_PADS_2-4):0]),
+ .serial_load_out(gpio_load_2[(`MPRJ_IO_PADS_2-4):0]),
+
+ .mgmt_gpio_in(mgmt_io_in[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+ .mgmt_gpio_out(mgmt_io_out[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+ .mgmt_gpio_oeb(mprj_io_one[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+
+
+ .one(mprj_io_one[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+ .zero(),
+
+ // Serial data chain for pad configuration
+ .serial_data_in(gpio_serial_link_2_shifted[(`MPRJ_IO_PADS_2-4):0]),
+ .serial_data_out(gpio_serial_link_2[(`MPRJ_IO_PADS_2-4):0]),
+
+ // User-facing signals
+ .user_gpio_out(user_io_out[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+ .user_gpio_oeb(user_io_oeb[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+ .user_gpio_in(user_io_in[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+
+ // Pad-facing signals (Pad GPIOv2)
+ .pad_gpio_inenb(mprj_io_inp_dis[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_vtrip_sel(mprj_io_vtrip_sel[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_slow_sel(mprj_io_slow_sel[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_holdover(mprj_io_holdover[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_ana_en(mprj_io_analog_en[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_ana_sel(mprj_io_analog_sel[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_ana_pol(mprj_io_analog_pol[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_dm(mprj_io_dm[(`MPRJ_IO_PADS*3-10):(`MPRJ_IO_PADS_1*3)]),
+ .pad_gpio_outenb(mprj_io_oeb[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_out(mprj_io_out[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_in(mprj_io_in[(`MPRJ_IO_PADS-4):(`MPRJ_IO_PADS_1)])
+ );
+
+ user_id_programming #(
+ .USER_PROJECT_ID(USER_PROJECT_ID)
+ ) user_id_value (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .mask_rev(mask_rev)
+ );
+
+ // Power-on-reset circuit
+ simple_por por (
+ `ifdef USE_POWER_PINS
+ .vdd3v3(vddio_core),
+ .vdd1v8(vccd_core),
+ .vss3v3(vssio_core),
+ .vss1v8(vssd_core),
+ `endif
+ .porb_h(porb_h),
+ .porb_l(porb_l),
+ .por_l(por_l)
+ );
+
+ // XRES (chip input pin reset) reset level converter
+ xres_buf rstb_level (
+ `ifdef USE_POWER_PINS
+ .VPWR(vddio_core),
+ .LVPWR(vccd_core),
+ .LVGND(vssd_core),
+ .VGND(vssio_core),
+ `endif
+ .A(rstb_h),
+ .X(rstb_l)
+ );
+
+ /* Spare logic for metal mask fixes */
+ // `define NUM_SPARE_BLOCKS (`MPRJ_IO_PADS+4)
+ `define NUM_SPARE_BLOCKS 4
+
+ wire [(27*`NUM_SPARE_BLOCKS)-1:0] spare_xz_nc;
+ wire [(4*`NUM_SPARE_BLOCKS)-1:0] spare_xi_nc;
+ wire [(1*`NUM_SPARE_BLOCKS)-1:0] spare_xib_nc;
+ wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xna_nc;
+ wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xno_nc;
+ wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xmx_nc;
+ wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xfq_nc;
+ wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xfqn_nc;
+
+ // Four spare logic blocks above the processor and one per GPIO
+ // control block.
+ spare_logic_block spare_logic [`NUM_SPARE_BLOCKS-1:0] (
+ `ifdef USE_POWER_PINS
+ .vccd(vccd_core),
+ .vssd(vssd_core),
+ `endif
+ .spare_xz(spare_xz_nc),
+ .spare_xi(spare_xi_nc),
+ .spare_xib(spare_xib_nc),
+ .spare_xna(spare_xna_nc),
+ .spare_xno(spare_xno_nc),
+ .spare_xmx(spare_xmx_nc),
+ .spare_xfq(spare_xfq_nc),
+ .spare_xfqn(spare_xfqn_nc)
+ );
+
+ `ifdef TOP_ROUTING
+ caravel_power_routing caravel_power_routing();
+ copyright_block copyright_block();
+ caravel_logo caravel_logo();
+ caravel_motto caravel_motto();
+ open_source open_source();
+ user_id_textblock user_id_textblock();
+ `endif
+
+endmodule
+// `default_nettype wire
