| 2022-06-03 12:16:39 - [INFO] - {{Project Git Info}} Repository: https://github.com/gitercn/riscduino_qcore_folk.git | Branch: main | Commit: aa75e446fa7757dd79717f376e848a4d369a48b5 |
| 2022-06-03 12:16:39 - [INFO] - {{EXTRACTING FILES}} Extracting compressed files in: riscduino_qcore_folk |
| 2022-06-03 12:16:44 - [INFO] - {{Project Type Info}} digital |
| 2022-06-03 12:16:44 - [INFO] - {{Project GDS Info}} user_project_wrapper: 0507457456d10a63886f8f85f5ef273429ebec32 |
| 2022-06-03 12:16:44 - [INFO] - {{Tools Info}} KLayout: v0.27.8 | Magic: v8.3.274 |
| 2022-06-03 12:16:44 - [INFO] - {{PDKs Info}} Open PDKs: 27ecf1c16911f7dd4428ffab96f62c1fb876ea70 | Skywater PDK: c094b6e83a4f9298e47f696ec5a7fd53535ec5eb |
| 2022-06-03 12:16:44 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in 'riscduino_qcore_folk/jobs/mpw_precheck/41322373-5695-4474-8666-baf2b4c97e4c/logs' |
| 2022-06-03 12:16:44 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: [License, Makefile, Default, Documentation, Consistency, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea] |
| 2022-06-03 12:16:44 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 13: License |
| 2022-06-03 12:16:45 - [INFO] - An approved LICENSE (Apache-2.0) was found in riscduino_qcore_folk. |
| 2022-06-03 12:16:45 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root. |
| 2022-06-03 12:16:46 - [INFO] - An approved LICENSE (Apache-2.0) was found in riscduino_qcore_folk. |
| 2022-06-03 12:16:46 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules |
| 2022-06-03 12:16:48 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino_qcore_folk/verilog/dv/bfm/usb_device/core/usb1d_ctrl.v): 'utf-8' codec can't decode byte 0x96 in position 5130: invalid start byte |
| 2022-06-03 12:16:48 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino_qcore_folk/verilog/dv/model/mt48lc8m8a2.v): 'utf-8' codec can't decode byte 0xa9 in position 1830: invalid start byte |
| 2022-06-03 12:16:48 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino_qcore_folk/verilog/dv/user_uart/.user_uart.c.un~): 'utf-8' codec can't decode byte 0x9f in position 3: invalid start byte |
| 2022-06-03 12:16:48 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 483 non-compliant file(s) with the SPDX Standard. |
| 2022-06-03 12:16:48 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['riscduino_qcore_folk/Makefile', 'riscduino_qcore_folk/run_regress', 'riscduino_qcore_folk/gds/.magicrc', 'riscduino_qcore_folk/hacks/patch/pdngen.patch', 'riscduino_qcore_folk/hacks/patch/resizer.patch', 'riscduino_qcore_folk/hacks/src/OpenROAD/PdnGen.tcl', 'riscduino_qcore_folk/hacks/src/OpenROAD/Resizer.cc', 'riscduino_qcore_folk/hacks/src/OpenSTA/network/ConcreteNetwork.cc', 'riscduino_qcore_folk/hacks/src/OpenSTA/tcl/NetworkEdit.tcl', 'riscduino_qcore_folk/hacks/src/OpenSTA/tcl/Sta.tcl', 'riscduino_qcore_folk/hacks/src/openlane/io_place.py', 'riscduino_qcore_folk/hacks/src/openlane/synth.tcl', 'riscduino_qcore_folk/hacks/src/openlane/synth_top.tcl', 'riscduino_qcore_folk/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib', 'riscduino_qcore_folk/openlane/Makefile'] |
| 2022-06-03 12:16:48 - [INFO] - For the full SPDX compliance report check: riscduino_qcore_folk/jobs/mpw_precheck/41322373-5695-4474-8666-baf2b4c97e4c/logs/spdx_compliance_report.log |
| 2022-06-03 12:16:48 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 13: Makefile |
| 2022-06-03 12:16:48 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid. |
| 2022-06-03 12:16:48 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 13: Default |
| 2022-06-03 12:16:48 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md' |
| 2022-06-03 12:16:52 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds' |
| 2022-06-03 12:16:52 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 13: Documentation |
| 2022-06-03 12:16:52 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate. |
| 2022-06-03 12:16:52 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 13: Consistency |
| 2022-06-03 12:16:59 - [INFO] - HIERARCHY CHECK PASSED: Module user_project_wrapper is instantiated in caravel. |
| 2022-06-03 12:16:59 - [INFO] - COMPLEXITY CHECK PASSED: Netlist caravel contains at least 8 instances (90 instances). |
| 2022-06-03 12:16:59 - [INFO] - MODELING CHECK PASSED: Netlist caravel is structural. |
| 2022-06-03 12:16:59 - [INFO] - SUBMODULE HOOKS CHECK PASSED: All module ports for user_project_wrapper are correctly connected in the top level netlist caravel. |
| 2022-06-03 12:16:59 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in caravel are connected to power |
| 2022-06-03 12:16:59 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravel netlist passed all consistency checks. |
| 2022-06-03 12:16:59 - [INFO] - PORTS CHECK PASSED: Netlist user_project_wrapper ports match the golden wrapper ports |
| 2022-06-03 12:16:59 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_project_wrapper contains at least 1 instances (15 instances). |
| 2022-06-03 12:16:59 - [INFO] - MODELING CHECK PASSED: Netlist user_project_wrapper is structural. |
| 2022-06-03 12:16:59 - [INFO] - LAYOUT CHECK PASSED: The GDS layout for user_project_wrapper matches the provided structural netlist. |
| 2022-06-03 12:16:59 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in user_project_wrapper are connected to power |
| 2022-06-03 12:16:59 - [INFO] - PORT TYPES CHECK PASSED: Netlist user_project_wrapper port types match the golden wrapper port types. |
| 2022-06-03 12:16:59 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} user_project_wrapper netlist passed all consistency checks. |
| 2022-06-03 12:16:59 - [INFO] - {{CONSISTENCY CHECK PASSED}} The user netlist and the top netlist are valid. |
| 2022-06-03 12:16:59 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 13: XOR |
| 2022-06-03 12:19:47 - [INFO] - {{XOR CHECK UPDATE}} Total XOR differences: 0, for more details view riscduino_qcore_folk/jobs/mpw_precheck/41322373-5695-4474-8666-baf2b4c97e4c/outputs/user_project_wrapper.xor.gds |
| 2022-06-03 12:19:47 - [INFO] - {{XOR CHECK PASSED}} The GDS file has no XOR violations. |
| 2022-06-03 12:19:47 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 13: Magic DRC |
| 2022-06-03 12:30:34 - [INFO] - 0 DRC violations |
| 2022-06-03 12:30:34 - [INFO] - {{MAGIC DRC CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations. |
| 2022-06-03 12:30:34 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 13: Klayout FEOL |
| 2022-06-03 12:32:58 - [INFO] - No DRC Violations found |
| 2022-06-03 12:32:58 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations. |
| 2022-06-03 12:32:58 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 13: Klayout BEOL |
| 2022-06-03 12:52:17 - [INFO] - No DRC Violations found |
| 2022-06-03 12:52:17 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations. |
| 2022-06-03 12:52:17 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 13: Klayout Offgrid |
| 2022-06-03 12:55:54 - [INFO] - No DRC Violations found |
| 2022-06-03 12:55:54 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations. |
| 2022-06-03 12:55:54 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 13: Klayout Metal Minimum Clear Area Density |
| 2022-06-03 12:57:24 - [INFO] - No DRC Violations found |
| 2022-06-03 12:57:24 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations. |
| 2022-06-03 12:57:24 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 13: Klayout Pin Label Purposes Overlapping Drawing |
| 2022-06-03 12:57:57 - [INFO] - No DRC Violations found |
| 2022-06-03 12:57:57 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations. |
| 2022-06-03 12:57:57 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 13: Klayout ZeroArea |
| 2022-06-03 12:58:12 - [INFO] - No DRC Violations found |
| 2022-06-03 12:58:12 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations. |
| 2022-06-03 12:58:12 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in 'riscduino_qcore_folk/jobs/mpw_precheck/41322373-5695-4474-8666-baf2b4c97e4c/logs' |
| 2022-06-03 12:58:12 - [INFO] - {{SUCCESS}} All Checks Passed !!! |
