first commit
diff --git a/LICENSE b/LICENSE
new file mode 100644
index 0000000..261eeb9
--- /dev/null
+++ b/LICENSE
@@ -0,0 +1,201 @@
+ Apache License
+ Version 2.0, January 2004
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+
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diff --git a/Makefile b/Makefile
new file mode 100644
index 0000000..3cc9ffd
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,141 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+PDK_ROOT?=/usr/local/share/pdk/sky130A
+INPUT_DIRECTORY?=/home/krishna/Strong_Arm_MPW6
+CARAVEL_ROOT?=/home/krishna/caravel_user_project_analog
+PRECHECK_ROOT?=/home/krishna/mpw_precheck
+SIM ?= RTL
+
+# Install lite version of caravel, (1): caravel-lite, (0): caravel
+CARAVEL_LITE?=1
+
+ifeq ($(CARAVEL_LITE),1)
+ CARAVEL_NAME := caravel-lite
+ CARAVEL_REPO := https://github.com/efabless/caravel-lite
+ CARAVEL_TAG := 'mpw-5a'
+else
+ CARAVEL_NAME := caravel
+ CARAVEL_REPO := https://github.com/efabless/caravel
+ CARAVEL_TAG := 'mpw-5a'
+endif
+
+# Include Caravel Makefile Targets
+.PHONY: % : check-caravel
+%:
+ export CARAVEL_ROOT=$(CARAVEL_ROOT) && $(MAKE) -f $(CARAVEL_ROOT)/Makefile $@
+
+# Verify Target for running simulations
+.PHONY: verify
+verify:
+ cd ./verilog/dv/ && \
+ export SIM=${SIM} && \
+ $(MAKE) -j$(THREADS)
+
+# Install DV setup
+.PHONY: simenv
+simenv:
+ docker pull efabless/dv_setup:latest
+
+PATTERNS=$(shell cd verilog/dv && find * -maxdepth 0 -type d)
+DV_PATTERNS = $(foreach dv, $(PATTERNS), verify-$(dv))
+TARGET_PATH=$(shell pwd)
+VERIFY_COMMAND="cd ${TARGET_PATH}/verilog/dv/$* && export SIM=${SIM} && make"
+$(DV_PATTERNS): verify-% : ./verilog/dv/%
+ docker run -v ${TARGET_PATH}:${TARGET_PATH} -v ${PDK_ROOT}:${PDK_ROOT} \
+ -v ${CARAVEL_ROOT}:${CARAVEL_ROOT} \
+ -e TARGET_PATH=${TARGET_PATH} -e PDK_ROOT=${PDK_ROOT} \
+ -e CARAVEL_ROOT=${CARAVEL_ROOT} \
+ -u $(id -u $$USER):$(id -g $$USER) efabless/dv_setup:latest \
+ sh -c $(VERIFY_COMMAND)
+
+# Openlane Makefile Targets
+BLOCKS = $(shell cd openlane && find * -maxdepth 0 -type d)
+.PHONY: $(BLOCKS)
+$(BLOCKS): %:
+ cd openlane && $(MAKE) $*
+
+# Install caravel
+.PHONY: install
+install:
+ @echo "Installing $(CARAVEL_NAME).."
+ @git clone -b $(CARAVEL_TAG) $(CARAVEL_REPO) $(CARAVEL_ROOT)
+
+# Create symbolic links to caravel's main files
+.PHONY: simlink
+simlink: check-caravel
+### Symbolic links relative path to $CARAVEL_ROOT
+ $(eval MAKEFILE_PATH := $(shell realpath --relative-to=openlane $(CARAVEL_ROOT)/openlane/Makefile))
+ mkdir -p openlane
+ cd openlane &&\
+ ln -sf $(MAKEFILE_PATH) Makefile
+
+# Update Caravel
+.PHONY: update_caravel
+update_caravel: check-caravel
+ cd $(CARAVEL_ROOT)/ && git checkout $(CARAVEL_TAG) && git pull
+
+# Uninstall Caravel
+.PHONY: uninstall
+uninstall:
+ rm -rf $(CARAVEL_ROOT)
+
+# Install Openlane
+.PHONY: openlane
+openlane:
+ cd openlane && $(MAKE) openlane
+
+# Install Pre-check
+# Default installs to the user home directory, override by "export PRECHECK_ROOT=<precheck-installation-path>"
+.PHONY: precheck
+precheck:
+ @git clone --depth=1 --branch mpw-5a https://github.com/efabless/mpw_precheck.git $(PRECHECK_ROOT)
+ @docker pull efabless/mpw_precheck:latest
+
+.PHONY: run-precheck
+run-precheck: check-pdk check-precheck
+ $(eval INPUT_DIRECTORY := $(shell pwd))
+ cd $(PRECHECK_ROOT) && \
+ docker run -v $(PRECHECK_ROOT):$(PRECHECK_ROOT) -v $(INPUT_DIRECTORY):$(INPUT_DIRECTORY) -v $(PDK_ROOT):$(PDK_ROOT) -e INPUT_DIRECTORY=$(INPUT_DIRECTORY) -e PDK_ROOT=$(PDK_ROOT) \
+ -u $(shell id -u $(USER)):$(shell id -g $(USER)) efabless/mpw_precheck:latest bash -c "cd $(PRECHECK_ROOT) ; python3 mpw_precheck.py --input_directory $(INPUT_DIRECTORY) --pdk_root $(PDK_ROOT)"
+
+# Clean
+.PHONY: clean
+clean:
+ cd ./verilog/dv/ && \
+ $(MAKE) -j$(THREADS) clean
+
+check-caravel:
+ @if [ ! -d "$(CARAVEL_ROOT)" ]; then \
+ echo "Caravel Root: "$(CARAVEL_ROOT)" doesn't exists, please export the correct path before running make. "; \
+ exit 1; \
+ fi
+
+check-precheck:
+ @if [ ! -d "$(PRECHECK_ROOT)" ]; then \
+ echo "Pre-check Root: "$(PRECHECK_ROOT)" doesn't exists, please export the correct path before running make. "; \
+ exit 1; \
+ fi
+
+check-pdk:
+ @if [ ! -d "$(PDK_ROOT)" ]; then \
+ echo "PDK Root: "$(PDK_ROOT)" doesn't exists, please export the correct path before running make. "; \
+ exit 1; \
+ fi
+
+.PHONY: help
+help:
+ cd $(CARAVEL_ROOT) && $(MAKE) help
+ @$(MAKE) -pRrq -f $(lastword $(MAKEFILE_LIST)) : 2>/dev/null | awk -v RS= -F: '/^# File/,/^# Finished Make data base/ {if ($$1 !~ "^[#.]") {print $$1}}' | sort | egrep -v -e '^[^[:alnum:]]' -e '^$@$$'
diff --git a/README.md b/README.md
new file mode 100644
index 0000000..17fac8e
--- /dev/null
+++ b/README.md
@@ -0,0 +1,14 @@
+# CMOS dynamic Comparator
+This project is the implementation of a optimised strong arm latch using Skywater 130nm technology.
+The purpose of this project is to test the open source tools provided with the PDK and to go through all the steps of the analog design flow.
+
+## CMOS Comparator
+The schematic of the comparator test bench was deisgned as follows :
+
+
+
+
+## Simulation
+We simulated the comparator with reference at the negative input and a pulse at the positive input. The output is a digital signal that triggers at every clock pulse depending on the input amplitude.
+
+
diff --git a/docs/Makefile b/docs/Makefile
new file mode 100644
index 0000000..c715218
--- /dev/null
+++ b/docs/Makefile
@@ -0,0 +1,37 @@
+
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+# Minimal makefile for Sphinx documentation
+#
+
+# You can set these variables from the command line, and also
+# from the environment for the first two.
+SPHINXOPTS ?=
+SPHINXBUILD ?= sphinx-build
+SOURCEDIR = source
+BUILDDIR = build
+
+# Put it first so that "make" without argument is like "make help".
+help:
+ @$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
+
+.PHONY: help Makefile
+
+# Catch-all target: route all unknown targets to Sphinx using the new
+# "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS).
+%: Makefile
+ @$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
+
diff --git a/docs/comparator.png b/docs/comparator.png
new file mode 100644
index 0000000..a71a3a0
--- /dev/null
+++ b/docs/comparator.png
Binary files differ
diff --git a/docs/environment.yml b/docs/environment.yml
new file mode 100644
index 0000000..2bddf94
--- /dev/null
+++ b/docs/environment.yml
@@ -0,0 +1,23 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+name: caravel-docs
+channels:
+- defaults
+dependencies:
+- python>=3.8
+- pip:
+ - -r file:requirements.txt
diff --git a/docs/requirements.txt b/docs/requirements.txt
new file mode 100644
index 0000000..f5c5383
--- /dev/null
+++ b/docs/requirements.txt
@@ -0,0 +1,6 @@
+git+https://github.com/SymbiFlow/sphinx_materialdesign_theme.git#egg=sphinx-symbiflow-theme
+
+docutils
+sphinx
+sphinx-autobuild
+sphinxcontrib-wavedrom
diff --git a/docs/sim_result.png b/docs/sim_result.png
new file mode 100644
index 0000000..0d81ec9
--- /dev/null
+++ b/docs/sim_result.png
Binary files differ
diff --git a/docs/source/conf.py b/docs/source/conf.py
new file mode 100644
index 0000000..f960f13
--- /dev/null
+++ b/docs/source/conf.py
@@ -0,0 +1,89 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# Configuration file for the Sphinx documentation builder.
+#
+# This file only contains a selection of the most common options. For a full
+# list see the documentation:
+# https://www.sphinx-doc.org/en/master/usage/configuration.html
+
+# -- Path setup --------------------------------------------------------------
+
+# If extensions (or modules to document with autodoc) are in another directory,
+# add these directories to sys.path here. If the directory is relative to the
+# documentation root, use os.path.abspath to make it absolute, like shown here.
+#
+# import os
+# import sys
+# sys.path.insert(0, os.path.abspath('.'))
+
+
+# -- Project information -----------------------------------------------------
+
+project = 'CIIC Harness'
+copyright = '2020, efabless'
+author = 'efabless'
+
+
+# -- General configuration ---------------------------------------------------
+
+# Add any Sphinx extension module names here, as strings. They can be
+# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
+# ones.
+extensions = [
+ 'sphinxcontrib.wavedrom',
+ 'sphinx.ext.mathjax',
+ 'sphinx.ext.todo'
+]
+
+# Add any paths that contain templates here, relative to this directory.
+templates_path = ['_templates']
+
+# List of patterns, relative to source directory, that match files and
+# directories to ignore when looking for source files.
+# This pattern also affects html_static_path and html_extra_path.
+exclude_patterns = [
+ 'build',
+ 'Thumbs.db',
+ # Files included in other rst files.
+ 'introduction.rst',
+]
+
+
+# -- Options for HTML output -------------------------------------------------
+"""
+html_theme_options = {
+ 'header_links' : [
+ ("Home", 'index', False, 'home'),
+ ("GitHub", "https://github.com/efabless/caravel", True, 'code'),
+ ],
+ 'hide_symbiflow_links': True,
+ 'license_url' : 'https://www.apache.org/licenses/LICENSE-2.0',
+}
+"""
+# The theme to use for HTML and HTML Help pages. See the documentation for
+# a list of builtin themes.
+#
+html_theme = 'sphinx_rtd_theme'
+
+# Add any paths that contain custom static files (such as style sheets) here,
+# relative to this directory. They are copied after the builtin static files,
+# so a file named "default.css" will overwrite the builtin "default.css".
+html_static_path = ['_static']
+
+todo_include_todos = False
+
+numfig = True
diff --git a/docs/source/index.rst b/docs/source/index.rst
new file mode 100644
index 0000000..b5f711d
--- /dev/null
+++ b/docs/source/index.rst
@@ -0,0 +1,337 @@
+.. raw:: html
+
+ <!---
+ # SPDX-FileCopyrightText: 2020 Efabless Corporation
+ #
+ # Licensed under the Apache License, Version 2.0 (the "License");
+ # you may not use this file except in compliance with the License.
+ # You may obtain a copy of the License at
+ #
+ # http://www.apache.org/licenses/LICENSE-2.0
+ #
+ # Unless required by applicable law or agreed to in writing, software
+ # distributed under the License is distributed on an "AS IS" BASIS,
+ # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ # See the License for the specific language governing permissions and
+ # limitations under the License.
+ #
+ # SPDX-License-Identifier: Apache-2.0
+ -->
+
+Caravel Analog User Project
+===========================
+
+|License| |User CI| |Caravan Build|
+
+Table of contents
+=================
+
+- `Overview <#overview>`__
+- `Install Caravel <#install-caravel>`__
+- `Caravel Integration <#caravel-integration>`__
+
+ - `User Project: Power on Reset <#user-project-power-on-reset>`_
+ - `Verilog Integration <#verilog-integration>`__
+
+- `Running Full Chip Simulation <#running-full-chip-simulation>`__
+- `Analog Design Flow <#analog-design-flow>`__
+- `Other Miscellaneous Targets <#other-miscellaneous-targets>`_
+- `Checklist for Open-MPW
+ Submission <#checklist-for-open-mpw-submission>`__
+
+Overview
+========
+
+This repo contains a sample user project that utilizes the caravan chip (analog version of `caravel <https://github.com/efabless/caravel.git>`__) user space. The user project is a simple power-on-reset that showcases how to make use of caravan's user space utilities like IO pads, logic analyzer probes, and wishbone port. The repo also demonstrates the recommended structure for the open-mpw **analog** projects.
+
+Install Caravel
+===============
+
+To setup caravel, run the following:
+
+.. code:: bash
+
+ # By default, CARAVEL_ROOT is set to $(pwd)/caravel
+ # If you want to install caravel at a different location, run "export CARAVEL_ROOT=<caravel-path>"
+ # Disable submodule installation if needed by, run "export SUBMODULE=0"
+
+ git clone https://github.com/efabless/caravel_user_project_analog.git
+ cd caravel_user_project_analog
+ make install
+
+To update the installed caravel to the latest, run:
+
+.. code:: bash
+
+ make update_caravel
+
+To remove caravel, run
+
+.. code:: bash
+
+ make uninstall
+
+By default
+`caravel-lite <https://github.com/efabless/caravel-lite.git>`__ is
+installed. To install the full version of caravel, run this prior to
+calling make install.
+
+.. code:: bash
+
+ export CARAVEL_LITE=0
+
+Caravel Integration
+=====================
+
+
+User Project: Power on Reset
+----------------------------
+
+This is an example user analog project which breaks out the power-on-reset
+circuit used by the management SoC for power-up behavior so that the circuit
+input and output can be independently controlled and measured.
+
+The power-on-reset circuit itself is a simple, non-temperature-compensated
+analog delay calibrated to 15ms under nominal conditions, with a Schmitt
+trigger inverter to provide hysteresis around the trigger point to provide
+a clean output reset signal.
+
+The circuit provides a single high-voltage (3.3V domain) sense-inverted reset
+signal "porb_h" and complementary low-voltage (1.8V domain) reset signals
+"por_l" and "porb_l".
+
+The only input to the circuit is the 3.3V domain power supply itself.
+
+
+Verilog Integration
+-------------------
+
+You need to create a wrapper around your macro that adheres to the
+template at
+`user\_analog_project\_wrapper <https://github.com/efabless/caravel/blob/master/verilog/rtl/__user_analog_project_wrapper.v>`__.
+The wrapper top module must be named ``user_analog_project_wrapper`` and must
+have the same input and output ports as the analog wrapper template. The wrapper gives access to the
+user space utilities provided by caravel like IO ports, logic analyzer
+probes, and wishbone bus connection to the management SoC.
+
+The verilog modules instantiated in the wrapper module should represent
+the analog project; they need not be more than empty blocks, but it is
+encouraged to write a simple behavioral description of the analog circuit
+in standard verilog, using real-valued wires when necessary. This allows
+the whole system to be run in a verilog testbench and verify the connectivity
+to the padframe and management SoC, even if the testbench C code does nothing
+more than set the mode of each GPIO pin. The example top-level verilog code
+emulates the behavior of the power-on-reset delay after applying a valid
+power supply to the circuit.
+
+
+Building the PDK
+================
+
+You have two options for building the pdk:
+
+- Build the pdk natively.
+
+Make sure you have `Magic VLSI Layout Tool <http://opencircuitdesign.com/magic/index.html>`__ `version 8.3.160 <https://github.com/RTimothyEdwards/magic/tree/8.3.160>`__ installed on your machine before building the pdk.
+
+.. code:: bash
+
+ # set PDK_ROOT to the path you wish to use for the pdk
+ export PDK_ROOT=<pdk-installation-path>
+
+ # you can optionally specify skywater-pdk and open-pdks commit used
+ # by setting and exporting SKYWATER_COMMIT and OPEN_PDKS_COMMIT
+ # if you do not set them, they default to the last verfied commits tested for this project
+
+ make pdk
+
+- Build the pdk using openlane's docker image which has magic installed.
+
+.. code:: bash
+
+ # set PDK_ROOT to the path you wish to use for the pdk
+ export PDK_ROOT=<pdk-installation-path>
+
+ # you can optionally specify skywater-pdk and open-pdks commit used
+ # by setting and exporting SKYWATER_COMMIT and OPEN_PDKS_COMMIT
+ # if you do not set them, they default to the last verfied commits tested for this project
+
+ make pdk-nonnative
+
+Running Full Chip Simulation
+============================
+
+First, you will need to install the simulation environment, by
+
+.. code:: bash
+
+ make simenv
+
+This will pull a docker image with the needed tools installed.
+
+To install the simulation environment locally, refer to `README <https://github.com/efabless/caravel_user_project_analog/blob/main/verilog/dv/README.md>`__
+
+Then, run the RTL and GL simulation by
+
+.. code:: bash
+
+ export PDK_ROOT=<pdk-installation-path>
+ export CARAVEL_ROOT=$(pwd)/caravel
+ # specify simulation mode: RTL/GL
+ export SIM=RTL
+ # Run the mprj_por testbench, make verify-mprj_por
+ make verify-<testbench-name>
+
+The verilog test-benches are under this directory
+`verilog/dv <https://github.com/efabless/caravel_user_project_analog/tree/main/verilog/dv>`__.
+
+
+Analog Design Flow
+===================
+
+The example project uses a very simple analog design flow with schematics
+made with xschem, simulation done using ngspice, layout done with magic,
+and LVS verification done with netgen. Sources for the power-on-reset
+circuit are in the "xschem/" directory, which also includes a schematic
+representing the wrapper with all of its ports, for use in a testbench
+circuit. There are several testbenches in the example, starting from
+tests of the component devices to a full test of the completed project
+inside the wrapper.
+
+There is no automation in this project; the schematic and layout were
+done by hand, including both the power-on-reset block and the power and
+signal routing to the pins on the wrapper.
+
+The power-on-reset circuit itself is simple and is not compensated for
+temperature or voltage variation. When the power supply reaches a
+sufficient level, the voltage divider sets the gate voltage on an nFET
+device to draw a current of nominally 240nA. The testbench
+"threshold_test_tb.spice" does a DC sweep to find the gate voltage that
+produces this value. Next, a cascaded current mirror divides down the
+current by a factor of (roughly) 400. The testbench current_test.spice
+checks the current division value. Finally, the output ~600pA from the
+end of the current mirror is accumulated on a capacitor until the value
+trips the input of the 3.3V Schmitt trigger buffer from the
+sky130_fd_sd_hvl library. The capacitor is sized to peg the nominal
+time to trigger at 15ms. The schematic "example_por_tb.sch" sets up
+the testbench for this timing test.
+
+The output of the Schmitt trigger buffer becomes the high-voltage
+output, and is input to a standard buffer and inverter used as
+level shifters from the 3.3V domain to the 1.8V domain, producing
+complementary low-voltage outputs.
+
+The user project is formed from two power-on-reset circuits, one of
+which is connected to the user area VDDA1 power supply, and the other
+of which is connected to one of the analog I/O pads, used as a power
+supply input and connected to its voltage ESD clamp circuit. The
+3.3V domain outputs are connected directly to GPIO pads through the
+ESD (150 ohm series) connection. The 1.8V domain outputs are connected
+to GPIO pads through the usual I/O connections, with the corresponding
+user output enable (sense inverted) held low to keep the output always
+active.
+
+The C code testbench is in "verilog/dv/mprj_por/mprj_por.c" and only
+sets the GPIO pins used to the correct state (user output function).
+The POR circuit outputs are monitored by the testbench verilog file
+"mprj_por_tb.v" which will fail if the connections are wrong or if
+the behavioral POR verilog does not work as intended.
+
+Note that to properly test this circuit, the GPIO pins have to be
+configured for output to be seen and measured, implying that the
+management SoC power supply must be stable and the C program running
+off of the SPI flash before the user area power supplies are raised.
+
+**NOTE**
+
+ When running spice extraction on the user_analog_project_wrapper layout, it is recommended to use `ext2spice short resistor`.
+ This is to preserve all the different port names in the extracted netlist. In case you have two ports that are electrically shorted
+ in the layout, the `short resistor` option will tell magic not to merge the two shorted ports instead it adds zero-ohm ideal resistors
+ between the net names so that they can be kept as separate nets.
+
+
+Running Open-MPW Precheck Locally
+=================================
+
+You can install the precheck by running
+
+.. code:: bash
+
+ # By default, this install the precheck in your home directory
+ # To change the installtion path, run "export PRECHECK_ROOT=<precheck installation path>"
+ make precheck
+
+This will clone the precheck repo and pull the latest precheck docker image.
+
+
+Then, you can run the precheck by running
+Specify CARAVEL_ROOT before running any of the following,
+
+.. code:: bash
+
+ # export CARAVEL_ROOT=$(pwd)/caravel
+ export CARAVEL_ROOT=<path-to-caravel>
+ make run-precheck
+
+This will run all the precheck checks on your project and will retain the logs under the ``checks`` directory.
+
+Other Miscellaneous Targets
+============================
+
+The makefile provides a number of useful that targets that can run compress, uncompress, and run XOR checks on your design.
+
+Compress gds files and any file larger than 100MB (GH file size limit),
+
+.. code:: bash
+
+ make compress
+
+Uncompress files,
+
+.. code:: bash
+
+ make uncompress
+
+
+Specify ``CARAVEL_ROOT`` before running any of the following,
+
+.. code:: bash
+
+ # export CARAVEL_ROOT=$(pwd)/caravel
+ export CARAVEL_ROOT=<path-to-caravel>
+
+Run XOR check,
+
+.. code:: bash
+
+ make xor-analog-wrapper
+
+Checklist for Open-MPW Submission
+=================================
+
+
+|:heavy_check_mark:| The project repo adheres to the same directory structure in this repo.
+
+|:heavy_check_mark:| The project repo contain info.yaml at the project root.
+
+|:heavy_check_mark:| Top level macro is named ``user_analog_project_wrapper``.
+
+|:heavy_check_mark:| Full Chip Simulation passes for RTL and GL (gate-level)
+
+|:heavy_check_mark:| The project contains a spice netlist for the ``user_analog_project_wrapper`` at netgen/user_analog_project_wrapper.spice
+
+|:heavy_check_mark:| The hardened Macros are LVS and DRC clean
+
+|:heavy_check_mark:| The ``user_analog_project_wrapper`` adheres to empty wrapper template order specified at `user_analog_project_wrapper_empty <https://github.com/efabless/caravel/blob/master/mag/user_analog_project_wrapper_empty.mag>`__
+
+|:heavy_check_mark:| XOR check passes with zero total difference.
+
+|:heavy_check_mark:| Open-MPW-Precheck tool runs successfully.
+
+
+.. |License| image:: https://img.shields.io/badge/License-Apache%202.0-blue.svg
+ :target: https://opensource.org/licenses/Apache-2.0
+.. |User CI| image:: https://github.com/efabless/caravel_user_project_analog/actions/workflows/user_project_ci.yml/badge.svg
+ :target: https://github.com/efabless/caravel_user_project_analog/actions/workflows/user_project_ci.yml
+.. |Caravan Build| image:: https://github.com/efabless/caravel_user_project_analog/actions/workflows/caravan_build.yml/badge.svg
+ :target: https://github.com/efabless/caravel_user_project_analog/actions/workflows/caravan_build.yml
diff --git a/gds/user_analog_project_wrapper.gds b/gds/user_analog_project_wrapper.gds
new file mode 100644
index 0000000..9f02f6e
--- /dev/null
+++ b/gds/user_analog_project_wrapper.gds
Binary files differ
diff --git a/info.yaml b/info.yaml
new file mode 100644
index 0000000..d44f6ef
--- /dev/null
+++ b/info.yaml
@@ -0,0 +1,19 @@
+---
+project:
+ description: "Common-mode insensitive dynamic comparator"
+ foundry: "SkyWater"
+ git_url: "https://github.com/maherbenhouria/caravel_user_project_analog.git"
+ organization: "Efabless"
+ organization_url: "http://efabless.com"
+ owner: "Maher Benhouria"
+ process: "SKY130"
+ project_name: "Caravel"
+ project_id: "00000000"
+ tags:
+ - "Open MPW"
+ - "Dynamic Comparator"
+ category: "Comparator"
+ top_level_netlist: "caravel/verilog/gl/caravel.v"
+ user_level_netlist: "verilog/rtl/user_project_wrapper.v"
+ version: "1.00"
+ cover_image: "docs/source/_static/caravel_harness.png"
diff --git a/mag b/mag
new file mode 160000
index 0000000..c5e1698
--- /dev/null
+++ b/mag
@@ -0,0 +1 @@
+Subproject commit c5e1698379c1e8a6d91343059fd0df0ea54568fc
diff --git a/netgen/comp.out b/netgen/comp.out
new file mode 100644
index 0000000..92d846a
--- /dev/null
+++ b/netgen/comp.out
@@ -0,0 +1,3347 @@
+Equate elements: no current cell.
+Equate elements: no current cell.
+Flattening unmatched subcell buffer_1#0 in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell inv_W2 in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_AC5Z8B in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_XJTKXQ in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell inv_W1 in circuit user_analog_project_wrapper (0)(3 instances)
+Flattening unmatched subcell nmos_1u in circuit user_analog_project_wrapper (0)(3 instances)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_7RYEVP in circuit user_analog_project_wrapper (0)(3 instances)
+Flattening unmatched subcell pmos_2uf2 in circuit user_analog_project_wrapper (0)(3 instances)
+Flattening unmatched subcell buffer_12 in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell buffer_1 in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell inv_W2 in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_AC5Z8B in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_XJTKXQ in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell inv_W1#0 in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell nmos_1u in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_7RYEVP in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell pmos_2uf2 in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell buffer_2 in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell inv_W8 in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_KZU588 in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_RL4NCG in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell inv_W16 in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_VJWT33 in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_3M44SC in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell comparator_SA in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell preamp_part1SA in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_G6PLX8 in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_NHLLAS in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_5233FE in circuit user_analog_project_wrapper (0)(4 instances)
+Flattening unmatched subcell SR_latch in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_F5U58G in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_AC5E9B in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell inv_W1 in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell nmos_1u in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_7RYEVP in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell pmos_2uf2 in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell latch_2SA in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell inv_W22 in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_5C3Z5B in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_KBWVY9 in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell buffer_2#0 in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell inv_W8 in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_KZU588 in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_RL4NCG in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell inv_W16 in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_VJWT33 in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_3M44SC in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell buffer_2#1 in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell inv_W8 in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_KZU588 in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_RL4NCG in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell inv_W16 in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_VJWT33 in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_3M44SC in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell comparator in circuit user_analog_project_wrapper (1)(1 instance)
+
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[0]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[10]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[11]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[12]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[13]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[14]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[15]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[16]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[17]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[1]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[2]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[3]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[4]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[5]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[6]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[7]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[8]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[9]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[0]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[10]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[11]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[12]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[13]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[14]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[15]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[16]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[17]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[1]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[2]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[3]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[4]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[5]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[6]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[7]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[8]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[9]
+Cell user_analog_project_wrapper (0) disconnected node: io_analog[0]
+Cell user_analog_project_wrapper (0) disconnected node: io_analog[10]
+Cell user_analog_project_wrapper (0) disconnected node: io_analog[7]
+Cell user_analog_project_wrapper (0) disconnected node: io_analog[9]
+Cell user_analog_project_wrapper (0) disconnected node: io_analog[4]
+Cell user_analog_project_wrapper (0) disconnected node: io_clamp_high[0]
+Cell user_analog_project_wrapper (0) disconnected node: io_clamp_low[0]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[0]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[10]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[11]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[12]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[13]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[14]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[15]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[16]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[17]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[18]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[19]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[1]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[20]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[21]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[22]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[23]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[24]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[25]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[26]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[2]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[3]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[4]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[5]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[6]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[7]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[8]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[9]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[0]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[10]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[11]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[12]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[13]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[14]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[15]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[16]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[17]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[18]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[19]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[1]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[20]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[21]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[22]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[23]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[24]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[25]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[26]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[2]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[3]
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+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[4]
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+Cell user_analog_project_wrapper (1) disconnected node: io_out[2]
+Cell user_analog_project_wrapper (1) disconnected node: io_out[1]
+Cell user_analog_project_wrapper (1) disconnected node: io_out[0]
+Cell user_analog_project_wrapper (1) disconnected node: io_oeb[26]
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+Cell user_analog_project_wrapper (1) disconnected node: io_oeb[7]
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+Cell user_analog_project_wrapper (1) disconnected node: io_oeb[4]
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+Cell user_analog_project_wrapper (1) disconnected node: gpio_analog[17]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_analog[16]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_analog[15]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_analog[14]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_analog[13]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_analog[12]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_analog[11]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_analog[10]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_analog[9]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_analog[8]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_analog[7]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_analog[6]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_analog[5]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_analog[4]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_analog[3]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_analog[2]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_analog[1]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_analog[0]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[17]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[16]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[15]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[14]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[13]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[12]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[11]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[10]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[9]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[8]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[7]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[6]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[5]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[4]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[3]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[2]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[1]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[0]
+Cell user_analog_project_wrapper (1) disconnected node: io_analog[10]
+Cell user_analog_project_wrapper (1) disconnected node: io_analog[9]
+Cell user_analog_project_wrapper (1) disconnected node: io_analog[7]
+Cell user_analog_project_wrapper (1) disconnected node: io_analog[4]
+Cell user_analog_project_wrapper (1) disconnected node: io_analog[0]
+Cell user_analog_project_wrapper (1) disconnected node: io_clamp_high[0]
+Cell user_analog_project_wrapper (1) disconnected node: io_clamp_low[0]
+Cell user_analog_project_wrapper (1) disconnected node: user_clock2
+Cell user_analog_project_wrapper (1) disconnected node: user_irq[2]
+Cell user_analog_project_wrapper (1) disconnected node: user_irq[1]
+Cell user_analog_project_wrapper (1) disconnected node: user_irq[0]
+Class user_analog_project_wrapper (0): Merged 306 parallel devices.
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[0]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[10]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[11]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[12]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[13]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[14]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[15]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[16]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[17]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[1]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[2]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[3]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[4]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[5]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[6]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[7]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[8]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[9]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[0]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[10]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[11]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[12]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[13]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[14]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[15]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[16]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[17]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[1]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[2]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[3]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[4]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[5]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[6]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[7]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[8]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[9]
+Cell user_analog_project_wrapper (0) disconnected node: io_analog[0]
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+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[2]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[1]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[0]
+Cell user_analog_project_wrapper (1) disconnected node: io_analog[10]
+Cell user_analog_project_wrapper (1) disconnected node: io_analog[9]
+Cell user_analog_project_wrapper (1) disconnected node: io_analog[7]
+Cell user_analog_project_wrapper (1) disconnected node: io_analog[4]
+Cell user_analog_project_wrapper (1) disconnected node: io_analog[0]
+Cell user_analog_project_wrapper (1) disconnected node: io_clamp_high[0]
+Cell user_analog_project_wrapper (1) disconnected node: io_clamp_low[0]
+Cell user_analog_project_wrapper (1) disconnected node: user_clock2
+Cell user_analog_project_wrapper (1) disconnected node: user_irq[2]
+Cell user_analog_project_wrapper (1) disconnected node: user_irq[1]
+Cell user_analog_project_wrapper (1) disconnected node: user_irq[0]
+Subcircuit summary:
+Circuit 1: user_analog_project_wrapper |Circuit 2: user_analog_project_wrapper
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8 (232->27) |sky130_fd_pr__pfet_01v8 (27)
+sky130_fd_pr__nfet_01v8 (127->26) |sky130_fd_pr__nfet_01v8 (26)
+vsrc (4) |vsrc (4)
+Number of devices: 57 |Number of devices: 57
+Number of nets: 35 |Number of nets: 35
+---------------------------------------------------------------------------------------
+Resolving automorphisms by property value.
+Resolving automorphisms by pin name.
+Netlists match uniquely.
+Circuits match correctly.
+
+Subcircuit pins:
+Circuit 1: user_analog_project_wrapper |Circuit 2: user_analog_project_wrapper
+-------------------------------------------|-------------------------------------------
+io_analog[5] |io_analog[5]
+io_analog[6] |io_analog[6]
+io_clamp_low[1] |io_clamp_low[1]
+io_clamp_low[2] |io_clamp_low[2]
+io_clamp_high[2] |io_clamp_high[2]
+io_clamp_high[1] |io_clamp_high[1]
+io_analog[3] |io_analog[3]
+io_analog[2] |io_analog[2]
+io_analog[1] |io_analog[1]
+vssa1 |vssa1
+io_analog[8] |io_analog[8]
+vccd1 |vccd1
+gpio_analog[0] |gpio_analog[0]
+gpio_analog[10] |gpio_analog[10]
+gpio_analog[11] |gpio_analog[11]
+gpio_analog[12] |gpio_analog[12]
+gpio_analog[13] |gpio_analog[13]
+gpio_analog[14] |gpio_analog[14]
+gpio_analog[15] |gpio_analog[15]
+gpio_analog[16] |gpio_analog[16]
+gpio_analog[17] |gpio_analog[17]
+gpio_analog[1] |gpio_analog[1]
+gpio_analog[2] |gpio_analog[2]
+gpio_analog[3] |gpio_analog[3]
+gpio_analog[4] |gpio_analog[4]
+gpio_analog[5] |gpio_analog[5]
+gpio_analog[6] |gpio_analog[6]
+gpio_analog[7] |gpio_analog[7]
+gpio_analog[8] |gpio_analog[8]
+gpio_analog[9] |gpio_analog[9]
+gpio_noesd[0] |gpio_noesd[0]
+gpio_noesd[10] |gpio_noesd[10]
+gpio_noesd[11] |gpio_noesd[11]
+gpio_noesd[12] |gpio_noesd[12]
+gpio_noesd[13] |gpio_noesd[13]
+gpio_noesd[14] |gpio_noesd[14]
+gpio_noesd[15] |gpio_noesd[15]
+gpio_noesd[16] |gpio_noesd[16]
+gpio_noesd[17] |gpio_noesd[17]
+gpio_noesd[1] |gpio_noesd[1]
+gpio_noesd[2] |gpio_noesd[2]
+gpio_noesd[3] |gpio_noesd[3]
+gpio_noesd[4] |gpio_noesd[4]
+gpio_noesd[5] |gpio_noesd[5]
+gpio_noesd[6] |gpio_noesd[6]
+gpio_noesd[7] |gpio_noesd[7]
+gpio_noesd[8] |gpio_noesd[8]
+gpio_noesd[9] |gpio_noesd[9]
+io_analog[0] |io_analog[0]
+io_analog[10] |io_analog[10]
+io_analog[7] |io_analog[7]
+io_analog[9] |io_analog[9]
+io_analog[4] |io_analog[4]
+io_clamp_high[0] |io_clamp_high[0]
+io_clamp_low[0] |io_clamp_low[0]
+io_in[0] |io_in[0]
+io_in[10] |io_in[10]
+io_in[11] |io_in[11]
+io_in[12] |io_in[12]
+io_in[13] |io_in[13]
+io_in[14] |io_in[14]
+io_in[15] |io_in[15]
+io_in[16] |io_in[16]
+io_in[17] |io_in[17]
+io_in[18] |io_in[18]
+io_in[19] |io_in[19]
+io_in[1] |io_in[1]
+io_in[20] |io_in[20]
+io_in[21] |io_in[21]
+io_in[22] |io_in[22]
+io_in[23] |io_in[23]
+io_in[24] |io_in[24]
+io_in[25] |io_in[25]
+io_in[26] |io_in[26]
+io_in[2] |io_in[2]
+io_in[3] |io_in[3]
+io_in[4] |io_in[4]
+io_in[5] |io_in[5]
+io_in[6] |io_in[6]
+io_in[7] |io_in[7]
+io_in[8] |io_in[8]
+io_in[9] |io_in[9]
+io_in_3v3[0] |io_in_3v3[0]
+io_in_3v3[10] |io_in_3v3[10]
+io_in_3v3[11] |io_in_3v3[11]
+io_in_3v3[12] |io_in_3v3[12]
+io_in_3v3[13] |io_in_3v3[13]
+io_in_3v3[14] |io_in_3v3[14]
+io_in_3v3[15] |io_in_3v3[15]
+io_in_3v3[16] |io_in_3v3[16]
+io_in_3v3[17] |io_in_3v3[17]
+io_in_3v3[18] |io_in_3v3[18]
+io_in_3v3[19] |io_in_3v3[19]
+io_in_3v3[1] |io_in_3v3[1]
+io_in_3v3[20] |io_in_3v3[20]
+io_in_3v3[21] |io_in_3v3[21]
+io_in_3v3[22] |io_in_3v3[22]
+io_in_3v3[23] |io_in_3v3[23]
+io_in_3v3[24] |io_in_3v3[24]
+io_in_3v3[25] |io_in_3v3[25]
+io_in_3v3[26] |io_in_3v3[26]
+io_in_3v3[2] |io_in_3v3[2]
+io_in_3v3[3] |io_in_3v3[3]
+io_in_3v3[4] |io_in_3v3[4]
+io_in_3v3[5] |io_in_3v3[5]
+io_in_3v3[6] |io_in_3v3[6]
+io_in_3v3[7] |io_in_3v3[7]
+io_in_3v3[8] |io_in_3v3[8]
+io_in_3v3[9] |io_in_3v3[9]
+io_oeb[0] |io_oeb[0]
+io_oeb[10] |io_oeb[10]
+io_oeb[11] |io_oeb[11]
+io_oeb[12] |io_oeb[12]
+io_oeb[13] |io_oeb[13]
+io_oeb[14] |io_oeb[14]
+io_oeb[15] |io_oeb[15]
+io_oeb[16] |io_oeb[16]
+io_oeb[17] |io_oeb[17]
+io_oeb[18] |io_oeb[18]
+io_oeb[19] |io_oeb[19]
+io_oeb[1] |io_oeb[1]
+io_oeb[20] |io_oeb[20]
+io_oeb[21] |io_oeb[21]
+io_oeb[22] |io_oeb[22]
+io_oeb[23] |io_oeb[23]
+io_oeb[24] |io_oeb[24]
+io_oeb[25] |io_oeb[25]
+io_oeb[26] |io_oeb[26]
+io_oeb[2] |io_oeb[2]
+io_oeb[3] |io_oeb[3]
+io_oeb[4] |io_oeb[4]
+io_oeb[5] |io_oeb[5]
+io_oeb[6] |io_oeb[6]
+io_oeb[7] |io_oeb[7]
+io_oeb[8] |io_oeb[8]
+io_oeb[9] |io_oeb[9]
+io_out[0] |io_out[0]
+io_out[10] |io_out[10]
+io_out[11] |io_out[11]
+io_out[12] |io_out[12]
+io_out[13] |io_out[13]
+io_out[14] |io_out[14]
+io_out[15] |io_out[15]
+io_out[16] |io_out[16]
+io_out[17] |io_out[17]
+io_out[18] |io_out[18]
+io_out[19] |io_out[19]
+io_out[1] |io_out[1]
+io_out[20] |io_out[20]
+io_out[21] |io_out[21]
+io_out[22] |io_out[22]
+io_out[23] |io_out[23]
+io_out[24] |io_out[24]
+io_out[25] |io_out[25]
+io_out[26] |io_out[26]
+io_out[2] |io_out[2]
+io_out[3] |io_out[3]
+io_out[4] |io_out[4]
+io_out[5] |io_out[5]
+io_out[6] |io_out[6]
+io_out[7] |io_out[7]
+io_out[8] |io_out[8]
+io_out[9] |io_out[9]
+la_data_in[0] |la_data_in[0]
+la_data_in[100] |la_data_in[100]
+la_data_in[101] |la_data_in[101]
+la_data_in[102] |la_data_in[102]
+la_data_in[103] |la_data_in[103]
+la_data_in[104] |la_data_in[104]
+la_data_in[105] |la_data_in[105]
+la_data_in[106] |la_data_in[106]
+la_data_in[107] |la_data_in[107]
+la_data_in[108] |la_data_in[108]
+la_data_in[109] |la_data_in[109]
+la_data_in[10] |la_data_in[10]
+la_data_in[110] |la_data_in[110]
+la_data_in[111] |la_data_in[111]
+la_data_in[112] |la_data_in[112]
+la_data_in[113] |la_data_in[113]
+la_data_in[114] |la_data_in[114]
+la_data_in[115] |la_data_in[115]
+la_data_in[116] |la_data_in[116]
+la_data_in[117] |la_data_in[117]
+la_data_in[118] |la_data_in[118]
+la_data_in[119] |la_data_in[119]
+la_data_in[11] |la_data_in[11]
+la_data_in[120] |la_data_in[120]
+la_data_in[121] |la_data_in[121]
+la_data_in[122] |la_data_in[122]
+la_data_in[123] |la_data_in[123]
+la_data_in[124] |la_data_in[124]
+la_data_in[125] |la_data_in[125]
+la_data_in[126] |la_data_in[126]
+la_data_in[127] |la_data_in[127]
+la_data_in[12] |la_data_in[12]
+la_data_in[13] |la_data_in[13]
+la_data_in[14] |la_data_in[14]
+la_data_in[15] |la_data_in[15]
+la_data_in[16] |la_data_in[16]
+la_data_in[17] |la_data_in[17]
+la_data_in[18] |la_data_in[18]
+la_data_in[19] |la_data_in[19]
+la_data_in[1] |la_data_in[1]
+la_data_in[20] |la_data_in[20]
+la_data_in[21] |la_data_in[21]
+la_data_in[22] |la_data_in[22]
+la_data_in[23] |la_data_in[23]
+la_data_in[24] |la_data_in[24]
+la_data_in[25] |la_data_in[25]
+la_data_in[26] |la_data_in[26]
+la_data_in[27] |la_data_in[27]
+la_data_in[28] |la_data_in[28]
+la_data_in[29] |la_data_in[29]
+la_data_in[2] |la_data_in[2]
+la_data_in[30] |la_data_in[30]
+la_data_in[31] |la_data_in[31]
+la_data_in[32] |la_data_in[32]
+la_data_in[33] |la_data_in[33]
+la_data_in[34] |la_data_in[34]
+la_data_in[35] |la_data_in[35]
+la_data_in[36] |la_data_in[36]
+la_data_in[37] |la_data_in[37]
+la_data_in[38] |la_data_in[38]
+la_data_in[39] |la_data_in[39]
+la_data_in[3] |la_data_in[3]
+la_data_in[40] |la_data_in[40]
+la_data_in[41] |la_data_in[41]
+la_data_in[42] |la_data_in[42]
+la_data_in[43] |la_data_in[43]
+la_data_in[44] |la_data_in[44]
+la_data_in[45] |la_data_in[45]
+la_data_in[46] |la_data_in[46]
+la_data_in[47] |la_data_in[47]
+la_data_in[48] |la_data_in[48]
+la_data_in[49] |la_data_in[49]
+la_data_in[4] |la_data_in[4]
+la_data_in[50] |la_data_in[50]
+la_data_in[51] |la_data_in[51]
+la_data_in[52] |la_data_in[52]
+la_data_in[53] |la_data_in[53]
+la_data_in[54] |la_data_in[54]
+la_data_in[55] |la_data_in[55]
+la_data_in[56] |la_data_in[56]
+la_data_in[57] |la_data_in[57]
+la_data_in[58] |la_data_in[58]
+la_data_in[59] |la_data_in[59]
+la_data_in[5] |la_data_in[5]
+la_data_in[60] |la_data_in[60]
+la_data_in[61] |la_data_in[61]
+la_data_in[62] |la_data_in[62]
+la_data_in[63] |la_data_in[63]
+la_data_in[64] |la_data_in[64]
+la_data_in[65] |la_data_in[65]
+la_data_in[66] |la_data_in[66]
+la_data_in[67] |la_data_in[67]
+la_data_in[68] |la_data_in[68]
+la_data_in[69] |la_data_in[69]
+la_data_in[6] |la_data_in[6]
+la_data_in[70] |la_data_in[70]
+la_data_in[71] |la_data_in[71]
+la_data_in[72] |la_data_in[72]
+la_data_in[73] |la_data_in[73]
+la_data_in[74] |la_data_in[74]
+la_data_in[75] |la_data_in[75]
+la_data_in[76] |la_data_in[76]
+la_data_in[77] |la_data_in[77]
+la_data_in[78] |la_data_in[78]
+la_data_in[79] |la_data_in[79]
+la_data_in[7] |la_data_in[7]
+la_data_in[80] |la_data_in[80]
+la_data_in[81] |la_data_in[81]
+la_data_in[82] |la_data_in[82]
+la_data_in[83] |la_data_in[83]
+la_data_in[84] |la_data_in[84]
+la_data_in[85] |la_data_in[85]
+la_data_in[86] |la_data_in[86]
+la_data_in[87] |la_data_in[87]
+la_data_in[88] |la_data_in[88]
+la_data_in[89] |la_data_in[89]
+la_data_in[8] |la_data_in[8]
+la_data_in[90] |la_data_in[90]
+la_data_in[91] |la_data_in[91]
+la_data_in[92] |la_data_in[92]
+la_data_in[93] |la_data_in[93]
+la_data_in[94] |la_data_in[94]
+la_data_in[95] |la_data_in[95]
+la_data_in[96] |la_data_in[96]
+la_data_in[97] |la_data_in[97]
+la_data_in[98] |la_data_in[98]
+la_data_in[99] |la_data_in[99]
+la_data_in[9] |la_data_in[9]
+la_data_out[0] |la_data_out[0]
+la_data_out[100] |la_data_out[100]
+la_data_out[101] |la_data_out[101]
+la_data_out[102] |la_data_out[102]
+la_data_out[103] |la_data_out[103]
+la_data_out[104] |la_data_out[104]
+la_data_out[105] |la_data_out[105]
+la_data_out[106] |la_data_out[106]
+la_data_out[107] |la_data_out[107]
+la_data_out[108] |la_data_out[108]
+la_data_out[109] |la_data_out[109]
+la_data_out[10] |la_data_out[10]
+la_data_out[110] |la_data_out[110]
+la_data_out[111] |la_data_out[111]
+la_data_out[112] |la_data_out[112]
+la_data_out[113] |la_data_out[113]
+la_data_out[114] |la_data_out[114]
+la_data_out[115] |la_data_out[115]
+la_data_out[116] |la_data_out[116]
+la_data_out[117] |la_data_out[117]
+la_data_out[118] |la_data_out[118]
+la_data_out[119] |la_data_out[119]
+la_data_out[11] |la_data_out[11]
+la_data_out[120] |la_data_out[120]
+la_data_out[121] |la_data_out[121]
+la_data_out[122] |la_data_out[122]
+la_data_out[123] |la_data_out[123]
+la_data_out[124] |la_data_out[124]
+la_data_out[125] |la_data_out[125]
+la_data_out[126] |la_data_out[126]
+la_data_out[127] |la_data_out[127]
+la_data_out[12] |la_data_out[12]
+la_data_out[13] |la_data_out[13]
+la_data_out[14] |la_data_out[14]
+la_data_out[15] |la_data_out[15]
+la_data_out[16] |la_data_out[16]
+la_data_out[17] |la_data_out[17]
+la_data_out[18] |la_data_out[18]
+la_data_out[19] |la_data_out[19]
+la_data_out[1] |la_data_out[1]
+la_data_out[20] |la_data_out[20]
+la_data_out[21] |la_data_out[21]
+la_data_out[22] |la_data_out[22]
+la_data_out[23] |la_data_out[23]
+la_data_out[24] |la_data_out[24]
+la_data_out[25] |la_data_out[25]
+la_data_out[26] |la_data_out[26]
+la_data_out[27] |la_data_out[27]
+la_data_out[28] |la_data_out[28]
+la_data_out[29] |la_data_out[29]
+la_data_out[2] |la_data_out[2]
+la_data_out[30] |la_data_out[30]
+la_data_out[31] |la_data_out[31]
+la_data_out[32] |la_data_out[32]
+la_data_out[33] |la_data_out[33]
+la_data_out[34] |la_data_out[34]
+la_data_out[35] |la_data_out[35]
+la_data_out[36] |la_data_out[36]
+la_data_out[37] |la_data_out[37]
+la_data_out[38] |la_data_out[38]
+la_data_out[39] |la_data_out[39]
+la_data_out[3] |la_data_out[3]
+la_data_out[40] |la_data_out[40]
+la_data_out[41] |la_data_out[41]
+la_data_out[42] |la_data_out[42]
+la_data_out[43] |la_data_out[43]
+la_data_out[44] |la_data_out[44]
+la_data_out[45] |la_data_out[45]
+la_data_out[46] |la_data_out[46]
+la_data_out[47] |la_data_out[47]
+la_data_out[48] |la_data_out[48]
+la_data_out[49] |la_data_out[49]
+la_data_out[4] |la_data_out[4]
+la_data_out[50] |la_data_out[50]
+la_data_out[51] |la_data_out[51]
+la_data_out[52] |la_data_out[52]
+la_data_out[53] |la_data_out[53]
+la_data_out[54] |la_data_out[54]
+la_data_out[55] |la_data_out[55]
+la_data_out[56] |la_data_out[56]
+la_data_out[57] |la_data_out[57]
+la_data_out[58] |la_data_out[58]
+la_data_out[59] |la_data_out[59]
+la_data_out[5] |la_data_out[5]
+la_data_out[60] |la_data_out[60]
+la_data_out[61] |la_data_out[61]
+la_data_out[62] |la_data_out[62]
+la_data_out[63] |la_data_out[63]
+la_data_out[64] |la_data_out[64]
+la_data_out[65] |la_data_out[65]
+la_data_out[66] |la_data_out[66]
+la_data_out[67] |la_data_out[67]
+la_data_out[68] |la_data_out[68]
+la_data_out[69] |la_data_out[69]
+la_data_out[6] |la_data_out[6]
+la_data_out[70] |la_data_out[70]
+la_data_out[71] |la_data_out[71]
+la_data_out[72] |la_data_out[72]
+la_data_out[73] |la_data_out[73]
+la_data_out[74] |la_data_out[74]
+la_data_out[75] |la_data_out[75]
+la_data_out[76] |la_data_out[76]
+la_data_out[77] |la_data_out[77]
+la_data_out[78] |la_data_out[78]
+la_data_out[79] |la_data_out[79]
+la_data_out[7] |la_data_out[7]
+la_data_out[80] |la_data_out[80]
+la_data_out[81] |la_data_out[81]
+la_data_out[82] |la_data_out[82]
+la_data_out[83] |la_data_out[83]
+la_data_out[84] |la_data_out[84]
+la_data_out[85] |la_data_out[85]
+la_data_out[86] |la_data_out[86]
+la_data_out[87] |la_data_out[87]
+la_data_out[88] |la_data_out[88]
+la_data_out[89] |la_data_out[89]
+la_data_out[8] |la_data_out[8]
+la_data_out[90] |la_data_out[90]
+la_data_out[91] |la_data_out[91]
+la_data_out[92] |la_data_out[92]
+la_data_out[93] |la_data_out[93]
+la_data_out[94] |la_data_out[94]
+la_data_out[95] |la_data_out[95]
+la_data_out[96] |la_data_out[96]
+la_data_out[97] |la_data_out[97]
+la_data_out[98] |la_data_out[98]
+la_data_out[99] |la_data_out[99]
+la_data_out[9] |la_data_out[9]
+la_oenb[0] |la_oenb[0]
+la_oenb[100] |la_oenb[100]
+la_oenb[101] |la_oenb[101]
+la_oenb[102] |la_oenb[102]
+la_oenb[103] |la_oenb[103]
+la_oenb[104] |la_oenb[104]
+la_oenb[105] |la_oenb[105]
+la_oenb[106] |la_oenb[106]
+la_oenb[107] |la_oenb[107]
+la_oenb[108] |la_oenb[108]
+la_oenb[109] |la_oenb[109]
+la_oenb[10] |la_oenb[10]
+la_oenb[110] |la_oenb[110]
+la_oenb[111] |la_oenb[111]
+la_oenb[112] |la_oenb[112]
+la_oenb[113] |la_oenb[113]
+la_oenb[114] |la_oenb[114]
+la_oenb[115] |la_oenb[115]
+la_oenb[116] |la_oenb[116]
+la_oenb[117] |la_oenb[117]
+la_oenb[118] |la_oenb[118]
+la_oenb[119] |la_oenb[119]
+la_oenb[11] |la_oenb[11]
+la_oenb[120] |la_oenb[120]
+la_oenb[121] |la_oenb[121]
+la_oenb[122] |la_oenb[122]
+la_oenb[123] |la_oenb[123]
+la_oenb[124] |la_oenb[124]
+la_oenb[125] |la_oenb[125]
+la_oenb[126] |la_oenb[126]
+la_oenb[127] |la_oenb[127]
+la_oenb[12] |la_oenb[12]
+la_oenb[13] |la_oenb[13]
+la_oenb[14] |la_oenb[14]
+la_oenb[15] |la_oenb[15]
+la_oenb[16] |la_oenb[16]
+la_oenb[17] |la_oenb[17]
+la_oenb[18] |la_oenb[18]
+la_oenb[19] |la_oenb[19]
+la_oenb[1] |la_oenb[1]
+la_oenb[20] |la_oenb[20]
+la_oenb[21] |la_oenb[21]
+la_oenb[22] |la_oenb[22]
+la_oenb[23] |la_oenb[23]
+la_oenb[24] |la_oenb[24]
+la_oenb[25] |la_oenb[25]
+la_oenb[26] |la_oenb[26]
+la_oenb[27] |la_oenb[27]
+la_oenb[28] |la_oenb[28]
+la_oenb[29] |la_oenb[29]
+la_oenb[2] |la_oenb[2]
+la_oenb[30] |la_oenb[30]
+la_oenb[31] |la_oenb[31]
+la_oenb[32] |la_oenb[32]
+la_oenb[33] |la_oenb[33]
+la_oenb[34] |la_oenb[34]
+la_oenb[35] |la_oenb[35]
+la_oenb[36] |la_oenb[36]
+la_oenb[37] |la_oenb[37]
+la_oenb[38] |la_oenb[38]
+la_oenb[39] |la_oenb[39]
+la_oenb[3] |la_oenb[3]
+la_oenb[40] |la_oenb[40]
+la_oenb[41] |la_oenb[41]
+la_oenb[42] |la_oenb[42]
+la_oenb[43] |la_oenb[43]
+la_oenb[44] |la_oenb[44]
+la_oenb[45] |la_oenb[45]
+la_oenb[46] |la_oenb[46]
+la_oenb[47] |la_oenb[47]
+la_oenb[48] |la_oenb[48]
+la_oenb[49] |la_oenb[49]
+la_oenb[4] |la_oenb[4]
+la_oenb[50] |la_oenb[50]
+la_oenb[51] |la_oenb[51]
+la_oenb[52] |la_oenb[52]
+la_oenb[53] |la_oenb[53]
+la_oenb[54] |la_oenb[54]
+la_oenb[55] |la_oenb[55]
+la_oenb[56] |la_oenb[56]
+la_oenb[57] |la_oenb[57]
+la_oenb[58] |la_oenb[58]
+la_oenb[59] |la_oenb[59]
+la_oenb[5] |la_oenb[5]
+la_oenb[60] |la_oenb[60]
+la_oenb[61] |la_oenb[61]
+la_oenb[62] |la_oenb[62]
+la_oenb[63] |la_oenb[63]
+la_oenb[64] |la_oenb[64]
+la_oenb[65] |la_oenb[65]
+la_oenb[66] |la_oenb[66]
+la_oenb[67] |la_oenb[67]
+la_oenb[68] |la_oenb[68]
+la_oenb[69] |la_oenb[69]
+la_oenb[6] |la_oenb[6]
+la_oenb[70] |la_oenb[70]
+la_oenb[71] |la_oenb[71]
+la_oenb[72] |la_oenb[72]
+la_oenb[73] |la_oenb[73]
+la_oenb[74] |la_oenb[74]
+la_oenb[75] |la_oenb[75]
+la_oenb[76] |la_oenb[76]
+la_oenb[77] |la_oenb[77]
+la_oenb[78] |la_oenb[78]
+la_oenb[79] |la_oenb[79]
+la_oenb[7] |la_oenb[7]
+la_oenb[80] |la_oenb[80]
+la_oenb[81] |la_oenb[81]
+la_oenb[82] |la_oenb[82]
+la_oenb[83] |la_oenb[83]
+la_oenb[84] |la_oenb[84]
+la_oenb[85] |la_oenb[85]
+la_oenb[86] |la_oenb[86]
+la_oenb[87] |la_oenb[87]
+la_oenb[88] |la_oenb[88]
+la_oenb[89] |la_oenb[89]
+la_oenb[8] |la_oenb[8]
+la_oenb[90] |la_oenb[90]
+la_oenb[91] |la_oenb[91]
+la_oenb[92] |la_oenb[92]
+la_oenb[93] |la_oenb[93]
+la_oenb[94] |la_oenb[94]
+la_oenb[95] |la_oenb[95]
+la_oenb[96] |la_oenb[96]
+la_oenb[97] |la_oenb[97]
+la_oenb[98] |la_oenb[98]
+la_oenb[99] |la_oenb[99]
+la_oenb[9] |la_oenb[9]
+user_clock2 |user_clock2
+user_irq[0] |user_irq[0]
+user_irq[1] |user_irq[1]
+user_irq[2] |user_irq[2]
+vccd2 |vccd2
+vdda1 |vdda1
+vdda2 |vdda2
+vssa2 |vssa2
+vssd1 |vssd1
+vssd2 |vssd2
+wb_clk_i |wb_clk_i
+wb_rst_i |wb_rst_i
+wbs_ack_o |wbs_ack_o
+wbs_adr_i[0] |wbs_adr_i[0]
+wbs_adr_i[10] |wbs_adr_i[10]
+wbs_adr_i[11] |wbs_adr_i[11]
+wbs_adr_i[12] |wbs_adr_i[12]
+wbs_adr_i[13] |wbs_adr_i[13]
+wbs_adr_i[14] |wbs_adr_i[14]
+wbs_adr_i[15] |wbs_adr_i[15]
+wbs_adr_i[16] |wbs_adr_i[16]
+wbs_adr_i[17] |wbs_adr_i[17]
+wbs_adr_i[18] |wbs_adr_i[18]
+wbs_adr_i[19] |wbs_adr_i[19]
+wbs_adr_i[1] |wbs_adr_i[1]
+wbs_adr_i[20] |wbs_adr_i[20]
+wbs_adr_i[21] |wbs_adr_i[21]
+wbs_adr_i[22] |wbs_adr_i[22]
+wbs_adr_i[23] |wbs_adr_i[23]
+wbs_adr_i[24] |wbs_adr_i[24]
+wbs_adr_i[25] |wbs_adr_i[25]
+wbs_adr_i[26] |wbs_adr_i[26]
+wbs_adr_i[27] |wbs_adr_i[27]
+wbs_adr_i[28] |wbs_adr_i[28]
+wbs_adr_i[29] |wbs_adr_i[29]
+wbs_adr_i[2] |wbs_adr_i[2]
+wbs_adr_i[30] |wbs_adr_i[30]
+wbs_adr_i[31] |wbs_adr_i[31]
+wbs_adr_i[3] |wbs_adr_i[3]
+wbs_adr_i[4] |wbs_adr_i[4]
+wbs_adr_i[5] |wbs_adr_i[5]
+wbs_adr_i[6] |wbs_adr_i[6]
+wbs_adr_i[7] |wbs_adr_i[7]
+wbs_adr_i[8] |wbs_adr_i[8]
+wbs_adr_i[9] |wbs_adr_i[9]
+wbs_cyc_i |wbs_cyc_i
+wbs_dat_i[0] |wbs_dat_i[0]
+wbs_dat_i[10] |wbs_dat_i[10]
+wbs_dat_i[11] |wbs_dat_i[11]
+wbs_dat_i[12] |wbs_dat_i[12]
+wbs_dat_i[13] |wbs_dat_i[13]
+wbs_dat_i[14] |wbs_dat_i[14]
+wbs_dat_i[15] |wbs_dat_i[15]
+wbs_dat_i[16] |wbs_dat_i[16]
+wbs_dat_i[17] |wbs_dat_i[17]
+wbs_dat_i[18] |wbs_dat_i[18]
+wbs_dat_i[19] |wbs_dat_i[19]
+wbs_dat_i[1] |wbs_dat_i[1]
+wbs_dat_i[20] |wbs_dat_i[20]
+wbs_dat_i[21] |wbs_dat_i[21]
+wbs_dat_i[22] |wbs_dat_i[22]
+wbs_dat_i[23] |wbs_dat_i[23]
+wbs_dat_i[24] |wbs_dat_i[24]
+wbs_dat_i[25] |wbs_dat_i[25]
+wbs_dat_i[26] |wbs_dat_i[26]
+wbs_dat_i[27] |wbs_dat_i[27]
+wbs_dat_i[28] |wbs_dat_i[28]
+wbs_dat_i[29] |wbs_dat_i[29]
+wbs_dat_i[2] |wbs_dat_i[2]
+wbs_dat_i[30] |wbs_dat_i[30]
+wbs_dat_i[31] |wbs_dat_i[31]
+wbs_dat_i[3] |wbs_dat_i[3]
+wbs_dat_i[4] |wbs_dat_i[4]
+wbs_dat_i[5] |wbs_dat_i[5]
+wbs_dat_i[6] |wbs_dat_i[6]
+wbs_dat_i[7] |wbs_dat_i[7]
+wbs_dat_i[8] |wbs_dat_i[8]
+wbs_dat_i[9] |wbs_dat_i[9]
+wbs_dat_o[0] |wbs_dat_o[0]
+wbs_dat_o[10] |wbs_dat_o[10]
+wbs_dat_o[11] |wbs_dat_o[11]
+wbs_dat_o[12] |wbs_dat_o[12]
+wbs_dat_o[13] |wbs_dat_o[13]
+wbs_dat_o[14] |wbs_dat_o[14]
+wbs_dat_o[15] |wbs_dat_o[15]
+wbs_dat_o[16] |wbs_dat_o[16]
+wbs_dat_o[17] |wbs_dat_o[17]
+wbs_dat_o[18] |wbs_dat_o[18]
+wbs_dat_o[19] |wbs_dat_o[19]
+wbs_dat_o[1] |wbs_dat_o[1]
+wbs_dat_o[20] |wbs_dat_o[20]
+wbs_dat_o[21] |wbs_dat_o[21]
+wbs_dat_o[22] |wbs_dat_o[22]
+wbs_dat_o[23] |wbs_dat_o[23]
+wbs_dat_o[24] |wbs_dat_o[24]
+wbs_dat_o[25] |wbs_dat_o[25]
+wbs_dat_o[26] |wbs_dat_o[26]
+wbs_dat_o[27] |wbs_dat_o[27]
+wbs_dat_o[28] |wbs_dat_o[28]
+wbs_dat_o[29] |wbs_dat_o[29]
+wbs_dat_o[2] |wbs_dat_o[2]
+wbs_dat_o[30] |wbs_dat_o[30]
+wbs_dat_o[31] |wbs_dat_o[31]
+wbs_dat_o[3] |wbs_dat_o[3]
+wbs_dat_o[4] |wbs_dat_o[4]
+wbs_dat_o[5] |wbs_dat_o[5]
+wbs_dat_o[6] |wbs_dat_o[6]
+wbs_dat_o[7] |wbs_dat_o[7]
+wbs_dat_o[8] |wbs_dat_o[8]
+wbs_dat_o[9] |wbs_dat_o[9]
+wbs_sel_i[0] |wbs_sel_i[0]
+wbs_sel_i[1] |wbs_sel_i[1]
+wbs_sel_i[2] |wbs_sel_i[2]
+wbs_sel_i[3] |wbs_sel_i[3]
+wbs_stb_i |wbs_stb_i
+wbs_we_i |wbs_we_i
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes user_analog_project_wrapper and user_analog_project_wrapper are equivalent.
+Circuits match uniquely.
diff --git a/netgen/comparator.spice b/netgen/comparator.spice
new file mode 100644
index 0000000..7776247
--- /dev/null
+++ b/netgen/comparator.spice
@@ -0,0 +1,140 @@
+** sch_path: /home/krishna/Strong_Arm_MPW6/xschem/comparator.sch
+**.subckt comparator VDD GND Vn Vp CLK Outn Outp
+*.iopin VDD
+*.iopin GND
+*.ipin Vn
+*.ipin Vp
+*.iopin CLK
+*.opin Outn
+*.opin Outp
+XM1 net2 Vp net1 GND sky130_fd_pr__nfet_01v8 L=0.15 W=5.3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 net3 Vn net1 GND sky130_fd_pr__nfet_01v8 L=0.15 W=5.3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net1 C GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM11 net2 C VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM12 Dn C VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM13 Dp C VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM14 net3 C VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM15 Dp Dn net3 GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.78 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM16 Dn Dp net2 GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.78 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM17 Dp Dn VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.78 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM18 Dn Dp VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.78 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM20 p Lp GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM21 n Ln GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM22 p n VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM23 n p VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM24 net4 CLK GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM25 net4 CLK VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM26 net5 net4 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM27 net5 net4 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM28 net6 net5 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=8 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM29 net6 net5 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM30 C net6 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM31 C net6 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=32 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM40 net7 n GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM41 net7 n VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM42 net8 net7 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM43 net8 net7 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM44 net9 net8 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=8 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM45 net9 net8 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM46 Outn net9 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM47 Outn net9 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=32 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM48 net10 p GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM49 net10 p VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM50 net11 net10 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM51 net11 net10 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM52 net12 net11 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=8 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM53 net12 net11 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM54 Outp net12 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM55 Outp net12 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=32 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 Lp Dp GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM5 Lp Dp VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 Ln Dn GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM7 Ln Dn VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+**.ends
+.end
diff --git a/netgen/comparator_SA.spice b/netgen/comparator_SA.spice
new file mode 100644
index 0000000..d7bdefd
--- /dev/null
+++ b/netgen/comparator_SA.spice
@@ -0,0 +1,121 @@
+* SPICE3 file created from comparator_SA.ext - technology: sky130A
+
+.subckt sky130_fd_pr__nfet_01v8_G6PLX8 a_159_n100# li_n945_n316# a_n221_n74# a_n129_n100#
++ a_63_n100# a_n159_n156# a_n33_n100# VSUBS
+X0 a_n129_n100# a_n159_n156# a_n221_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+X1 a_63_n100# a_n159_n156# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_n33_n100# a_n159_n156# a_n129_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_159_n100# a_n159_n156# a_63_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_NHLLAS a_n63_n153# a_n129_n133# a_63_n133# a_129_n153#
++ a_n221_n96# a_n33_n133# a_n159_n153# a_159_n133# a_33_n153# VSUBS
+X0 a_159_n133# a_129_n153# a_63_n133# VSUBS sky130_fd_pr__nfet_01v8 ad=4.049e+11p pd=3.28e+06u as=4.389e+11p ps=3.32e+06u w=1.33e+06u l=150000u
+X1 a_63_n133# a_33_n153# a_n33_n133# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=4.389e+11p ps=3.32e+06u w=1.33e+06u l=150000u
+X2 a_n129_n133# a_n159_n153# a_n221_n96# VSUBS sky130_fd_pr__nfet_01v8 ad=4.389e+11p pd=3.32e+06u as=4.049e+11p ps=3.28e+06u w=1.33e+06u l=150000u
+X3 a_n33_n133# a_n63_n153# a_n129_n133# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.33e+06u l=150000u
+.ends
+
+.subckt preamp_part1SA m1_n694_236# a_n734_300# li_126_310# m1_924_192# a_80_354#
++ a_976_302# a_n302_940# w_n720_482# a_506_940# li_318_312# li_n66_312# VSUBS
+Xsky130_fd_pr__nfet_01v8_G6PLX8_0 li_318_312# li_n24_n74# li_n66_312# li_n24_n74#
++ li_n24_n74# a_80_354# li_126_310# VSUBS sky130_fd_pr__nfet_01v8_G6PLX8
+Xsky130_fd_pr__nfet_01v8_NHLLAS_0 a_n734_300# m1_n694_236# m1_n694_236# a_n734_300#
++ li_n24_n74# li_n24_n74# a_n734_300# li_n24_n74# a_n734_300# VSUBS sky130_fd_pr__nfet_01v8_NHLLAS
+Xsky130_fd_pr__nfet_01v8_NHLLAS_1 a_976_302# m1_924_192# m1_924_192# a_976_302# li_n24_n74#
++ li_n24_n74# a_976_302# li_n24_n74# a_976_302# VSUBS sky130_fd_pr__nfet_01v8_NHLLAS
+
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_5233FE a_n15_n76# w_n109_n112# a_n73_n50# a_15_n50#
++ VSUBS
+X0 a_15_n50# a_n15_n76# a_n73_n50# w_n109_n112# sky130_fd_pr__pfet_01v8 ad=1.45e+11p pd=1.58e+06u as=1.45e+11p ps=1.58e+06u w=500000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_F5U58G a_n73_n100# a_15_n100# a_n15_n126# VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AC5E9B w_n161_n200# a_33_n126# a_63_n100# a_n125_n74#
++ a_n33_n100# a_n63_n130# VSUBS
+X0 a_63_n100# a_33_n126# a_n33_n100# w_n161_n200# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n130# a_n125_n74# w_n161_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt SR_latch a_648_848# sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126# sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#
++ a_262_508# VDD w_0_524# GND VSUBS
+Xsky130_fd_pr__nfet_01v8_F5U58G_0 a_648_848# GND sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#
++ VSUBS sky130_fd_pr__nfet_01v8_F5U58G
+Xsky130_fd_pr__nfet_01v8_F5U58G_1 GND a_262_508# sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126#
++ VSUBS sky130_fd_pr__nfet_01v8_F5U58G
+Xsky130_fd_pr__pfet_01v8_AC5E9B_0 w_0_524# a_262_508# VDD VDD a_648_848# a_262_508#
++ VSUBS sky130_fd_pr__pfet_01v8_AC5E9B
+Xsky130_fd_pr__pfet_01v8_AC5E9B_1 w_0_524# a_648_848# VDD VDD a_262_508# a_648_848#
++ VSUBS sky130_fd_pr__pfet_01v8_AC5E9B
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7RYEVP a_n73_n69# a_n15_n89# a_15_n69# VSUBS
+X0 a_15_n69# a_n15_n89# a_n73_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt nmos_1u sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS sky130_fd_pr__nfet_01v8_7RYEVP_0/a_n15_n89#
++ sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#
+Xsky130_fd_pr__nfet_01v8_7RYEVP_0 sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS sky130_fd_pr__nfet_01v8_7RYEVP_0/a_n15_n89#
++ sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69# sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS
++ sky130_fd_pr__nfet_01v8_7RYEVP
+.ends
+
+.subckt pmos_2uf2 a_63_n100# a_33_n130# w_n317_n202# a_n33_n100# a_n63_n130# VSUBS
+X0 a_63_n100# a_33_n130# a_n33_n100# w_n317_n202# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n130# w_n317_n202# w_n317_n202# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.8e+11p ps=2.76e+06u w=1e+06u l=150000u
+.ends
+
+.subckt inv_W1 Vout Vin VDD GND
+Xnmos_1u_0 GND Vin Vout nmos_1u
+Xpmos_2uf2_0 VDD Vin VDD Vout Vin GND pmos_2uf2
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_5C3Z5B a_15_n78# a_n15_n104# a_n73_n78# w_n109_n140#
++ VSUBS
+X0 a_15_n78# a_n15_n104# a_n73_n78# w_n109_n140# sky130_fd_pr__pfet_01v8 ad=2.262e+11p pd=2.14e+06u as=2.262e+11p ps=2.14e+06u w=780000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KBWVY9 a_15_n78# a_n15_n104# a_n73_n78# VSUBS
+X0 a_15_n78# a_n15_n104# a_n73_n78# VSUBS sky130_fd_pr__nfet_01v8 ad=2.262e+11p pd=2.14e+06u as=2.262e+11p ps=2.14e+06u w=780000u l=150000u
+.ends
+
+.subckt inv_W22 li_200_260# sky130_fd_pr__nfet_01v8_KBWVY9_0/a_n73_n78# sky130_fd_pr__pfet_01v8_5C3Z5B_0/w_n109_n140#
++ Vin VDD sky130_fd_pr__pfet_01v8_5C3Z5B_0/a_15_n78# VSUBS
+Xsky130_fd_pr__pfet_01v8_5C3Z5B_0 sky130_fd_pr__pfet_01v8_5C3Z5B_0/a_15_n78# Vin VDD
++ sky130_fd_pr__pfet_01v8_5C3Z5B_0/w_n109_n140# VSUBS sky130_fd_pr__pfet_01v8_5C3Z5B
+Xsky130_fd_pr__nfet_01v8_KBWVY9_0 li_200_260# Vin sky130_fd_pr__nfet_01v8_KBWVY9_0/a_n73_n78#
++ VSUBS sky130_fd_pr__nfet_01v8_KBWVY9
+.ends
+
+.subckt latch_2SA inv_W22_0/sky130_fd_pr__pfet_01v8_5C3Z5B_0/a_15_n78# w_0_516# inv_W22_0/Vin
++ inv_W22_1/li_200_260# inv_W22_1/sky130_fd_pr__nfet_01v8_KBWVY9_0/a_n73_n78# inv_W22_0/sky130_fd_pr__nfet_01v8_KBWVY9_0/a_n73_n78#
++ inv_W22_0/li_200_260# inv_W22_1/Vin inv_W22_1/VDD inv_W22_1/sky130_fd_pr__pfet_01v8_5C3Z5B_0/a_15_n78#
++ VSUBS
+Xinv_W22_0 inv_W22_0/li_200_260# inv_W22_0/sky130_fd_pr__nfet_01v8_KBWVY9_0/a_n73_n78#
++ w_0_516# inv_W22_0/Vin inv_W22_1/VDD inv_W22_0/sky130_fd_pr__pfet_01v8_5C3Z5B_0/a_15_n78#
++ VSUBS inv_W22
+Xinv_W22_1 inv_W22_1/li_200_260# inv_W22_1/sky130_fd_pr__nfet_01v8_KBWVY9_0/a_n73_n78#
++ w_0_516# inv_W22_1/Vin inv_W22_1/VDD inv_W22_1/sky130_fd_pr__pfet_01v8_5C3Z5B_0/a_15_n78#
++ VSUBS inv_W22
+.ends
+
+
+* Top level circuit comparator_SA
+
+Xpreamp_part1SA_0 fn Vn GND fp CLK Vp CLK VDD CLK GND GND GND preamp_part1SA
+Xsky130_fd_pr__pfet_01v8_5233FE_0 CLK VDD VDD fn GND sky130_fd_pr__pfet_01v8_5233FE
+Xsky130_fd_pr__pfet_01v8_5233FE_1 CLK VDD fp VDD GND sky130_fd_pr__pfet_01v8_5233FE
+Xsky130_fd_pr__pfet_01v8_5233FE_2 CLK VDD VDD Dn GND sky130_fd_pr__pfet_01v8_5233FE
+Xsky130_fd_pr__pfet_01v8_5233FE_3 CLK VDD VDD Dp GND sky130_fd_pr__pfet_01v8_5233FE
+XSR_latch_0 Outp Ln Lp Outn VDD VDD GND GND SR_latch
+Xinv_W1_0 Lp Dp VDD GND inv_W1
+Xinv_W1_1 Ln Dn VDD GND inv_W1
+Xlatch_2SA_0 Dn VDD Dp Dp fp fn Dn Dn VDD Dp GND latch_2SA
+
+.end
+
diff --git a/netgen/comparator_lvs.spice b/netgen/comparator_lvs.spice
new file mode 100644
index 0000000..a7b7d6a
--- /dev/null
+++ b/netgen/comparator_lvs.spice
@@ -0,0 +1,68 @@
+** sch_path: /home/krishna/Strong_Arm_MPW6/xschem/comparator_lvs.sch
+.subckt comparator_lvs VDD GND Vp Vn CLK outn outp
+.iopin VDD
+.iopin GND
+.ipin Vp
+.ipin Vn
+.iopin CLK
+.iopin outn
+.iopin outp
+XM1 net2 Vn net1 GND sky130_fd_pr__nfet_01v8 L=0.15 W=5.3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 net3 Vp net1 GND sky130_fd_pr__nfet_01v8 L=0.15 W=5.3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net1 CLK GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM11 net2 CLK VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM12 Dn CLK VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM13 Dp CLK VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM14 net3 CLK VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM15 Dp Dn net3 GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.78 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM16 Dn Dp net2 GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.78 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM17 Dp Dn VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.78 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM18 Dn Dp VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.78 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM20 outp Lp GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM21 outn Ln GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM22 outp outn VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM23 outn outp VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 Lp Dp GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM5 Lp Dp VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 Ln Dn GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM7 Ln Dn VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+.end
diff --git a/netgen/example_por.spice b/netgen/example_por.spice
new file mode 100644
index 0000000..d96a104
--- /dev/null
+++ b/netgen/example_por.spice
@@ -0,0 +1,483 @@
+* SPICE3 file created from user_analog_project_wrapper.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_AC5Z8B a_159_n100# li_217_n290# li_n261_n290# li_229_174#
++ a_n221_n74# a_n129_n100# a_n159_n152# li_225_n726# a_n33_n100# w_n261_n210# li_n261_174#
++ li_n261_n726# VSUBS
+X0 a_n129_n100# a_n159_n152# a_n33_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5.32e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n159_n152# a_n129_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_159_n100# a_n159_n152# a_n129_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n129_n100# a_n159_n152# a_n221_n74# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_XJTKXQ a_33_n122# a_n63_n122# a_63_n100# a_n125_n74#
++ a_n33_n100# VSUBS
+X0 a_63_n100# a_33_n122# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n122# a_n125_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt inv_W2 sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210# Vout Vin VDD GND VSUBS
+Xsky130_fd_pr__pfet_01v8_AC5Z8B_0 VDD Vout Vin VDD VDD Vout Vin GND VDD sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#
++ VDD GND VSUBS sky130_fd_pr__pfet_01v8_AC5Z8B
+Xsky130_fd_pr__nfet_01v8_XJTKXQ_0 Vin Vin GND GND Vout VSUBS sky130_fd_pr__nfet_01v8_XJTKXQ
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7RYEVP a_n73_n69# a_n15_n89# a_15_n69# VSUBS
+X0 a_15_n69# a_n15_n89# a_n73_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt nmos_1u sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS sky130_fd_pr__nfet_01v8_7RYEVP_0/a_n15_n89#
++ sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#
+Xsky130_fd_pr__nfet_01v8_7RYEVP_0 sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS sky130_fd_pr__nfet_01v8_7RYEVP_0/a_n15_n89#
++ sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69# sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS
++ sky130_fd_pr__nfet_01v8_7RYEVP
+.ends
+
+.subckt pmos_2uf2 a_63_n100# a_33_n130# w_n317_n202# a_n33_n100# a_n63_n130# VSUBS
+X0 a_63_n100# a_33_n130# a_n33_n100# w_n317_n202# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n130# w_n317_n202# w_n317_n202# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.8e+11p ps=2.76e+06u w=1e+06u l=150000u
+.ends
+
+.subckt inv_W1 Vout Vin VDD GND
+Xnmos_1u_0 GND Vin Vout nmos_1u
+Xpmos_2uf2_0 VDD Vin VDD Vout Vin GND pmos_2uf2
+.ends
+
+.subckt buffer_1#0 inv_W2_0/VDD inv_W2_0/Vout inv_W1_0/Vin VSUBS
+Xinv_W2_0 inv_W2_0/VDD inv_W2_0/Vout inv_W2_0/Vin inv_W2_0/VDD VSUBS VSUBS inv_W2
+Xinv_W1_0 inv_W2_0/Vin inv_W1_0/Vin inv_W2_0/VDD VSUBS inv_W1
+.ends
+
+.subckt inv_W1#0 Vout Vin VDD GND
+Xnmos_1u_0 GND Vin Vout nmos_1u
+Xpmos_2uf2_0 VDD Vin VDD Vout Vin GND pmos_2uf2
+.ends
+
+.subckt buffer_1 inv_W2_0/Vout inv_W1_0/Vin VSUBS inv_W2_0/VDD
+Xinv_W2_0 inv_W2_0/VDD inv_W2_0/Vout inv_W2_0/Vin inv_W2_0/VDD VSUBS VSUBS inv_W2
+Xinv_W1_0 inv_W2_0/Vin inv_W1_0/Vin inv_W2_0/VDD VSUBS inv_W1#0
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KZU588 a_159_n100# a_255_n100# a_351_n100# a_n129_n100#
++ a_63_n100# li_321_116# a_n353_n162# a_n225_n100# a_n413_n74# a_n321_n100# a_n33_n100#
++ VSUBS
+X0 a_n321_n100# a_n353_n162# a_n413_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+X1 a_n225_n100# a_n353_n162# a_n321_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n129_n100# a_n353_n162# a_n225_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X3 a_63_n100# a_n353_n162# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X4 a_n33_n100# a_n353_n162# a_n129_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_351_n100# a_n353_n162# a_255_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X6 a_159_n100# a_n353_n162# a_63_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X7 a_255_n100# a_n353_n162# a_159_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_RL4NCG a_543_n100# a_159_n100# a_n609_n100# a_321_n126#
++ a_n705_n100# a_255_n100# a_n159_n128# a_n543_n128# a_n255_n126# a_351_n100# a_n417_n100#
++ a_33_n128# a_n129_n100# a_n513_n100# a_n351_n128# a_63_n100# w_n833_n200# a_n225_n100#
++ a_609_n128# a_n63_n126# a_n797_n74# a_705_n126# a_n321_n100# a_639_n100# a_417_n128#
++ a_n639_n126# a_735_n100# a_n33_n100# a_513_n126# a_129_n126# a_447_n100# a_n735_n128#
++ a_n447_n126# a_225_n128# VSUBS
+X0 a_63_n100# a_33_n128# a_n33_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n126# a_n129_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_255_n100# a_225_n128# a_159_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X3 a_351_n100# a_321_n126# a_255_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X4 a_543_n100# a_513_n126# a_447_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X5 a_159_n100# a_129_n126# a_63_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_447_n100# a_417_n128# a_351_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_639_n100# a_609_n128# a_543_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X8 a_735_n100# a_705_n126# a_639_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X9 a_n513_n100# a_n543_n128# a_n609_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X10 a_n321_n100# a_n351_n128# a_n417_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X11 a_n225_n100# a_n255_n126# a_n321_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X12 a_n705_n100# a_n735_n128# a_n797_n74# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+X13 a_n609_n100# a_n639_n126# a_n705_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X14 a_n417_n100# a_n447_n126# a_n513_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X15 a_n129_n100# a_n159_n128# a_n225_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt inv_W8 li_354_902# w_354_500# li_354_0# li_512_546# a_804_430# VSUBS
+Xsky130_fd_pr__nfet_01v8_KZU588_0 li_354_0# li_512_546# li_354_0# li_512_546# li_512_546#
++ li_512_546# a_804_430# li_354_0# li_354_0# li_512_546# li_354_0# VSUBS sky130_fd_pr__nfet_01v8_KZU588
+Xsky130_fd_pr__pfet_01v8_RL4NCG_0 li_354_902# li_354_902# li_354_902# a_804_430# li_512_546#
++ li_512_546# a_804_430# a_804_430# a_804_430# li_354_902# li_354_902# a_804_430#
++ li_512_546# li_512_546# a_804_430# li_512_546# w_354_500# li_354_902# a_804_430#
++ a_804_430# li_354_902# a_804_430# li_512_546# li_512_546# a_804_430# a_804_430#
++ li_354_902# li_354_902# a_804_430# a_804_430# li_512_546# a_804_430# a_804_430#
++ a_804_430# VSUBS sky130_fd_pr__pfet_01v8_RL4NCG
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_VJWT33 a_543_n100# a_159_n100# a_n609_n100# a_n705_n100#
++ a_255_n100# a_351_n100# a_n417_n100# a_n129_n100# a_n513_n100# a_63_n100# a_n225_n100#
++ a_n797_n74# a_n735_n176# a_n321_n100# a_639_n100# a_735_n100# a_n33_n100# a_447_n100#
++ VSUBS
+X0 a_n513_n100# a_n735_n176# a_n609_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n321_n100# a_n735_n176# a_n417_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_n225_n100# a_n735_n176# a_n321_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n705_n100# a_n735_n176# a_n797_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+X4 a_n609_n100# a_n735_n176# a_n705_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_n417_n100# a_n735_n176# a_n513_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_n129_n100# a_n735_n176# a_n225_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X7 a_63_n100# a_n735_n176# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X8 a_n33_n100# a_n735_n176# a_n129_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X9 a_351_n100# a_n735_n176# a_255_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X10 a_159_n100# a_n735_n176# a_63_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X11 a_255_n100# a_n735_n176# a_159_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X12 a_447_n100# a_n735_n176# a_351_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X13 a_543_n100# a_n735_n176# a_447_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X14 a_639_n100# a_n735_n176# a_543_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X15 a_735_n100# a_n735_n176# a_639_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_3M44SC a_543_n100# a_159_n100# a_n609_n100# a_321_n126#
++ a_1473_n126# a_1089_n126# a_n1407_n126# a_n705_n100# a_255_n100# a_n159_n128# a_n543_n128#
++ a_1407_n100# a_1185_n128# a_n255_n126# a_351_n100# a_n417_n100# a_n801_n100# a_n1119_n128#
++ a_n1503_n128# a_1281_n126# a_897_n126# a_33_n128# w_n1601_n200# a_1503_n100# a_1119_n100#
++ a_n1377_n100# a_n1215_n126# a_n129_n100# a_n513_n100# a_n351_n128# a_n1565_n74#
++ a_1215_n100# a_63_n100# a_n1089_n100# a_n1473_n100# a_993_n128# a_n225_n100# a_609_n128#
++ a_n63_n126# a_n1311_n128# a_1311_n100# a_927_n100# a_n1185_n100# a_705_n126# a_n1023_n126#
++ a_n321_n100# a_1023_n100# a_639_n100# a_n1281_n100# a_n927_n128# a_801_n128# a_417_n128#
++ a_n639_n126# a_735_n100# a_n33_n100# a_513_n126# a_129_n126# a_n897_n100# a_831_n100#
++ a_447_n100# a_n735_n128# a_n993_n100# a_n447_n126# a_n831_n126# a_1377_n128# a_225_n128#
++ VSUBS
+X0 a_63_n100# a_33_n128# a_n33_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_927_n100# a_897_n126# a_831_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_1023_n100# a_993_n128# a_927_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X3 a_1311_n100# a_1281_n126# a_1215_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X4 a_1119_n100# a_1089_n126# a_1023_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X5 a_1215_n100# a_1185_n128# a_1119_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_1407_n100# a_1377_n128# a_1311_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X7 a_1503_n100# a_1473_n126# a_1407_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X8 a_n33_n100# a_n63_n126# a_n129_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X9 a_255_n100# a_225_n128# a_159_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X10 a_351_n100# a_321_n126# a_255_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X11 a_543_n100# a_513_n126# a_447_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X12 a_831_n100# a_801_n128# a_735_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X13 a_159_n100# a_129_n126# a_63_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X14 a_447_n100# a_417_n128# a_351_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X15 a_639_n100# a_609_n128# a_543_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X16 a_735_n100# a_705_n126# a_639_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X17 a_n1281_n100# a_n1311_n128# a_n1377_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X18 a_n993_n100# a_n1023_n126# a_n1089_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X19 a_n1473_n100# a_n1503_n128# a_n1565_n74# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+X20 a_n1377_n100# a_n1407_n126# a_n1473_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X21 a_n1185_n100# a_n1215_n126# a_n1281_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X22 a_n1089_n100# a_n1119_n128# a_n1185_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X23 a_n801_n100# a_n831_n126# a_n897_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X24 a_n513_n100# a_n543_n128# a_n609_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X25 a_n321_n100# a_n351_n128# a_n417_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X26 a_n225_n100# a_n255_n126# a_n321_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X27 a_n897_n100# a_n927_n128# a_n993_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X28 a_n705_n100# a_n735_n128# a_n801_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X29 a_n609_n100# a_n639_n126# a_n705_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X30 a_n417_n100# a_n447_n126# a_n513_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X31 a_n129_n100# a_n159_n128# a_n225_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+
+.ends
+
+.subckt inv_W16 li_128_546# li_n14_902# a_82_816# w_82_814# li_n14_0# VSUBS
+Xsky130_fd_pr__nfet_01v8_VJWT33_0 li_n14_0# li_n14_0# li_n14_0# li_128_546# li_128_546#
++ li_n14_0# li_n14_0# li_128_546# li_128_546# li_128_546# li_n14_0# li_n14_0# a_82_816#
++ li_128_546# li_128_546# li_n14_0# li_n14_0# li_128_546# VSUBS sky130_fd_pr__nfet_01v8_VJWT33
+Xsky130_fd_pr__pfet_01v8_3M44SC_0 li_n14_902# li_n14_902# li_n14_902# a_82_816# a_82_816#
++ a_82_816# a_82_816# li_128_546# li_128_546# a_82_816# a_82_816# li_128_546# a_82_816#
++ a_82_816# li_n14_902# li_n14_902# li_n14_902# a_82_816# a_82_816# a_82_816# a_82_816#
++ a_82_816# w_82_814# li_n14_902# li_n14_902# li_n14_902# a_82_816# li_128_546# li_128_546#
++ a_82_816# li_n14_902# li_128_546# li_128_546# li_128_546# li_128_546# a_82_816#
++ li_n14_902# a_82_816# a_82_816# a_82_816# li_n14_902# li_n14_902# li_n14_902# a_82_816#
++ a_82_816# li_128_546# li_128_546# li_128_546# li_128_546# a_82_816# a_82_816# a_82_816#
++ a_82_816# li_n14_902# li_n14_902# a_82_816# a_82_816# li_128_546# li_128_546# li_128_546#
++ a_82_816# li_n14_902# a_82_816# a_82_816# a_82_816# a_82_816# VSUBS sky130_fd_pr__pfet_01v8_3M44SC
+
+.ends
+
+.subckt buffer_2 Vout inv_W8_0/li_354_902# w_1666_500# inv_W8_0/a_804_430# inv_W8_0/li_354_0#
++ VSUBS
+Xinv_W8_0 inv_W8_0/li_354_902# w_1666_500# inv_W8_0/li_354_0# inv_W16_0/a_82_816#
++ inv_W8_0/a_804_430# VSUBS inv_W8
+Xinv_W16_0 Vout inv_W8_0/li_354_902# inv_W16_0/a_82_816# w_1666_500# inv_W8_0/li_354_0#
++ VSUBS inv_W16
+
+.ends
+
+.subckt buffer_12 buf_out buf_in VDD GND
+Xbuffer_1_0 buffer_1_0/inv_W2_0/Vout buf_in GND VDD buffer_1
+Xbuffer_2_0 buf_out VDD VDD buffer_1_0/inv_W2_0/Vout GND GND buffer_2
+
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_G6PLX8 a_159_n100# li_n945_n316# a_n221_n74# a_n129_n100#
++ a_63_n100# a_n159_n156# a_n33_n100# VSUBS
+X0 a_n129_n100# a_n159_n156# a_n221_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+X1 a_63_n100# a_n159_n156# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_n33_n100# a_n159_n156# a_n129_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_159_n100# a_n159_n156# a_63_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_NHLLAS a_n63_n153# a_n129_n133# a_63_n133# a_129_n153#
++ a_n221_n96# a_n33_n133# a_n159_n153# a_159_n133# a_33_n153# VSUBS
+X0 a_159_n133# a_129_n153# a_63_n133# VSUBS sky130_fd_pr__nfet_01v8 ad=4.049e+11p pd=3.28e+06u as=4.389e+11p ps=3.32e+06u w=1.33e+06u l=150000u
+X1 a_63_n133# a_33_n153# a_n33_n133# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=4.389e+11p ps=3.32e+06u w=1.33e+06u l=150000u
+X2 a_n129_n133# a_n159_n153# a_n221_n96# VSUBS sky130_fd_pr__nfet_01v8 ad=4.389e+11p pd=3.32e+06u as=4.049e+11p ps=3.28e+06u w=1.33e+06u l=150000u
+X3 a_n33_n133# a_n63_n153# a_n129_n133# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.33e+06u l=150000u
+.ends
+
+.subckt preamp_part1SA m1_n694_236# a_n734_300# li_126_310# m1_924_192# a_80_354#
++ a_976_302# a_n302_940# w_n720_482# a_506_940# li_318_312# li_n66_312# VSUBS
+Xsky130_fd_pr__nfet_01v8_G6PLX8_0 li_318_312# li_n24_n74# li_n66_312# li_n24_n74#
++ li_n24_n74# a_80_354# li_126_310# VSUBS sky130_fd_pr__nfet_01v8_G6PLX8
+Xsky130_fd_pr__nfet_01v8_NHLLAS_0 a_n734_300# m1_n694_236# m1_n694_236# a_n734_300#
++ li_n24_n74# li_n24_n74# a_n734_300# li_n24_n74# a_n734_300# VSUBS sky130_fd_pr__nfet_01v8_NHLLAS
+Xsky130_fd_pr__nfet_01v8_NHLLAS_1 a_976_302# m1_924_192# m1_924_192# a_976_302# li_n24_n74#
++ li_n24_n74# a_976_302# li_n24_n74# a_976_302# VSUBS sky130_fd_pr__nfet_01v8_NHLLAS
+
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_5233FE a_n15_n76# w_n109_n112# a_n73_n50# a_15_n50#
++ VSUBS
+X0 a_15_n50# a_n15_n76# a_n73_n50# w_n109_n112# sky130_fd_pr__pfet_01v8 ad=1.45e+11p pd=1.58e+06u as=1.45e+11p ps=1.58e+06u w=500000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_F5U58G a_n73_n100# a_15_n100# a_n15_n126# VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AC5E9B w_n161_n200# a_33_n126# a_63_n100# a_n125_n74#
++ a_n33_n100# a_n63_n130# VSUBS
+X0 a_63_n100# a_33_n126# a_n33_n100# w_n161_n200# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n130# a_n125_n74# w_n161_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt SR_latch a_648_848# sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126# sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#
++ a_262_508# VDD w_0_524# GND VSUBS
+Xsky130_fd_pr__nfet_01v8_F5U58G_0 a_648_848# GND sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#
++ VSUBS sky130_fd_pr__nfet_01v8_F5U58G
+Xsky130_fd_pr__nfet_01v8_F5U58G_1 GND a_262_508# sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126#
++ VSUBS sky130_fd_pr__nfet_01v8_F5U58G
+Xsky130_fd_pr__pfet_01v8_AC5E9B_0 w_0_524# a_262_508# VDD VDD a_648_848# a_262_508#
++ VSUBS sky130_fd_pr__pfet_01v8_AC5E9B
+Xsky130_fd_pr__pfet_01v8_AC5E9B_1 w_0_524# a_648_848# VDD VDD a_262_508# a_648_848#
++ VSUBS sky130_fd_pr__pfet_01v8_AC5E9B
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_5C3Z5B a_15_n78# a_n15_n104# a_n73_n78# w_n109_n140#
++ VSUBS
+X0 a_15_n78# a_n15_n104# a_n73_n78# w_n109_n140# sky130_fd_pr__pfet_01v8 ad=2.262e+11p pd=2.14e+06u as=2.262e+11p ps=2.14e+06u w=780000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KBWVY9 a_15_n78# a_n15_n104# a_n73_n78# VSUBS
+X0 a_15_n78# a_n15_n104# a_n73_n78# VSUBS sky130_fd_pr__nfet_01v8 ad=2.262e+11p pd=2.14e+06u as=2.262e+11p ps=2.14e+06u w=780000u l=150000u
+.ends
+
+.subckt inv_W22 li_200_260# sky130_fd_pr__nfet_01v8_KBWVY9_0/a_n73_n78# sky130_fd_pr__pfet_01v8_5C3Z5B_0/w_n109_n140#
++ Vin VDD sky130_fd_pr__pfet_01v8_5C3Z5B_0/a_15_n78# VSUBS
+Xsky130_fd_pr__pfet_01v8_5C3Z5B_0 sky130_fd_pr__pfet_01v8_5C3Z5B_0/a_15_n78# Vin VDD
++ sky130_fd_pr__pfet_01v8_5C3Z5B_0/w_n109_n140# VSUBS sky130_fd_pr__pfet_01v8_5C3Z5B
+Xsky130_fd_pr__nfet_01v8_KBWVY9_0 li_200_260# Vin sky130_fd_pr__nfet_01v8_KBWVY9_0/a_n73_n78#
++ VSUBS sky130_fd_pr__nfet_01v8_KBWVY9
+.ends
+
+.subckt latch_2SA inv_W22_0/sky130_fd_pr__pfet_01v8_5C3Z5B_0/a_15_n78# w_0_516# inv_W22_0/Vin
++ inv_W22_1/li_200_260# inv_W22_1/sky130_fd_pr__nfet_01v8_KBWVY9_0/a_n73_n78# inv_W22_0/sky130_fd_pr__nfet_01v8_KBWVY9_0/a_n73_n78#
++ inv_W22_0/li_200_260# inv_W22_1/Vin inv_W22_1/VDD inv_W22_1/sky130_fd_pr__pfet_01v8_5C3Z5B_0/a_15_n78#
++ VSUBS
+Xinv_W22_0 inv_W22_0/li_200_260# inv_W22_0/sky130_fd_pr__nfet_01v8_KBWVY9_0/a_n73_n78#
++ w_0_516# inv_W22_0/Vin inv_W22_1/VDD inv_W22_0/sky130_fd_pr__pfet_01v8_5C3Z5B_0/a_15_n78#
++ VSUBS inv_W22
+Xinv_W22_1 inv_W22_1/li_200_260# inv_W22_1/sky130_fd_pr__nfet_01v8_KBWVY9_0/a_n73_n78#
++ w_0_516# inv_W22_1/Vin inv_W22_1/VDD inv_W22_1/sky130_fd_pr__pfet_01v8_5C3Z5B_0/a_15_n78#
++ VSUBS inv_W22
+.ends
+
+.subckt comparator_SA Outn Vp Vn CLK VDD GND Outp
+Xpreamp_part1SA_0 fn Vn GND fp CLK Vp CLK VDD CLK GND GND GND preamp_part1SA
+Xsky130_fd_pr__pfet_01v8_5233FE_0 CLK VDD VDD fn GND sky130_fd_pr__pfet_01v8_5233FE
+Xsky130_fd_pr__pfet_01v8_5233FE_1 CLK VDD fp VDD GND sky130_fd_pr__pfet_01v8_5233FE
+Xsky130_fd_pr__pfet_01v8_5233FE_2 CLK VDD VDD Dn GND sky130_fd_pr__pfet_01v8_5233FE
+Xsky130_fd_pr__pfet_01v8_5233FE_3 CLK VDD VDD Dp GND sky130_fd_pr__pfet_01v8_5233FE
+XSR_latch_0 Outp Ln Lp Outn VDD VDD GND GND SR_latch
+Xinv_W1_0 Lp Dp VDD GND inv_W1
+Xinv_W1_1 Ln Dn VDD GND inv_W1
+Xlatch_2SA_0 Dn VDD Dp Dp fp fn Dn Dn VDD Dp GND latch_2SA
+
+.ends
+
+.subckt buffer_2#0 Vout w_1666_500# inv_W8_0/li_354_902# inv_W8_0/a_804_430# inv_W8_0/li_354_0#
++ VSUBS
+Xinv_W8_0 inv_W8_0/li_354_902# w_1666_500# inv_W8_0/li_354_0# inv_W16_0/a_82_816#
++ inv_W8_0/a_804_430# VSUBS inv_W8
+Xinv_W16_0 Vout inv_W8_0/li_354_902# inv_W16_0/a_82_816# w_1666_500# inv_W8_0/li_354_0#
++ VSUBS inv_W16
+
+.ends
+
+.subckt buffer_2#1 Vout w_1666_500# inv_W8_0/li_354_902# inv_W8_0/a_804_430# inv_W8_0/li_354_0#
++ VSUBS
+Xinv_W8_0 inv_W8_0/li_354_902# w_1666_500# inv_W8_0/li_354_0# inv_W16_0/a_82_816#
++ inv_W8_0/a_804_430# VSUBS inv_W8
+Xinv_W16_0 Vout inv_W8_0/li_354_902# inv_W16_0/a_82_816# w_1666_500# inv_W8_0/li_354_0#
++ VSUBS inv_W16
+
+.ends
+
+.subckt user_analog_project_wrapper gpio_analog[0] gpio_analog[10] gpio_analog[11]
++ gpio_analog[12] gpio_analog[13] gpio_analog[14] gpio_analog[15] gpio_analog[16]
++ gpio_analog[17] gpio_analog[1] gpio_analog[2] gpio_analog[3] gpio_analog[4] gpio_analog[5]
++ gpio_analog[6] gpio_analog[7] gpio_analog[8] gpio_analog[9] gpio_noesd[0] gpio_noesd[10]
++ gpio_noesd[11] gpio_noesd[12] gpio_noesd[13] gpio_noesd[14] gpio_noesd[15] gpio_noesd[16]
++ gpio_noesd[17] gpio_noesd[1] gpio_noesd[2] gpio_noesd[3] gpio_noesd[4] gpio_noesd[5]
++ gpio_noesd[6] gpio_noesd[7] gpio_noesd[8] gpio_noesd[9] io_analog[0] io_analog[10]
++ io_analog[1] io_analog[2] io_analog[3] io_analog[5] io_analog[6] io_analog[7] io_analog[8]
++ io_analog[9] io_analog[4] io_clamp_high[0] io_clamp_high[1] io_clamp_high[2] io_clamp_low[0]
++ io_clamp_low[1] io_clamp_low[2] io_in[0] io_in[10] io_in[11] io_in[12] io_in[13]
++ io_in[14] io_in[15] io_in[16] io_in[17] io_in[18] io_in[19] io_in[1] io_in[20] io_in[21]
++ io_in[22] io_in[23] io_in[24] io_in[25] io_in[26] io_in[2] io_in[3] io_in[4] io_in[5]
++ io_in[6] io_in[7] io_in[8] io_in[9] io_in_3v3[0] io_in_3v3[10] io_in_3v3[11] io_in_3v3[12]
++ io_in_3v3[13] io_in_3v3[14] io_in_3v3[15] io_in_3v3[16] io_in_3v3[17] io_in_3v3[18]
++ io_in_3v3[19] io_in_3v3[1] io_in_3v3[20] io_in_3v3[21] io_in_3v3[22] io_in_3v3[23]
++ io_in_3v3[24] io_in_3v3[25] io_in_3v3[26] io_in_3v3[2] io_in_3v3[3] io_in_3v3[4]
++ io_in_3v3[5] io_in_3v3[6] io_in_3v3[7] io_in_3v3[8] io_in_3v3[9] io_oeb[0] io_oeb[10]
++ io_oeb[11] io_oeb[12] io_oeb[13] io_oeb[14] io_oeb[15] io_oeb[16] io_oeb[17] io_oeb[18]
++ io_oeb[19] io_oeb[1] io_oeb[20] io_oeb[21] io_oeb[22] io_oeb[23] io_oeb[24] io_oeb[25]
++ io_oeb[26] io_oeb[2] io_oeb[3] io_oeb[4] io_oeb[5] io_oeb[6] io_oeb[7] io_oeb[8]
++ io_oeb[9] io_out[0] io_out[10] io_out[11] io_out[12] io_out[13] io_out[14] io_out[15]
++ io_out[16] io_out[17] io_out[18] io_out[19] io_out[1] io_out[20] io_out[21] io_out[22]
++ io_out[23] io_out[24] io_out[25] io_out[26] io_out[2] io_out[3] io_out[4] io_out[5]
++ io_out[6] io_out[7] io_out[8] io_out[9] la_data_in[0] la_data_in[100] la_data_in[101]
++ la_data_in[102] la_data_in[103] la_data_in[104] la_data_in[105] la_data_in[106]
++ la_data_in[107] la_data_in[108] la_data_in[109] la_data_in[10] la_data_in[110] la_data_in[111]
++ la_data_in[112] la_data_in[113] la_data_in[114] la_data_in[115] la_data_in[116]
++ la_data_in[117] la_data_in[118] la_data_in[119] la_data_in[11] la_data_in[120] la_data_in[121]
++ la_data_in[122] la_data_in[123] la_data_in[124] la_data_in[125] la_data_in[126]
++ la_data_in[127] la_data_in[12] la_data_in[13] la_data_in[14] la_data_in[15] la_data_in[16]
++ la_data_in[17] la_data_in[18] la_data_in[19] la_data_in[1] la_data_in[20] la_data_in[21]
++ la_data_in[22] la_data_in[23] la_data_in[24] la_data_in[25] la_data_in[26] la_data_in[27]
++ la_data_in[28] la_data_in[29] la_data_in[2] la_data_in[30] la_data_in[31] la_data_in[32]
++ la_data_in[33] la_data_in[34] la_data_in[35] la_data_in[36] la_data_in[37] la_data_in[38]
++ la_data_in[39] la_data_in[3] la_data_in[40] la_data_in[41] la_data_in[42] la_data_in[43]
++ la_data_in[44] la_data_in[45] la_data_in[46] la_data_in[47] la_data_in[48] la_data_in[49]
++ la_data_in[4] la_data_in[50] la_data_in[51] la_data_in[52] la_data_in[53] la_data_in[54]
++ la_data_in[55] la_data_in[56] la_data_in[57] la_data_in[58] la_data_in[59] la_data_in[5]
++ la_data_in[60] la_data_in[61] la_data_in[62] la_data_in[63] la_data_in[64] la_data_in[65]
++ la_data_in[66] la_data_in[67] la_data_in[68] la_data_in[69] la_data_in[6] la_data_in[70]
++ la_data_in[71] la_data_in[72] la_data_in[73] la_data_in[74] la_data_in[75] la_data_in[76]
++ la_data_in[77] la_data_in[78] la_data_in[79] la_data_in[7] la_data_in[80] la_data_in[81]
++ la_data_in[82] la_data_in[83] la_data_in[84] la_data_in[85] la_data_in[86] la_data_in[87]
++ la_data_in[88] la_data_in[89] la_data_in[8] la_data_in[90] la_data_in[91] la_data_in[92]
++ la_data_in[93] la_data_in[94] la_data_in[95] la_data_in[96] la_data_in[97] la_data_in[98]
++ la_data_in[99] la_data_in[9] la_data_out[0] la_data_out[100] la_data_out[101] la_data_out[102]
++ la_data_out[103] la_data_out[104] la_data_out[105] la_data_out[106] la_data_out[107]
++ la_data_out[108] la_data_out[109] la_data_out[10] la_data_out[110] la_data_out[111]
++ la_data_out[112] la_data_out[113] la_data_out[114] la_data_out[115] la_data_out[116]
++ la_data_out[117] la_data_out[118] la_data_out[119] la_data_out[11] la_data_out[120]
++ la_data_out[121] la_data_out[122] la_data_out[123] la_data_out[124] la_data_out[125]
++ la_data_out[126] la_data_out[127] la_data_out[12] la_data_out[13] la_data_out[14]
++ la_data_out[15] la_data_out[16] la_data_out[17] la_data_out[18] la_data_out[19]
++ la_data_out[1] la_data_out[20] la_data_out[21] la_data_out[22] la_data_out[23] la_data_out[24]
++ la_data_out[25] la_data_out[26] la_data_out[27] la_data_out[28] la_data_out[29]
++ la_data_out[2] la_data_out[30] la_data_out[31] la_data_out[32] la_data_out[33] la_data_out[34]
++ la_data_out[35] la_data_out[36] la_data_out[37] la_data_out[38] la_data_out[39]
++ la_data_out[3] la_data_out[40] la_data_out[41] la_data_out[42] la_data_out[43] la_data_out[44]
++ la_data_out[45] la_data_out[46] la_data_out[47] la_data_out[48] la_data_out[49]
++ la_data_out[4] la_data_out[50] la_data_out[51] la_data_out[52] la_data_out[53] la_data_out[54]
++ la_data_out[55] la_data_out[56] la_data_out[57] la_data_out[58] la_data_out[59]
++ la_data_out[5] la_data_out[60] la_data_out[61] la_data_out[62] la_data_out[63] la_data_out[64]
++ la_data_out[65] la_data_out[66] la_data_out[67] la_data_out[68] la_data_out[69]
++ la_data_out[6] la_data_out[70] la_data_out[71] la_data_out[72] la_data_out[73] la_data_out[74]
++ la_data_out[75] la_data_out[76] la_data_out[77] la_data_out[78] la_data_out[79]
++ la_data_out[7] la_data_out[80] la_data_out[81] la_data_out[82] la_data_out[83] la_data_out[84]
++ la_data_out[85] la_data_out[86] la_data_out[87] la_data_out[88] la_data_out[89]
++ la_data_out[8] la_data_out[90] la_data_out[91] la_data_out[92] la_data_out[93] la_data_out[94]
++ la_data_out[95] la_data_out[96] la_data_out[97] la_data_out[98] la_data_out[99]
++ la_data_out[9] la_oenb[0] la_oenb[100] la_oenb[101] la_oenb[102] la_oenb[103] la_oenb[104]
++ la_oenb[105] la_oenb[106] la_oenb[107] la_oenb[108] la_oenb[109] la_oenb[10] la_oenb[110]
++ la_oenb[111] la_oenb[112] la_oenb[113] la_oenb[114] la_oenb[115] la_oenb[116] la_oenb[117]
++ la_oenb[118] la_oenb[119] la_oenb[11] la_oenb[120] la_oenb[121] la_oenb[122] la_oenb[123]
++ la_oenb[124] la_oenb[125] la_oenb[126] la_oenb[127] la_oenb[12] la_oenb[13] la_oenb[14]
++ la_oenb[15] la_oenb[16] la_oenb[17] la_oenb[18] la_oenb[19] la_oenb[1] la_oenb[20]
++ la_oenb[21] la_oenb[22] la_oenb[23] la_oenb[24] la_oenb[25] la_oenb[26] la_oenb[27]
++ la_oenb[28] la_oenb[29] la_oenb[2] la_oenb[30] la_oenb[31] la_oenb[32] la_oenb[33]
++ la_oenb[34] la_oenb[35] la_oenb[36] la_oenb[37] la_oenb[38] la_oenb[39] la_oenb[3]
++ la_oenb[40] la_oenb[41] la_oenb[42] la_oenb[43] la_oenb[44] la_oenb[45] la_oenb[46]
++ la_oenb[47] la_oenb[48] la_oenb[49] la_oenb[4] la_oenb[50] la_oenb[51] la_oenb[52]
++ la_oenb[53] la_oenb[54] la_oenb[55] la_oenb[56] la_oenb[57] la_oenb[58] la_oenb[59]
++ la_oenb[5] la_oenb[60] la_oenb[61] la_oenb[62] la_oenb[63] la_oenb[64] la_oenb[65]
++ la_oenb[66] la_oenb[67] la_oenb[68] la_oenb[69] la_oenb[6] la_oenb[70] la_oenb[71]
++ la_oenb[72] la_oenb[73] la_oenb[74] la_oenb[75] la_oenb[76] la_oenb[77] la_oenb[78]
++ la_oenb[79] la_oenb[7] la_oenb[80] la_oenb[81] la_oenb[82] la_oenb[83] la_oenb[84]
++ la_oenb[85] la_oenb[86] la_oenb[87] la_oenb[88] la_oenb[89] la_oenb[8] la_oenb[90]
++ la_oenb[91] la_oenb[92] la_oenb[93] la_oenb[94] la_oenb[95] la_oenb[96] la_oenb[97]
++ la_oenb[98] la_oenb[99] la_oenb[9] user_clock2 user_irq[0] user_irq[1] user_irq[2]
++ vccd1 vccd2 vdda1 vdda2 vssa1 vssa2 vssd1 vssd2 wb_clk_i wb_rst_i wbs_ack_o wbs_adr_i[0]
++ wbs_adr_i[10] wbs_adr_i[11] wbs_adr_i[12] wbs_adr_i[13] wbs_adr_i[14] wbs_adr_i[15]
++ wbs_adr_i[16] wbs_adr_i[17] wbs_adr_i[18] wbs_adr_i[19] wbs_adr_i[1] wbs_adr_i[20]
++ wbs_adr_i[21] wbs_adr_i[22] wbs_adr_i[23] wbs_adr_i[24] wbs_adr_i[25] wbs_adr_i[26]
++ wbs_adr_i[27] wbs_adr_i[28] wbs_adr_i[29] wbs_adr_i[2] wbs_adr_i[30] wbs_adr_i[31]
++ wbs_adr_i[3] wbs_adr_i[4] wbs_adr_i[5] wbs_adr_i[6] wbs_adr_i[7] wbs_adr_i[8] wbs_adr_i[9]
++ wbs_cyc_i wbs_dat_i[0] wbs_dat_i[10] wbs_dat_i[11] wbs_dat_i[12] wbs_dat_i[13] wbs_dat_i[14]
++ wbs_dat_i[15] wbs_dat_i[16] wbs_dat_i[17] wbs_dat_i[18] wbs_dat_i[19] wbs_dat_i[1]
++ wbs_dat_i[20] wbs_dat_i[21] wbs_dat_i[22] wbs_dat_i[23] wbs_dat_i[24] wbs_dat_i[25]
++ wbs_dat_i[26] wbs_dat_i[27] wbs_dat_i[28] wbs_dat_i[29] wbs_dat_i[2] wbs_dat_i[30]
++ wbs_dat_i[31] wbs_dat_i[3] wbs_dat_i[4] wbs_dat_i[5] wbs_dat_i[6] wbs_dat_i[7] wbs_dat_i[8]
++ wbs_dat_i[9] wbs_dat_o[0] wbs_dat_o[10] wbs_dat_o[11] wbs_dat_o[12] wbs_dat_o[13]
++ wbs_dat_o[14] wbs_dat_o[15] wbs_dat_o[16] wbs_dat_o[17] wbs_dat_o[18] wbs_dat_o[19]
++ wbs_dat_o[1] wbs_dat_o[20] wbs_dat_o[21] wbs_dat_o[22] wbs_dat_o[23] wbs_dat_o[24]
++ wbs_dat_o[25] wbs_dat_o[26] wbs_dat_o[27] wbs_dat_o[28] wbs_dat_o[29] wbs_dat_o[2]
++ wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6]
++ wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3]
++ wbs_stb_i wbs_we_i
+Xbuffer_1_0 vccd1 L1 comparator_SA_0/Outn vssa1 buffer_1#0
+Xbuffer_1_1 vccd1 L2 comparator_SA_0/Outp vssa1 buffer_1#0
+Xbuffer_12_0 comparator_SA_0/CLK io_analog[8] vccd1 vssa1 buffer_12
+Xbuffer_12_1 io_analog[1] inv_W1_0/Vout vccd1 vssa1 buffer_12
+Xcomparator_SA_0 comparator_SA_0/Outn io_analog[5] io_analog[6] comparator_SA_0/CLK
++ vccd1 vssa1 comparator_SA_0/Outp comparator_SA
+Xinv_W1_0 inv_W1_0/Vout io_analog[8] vccd1 vssa1 inv_W1
+Xbuffer_2_0 io_analog[3] vccd1 vccd1 L1 vssa1 vssa1 buffer_2#0
+Xbuffer_2_1 io_analog[2] vccd1 vccd1 L2 vssa1 vssa1 buffer_2#1
+V0 vssa1 io_clamp_low[1] 0.0
+V1 vssa1 io_clamp_low[2] 0.0
+V2 vccd1 io_clamp_high[2] 0.0
+V3 vccd1 io_clamp_high[1] 0.0
+C0 vccd1 io_analog[5] 565.79fF
+C1 vssa1 io_analog[6] 61.52fF
+C2 vssa1 io_analog[1] 7.75fF
+C3 comparator_SA_0/CLK vccd1 13.91fF
+C4 vccd1 comparator_SA_0/Outn 66.73fF
+C5 vccd1 io_analog[3] 35.18fF
+C6 vssa1 io_analog[5] 63.24fF
+C7 vssa1 vccd1 285.36fF
+C8 vccd1 comparator_SA_0/Outp 66.83fF
+C9 vccd1 io_analog[6] 520.22fF
+C10 vccd1 io_analog[1] 66.42fF
+C11 vccd1 io_analog[2] 35.31fF
+C12 vssa1 L1 13.68fF
+C13 vssa1 L2 17.20fF
+C14 comparator_SA_0/CLK io_analog[6] 3.15fF
+C15 io_analog[4] 0 25.05fF
+C16 vssd2 0 13.04fF
+C17 vssd1 0 13.62fF
+C18 vdda2 0 13.04fF
+C19 vdda1 0 26.08fF
+C20 vssa2 0 13.04fF
+C21 io_analog[0] 0 6.83fF
+C22 io_clamp_high[0] 0 3.58fF
+C23 io_clamp_low[0] 0 3.58fF
+C24 vccd2 0 13.04fF
+C25 io_analog[10] 0 6.83fF
+C26 io_analog[7] 0 8.28fF
+C27 io_analog[9] 0 6.98fF
+C28 io_analog[2] 0 20.75fF
+C29 L2 0 86.93fF
+C30 io_analog[3] 0 20.96fF
+C31 L1 0 96.89fF
+C32 io_analog[8] 0 283.16fF
+C33 comparator_SA_0/Outp 0 110.68fF
+C34 comparator_SA_0/Outn 0 103.95fF
+C35 io_analog[5] 0 282.40fF
+C36 io_analog[6] 0 292.62fF
+C37 io_analog[1] 0 408.98fF
+C38 vccd1 0 2370.36fF
+C39 vssa1 0 1810.15fF
+C40 inv_W1_0/Vout 0 2.80fF
+C41 comparator_SA_0/CLK 0 162.51fF
+.ends
+
diff --git a/netgen/run_lvs_por.sh b/netgen/run_lvs_por.sh
new file mode 100755
index 0000000..1bf43a0
--- /dev/null
+++ b/netgen/run_lvs_por.sh
@@ -0,0 +1,24 @@
+#!/bin/sh
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+#--------------------------------------------------------------------------------
+# Run LVS on the example_por layout
+#
+# NOTE: By specifying the testbench for the schematic-side netlist, the proper
+# includes used by the testbench simulation are picked up. Otherwise, the LVS
+# itself compares just the simple_por subcircuit from the testbench.
+#--------------------------------------------------------------------------------
+netgen -batch lvs "example_por.spice comparator_SA" "../xschem/comparator_lvs.spice comparator_lvs" /usr/local/share/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl comp.out
diff --git a/netgen/run_lvs_wrapper_verilog.sh b/netgen/run_lvs_wrapper_verilog.sh
new file mode 100755
index 0000000..f093ac3
--- /dev/null
+++ b/netgen/run_lvs_wrapper_verilog.sh
@@ -0,0 +1,22 @@
+#!/bin/sh
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+#--------------------------------------------------------------------------------
+# Run LVS on the user_analog_project_wrapper layout, comparing against the
+# top-level verilog module.
+#
+#--------------------------------------------------------------------------------
+netgen -batch lvs "user_analog_project_wrapper.spice user_analog_project_wrapper" "../verilog/rtl/user_analog_project_wrapper.v user_analog_project_wrapper" /usr/local/share/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl comp.out
diff --git a/netgen/run_lvs_wrapper_xschem.sh b/netgen/run_lvs_wrapper_xschem.sh
new file mode 100755
index 0000000..c741050
--- /dev/null
+++ b/netgen/run_lvs_wrapper_xschem.sh
@@ -0,0 +1,22 @@
+#!/bin/sh
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+#--------------------------------------------------------------------------------
+# Run LVS on the user_analog_project_wrapper layout, comparing against the
+# top-level xschem subcircuit from the wrapper testbench.
+#
+#--------------------------------------------------------------------------------
+netgen -batch lvs "user_analog_project_wrapper.spice user_analog_project_wrapper" "../xschem/analog_wrapper_tb.spice user_analog_project_wrapper" /usr/local/share/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl comp.out
diff --git a/netgen/user_analog_project_wrapper.spice b/netgen/user_analog_project_wrapper.spice
new file mode 100644
index 0000000..2f4b8a1
--- /dev/null
+++ b/netgen/user_analog_project_wrapper.spice
@@ -0,0 +1,442 @@
+* SPICE3 file created from user_analog_project_wrapper.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_AC5Z8B a_159_n100# li_217_n290# li_n261_n290# li_229_174#
++ a_n221_n74# a_n129_n100# a_n159_n152# li_225_n726# a_n33_n100# w_n261_n210# li_n261_174#
++ li_n261_n726# VSUBS
+X0 a_n129_n100# a_n159_n152# a_n33_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5.32e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n159_n152# a_n129_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_159_n100# a_n159_n152# a_n129_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n129_n100# a_n159_n152# a_n221_n74# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_XJTKXQ a_33_n122# a_n63_n122# a_63_n100# a_n125_n74#
++ a_n33_n100# VSUBS
+X0 a_63_n100# a_33_n122# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n122# a_n125_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt inv_W2 sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210# Vout Vin VDD GND VSUBS
+Xsky130_fd_pr__pfet_01v8_AC5Z8B_0 VDD Vout Vin VDD VDD Vout Vin GND VDD sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#
++ VDD GND VSUBS sky130_fd_pr__pfet_01v8_AC5Z8B
+Xsky130_fd_pr__nfet_01v8_XJTKXQ_0 Vin Vin GND GND Vout VSUBS sky130_fd_pr__nfet_01v8_XJTKXQ
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7RYEVP a_n73_n69# a_n15_n89# a_15_n69# VSUBS
+X0 a_15_n69# a_n15_n89# a_n73_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt nmos_1u sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS sky130_fd_pr__nfet_01v8_7RYEVP_0/a_n15_n89#
++ sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#
+Xsky130_fd_pr__nfet_01v8_7RYEVP_0 sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS sky130_fd_pr__nfet_01v8_7RYEVP_0/a_n15_n89#
++ sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69# sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS
++ sky130_fd_pr__nfet_01v8_7RYEVP
+.ends
+
+.subckt pmos_2uf2 a_63_n100# a_33_n130# w_n317_n202# a_n33_n100# a_n63_n130# VSUBS
+X0 a_63_n100# a_33_n130# a_n33_n100# w_n317_n202# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n130# w_n317_n202# w_n317_n202# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.8e+11p ps=2.76e+06u w=1e+06u l=150000u
+.ends
+
+.subckt inv_W1 Vout Vin VDD GND
+Xnmos_1u_0 GND Vin Vout nmos_1u
+Xpmos_2uf2_0 VDD Vin VDD Vout Vin GND pmos_2uf2
+.ends
+
+.subckt buffer_1#0 inv_W2_0/VDD inv_W2_0/Vout inv_W1_0/Vin VSUBS
+Xinv_W2_0 inv_W2_0/VDD inv_W2_0/Vout inv_W2_0/Vin inv_W2_0/VDD VSUBS VSUBS inv_W2
+Xinv_W1_0 inv_W2_0/Vin inv_W1_0/Vin inv_W2_0/VDD VSUBS inv_W1
+.ends
+
+.subckt inv_W1#0 Vout Vin VDD GND
+Xnmos_1u_0 GND Vin Vout nmos_1u
+Xpmos_2uf2_0 VDD Vin VDD Vout Vin GND pmos_2uf2
+.ends
+
+.subckt buffer_1 inv_W2_0/Vout inv_W1_0/Vin VSUBS inv_W2_0/VDD
+Xinv_W2_0 inv_W2_0/VDD inv_W2_0/Vout inv_W2_0/Vin inv_W2_0/VDD VSUBS VSUBS inv_W2
+Xinv_W1_0 inv_W2_0/Vin inv_W1_0/Vin inv_W2_0/VDD VSUBS inv_W1#0
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KZU588 a_159_n100# a_255_n100# a_351_n100# a_n129_n100#
++ a_63_n100# li_321_116# a_n353_n162# a_n225_n100# a_n413_n74# a_n321_n100# a_n33_n100#
++ VSUBS
+X0 a_n321_n100# a_n353_n162# a_n413_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+X1 a_n225_n100# a_n353_n162# a_n321_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n129_n100# a_n353_n162# a_n225_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X3 a_63_n100# a_n353_n162# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X4 a_n33_n100# a_n353_n162# a_n129_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_351_n100# a_n353_n162# a_255_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X6 a_159_n100# a_n353_n162# a_63_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X7 a_255_n100# a_n353_n162# a_159_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_RL4NCG a_543_n100# a_159_n100# a_n609_n100# a_321_n126#
++ a_n705_n100# a_255_n100# a_n159_n128# a_n543_n128# a_n255_n126# a_351_n100# a_n417_n100#
++ a_33_n128# a_n129_n100# a_n513_n100# a_n351_n128# a_63_n100# w_n833_n200# a_n225_n100#
++ a_609_n128# a_n63_n126# a_n797_n74# a_705_n126# a_n321_n100# a_639_n100# a_417_n128#
++ a_n639_n126# a_735_n100# a_n33_n100# a_513_n126# a_129_n126# a_447_n100# a_n735_n128#
++ a_n447_n126# a_225_n128# VSUBS
+X0 a_63_n100# a_33_n128# a_n33_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n126# a_n129_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_255_n100# a_225_n128# a_159_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X3 a_351_n100# a_321_n126# a_255_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X4 a_543_n100# a_513_n126# a_447_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X5 a_159_n100# a_129_n126# a_63_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_447_n100# a_417_n128# a_351_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_639_n100# a_609_n128# a_543_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X8 a_735_n100# a_705_n126# a_639_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X9 a_n513_n100# a_n543_n128# a_n609_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X10 a_n321_n100# a_n351_n128# a_n417_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X11 a_n225_n100# a_n255_n126# a_n321_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X12 a_n705_n100# a_n735_n128# a_n797_n74# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+X13 a_n609_n100# a_n639_n126# a_n705_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X14 a_n417_n100# a_n447_n126# a_n513_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X15 a_n129_n100# a_n159_n128# a_n225_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt inv_W8 li_354_902# w_354_500# li_354_0# li_512_546# a_804_430# VSUBS
+Xsky130_fd_pr__nfet_01v8_KZU588_0 li_354_0# li_512_546# li_354_0# li_512_546# li_512_546#
++ li_512_546# a_804_430# li_354_0# li_354_0# li_512_546# li_354_0# VSUBS sky130_fd_pr__nfet_01v8_KZU588
+Xsky130_fd_pr__pfet_01v8_RL4NCG_0 li_354_902# li_354_902# li_354_902# a_804_430# li_512_546#
++ li_512_546# a_804_430# a_804_430# a_804_430# li_354_902# li_354_902# a_804_430#
++ li_512_546# li_512_546# a_804_430# li_512_546# w_354_500# li_354_902# a_804_430#
++ a_804_430# li_354_902# a_804_430# li_512_546# li_512_546# a_804_430# a_804_430#
++ li_354_902# li_354_902# a_804_430# a_804_430# li_512_546# a_804_430# a_804_430#
++ a_804_430# VSUBS sky130_fd_pr__pfet_01v8_RL4NCG
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_VJWT33 a_543_n100# a_159_n100# a_n609_n100# a_n705_n100#
++ a_255_n100# a_351_n100# a_n417_n100# a_n129_n100# a_n513_n100# a_63_n100# a_n225_n100#
++ a_n797_n74# a_n735_n176# a_n321_n100# a_639_n100# a_735_n100# a_n33_n100# a_447_n100#
++ VSUBS
+X0 a_n513_n100# a_n735_n176# a_n609_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n321_n100# a_n735_n176# a_n417_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_n225_n100# a_n735_n176# a_n321_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n705_n100# a_n735_n176# a_n797_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+X4 a_n609_n100# a_n735_n176# a_n705_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_n417_n100# a_n735_n176# a_n513_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_n129_n100# a_n735_n176# a_n225_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X7 a_63_n100# a_n735_n176# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X8 a_n33_n100# a_n735_n176# a_n129_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X9 a_351_n100# a_n735_n176# a_255_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X10 a_159_n100# a_n735_n176# a_63_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X11 a_255_n100# a_n735_n176# a_159_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X12 a_447_n100# a_n735_n176# a_351_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X13 a_543_n100# a_n735_n176# a_447_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X14 a_639_n100# a_n735_n176# a_543_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X15 a_735_n100# a_n735_n176# a_639_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_3M44SC a_543_n100# a_159_n100# a_n609_n100# a_321_n126#
++ a_1473_n126# a_1089_n126# a_n1407_n126# a_n705_n100# a_255_n100# a_n159_n128# a_n543_n128#
++ a_1407_n100# a_1185_n128# a_n255_n126# a_351_n100# a_n417_n100# a_n801_n100# a_n1119_n128#
++ a_n1503_n128# a_1281_n126# a_897_n126# a_33_n128# w_n1601_n200# a_1503_n100# a_1119_n100#
++ a_n1377_n100# a_n1215_n126# a_n129_n100# a_n513_n100# a_n351_n128# a_n1565_n74#
++ a_1215_n100# a_63_n100# a_n1089_n100# a_n1473_n100# a_993_n128# a_n225_n100# a_609_n128#
++ a_n63_n126# a_n1311_n128# a_1311_n100# a_927_n100# a_n1185_n100# a_705_n126# a_n1023_n126#
++ a_n321_n100# a_1023_n100# a_639_n100# a_n1281_n100# a_n927_n128# a_801_n128# a_417_n128#
++ a_n639_n126# a_735_n100# a_n33_n100# a_513_n126# a_129_n126# a_n897_n100# a_831_n100#
++ a_447_n100# a_n735_n128# a_n993_n100# a_n447_n126# a_n831_n126# a_1377_n128# a_225_n128#
++ VSUBS
+X0 a_63_n100# a_33_n128# a_n33_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_927_n100# a_897_n126# a_831_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_1023_n100# a_993_n128# a_927_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X3 a_1311_n100# a_1281_n126# a_1215_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X4 a_1119_n100# a_1089_n126# a_1023_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X5 a_1215_n100# a_1185_n128# a_1119_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_1407_n100# a_1377_n128# a_1311_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X7 a_1503_n100# a_1473_n126# a_1407_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X8 a_n33_n100# a_n63_n126# a_n129_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X9 a_255_n100# a_225_n128# a_159_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X10 a_351_n100# a_321_n126# a_255_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X11 a_543_n100# a_513_n126# a_447_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X12 a_831_n100# a_801_n128# a_735_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X13 a_159_n100# a_129_n126# a_63_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X14 a_447_n100# a_417_n128# a_351_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X15 a_639_n100# a_609_n128# a_543_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X16 a_735_n100# a_705_n126# a_639_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X17 a_n1281_n100# a_n1311_n128# a_n1377_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X18 a_n993_n100# a_n1023_n126# a_n1089_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X19 a_n1473_n100# a_n1503_n128# a_n1565_n74# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+X20 a_n1377_n100# a_n1407_n126# a_n1473_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X21 a_n1185_n100# a_n1215_n126# a_n1281_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X22 a_n1089_n100# a_n1119_n128# a_n1185_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X23 a_n801_n100# a_n831_n126# a_n897_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X24 a_n513_n100# a_n543_n128# a_n609_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X25 a_n321_n100# a_n351_n128# a_n417_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X26 a_n225_n100# a_n255_n126# a_n321_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X27 a_n897_n100# a_n927_n128# a_n993_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X28 a_n705_n100# a_n735_n128# a_n801_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X29 a_n609_n100# a_n639_n126# a_n705_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X30 a_n417_n100# a_n447_n126# a_n513_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X31 a_n129_n100# a_n159_n128# a_n225_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+
+.ends
+
+.subckt inv_W16 li_128_546# li_n14_902# a_82_816# w_82_814# li_n14_0# VSUBS
+Xsky130_fd_pr__nfet_01v8_VJWT33_0 li_n14_0# li_n14_0# li_n14_0# li_128_546# li_128_546#
++ li_n14_0# li_n14_0# li_128_546# li_128_546# li_128_546# li_n14_0# li_n14_0# a_82_816#
++ li_128_546# li_128_546# li_n14_0# li_n14_0# li_128_546# VSUBS sky130_fd_pr__nfet_01v8_VJWT33
+Xsky130_fd_pr__pfet_01v8_3M44SC_0 li_n14_902# li_n14_902# li_n14_902# a_82_816# a_82_816#
++ a_82_816# a_82_816# li_128_546# li_128_546# a_82_816# a_82_816# li_128_546# a_82_816#
++ a_82_816# li_n14_902# li_n14_902# li_n14_902# a_82_816# a_82_816# a_82_816# a_82_816#
++ a_82_816# w_82_814# li_n14_902# li_n14_902# li_n14_902# a_82_816# li_128_546# li_128_546#
++ a_82_816# li_n14_902# li_128_546# li_128_546# li_128_546# li_128_546# a_82_816#
++ li_n14_902# a_82_816# a_82_816# a_82_816# li_n14_902# li_n14_902# li_n14_902# a_82_816#
++ a_82_816# li_128_546# li_128_546# li_128_546# li_128_546# a_82_816# a_82_816# a_82_816#
++ a_82_816# li_n14_902# li_n14_902# a_82_816# a_82_816# li_128_546# li_128_546# li_128_546#
++ a_82_816# li_n14_902# a_82_816# a_82_816# a_82_816# a_82_816# VSUBS sky130_fd_pr__pfet_01v8_3M44SC
+
+.ends
+
+.subckt buffer_2 Vout inv_W8_0/li_354_902# w_1666_500# inv_W8_0/a_804_430# inv_W8_0/li_354_0#
++ VSUBS
+Xinv_W8_0 inv_W8_0/li_354_902# w_1666_500# inv_W8_0/li_354_0# inv_W16_0/a_82_816#
++ inv_W8_0/a_804_430# VSUBS inv_W8
+Xinv_W16_0 Vout inv_W8_0/li_354_902# inv_W16_0/a_82_816# w_1666_500# inv_W8_0/li_354_0#
++ VSUBS inv_W16
+
+.ends
+
+.subckt buffer_12 buf_out buf_in VDD GND
+Xbuffer_1_0 buffer_1_0/inv_W2_0/Vout buf_in GND VDD buffer_1
+Xbuffer_2_0 buf_out VDD VDD buffer_1_0/inv_W2_0/Vout GND GND buffer_2
+
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_G6PLX8 a_159_n100# li_n945_n316# a_n221_n74# a_n129_n100#
++ a_63_n100# a_n159_n156# a_n33_n100# VSUBS
+X0 a_n129_n100# a_n159_n156# a_n221_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+X1 a_63_n100# a_n159_n156# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_n33_n100# a_n159_n156# a_n129_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_159_n100# a_n159_n156# a_63_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_NHLLAS a_n63_n153# a_n129_n133# a_63_n133# a_129_n153#
++ a_n221_n96# a_n33_n133# a_n159_n153# a_159_n133# a_33_n153# VSUBS
+X0 a_159_n133# a_129_n153# a_63_n133# VSUBS sky130_fd_pr__nfet_01v8 ad=4.049e+11p pd=3.28e+06u as=4.389e+11p ps=3.32e+06u w=1.33e+06u l=150000u
+X1 a_63_n133# a_33_n153# a_n33_n133# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=4.389e+11p ps=3.32e+06u w=1.33e+06u l=150000u
+X2 a_n129_n133# a_n159_n153# a_n221_n96# VSUBS sky130_fd_pr__nfet_01v8 ad=4.389e+11p pd=3.32e+06u as=4.049e+11p ps=3.28e+06u w=1.33e+06u l=150000u
+X3 a_n33_n133# a_n63_n153# a_n129_n133# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.33e+06u l=150000u
+.ends
+
+.subckt preamp_part1SA m1_n694_236# a_n734_300# li_126_310# m1_924_192# a_80_354#
++ a_976_302# a_n302_940# w_n720_482# a_506_940# li_318_312# li_n66_312# VSUBS
+Xsky130_fd_pr__nfet_01v8_G6PLX8_0 li_318_312# li_n24_n74# li_n66_312# li_n24_n74#
++ li_n24_n74# a_80_354# li_126_310# VSUBS sky130_fd_pr__nfet_01v8_G6PLX8
+Xsky130_fd_pr__nfet_01v8_NHLLAS_0 a_n734_300# m1_n694_236# m1_n694_236# a_n734_300#
++ li_n24_n74# li_n24_n74# a_n734_300# li_n24_n74# a_n734_300# VSUBS sky130_fd_pr__nfet_01v8_NHLLAS
+Xsky130_fd_pr__nfet_01v8_NHLLAS_1 a_976_302# m1_924_192# m1_924_192# a_976_302# li_n24_n74#
++ li_n24_n74# a_976_302# li_n24_n74# a_976_302# VSUBS sky130_fd_pr__nfet_01v8_NHLLAS
+
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_5233FE a_n15_n76# w_n109_n112# a_n73_n50# a_15_n50#
++ VSUBS
+X0 a_15_n50# a_n15_n76# a_n73_n50# w_n109_n112# sky130_fd_pr__pfet_01v8 ad=1.45e+11p pd=1.58e+06u as=1.45e+11p ps=1.58e+06u w=500000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_F5U58G a_n73_n100# a_15_n100# a_n15_n126# VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AC5E9B w_n161_n200# a_33_n126# a_63_n100# a_n125_n74#
++ a_n33_n100# a_n63_n130# VSUBS
+X0 a_63_n100# a_33_n126# a_n33_n100# w_n161_n200# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n130# a_n125_n74# w_n161_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt SR_latch a_648_848# sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126# sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#
++ a_262_508# VDD w_0_524# GND VSUBS
+Xsky130_fd_pr__nfet_01v8_F5U58G_0 a_648_848# GND sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#
++ VSUBS sky130_fd_pr__nfet_01v8_F5U58G
+Xsky130_fd_pr__nfet_01v8_F5U58G_1 GND a_262_508# sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126#
++ VSUBS sky130_fd_pr__nfet_01v8_F5U58G
+Xsky130_fd_pr__pfet_01v8_AC5E9B_0 w_0_524# a_262_508# VDD VDD a_648_848# a_262_508#
++ VSUBS sky130_fd_pr__pfet_01v8_AC5E9B
+Xsky130_fd_pr__pfet_01v8_AC5E9B_1 w_0_524# a_648_848# VDD VDD a_262_508# a_648_848#
++ VSUBS sky130_fd_pr__pfet_01v8_AC5E9B
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_5C3Z5B a_15_n78# a_n15_n104# a_n73_n78# w_n109_n140#
++ VSUBS
+X0 a_15_n78# a_n15_n104# a_n73_n78# w_n109_n140# sky130_fd_pr__pfet_01v8 ad=2.262e+11p pd=2.14e+06u as=2.262e+11p ps=2.14e+06u w=780000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KBWVY9 a_15_n78# a_n15_n104# a_n73_n78# VSUBS
+X0 a_15_n78# a_n15_n104# a_n73_n78# VSUBS sky130_fd_pr__nfet_01v8 ad=2.262e+11p pd=2.14e+06u as=2.262e+11p ps=2.14e+06u w=780000u l=150000u
+.ends
+
+.subckt inv_W22 li_200_260# sky130_fd_pr__nfet_01v8_KBWVY9_0/a_n73_n78# sky130_fd_pr__pfet_01v8_5C3Z5B_0/w_n109_n140#
++ Vin VDD sky130_fd_pr__pfet_01v8_5C3Z5B_0/a_15_n78# VSUBS
+Xsky130_fd_pr__pfet_01v8_5C3Z5B_0 sky130_fd_pr__pfet_01v8_5C3Z5B_0/a_15_n78# Vin VDD
++ sky130_fd_pr__pfet_01v8_5C3Z5B_0/w_n109_n140# VSUBS sky130_fd_pr__pfet_01v8_5C3Z5B
+Xsky130_fd_pr__nfet_01v8_KBWVY9_0 li_200_260# Vin sky130_fd_pr__nfet_01v8_KBWVY9_0/a_n73_n78#
++ VSUBS sky130_fd_pr__nfet_01v8_KBWVY9
+.ends
+
+.subckt latch_2SA inv_W22_0/sky130_fd_pr__pfet_01v8_5C3Z5B_0/a_15_n78# w_0_516# inv_W22_0/Vin
++ inv_W22_1/li_200_260# inv_W22_1/sky130_fd_pr__nfet_01v8_KBWVY9_0/a_n73_n78# inv_W22_0/sky130_fd_pr__nfet_01v8_KBWVY9_0/a_n73_n78#
++ inv_W22_0/li_200_260# inv_W22_1/Vin inv_W22_1/VDD inv_W22_1/sky130_fd_pr__pfet_01v8_5C3Z5B_0/a_15_n78#
++ VSUBS
+Xinv_W22_0 inv_W22_0/li_200_260# inv_W22_0/sky130_fd_pr__nfet_01v8_KBWVY9_0/a_n73_n78#
++ w_0_516# inv_W22_0/Vin inv_W22_1/VDD inv_W22_0/sky130_fd_pr__pfet_01v8_5C3Z5B_0/a_15_n78#
++ VSUBS inv_W22
+Xinv_W22_1 inv_W22_1/li_200_260# inv_W22_1/sky130_fd_pr__nfet_01v8_KBWVY9_0/a_n73_n78#
++ w_0_516# inv_W22_1/Vin inv_W22_1/VDD inv_W22_1/sky130_fd_pr__pfet_01v8_5C3Z5B_0/a_15_n78#
++ VSUBS inv_W22
+.ends
+
+.subckt comparator_SA Outn Vp Vn CLK VDD GND Outp
+Xpreamp_part1SA_0 fn Vn GND fp CLK Vp CLK VDD CLK GND GND GND preamp_part1SA
+Xsky130_fd_pr__pfet_01v8_5233FE_0 CLK VDD VDD fn GND sky130_fd_pr__pfet_01v8_5233FE
+Xsky130_fd_pr__pfet_01v8_5233FE_1 CLK VDD fp VDD GND sky130_fd_pr__pfet_01v8_5233FE
+Xsky130_fd_pr__pfet_01v8_5233FE_2 CLK VDD VDD Dn GND sky130_fd_pr__pfet_01v8_5233FE
+Xsky130_fd_pr__pfet_01v8_5233FE_3 CLK VDD VDD Dp GND sky130_fd_pr__pfet_01v8_5233FE
+XSR_latch_0 Outp Ln Lp Outn VDD VDD GND GND SR_latch
+Xinv_W1_0 Lp Dp VDD GND inv_W1
+Xinv_W1_1 Ln Dn VDD GND inv_W1
+Xlatch_2SA_0 Dn VDD Dp Dp fp fn Dn Dn VDD Dp GND latch_2SA
+
+.ends
+
+.subckt buffer_2#0 Vout w_1666_500# inv_W8_0/li_354_902# inv_W8_0/a_804_430# inv_W8_0/li_354_0#
++ VSUBS
+Xinv_W8_0 inv_W8_0/li_354_902# w_1666_500# inv_W8_0/li_354_0# inv_W16_0/a_82_816#
++ inv_W8_0/a_804_430# VSUBS inv_W8
+Xinv_W16_0 Vout inv_W8_0/li_354_902# inv_W16_0/a_82_816# w_1666_500# inv_W8_0/li_354_0#
++ VSUBS inv_W16
+
+.ends
+
+.subckt buffer_2#1 Vout w_1666_500# inv_W8_0/li_354_902# inv_W8_0/a_804_430# inv_W8_0/li_354_0#
++ VSUBS
+Xinv_W8_0 inv_W8_0/li_354_902# w_1666_500# inv_W8_0/li_354_0# inv_W16_0/a_82_816#
++ inv_W8_0/a_804_430# VSUBS inv_W8
+Xinv_W16_0 Vout inv_W8_0/li_354_902# inv_W16_0/a_82_816# w_1666_500# inv_W8_0/li_354_0#
++ VSUBS inv_W16
+
+.ends
+
+.subckt user_analog_project_wrapper gpio_analog[0] gpio_analog[10] gpio_analog[11]
++ gpio_analog[12] gpio_analog[13] gpio_analog[14] gpio_analog[15] gpio_analog[16]
++ gpio_analog[17] gpio_analog[1] gpio_analog[2] gpio_analog[3] gpio_analog[4] gpio_analog[5]
++ gpio_analog[6] gpio_analog[7] gpio_analog[8] gpio_analog[9] gpio_noesd[0] gpio_noesd[10]
++ gpio_noesd[11] gpio_noesd[12] gpio_noesd[13] gpio_noesd[14] gpio_noesd[15] gpio_noesd[16]
++ gpio_noesd[17] gpio_noesd[1] gpio_noesd[2] gpio_noesd[3] gpio_noesd[4] gpio_noesd[5]
++ gpio_noesd[6] gpio_noesd[7] gpio_noesd[8] gpio_noesd[9] io_analog[0] io_analog[10]
++ io_analog[1] io_analog[2] io_analog[3] io_analog[5] io_analog[6] io_analog[7] io_analog[8]
++ io_analog[9] io_analog[4] io_clamp_high[0] io_clamp_high[1] io_clamp_high[2] io_clamp_low[0]
++ io_clamp_low[1] io_clamp_low[2] io_in[0] io_in[10] io_in[11] io_in[12] io_in[13]
++ io_in[14] io_in[15] io_in[16] io_in[17] io_in[18] io_in[19] io_in[1] io_in[20] io_in[21]
++ io_in[22] io_in[23] io_in[24] io_in[25] io_in[26] io_in[2] io_in[3] io_in[4] io_in[5]
++ io_in[6] io_in[7] io_in[8] io_in[9] io_in_3v3[0] io_in_3v3[10] io_in_3v3[11] io_in_3v3[12]
++ io_in_3v3[13] io_in_3v3[14] io_in_3v3[15] io_in_3v3[16] io_in_3v3[17] io_in_3v3[18]
++ io_in_3v3[19] io_in_3v3[1] io_in_3v3[20] io_in_3v3[21] io_in_3v3[22] io_in_3v3[23]
++ io_in_3v3[24] io_in_3v3[25] io_in_3v3[26] io_in_3v3[2] io_in_3v3[3] io_in_3v3[4]
++ io_in_3v3[5] io_in_3v3[6] io_in_3v3[7] io_in_3v3[8] io_in_3v3[9] io_oeb[0] io_oeb[10]
++ io_oeb[11] io_oeb[12] io_oeb[13] io_oeb[14] io_oeb[15] io_oeb[16] io_oeb[17] io_oeb[18]
++ io_oeb[19] io_oeb[1] io_oeb[20] io_oeb[21] io_oeb[22] io_oeb[23] io_oeb[24] io_oeb[25]
++ io_oeb[26] io_oeb[2] io_oeb[3] io_oeb[4] io_oeb[5] io_oeb[6] io_oeb[7] io_oeb[8]
++ io_oeb[9] io_out[0] io_out[10] io_out[11] io_out[12] io_out[13] io_out[14] io_out[15]
++ io_out[16] io_out[17] io_out[18] io_out[19] io_out[1] io_out[20] io_out[21] io_out[22]
++ io_out[23] io_out[24] io_out[25] io_out[26] io_out[2] io_out[3] io_out[4] io_out[5]
++ io_out[6] io_out[7] io_out[8] io_out[9] la_data_in[0] la_data_in[100] la_data_in[101]
++ la_data_in[102] la_data_in[103] la_data_in[104] la_data_in[105] la_data_in[106]
++ la_data_in[107] la_data_in[108] la_data_in[109] la_data_in[10] la_data_in[110] la_data_in[111]
++ la_data_in[112] la_data_in[113] la_data_in[114] la_data_in[115] la_data_in[116]
++ la_data_in[117] la_data_in[118] la_data_in[119] la_data_in[11] la_data_in[120] la_data_in[121]
++ la_data_in[122] la_data_in[123] la_data_in[124] la_data_in[125] la_data_in[126]
++ la_data_in[127] la_data_in[12] la_data_in[13] la_data_in[14] la_data_in[15] la_data_in[16]
++ la_data_in[17] la_data_in[18] la_data_in[19] la_data_in[1] la_data_in[20] la_data_in[21]
++ la_data_in[22] la_data_in[23] la_data_in[24] la_data_in[25] la_data_in[26] la_data_in[27]
++ la_data_in[28] la_data_in[29] la_data_in[2] la_data_in[30] la_data_in[31] la_data_in[32]
++ la_data_in[33] la_data_in[34] la_data_in[35] la_data_in[36] la_data_in[37] la_data_in[38]
++ la_data_in[39] la_data_in[3] la_data_in[40] la_data_in[41] la_data_in[42] la_data_in[43]
++ la_data_in[44] la_data_in[45] la_data_in[46] la_data_in[47] la_data_in[48] la_data_in[49]
++ la_data_in[4] la_data_in[50] la_data_in[51] la_data_in[52] la_data_in[53] la_data_in[54]
++ la_data_in[55] la_data_in[56] la_data_in[57] la_data_in[58] la_data_in[59] la_data_in[5]
++ la_data_in[60] la_data_in[61] la_data_in[62] la_data_in[63] la_data_in[64] la_data_in[65]
++ la_data_in[66] la_data_in[67] la_data_in[68] la_data_in[69] la_data_in[6] la_data_in[70]
++ la_data_in[71] la_data_in[72] la_data_in[73] la_data_in[74] la_data_in[75] la_data_in[76]
++ la_data_in[77] la_data_in[78] la_data_in[79] la_data_in[7] la_data_in[80] la_data_in[81]
++ la_data_in[82] la_data_in[83] la_data_in[84] la_data_in[85] la_data_in[86] la_data_in[87]
++ la_data_in[88] la_data_in[89] la_data_in[8] la_data_in[90] la_data_in[91] la_data_in[92]
++ la_data_in[93] la_data_in[94] la_data_in[95] la_data_in[96] la_data_in[97] la_data_in[98]
++ la_data_in[99] la_data_in[9] la_data_out[0] la_data_out[100] la_data_out[101] la_data_out[102]
++ la_data_out[103] la_data_out[104] la_data_out[105] la_data_out[106] la_data_out[107]
++ la_data_out[108] la_data_out[109] la_data_out[10] la_data_out[110] la_data_out[111]
++ la_data_out[112] la_data_out[113] la_data_out[114] la_data_out[115] la_data_out[116]
++ la_data_out[117] la_data_out[118] la_data_out[119] la_data_out[11] la_data_out[120]
++ la_data_out[121] la_data_out[122] la_data_out[123] la_data_out[124] la_data_out[125]
++ la_data_out[126] la_data_out[127] la_data_out[12] la_data_out[13] la_data_out[14]
++ la_data_out[15] la_data_out[16] la_data_out[17] la_data_out[18] la_data_out[19]
++ la_data_out[1] la_data_out[20] la_data_out[21] la_data_out[22] la_data_out[23] la_data_out[24]
++ la_data_out[25] la_data_out[26] la_data_out[27] la_data_out[28] la_data_out[29]
++ la_data_out[2] la_data_out[30] la_data_out[31] la_data_out[32] la_data_out[33] la_data_out[34]
++ la_data_out[35] la_data_out[36] la_data_out[37] la_data_out[38] la_data_out[39]
++ la_data_out[3] la_data_out[40] la_data_out[41] la_data_out[42] la_data_out[43] la_data_out[44]
++ la_data_out[45] la_data_out[46] la_data_out[47] la_data_out[48] la_data_out[49]
++ la_data_out[4] la_data_out[50] la_data_out[51] la_data_out[52] la_data_out[53] la_data_out[54]
++ la_data_out[55] la_data_out[56] la_data_out[57] la_data_out[58] la_data_out[59]
++ la_data_out[5] la_data_out[60] la_data_out[61] la_data_out[62] la_data_out[63] la_data_out[64]
++ la_data_out[65] la_data_out[66] la_data_out[67] la_data_out[68] la_data_out[69]
++ la_data_out[6] la_data_out[70] la_data_out[71] la_data_out[72] la_data_out[73] la_data_out[74]
++ la_data_out[75] la_data_out[76] la_data_out[77] la_data_out[78] la_data_out[79]
++ la_data_out[7] la_data_out[80] la_data_out[81] la_data_out[82] la_data_out[83] la_data_out[84]
++ la_data_out[85] la_data_out[86] la_data_out[87] la_data_out[88] la_data_out[89]
++ la_data_out[8] la_data_out[90] la_data_out[91] la_data_out[92] la_data_out[93] la_data_out[94]
++ la_data_out[95] la_data_out[96] la_data_out[97] la_data_out[98] la_data_out[99]
++ la_data_out[9] la_oenb[0] la_oenb[100] la_oenb[101] la_oenb[102] la_oenb[103] la_oenb[104]
++ la_oenb[105] la_oenb[106] la_oenb[107] la_oenb[108] la_oenb[109] la_oenb[10] la_oenb[110]
++ la_oenb[111] la_oenb[112] la_oenb[113] la_oenb[114] la_oenb[115] la_oenb[116] la_oenb[117]
++ la_oenb[118] la_oenb[119] la_oenb[11] la_oenb[120] la_oenb[121] la_oenb[122] la_oenb[123]
++ la_oenb[124] la_oenb[125] la_oenb[126] la_oenb[127] la_oenb[12] la_oenb[13] la_oenb[14]
++ la_oenb[15] la_oenb[16] la_oenb[17] la_oenb[18] la_oenb[19] la_oenb[1] la_oenb[20]
++ la_oenb[21] la_oenb[22] la_oenb[23] la_oenb[24] la_oenb[25] la_oenb[26] la_oenb[27]
++ la_oenb[28] la_oenb[29] la_oenb[2] la_oenb[30] la_oenb[31] la_oenb[32] la_oenb[33]
++ la_oenb[34] la_oenb[35] la_oenb[36] la_oenb[37] la_oenb[38] la_oenb[39] la_oenb[3]
++ la_oenb[40] la_oenb[41] la_oenb[42] la_oenb[43] la_oenb[44] la_oenb[45] la_oenb[46]
++ la_oenb[47] la_oenb[48] la_oenb[49] la_oenb[4] la_oenb[50] la_oenb[51] la_oenb[52]
++ la_oenb[53] la_oenb[54] la_oenb[55] la_oenb[56] la_oenb[57] la_oenb[58] la_oenb[59]
++ la_oenb[5] la_oenb[60] la_oenb[61] la_oenb[62] la_oenb[63] la_oenb[64] la_oenb[65]
++ la_oenb[66] la_oenb[67] la_oenb[68] la_oenb[69] la_oenb[6] la_oenb[70] la_oenb[71]
++ la_oenb[72] la_oenb[73] la_oenb[74] la_oenb[75] la_oenb[76] la_oenb[77] la_oenb[78]
++ la_oenb[79] la_oenb[7] la_oenb[80] la_oenb[81] la_oenb[82] la_oenb[83] la_oenb[84]
++ la_oenb[85] la_oenb[86] la_oenb[87] la_oenb[88] la_oenb[89] la_oenb[8] la_oenb[90]
++ la_oenb[91] la_oenb[92] la_oenb[93] la_oenb[94] la_oenb[95] la_oenb[96] la_oenb[97]
++ la_oenb[98] la_oenb[99] la_oenb[9] user_clock2 user_irq[0] user_irq[1] user_irq[2]
++ vccd1 vccd2 vdda1 vdda2 vssa1 vssa2 vssd1 vssd2 wb_clk_i wb_rst_i wbs_ack_o wbs_adr_i[0]
++ wbs_adr_i[10] wbs_adr_i[11] wbs_adr_i[12] wbs_adr_i[13] wbs_adr_i[14] wbs_adr_i[15]
++ wbs_adr_i[16] wbs_adr_i[17] wbs_adr_i[18] wbs_adr_i[19] wbs_adr_i[1] wbs_adr_i[20]
++ wbs_adr_i[21] wbs_adr_i[22] wbs_adr_i[23] wbs_adr_i[24] wbs_adr_i[25] wbs_adr_i[26]
++ wbs_adr_i[27] wbs_adr_i[28] wbs_adr_i[29] wbs_adr_i[2] wbs_adr_i[30] wbs_adr_i[31]
++ wbs_adr_i[3] wbs_adr_i[4] wbs_adr_i[5] wbs_adr_i[6] wbs_adr_i[7] wbs_adr_i[8] wbs_adr_i[9]
++ wbs_cyc_i wbs_dat_i[0] wbs_dat_i[10] wbs_dat_i[11] wbs_dat_i[12] wbs_dat_i[13] wbs_dat_i[14]
++ wbs_dat_i[15] wbs_dat_i[16] wbs_dat_i[17] wbs_dat_i[18] wbs_dat_i[19] wbs_dat_i[1]
++ wbs_dat_i[20] wbs_dat_i[21] wbs_dat_i[22] wbs_dat_i[23] wbs_dat_i[24] wbs_dat_i[25]
++ wbs_dat_i[26] wbs_dat_i[27] wbs_dat_i[28] wbs_dat_i[29] wbs_dat_i[2] wbs_dat_i[30]
++ wbs_dat_i[31] wbs_dat_i[3] wbs_dat_i[4] wbs_dat_i[5] wbs_dat_i[6] wbs_dat_i[7] wbs_dat_i[8]
++ wbs_dat_i[9] wbs_dat_o[0] wbs_dat_o[10] wbs_dat_o[11] wbs_dat_o[12] wbs_dat_o[13]
++ wbs_dat_o[14] wbs_dat_o[15] wbs_dat_o[16] wbs_dat_o[17] wbs_dat_o[18] wbs_dat_o[19]
++ wbs_dat_o[1] wbs_dat_o[20] wbs_dat_o[21] wbs_dat_o[22] wbs_dat_o[23] wbs_dat_o[24]
++ wbs_dat_o[25] wbs_dat_o[26] wbs_dat_o[27] wbs_dat_o[28] wbs_dat_o[29] wbs_dat_o[2]
++ wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6]
++ wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3]
++ wbs_stb_i wbs_we_i
+Xbuffer_1_0 vccd1 L1 comparator_SA_0/Outn vssa1 buffer_1#0
+Xbuffer_1_1 vccd1 L2 comparator_SA_0/Outp vssa1 buffer_1#0
+Xbuffer_12_0 comparator_SA_0/CLK io_analog[8] vccd1 vssa1 buffer_12
+Xbuffer_12_1 io_analog[1] inv_W1_0/Vout vccd1 vssa1 buffer_12
+Xcomparator_SA_0 comparator_SA_0/Outn io_analog[5] io_analog[6] comparator_SA_0/CLK
++ vccd1 vssa1 comparator_SA_0/Outp comparator_SA
+Xinv_W1_0 inv_W1_0/Vout io_analog[8] vccd1 vssa1 inv_W1
+Xbuffer_2_0 io_analog[3] vccd1 vccd1 L1 vssa1 vssa1 buffer_2#0
+Xbuffer_2_1 io_analog[2] vccd1 vccd1 L2 vssa1 vssa1 buffer_2#1
+V0 vssa1 io_clamp_low[1] 0.0
+V1 vssa1 io_clamp_low[2] 0.0
+V2 vccd1 io_clamp_high[2] 0.0
+V3 vccd1 io_clamp_high[1] 0.0
+
+.ends
+
diff --git a/openlane/.gitignore b/openlane/.gitignore
new file mode 100644
index 0000000..e4867d8
--- /dev/null
+++ b/openlane/.gitignore
@@ -0,0 +1,2 @@
+*/runs
+default.cvcrc
diff --git a/openlane/Makefile b/openlane/Makefile
new file mode 120000
index 0000000..48e5b4a
--- /dev/null
+++ b/openlane/Makefile
@@ -0,0 +1 @@
+../caravel/openlane/Makefile
\ No newline at end of file
diff --git a/precheck_results/31_MAY_2022___07_11_48/logs/gds.info b/precheck_results/31_MAY_2022___07_11_48/logs/gds.info
new file mode 100644
index 0000000..66a0e97
--- /dev/null
+++ b/precheck_results/31_MAY_2022___07_11_48/logs/gds.info
@@ -0,0 +1 @@
+user_analog_project_wrapper.gds: abb23bc6d6891972936e14fe7b9382be38c46d6f
\ No newline at end of file
diff --git a/precheck_results/31_MAY_2022___07_11_48/logs/pdks.info b/precheck_results/31_MAY_2022___07_11_48/logs/pdks.info
new file mode 100644
index 0000000..3072015
--- /dev/null
+++ b/precheck_results/31_MAY_2022___07_11_48/logs/pdks.info
@@ -0,0 +1,2 @@
+Open PDKs a3d6ffea8022332b859daa454cef7ee7131c5181
+Skywater PDK f70d8ca46961ff92719d8870a18a076370b85f6c
\ No newline at end of file
diff --git a/precheck_results/31_MAY_2022___07_11_48/logs/precheck.log b/precheck_results/31_MAY_2022___07_11_48/logs/precheck.log
new file mode 100644
index 0000000..c648bcd
--- /dev/null
+++ b/precheck_results/31_MAY_2022___07_11_48/logs/precheck.log
@@ -0,0 +1,24 @@
+2022-05-31 07:11:48 - [INFO] - {{EXTRACTING FILES}} Extracting compressed files in: /home/krishna/Strong_Arm_MPW6
+2022-05-31 07:11:48 - [INFO] - {{Project Type Info}} analog
+2022-05-31 07:11:48 - [INFO] - {{Project GDS Info}} user_analog_project_wrapper: abb23bc6d6891972936e14fe7b9382be38c46d6f
+2022-05-31 07:11:50 - [INFO] - {{Tools Info}} KLayout: v0.27.8 | Magic: v8.3.274
+2022-05-31 07:11:50 - [INFO] - {{PDKs Info}} Open PDKs: a3d6ffea8022332b859daa454cef7ee7131c5181 | Skywater PDK: f70d8ca46961ff92719d8870a18a076370b85f6c
+2022-05-31 07:11:50 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in '/home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___07_11_48/logs'
+2022-05-31 07:11:50 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: [License, Makefile, Default, Documentation, Consistency, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea]
+2022-05-31 07:11:50 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 13: License
+2022-05-31 07:11:52 - [INFO] - An approved LICENSE (Apache-2.0) was found in /home/krishna/Strong_Arm_MPW6.
+2022-05-31 07:11:52 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
+2022-05-31 07:11:53 - [INFO] - An approved LICENSE (Apache-2.0) was found in /home/krishna/Strong_Arm_MPW6.
+2022-05-31 07:11:53 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
+2022-05-31 07:11:53 - [ERROR] - SPDX COMPLIANCE SYMLINK FILE NOT FOUND in /home/krishna/Strong_Arm_MPW6/openlane/Makefile
+2022-05-31 07:11:53 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 84 non-compliant file(s) with the SPDX Standard.
+2022-05-31 07:11:53 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['/home/krishna/Strong_Arm_MPW6/Makefile', '/home/krishna/Strong_Arm_MPW6/verilog/dv/Makefile', '/home/krishna/Strong_Arm_MPW6/verilog/dv/mprj_por/mprj_por.c', '/home/krishna/Strong_Arm_MPW6/verilog/dv/mprj_por/mprj_por_tb.v', '/home/krishna/Strong_Arm_MPW6/verilog/dv/mprj_por/Makefile', '/home/krishna/Strong_Arm_MPW6/verilog/rtl/uprj_analog_netlists.v', '/home/krishna/Strong_Arm_MPW6/verilog/rtl/example_por.v', '/home/krishna/Strong_Arm_MPW6/verilog/rtl/user_analog_proj_example.v', '/home/krishna/Strong_Arm_MPW6/verilog/rtl/user_analog_project_wrapper.v', '/home/krishna/Strong_Arm_MPW6/verilog/rtl/comparator.v', '/home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___07_11_48/logs/tools.info', '/home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___07_11_48/logs/gds.info', '/home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___07_11_48/logs/pdks.info', '/home/krishna/Strong_Arm_MPW6/mag/sky130_fd_pr__pfet_01v8_AC5Z8B#0.ext', '/home/krishna/Strong_Arm_MPW6/mag/compaartor_v4.ext']
+2022-05-31 07:11:53 - [INFO] - For the full SPDX compliance report check: /home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___07_11_48/logs/spdx_compliance_report.log
+2022-05-31 07:11:53 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 13: Makefile
+2022-05-31 07:11:53 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
+2022-05-31 07:11:53 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 13: Default
+2022-05-31 07:11:53 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
+2022-05-31 07:11:53 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
+2022-05-31 07:11:53 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 13: Documentation
+2022-05-31 07:11:53 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
+2022-05-31 07:11:53 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 13: Consistency
diff --git a/precheck_results/31_MAY_2022___07_11_48/logs/spdx_compliance_report.log b/precheck_results/31_MAY_2022___07_11_48/logs/spdx_compliance_report.log
new file mode 100644
index 0000000..dc71e5a
--- /dev/null
+++ b/precheck_results/31_MAY_2022___07_11_48/logs/spdx_compliance_report.log
@@ -0,0 +1,84 @@
+/home/krishna/Strong_Arm_MPW6/Makefile
+/home/krishna/Strong_Arm_MPW6/verilog/dv/Makefile
+/home/krishna/Strong_Arm_MPW6/verilog/dv/mprj_por/mprj_por.c
+/home/krishna/Strong_Arm_MPW6/verilog/dv/mprj_por/mprj_por_tb.v
+/home/krishna/Strong_Arm_MPW6/verilog/dv/mprj_por/Makefile
+/home/krishna/Strong_Arm_MPW6/verilog/rtl/uprj_analog_netlists.v
+/home/krishna/Strong_Arm_MPW6/verilog/rtl/example_por.v
+/home/krishna/Strong_Arm_MPW6/verilog/rtl/user_analog_proj_example.v
+/home/krishna/Strong_Arm_MPW6/verilog/rtl/user_analog_project_wrapper.v
+/home/krishna/Strong_Arm_MPW6/verilog/rtl/comparator.v
+/home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___07_11_48/logs/tools.info
+/home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___07_11_48/logs/gds.info
+/home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___07_11_48/logs/pdks.info
+/home/krishna/Strong_Arm_MPW6/mag/sky130_fd_pr__pfet_01v8_AC5Z8B#0.ext
+/home/krishna/Strong_Arm_MPW6/mag/compaartor_v4.ext
+/home/krishna/Strong_Arm_MPW6/mag/inv_W2.ext
+/home/krishna/Strong_Arm_MPW6/mag/sky130_fd_pr__diode_pw2nd_05v5_KLAK3C.ext
+/home/krishna/Strong_Arm_MPW6/mag/sky130_fd_pr__diode_pw2nd_05v5_FT7GK8.ext
+/home/krishna/Strong_Arm_MPW6/mag/comparator_SA.ext
+/home/krishna/Strong_Arm_MPW6/mag/inv_W2#0.ext
+/home/krishna/Strong_Arm_MPW6/mag/.magicrc
+/home/krishna/Strong_Arm_MPW6/mag/inv_W1#0.ext
+/home/krishna/Strong_Arm_MPW6/mag/sky130_fd_pr__nfet_01v8_XJTKXQ#1.ext
+/home/krishna/Strong_Arm_MPW6/mag/sky130_fd_pr__nfet_01v8_XJTKXQ.ext
+/home/krishna/Strong_Arm_MPW6/mag/sky130_fd_pr__pfet_01v8_AC5Z8B.ext
+/home/krishna/Strong_Arm_MPW6/mag/buffer_2#1.ext
+/home/krishna/Strong_Arm_MPW6/mag/buffer_1#0.ext
+/home/krishna/Strong_Arm_MPW6/mag/sky130_fd_pr__pfet_01v8_5233FE.ext
+/home/krishna/Strong_Arm_MPW6/mag/user_analog_project_wrapper.ext
+/home/krishna/Strong_Arm_MPW6/mag/buffer_2#0.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/inv_W2.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_VJWT33.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_7RYEVP.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_RL4NCG.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_5C3Z5B.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_KZU588.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/inv.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/buffer_1.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/nmos_1u.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_5YYKDE.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/inv_W22.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/pmos_2uf2.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/sky130A.magicrc
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_KBWVY9.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_3M44SC.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/.magicrc
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/buffer_2.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/inv_W8.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/buffer_sample_lay.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_XJTKXQ.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_QQ4XG9.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_AC5Z8B.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/inv_W1.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/.spiceinit
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/buffer_12.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/inv_W16.ext
+/home/krishna/Strong_Arm_MPW6/mag/latch/SR_latch.ext
+/home/krishna/Strong_Arm_MPW6/mag/latch/latch_2SA.ext
+/home/krishna/Strong_Arm_MPW6/mag/latch/sky130_fd_pr__pfet_01v8_AC5E9B.ext
+/home/krishna/Strong_Arm_MPW6/mag/latch/.magicrc
+/home/krishna/Strong_Arm_MPW6/mag/latch/sky130_fd_pr__nfet_01v8_F5U58G.ext
+/home/krishna/Strong_Arm_MPW6/mag/latch/latch_2.ext
+/home/krishna/Strong_Arm_MPW6/mag/latch/sky130_fd_pr__pfet_01v8_5SVZDE.ext
+/home/krishna/Strong_Arm_MPW6/mag/preamp/sky130_fd_pr__nfet_01v8_G6PLX8.ext
+/home/krishna/Strong_Arm_MPW6/mag/preamp/preamp_part1SA.ext
+/home/krishna/Strong_Arm_MPW6/mag/preamp/.magicrc
+/home/krishna/Strong_Arm_MPW6/mag/preamp/sky130_fd_pr__pfet_01v8_5Y8GKB.ext
+/home/krishna/Strong_Arm_MPW6/mag/preamp/sky130_fd_pr__nfet_01v8_NHLLAS.ext
+/home/krishna/Strong_Arm_MPW6/xschem/xschemrc
+/home/krishna/Strong_Arm_MPW6/xschem/comparator_lvs.sch
+/home/krishna/Strong_Arm_MPW6/xschem/user_analog_project_wrapper.sym
+/home/krishna/Strong_Arm_MPW6/xschem/comparator.sch
+/home/krishna/Strong_Arm_MPW6/xschem/comparator.sym
+/home/krishna/Strong_Arm_MPW6/xschem/analog_wrapper_tb.sch
+/home/krishna/Strong_Arm_MPW6/xschem/user_analog_project_wrapper.sch
+/home/krishna/Strong_Arm_MPW6/xschem/.spiceinit
+/home/krishna/Strong_Arm_MPW6/xschem/comparator_tb.sch
+/home/krishna/Strong_Arm_MPW6/docs/Makefile
+/home/krishna/Strong_Arm_MPW6/docs/environment.yml
+/home/krishna/Strong_Arm_MPW6/docs/source/conf.py
+/home/krishna/Strong_Arm_MPW6/docs/source/index.rst
+/home/krishna/Strong_Arm_MPW6/netgen/run_lvs_wrapper_verilog.sh
+/home/krishna/Strong_Arm_MPW6/netgen/run_lvs_por.sh
+/home/krishna/Strong_Arm_MPW6/netgen/run_lvs_wrapper_xschem.sh
diff --git a/precheck_results/31_MAY_2022___07_11_48/logs/tools.info b/precheck_results/31_MAY_2022___07_11_48/logs/tools.info
new file mode 100644
index 0000000..9b2230a
--- /dev/null
+++ b/precheck_results/31_MAY_2022___07_11_48/logs/tools.info
@@ -0,0 +1,2 @@
+KLayout: 0.27.8
+Magic: 8.3.274
\ No newline at end of file
diff --git a/precheck_results/31_MAY_2022___08_35_25/logs/gds.info b/precheck_results/31_MAY_2022___08_35_25/logs/gds.info
new file mode 100644
index 0000000..66a0e97
--- /dev/null
+++ b/precheck_results/31_MAY_2022___08_35_25/logs/gds.info
@@ -0,0 +1 @@
+user_analog_project_wrapper.gds: abb23bc6d6891972936e14fe7b9382be38c46d6f
\ No newline at end of file
diff --git a/precheck_results/31_MAY_2022___08_35_25/logs/pdks.info b/precheck_results/31_MAY_2022___08_35_25/logs/pdks.info
new file mode 100644
index 0000000..3072015
--- /dev/null
+++ b/precheck_results/31_MAY_2022___08_35_25/logs/pdks.info
@@ -0,0 +1,2 @@
+Open PDKs a3d6ffea8022332b859daa454cef7ee7131c5181
+Skywater PDK f70d8ca46961ff92719d8870a18a076370b85f6c
\ No newline at end of file
diff --git a/precheck_results/31_MAY_2022___08_35_25/logs/precheck.log b/precheck_results/31_MAY_2022___08_35_25/logs/precheck.log
new file mode 100644
index 0000000..c0a38c5
--- /dev/null
+++ b/precheck_results/31_MAY_2022___08_35_25/logs/precheck.log
@@ -0,0 +1,24 @@
+2022-05-31 08:35:25 - [INFO] - {{EXTRACTING FILES}} Extracting compressed files in: /home/krishna/Strong_Arm_MPW6
+2022-05-31 08:35:25 - [INFO] - {{Project Type Info}} analog
+2022-05-31 08:35:25 - [INFO] - {{Project GDS Info}} user_analog_project_wrapper: abb23bc6d6891972936e14fe7b9382be38c46d6f
+2022-05-31 08:35:25 - [INFO] - {{Tools Info}} KLayout: v0.27.8 | Magic: v8.3.274
+2022-05-31 08:35:25 - [INFO] - {{PDKs Info}} Open PDKs: a3d6ffea8022332b859daa454cef7ee7131c5181 | Skywater PDK: f70d8ca46961ff92719d8870a18a076370b85f6c
+2022-05-31 08:35:25 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in '/home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___08_35_25/logs'
+2022-05-31 08:35:25 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: [License, Makefile, Default, Documentation, Consistency, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea]
+2022-05-31 08:35:25 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 13: License
+2022-05-31 08:35:26 - [INFO] - An approved LICENSE (Apache-2.0) was found in /home/krishna/Strong_Arm_MPW6.
+2022-05-31 08:35:26 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
+2022-05-31 08:35:27 - [INFO] - An approved LICENSE (Apache-2.0) was found in /home/krishna/Strong_Arm_MPW6.
+2022-05-31 08:35:27 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
+2022-05-31 08:35:27 - [ERROR] - SPDX COMPLIANCE SYMLINK FILE NOT FOUND in /home/krishna/Strong_Arm_MPW6/openlane/Makefile
+2022-05-31 08:35:27 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 87 non-compliant file(s) with the SPDX Standard.
+2022-05-31 08:35:27 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['/home/krishna/Strong_Arm_MPW6/Makefile', '/home/krishna/Strong_Arm_MPW6/verilog/dv/Makefile', '/home/krishna/Strong_Arm_MPW6/verilog/dv/mprj_por/mprj_por.c', '/home/krishna/Strong_Arm_MPW6/verilog/dv/mprj_por/mprj_por_tb.v', '/home/krishna/Strong_Arm_MPW6/verilog/dv/mprj_por/Makefile', '/home/krishna/Strong_Arm_MPW6/verilog/rtl/uprj_analog_netlists.v', '/home/krishna/Strong_Arm_MPW6/verilog/rtl/example_por.v', '/home/krishna/Strong_Arm_MPW6/verilog/rtl/user_analog_proj_example.v', '/home/krishna/Strong_Arm_MPW6/verilog/rtl/user_analog_project_wrapper.v', '/home/krishna/Strong_Arm_MPW6/verilog/rtl/comparator.v', '/home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___08_35_25/logs/tools.info', '/home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___08_35_25/logs/gds.info', '/home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___08_35_25/logs/pdks.info', '/home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___07_11_48/logs/tools.info', '/home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___07_11_48/logs/gds.info']
+2022-05-31 08:35:27 - [INFO] - For the full SPDX compliance report check: /home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___08_35_25/logs/spdx_compliance_report.log
+2022-05-31 08:35:27 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 13: Makefile
+2022-05-31 08:35:27 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
+2022-05-31 08:35:27 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 13: Default
+2022-05-31 08:35:27 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
+2022-05-31 08:35:27 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
+2022-05-31 08:35:27 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 13: Documentation
+2022-05-31 08:35:27 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
+2022-05-31 08:35:27 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 13: Consistency
diff --git a/precheck_results/31_MAY_2022___08_35_25/logs/spdx_compliance_report.log b/precheck_results/31_MAY_2022___08_35_25/logs/spdx_compliance_report.log
new file mode 100644
index 0000000..d47ef5e
--- /dev/null
+++ b/precheck_results/31_MAY_2022___08_35_25/logs/spdx_compliance_report.log
@@ -0,0 +1,87 @@
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+/home/krishna/Strong_Arm_MPW6/verilog/rtl/example_por.v
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diff --git a/precheck_results/31_MAY_2022___08_35_25/logs/tools.info b/precheck_results/31_MAY_2022___08_35_25/logs/tools.info
new file mode 100644
index 0000000..9b2230a
--- /dev/null
+++ b/precheck_results/31_MAY_2022___08_35_25/logs/tools.info
@@ -0,0 +1,2 @@
+KLayout: 0.27.8
+Magic: 8.3.274
\ No newline at end of file
diff --git a/precheck_results/31_MAY_2022___08_42_48/logs/gds.info b/precheck_results/31_MAY_2022___08_42_48/logs/gds.info
new file mode 100644
index 0000000..66a0e97
--- /dev/null
+++ b/precheck_results/31_MAY_2022___08_42_48/logs/gds.info
@@ -0,0 +1 @@
+user_analog_project_wrapper.gds: abb23bc6d6891972936e14fe7b9382be38c46d6f
\ No newline at end of file
diff --git a/precheck_results/31_MAY_2022___08_42_48/logs/pdks.info b/precheck_results/31_MAY_2022___08_42_48/logs/pdks.info
new file mode 100644
index 0000000..3072015
--- /dev/null
+++ b/precheck_results/31_MAY_2022___08_42_48/logs/pdks.info
@@ -0,0 +1,2 @@
+Open PDKs a3d6ffea8022332b859daa454cef7ee7131c5181
+Skywater PDK f70d8ca46961ff92719d8870a18a076370b85f6c
\ No newline at end of file
diff --git a/precheck_results/31_MAY_2022___08_42_48/logs/precheck.log b/precheck_results/31_MAY_2022___08_42_48/logs/precheck.log
new file mode 100644
index 0000000..0ef2605
--- /dev/null
+++ b/precheck_results/31_MAY_2022___08_42_48/logs/precheck.log
@@ -0,0 +1,24 @@
+2022-05-31 08:42:48 - [INFO] - {{EXTRACTING FILES}} Extracting compressed files in: /home/krishna/Strong_Arm_MPW6
+2022-05-31 08:42:48 - [INFO] - {{Project Type Info}} analog
+2022-05-31 08:42:48 - [INFO] - {{Project GDS Info}} user_analog_project_wrapper: abb23bc6d6891972936e14fe7b9382be38c46d6f
+2022-05-31 08:42:48 - [INFO] - {{Tools Info}} KLayout: v0.27.8 | Magic: v8.3.274
+2022-05-31 08:42:48 - [INFO] - {{PDKs Info}} Open PDKs: a3d6ffea8022332b859daa454cef7ee7131c5181 | Skywater PDK: f70d8ca46961ff92719d8870a18a076370b85f6c
+2022-05-31 08:42:48 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in '/home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___08_42_48/logs'
+2022-05-31 08:42:48 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: [License, Makefile, Default, Documentation, Consistency, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea]
+2022-05-31 08:42:48 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 13: License
+2022-05-31 08:42:49 - [INFO] - An approved LICENSE (Apache-2.0) was found in /home/krishna/Strong_Arm_MPW6.
+2022-05-31 08:42:49 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
+2022-05-31 08:42:50 - [INFO] - An approved LICENSE (Apache-2.0) was found in /home/krishna/Strong_Arm_MPW6.
+2022-05-31 08:42:50 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
+2022-05-31 08:42:50 - [ERROR] - SPDX COMPLIANCE SYMLINK FILE NOT FOUND in /home/krishna/Strong_Arm_MPW6/openlane/Makefile
+2022-05-31 08:42:50 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 90 non-compliant file(s) with the SPDX Standard.
+2022-05-31 08:42:50 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['/home/krishna/Strong_Arm_MPW6/Makefile', '/home/krishna/Strong_Arm_MPW6/verilog/dv/Makefile', '/home/krishna/Strong_Arm_MPW6/verilog/dv/mprj_por/mprj_por.c', '/home/krishna/Strong_Arm_MPW6/verilog/dv/mprj_por/mprj_por_tb.v', '/home/krishna/Strong_Arm_MPW6/verilog/dv/mprj_por/Makefile', '/home/krishna/Strong_Arm_MPW6/verilog/rtl/uprj_analog_netlists.v', '/home/krishna/Strong_Arm_MPW6/verilog/rtl/example_por.v', '/home/krishna/Strong_Arm_MPW6/verilog/rtl/user_analog_proj_example.v', '/home/krishna/Strong_Arm_MPW6/verilog/rtl/user_analog_project_wrapper.v', '/home/krishna/Strong_Arm_MPW6/verilog/rtl/comparator.v', '/home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___08_35_25/logs/tools.info', '/home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___08_35_25/logs/gds.info', '/home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___08_35_25/logs/pdks.info', '/home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___07_11_48/logs/tools.info', '/home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___07_11_48/logs/gds.info']
+2022-05-31 08:42:50 - [INFO] - For the full SPDX compliance report check: /home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___08_42_48/logs/spdx_compliance_report.log
+2022-05-31 08:42:50 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 13: Makefile
+2022-05-31 08:42:50 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
+2022-05-31 08:42:50 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 13: Default
+2022-05-31 08:42:50 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
+2022-05-31 08:42:50 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
+2022-05-31 08:42:50 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 13: Documentation
+2022-05-31 08:42:50 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
+2022-05-31 08:42:50 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 13: Consistency
diff --git a/precheck_results/31_MAY_2022___08_42_48/logs/spdx_compliance_report.log b/precheck_results/31_MAY_2022___08_42_48/logs/spdx_compliance_report.log
new file mode 100644
index 0000000..2acb5a4
--- /dev/null
+++ b/precheck_results/31_MAY_2022___08_42_48/logs/spdx_compliance_report.log
@@ -0,0 +1,90 @@
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diff --git a/precheck_results/31_MAY_2022___08_42_48/logs/tools.info b/precheck_results/31_MAY_2022___08_42_48/logs/tools.info
new file mode 100644
index 0000000..9b2230a
--- /dev/null
+++ b/precheck_results/31_MAY_2022___08_42_48/logs/tools.info
@@ -0,0 +1,2 @@
+KLayout: 0.27.8
+Magic: 8.3.274
\ No newline at end of file
diff --git a/precheck_results/31_MAY_2022___14_11_20/logs/gds.info b/precheck_results/31_MAY_2022___14_11_20/logs/gds.info
new file mode 100644
index 0000000..66a0e97
--- /dev/null
+++ b/precheck_results/31_MAY_2022___14_11_20/logs/gds.info
@@ -0,0 +1 @@
+user_analog_project_wrapper.gds: abb23bc6d6891972936e14fe7b9382be38c46d6f
\ No newline at end of file
diff --git a/precheck_results/31_MAY_2022___14_11_20/logs/klayout_beol_check.log b/precheck_results/31_MAY_2022___14_11_20/logs/klayout_beol_check.log
new file mode 100644
index 0000000..89bfed1
--- /dev/null
+++ b/precheck_results/31_MAY_2022___14_11_20/logs/klayout_beol_check.log
@@ -0,0 +1,992 @@
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:38: warning: already initialized constant DRC::DRCEngine::FEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:28: warning: previous definition of FEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:42: warning: already initialized constant DRC::DRCEngine::BEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:29: warning: previous definition of BEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:50: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:30: warning: previous definition of OFFGRID was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::SEAL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:31: warning: previous definition of SEAL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:32: warning: previous definition of FLOATING_MET was here
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+Writing report database: /home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___14_11_20/outputs/reports/klayout_beol_check.xml ..
+Total elapsed: 3.970s Memory: 1106.00M
diff --git a/precheck_results/31_MAY_2022___14_11_20/logs/klayout_beol_check.total b/precheck_results/31_MAY_2022___14_11_20/logs/klayout_beol_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/31_MAY_2022___14_11_20/logs/klayout_beol_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/31_MAY_2022___14_11_20/logs/klayout_feol_check.log b/precheck_results/31_MAY_2022___14_11_20/logs/klayout_feol_check.log
new file mode 100644
index 0000000..eb46960
--- /dev/null
+++ b/precheck_results/31_MAY_2022___14_11_20/logs/klayout_feol_check.log
@@ -0,0 +1,789 @@
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:36: warning: already initialized constant DRC::DRCEngine::FEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:28: warning: previous definition of FEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:44: warning: already initialized constant DRC::DRCEngine::BEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:29: warning: previous definition of BEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:50: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:30: warning: previous definition of OFFGRID was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::SEAL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:31: warning: previous definition of SEAL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:32: warning: previous definition of FLOATING_MET was here
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+"and" in: sky130A_mr.drc:369
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+"output" in: sky130A_mr.drc:369
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+"enclosing" in: sky130A_mr.drc:370
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+"output" in: sky130A_mr.drc:370
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+"enclosing" in: sky130A_mr.drc:371
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+"output" in: sky130A_mr.drc:371
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+"separation" in: sky130A_mr.drc:372
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+"output" in: sky130A_mr.drc:372
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 1067.00M
+END: 97/44 (cap2m)
+FEOL section
+START: 75/20 (hvi)
+"not" in: sky130A_mr.drc:672
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+ Elapsed: 0.000s Memory: 1067.00M
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+"output" in: sky130A_mr.drc:674
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+END: 75/20 (hvi)
+START: 125/20 (hvntm)
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+"output" in: sky130A_mr.drc:681
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+ Elapsed: 0.000s Memory: 1067.00M
+END: 125/20 (hvntm)
+Writing report database: /home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___14_11_20/outputs/reports/klayout_feol_check.xml ..
+Total elapsed: 1.480s Memory: 1067.00M
diff --git a/precheck_results/31_MAY_2022___14_11_20/logs/klayout_feol_check.total b/precheck_results/31_MAY_2022___14_11_20/logs/klayout_feol_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/31_MAY_2022___14_11_20/logs/klayout_feol_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/31_MAY_2022___14_11_20/logs/klayout_met_min_ca_density_check.log b/precheck_results/31_MAY_2022___14_11_20/logs/klayout_met_min_ca_density_check.log
new file mode 100644
index 0000000..6ec1113
--- /dev/null
+++ b/precheck_results/31_MAY_2022___14_11_20/logs/klayout_met_min_ca_density_check.log
@@ -0,0 +1,79 @@
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+ Elapsed: 0.010s Memory: 522.00M
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+"area" in: met_min_ca_density.lydrc:59
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+"area" in: met_min_ca_density.lydrc:69
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+"area" in: met_min_ca_density.lydrc:109
+ Elapsed: 0.010s Memory: 523.00M
+m5_ca_density is 0.9761541531755915
+Writing report database: /home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___14_11_20/outputs/reports/klayout_met_min_ca_density_check.xml ..
+Total elapsed: 0.170s Memory: 522.00M
diff --git a/precheck_results/31_MAY_2022___14_11_20/logs/klayout_met_min_ca_density_check.total b/precheck_results/31_MAY_2022___14_11_20/logs/klayout_met_min_ca_density_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/31_MAY_2022___14_11_20/logs/klayout_met_min_ca_density_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/31_MAY_2022___14_11_20/logs/klayout_offgrid_check.log b/precheck_results/31_MAY_2022___14_11_20/logs/klayout_offgrid_check.log
new file mode 100644
index 0000000..6e167ed
--- /dev/null
+++ b/precheck_results/31_MAY_2022___14_11_20/logs/klayout_offgrid_check.log
@@ -0,0 +1,755 @@
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:38: warning: already initialized constant DRC::DRCEngine::FEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:28: warning: previous definition of FEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:44: warning: already initialized constant DRC::DRCEngine::BEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:29: warning: previous definition of BEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:48: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:30: warning: previous definition of OFFGRID was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::SEAL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:31: warning: previous definition of SEAL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:32: warning: previous definition of FLOATING_MET was here
+"input" in: sky130A_mr.drc:112
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+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:760
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"with_angle" in: sky130A_mr.drc:761
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:761
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"ongrid" in: sky130A_mr.drc:762
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:762
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"with_angle" in: sky130A_mr.drc:763
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"output" in: sky130A_mr.drc:763
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"ongrid" in: sky130A_mr.drc:764
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:764
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"with_angle" in: sky130A_mr.drc:765
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:765
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"ongrid" in: sky130A_mr.drc:766
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:766
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+Writing report database: /home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___14_11_20/outputs/reports/klayout_offgrid_check.xml ..
+Total elapsed: 1.550s Memory: 530.00M
diff --git a/precheck_results/31_MAY_2022___14_11_20/logs/klayout_offgrid_check.total b/precheck_results/31_MAY_2022___14_11_20/logs/klayout_offgrid_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/31_MAY_2022___14_11_20/logs/klayout_offgrid_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/31_MAY_2022___14_11_20/logs/klayout_pin_label_purposes_overlapping_drawing_check.log b/precheck_results/31_MAY_2022___14_11_20/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
new file mode 100644
index 0000000..dd22467
--- /dev/null
+++ b/precheck_results/31_MAY_2022___14_11_20/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
@@ -0,0 +1,29 @@
+Running pin_label_purposes_overlapping_drawing.rb.drc on file=/home/krishna/Strong_Arm_MPW6/gds/user_analog_project_wrapper.gds, topcell=user_analog_project_wrapper, output to /home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___14_11_20/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
+ deep:true tiled:false threads:12
+--- #err|description, table for cell: user_analog_project_wrapper
+NO-Check ---- pwell:64/44/EMP 122/16/EMP 64/59/EMP 44/16/EMP 44/5/EMP
+ ---- nwell:64/20/dat 64/16/EMP 64/5/EMP
+ ---- diff:65/20/dat 65/16/EMP 65/6/EMP
+ ---- tap:65/44/dat 65/48/EMP 65/5/EMP
+ ---- poly:66/20/dat 66/16/EMP 66/5/EMP
+ ---- licon1:66/44/dat 66/58/EMP
+ ---- li1:67/20/dat 67/16/EMP 67/5/EMP
+ ---- mcon:67/44/dat 67/48/EMP
+ ---- met1:68/20/dat 68/16/EMP 68/5/EMP
+ ---- via:68/44/dat 68/58/EMP
+ ---- met2:69/20/dat 69/16/dat 69/5/EMP
+ ---- via2:69/44/dat 69/58/EMP
+ ---- met3:70/20/dat 70/16/dat 70/5/EMP
+ ---- via3:70/44/dat 70/48/EMP
+ ---- met4:71/20/dat 71/16/dat 71/5/EMP
+ ---- via4:71/44/dat 71/48/EMP
+ ---- met5:72/20/dat 72/16/dat 72/5/EMP
+ ---- pad:76/20/EMP 76/5/EMP 76/16/EMP
+ ---- pnp:82/44/EMP 82/59/EMP
+ ---- npn:82/20/EMP 82/5/EMP
+ ---- rdl:74/20/EMP 74/16/EMP 74/5/EMP
+ ---- inductor:82/24/EMP 82/25/EMP
+ 0 total error(s) among 0 error type(s), 33 checks, cell: user_analog_project_wrapper
+Writing report...
+VmPeak: 2369876 kB
+VmHWM: 258164 kB
diff --git a/precheck_results/31_MAY_2022___14_11_20/logs/klayout_pin_label_purposes_overlapping_drawing_check.total b/precheck_results/31_MAY_2022___14_11_20/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/31_MAY_2022___14_11_20/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/31_MAY_2022___14_11_20/logs/klayout_zeroarea_check.log b/precheck_results/31_MAY_2022___14_11_20/logs/klayout_zeroarea_check.log
new file mode 100644
index 0000000..f33b577
--- /dev/null
+++ b/precheck_results/31_MAY_2022___14_11_20/logs/klayout_zeroarea_check.log
@@ -0,0 +1,4 @@
+0 zero-area shapes
+writing to /home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___14_11_20/outputs/user_analog_project_wrapper_no_zero_areas.gds
+VmPeak: 542064 kB
+VmHWM: 260744 kB
diff --git a/precheck_results/31_MAY_2022___14_11_20/logs/klayout_zeroarea_check.total b/precheck_results/31_MAY_2022___14_11_20/logs/klayout_zeroarea_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/31_MAY_2022___14_11_20/logs/klayout_zeroarea_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/31_MAY_2022___14_11_20/logs/magic_drc_check.log b/precheck_results/31_MAY_2022___14_11_20/logs/magic_drc_check.log
new file mode 100644
index 0000000..75c65b2
--- /dev/null
+++ b/precheck_results/31_MAY_2022___14_11_20/logs/magic_drc_check.log
@@ -0,0 +1,30 @@
+
+Magic 8.3 revision 274 - Compiled on Fri Mar 4 22:54:15 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Could not find file '/usr/local/share/pdk/sky130A/sky130A/libs.tech/magic/sky130A.tech' in any of these directories:
+ . $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Error parsing "/home/krishna/mpw_precheck/checks/tech-files/sky130A.magicrc": couldn't read file "/usr/local/share/pdk/sky130A/sky130A/libs.tech/magic/sky130A.tcl": no such file or directory
+Bad local startup file "/home/krishna/mpw_precheck/checks/tech-files/sky130A.magicrc", continuing without.
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading "/home/krishna/mpw_precheck/checks/drc_checks/magic/magic_drc_check.tcl" from command line.
+Don't know how to read GDS-II:
+Nothing in "cifinput" section of tech file.
+[INFO]: Loading user_analog_project_wrapper
+
+File user_analog_project_wrapper.mag couldn't be read
+No such file or directory
+Creating new cell
+"drc(full)" is not one of the DRC styles Magic knows.
+The current style is "default".
+The DRC styles are: default.
+No errors found.
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+[INFO]: DRC Checking DONE (/home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___14_11_20/outputs/reports/magic_drc_check.drc.report)
+[INFO]: Saving mag view with DRC errors(/home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___14_11_20/outputs/user_analog_project_wrapper.magic.drc.mag)
+[INFO]: Saved
diff --git a/precheck_results/31_MAY_2022___14_11_20/logs/magic_drc_check.total b/precheck_results/31_MAY_2022___14_11_20/logs/magic_drc_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/31_MAY_2022___14_11_20/logs/magic_drc_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/31_MAY_2022___14_11_20/logs/pdks.info b/precheck_results/31_MAY_2022___14_11_20/logs/pdks.info
new file mode 100644
index 0000000..3072015
--- /dev/null
+++ b/precheck_results/31_MAY_2022___14_11_20/logs/pdks.info
@@ -0,0 +1,2 @@
+Open PDKs a3d6ffea8022332b859daa454cef7ee7131c5181
+Skywater PDK f70d8ca46961ff92719d8870a18a076370b85f6c
\ No newline at end of file
diff --git a/precheck_results/31_MAY_2022___14_11_20/logs/precheck.log b/precheck_results/31_MAY_2022___14_11_20/logs/precheck.log
new file mode 100644
index 0000000..5ca22be
--- /dev/null
+++ b/precheck_results/31_MAY_2022___14_11_20/logs/precheck.log
@@ -0,0 +1,62 @@
+2022-05-31 14:11:20 - [INFO] - {{EXTRACTING FILES}} Extracting compressed files in: /home/krishna/Strong_Arm_MPW6
+2022-05-31 14:11:20 - [INFO] - {{Project Type Info}} analog
+2022-05-31 14:11:20 - [INFO] - {{Project GDS Info}} user_analog_project_wrapper: abb23bc6d6891972936e14fe7b9382be38c46d6f
+2022-05-31 14:11:22 - [INFO] - {{Tools Info}} KLayout: v0.27.8 | Magic: v8.3.274
+2022-05-31 14:11:22 - [INFO] - {{PDKs Info}} Open PDKs: a3d6ffea8022332b859daa454cef7ee7131c5181 | Skywater PDK: f70d8ca46961ff92719d8870a18a076370b85f6c
+2022-05-31 14:11:22 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in '/home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___14_11_20/logs'
+2022-05-31 14:11:22 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: [License, Makefile, Default, Documentation, Consistency, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea]
+2022-05-31 14:11:22 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 13: License
+2022-05-31 14:11:23 - [INFO] - An approved LICENSE (Apache-2.0) was found in /home/krishna/Strong_Arm_MPW6.
+2022-05-31 14:11:23 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
+2022-05-31 14:11:24 - [INFO] - An approved LICENSE (Apache-2.0) was found in /home/krishna/Strong_Arm_MPW6.
+2022-05-31 14:11:24 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
+2022-05-31 14:11:24 - [ERROR] - SPDX COMPLIANCE SYMLINK FILE NOT FOUND in /home/krishna/Strong_Arm_MPW6/openlane/Makefile
+2022-05-31 14:11:24 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (/home/krishna/Strong_Arm_MPW6/netgen/.run_lvs_wrapper_xschem.sh.swp): 'utf-8' codec can't decode byte 0xd2 in position 20: invalid continuation byte
+2022-05-31 14:11:24 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 93 non-compliant file(s) with the SPDX Standard.
+2022-05-31 14:11:24 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['/home/krishna/Strong_Arm_MPW6/Makefile', '/home/krishna/Strong_Arm_MPW6/verilog/dv/Makefile', '/home/krishna/Strong_Arm_MPW6/verilog/dv/mprj_por/mprj_por.c', '/home/krishna/Strong_Arm_MPW6/verilog/dv/mprj_por/mprj_por_tb.v', '/home/krishna/Strong_Arm_MPW6/verilog/dv/mprj_por/Makefile', '/home/krishna/Strong_Arm_MPW6/verilog/rtl/uprj_analog_netlists.v', '/home/krishna/Strong_Arm_MPW6/verilog/rtl/example_por.v', '/home/krishna/Strong_Arm_MPW6/verilog/rtl/user_analog_proj_example.v', '/home/krishna/Strong_Arm_MPW6/verilog/rtl/user_analog_project_wrapper.v', '/home/krishna/Strong_Arm_MPW6/verilog/rtl/comparator.v', '/home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___08_35_25/logs/tools.info', '/home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___08_35_25/logs/gds.info', '/home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___08_35_25/logs/pdks.info', '/home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___14_11_20/logs/tools.info', '/home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___14_11_20/logs/gds.info']
+2022-05-31 14:11:24 - [INFO] - For the full SPDX compliance report check: /home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___14_11_20/logs/spdx_compliance_report.log
+2022-05-31 14:11:24 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 13: Makefile
+2022-05-31 14:11:24 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
+2022-05-31 14:11:24 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 13: Default
+2022-05-31 14:11:24 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
+2022-05-31 14:11:24 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
+2022-05-31 14:11:24 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 13: Documentation
+2022-05-31 14:11:24 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
+2022-05-31 14:11:24 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 13: Consistency
+2022-05-31 14:11:26 - [INFO] - HIERARCHY CHECK PASSED: Module user_analog_project_wrapper is instantiated in caravan.
+2022-05-31 14:11:26 - [INFO] - COMPLEXITY CHECK PASSED: Netlist caravan contains at least 8 instances (68 instances).
+2022-05-31 14:11:26 - [INFO] - MODELING CHECK PASSED: Netlist caravan is structural.
+2022-05-31 14:11:26 - [INFO] - SUBMODULE HOOKS CHECK PASSED: All module ports for user_analog_project_wrapper are correctly connected in the top level netlist caravan.
+2022-05-31 14:11:26 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravan netlist passed all consistency checks.
+2022-05-31 14:11:26 - [INFO] - PORTS CHECK PASSED: Netlist user_analog_project_wrapper ports match the golden wrapper ports
+2022-05-31 14:11:26 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_analog_project_wrapper contains at least 1 instances (12 instances).
+2022-05-31 14:11:26 - [INFO] - MODELING CHECK PASSED: Netlist user_analog_project_wrapper is structural.
+2022-05-31 14:11:26 - [INFO] - LAYOUT CHECK PASSED: The GDS layout for user_analog_project_wrapper matches the provided structural netlist.
+2022-05-31 14:11:26 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} user_analog_project_wrapper netlist passed all consistency checks.
+2022-05-31 14:11:26 - [INFO] - {{CONSISTENCY CHECK PASSED}} The user netlist and the top netlist are valid.
+2022-05-31 14:11:26 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 13: XOR
+2022-05-31 14:11:28 - [ERROR] - XOR CHECK FILE NOT FOUND in /home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___14_11_20/logs/xor_check.total
+2022-05-31 14:11:28 - [WARNING] - {{XOR CHECK FAILED}} The GDS file has non-conforming geometries.
+2022-05-31 14:11:28 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 13: Magic DRC
+2022-05-31 14:11:28 - [INFO] - 0 DRC violations
+2022-05-31 14:11:28 - [INFO] - {{MAGIC DRC CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-05-31 14:11:28 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 13: Klayout FEOL
+2022-05-31 14:11:31 - [INFO] - No DRC Violations found
+2022-05-31 14:11:31 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-05-31 14:11:31 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 13: Klayout BEOL
+2022-05-31 14:11:35 - [INFO] - No DRC Violations found
+2022-05-31 14:11:35 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-05-31 14:11:35 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 13: Klayout Offgrid
+2022-05-31 14:11:38 - [INFO] - No DRC Violations found
+2022-05-31 14:11:38 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-05-31 14:11:38 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 13: Klayout Metal Minimum Clear Area Density
+2022-05-31 14:11:39 - [INFO] - No DRC Violations found
+2022-05-31 14:11:39 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-05-31 14:11:39 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 13: Klayout Pin Label Purposes Overlapping Drawing
+2022-05-31 14:11:40 - [INFO] - No DRC Violations found
+2022-05-31 14:11:40 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-05-31 14:11:40 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 13: Klayout ZeroArea
+2022-05-31 14:11:41 - [INFO] - No DRC Violations found
+2022-05-31 14:11:41 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-05-31 14:11:41 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in '/home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___14_11_20/logs'
+2022-05-31 14:11:41 - [CRITICAL] - {{FAILURE}} 1 Check(s) Failed: ['XOR'] !!!
diff --git a/precheck_results/31_MAY_2022___14_11_20/logs/spdx_compliance_report.log b/precheck_results/31_MAY_2022___14_11_20/logs/spdx_compliance_report.log
new file mode 100644
index 0000000..ff41d24
--- /dev/null
+++ b/precheck_results/31_MAY_2022___14_11_20/logs/spdx_compliance_report.log
@@ -0,0 +1,93 @@
+/home/krishna/Strong_Arm_MPW6/Makefile
+/home/krishna/Strong_Arm_MPW6/verilog/dv/Makefile
+/home/krishna/Strong_Arm_MPW6/verilog/dv/mprj_por/mprj_por.c
+/home/krishna/Strong_Arm_MPW6/verilog/dv/mprj_por/mprj_por_tb.v
+/home/krishna/Strong_Arm_MPW6/verilog/dv/mprj_por/Makefile
+/home/krishna/Strong_Arm_MPW6/verilog/rtl/uprj_analog_netlists.v
+/home/krishna/Strong_Arm_MPW6/verilog/rtl/example_por.v
+/home/krishna/Strong_Arm_MPW6/verilog/rtl/user_analog_proj_example.v
+/home/krishna/Strong_Arm_MPW6/verilog/rtl/user_analog_project_wrapper.v
+/home/krishna/Strong_Arm_MPW6/verilog/rtl/comparator.v
+/home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___08_35_25/logs/tools.info
+/home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___08_35_25/logs/gds.info
+/home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___08_35_25/logs/pdks.info
+/home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___14_11_20/logs/tools.info
+/home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___14_11_20/logs/gds.info
+/home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___14_11_20/logs/pdks.info
+/home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___07_11_48/logs/tools.info
+/home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___07_11_48/logs/gds.info
+/home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___07_11_48/logs/pdks.info
+/home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___08_42_48/logs/tools.info
+/home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___08_42_48/logs/gds.info
+/home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___08_42_48/logs/pdks.info
+/home/krishna/Strong_Arm_MPW6/mag/sky130_fd_pr__pfet_01v8_AC5Z8B#0.ext
+/home/krishna/Strong_Arm_MPW6/mag/compaartor_v4.ext
+/home/krishna/Strong_Arm_MPW6/mag/inv_W2.ext
+/home/krishna/Strong_Arm_MPW6/mag/sky130_fd_pr__diode_pw2nd_05v5_KLAK3C.ext
+/home/krishna/Strong_Arm_MPW6/mag/sky130_fd_pr__diode_pw2nd_05v5_FT7GK8.ext
+/home/krishna/Strong_Arm_MPW6/mag/comparator_SA.ext
+/home/krishna/Strong_Arm_MPW6/mag/inv_W2#0.ext
+/home/krishna/Strong_Arm_MPW6/mag/.magicrc
+/home/krishna/Strong_Arm_MPW6/mag/inv_W1#0.ext
+/home/krishna/Strong_Arm_MPW6/mag/sky130_fd_pr__nfet_01v8_XJTKXQ#1.ext
+/home/krishna/Strong_Arm_MPW6/mag/sky130_fd_pr__nfet_01v8_XJTKXQ.ext
+/home/krishna/Strong_Arm_MPW6/mag/sky130_fd_pr__pfet_01v8_AC5Z8B.ext
+/home/krishna/Strong_Arm_MPW6/mag/buffer_2#1.ext
+/home/krishna/Strong_Arm_MPW6/mag/buffer_1#0.ext
+/home/krishna/Strong_Arm_MPW6/mag/sky130_fd_pr__pfet_01v8_5233FE.ext
+/home/krishna/Strong_Arm_MPW6/mag/user_analog_project_wrapper.ext
+/home/krishna/Strong_Arm_MPW6/mag/buffer_2#0.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/inv_W2.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_VJWT33.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_7RYEVP.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_RL4NCG.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_5C3Z5B.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_KZU588.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/inv.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/buffer_1.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/nmos_1u.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_5YYKDE.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/inv_W22.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/pmos_2uf2.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/sky130A.magicrc
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_KBWVY9.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_3M44SC.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/.magicrc
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/buffer_2.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/inv_W8.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/buffer_sample_lay.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_XJTKXQ.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_QQ4XG9.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_AC5Z8B.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/inv_W1.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/.spiceinit
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/buffer_12.ext
+/home/krishna/Strong_Arm_MPW6/mag/myinv_layout2/inv_W16.ext
+/home/krishna/Strong_Arm_MPW6/mag/latch/SR_latch.ext
+/home/krishna/Strong_Arm_MPW6/mag/latch/latch_2SA.ext
+/home/krishna/Strong_Arm_MPW6/mag/latch/sky130_fd_pr__pfet_01v8_AC5E9B.ext
+/home/krishna/Strong_Arm_MPW6/mag/latch/.magicrc
+/home/krishna/Strong_Arm_MPW6/mag/latch/sky130_fd_pr__nfet_01v8_F5U58G.ext
+/home/krishna/Strong_Arm_MPW6/mag/latch/latch_2.ext
+/home/krishna/Strong_Arm_MPW6/mag/latch/sky130_fd_pr__pfet_01v8_5SVZDE.ext
+/home/krishna/Strong_Arm_MPW6/mag/preamp/sky130_fd_pr__nfet_01v8_G6PLX8.ext
+/home/krishna/Strong_Arm_MPW6/mag/preamp/preamp_part1SA.ext
+/home/krishna/Strong_Arm_MPW6/mag/preamp/.magicrc
+/home/krishna/Strong_Arm_MPW6/mag/preamp/sky130_fd_pr__pfet_01v8_5Y8GKB.ext
+/home/krishna/Strong_Arm_MPW6/mag/preamp/sky130_fd_pr__nfet_01v8_NHLLAS.ext
+/home/krishna/Strong_Arm_MPW6/xschem/xschemrc
+/home/krishna/Strong_Arm_MPW6/xschem/comparator_lvs.sch
+/home/krishna/Strong_Arm_MPW6/xschem/user_analog_project_wrapper.sym
+/home/krishna/Strong_Arm_MPW6/xschem/comparator.sch
+/home/krishna/Strong_Arm_MPW6/xschem/comparator.sym
+/home/krishna/Strong_Arm_MPW6/xschem/analog_wrapper_tb.sch
+/home/krishna/Strong_Arm_MPW6/xschem/user_analog_project_wrapper.sch
+/home/krishna/Strong_Arm_MPW6/xschem/.spiceinit
+/home/krishna/Strong_Arm_MPW6/xschem/comparator_tb.sch
+/home/krishna/Strong_Arm_MPW6/docs/Makefile
+/home/krishna/Strong_Arm_MPW6/docs/environment.yml
+/home/krishna/Strong_Arm_MPW6/docs/source/conf.py
+/home/krishna/Strong_Arm_MPW6/docs/source/index.rst
+/home/krishna/Strong_Arm_MPW6/netgen/run_lvs_wrapper_verilog.sh
+/home/krishna/Strong_Arm_MPW6/netgen/run_lvs_por.sh
+/home/krishna/Strong_Arm_MPW6/netgen/run_lvs_wrapper_xschem.sh
diff --git a/precheck_results/31_MAY_2022___14_11_20/logs/tools.info b/precheck_results/31_MAY_2022___14_11_20/logs/tools.info
new file mode 100644
index 0000000..9b2230a
--- /dev/null
+++ b/precheck_results/31_MAY_2022___14_11_20/logs/tools.info
@@ -0,0 +1,2 @@
+KLayout: 0.27.8
+Magic: 8.3.274
\ No newline at end of file
diff --git a/precheck_results/31_MAY_2022___14_11_20/logs/xor_check.log b/precheck_results/31_MAY_2022___14_11_20/logs/xor_check.log
new file mode 100644
index 0000000..1259cee
--- /dev/null
+++ b/precheck_results/31_MAY_2022___14_11_20/logs/xor_check.log
@@ -0,0 +1,179 @@
+Reading file /home/krishna/Strong_Arm_MPW6/gds/user_analog_project_wrapper.gds for cell user_analog_project_wrapper
+dbu=0.001
+cell user_analog_project_wrapper dbu-bbox(ll;ur)=(-4000,-4000;2924000,3524000)
+cell user_analog_project_wrapper dbu-bbox(left,bottom,right,top)=(-4000,-4000,2924000,3524000)
+cell user_analog_project_wrapper dbu-size(width,height)=(2928000,3528000)
+cell user_analog_project_wrapper micron-bbox(left,bottom,right,top)=(-4.0,-4.0,2924.0,3524.0)
+cell user_analog_project_wrapper micron-size(width,height)=(2928.0,3528.0)
+Done.
+
+Magic 8.3 revision 274 - Compiled on Fri Mar 4 22:54:15 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Loading "/home/krishna/mpw_precheck/checks/xor_check/erase_box.tcl" from command line.
+"sky130(vendor)" is not one of the CIF input styles Magic knows.
+Error: No style is set
+The CIF input styles are: .
+Don't know how to read GDS-II:
+Nothing in "cifinput" section of tech file.
+File user_analog_project_wrapper.mag couldn't be read
+No such file or directory
+Creating new cell
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 43.000 x 3520.000 (-43.000, 0.000), ( 0.000, 3520.000) 151360.000
+lambda: 43 x 3520 ( -43, 0 ), ( 0, 3520 ) 151360
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 43.000 x 3520.000 ( 2920.000, 0.000), ( 2963.000, 3520.000) 151360.000
+lambda: 43 x 3520 ( 2920, 0 ), ( 2963, 3520 ) 151360
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 3006.000 x 38.000 (-43.000, -38.000), ( 2963.000, 0.000) 114228.000
+lambda: 3006 x 38 ( -43, -38 ), ( 2963, 0 ) 114228
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 3006.000 x 37.000 (-43.000, 3520.000), ( 2963.000, 3557.000) 111222.000
+lambda: 3006 x 37 ( -43, 3520 ), ( 2963, 3557 ) 111222
+Unrecognized layer: metal5
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal4
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal5
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal4
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+No CIF/GDS output style set!
+I/O error in writing file /home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___14_11_20/outputs/user_analog_project_wrapper_erased.gds.
+File may be incompletely written.
+
+Magic 8.3 revision 274 - Compiled on Fri Mar 4 22:54:15 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Loading "/home/krishna/mpw_precheck/checks/xor_check/erase_box.tcl" from command line.
+"sky130(vendor)" is not one of the CIF input styles Magic knows.
+Error: No style is set
+The CIF input styles are: .
+Don't know how to read GDS-II:
+Nothing in "cifinput" section of tech file.
+File user_analog_project_wrapper.mag couldn't be read
+No such file or directory
+Creating new cell
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 43.000 x 3520.000 (-43.000, 0.000), ( 0.000, 3520.000) 151360.000
+lambda: 43 x 3520 ( -43, 0 ), ( 0, 3520 ) 151360
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 43.000 x 3520.000 ( 2920.000, 0.000), ( 2963.000, 3520.000) 151360.000
+lambda: 43 x 3520 ( 2920, 0 ), ( 2963, 3520 ) 151360
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 3006.000 x 38.000 (-43.000, -38.000), ( 2963.000, 0.000) 114228.000
+lambda: 3006 x 38 ( -43, -38 ), ( 2963, 0 ) 114228
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 3006.000 x 37.000 (-43.000, 3520.000), ( 2963.000, 3557.000) 111222.000
+lambda: 3006 x 37 ( -43, 3520 ), ( 2963, 3557 ) 111222
+Unrecognized layer: metal5
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal4
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal5
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal4
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+No CIF/GDS output style set!
+I/O error in writing file /home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___14_11_20/outputs/user_analog_project_wrapper_empty_erased.gds.
+File may be incompletely written.
+Reading /home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___14_11_20/outputs/user_analog_project_wrapper_erased.gds ..
+ERROR: In /home/krishna/mpw_precheck/checks/xor_check/xor.rb.drc: 'source': Stream has unknown format: /home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___14_11_20/outputs/user_analog_project_wrapper_erased.gds in Layout::read
+Total elapsed: 0.010s Memory: 521.00M
+ERROR: 'source': Stream has unknown format: /home/krishna/Strong_Arm_MPW6/precheck_results/31_MAY_2022___14_11_20/outputs/user_analog_project_wrapper_erased.gds in Layout::read in Executable::execute
+ /home/krishna/mpw_precheck/checks/xor_check/xor.rb.drc:15:in `execute'
+ :/built-in-macros/drc_interpreters.lym:27:in `instance_eval'
+ :/built-in-macros/drc_interpreters.lym:27:in `execute'
diff --git a/precheck_results/31_MAY_2022___14_11_20/outputs/reports/klayout_beol_check.xml b/precheck_results/31_MAY_2022___14_11_20/outputs/reports/klayout_beol_check.xml
new file mode 100644
index 0000000..12e54e4
--- /dev/null
+++ b/precheck_results/31_MAY_2022___14_11_20/outputs/reports/klayout_beol_check.xml
@@ -0,0 +1,447 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ <category>
+ <name>li.1</name>
+ <description>li.1 : min. li width : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li.3</name>
+ <description>li.3 : min. li spacing : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li.5</name>
+ <description>li.5 : min. li enclosure of licon of 2 adjacent edges : 0.08um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li.6</name>
+ <description>li.6 : min. li area : 0.0561um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.1</name>
+ <description>ct.1: non-ring mcon should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.1_a</name>
+ <description>ct.1_a : minimum width of mcon : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.1_b</name>
+ <description>ct.1_b : maximum length of mcon : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.2</name>
+ <description>ct.2 : min. mcon spacing : 0.19um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.4</name>
+ <description>ct.4 : mcon should covered by li</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.1</name>
+ <description>m1.1 : min. m1 width : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.2</name>
+ <description>m1.2 : min. m1 spacing : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.3ab</name>
+ <description>m1.3ab : min. 3um.m1 spacing m1 : 0.28um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>791_m1.4</name>
+ <description>791_m1.4 : min. m1 enclosure of mcon : 0.03um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.4</name>
+ <description>m1.4 : mcon periphery must be enclosed by m1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.4a</name>
+ <description>m1.4a : min. m1 enclosure of mcon for specific cells : 0.005um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.4a_a</name>
+ <description>m1.4a_a : mcon periph must be enclosed by met1 for specific cells</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.6</name>
+ <description>m1.6 : min. m1 area : 0.083um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.7</name>
+ <description>m1.7 : min. m1 with holes area : 0.14um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.5</name>
+ <description>m1.5 : min. m1 enclosure of mcon of 2 adjacent edges : 0.06um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.1a</name>
+ <description>via.1a : via outside of moduleCut should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.1a_a</name>
+ <description>via.1a_a : min. width of via outside of moduleCut : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.1a_b</name>
+ <description>via.1a_b : maximum length of via : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.2</name>
+ <description>via.2 : min. via spacing : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.4a</name>
+ <description>via.4a : min. m1 enclosure of 0.15um via : 0.055um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.4a_a</name>
+ <description>via.4a_a : 0.15um via must be enclosed by met1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.5a</name>
+ <description>via.5a : min. m1 enclosure of 0.15um via of 2 adjacent edges : 0.085um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.1</name>
+ <description>m2.1 : min. m2 width : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.2</name>
+ <description>m2.2 : min. m2 spacing : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.3ab</name>
+ <description>m2.3ab : min. 3um.m2 spacing m2 : 0.28um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.6</name>
+ <description>m2.6 : min. m2 area : 0.0676um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.7</name>
+ <description>m2.7 : min. m2 holes area : 0.14um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.4</name>
+ <description>m2.4 : min. m2 enclosure of via : 0.055um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.4_a</name>
+ <description>m2.4_a : via in periphery must be enclosed by met2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.5</name>
+ <description>m2.5 : min. m2 enclosure of via of 2 adjacent edges : 0.085um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.1a</name>
+ <description>via2.1a : via2 outside of moduleCut should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.1a_a</name>
+ <description>via2.1a_a : min. width of via2 outside of moduleCut : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.1a_b</name>
+ <description>via2.1a_b : maximum length of via2 : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.2</name>
+ <description>via2.2 : min. via2 spacing : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.4</name>
+ <description>via2.4 : min. m2 enclosure of via2 : 0.04um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.4_a</name>
+ <description>via2.4_a : via must be enclosed by met2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.5</name>
+ <description>via2.5 : min. m3 enclosure of via2 of 2 adjacent edges : 0.085um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.1</name>
+ <description>m3.1 : min. m3 width : 0.3um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.2</name>
+ <description>m3.2 : min. m3 spacing : 0.3um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.3cd</name>
+ <description>m3.3cd : min. 3um.m3 spacing m3 : 0.4um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.4</name>
+ <description>m3.4 : min. m3 enclosure of via2 : 0.065um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.4_a</name>
+ <description>m3.4_a : via2 must be enclosed by met3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.1</name>
+ <description>via3.1 : via3 outside of moduleCut should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.1_a</name>
+ <description>via3.1_a : min. width of via3 outside of moduleCut : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.1_b</name>
+ <description>via3.1_b : maximum length of via3 : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.2</name>
+ <description>via3.2 : min. via3 spacing : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.4</name>
+ <description>via3.4 : min. m3 enclosure of via3 : 0.06um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.4_a</name>
+ <description>via3.4_a : non-ring via3 must be enclosed by met3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.5</name>
+ <description>via3.5 : min. m3 enclosure of via3 of 2 adjacent edges : 0.09um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.1</name>
+ <description>m4.1 : min. m4 width : 0.3um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.2</name>
+ <description>m4.2 : min. m4 spacing : 0.3um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.4a</name>
+ <description>m4.4a : min. m4 area : 0.240um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.5ab</name>
+ <description>m4.5ab : min. 3um.m4 spacing m4 : 0.4um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.3</name>
+ <description>m4.3 : min. m4 enclosure of via3 : 0.065um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.3_a</name>
+ <description>m4.3_a : via3 must be enclosed by met4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.1</name>
+ <description>via4.1 : via4 outside of moduleCut should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.1_a</name>
+ <description>via4.1_a : min. width of via4 outside of moduleCut : 0.8um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.1_b</name>
+ <description>via4.1_b : maximum length of via4 : 0.8um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.2</name>
+ <description>via4.2 : min. via4 spacing : 0.8um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.4</name>
+ <description>via4.4 : min. m4 enclosure of via4 : 0.19um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.4_a</name>
+ <description>via4.4_a : m4 must enclose all via4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.1</name>
+ <description>m5.1 : min. m5 width : 1.6um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.2</name>
+ <description>m5.2 : min. m5 spacing : 1.6um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.3</name>
+ <description>m5.3 : min. m5 enclosure of via4 : 0.31um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.3_a</name>
+ <description>m5.3_a : via must be enclosed by m5</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.4</name>
+ <description>m5.4 : min. m5 area : 4.0um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pad.2</name>
+ <description>pad.2 : min. pad spacing : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/31_MAY_2022___14_11_20/outputs/reports/klayout_feol_check.xml b/precheck_results/31_MAY_2022___14_11_20/outputs/reports/klayout_feol_check.xml
new file mode 100644
index 0000000..d0ecd3f
--- /dev/null
+++ b/precheck_results/31_MAY_2022___14_11_20/outputs/reports/klayout_feol_check.xml
@@ -0,0 +1,363 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ <category>
+ <name>dnwell.2</name>
+ <description>dnwell.2 : min. dnwell width : 3.0um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell.1</name>
+ <description>nwell.1 : min. nwell width : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell.2a</name>
+ <description>nwell.2a : min. nwell spacing (merged if less) : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell.6</name>
+ <description>nwell.6 : min enclosure of nwellHole by dnwell : 1.03um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp.1</name>
+ <description>hvtp.1 : min. hvtp width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp.2</name>
+ <description>hvtp.2 : min. hvtp spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr.1</name>
+ <description>hvtr.1 : min. hvtr width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr.2</name>
+ <description>hvtr.2 : min. hvtr spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr.2_a</name>
+ <description>hvtr.2_a : hvtr must not overlap hvtp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn.1a</name>
+ <description>lvtn.1a : min. lvtn width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn.2</name>
+ <description>lvtn.2 : min. lvtn spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm.1</name>
+ <description>ncm.1 : min. ncm width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm.2a</name>
+ <description>ncm.2a : min. ncm spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1</name>
+ <description>difftap.1 : min. diff width across areaid:ce : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1_a</name>
+ <description>difftap.1_a : min. diff width in periphery : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1_b</name>
+ <description>difftap.1_b : min. tap width across areaid:ce : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1_c</name>
+ <description>difftap.1_c : min. tap width in periphery : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.3</name>
+ <description>difftap.3 : min. difftap spacing : 0.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm.1</name>
+ <description>tunm.1 : min. tunm width : 0.41um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm.2</name>
+ <description>tunm.2 : min. tunm spacing : 0.5um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly.1a</name>
+ <description>poly.1a : min. poly width : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly.2</name>
+ <description>poly.2 : min. poly spacing : 0.21um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm.1a</name>
+ <description>rpm.1a : min. rpm width : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm.2</name>
+ <description>rpm.2 : min. rpm spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>urpm.1a</name>
+ <description>urpm.1a : min. rpm width : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>urpm.2</name>
+ <description>urpm.2 : min. rpm spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc.1</name>
+ <description>npc.1 : min. npc width : 0.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc.2</name>
+ <description>npc.2 : min. npc spacing, should be manually merged if less than : 0.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsd.1</name>
+ <description>nsd.1 : min. nsdm width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsd.2</name>
+ <description>nsd.2 : min. nsdm spacing, should be manually merged if less than : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psd.1</name>
+ <description>psd.1 : min. psdm width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psd.2</name>
+ <description>psd.2 : min. psdm spacing, should be manually merged if less than : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.1</name>
+ <description>licon.1 : licon should be rectangle</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.1_a/b</name>
+ <description>licon.1_a/b : minimum/maximum width of licon : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.13</name>
+ <description>licon.13 : min. difftap licon spacing to npc : 0.09um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.13_a</name>
+ <description>licon.13_a : licon of diffTap in periphery must not overlap npc</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.17</name>
+ <description>licon.17 : Licons may not overlap both poly and (diff or tap)</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.1</name>
+ <description>capm.1 : min. capm width : 1.0um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.2a</name>
+ <description>capm.2a : min. capm spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.2b</name>
+ <description>capm.2b : min. capm spacing : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.2b_a</name>
+ <description>capm.2b_a : min. spacing of m3_bot_plate : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.3</name>
+ <description>capm.3 : min. capm and m3 enclosure of m3 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.3_a</name>
+ <description>capm.3_a : min. m3 enclosure of capm : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.4</name>
+ <description>capm.4 : min. capm enclosure of via3 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.5</name>
+ <description>capm.5 : min. capm spacing to via3 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.1</name>
+ <description>cap2m.1 : min. cap2m width : 1.0um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.2a</name>
+ <description>cap2m.2a : min. cap2m spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.2b</name>
+ <description>cap2m.2b : min. cap2m spacing : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.2b_a</name>
+ <description>cap2m.2b_a : min. spacing of m4_bot_plate : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.3</name>
+ <description>cap2m.3 : min. m4 enclosure of cap2m : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.3_a</name>
+ <description>cap2m.3_a : min. m4 enclosure of cap2m : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.4</name>
+ <description>cap2m.4 : min. cap2m enclosure of via4 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.5</name>
+ <description>cap2m.5 : min. cap2m spacing to via4 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi.1</name>
+ <description>hvi.1 : min. hvi width : 0.6um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi.2a</name>
+ <description>hvi.2a : min. hvi spacing : 0.7um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm.1</name>
+ <description>hvntm.1 : min. hvntm width : 0.7um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm.2</name>
+ <description>hvntm.2 : min. hvntm spacing : 0.7um</description>
+ <categories>
+ </categories>
+ </category>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/31_MAY_2022___14_11_20/outputs/reports/klayout_met_min_ca_density_check.xml b/precheck_results/31_MAY_2022___14_11_20/outputs/reports/klayout_met_min_ca_density_check.xml
new file mode 100644
index 0000000..cdcd318
--- /dev/null
+++ b/precheck_results/31_MAY_2022___14_11_20/outputs/reports/klayout_met_min_ca_density_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>Density Checks</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/drc_checks/klayout/met_min_ca_density.lydrc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/31_MAY_2022___14_11_20/outputs/reports/klayout_offgrid_check.xml b/precheck_results/31_MAY_2022___14_11_20/outputs/reports/klayout_offgrid_check.xml
new file mode 100644
index 0000000..b69c1b3
--- /dev/null
+++ b/precheck_results/31_MAY_2022___14_11_20/outputs/reports/klayout_offgrid_check.xml
@@ -0,0 +1,483 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ <category>
+ <name>dnwell_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on dnwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>dnwell_angle</name>
+ <description>x.3a : non 45 degree angle dnwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on nwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell_angle</name>
+ <description>x.3a : non 45 degree angle nwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwbm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pwbm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwbm_angle</name>
+ <description>x.3a : non 45 degree angle pwbm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwde_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pwde</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwde_angle</name>
+ <description>x.3a : non 45 degree angle pwde</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvtp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp_angle</name>
+ <description>x.3a : non 45 degree angle hvtp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvtr</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr_angle</name>
+ <description>x.3a : non 45 degree angle hvtr</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on lvtn</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn_angle</name>
+ <description>x.3a : non 45 degree angle lvtn</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on ncm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm_angle</name>
+ <description>x.3a : non 45 degree angle ncm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>diff_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on diff</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tap_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on tap</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>diff_angle</name>
+ <description>x.2 : non 90 degree angle diff</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>diff_angle</name>
+ <description>x.2c : non 45 degree angle diff</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tap_angle</name>
+ <description>x.2 : non 90 degree angle tap</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tap_angle</name>
+ <description>x.2c : non 45 degree angle tap</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on tunm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm_angle</name>
+ <description>x.3a : non 45 degree angle tunm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on poly</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly_angle</name>
+ <description>x.2 : non 90 degree angle poly</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on rpm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm_angle</name>
+ <description>x.3a : non 45 degree angle rpm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on npc</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc_angle</name>
+ <description>x.3a : non 45 degree angle npc</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsdm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on nsdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsdm_angle</name>
+ <description>x.3a : non 45 degree angle nsdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psdm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on psdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psdm_angle</name>
+ <description>x.3a : non 45 degree angle psdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on licon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon_angle</name>
+ <description>x.2 : non 90 degree angle licon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on li</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li_angle</name>
+ <description>x.3a : non 45 degree angle li</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on mcon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct_angle</name>
+ <description>x.2 : non 90 degree angle mcon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vpp_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on vpp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vpp_angle</name>
+ <description>x.3a : non 45 degree angle vpp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1_angle</name>
+ <description>x.3a : non 45 degree angle m1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via_angle</name>
+ <description>x.2 : non 90 degree angle via</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2_angle</name>
+ <description>x.3a : non 45 degree angle m2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2_angle</name>
+ <description>x.2 : non 90 degree angle via2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3_angle</name>
+ <description>x.3a : non 45 degree angle m3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3_angle</name>
+ <description>x.2 : non 90 degree angle via3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on nsm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsm_angle</name>
+ <description>x.3a : non 45 degree angle nsm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4_angle</name>
+ <description>x.3a : non 45 degree angle m4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4_angle</name>
+ <description>x.2 : non 90 degree angle via4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m5</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5_angle</name>
+ <description>x.3a : non 45 degree angle m5</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pad_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pad</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pad_angle</name>
+ <description>x.3a : non 45 degree angle pad</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mf_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on mf</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mf_angle</name>
+ <description>x.2 : non 90 degree angle mf</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi_angle</name>
+ <description>x.3a : non 45 degree angle hvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvntm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm_angle</name>
+ <description>x.3a : non 45 degree angle hvntm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vhvi_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on vhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vhvi_angle</name>
+ <description>x.3a : non 45 degree angle vhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>uhvi_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on uhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>uhvi_angle</name>
+ <description>x.3a : non 45 degree angle uhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwell_rs_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pwell_rs</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwell_rs_angle</name>
+ <description>x.3a : non 45 degree angle pwell_rs</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>areaid_re_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on areaid.re</description>
+ <categories>
+ </categories>
+ </category>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/31_MAY_2022___14_11_20/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml b/precheck_results/31_MAY_2022___14_11_20/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
new file mode 100644
index 0000000..05746fb
--- /dev/null
+++ b/precheck_results/31_MAY_2022___14_11_20/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>pin_label_purposes_overlapping_drawing.rb.drc, input=/home/krishna/Strong_Arm_MPW6/gds/user_analog_project_wrapper.gds, topcell=user_analog_project_wrapper</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/drc_checks/klayout/pin_label_purposes_overlapping_drawing.rb.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/31_MAY_2022___14_11_20/outputs/reports/klayout_zeroarea_check.xml b/precheck_results/31_MAY_2022___14_11_20/outputs/reports/klayout_zeroarea_check.xml
new file mode 100644
index 0000000..885685a
--- /dev/null
+++ b/precheck_results/31_MAY_2022___14_11_20/outputs/reports/klayout_zeroarea_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>zero area check</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/drc_checks/klayout/zeroarea.rb.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/31_MAY_2022___14_11_20/outputs/reports/magic_drc_check.drc.report b/precheck_results/31_MAY_2022___14_11_20/outputs/reports/magic_drc_check.drc.report
new file mode 100644
index 0000000..829b9d5
--- /dev/null
+++ b/precheck_results/31_MAY_2022___14_11_20/outputs/reports/magic_drc_check.drc.report
@@ -0,0 +1,5 @@
+user_analog_project_wrapper
+----------------------------------------
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+
diff --git a/precheck_results/31_MAY_2022___14_11_20/outputs/reports/magic_drc_check.rdb b/precheck_results/31_MAY_2022___14_11_20/outputs/reports/magic_drc_check.rdb
new file mode 100644
index 0000000..8a882f3
--- /dev/null
+++ b/precheck_results/31_MAY_2022___14_11_20/outputs/reports/magic_drc_check.rdb
@@ -0,0 +1,2 @@
+$user_analog_project_wrapper
+ 100
diff --git a/precheck_results/31_MAY_2022___14_11_20/outputs/reports/magic_drc_check.tcl b/precheck_results/31_MAY_2022___14_11_20/outputs/reports/magic_drc_check.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/precheck_results/31_MAY_2022___14_11_20/outputs/reports/magic_drc_check.tcl
diff --git a/precheck_results/31_MAY_2022___14_11_20/outputs/reports/magic_drc_check.tr b/precheck_results/31_MAY_2022___14_11_20/outputs/reports/magic_drc_check.tr
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/precheck_results/31_MAY_2022___14_11_20/outputs/reports/magic_drc_check.tr
diff --git a/precheck_results/31_MAY_2022___14_11_20/outputs/reports/magic_drc_check.xml b/precheck_results/31_MAY_2022___14_11_20/outputs/reports/magic_drc_check.xml
new file mode 100644
index 0000000..7161d7c
--- /dev/null
+++ b/precheck_results/31_MAY_2022___14_11_20/outputs/reports/magic_drc_check.xml
@@ -0,0 +1,10 @@
+<?xml version="1.0" ?>
+<report-database>
+ <categories/>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ </cell>
+ </cells>
+ <items/>
+</report-database>
diff --git a/precheck_results/31_MAY_2022___14_11_20/outputs/user_analog_project_wrapper.magic.drc.mag b/precheck_results/31_MAY_2022___14_11_20/outputs/user_analog_project_wrapper.magic.drc.mag
new file mode 100644
index 0000000..bc7865b
--- /dev/null
+++ b/precheck_results/31_MAY_2022___14_11_20/outputs/user_analog_project_wrapper.magic.drc.mag
@@ -0,0 +1,7 @@
+magic
+tech minimum
+magscale 1 2
+timestamp 0
+<< checkpaint >>
+rect 0 0 1 1
+<< end >>
diff --git a/precheck_results/31_MAY_2022___14_11_20/outputs/user_analog_project_wrapper_empty_erased.gds b/precheck_results/31_MAY_2022___14_11_20/outputs/user_analog_project_wrapper_empty_erased.gds
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/precheck_results/31_MAY_2022___14_11_20/outputs/user_analog_project_wrapper_empty_erased.gds
diff --git a/precheck_results/31_MAY_2022___14_11_20/outputs/user_analog_project_wrapper_erased.gds b/precheck_results/31_MAY_2022___14_11_20/outputs/user_analog_project_wrapper_erased.gds
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/precheck_results/31_MAY_2022___14_11_20/outputs/user_analog_project_wrapper_erased.gds
diff --git a/precheck_results/31_MAY_2022___14_11_20/outputs/user_analog_project_wrapper_no_zero_areas.gds b/precheck_results/31_MAY_2022___14_11_20/outputs/user_analog_project_wrapper_no_zero_areas.gds
new file mode 100644
index 0000000..72ed04d
--- /dev/null
+++ b/precheck_results/31_MAY_2022___14_11_20/outputs/user_analog_project_wrapper_no_zero_areas.gds
Binary files differ
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
new file mode 100644
index 0000000..a9c2027
--- /dev/null
+++ b/verilog/dv/Makefile
@@ -0,0 +1,39 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# ---- Test patterns for project striVe ----
+
+.SUFFIXES:
+.SILENT: clean all
+
+PATTERNS = mprj_por
+
+all: ${PATTERNS}
+ for i in ${PATTERNS}; do \
+ ( cd $$i && make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \
+ done
+
+DV_PATTERNS = $(foreach dv, $(PATTERNS), verify-$(dv))
+$(DV_PATTERNS): verify-% :
+ cd $* && make
+
+clean: ${PATTERNS}
+ for i in ${PATTERNS}; do \
+ ( cd $$i && make clean ) ; \
+ done
+ rm -rf *.log
+
+.PHONY: clean all
diff --git a/verilog/dv/README.md b/verilog/dv/README.md
new file mode 100644
index 0000000..6be9cd3
--- /dev/null
+++ b/verilog/dv/README.md
@@ -0,0 +1,131 @@
+<!---
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+-->
+
+# Simulation Environment Setup
+
+There are two options for setting up the simulation environment:
+
+* Pulling a pre-built docker image
+* Installing the dependecies locally
+
+## 1. Docker
+
+There is an available docker setup with the needed tools at [efabless/dockerized-verification-setup](https://github.com/efabless/dockerized-verification-setup)
+
+Run the following to pull the image:
+
+```
+docker pull efabless/dv_setup:latest
+```
+
+## 2. Local Installion (Linux)
+
+You will need to fullfil these dependecies:
+
+* Icarus Verilog (10.2+)
+* RV32I Toolchain
+
+Using apt, you can install Icarus Verilog:
+
+```bash
+sudo apt-get install iverilog
+```
+
+Next, you will need to build the RV32I toolchain. Firstly, export the installation path for the RV32I toolchain,
+
+```bash
+export GCC_PATH=<gcc-installation-path>
+```
+
+Then, run the following:
+
+```bash
+# packages needed:
+sudo apt-get install autoconf automake autotools-dev curl libmpc-dev \
+ libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo \
+ gperf libtool patchutils bc zlib1g-dev git libexpat1-dev
+
+sudo mkdir $GCC_PATH
+sudo chown $USER $GCC_PATH
+
+git clone https://github.com/riscv/riscv-gnu-toolchain riscv-gnu-toolchain-rv32i
+cd riscv-gnu-toolchain-rv32i
+git checkout 411d134
+git submodule update --init --recursive
+
+mkdir build; cd build
+../configure --with-arch=rv32i --prefix=$GCC_PATH
+make -j$(nproc)
+```
+
+# Running Simulation
+
+## Docker
+
+First, you will need to export a number of environment variables:
+
+```bash
+export PDK_PATH=<pdk-location/sky130A>
+export CARAVEL_ROOT=<caravel_root>
+export UPRJ_ROOT=<user_project_root>
+```
+
+Then, run the following command to start the docker container :
+
+```
+docker run -it -v $CARAVEL_ROOT:$CARAVEL_ROOT -v $PDK_PATH:$PDK_PATH -v $UPRJ_ROOT:$UPRJ_ROOT -e CARAVEL_ROOT=$CARAVEL_ROOT -e PDK_PATH=$PDK_PATH -e UPRJ_ROOT=$UPRJ_ROOT -u $(id -u $USER):$(id -g $USER) efabless/dv_setup:latest
+```
+
+Then, navigate to the directory where the DV tests reside :
+
+```bash
+cd $UPRJ_ROOT/verilog/dv/
+```
+
+Then, follow the instructions at [Both](#both) to run RTL/GL simulation.
+
+## Local
+
+You will need to export these environment variables:
+
+```bash
+export GCC_PATH=<gcc-installation-path>
+export PDK_PATH=<pdk-location/sky130A>
+```
+
+Then, follow the instruction at [Both](#both) to run RTL/GL simulation.
+
+## Both
+
+To run RTL simulation for one of the DV tests,
+
+```bash
+cd <dv-test>
+make
+```
+
+To run gate level simulation for one of the DV tests,
+
+```bash
+cd <dv-test>
+SIM=GL make
+```
+
+# User Analog Project Example DV
+
+> :construction: Under construction :construction:
diff --git a/verilog/dv/mprj_por/Makefile b/verilog/dv/mprj_por/Makefile
new file mode 100644
index 0000000..5d0825f
--- /dev/null
+++ b/verilog/dv/mprj_por/Makefile
@@ -0,0 +1,96 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+## PDK
+PDK_PATH = $(PDK_ROOT)/sky130A
+
+## Caravel Pointers
+CARAVEL_ROOT ?= ../../../caravel
+CARAVEL_PATH ?= $(CARAVEL_ROOT)
+CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
+CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog
+CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
+CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
+
+## User Project Pointers
+UPRJ_VERILOG_PATH ?= ../../../verilog
+UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
+UPRJ_BEHAVIOURAL_MODELS = ../
+
+## RISCV GCC
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+## Simulation mode: RTL/GL
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = mprj_por
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog $(SIM_DEFINES) -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \
+ $< -o $@
+else
+ iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s check-env
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
diff --git a/verilog/dv/mprj_por/mprj_por.c b/verilog/dv/mprj_por/mprj_por.c
new file mode 100644
index 0000000..9a51fc5
--- /dev/null
+++ b/verilog/dv/mprj_por/mprj_por.c
@@ -0,0 +1,49 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include "verilog/dv/caravel/defs.h"
+
+// --------------------------------------------------------
+
+void main()
+{
+ reg_spimaster_config = 0xa002; // Enable, prescaler = 2
+
+ reg_mprj_datal = 0x00000000;
+ reg_mprj_datah = 0x00000000;
+
+ // Configure mprj_io 10 and 25 as analog (digital in/out = off)
+ // Configure mprj_io 11, 12, 26, and 27 as digital output
+ // mprj_io 14 to 24 are analog pads and cannot be configured
+
+ reg_mprj_io_27 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_USER_STD_ANALOG;
+
+ reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_10 = GPIO_MODE_USER_STD_ANALOG;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ /* Block until end of test */
+ while (1);
+}
+
diff --git a/verilog/dv/mprj_por/mprj_por_tb.v b/verilog/dv/mprj_por/mprj_por_tb.v
new file mode 100644
index 0000000..39e4a36
--- /dev/null
+++ b/verilog/dv/mprj_por/mprj_por_tb.v
@@ -0,0 +1,170 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype wire
+
+`timescale 1 ns / 1 ps
+
+`include "uprj_analog_netlists.v"
+`include "caravan_netlists.v"
+`include "spiflash.v"
+`include "tbuart.v"
+
+module mprj_por_tb;
+ // Signals declaration
+ reg clock;
+ reg RSTB;
+ reg CSB;
+ reg power1, power2;
+ reg power3;
+
+ wire HIGH;
+ wire LOW;
+ wire TRI;
+ assign HIGH = 1'b1;
+ assign LOW = 1'b0;
+ assign TRI = 1'bz;
+
+ wire gpio;
+ wire uart_tx;
+ wire [37:0] mprj_io;
+ wire [3:0] checkbits;
+ wire [1:0] status;
+
+ // Signals Assignment
+ assign uart_tx = mprj_io[6];
+ assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+ // Power supply for POR
+ assign mprj_io[18] = power3;
+
+ // Readback from POR (digital HV through analog pad connection)
+ assign status = {mprj_io[25], mprj_io[10]};
+
+ // Readback from POR (digital LV)
+ assign checkbits = {mprj_io[27:26], mprj_io[12:11]};
+
+ always #12.5 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin
+ $dumpfile("mprj_por.vcd");
+ $dumpvars(0, mprj_por_tb);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (150) begin
+ repeat (1000) @(posedge clock);
+ end
+ $display("%c[1;31m",27);
+ $display ("Monitor: Timeout, Test Project IO Stimulus (RTL) Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ initial begin
+ wait(status == 2'h1);
+ $display("Monitor: mprj_por test started");
+ #100;
+ if (checkbits != 4'h9) begin
+ $display("Monitor: mprj_por test failed");
+ $finish;
+ end
+ wait(status == 2'h3);
+ #100;
+ if (checkbits != 4'h5) begin
+ $display("Monitor: mprj_por test failed");
+ $finish;
+ end
+ $display("Monitor: mprj_por test Passed");
+ #10000;
+ $finish;
+ end
+
+ // Reset Operation
+ initial begin
+ RSTB <= 1'b0;
+ CSB <= 1'b1; // Force CSB high
+ #2000;
+ RSTB <= 1'b1; // Release reset
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ power3 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ #150000; // Need time to run the managment SoC setup.
+ power3 <= 1'b1; // Power up the 2nd POR.
+ end
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+
+ wire VDD3V3 = power1;
+ wire VDD1V8 = power2;
+ wire VSS = 1'b0;
+
+ caravan uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+
+ spiflash #(
+ .FILENAME("mprj_por.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+ // Testbench UART
+ tbuart tbuart (
+ .ser_rx(uart_tx)
+ );
+
+endmodule
+`default_nettype wire
diff --git a/verilog/rtl/comparator.v b/verilog/rtl/comparator.v
new file mode 100644
index 0000000..9b74583
--- /dev/null
+++ b/verilog/rtl/comparator.v
@@ -0,0 +1,37 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+`timescale 1 ns / 1 ps
+
+// This is just a copy of simple_por.v from the Caravel project, used
+// as an analog user project example.
+
+module comparator(
+`ifdef USE_POWER_PINS
+ inout VDD,
+ inout GND,
+`endif
+ input Vn,
+ input Vp,
+ input CLK,
+
+ output Outn,
+ output Outp
+);
+
+
+endmodule
+`default_nettype wire
diff --git a/verilog/rtl/example_por.v b/verilog/rtl/example_por.v
new file mode 100644
index 0000000..9c74cdb
--- /dev/null
+++ b/verilog/rtl/example_por.v
@@ -0,0 +1,95 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+`timescale 1 ns / 1 ps
+
+// This is just a copy of simple_por.v from the Caravel project, used
+// as an analog user project example.
+
+module example_por(
+`ifdef USE_POWER_PINS
+
+ inout vccd1,
+ inout vssa1,
+`endif
+ output porb_h,
+ output porb_l,
+ output por_l
+);
+
+ wire mid, porb_h;
+ reg inode;
+
+ // This is a behavioral model! Actual circuit is a resitor dumping
+ // current (slowly) from vdd3v3 onto a capacitor, and this fed into
+ // two schmitt triggers for strong hysteresis/glitch tolerance.
+
+ initial begin
+ inode <= 1'b0;
+ end
+
+ // Emulate current source on capacitor as a 500ns delay either up or
+ // down. Note that this is sped way up for verilog simulation; the
+ // actual circuit is set to a 15ms delay.
+
+ always @(posedge vdd3v3) begin
+ #500 inode <= 1'b1;
+ end
+ always @(negedge vdd3v3) begin
+ #500 inode <= 1'b0;
+ end
+
+ // Instantiate two shmitt trigger buffers in series
+
+ sky130_fd_sc_hvl__schmittbuf_1 hystbuf1 (
+`ifdef USE_POWER_PINS
+ .VPWR(vdd3v3),
+ .VGND(vss),
+ .VPB(vdd3v3),
+ .VNB(vss),
+`endif
+ .A(inode),
+ .X(mid)
+ );
+
+ sky130_fd_sc_hvl__schmittbuf_1 hystbuf2 (
+`ifdef USE_POWER_PINS
+ .VPWR(vdd3v3),
+ .VGND(vss),
+ .VPB(vdd3v3),
+ .VNB(vss),
+`endif
+ .A(mid),
+ .X(porb_h)
+ );
+
+ sky130_fd_sc_hvl__lsbufhv2lv_1 porb_level (
+`ifdef USE_POWER_PINS
+ .VPWR(vdd3v3),
+ .VPB(vdd3v3),
+ .LVPWR(vdd1v8),
+ .VNB(vss),
+ .VGND(vss),
+`endif
+ .A(porb_h),
+ .X(porb_l)
+ );
+
+ // since this is behavioral anyway, but this should be
+ // replaced by a proper inverter
+ assign por_l = ~porb_l;
+endmodule
+`default_nettype wire
diff --git a/verilog/rtl/uprj_analog_netlists.v b/verilog/rtl/uprj_analog_netlists.v
new file mode 100644
index 0000000..062a873
--- /dev/null
+++ b/verilog/rtl/uprj_analog_netlists.v
@@ -0,0 +1,38 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+/*--------------------------------------------------------------*/
+/* caravel, a project harness for the Google/SkyWater sky130 */
+/* fabrication process and open source PDK */
+/* */
+/* Copyright 2020 efabless, Inc. */
+/* Written by Tim Edwards, December 2019 */
+/* and Mohamed Shalan, August 2020 */
+/* This file is open source hardware released under the */
+/* Apache 2.0 license. See file LICENSE. */
+/* */
+/*--------------------------------------------------------------*/
+
+`include "defines.v"
+`define USE_POWER_PINS
+
+`ifdef GL
+ `default_nettype wire
+ // Use behavorial model with gate-level simulation
+ `include "rtl/user_analog_project_wrapper.v"
+ `include "rtl/user_analog_proj_example.v"
+`else
+ `include "user_analog_project_wrapper.v"
+ `include "user_analog_proj_example.v"
+`endif
diff --git a/verilog/rtl/user_analog_proj_example.v b/verilog/rtl/user_analog_proj_example.v
new file mode 100644
index 0000000..40f6aa5
--- /dev/null
+++ b/verilog/rtl/user_analog_proj_example.v
@@ -0,0 +1,190 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`include "comparator.v"
+
+
+/*
+ * I/O mapping for analog
+ *
+ * mprj_io[37] io_in/out/oeb/in_3v3[26] --- ---
+ * mprj_io[36] io_in/out/oeb/in_3v3[25] --- ---
+ * mprj_io[35] io_in/out/oeb/in_3v3[24] gpio_analog/noesd[17] ---
+ * mprj_io[34] io_in/out/oeb/in_3v3[23] gpio_analog/noesd[16] ---
+ * mprj_io[33] io_in/out/oeb/in_3v3[22] gpio_analog/noesd[15] ---
+ * mprj_io[32] io_in/out/oeb/in_3v3[21] gpio_analog/noesd[14] ---
+ * mprj_io[31] io_in/out/oeb/in_3v3[20] gpio_analog/noesd[13] ---
+ * mprj_io[30] io_in/out/oeb/in_3v3[19] gpio_analog/noesd[12] ---
+ * mprj_io[29] io_in/out/oeb/in_3v3[18] gpio_analog/noesd[11] ---
+ * mprj_io[28] io_in/out/oeb/in_3v3[17] gpio_analog/noesd[10] ---
+ * mprj_io[27] io_in/out/oeb/in_3v3[16] gpio_analog/noesd[9] ---
+ * mprj_io[26] io_in/out/oeb/in_3v3[15] gpio_analog/noesd[8] ---
+ * mprj_io[25] io_in/out/oeb/in_3v3[14] gpio_analog/noesd[7] ---
+ * mprj_io[24] --- --- user_analog[10]
+ * mprj_io[23] --- --- user_analog[9]
+ * mprj_io[22] --- --- user_analog[8]
+ * mprj_io[21] --- --- user_analog[7]
+ * mprj_io[20] --- --- user_analog[6] clamp[2]
+ * mprj_io[19] --- --- user_analog[5] clamp[1]
+ * mprj_io[18] --- --- user_analog[4] clamp[0]
+ * mprj_io[17] --- --- user_analog[3]
+ * mprj_io[16] --- --- user_analog[2]
+ * mprj_io[15] --- --- user_analog[1]
+ * mprj_io[14] --- --- user_analog[0]
+ * mprj_io[13] io_in/out/oeb/in_3v3[13] gpio_analog/noesd[6] ---
+ * mprj_io[12] io_in/out/oeb/in_3v3[12] gpio_analog/noesd[5] ---
+ * mprj_io[11] io_in/out/oeb/in_3v3[11] gpio_analog/noesd[4] ---
+ * mprj_io[10] io_in/out/oeb/in_3v3[10] gpio_analog/noesd[3] ---
+ * mprj_io[9] io_in/out/oeb/in_3v3[9] gpio_analog/noesd[2] ---
+ * mprj_io[8] io_in/out/oeb/in_3v3[8] gpio_analog/noesd[1] ---
+ * mprj_io[7] io_in/out/oeb/in_3v3[7] gpio_analog/noesd[0] ---
+ * mprj_io[6] io_in/out/oeb/in_3v3[6] --- ---
+ * mprj_io[5] io_in/out/oeb/in_3v3[5] --- ---
+ * mprj_io[4] io_in/out/oeb/in_3v3[4] --- ---
+ * mprj_io[3] io_in/out/oeb/in_3v3[3] --- ---
+ * mprj_io[2] io_in/out/oeb/in_3v3[2] --- ---
+ * mprj_io[1] io_in/out/oeb/in_3v3[1] --- ---
+ * mprj_io[0] io_in/out/oeb/in_3v3[0] --- ---
+ *
+ */
+
+/*
+ *----------------------------------------------------------------
+ *
+ * user_analog_proj_example
+ *
+ * This is an example of a (trivially simple) analog user project,
+ * showing how the user project can connect to the I/O pads, both
+ * the digital pads, the analog connection on the digital pads,
+ * and the dedicated analog pins used as an additional power supply
+ * input, with a connected ESD clamp.
+ *
+ * See the testbench in directory "mprj_por" for the example
+ * program that drives this user project.
+ *
+ *----------------------------------------------------------------
+ */
+
+module user_analog_proj_example (
+`ifdef USE_POWER_PINS
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8v supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+`endif
+
+ // Wishbone Slave ports (WB MI A)
+ input wb_clk_i,
+ input wb_rst_i,
+ input wbs_stb_i,
+ input wbs_cyc_i,
+ input wbs_we_i,
+ input [3:0] wbs_sel_i,
+ input [31:0] wbs_dat_i,
+ input [31:0] wbs_adr_i,
+ output wbs_ack_o,
+ output [31:0] wbs_dat_o,
+
+ // Logic Analyzer Signals
+ input [127:0] la_data_in,
+ output [127:0] la_data_out,
+ input [127:0] la_oenb,
+
+ // IOs
+ input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in,
+ input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3,
+ output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out,
+ output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb,
+
+ // GPIO-analog
+ inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog,
+ inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd,
+
+ // Dedicated analog
+ inout [`ANALOG_PADS-1:0] io_analog,
+ inout [2:0] io_clamp_high,
+ inout [2:0] io_clamp_low,
+
+ // Clock
+ input user_clock2,
+
+ // IRQ
+ output [2:0] irq
+);
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb;
+ wire [`ANALOG_PADS-1:0] io_analog;
+
+ // wire [31:0] rdata;
+ // wire [31:0] wdata;
+
+ // wire valid;
+ // wire [3:0] wstrb;
+ `ifdef USE_POWER_PINS
+
+ assign io_clamp_high[2:1] = vccd1;
+ assign io_clamp_low[2:1] = vssa1;
+ `endif
+ wire analog0, analog2, analog3, ;
+
+ // WB MI A
+ // assign valid = wbs_cyc_i && wbs_stb_i;
+ // assign wstrb = wbs_sel_i & {4{wbs_we_i}};
+ // assign wbs_dat_o = rdata;
+ // assign wdata = wbs_dat_i;
+
+ // IO --- unused (no need to connect to anything)
+ // assign io_out[`MPRJ_IO_PADS-`ANALOG_PADS-1:17] = 0;
+ // assign io_out[14:13] = 11'b0;
+ // assign io_out[10:0] = 11'b0;
+
+ // assign io_oeb[`MPRJ_IO_PADS-`ANALOG_PADS-1:17] = -1;
+ // assign io_oeb[14:13] = 11'b1;
+ // assign io_oeb[10:0] = 11'b1;
+
+ // IO --- enable outputs on 11, 12, 15, and 16
+ assign io_analog[2] = analog2;
+ assign io_analog[3] = analog3;
+ assign io_analog[5] = analog5;
+ assign io_analog[6] = analog6;
+ assign io_analog[1] = analog1;
+ assign io_analog[8] = analog8;
+
+
+ comparator comp1 (
+ `ifdef USE_POWER_PINS
+ .VDD(vccd1),
+ .GND(vssa1),
+ `endif
+ .Vp(analog5), // 3.3V domain output
+ .Vn(analog6), // 1.8V domain output
+ .CLK(analog8),
+
+ .Outn(analog3),
+ .Outp(analog2) // 1.8V domain output
+ );
+
+
+endmodule
+
+`default_nettype wire
diff --git a/verilog/rtl/user_analog_project_wrapper.v b/verilog/rtl/user_analog_project_wrapper.v
new file mode 100644
index 0000000..7ee4c33
--- /dev/null
+++ b/verilog/rtl/user_analog_project_wrapper.v
@@ -0,0 +1,182 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+/*
+ *-------------------------------------------------------------
+ *
+ * user_analog_project_wrapper
+ *
+ * This wrapper enumerates all of the pins available to the
+ * user for the user analog project.
+ *
+ *-------------------------------------------------------------
+ */
+
+module user_analog_project_wrapper (
+`ifdef USE_POWER_PINS
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8v supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+`endif
+
+ // Wishbone Slave ports (WB MI A)
+ input wb_clk_i,
+ input wb_rst_i,
+ input wbs_stb_i,
+ input wbs_cyc_i,
+ input wbs_we_i,
+ input [3:0] wbs_sel_i,
+ input [31:0] wbs_dat_i,
+ input [31:0] wbs_adr_i,
+ output wbs_ack_o,
+ output [31:0] wbs_dat_o,
+
+ // Logic Analyzer Signals
+ input [127:0] la_data_in,
+ output [127:0] la_data_out,
+ input [127:0] la_oenb,
+
+ /* GPIOs. There are 27 GPIOs, on either side of the analog.
+ * These have the following mapping to the GPIO padframe pins
+ * and memory-mapped registers, since the numbering remains the
+ * same as caravel but skips over the analog I/O:
+ *
+ * io_in/out/oeb/in_3v3 [26:14] <---> mprj_io[37:25]
+ * io_in/out/oeb/in_3v3 [13:0] <---> mprj_io[13:0]
+ *
+ * When the GPIOs are configured by the Management SoC for
+ * user use, they have three basic bidirectional controls:
+ * in, out, and oeb (output enable, sense inverted). For
+ * analog projects, a 3.3V copy of the signal input is
+ * available. out and oeb must be 1.8V signals.
+ */
+
+ input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in,
+ input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3,
+ output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out,
+ output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb,
+
+ /* Analog (direct connection to GPIO pad---not for high voltage or
+ * high frequency use). The management SoC must turn off both
+ * input and output buffers on these GPIOs to allow analog access.
+ * These signals may drive a voltage up to the value of VDDIO
+ * (3.3V typical, 5.5V maximum).
+ *
+ * Note that analog I/O is not available on the 7 lowest-numbered
+ * GPIO pads, and so the analog_io indexing is offset from the
+ * GPIO indexing by 7, as follows:
+ *
+ * gpio_analog/noesd [17:7] <---> mprj_io[35:25]
+ * gpio_analog/noesd [6:0] <---> mprj_io[13:7]
+ *
+ */
+
+ inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog,
+ inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd,
+
+ /* Analog signals, direct through to pad. These have no ESD at all,
+ * so ESD protection is the responsibility of the designer.
+ *
+ * user_analog[10:0] <---> mprj_io[24:14]
+ *
+ */
+ inout [`ANALOG_PADS-1:0] io_analog,
+
+ /* Additional power supply ESD clamps, one per analog pad. The
+ * high side should be connected to a 3.3-5.5V power supply.
+ * The low side should be connected to ground.
+ *
+ * clamp_high[2:0] <---> mprj_io[20:18]
+ * clamp_low[2:0] <---> mprj_io[20:18]
+ *
+ */
+ inout [2:0] io_clamp_high,
+ inout [2:0] io_clamp_low,
+
+ // Independent clock (on independent integer divider)
+ input user_clock2,
+
+ // User maskable interrupt signals
+ output [2:0] user_irq
+);
+
+/*--------------------------------------*/
+/* User project is instantiated here */
+/*--------------------------------------*/
+
+user_analog_proj_example mprj (
+ `ifdef USE_POWER_PINS
+ .vdda1(vdda1), // User area 1 3.3V power
+ .vdda2(vdda2), // User area 2 3.3V power
+ .vssa1(vssa1), // User area 1 analog ground
+ .vssa2(vssa2), // User area 2 analog ground
+ .vccd1(vccd1), // User area 1 1.8V power
+ .vccd2(vccd2), // User area 2 1.8V power
+ .vssd1(vssd1), // User area 1 digital ground
+ .vssd2(vssd2), // User area 2 digital ground
+ `endif
+
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+
+ // MGMT SoC Wishbone Slave
+
+ .wbs_cyc_i(wbs_cyc_i),
+ .wbs_stb_i(wbs_stb_i),
+ .wbs_we_i(wbs_we_i),
+ .wbs_sel_i(wbs_sel_i),
+ .wbs_adr_i(wbs_adr_i),
+ .wbs_dat_i(wbs_dat_i),
+ .wbs_ack_o(wbs_ack_o),
+ .wbs_dat_o(wbs_dat_o),
+
+ // Logic Analyzer
+
+ .la_data_in(la_data_in),
+ .la_data_out(la_data_out),
+ .la_oenb (la_oenb),
+
+ // IO Pads
+ .io_in (io_in),
+ .io_in_3v3 (io_in_3v3),
+ .io_out(io_out),
+ .io_oeb(io_oeb),
+
+ // GPIO-analog
+ .gpio_analog(gpio_analog),
+ .gpio_noesd(gpio_noesd),
+
+ // Dedicated analog
+ .io_analog(io_analog),
+ .io_clamp_high(vccd1),
+ .io_clamp_low(vssa1),
+
+ // Clock
+ .user_clock2(user_clock2),
+
+ // IRQ
+ .irq(user_irq)
+);
+
+endmodule // user_analog_project_wrapper
+
+`default_nettype wire
diff --git a/xschem/.spiceinit b/xschem/.spiceinit
new file mode 100644
index 0000000..e6a73aa
--- /dev/null
+++ b/xschem/.spiceinit
@@ -0,0 +1,5 @@
+* ngspice initialization for sky130
+* assert BSIM compatibility mode with "nf" vs. "W"
+set ngbehavior=hsa
+* "nomodcheck" speeds up loading time
+set ng_nomodcheck
diff --git a/xschem/analog_wrapper_tb.sch b/xschem/analog_wrapper_tb.sch
new file mode 100644
index 0000000..176c9c2
--- /dev/null
+++ b/xschem/analog_wrapper_tb.sch
@@ -0,0 +1,151 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 800 -820 800 -800 {
+lab=GND}
+N 800 -910 800 -880 {
+lab=VDD}
+N 1010 -710 1010 -690 {
+lab=io_analog[5]}
+N 1010 -790 1010 -770 {
+lab=io_analog[6]}
+N 1010 -690 1100 -690 {
+lab=io_analog[5]}
+N 1100 -690 1100 -670 {
+lab=io_analog[5]}
+N 1100 -610 1100 -590 {
+lab=GND}
+N 1100 -690 1170 -690 {
+lab=io_analog[5]}
+N 1170 -790 1170 -690 {
+lab=io_analog[5]}
+N 910 -1020 910 -990 {
+lab=io_analog[8]}
+N 910 -930 910 -900 {
+lab=GND}
+N 1330 -710 1330 -670 {
+lab=GND}
+N 1330 -810 1330 -770 {
+lab=GND}
+N 1490 -1210 1540 -1210 {
+lab=#net1}
+N 1490 -1190 1540 -1190 {
+lab=#net2}
+N 1490 -1170 1540 -1170 {
+lab=GND}
+N 1490 -1150 1540 -1150 {
+lab=#net3}
+N 1490 -1130 1540 -1130 {
+lab=VDD}
+N 1490 -1110 1540 -1110 {
+lab=#net4}
+N 1490 -1090 1540 -1090 {
+lab=#net5}
+N 1490 -1070 1540 -1070 {
+lab=#net6}
+N 1490 -1050 1540 -1050 {
+lab=#net7}
+N 1490 -1030 1540 -1030 {
+lab=#net8}
+N 1490 -1010 1540 -1010 {
+lab=#net9}
+N 1490 -990 1540 -990 {
+lab=#net10}
+N 1490 -970 1540 -970 {
+lab=#net11}
+N 1490 -950 1540 -950 {
+lab=#net12}
+N 1490 -930 1540 -930 {
+lab=#net13}
+N 1490 -910 1540 -910 {
+lab=io_analog[3]}
+N 1490 -890 1540 -890 {
+lab=#net14}
+N 1490 -870 1540 -870 {
+lab=#net15}
+N 1490 -850 1540 -850 {
+lab=#net16}
+N 1840 -1210 1890 -1210 {
+lab=#net17}
+N 1840 -1190 1890 -1190 {
+lab=#net18}
+N 1840 -1170 1890 -1170 {
+lab=#net19}
+N 1840 -1150 1890 -1150 {
+lab=#net20}
+N 1840 -1130 1890 -1130 {
+lab=#net21}
+N 1840 -1110 1890 -1110 {
+lab=#net22}
+N 1840 -1090 1890 -1090 {
+lab=#net23}
+N 1840 -1070 1890 -1070 {
+lab=#net24}
+N 1840 -1050 1890 -1050 {
+lab=#net25}
+N 1840 -1030 1890 -1030 {
+lab=#net26}
+N 1840 -1010 1890 -1010 {
+lab=#net27}
+N 1840 -990 1890 -990 {
+lab=#net28}
+N 1840 -970 1890 -970 {
+lab=#net29}
+N 2030 -990 2030 -950 {
+lab=GND}
+N 2130 -990 2130 -940 {
+lab=GND}
+N 2030 -1120 2030 -1050 {
+lab=io_analog[3]}
+N 2130 -1120 2130 -1050 {
+lab=io_analog[2]}
+C {devices/TT_models.sym} 950 -1180 0 0 {name=TT_MODELS
+only_toplevel=true
+format="tcleval( @value )"
+value="
+** opencircuitdesign pdks install
+.lib /usr/local/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
+
+"
+spice_ignore=falsename=s1 only_toplevel=false value=blabla}
+C {devices/vsource.sym} 800 -850 0 0 {name=Vdd value=1.8}
+C {devices/vsource.sym} 1010 -740 0 0 {name=Vn value="pulse(-10m 10m 1ps 1ps 1ps 4ns 8ns)"}
+C {devices/lab_pin.sym} 1010 -790 0 0 {name=l24 sig_type=std_logic lab=io_analog[6]}
+C {devices/vsource.sym} 1100 -640 0 0 {name=Vcm value=1.2}
+C {devices/lab_pin.sym} 1170 -790 2 0 {name=l25 sig_type=std_logic lab=io_analog[5]}
+C {devices/code_shown.sym} 2030 -770 0 0 {name=SPICE only_toplevel=false value=".tran 0.01n 50n
+.save all"}
+C {devices/vsource.sym} 910 -960 0 0 {name=V1 value="pulse(1.8 0 1ps 1ps 1ps 2ns 4ns)"}
+C {devices/lab_pin.sym} 910 -1020 0 0 {name=l22 sig_type=std_logic lab=io_analog[8]}
+C {devices/gnd.sym} 1330 -670 0 0 {name=l3 lab=GND}
+C {devices/lab_pin.sym} 1330 -810 2 0 {name=l4 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 1100 -590 2 0 {name=l5 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 800 -800 2 0 {name=l7 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 910 -900 2 0 {name=l8 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 800 -910 0 0 {name=l9 sig_type=std_logic lab=VDD}
+C {devices/res.sym} 1330 -740 0 0 {name=R1
+value=0
+footprint=1206
+device=resistor
+m=1}
+C {user_analog_project_wrapper.sym} 1690 -1030 0 1 {name=x1}
+C {devices/lab_pin.sym} 1490 -1130 0 0 {name=l1 sig_type=std_logic lab=VDD}
+C {devices/lab_pin.sym} 1490 -1170 0 0 {name=l2 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 2030 -1120 1 0 {name=l12 sig_type=std_logic lab=io_analog[3]}
+C {devices/lab_pin.sym} 2130 -1120 1 0 {name=l13 sig_type=std_logic lab=io_analog[2]}
+C {devices/capa.sym} 2030 -1020 0 0 {name=C1
+m=1
+value=0.1p
+footprint=1206
+device="ceramic capacitor"}
+C {devices/capa.sym} 2130 -1020 0 0 {name=C2
+m=1
+value=0.1p
+footprint=1206
+device="ceramic capacitor"}
+C {devices/lab_pin.sym} 2030 -950 0 0 {name=l10 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 2130 -940 0 0 {name=l11 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 1490 -910 0 0 {name=l14 sig_type=std_logic lab=io_analog[10:0]}
diff --git a/xschem/analog_wrapper_tb.spice b/xschem/analog_wrapper_tb.spice
new file mode 100644
index 0000000..2ded234
--- /dev/null
+++ b/xschem/analog_wrapper_tb.spice
@@ -0,0 +1,398 @@
+** sch_path: /home/krishna/Strong_Arm_MPW6/xschem/analog_wrapper_tb.sch
+**.subckt analog_wrapper_tb
+Vdd VDD GND 1.8
+Vn io_analog[6] io_analog[5] pulse(-10m 10m 1ps 1ps 1ps 4ns 8ns)
+Vcm io_analog[5] GND 1.2
+V1 io_analog[8] GND pulse(1.8 0 1ps 1ps 1ps 2ns 4ns)
+R1 GND GND 0 m=1
+x1 net1 net2 GND net3 VDD net4 net5 net6 net17 net18 net19 net20 net21 net22[3] net22[2] net22[1]
++ net22[0] net23[31] net23[30] net23[29] net23[28] net23[27] net23[26] net23[25] net23[24] net23[23] net23[22]
++ net23[21] net23[20] net23[19] net23[18] net23[17] net23[16] net23[15] net23[14] net23[13] net23[12] net23[11]
++ net23[10] net23[9] net23[8] net23[7] net23[6] net23[5] net23[4] net23[3] net23[2] net23[1] net23[0] net24[31]
++ net24[30] net24[29] net24[28] net24[27] net24[26] net24[25] net24[24] net24[23] net24[22] net24[21] net24[20]
++ net24[19] net24[18] net24[17] net24[16] net24[15] net24[14] net24[13] net24[12] net24[11] net24[10] net24[9]
++ net24[8] net24[7] net24[6] net24[5] net24[4] net24[3] net24[2] net24[1] net24[0] net7 net8[31] net8[30]
++ net8[29] net8[28] net8[27] net8[26] net8[25] net8[24] net8[23] net8[22] net8[21] net8[20] net8[19] net8[18]
++ net8[17] net8[16] net8[15] net8[14] net8[13] net8[12] net8[11] net8[10] net8[9] net8[8] net8[7] net8[6]
++ net8[5] net8[4] net8[3] net8[2] net8[1] net8[0] net25[127] net25[126] net25[125] net25[124] net25[123]
++ net25[122] net25[121] net25[120] net25[119] net25[118] net25[117] net25[116] net25[115] net25[114] net25[113]
++ net25[112] net25[111] net25[110] net25[109] net25[108] net25[107] net25[106] net25[105] net25[104] net25[103]
++ net25[102] net25[101] net25[100] net25[99] net25[98] net25[97] net25[96] net25[95] net25[94] net25[93]
++ net25[92] net25[91] net25[90] net25[89] net25[88] net25[87] net25[86] net25[85] net25[84] net25[83] net25[82]
++ net25[81] net25[80] net25[79] net25[78] net25[77] net25[76] net25[75] net25[74] net25[73] net25[72] net25[71]
++ net25[70] net25[69] net25[68] net25[67] net25[66] net25[65] net25[64] net25[63] net25[62] net25[61] net25[60]
++ net25[59] net25[58] net25[57] net25[56] net25[55] net25[54] net25[53] net25[52] net25[51] net25[50] net25[49]
++ net25[48] net25[47] net25[46] net25[45] net25[44] net25[43] net25[42] net25[41] net25[40] net25[39] net25[38]
++ net25[37] net25[36] net25[35] net25[34] net25[33] net25[32] net25[31] net25[30] net25[29] net25[28] net25[27]
++ net25[26] net25[25] net25[24] net25[23] net25[22] net25[21] net25[20] net25[19] net25[18] net25[17] net25[16]
++ net25[15] net25[14] net25[13] net25[12] net25[11] net25[10] net25[9] net25[8] net25[7] net25[6] net25[5]
++ net25[4] net25[3] net25[2] net25[1] net25[0] net9[127] net9[126] net9[125] net9[124] net9[123] net9[122]
++ net9[121] net9[120] net9[119] net9[118] net9[117] net9[116] net9[115] net9[114] net9[113] net9[112] net9[111]
++ net9[110] net9[109] net9[108] net9[107] net9[106] net9[105] net9[104] net9[103] net9[102] net9[101] net9[100]
++ net9[99] net9[98] net9[97] net9[96] net9[95] net9[94] net9[93] net9[92] net9[91] net9[90] net9[89] net9[88]
++ net9[87] net9[86] net9[85] net9[84] net9[83] net9[82] net9[81] net9[80] net9[79] net9[78] net9[77] net9[76]
++ net9[75] net9[74] net9[73] net9[72] net9[71] net9[70] net9[69] net9[68] net9[67] net9[66] net9[65] net9[64]
++ net9[63] net9[62] net9[61] net9[60] net9[59] net9[58] net9[57] net9[56] net9[55] net9[54] net9[53] net9[52]
++ net9[51] net9[50] net9[49] net9[48] net9[47] net9[46] net9[45] net9[44] net9[43] net9[42] net9[41] net9[40]
++ net9[39] net9[38] net9[37] net9[36] net9[35] net9[34] net9[33] net9[32] net9[31] net9[30] net9[29] net9[28]
++ net9[27] net9[26] net9[25] net9[24] net9[23] net9[22] net9[21] net9[20] net9[19] net9[18] net9[17] net9[16]
++ net9[15] net9[14] net9[13] net9[12] net9[11] net9[10] net9[9] net9[8] net9[7] net9[6] net9[5] net9[4]
++ net9[3] net9[2] net9[1] net9[0] net26[127] net26[126] net26[125] net26[124] net26[123] net26[122]
++ net26[121] net26[120] net26[119] net26[118] net26[117] net26[116] net26[115] net26[114] net26[113] net26[112]
++ net26[111] net26[110] net26[109] net26[108] net26[107] net26[106] net26[105] net26[104] net26[103] net26[102]
++ net26[101] net26[100] net26[99] net26[98] net26[97] net26[96] net26[95] net26[94] net26[93] net26[92]
++ net26[91] net26[90] net26[89] net26[88] net26[87] net26[86] net26[85] net26[84] net26[83] net26[82] net26[81]
++ net26[80] net26[79] net26[78] net26[77] net26[76] net26[75] net26[74] net26[73] net26[72] net26[71] net26[70]
++ net26[69] net26[68] net26[67] net26[66] net26[65] net26[64] net26[63] net26[62] net26[61] net26[60] net26[59]
++ net26[58] net26[57] net26[56] net26[55] net26[54] net26[53] net26[52] net26[51] net26[50] net26[49] net26[48]
++ net26[47] net26[46] net26[45] net26[44] net26[43] net26[42] net26[41] net26[40] net26[39] net26[38] net26[37]
++ net26[36] net26[35] net26[34] net26[33] net26[32] net26[31] net26[30] net26[29] net26[28] net26[27] net26[26]
++ net26[25] net26[24] net26[23] net26[22] net26[21] net26[20] net26[19] net26[18] net26[17] net26[16] net26[15]
++ net26[14] net26[13] net26[12] net26[11] net26[10] net26[9] net26[8] net26[7] net26[6] net26[5] net26[4]
++ net26[3] net26[2] net26[1] net26[0] net27[26] net27[25] net27[24] net27[23] net27[22] net27[21] net27[20]
++ net27[19] net27[18] net27[17] net27[16] net27[15] net27[14] net27[13] net27[12] net27[11] net27[10] net27[9]
++ net27[8] net27[7] net27[6] net27[5] net27[4] net27[3] net27[2] net27[1] net27[0] net28[26] net28[25]
++ net28[24] net28[23] net28[22] net28[21] net28[20] net28[19] net28[18] net28[17] net28[16] net28[15] net28[14]
++ net28[13] net28[12] net28[11] net28[10] net28[9] net28[8] net28[7] net28[6] net28[5] net28[4] net28[3]
++ net28[2] net28[1] net28[0] net10[26] net10[25] net10[24] net10[23] net10[22] net10[21] net10[20] net10[19]
++ net10[18] net10[17] net10[16] net10[15] net10[14] net10[13] net10[12] net10[11] net10[10] net10[9] net10[8]
++ net10[7] net10[6] net10[5] net10[4] net10[3] net10[2] net10[1] net10[0] net11[26] net11[25] net11[24]
++ net11[23] net11[22] net11[21] net11[20] net11[19] net11[18] net11[17] net11[16] net11[15] net11[14] net11[13]
++ net11[12] net11[11] net11[10] net11[9] net11[8] net11[7] net11[6] net11[5] net11[4] net11[3] net11[2]
++ net11[1] net11[0] net12[17] net12[16] net12[15] net12[14] net12[13] net12[12] net12[11] net12[10] net12[9]
++ net12[8] net12[7] net12[6] net12[5] net12[4] net12[3] net12[2] net12[1] net12[0] net13[17] net13[16]
++ net13[15] net13[14] net13[13] net13[12] net13[11] net13[10] net13[9] net13[8] net13[7] net13[6] net13[5]
++ net13[4] net13[3] net13[2] net13[1] net13[0] io_analog[10] io_analog[9] io_analog[8] io_analog[7]
++ io_analog[6] io_analog[5] io_analog[4] io_analog[3] io_analog[2] io_analog[1] io_analog[0] net14[2] net14[1]
++ net14[0] net15[2] net15[1] net15[0] net29 net16[2] net16[1] net16[0] user_analog_project_wrapper
+C1 io_analog[3] GND 0.1p m=1
+C2 io_analog[2] GND 0.1p m=1
+**** begin user architecture code
+
+** opencircuitdesign pdks install
+.lib /usr/local/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
+
+
+
+.tran 0.01n 50n
+.save all
+
+**** end user architecture code
+**.ends
+
+* expanding symbol: user_analog_project_wrapper.sym # of pins=32
+** sym_path: /home/krishna/Strong_Arm_MPW6/xschem/user_analog_project_wrapper.sym
+** sch_path: /home/krishna/Strong_Arm_MPW6/xschem/user_analog_project_wrapper.sch
+.subckt user_analog_project_wrapper vdda1 vdda2 vssa1 vssa2 vccd1 vccd2 vssd1 vssd2 wb_clk_i
++ wb_rst_i wbs_stb_i wbs_cyc_i wbs_we_i wbs_sel_i[3] wbs_sel_i[2] wbs_sel_i[1] wbs_sel_i[0] wbs_dat_i[31]
++ wbs_dat_i[30] wbs_dat_i[29] wbs_dat_i[28] wbs_dat_i[27] wbs_dat_i[26] wbs_dat_i[25] wbs_dat_i[24] wbs_dat_i[23]
++ wbs_dat_i[22] wbs_dat_i[21] wbs_dat_i[20] wbs_dat_i[19] wbs_dat_i[18] wbs_dat_i[17] wbs_dat_i[16] wbs_dat_i[15]
++ wbs_dat_i[14] wbs_dat_i[13] wbs_dat_i[12] wbs_dat_i[11] wbs_dat_i[10] wbs_dat_i[9] wbs_dat_i[8] wbs_dat_i[7]
++ wbs_dat_i[6] wbs_dat_i[5] wbs_dat_i[4] wbs_dat_i[3] wbs_dat_i[2] wbs_dat_i[1] wbs_dat_i[0] wbs_adr_i[31]
++ wbs_adr_i[30] wbs_adr_i[29] wbs_adr_i[28] wbs_adr_i[27] wbs_adr_i[26] wbs_adr_i[25] wbs_adr_i[24] wbs_adr_i[23]
++ wbs_adr_i[22] wbs_adr_i[21] wbs_adr_i[20] wbs_adr_i[19] wbs_adr_i[18] wbs_adr_i[17] wbs_adr_i[16] wbs_adr_i[15]
++ wbs_adr_i[14] wbs_adr_i[13] wbs_adr_i[12] wbs_adr_i[11] wbs_adr_i[10] wbs_adr_i[9] wbs_adr_i[8] wbs_adr_i[7]
++ wbs_adr_i[6] wbs_adr_i[5] wbs_adr_i[4] wbs_adr_i[3] wbs_adr_i[2] wbs_adr_i[1] wbs_adr_i[0] wbs_ack_o
++ wbs_dat_o[31] wbs_dat_o[30] wbs_dat_o[29] wbs_dat_o[28] wbs_dat_o[27] wbs_dat_o[26] wbs_dat_o[25] wbs_dat_o[24]
++ wbs_dat_o[23] wbs_dat_o[22] wbs_dat_o[21] wbs_dat_o[20] wbs_dat_o[19] wbs_dat_o[18] wbs_dat_o[17] wbs_dat_o[16]
++ wbs_dat_o[15] wbs_dat_o[14] wbs_dat_o[13] wbs_dat_o[12] wbs_dat_o[11] wbs_dat_o[10] wbs_dat_o[9] wbs_dat_o[8]
++ wbs_dat_o[7] wbs_dat_o[6] wbs_dat_o[5] wbs_dat_o[4] wbs_dat_o[3] wbs_dat_o[2] wbs_dat_o[1] wbs_dat_o[0]
++ la_data_in[127] la_data_in[126] la_data_in[125] la_data_in[124] la_data_in[123] la_data_in[122] la_data_in[121]
++ la_data_in[120] la_data_in[119] la_data_in[118] la_data_in[117] la_data_in[116] la_data_in[115] la_data_in[114]
++ la_data_in[113] la_data_in[112] la_data_in[111] la_data_in[110] la_data_in[109] la_data_in[108] la_data_in[107]
++ la_data_in[106] la_data_in[105] la_data_in[104] la_data_in[103] la_data_in[102] la_data_in[101] la_data_in[100]
++ la_data_in[99] la_data_in[98] la_data_in[97] la_data_in[96] la_data_in[95] la_data_in[94] la_data_in[93]
++ la_data_in[92] la_data_in[91] la_data_in[90] la_data_in[89] la_data_in[88] la_data_in[87] la_data_in[86]
++ la_data_in[85] la_data_in[84] la_data_in[83] la_data_in[82] la_data_in[81] la_data_in[80] la_data_in[79]
++ la_data_in[78] la_data_in[77] la_data_in[76] la_data_in[75] la_data_in[74] la_data_in[73] la_data_in[72]
++ la_data_in[71] la_data_in[70] la_data_in[69] la_data_in[68] la_data_in[67] la_data_in[66] la_data_in[65]
++ la_data_in[64] la_data_in[63] la_data_in[62] la_data_in[61] la_data_in[60] la_data_in[59] la_data_in[58]
++ la_data_in[57] la_data_in[56] la_data_in[55] la_data_in[54] la_data_in[53] la_data_in[52] la_data_in[51]
++ la_data_in[50] la_data_in[49] la_data_in[48] la_data_in[47] la_data_in[46] la_data_in[45] la_data_in[44]
++ la_data_in[43] la_data_in[42] la_data_in[41] la_data_in[40] la_data_in[39] la_data_in[38] la_data_in[37]
++ la_data_in[36] la_data_in[35] la_data_in[34] la_data_in[33] la_data_in[32] la_data_in[31] la_data_in[30]
++ la_data_in[29] la_data_in[28] la_data_in[27] la_data_in[26] la_data_in[25] la_data_in[24] la_data_in[23]
++ la_data_in[22] la_data_in[21] la_data_in[20] la_data_in[19] la_data_in[18] la_data_in[17] la_data_in[16]
++ la_data_in[15] la_data_in[14] la_data_in[13] la_data_in[12] la_data_in[11] la_data_in[10] la_data_in[9]
++ la_data_in[8] la_data_in[7] la_data_in[6] la_data_in[5] la_data_in[4] la_data_in[3] la_data_in[2] la_data_in[1]
++ la_data_in[0] la_data_out[127] la_data_out[126] la_data_out[125] la_data_out[124] la_data_out[123]
++ la_data_out[122] la_data_out[121] la_data_out[120] la_data_out[119] la_data_out[118] la_data_out[117]
++ la_data_out[116] la_data_out[115] la_data_out[114] la_data_out[113] la_data_out[112] la_data_out[111]
++ la_data_out[110] la_data_out[109] la_data_out[108] la_data_out[107] la_data_out[106] la_data_out[105]
++ la_data_out[104] la_data_out[103] la_data_out[102] la_data_out[101] la_data_out[100] la_data_out[99] la_data_out[98]
++ la_data_out[97] la_data_out[96] la_data_out[95] la_data_out[94] la_data_out[93] la_data_out[92] la_data_out[91]
++ la_data_out[90] la_data_out[89] la_data_out[88] la_data_out[87] la_data_out[86] la_data_out[85] la_data_out[84]
++ la_data_out[83] la_data_out[82] la_data_out[81] la_data_out[80] la_data_out[79] la_data_out[78] la_data_out[77]
++ la_data_out[76] la_data_out[75] la_data_out[74] la_data_out[73] la_data_out[72] la_data_out[71] la_data_out[70]
++ la_data_out[69] la_data_out[68] la_data_out[67] la_data_out[66] la_data_out[65] la_data_out[64] la_data_out[63]
++ la_data_out[62] la_data_out[61] la_data_out[60] la_data_out[59] la_data_out[58] la_data_out[57] la_data_out[56]
++ la_data_out[55] la_data_out[54] la_data_out[53] la_data_out[52] la_data_out[51] la_data_out[50] la_data_out[49]
++ la_data_out[48] la_data_out[47] la_data_out[46] la_data_out[45] la_data_out[44] la_data_out[43] la_data_out[42]
++ la_data_out[41] la_data_out[40] la_data_out[39] la_data_out[38] la_data_out[37] la_data_out[36] la_data_out[35]
++ la_data_out[34] la_data_out[33] la_data_out[32] la_data_out[31] la_data_out[30] la_data_out[29] la_data_out[28]
++ la_data_out[27] la_data_out[26] la_data_out[25] la_data_out[24] la_data_out[23] la_data_out[22] la_data_out[21]
++ la_data_out[20] la_data_out[19] la_data_out[18] la_data_out[17] la_data_out[16] la_data_out[15] la_data_out[14]
++ la_data_out[13] la_data_out[12] la_data_out[11] la_data_out[10] la_data_out[9] la_data_out[8] la_data_out[7]
++ la_data_out[6] la_data_out[5] la_data_out[4] la_data_out[3] la_data_out[2] la_data_out[1] la_data_out[0]
++ la_oenb[127] la_oenb[126] la_oenb[125] la_oenb[124] la_oenb[123] la_oenb[122] la_oenb[121] la_oenb[120]
++ la_oenb[119] la_oenb[118] la_oenb[117] la_oenb[116] la_oenb[115] la_oenb[114] la_oenb[113] la_oenb[112]
++ la_oenb[111] la_oenb[110] la_oenb[109] la_oenb[108] la_oenb[107] la_oenb[106] la_oenb[105] la_oenb[104]
++ la_oenb[103] la_oenb[102] la_oenb[101] la_oenb[100] la_oenb[99] la_oenb[98] la_oenb[97] la_oenb[96] la_oenb[95]
++ la_oenb[94] la_oenb[93] la_oenb[92] la_oenb[91] la_oenb[90] la_oenb[89] la_oenb[88] la_oenb[87] la_oenb[86]
++ la_oenb[85] la_oenb[84] la_oenb[83] la_oenb[82] la_oenb[81] la_oenb[80] la_oenb[79] la_oenb[78] la_oenb[77]
++ la_oenb[76] la_oenb[75] la_oenb[74] la_oenb[73] la_oenb[72] la_oenb[71] la_oenb[70] la_oenb[69] la_oenb[68]
++ la_oenb[67] la_oenb[66] la_oenb[65] la_oenb[64] la_oenb[63] la_oenb[62] la_oenb[61] la_oenb[60] la_oenb[59]
++ la_oenb[58] la_oenb[57] la_oenb[56] la_oenb[55] la_oenb[54] la_oenb[53] la_oenb[52] la_oenb[51] la_oenb[50]
++ la_oenb[49] la_oenb[48] la_oenb[47] la_oenb[46] la_oenb[45] la_oenb[44] la_oenb[43] la_oenb[42] la_oenb[41]
++ la_oenb[40] la_oenb[39] la_oenb[38] la_oenb[37] la_oenb[36] la_oenb[35] la_oenb[34] la_oenb[33] la_oenb[32]
++ la_oenb[31] la_oenb[30] la_oenb[29] la_oenb[28] la_oenb[27] la_oenb[26] la_oenb[25] la_oenb[24] la_oenb[23]
++ la_oenb[22] la_oenb[21] la_oenb[20] la_oenb[19] la_oenb[18] la_oenb[17] la_oenb[16] la_oenb[15] la_oenb[14]
++ la_oenb[13] la_oenb[12] la_oenb[11] la_oenb[10] la_oenb[9] la_oenb[8] la_oenb[7] la_oenb[6] la_oenb[5]
++ la_oenb[4] la_oenb[3] la_oenb[2] la_oenb[1] la_oenb[0] io_in[26] io_in[25] io_in[24] io_in[23] io_in[22]
++ io_in[21] io_in[20] io_in[19] io_in[18] io_in[17] io_in[16] io_in[15] io_in[14] io_in[13] io_in[12] io_in[11]
++ io_in[10] io_in[9] io_in[8] io_in[7] io_in[6] io_in[5] io_in[4] io_in[3] io_in[2] io_in[1] io_in[0]
++ io_in_3v3[26] io_in_3v3[25] io_in_3v3[24] io_in_3v3[23] io_in_3v3[22] io_in_3v3[21] io_in_3v3[20] io_in_3v3[19]
++ io_in_3v3[18] io_in_3v3[17] io_in_3v3[16] io_in_3v3[15] io_in_3v3[14] io_in_3v3[13] io_in_3v3[12] io_in_3v3[11]
++ io_in_3v3[10] io_in_3v3[9] io_in_3v3[8] io_in_3v3[7] io_in_3v3[6] io_in_3v3[5] io_in_3v3[4] io_in_3v3[3]
++ io_in_3v3[2] io_in_3v3[1] io_in_3v3[0] io_out[26] io_out[25] io_out[24] io_out[23] io_out[22] io_out[21]
++ io_out[20] io_out[19] io_out[18] io_out[17] io_out[16] io_out[15] io_out[14] io_out[13] io_out[12] io_out[11]
++ io_out[10] io_out[9] io_out[8] io_out[7] io_out[6] io_out[5] io_out[4] io_out[3] io_out[2] io_out[1] io_out[0]
++ io_oeb[26] io_oeb[25] io_oeb[24] io_oeb[23] io_oeb[22] io_oeb[21] io_oeb[20] io_oeb[19] io_oeb[18] io_oeb[17]
++ io_oeb[16] io_oeb[15] io_oeb[14] io_oeb[13] io_oeb[12] io_oeb[11] io_oeb[10] io_oeb[9] io_oeb[8] io_oeb[7]
++ io_oeb[6] io_oeb[5] io_oeb[4] io_oeb[3] io_oeb[2] io_oeb[1] io_oeb[0] gpio_analog[17] gpio_analog[16]
++ gpio_analog[15] gpio_analog[14] gpio_analog[13] gpio_analog[12] gpio_analog[11] gpio_analog[10] gpio_analog[9]
++ gpio_analog[8] gpio_analog[7] gpio_analog[6] gpio_analog[5] gpio_analog[4] gpio_analog[3] gpio_analog[2]
++ gpio_analog[1] gpio_analog[0] gpio_noesd[17] gpio_noesd[16] gpio_noesd[15] gpio_noesd[14] gpio_noesd[13]
++ gpio_noesd[12] gpio_noesd[11] gpio_noesd[10] gpio_noesd[9] gpio_noesd[8] gpio_noesd[7] gpio_noesd[6] gpio_noesd[5]
++ gpio_noesd[4] gpio_noesd[3] gpio_noesd[2] gpio_noesd[1] gpio_noesd[0] io_analog[10] io_analog[9] io_analog[8]
++ io_analog[7] io_analog[6] io_analog[5] io_analog[4] io_analog[3] io_analog[2] io_analog[1] io_analog[0]
++ io_clamp_high[2] io_clamp_high[1] io_clamp_high[0] io_clamp_low[2] io_clamp_low[1] io_clamp_low[0] user_clock2
++ user_irq[2] user_irq[1] user_irq[0]
+*.iopin vdda1
+*.iopin vdda2
+*.iopin vssa1
+*.iopin vssa2
+*.iopin vccd1
+*.iopin vccd2
+*.iopin vssd1
+*.iopin vssd2
+*.ipin wb_clk_i
+*.ipin wb_rst_i
+*.ipin wbs_stb_i
+*.ipin wbs_cyc_i
+*.ipin wbs_we_i
+*.ipin wbs_sel_i[3],wbs_sel_i[2],wbs_sel_i[1],wbs_sel_i[0]
+*.ipin
+*+ wbs_dat_i[31],wbs_dat_i[30],wbs_dat_i[29],wbs_dat_i[28],wbs_dat_i[27],wbs_dat_i[26],wbs_dat_i[25],wbs_dat_i[24],wbs_dat_i[23],wbs_dat_i[22],wbs_dat_i[21],wbs_dat_i[20],wbs_dat_i[19],wbs_dat_i[18],wbs_dat_i[17],wbs_dat_i[16],wbs_dat_i[15],wbs_dat_i[14],wbs_dat_i[13],wbs_dat_i[12],wbs_dat_i[11],wbs_dat_i[10],wbs_dat_i[9],wbs_dat_i[8],wbs_dat_i[7],wbs_dat_i[6],wbs_dat_i[5],wbs_dat_i[4],wbs_dat_i[3],wbs_dat_i[2],wbs_dat_i[1],wbs_dat_i[0]
+*.ipin
+*+ wbs_adr_i[31],wbs_adr_i[30],wbs_adr_i[29],wbs_adr_i[28],wbs_adr_i[27],wbs_adr_i[26],wbs_adr_i[25],wbs_adr_i[24],wbs_adr_i[23],wbs_adr_i[22],wbs_adr_i[21],wbs_adr_i[20],wbs_adr_i[19],wbs_adr_i[18],wbs_adr_i[17],wbs_adr_i[16],wbs_adr_i[15],wbs_adr_i[14],wbs_adr_i[13],wbs_adr_i[12],wbs_adr_i[11],wbs_adr_i[10],wbs_adr_i[9],wbs_adr_i[8],wbs_adr_i[7],wbs_adr_i[6],wbs_adr_i[5],wbs_adr_i[4],wbs_adr_i[3],wbs_adr_i[2],wbs_adr_i[1],wbs_adr_i[0]
+*.opin wbs_ack_o
+*.opin
+*+ wbs_dat_o[31],wbs_dat_o[30],wbs_dat_o[29],wbs_dat_o[28],wbs_dat_o[27],wbs_dat_o[26],wbs_dat_o[25],wbs_dat_o[24],wbs_dat_o[23],wbs_dat_o[22],wbs_dat_o[21],wbs_dat_o[20],wbs_dat_o[19],wbs_dat_o[18],wbs_dat_o[17],wbs_dat_o[16],wbs_dat_o[15],wbs_dat_o[14],wbs_dat_o[13],wbs_dat_o[12],wbs_dat_o[11],wbs_dat_o[10],wbs_dat_o[9],wbs_dat_o[8],wbs_dat_o[7],wbs_dat_o[6],wbs_dat_o[5],wbs_dat_o[4],wbs_dat_o[3],wbs_dat_o[2],wbs_dat_o[1],wbs_dat_o[0]
+*.ipin
+*+ la_data_in[127],la_data_in[126],la_data_in[125],la_data_in[124],la_data_in[123],la_data_in[122],la_data_in[121],la_data_in[120],la_data_in[119],la_data_in[118],la_data_in[117],la_data_in[116],la_data_in[115],la_data_in[114],la_data_in[113],la_data_in[112],la_data_in[111],la_data_in[110],la_data_in[109],la_data_in[108],la_data_in[107],la_data_in[106],la_data_in[105],la_data_in[104],la_data_in[103],la_data_in[102],la_data_in[101],la_data_in[100],la_data_in[99],la_data_in[98],la_data_in[97],la_data_in[96],la_data_in[95],la_data_in[94],la_data_in[93],la_data_in[92],la_data_in[91],la_data_in[90],la_data_in[89],la_data_in[88],la_data_in[87],la_data_in[86],la_data_in[85],la_data_in[84],la_data_in[83],la_data_in[82],la_data_in[81],la_data_in[80],la_data_in[79],la_data_in[78],la_data_in[77],la_data_in[76],la_data_in[75],la_data_in[74],la_data_in[73],la_data_in[72],la_data_in[71],la_data_in[70],la_data_in[69],la_data_in[68],la_data_in[67],la_data_in[66],la_data_in[65],la_data_in[64],la_data_in[63],la_data_in[62],la_data_in[61],la_data_in[60],la_data_in[59],la_data_in[58],la_data_in[57],la_data_in[56],la_data_in[55],la_data_in[54],la_data_in[53],la_data_in[52],la_data_in[51],la_data_in[50],la_data_in[49],la_data_in[48],la_data_in[47],la_data_in[46],la_data_in[45],la_data_in[44],la_data_in[43],la_data_in[42],la_data_in[41],la_data_in[40],la_data_in[39],la_data_in[38],la_data_in[37],la_data_in[36],la_data_in[35],la_data_in[34],la_data_in[33],la_data_in[32],la_data_in[31],la_data_in[30],la_data_in[29],la_data_in[28],la_data_in[27],la_data_in[26],la_data_in[25],la_data_in[24],la_data_in[23],la_data_in[22],la_data_in[21],la_data_in[20],la_data_in[19],la_data_in[18],la_data_in[17],la_data_in[16],la_data_in[15],la_data_in[14],la_data_in[13],la_data_in[12],la_data_in[11],la_data_in[10],la_data_in[9],la_data_in[8],la_data_in[7],la_data_in[6],la_data_in[5],la_data_in[4],la_data_in[3],la_data_in[2],la_data_in[1],la_data_in[0]
+*.opin
+*+ la_data_out[127],la_data_out[126],la_data_out[125],la_data_out[124],la_data_out[123],la_data_out[122],la_data_out[121],la_data_out[120],la_data_out[119],la_data_out[118],la_data_out[117],la_data_out[116],la_data_out[115],la_data_out[114],la_data_out[113],la_data_out[112],la_data_out[111],la_data_out[110],la_data_out[109],la_data_out[108],la_data_out[107],la_data_out[106],la_data_out[105],la_data_out[104],la_data_out[103],la_data_out[102],la_data_out[101],la_data_out[100],la_data_out[99],la_data_out[98],la_data_out[97],la_data_out[96],la_data_out[95],la_data_out[94],la_data_out[93],la_data_out[92],la_data_out[91],la_data_out[90],la_data_out[89],la_data_out[88],la_data_out[87],la_data_out[86],la_data_out[85],la_data_out[84],la_data_out[83],la_data_out[82],la_data_out[81],la_data_out[80],la_data_out[79],la_data_out[78],la_data_out[77],la_data_out[76],la_data_out[75],la_data_out[74],la_data_out[73],la_data_out[72],la_data_out[71],la_data_out[70],la_data_out[69],la_data_out[68],la_data_out[67],la_data_out[66],la_data_out[65],la_data_out[64],la_data_out[63],la_data_out[62],la_data_out[61],la_data_out[60],la_data_out[59],la_data_out[58],la_data_out[57],la_data_out[56],la_data_out[55],la_data_out[54],la_data_out[53],la_data_out[52],la_data_out[51],la_data_out[50],la_data_out[49],la_data_out[48],la_data_out[47],la_data_out[46],la_data_out[45],la_data_out[44],la_data_out[43],la_data_out[42],la_data_out[41],la_data_out[40],la_data_out[39],la_data_out[38],la_data_out[37],la_data_out[36],la_data_out[35],la_data_out[34],la_data_out[33],la_data_out[32],la_data_out[31],la_data_out[30],la_data_out[29],la_data_out[28],la_data_out[27],la_data_out[26],la_data_out[25],la_data_out[24],la_data_out[23],la_data_out[22],la_data_out[21],la_data_out[20],la_data_out[19],la_data_out[18],la_data_out[17],la_data_out[16],la_data_out[15],la_data_out[14],la_data_out[13],la_data_out[12],la_data_out[11],la_data_out[10],la_data_out[9],la_data_out[8],la_data_out[7],la_data_out[6],la_data_out[5],la_data_out[4],la_data_out[3],la_data_out[2],la_data_out[1],la_data_out[0]
+*.ipin
+*+ io_in[26],io_in[25],io_in[24],io_in[23],io_in[22],io_in[21],io_in[20],io_in[19],io_in[18],io_in[17],io_in[16],io_in[15],io_in[14],io_in[13],io_in[12],io_in[11],io_in[10],io_in[9],io_in[8],io_in[7],io_in[6],io_in[5],io_in[4],io_in[3],io_in[2],io_in[1],io_in[0]
+*.ipin
+*+ io_in_3v3[26],io_in_3v3[25],io_in_3v3[24],io_in_3v3[23],io_in_3v3[22],io_in_3v3[21],io_in_3v3[20],io_in_3v3[19],io_in_3v3[18],io_in_3v3[17],io_in_3v3[16],io_in_3v3[15],io_in_3v3[14],io_in_3v3[13],io_in_3v3[12],io_in_3v3[11],io_in_3v3[10],io_in_3v3[9],io_in_3v3[8],io_in_3v3[7],io_in_3v3[6],io_in_3v3[5],io_in_3v3[4],io_in_3v3[3],io_in_3v3[2],io_in_3v3[1],io_in_3v3[0]
+*.ipin user_clock2
+*.opin
+*+ io_out[26],io_out[25],io_out[24],io_out[23],io_out[22],io_out[21],io_out[20],io_out[19],io_out[18],io_out[17],io_out[16],io_out[15],io_out[14],io_out[13],io_out[12],io_out[11],io_out[10],io_out[9],io_out[8],io_out[7],io_out[6],io_out[5],io_out[4],io_out[3],io_out[2],io_out[1],io_out[0]
+*.opin
+*+ io_oeb[26],io_oeb[25],io_oeb[24],io_oeb[23],io_oeb[22],io_oeb[21],io_oeb[20],io_oeb[19],io_oeb[18],io_oeb[17],io_oeb[16],io_oeb[15],io_oeb[14],io_oeb[13],io_oeb[12],io_oeb[11],io_oeb[10],io_oeb[9],io_oeb[8],io_oeb[7],io_oeb[6],io_oeb[5],io_oeb[4],io_oeb[3],io_oeb[2],io_oeb[1],io_oeb[0]
+*.iopin
+*+ gpio_analog[17],gpio_analog[16],gpio_analog[15],gpio_analog[14],gpio_analog[13],gpio_analog[12],gpio_analog[11],gpio_analog[10],gpio_analog[9],gpio_analog[8],gpio_analog[7],gpio_analog[6],gpio_analog[5],gpio_analog[4],gpio_analog[3],gpio_analog[2],gpio_analog[1],gpio_analog[0]
+*.iopin
+*+ gpio_noesd[17],gpio_noesd[16],gpio_noesd[15],gpio_noesd[14],gpio_noesd[13],gpio_noesd[12],gpio_noesd[11],gpio_noesd[10],gpio_noesd[9],gpio_noesd[8],gpio_noesd[7],gpio_noesd[6],gpio_noesd[5],gpio_noesd[4],gpio_noesd[3],gpio_noesd[2],gpio_noesd[1],gpio_noesd[0]
+*.iopin
+*+ io_analog[10],io_analog[9],io_analog[8],io_analog[7],io_analog[6],io_analog[5],io_analog[4],io_analog[3],io_analog[2],io_analog[1],io_analog[0]
+*.iopin io_clamp_high[2],io_clamp_high[1],io_clamp_high[0]
+*.iopin io_clamp_low[2],io_clamp_low[1],io_clamp_low[0]
+*.opin user_irq[2],user_irq[1],user_irq[0]
+*.ipin
+*+ la_oenb[127],la_oenb[126],la_oenb[125],la_oenb[124],la_oenb[123],la_oenb[122],la_oenb[121],la_oenb[120],la_oenb[119],la_oenb[118],la_oenb[117],la_oenb[116],la_oenb[115],la_oenb[114],la_oenb[113],la_oenb[112],la_oenb[111],la_oenb[110],la_oenb[109],la_oenb[108],la_oenb[107],la_oenb[106],la_oenb[105],la_oenb[104],la_oenb[103],la_oenb[102],la_oenb[101],la_oenb[100],la_oenb[99],la_oenb[98],la_oenb[97],la_oenb[96],la_oenb[95],la_oenb[94],la_oenb[93],la_oenb[92],la_oenb[91],la_oenb[90],la_oenb[89],la_oenb[88],la_oenb[87],la_oenb[86],la_oenb[85],la_oenb[84],la_oenb[83],la_oenb[82],la_oenb[81],la_oenb[80],la_oenb[79],la_oenb[78],la_oenb[77],la_oenb[76],la_oenb[75],la_oenb[74],la_oenb[73],la_oenb[72],la_oenb[71],la_oenb[70],la_oenb[69],la_oenb[68],la_oenb[67],la_oenb[66],la_oenb[65],la_oenb[64],la_oenb[63],la_oenb[62],la_oenb[61],la_oenb[60],la_oenb[59],la_oenb[58],la_oenb[57],la_oenb[56],la_oenb[55],la_oenb[54],la_oenb[53],la_oenb[52],la_oenb[51],la_oenb[50],la_oenb[49],la_oenb[48],la_oenb[47],la_oenb[46],la_oenb[45],la_oenb[44],la_oenb[43],la_oenb[42],la_oenb[41],la_oenb[40],la_oenb[39],la_oenb[38],la_oenb[37],la_oenb[36],la_oenb[35],la_oenb[34],la_oenb[33],la_oenb[32],la_oenb[31],la_oenb[30],la_oenb[29],la_oenb[28],la_oenb[27],la_oenb[26],la_oenb[25],la_oenb[24],la_oenb[23],la_oenb[22],la_oenb[21],la_oenb[20],la_oenb[19],la_oenb[18],la_oenb[17],la_oenb[16],la_oenb[15],la_oenb[14],la_oenb[13],la_oenb[12],la_oenb[11],la_oenb[10],la_oenb[9],la_oenb[8],la_oenb[7],la_oenb[6],la_oenb[5],la_oenb[4],la_oenb[3],la_oenb[2],la_oenb[1],la_oenb[0]
+x1 vccd1 vssa1 io_analog[3] io_analog[8] io_analog[2] io_analog[5] io_analog[6] comparator
+XM40 net1 net2 vssa1 vssa1 sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM41 net1 net2 vccd1 vccd1 sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM42 net3 net1 vssa1 vssa1 sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM43 net3 net1 vccd1 vccd1 sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM44 net4 net3 vssa1 vssa1 sky130_fd_pr__nfet_01v8 L=0.15 W=8 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM45 net4 net3 vccd1 vccd1 sky130_fd_pr__pfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM46 io_analog[1] net4 vssa1 vssa1 sky130_fd_pr__nfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM47 io_analog[1] net4 vccd1 vccd1 sky130_fd_pr__pfet_01v8 L=0.15 W=32 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM1 net2 io_analog[8] vssa1 vssa1 sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM2 net2 io_analog[8] vccd1 vccd1 sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+V0 vssa1 io_clamp_low[1] 0.0
+V1 vssa1 io_clamp_low[2] 0.0
+V2 vccd1 io_clamp_high[2] 0.0
+V3 vccd1 io_clamp_high[1] 0.0
+.ends
+
+
+* expanding symbol: comparator.sym # of pins=7
+** sym_path: /home/krishna/Strong_Arm_MPW6/xschem/comparator.sym
+** sch_path: /home/krishna/Strong_Arm_MPW6/xschem/comparator.sch
+.subckt comparator VDD GND Outn CLK Outp Vp Vn
+
+*.iopin VDD
+*.iopin GND
+*.ipin Vp
+*.ipin Vn
+*.iopin CLK
+*.opin Outn
+*.opin Outp
+XM1 net2 Vn net1 GND sky130_fd_pr__nfet_01v8 L=0.15 W=5.3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 net3 Vp net1 GND sky130_fd_pr__nfet_01v8 L=0.15 W=5.3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net1 C GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM11 net2 C VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM12 Dn C VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM13 Dp C VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM14 net3 C VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM15 Dp Dn net3 GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.78 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM16 Dn Dp net2 GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.78 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM17 Dp Dn VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.78 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM18 Dn Dp VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.78 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM20 p Lp GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM21 n Ln GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM22 p n VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM23 n p VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM24 net4 CLK GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM25 net4 CLK VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM26 net5 net4 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM27 net5 net4 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM28 net6 net5 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=8 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM29 net6 net5 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM30 C net6 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM31 C net6 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=32 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM40 net7 n GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM41 net7 n VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM42 net8 net7 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM43 net8 net7 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM44 net9 net8 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=8 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM45 net9 net8 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM46 Outn net9 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM47 Outn net9 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=32 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM48 net10 p GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM49 net10 p VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM50 net11 net10 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM51 net11 net10 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM52 net12 net11 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=8 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM53 net12 net11 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM54 Outp net12 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM55 Outp net12 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=32 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 Lp Dp GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM5 Lp Dp VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 Ln Dn GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM7 Ln Dn VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+.GLOBAL GND
+.end
diff --git a/xschem/comparator.sch b/xschem/comparator.sch
new file mode 100644
index 0000000..e39dc98
--- /dev/null
+++ b/xschem/comparator.sch
@@ -0,0 +1,1398 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 1380 -610 1380 -570 {
+lab=#net1}
+N 1790 -600 1790 -570 {
+lab=#net1}
+N 1590 -570 1590 -550 {
+lab=#net1}
+N 1590 -490 1590 -460 {
+lab=GND}
+N 1590 -520 1610 -520 {
+lab=GND}
+N 1610 -520 1610 -480 {
+lab=GND}
+N 1590 -480 1610 -480 {
+lab=GND}
+N 1370 -640 1560 -640 {
+lab=GND}
+N 1610 -630 1790 -630 {
+lab=GND}
+N 1180 -1000 1220 -1000 {
+lab=C}
+N 1890 -990 1900 -990 {
+lab=C}
+N 1890 -990 1890 -950 {
+lab=C}
+N 1260 -1000 1280 -1000 {
+lab=VDD}
+N 1280 -1040 1280 -1000 {
+lab=VDD}
+N 1260 -1040 1280 -1040 {
+lab=VDD}
+N 1260 -1040 1260 -1030 {
+lab=VDD}
+N 1460 -1150 1780 -1150 {
+lab=VDD}
+N 1940 -1030 1940 -1020 {
+lab=VDD}
+N 1840 -1140 1840 -1130 {
+lab=VDD}
+N 1360 -1140 1360 -1130 {
+lab=VDD}
+N 1360 -1100 1370 -1100 {
+lab=VDD}
+N 1370 -1100 1380 -1100 {
+lab=VDD}
+N 1380 -1140 1380 -1100 {
+lab=VDD}
+N 1840 -1100 1860 -1100 {
+lab=VDD}
+N 1860 -1140 1860 -1100 {
+lab=VDD}
+N 1940 -990 1960 -990 {
+lab=VDD}
+N 1960 -1030 1960 -990 {
+lab=VDD}
+N 1940 -1030 1960 -1030 {
+lab=VDD}
+N 1510 -520 1550 -520 {
+lab=C}
+N 1310 -640 1340 -640 {
+lab=Vn}
+N 1830 -630 1880 -630 {
+lab=Vp}
+N 1510 -1030 1540 -1030 {
+lab=Dp}
+N 1540 -1030 1540 -890 {
+lab=Dp}
+N 1510 -890 1540 -890 {
+lab=Dp}
+N 1630 -1030 1670 -1030 {
+lab=Dn}
+N 1630 -1030 1630 -890 {
+lab=Dn}
+N 1470 -1000 1470 -920 {
+lab=Dn}
+N 1630 -890 1670 -890 {
+lab=Dn}
+N 1710 -1000 1710 -920 {
+lab=Dp}
+N 1470 -860 1470 -840 {
+lab=#net2}
+N 1710 -860 1710 -840 {
+lab=#net3}
+N 1470 -1080 1470 -1060 {
+lab=VDD}
+N 1470 -1080 1710 -1080 {
+lab=VDD}
+N 1710 -1080 1710 -1060 {
+lab=VDD}
+N 1470 -980 1630 -980 {
+lab=Dn}
+N 1540 -940 1710 -940 {
+lab=Dp}
+N 1440 -890 1470 -890 {
+lab=GND}
+N 1710 -890 1730 -890 {
+lab=GND}
+N 1730 -890 1740 -890 {
+lab=GND}
+N 1740 -890 1740 -840 {
+lab=GND}
+N 1580 -1120 1580 -1080 {
+lab=VDD}
+N 1440 -1030 1470 -1030 {
+lab=VDD}
+N 1440 -1080 1440 -1030 {
+lab=VDD}
+N 1710 -1030 1740 -1030 {
+lab=VDD}
+N 1740 -1080 1740 -1030 {
+lab=VDD}
+N 2640 -1110 2670 -1110 {
+lab=p}
+N 2760 -1110 2800 -1110 {
+lab=n}
+N 2600 -1080 2600 -1000 {
+lab=n}
+N 2840 -1080 2840 -1000 {
+lab=p}
+N 2600 -940 2600 -920 {
+lab=GND}
+N 2600 -920 2840 -920 {
+lab=GND}
+N 2840 -940 2840 -920 {
+lab=GND}
+N 2600 -1160 2600 -1140 {
+lab=VDD}
+N 2600 -1160 2840 -1160 {
+lab=VDD}
+N 2840 -1160 2840 -1140 {
+lab=VDD}
+N 2710 -1200 2710 -1160 {
+lab=VDD}
+N 2570 -1110 2600 -1110 {
+lab=VDD}
+N 2570 -1160 2570 -1110 {
+lab=VDD}
+N 2570 -1160 2600 -1160 {
+lab=VDD}
+N 2840 -1110 2870 -1110 {
+lab=VDD}
+N 2870 -1160 2870 -1110 {
+lab=VDD}
+N 2840 -1160 2870 -1160 {
+lab=VDD}
+N 2530 -970 2560 -970 {
+lab=Ln}
+N 2880 -970 2910 -970 {
+lab=Lp}
+N 2670 -1110 2740 -1040 {
+lab=p}
+N 2740 -1040 2840 -1040 {
+lab=p}
+N 2670 -1040 2760 -1110 {
+lab=n}
+N 2600 -1040 2670 -1040 {
+lab=n}
+N 2600 -970 2620 -970 {
+lab=GND}
+N 2620 -970 2620 -920 {
+lab=GND}
+N 2820 -970 2840 -970 {
+lab=GND}
+N 2820 -970 2820 -920 {
+lab=GND}
+N 1440 -1100 1440 -1080 {
+lab=VDD}
+N 1440 -1100 1740 -1100 {
+lab=VDD}
+N 1740 -1100 1740 -1080 {
+lab=VDD}
+N 1620 -1150 1620 -1100 {
+lab=VDD}
+N 550 -1130 550 -1110 {
+lab=#net4}
+N 490 -1180 510 -1180 {
+lab=CLK}
+N 490 -1130 490 -1080 {
+lab=CLK}
+N 490 -1080 510 -1080 {
+lab=CLK}
+N 550 -1220 550 -1210 {
+lab=VDD}
+N 550 -1180 580 -1180 {
+lab=VDD}
+N 580 -1220 580 -1180 {
+lab=VDD}
+N 550 -1220 580 -1220 {
+lab=VDD}
+N 550 -1040 550 -1030 {
+lab=GND}
+N 550 -1080 580 -1080 {
+lab=GND}
+N 580 -1080 580 -1040 {
+lab=GND}
+N 550 -1040 580 -1040 {
+lab=GND}
+N 710 -1130 710 -1110 {
+lab=#net5}
+N 650 -1180 670 -1180 {
+lab=#net4}
+N 650 -1130 650 -1080 {
+lab=#net4}
+N 650 -1080 670 -1080 {
+lab=#net4}
+N 710 -1220 710 -1210 {
+lab=VDD}
+N 710 -1180 740 -1180 {
+lab=VDD}
+N 740 -1220 740 -1180 {
+lab=VDD}
+N 710 -1220 740 -1220 {
+lab=VDD}
+N 710 -1040 710 -1030 {
+lab=GND}
+N 710 -1080 740 -1080 {
+lab=GND}
+N 740 -1080 740 -1040 {
+lab=GND}
+N 710 -1040 740 -1040 {
+lab=GND}
+N 870 -1130 870 -1110 {
+lab=#net6}
+N 810 -1180 830 -1180 {
+lab=#net5}
+N 810 -1130 810 -1080 {
+lab=#net5}
+N 810 -1080 830 -1080 {
+lab=#net5}
+N 870 -1220 870 -1210 {
+lab=VDD}
+N 870 -1180 900 -1180 {
+lab=VDD}
+N 900 -1220 900 -1180 {
+lab=VDD}
+N 870 -1220 900 -1220 {
+lab=VDD}
+N 870 -1040 870 -1030 {
+lab=GND}
+N 870 -1080 900 -1080 {
+lab=GND}
+N 900 -1080 900 -1040 {
+lab=GND}
+N 870 -1040 900 -1040 {
+lab=GND}
+N 1020 -1130 1020 -1110 {
+lab=C}
+N 960 -1180 980 -1180 {
+lab=#net6}
+N 960 -1130 960 -1080 {
+lab=#net6}
+N 960 -1080 980 -1080 {
+lab=#net6}
+N 1020 -1220 1020 -1210 {
+lab=VDD}
+N 1020 -1180 1050 -1180 {
+lab=VDD}
+N 1050 -1220 1050 -1180 {
+lab=VDD}
+N 1020 -1220 1050 -1220 {
+lab=VDD}
+N 1020 -1040 1020 -1030 {
+lab=GND}
+N 1020 -1080 1050 -1080 {
+lab=GND}
+N 1050 -1080 1050 -1040 {
+lab=GND}
+N 1020 -1040 1050 -1040 {
+lab=GND}
+N 550 -1130 650 -1130 {
+lab=#net4}
+N 710 -1130 810 -1130 {
+lab=#net5}
+N 870 -1130 960 -1130 {
+lab=#net6}
+N 1020 -1130 1110 -1130 {
+lab=C}
+N 460 -1130 490 -1130 {
+lab=CLK}
+N 550 -1250 550 -1220 {
+lab=VDD}
+N 870 -1250 1020 -1250 {
+lab=VDD}
+N 1020 -1250 1020 -1220 {
+lab=VDD}
+N 710 -1250 710 -1220 {
+lab=VDD}
+N 870 -1250 870 -1220 {
+lab=VDD}
+N 550 -1050 550 -1040 {
+lab=GND}
+N 710 -1050 710 -1040 {
+lab=GND}
+N 870 -1050 870 -1040 {
+lab=GND}
+N 1020 -1050 1020 -1040 {
+lab=GND}
+N 550 -1150 550 -1130 {
+lab=#net4}
+N 650 -1180 650 -1130 {
+lab=#net4}
+N 710 -1150 710 -1130 {
+lab=#net5}
+N 810 -1180 810 -1130 {
+lab=#net5}
+N 870 -1150 870 -1130 {
+lab=#net6}
+N 960 -1180 960 -1130 {
+lab=#net6}
+N 1020 -1150 1020 -1130 {
+lab=C}
+N 490 -1180 490 -1130 {
+lab=CLK}
+N 550 -1250 710 -1250 {
+lab=VDD}
+N 710 -1250 870 -1250 {
+lab=VDD}
+N 550 -1030 1020 -1030 {
+lab=GND}
+N 3100 -1220 3100 -1200 {
+lab=#net7}
+N 3040 -1270 3060 -1270 {
+lab=n}
+N 3040 -1220 3040 -1170 {
+lab=n}
+N 3040 -1170 3060 -1170 {
+lab=n}
+N 3100 -1310 3100 -1300 {
+lab=VDD}
+N 3100 -1270 3130 -1270 {
+lab=VDD}
+N 3130 -1310 3130 -1270 {
+lab=VDD}
+N 3100 -1310 3130 -1310 {
+lab=VDD}
+N 3100 -1130 3100 -1120 {
+lab=GND}
+N 3100 -1170 3130 -1170 {
+lab=GND}
+N 3130 -1170 3130 -1130 {
+lab=GND}
+N 3100 -1130 3130 -1130 {
+lab=GND}
+N 3260 -1220 3260 -1200 {
+lab=#net8}
+N 3200 -1270 3220 -1270 {
+lab=#net7}
+N 3200 -1220 3200 -1170 {
+lab=#net7}
+N 3200 -1170 3220 -1170 {
+lab=#net7}
+N 3260 -1310 3260 -1300 {
+lab=VDD}
+N 3260 -1270 3290 -1270 {
+lab=VDD}
+N 3290 -1310 3290 -1270 {
+lab=VDD}
+N 3260 -1310 3290 -1310 {
+lab=VDD}
+N 3260 -1130 3260 -1120 {
+lab=GND}
+N 3260 -1170 3290 -1170 {
+lab=GND}
+N 3290 -1170 3290 -1130 {
+lab=GND}
+N 3260 -1130 3290 -1130 {
+lab=GND}
+N 3420 -1220 3420 -1200 {
+lab=#net9}
+N 3360 -1270 3380 -1270 {
+lab=#net8}
+N 3360 -1220 3360 -1170 {
+lab=#net8}
+N 3360 -1170 3380 -1170 {
+lab=#net8}
+N 3420 -1310 3420 -1300 {
+lab=VDD}
+N 3420 -1270 3450 -1270 {
+lab=VDD}
+N 3450 -1310 3450 -1270 {
+lab=VDD}
+N 3420 -1310 3450 -1310 {
+lab=VDD}
+N 3420 -1130 3420 -1120 {
+lab=GND}
+N 3420 -1170 3450 -1170 {
+lab=GND}
+N 3450 -1170 3450 -1130 {
+lab=GND}
+N 3420 -1130 3450 -1130 {
+lab=GND}
+N 3570 -1220 3570 -1200 {
+lab=Outn}
+N 3510 -1270 3530 -1270 {
+lab=#net9}
+N 3510 -1220 3510 -1170 {
+lab=#net9}
+N 3510 -1170 3530 -1170 {
+lab=#net9}
+N 3570 -1310 3570 -1300 {
+lab=VDD}
+N 3570 -1270 3600 -1270 {
+lab=VDD}
+N 3600 -1310 3600 -1270 {
+lab=VDD}
+N 3570 -1310 3600 -1310 {
+lab=VDD}
+N 3570 -1130 3570 -1120 {
+lab=GND}
+N 3570 -1170 3600 -1170 {
+lab=GND}
+N 3600 -1170 3600 -1130 {
+lab=GND}
+N 3570 -1130 3600 -1130 {
+lab=GND}
+N 3100 -1220 3200 -1220 {
+lab=#net7}
+N 3260 -1220 3360 -1220 {
+lab=#net8}
+N 3420 -1220 3510 -1220 {
+lab=#net9}
+N 3570 -1220 3660 -1220 {
+lab=Outn}
+N 3010 -1220 3040 -1220 {
+lab=n}
+N 3100 -1340 3100 -1310 {
+lab=VDD}
+N 3420 -1340 3570 -1340 {
+lab=VDD}
+N 3570 -1340 3570 -1310 {
+lab=VDD}
+N 3260 -1340 3260 -1310 {
+lab=VDD}
+N 3420 -1340 3420 -1310 {
+lab=VDD}
+N 3100 -1140 3100 -1130 {
+lab=GND}
+N 3260 -1140 3260 -1130 {
+lab=GND}
+N 3420 -1140 3420 -1130 {
+lab=GND}
+N 3570 -1140 3570 -1130 {
+lab=GND}
+N 3100 -1240 3100 -1220 {
+lab=#net7}
+N 3200 -1270 3200 -1220 {
+lab=#net7}
+N 3260 -1240 3260 -1220 {
+lab=#net8}
+N 3360 -1270 3360 -1220 {
+lab=#net8}
+N 3420 -1240 3420 -1220 {
+lab=#net9}
+N 3510 -1270 3510 -1220 {
+lab=#net9}
+N 3570 -1240 3570 -1220 {
+lab=Outn}
+N 3040 -1270 3040 -1220 {
+lab=n}
+N 3100 -1340 3260 -1340 {
+lab=VDD}
+N 3260 -1340 3420 -1340 {
+lab=VDD}
+N 3100 -1120 3570 -1120 {
+lab=GND}
+N 3100 -850 3100 -830 {
+lab=#net10}
+N 3040 -900 3060 -900 {
+lab=p}
+N 3040 -850 3040 -800 {
+lab=p}
+N 3040 -800 3060 -800 {
+lab=p}
+N 3100 -940 3100 -930 {
+lab=VDD}
+N 3100 -900 3130 -900 {
+lab=VDD}
+N 3130 -940 3130 -900 {
+lab=VDD}
+N 3100 -940 3130 -940 {
+lab=VDD}
+N 3100 -760 3100 -750 {
+lab=GND}
+N 3100 -800 3130 -800 {
+lab=GND}
+N 3130 -800 3130 -760 {
+lab=GND}
+N 3100 -760 3130 -760 {
+lab=GND}
+N 3260 -850 3260 -830 {
+lab=#net11}
+N 3200 -900 3220 -900 {
+lab=#net10}
+N 3200 -850 3200 -800 {
+lab=#net10}
+N 3200 -800 3220 -800 {
+lab=#net10}
+N 3260 -940 3260 -930 {
+lab=VDD}
+N 3260 -900 3290 -900 {
+lab=VDD}
+N 3290 -940 3290 -900 {
+lab=VDD}
+N 3260 -940 3290 -940 {
+lab=VDD}
+N 3260 -760 3260 -750 {
+lab=GND}
+N 3260 -800 3290 -800 {
+lab=GND}
+N 3290 -800 3290 -760 {
+lab=GND}
+N 3260 -760 3290 -760 {
+lab=GND}
+N 3420 -850 3420 -830 {
+lab=#net12}
+N 3360 -900 3380 -900 {
+lab=#net11}
+N 3360 -850 3360 -800 {
+lab=#net11}
+N 3360 -800 3380 -800 {
+lab=#net11}
+N 3420 -940 3420 -930 {
+lab=VDD}
+N 3420 -900 3450 -900 {
+lab=VDD}
+N 3450 -940 3450 -900 {
+lab=VDD}
+N 3420 -940 3450 -940 {
+lab=VDD}
+N 3420 -760 3420 -750 {
+lab=GND}
+N 3420 -800 3450 -800 {
+lab=GND}
+N 3450 -800 3450 -760 {
+lab=GND}
+N 3420 -760 3450 -760 {
+lab=GND}
+N 3570 -850 3570 -830 {
+lab=Outp}
+N 3510 -900 3530 -900 {
+lab=#net12}
+N 3510 -850 3510 -800 {
+lab=#net12}
+N 3510 -800 3530 -800 {
+lab=#net12}
+N 3570 -940 3570 -930 {
+lab=VDD}
+N 3570 -900 3600 -900 {
+lab=VDD}
+N 3600 -940 3600 -900 {
+lab=VDD}
+N 3570 -940 3600 -940 {
+lab=VDD}
+N 3570 -760 3570 -750 {
+lab=GND}
+N 3570 -800 3600 -800 {
+lab=GND}
+N 3600 -800 3600 -760 {
+lab=GND}
+N 3570 -760 3600 -760 {
+lab=GND}
+N 3100 -850 3200 -850 {
+lab=#net10}
+N 3260 -850 3360 -850 {
+lab=#net11}
+N 3420 -850 3510 -850 {
+lab=#net12}
+N 3570 -850 3660 -850 {
+lab=Outp}
+N 3010 -850 3040 -850 {
+lab=p}
+N 3100 -970 3100 -940 {
+lab=VDD}
+N 3420 -970 3570 -970 {
+lab=VDD}
+N 3570 -970 3570 -940 {
+lab=VDD}
+N 3260 -970 3260 -940 {
+lab=VDD}
+N 3420 -970 3420 -940 {
+lab=VDD}
+N 3100 -770 3100 -760 {
+lab=GND}
+N 3260 -770 3260 -760 {
+lab=GND}
+N 3420 -770 3420 -760 {
+lab=GND}
+N 3570 -770 3570 -760 {
+lab=GND}
+N 3100 -870 3100 -850 {
+lab=#net10}
+N 3200 -900 3200 -850 {
+lab=#net10}
+N 3260 -870 3260 -850 {
+lab=#net11}
+N 3360 -900 3360 -850 {
+lab=#net11}
+N 3420 -870 3420 -850 {
+lab=#net12}
+N 3510 -900 3510 -850 {
+lab=#net12}
+N 3570 -870 3570 -850 {
+lab=Outp}
+N 3040 -900 3040 -850 {
+lab=p}
+N 3100 -970 3260 -970 {
+lab=VDD}
+N 3260 -970 3420 -970 {
+lab=VDD}
+N 3100 -750 3570 -750 {
+lab=GND}
+N 1590 -630 1610 -630 {
+lab=GND}
+N 1590 -630 1590 -600 {
+lab=GND}
+N 1560 -640 1590 -640 {
+lab=GND}
+N 1590 -640 1590 -630 {
+lab=GND}
+N 1380 -840 1380 -670 {
+lab=#net2}
+N 1420 -840 1470 -840 {
+lab=#net2}
+N 1440 -890 1440 -800 {
+lab=GND}
+N 1440 -800 1440 -640 {
+lab=GND}
+N 1790 -830 1790 -660 {
+lab=#net3}
+N 1710 -830 1790 -830 {
+lab=#net3}
+N 1710 -840 1710 -830 {
+lab=#net3}
+N 1740 -840 1740 -630 {
+lab=GND}
+N 1380 -570 1590 -570 {
+lab=#net1}
+N 1590 -570 1790 -570 {
+lab=#net1}
+N 1380 -840 1420 -840 {
+lab=#net2}
+N 1360 -1150 1460 -1150 {
+lab=VDD}
+N 1360 -1150 1360 -1140 {
+lab=VDD}
+N 1380 -1150 1380 -1140 {
+lab=VDD}
+N 1780 -1150 1860 -1150 {
+lab=VDD}
+N 1860 -1150 1860 -1140 {
+lab=VDD}
+N 1840 -1150 1840 -1140 {
+lab=VDD}
+N 1580 -1150 1580 -1120 {
+lab=VDD}
+N 1360 -1070 1360 -960 {
+lab=Dn}
+N 1360 -960 1470 -960 {
+lab=Dn}
+N 1840 -1070 1840 -980 {
+lab=Dp}
+N 1710 -980 1840 -980 {
+lab=Dp}
+N 1940 -960 1940 -830 {
+lab=#net3}
+N 1790 -830 1940 -830 {
+lab=#net3}
+N 1260 -970 1260 -840 {
+lab=#net2}
+N 1260 -840 1380 -840 {
+lab=#net2}
+N 1280 -1150 1280 -1040 {
+lab=VDD}
+N 1280 -1150 1360 -1150 {
+lab=VDD}
+N 1940 -1150 1940 -1030 {
+lab=VDD}
+N 1860 -1150 1940 -1150 {
+lab=VDD}
+N 1210 -1100 1320 -1100 {
+lab=C}
+N 1210 -1100 1210 -1000 {
+lab=C}
+N 1780 -1100 1800 -1100 {
+lab=C}
+N 2200 -960 2200 -940 {
+lab=Lp}
+N 2140 -1010 2160 -1010 {
+lab=Dp}
+N 2140 -960 2140 -910 {
+lab=Dp}
+N 2140 -910 2160 -910 {
+lab=Dp}
+N 2200 -1050 2200 -1040 {
+lab=VDD}
+N 2200 -1010 2230 -1010 {
+lab=VDD}
+N 2230 -1050 2230 -1010 {
+lab=VDD}
+N 2200 -1050 2230 -1050 {
+lab=VDD}
+N 2200 -870 2200 -860 {
+lab=GND}
+N 2200 -910 2230 -910 {
+lab=GND}
+N 2230 -910 2230 -870 {
+lab=GND}
+N 2200 -870 2230 -870 {
+lab=GND}
+N 2200 -1080 2200 -1050 {
+lab=VDD}
+N 2200 -880 2200 -870 {
+lab=GND}
+N 2200 -980 2200 -960 {
+lab=Lp}
+N 2140 -1010 2140 -960 {
+lab=Dp}
+N 2200 -650 2200 -630 {
+lab=Ln}
+N 2140 -700 2160 -700 {
+lab=Dn}
+N 2140 -650 2140 -600 {
+lab=Dn}
+N 2140 -600 2160 -600 {
+lab=Dn}
+N 2200 -740 2200 -730 {
+lab=VDD}
+N 2200 -700 2230 -700 {
+lab=VDD}
+N 2230 -740 2230 -700 {
+lab=VDD}
+N 2200 -740 2230 -740 {
+lab=VDD}
+N 2200 -560 2200 -550 {
+lab=GND}
+N 2200 -600 2230 -600 {
+lab=GND}
+N 2230 -600 2230 -560 {
+lab=GND}
+N 2200 -560 2230 -560 {
+lab=GND}
+N 2200 -770 2200 -740 {
+lab=VDD}
+N 2200 -570 2200 -560 {
+lab=GND}
+N 2200 -670 2200 -650 {
+lab=Ln}
+N 2140 -700 2140 -650 {
+lab=Dn}
+C {sky130_fd_pr/nfet_01v8.sym} 1360 -640 0 0 {name=M1
+L=0.15
+W=5.3
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 1810 -630 0 1 {name=M2
+L=0.15
+W=5.3
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 1570 -520 0 0 {name=M3
+L=0.15
+W=4
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 1240 -1000 0 0 {name=M11
+L=0.15
+W=0.5
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 1340 -1100 0 0 {name=M12
+L=0.15
+W=0.5
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 1820 -1100 0 0 {name=M13
+L=0.15
+W=0.5
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 1920 -990 0 0 {name=M14
+L=0.15
+W=0.5
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {devices/lab_pin.sym} 1510 -520 0 0 {name=l5 sig_type=std_logic lab=C}
+C {sky130_fd_pr/nfet_01v8.sym} 1690 -890 0 0 {name=M15
+L=0.15
+W=0.78
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 1490 -890 0 1 {name=M16
+L=0.15
+W=0.78
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 1690 -1030 0 0 {name=M17
+L=0.15
+W=0.78
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 1490 -1030 0 1 {name=M18
+L=0.15
+W=0.78
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {devices/lab_pin.sym} 1470 -940 0 0 {name=l14 sig_type=std_logic lab=Dn}
+C {devices/lab_pin.sym} 1710 -960 2 0 {name=l15 sig_type=std_logic lab=Dp}
+C {sky130_fd_pr/nfet_01v8.sym} 2860 -970 0 1 {name=M20
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 2580 -970 0 0 {name=M21
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 2820 -1110 0 0 {name=M22
+L=0.15
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 2620 -1110 0 1 {name=M23
+L=0.15
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {devices/lab_pin.sym} 2530 -970 0 0 {name=l30 sig_type=std_logic lab=Ln}
+C {devices/lab_pin.sym} 2910 -970 2 0 {name=l31 sig_type=std_logic lab=Lp}
+C {devices/lab_pin.sym} 2840 -1060 2 0 {name=l34 sig_type=std_logic lab=p}
+C {devices/iopin.sym} 740 -270 0 0 {name=p1 lab=VDD}
+C {devices/iopin.sym} 740 -230 0 0 {name=p2 lab=GND
+}
+C {devices/ipin.sym} 1870 -630 2 0 {name=p3 lab=Vp
+}
+C {devices/ipin.sym} 1320 -640 0 0 {name=p4 lab=Vn}
+C {devices/iopin.sym} 470 -1130 2 0 {name=p5 lab=CLK}
+C {devices/opin.sym} 3650 -1220 0 0 {name=p7 lab=Outn}
+C {devices/opin.sym} 3650 -850 0 0 {name=p8 lab=Outp}
+C {devices/lab_pin.sym} 1610 -1150 1 0 {name=l9 sig_type=std_logic lab=VDD}
+C {devices/lab_pin.sym} 2710 -1200 1 0 {name=l27 sig_type=std_logic lab=VDD}
+C {devices/lab_pin.sym} 1590 -460 3 0 {name=l10 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 2690 -920 3 0 {name=l19 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 1590 -600 0 0 {name=l1 sig_type=std_logic lab=GND}
+C {sky130_fd_pr/nfet_01v8.sym} 530 -1080 0 0 {name=M24
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 530 -1180 0 0 {name=M25
+L=0.15
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 690 -1080 0 0 {name=M26
+L=0.15
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 690 -1180 0 0 {name=M27
+L=0.15
+W=4
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 850 -1080 0 0 {name=M28
+L=0.15
+W=8
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 850 -1180 0 0 {name=M29
+L=0.15
+W=16
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 1000 -1080 0 0 {name=M30
+L=0.15
+W=16
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 1000 -1180 0 0 {name=M31
+L=0.15
+W=32
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {devices/lab_pin.sym} 830 -1030 3 0 {name=l24 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 840 -1250 1 0 {name=l25 sig_type=std_logic lab=VDD}
+C {devices/lab_pin.sym} 1110 -1130 0 0 {name=l29 sig_type=std_logic lab=C}
+C {devices/lab_pin.sym} 1180 -1000 0 0 {name=l8 sig_type=std_logic lab=C
+}
+C {sky130_fd_pr/nfet_01v8.sym} 3080 -1170 0 0 {name=M40
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 3080 -1270 0 0 {name=M41
+L=0.15
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 3240 -1170 0 0 {name=M42
+L=0.15
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 3240 -1270 0 0 {name=M43
+L=0.15
+W=4
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 3400 -1170 0 0 {name=M44
+L=0.15
+W=8
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 3400 -1270 0 0 {name=M45
+L=0.15
+W=16
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 3550 -1170 0 0 {name=M46
+L=0.15
+W=16
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 3550 -1270 0 0 {name=M47
+L=0.15
+W=32
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {devices/lab_pin.sym} 3380 -1120 3 0 {name=l20 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 3390 -1340 1 0 {name=l22 sig_type=std_logic lab=VDD}
+C {sky130_fd_pr/nfet_01v8.sym} 3080 -800 0 0 {name=M48
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 3080 -900 0 0 {name=M49
+L=0.15
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 3240 -800 0 0 {name=M50
+L=0.15
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 3240 -900 0 0 {name=M51
+L=0.15
+W=4
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 3400 -800 0 0 {name=M52
+L=0.15
+W=8
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 3400 -900 0 0 {name=M53
+L=0.15
+W=16
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 3550 -800 0 0 {name=M54
+L=0.15
+W=16
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 3550 -900 0 0 {name=M55
+L=0.15
+W=32
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {devices/lab_pin.sym} 3380 -750 3 0 {name=l21 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 3390 -970 1 0 {name=l23 sig_type=std_logic lab=VDD}
+C {devices/lab_pin.sym} 3010 -850 2 0 {name=l17 sig_type=std_logic lab=p}
+C {devices/lab_pin.sym} 2600 -1060 2 0 {name=l18 sig_type=std_logic lab=n}
+C {devices/lab_pin.sym} 3010 -1220 0 0 {name=l33 sig_type=std_logic lab=n}
+C {devices/lab_pin.sym} 1780 -1100 0 0 {name=l2 sig_type=std_logic lab=C}
+C {devices/lab_pin.sym} 1890 -950 0 0 {name=l3 sig_type=std_logic lab=C}
+C {sky130_fd_pr/nfet_01v8.sym} 2180 -910 0 0 {name=M4
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 2180 -1010 0 0 {name=M5
+L=0.15
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 2180 -600 0 0 {name=M6
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 2180 -700 0 0 {name=M7
+L=0.15
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {devices/lab_pin.sym} 2140 -960 2 0 {name=l4 sig_type=std_logic lab=Dp}
+C {devices/lab_pin.sym} 2140 -650 0 0 {name=l6 sig_type=std_logic lab=Dn}
+C {devices/lab_pin.sym} 2200 -650 2 0 {name=l7 sig_type=std_logic lab=Ln}
+C {devices/lab_pin.sym} 2200 -960 2 0 {name=l11 sig_type=std_logic lab=Lp}
+C {devices/lab_pin.sym} 2200 -1080 1 0 {name=l12 sig_type=std_logic lab=VDD}
+C {devices/lab_pin.sym} 2200 -770 1 0 {name=l13 sig_type=std_logic lab=VDD}
+C {devices/lab_pin.sym} 2200 -550 0 0 {name=l16 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 2200 -860 0 0 {name=l26 sig_type=std_logic lab=GND}
diff --git a/xschem/comparator.spice b/xschem/comparator.spice
new file mode 100644
index 0000000..7776247
--- /dev/null
+++ b/xschem/comparator.spice
@@ -0,0 +1,140 @@
+** sch_path: /home/krishna/Strong_Arm_MPW6/xschem/comparator.sch
+**.subckt comparator VDD GND Vn Vp CLK Outn Outp
+*.iopin VDD
+*.iopin GND
+*.ipin Vn
+*.ipin Vp
+*.iopin CLK
+*.opin Outn
+*.opin Outp
+XM1 net2 Vp net1 GND sky130_fd_pr__nfet_01v8 L=0.15 W=5.3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 net3 Vn net1 GND sky130_fd_pr__nfet_01v8 L=0.15 W=5.3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net1 C GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM11 net2 C VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM12 Dn C VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM13 Dp C VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM14 net3 C VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM15 Dp Dn net3 GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.78 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM16 Dn Dp net2 GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.78 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM17 Dp Dn VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.78 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM18 Dn Dp VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.78 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM20 p Lp GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM21 n Ln GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM22 p n VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM23 n p VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM24 net4 CLK GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM25 net4 CLK VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM26 net5 net4 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM27 net5 net4 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM28 net6 net5 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=8 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM29 net6 net5 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM30 C net6 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM31 C net6 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=32 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM40 net7 n GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM41 net7 n VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM42 net8 net7 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM43 net8 net7 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM44 net9 net8 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=8 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM45 net9 net8 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM46 Outn net9 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM47 Outn net9 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=32 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM48 net10 p GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM49 net10 p VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM50 net11 net10 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM51 net11 net10 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM52 net12 net11 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=8 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM53 net12 net11 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM54 Outp net12 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM55 Outp net12 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=32 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 Lp Dp GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM5 Lp Dp VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 Ln Dn GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM7 Ln Dn VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+**.ends
+.end
diff --git a/xschem/comparator.sym b/xschem/comparator.sym
new file mode 100644
index 0000000..58d1fa1
--- /dev/null
+++ b/xschem/comparator.sym
@@ -0,0 +1,32 @@
+v {xschem version=3.0.0 file_version=1.2}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+T {@symname} -63 -6 0 0 0.3 0.3 {}
+T {@name} 135 -62 0 0 0.2 0.2 {}
+L 4 -130 -50 130 -50 {}
+L 4 -130 50 130 50 {}
+L 4 -130 -50 -130 50 {}
+L 4 130 -50 130 50 {}
+B 5 147.5 -42.5 152.5 -37.5 {name=VDD dir=inout }
+L 7 130 -40 150 -40 {}
+T {VDD} 125 -44 0 1 0.2 0.2 {}
+B 5 147.5 -22.5 152.5 -17.5 {name=GND dir=inout }
+L 7 130 -20 150 -20 {}
+T {GND} 125 -24 0 1 0.2 0.2 {}
+B 5 147.5 -2.5 152.5 2.5 {name=Outn dir=out }
+L 4 130 0 150 0 {}
+T {Outn} 125 -4 0 1 0.2 0.2 {}
+B 5 147.5 17.5 152.5 22.5 {name=CLK dir=inout }
+L 7 130 20 150 20 {}
+T {CLK} 125 16 0 1 0.2 0.2 {}
+B 5 147.5 37.5 152.5 42.5 {name=Outp dir=out }
+L 4 130 40 150 40 {}
+T {Outp} 125 36 0 1 0.2 0.2 {}
+B 5 -152.5 -42.5 -147.5 -37.5 {name=Vp dir=in }
+L 4 -150 -40 -130 -40 {}
+T {Vp} -125 -44 0 0 0.2 0.2 {}
+B 5 -152.5 -22.5 -147.5 -17.5 {name=Vn dir=in }
+L 4 -150 -20 -130 -20 {}
+T {Vn} -125 -24 0 0 0.2 0.2 {}
diff --git a/xschem/comparator_SA.spice b/xschem/comparator_SA.spice
new file mode 100644
index 0000000..5d0578c
--- /dev/null
+++ b/xschem/comparator_SA.spice
@@ -0,0 +1,139 @@
+* SPICE3 file created from comparator_SA.ext - technology: sky130A
+Vdd VDD GND 1.8
+Vn Vn Vp pulse(-10m 10m 1ps 1ps 1ps 4ns 8ns)
+Vcm Vp GND 1.2
+V1 CLK GND pulse(1.8 0 1ps 1ps 1ps 2ns 4ns)
+
+**** begin user architecture code
+
+** opencircuitdesign pdks install
+.lib /usr/local/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
+
+.control
+save ALL
+tran 0.01n 10n
+write comparator_pls.raw
+
+.endc
+**** end user architecture code
+**.ends
+.subckt sky130_fd_pr__nfet_01v8_G6PLX8 a_159_n100# li_n945_n316# a_n221_n74# a_n129_n100#
++ a_63_n100# a_n159_n156# a_n33_n100# VSUBS
+X0 a_n129_n100# a_n159_n156# a_n221_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+X1 a_63_n100# a_n159_n156# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_n33_n100# a_n159_n156# a_n129_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_159_n100# a_n159_n156# a_63_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_NHLLAS a_n63_n153# a_n129_n133# a_63_n133# a_129_n153#
++ a_n221_n96# a_n33_n133# a_n159_n153# a_159_n133# a_33_n153# VSUBS
+X0 a_159_n133# a_129_n153# a_63_n133# VSUBS sky130_fd_pr__nfet_01v8 ad=4.049e+11p pd=3.28e+06u as=4.389e+11p ps=3.32e+06u w=1.33e+06u l=150000u
+X1 a_63_n133# a_33_n153# a_n33_n133# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=4.389e+11p ps=3.32e+06u w=1.33e+06u l=150000u
+X2 a_n129_n133# a_n159_n153# a_n221_n96# VSUBS sky130_fd_pr__nfet_01v8 ad=4.389e+11p pd=3.32e+06u as=4.049e+11p ps=3.28e+06u w=1.33e+06u l=150000u
+X3 a_n33_n133# a_n63_n153# a_n129_n133# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.33e+06u l=150000u
+.ends
+
+.subckt preamp_part1SA m1_n694_236# a_n734_300# li_126_310# m1_924_192# a_80_354#
++ a_976_302# a_n302_940# w_n720_482# a_506_940# li_318_312# li_n66_312# VSUBS
+Xsky130_fd_pr__nfet_01v8_G6PLX8_0 li_318_312# li_n24_n74# li_n66_312# li_n24_n74#
++ li_n24_n74# a_80_354# li_126_310# VSUBS sky130_fd_pr__nfet_01v8_G6PLX8
+Xsky130_fd_pr__nfet_01v8_NHLLAS_0 a_n734_300# m1_n694_236# m1_n694_236# a_n734_300#
++ li_n24_n74# li_n24_n74# a_n734_300# li_n24_n74# a_n734_300# VSUBS sky130_fd_pr__nfet_01v8_NHLLAS
+Xsky130_fd_pr__nfet_01v8_NHLLAS_1 a_976_302# m1_924_192# m1_924_192# a_976_302# li_n24_n74#
++ li_n24_n74# a_976_302# li_n24_n74# a_976_302# VSUBS sky130_fd_pr__nfet_01v8_NHLLAS
+C0 w_n720_482# VSUBS 2.50fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_5233FE a_n15_n76# w_n109_n112# a_n73_n50# a_15_n50#
++ VSUBS
+X0 a_15_n50# a_n15_n76# a_n73_n50# w_n109_n112# sky130_fd_pr__pfet_01v8 ad=1.45e+11p pd=1.58e+06u as=1.45e+11p ps=1.58e+06u w=500000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_F5U58G a_n73_n100# a_15_n100# a_n15_n126# VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AC5E9B w_n161_n200# a_33_n126# a_63_n100# a_n125_n74#
++ a_n33_n100# a_n63_n130# VSUBS
+X0 a_63_n100# a_33_n126# a_n33_n100# w_n161_n200# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n130# a_n125_n74# w_n161_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt SR_latch a_648_848# sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126# sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#
++ a_262_508# VDD w_0_524# GND VSUBS
+Xsky130_fd_pr__nfet_01v8_F5U58G_0 a_648_848# GND sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#
++ VSUBS sky130_fd_pr__nfet_01v8_F5U58G
+Xsky130_fd_pr__nfet_01v8_F5U58G_1 GND a_262_508# sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126#
++ VSUBS sky130_fd_pr__nfet_01v8_F5U58G
+Xsky130_fd_pr__pfet_01v8_AC5E9B_0 w_0_524# a_262_508# VDD VDD a_648_848# a_262_508#
++ VSUBS sky130_fd_pr__pfet_01v8_AC5E9B
+Xsky130_fd_pr__pfet_01v8_AC5E9B_1 w_0_524# a_648_848# VDD VDD a_262_508# a_648_848#
++ VSUBS sky130_fd_pr__pfet_01v8_AC5E9B
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7RYEVP a_n73_n69# a_n15_n89# a_15_n69# VSUBS
+X0 a_15_n69# a_n15_n89# a_n73_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt nmos_1u sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS sky130_fd_pr__nfet_01v8_7RYEVP_0/a_n15_n89#
++ sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#
+Xsky130_fd_pr__nfet_01v8_7RYEVP_0 sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS sky130_fd_pr__nfet_01v8_7RYEVP_0/a_n15_n89#
++ sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69# sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS
++ sky130_fd_pr__nfet_01v8_7RYEVP
+.ends
+
+.subckt pmos_2uf2 a_63_n100# a_33_n130# w_n317_n202# a_n33_n100# a_n63_n130# VSUBS
+X0 a_63_n100# a_33_n130# a_n33_n100# w_n317_n202# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n130# w_n317_n202# w_n317_n202# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.8e+11p ps=2.76e+06u w=1e+06u l=150000u
+.ends
+
+.subckt inv_W1 Vout Vin VDD GND
+Xnmos_1u_0 GND Vin Vout nmos_1u
+Xpmos_2uf2_0 VDD Vin VDD Vout Vin GND pmos_2uf2
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_5C3Z5B a_15_n78# a_n15_n104# a_n73_n78# w_n109_n140#
++ VSUBS
+X0 a_15_n78# a_n15_n104# a_n73_n78# w_n109_n140# sky130_fd_pr__pfet_01v8 ad=2.262e+11p pd=2.14e+06u as=2.262e+11p ps=2.14e+06u w=780000u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KBWVY9 a_15_n78# a_n15_n104# a_n73_n78# VSUBS
+X0 a_15_n78# a_n15_n104# a_n73_n78# VSUBS sky130_fd_pr__nfet_01v8 ad=2.262e+11p pd=2.14e+06u as=2.262e+11p ps=2.14e+06u w=780000u l=150000u
+.ends
+
+.subckt inv_W22 li_200_260# sky130_fd_pr__nfet_01v8_KBWVY9_0/a_n73_n78# sky130_fd_pr__pfet_01v8_5C3Z5B_0/w_n109_n140#
++ Vin VDD sky130_fd_pr__pfet_01v8_5C3Z5B_0/a_15_n78# VSUBS
+Xsky130_fd_pr__pfet_01v8_5C3Z5B_0 sky130_fd_pr__pfet_01v8_5C3Z5B_0/a_15_n78# Vin VDD
++ sky130_fd_pr__pfet_01v8_5C3Z5B_0/w_n109_n140# VSUBS sky130_fd_pr__pfet_01v8_5C3Z5B
+Xsky130_fd_pr__nfet_01v8_KBWVY9_0 li_200_260# Vin sky130_fd_pr__nfet_01v8_KBWVY9_0/a_n73_n78#
++ VSUBS sky130_fd_pr__nfet_01v8_KBWVY9
+.ends
+
+.subckt latch_2SA inv_W22_0/sky130_fd_pr__pfet_01v8_5C3Z5B_0/a_15_n78# w_0_516# inv_W22_0/Vin
++ inv_W22_1/li_200_260# inv_W22_1/sky130_fd_pr__nfet_01v8_KBWVY9_0/a_n73_n78# inv_W22_0/sky130_fd_pr__nfet_01v8_KBWVY9_0/a_n73_n78#
++ inv_W22_0/li_200_260# inv_W22_1/Vin inv_W22_1/VDD inv_W22_1/sky130_fd_pr__pfet_01v8_5C3Z5B_0/a_15_n78#
++ VSUBS
+Xinv_W22_0 inv_W22_0/li_200_260# inv_W22_0/sky130_fd_pr__nfet_01v8_KBWVY9_0/a_n73_n78#
++ w_0_516# inv_W22_0/Vin inv_W22_1/VDD inv_W22_0/sky130_fd_pr__pfet_01v8_5C3Z5B_0/a_15_n78#
++ VSUBS inv_W22
+Xinv_W22_1 inv_W22_1/li_200_260# inv_W22_1/sky130_fd_pr__nfet_01v8_KBWVY9_0/a_n73_n78#
++ w_0_516# inv_W22_1/Vin inv_W22_1/VDD inv_W22_1/sky130_fd_pr__pfet_01v8_5C3Z5B_0/a_15_n78#
++ VSUBS inv_W22
+.ends
+
+
+* Top level circuit comparator_SA
+
+Xpreamp_part1SA_0 fn Vn GND fp CLK Vp CLK VDD CLK GND GND GND preamp_part1SA
+Xsky130_fd_pr__pfet_01v8_5233FE_0 CLK VDD VDD fn GND sky130_fd_pr__pfet_01v8_5233FE
+Xsky130_fd_pr__pfet_01v8_5233FE_1 CLK VDD fp VDD GND sky130_fd_pr__pfet_01v8_5233FE
+Xsky130_fd_pr__pfet_01v8_5233FE_2 CLK VDD VDD Dn GND sky130_fd_pr__pfet_01v8_5233FE
+Xsky130_fd_pr__pfet_01v8_5233FE_3 CLK VDD VDD Dp GND sky130_fd_pr__pfet_01v8_5233FE
+XSR_latch_0 Outp Ln Lp Outn VDD VDD GND GND SR_latch
+Xinv_W1_0 Lp Dp VDD GND inv_W1
+Xinv_W1_1 Ln Dn VDD GND inv_W1
+Xlatch_2SA_0 Dn VDD Dp Dp fp fn Dn Dn VDD Dp GND latch_2SA
+C0 VDD GND 24.40fF
+C1 CLK GND 12.83fF
+.end
+
diff --git a/xschem/comparator_lvs.sch b/xschem/comparator_lvs.sch
new file mode 100644
index 0000000..a1b9ed3
--- /dev/null
+++ b/xschem/comparator_lvs.sch
@@ -0,0 +1,619 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 1380 -610 1380 -570 {
+lab=#net1}
+N 1790 -600 1790 -570 {
+lab=#net1}
+N 1590 -570 1590 -550 {
+lab=#net1}
+N 1590 -490 1590 -460 {
+lab=GND}
+N 1590 -520 1610 -520 {
+lab=GND}
+N 1610 -520 1610 -480 {
+lab=GND}
+N 1590 -480 1610 -480 {
+lab=GND}
+N 1370 -640 1560 -640 {
+lab=GND}
+N 1610 -630 1790 -630 {
+lab=GND}
+N 1180 -1000 1220 -1000 {
+lab=CLK}
+N 1890 -990 1900 -990 {
+lab=CLK}
+N 1890 -990 1890 -950 {
+lab=CLK}
+N 1260 -1000 1280 -1000 {
+lab=VDD}
+N 1280 -1040 1280 -1000 {
+lab=VDD}
+N 1260 -1040 1280 -1040 {
+lab=VDD}
+N 1260 -1040 1260 -1030 {
+lab=VDD}
+N 1460 -1150 1780 -1150 {
+lab=VDD}
+N 1940 -1030 1940 -1020 {
+lab=VDD}
+N 1840 -1140 1840 -1130 {
+lab=VDD}
+N 1360 -1140 1360 -1130 {
+lab=VDD}
+N 1360 -1100 1370 -1100 {
+lab=VDD}
+N 1370 -1100 1380 -1100 {
+lab=VDD}
+N 1380 -1140 1380 -1100 {
+lab=VDD}
+N 1840 -1100 1860 -1100 {
+lab=VDD}
+N 1860 -1140 1860 -1100 {
+lab=VDD}
+N 1940 -990 1960 -990 {
+lab=VDD}
+N 1960 -1030 1960 -990 {
+lab=VDD}
+N 1940 -1030 1960 -1030 {
+lab=VDD}
+N 1510 -520 1550 -520 {
+lab=CLK}
+N 1310 -640 1340 -640 {
+lab=Vn}
+N 1830 -630 1880 -630 {
+lab=Vp}
+N 1510 -1030 1540 -1030 {
+lab=Dp}
+N 1540 -1030 1540 -890 {
+lab=Dp}
+N 1510 -890 1540 -890 {
+lab=Dp}
+N 1630 -1030 1670 -1030 {
+lab=Dn}
+N 1630 -1030 1630 -890 {
+lab=Dn}
+N 1470 -1000 1470 -920 {
+lab=Dn}
+N 1630 -890 1670 -890 {
+lab=Dn}
+N 1710 -1000 1710 -920 {
+lab=Dp}
+N 1470 -860 1470 -840 {
+lab=#net2}
+N 1710 -860 1710 -840 {
+lab=#net3}
+N 1470 -1080 1470 -1060 {
+lab=VDD}
+N 1470 -1080 1710 -1080 {
+lab=VDD}
+N 1710 -1080 1710 -1060 {
+lab=VDD}
+N 1470 -980 1630 -980 {
+lab=Dn}
+N 1540 -940 1710 -940 {
+lab=Dp}
+N 1440 -890 1470 -890 {
+lab=GND}
+N 1710 -890 1730 -890 {
+lab=GND}
+N 1730 -890 1740 -890 {
+lab=GND}
+N 1740 -890 1740 -840 {
+lab=GND}
+N 1580 -1120 1580 -1080 {
+lab=VDD}
+N 1440 -1030 1470 -1030 {
+lab=VDD}
+N 1440 -1080 1440 -1030 {
+lab=VDD}
+N 1710 -1030 1740 -1030 {
+lab=VDD}
+N 1740 -1080 1740 -1030 {
+lab=VDD}
+N 2640 -1110 2670 -1110 {
+lab=outp}
+N 2760 -1110 2800 -1110 {
+lab=outn}
+N 2600 -1080 2600 -1000 {
+lab=outn}
+N 2840 -1080 2840 -1000 {
+lab=outp}
+N 2600 -940 2600 -920 {
+lab=GND}
+N 2600 -920 2840 -920 {
+lab=GND}
+N 2840 -940 2840 -920 {
+lab=GND}
+N 2600 -1160 2600 -1140 {
+lab=VDD}
+N 2600 -1160 2840 -1160 {
+lab=VDD}
+N 2840 -1160 2840 -1140 {
+lab=VDD}
+N 2710 -1200 2710 -1160 {
+lab=VDD}
+N 2570 -1110 2600 -1110 {
+lab=VDD}
+N 2570 -1160 2570 -1110 {
+lab=VDD}
+N 2570 -1160 2600 -1160 {
+lab=VDD}
+N 2840 -1110 2870 -1110 {
+lab=VDD}
+N 2870 -1160 2870 -1110 {
+lab=VDD}
+N 2840 -1160 2870 -1160 {
+lab=VDD}
+N 2530 -970 2560 -970 {
+lab=Ln}
+N 2880 -970 2910 -970 {
+lab=Lp}
+N 2670 -1110 2740 -1040 {
+lab=outp}
+N 2740 -1040 2840 -1040 {
+lab=outp}
+N 2670 -1040 2760 -1110 {
+lab=outn}
+N 2600 -1040 2670 -1040 {
+lab=outn}
+N 2600 -970 2620 -970 {
+lab=GND}
+N 2620 -970 2620 -920 {
+lab=GND}
+N 2820 -970 2840 -970 {
+lab=GND}
+N 2820 -970 2820 -920 {
+lab=GND}
+N 1440 -1100 1440 -1080 {
+lab=VDD}
+N 1440 -1100 1740 -1100 {
+lab=VDD}
+N 1740 -1100 1740 -1080 {
+lab=VDD}
+N 1620 -1150 1620 -1100 {
+lab=VDD}
+N 1590 -630 1610 -630 {
+lab=GND}
+N 1590 -630 1590 -600 {
+lab=GND}
+N 1560 -640 1590 -640 {
+lab=GND}
+N 1590 -640 1590 -630 {
+lab=GND}
+N 1380 -840 1380 -670 {
+lab=#net2}
+N 1420 -840 1470 -840 {
+lab=#net2}
+N 1440 -890 1440 -800 {
+lab=GND}
+N 1440 -800 1440 -640 {
+lab=GND}
+N 1790 -830 1790 -660 {
+lab=#net3}
+N 1710 -830 1790 -830 {
+lab=#net3}
+N 1710 -840 1710 -830 {
+lab=#net3}
+N 1740 -840 1740 -630 {
+lab=GND}
+N 1380 -570 1590 -570 {
+lab=#net1}
+N 1590 -570 1790 -570 {
+lab=#net1}
+N 1380 -840 1420 -840 {
+lab=#net2}
+N 1360 -1150 1460 -1150 {
+lab=VDD}
+N 1360 -1150 1360 -1140 {
+lab=VDD}
+N 1380 -1150 1380 -1140 {
+lab=VDD}
+N 1780 -1150 1860 -1150 {
+lab=VDD}
+N 1860 -1150 1860 -1140 {
+lab=VDD}
+N 1840 -1150 1840 -1140 {
+lab=VDD}
+N 1580 -1150 1580 -1120 {
+lab=VDD}
+N 1360 -1070 1360 -960 {
+lab=Dn}
+N 1360 -960 1470 -960 {
+lab=Dn}
+N 1840 -1070 1840 -980 {
+lab=Dp}
+N 1710 -980 1840 -980 {
+lab=Dp}
+N 1940 -960 1940 -830 {
+lab=#net3}
+N 1790 -830 1940 -830 {
+lab=#net3}
+N 1260 -970 1260 -840 {
+lab=#net2}
+N 1260 -840 1380 -840 {
+lab=#net2}
+N 1280 -1150 1280 -1040 {
+lab=VDD}
+N 1280 -1150 1360 -1150 {
+lab=VDD}
+N 1940 -1150 1940 -1030 {
+lab=VDD}
+N 1860 -1150 1940 -1150 {
+lab=VDD}
+N 1210 -1100 1320 -1100 {
+lab=CLK}
+N 1210 -1100 1210 -1000 {
+lab=CLK}
+N 1780 -1100 1800 -1100 {
+lab=CLK}
+N 2200 -960 2200 -940 {
+lab=Lp}
+N 2140 -1010 2160 -1010 {
+lab=Dp}
+N 2140 -960 2140 -910 {
+lab=Dp}
+N 2140 -910 2160 -910 {
+lab=Dp}
+N 2200 -1050 2200 -1040 {
+lab=VDD}
+N 2200 -1010 2230 -1010 {
+lab=VDD}
+N 2230 -1050 2230 -1010 {
+lab=VDD}
+N 2200 -1050 2230 -1050 {
+lab=VDD}
+N 2200 -870 2200 -860 {
+lab=GND}
+N 2200 -910 2230 -910 {
+lab=GND}
+N 2230 -910 2230 -870 {
+lab=GND}
+N 2200 -870 2230 -870 {
+lab=GND}
+N 2200 -1080 2200 -1050 {
+lab=VDD}
+N 2200 -880 2200 -870 {
+lab=GND}
+N 2200 -980 2200 -960 {
+lab=Lp}
+N 2140 -1010 2140 -960 {
+lab=Dp}
+N 2200 -650 2200 -630 {
+lab=Ln}
+N 2140 -700 2160 -700 {
+lab=Dn}
+N 2140 -650 2140 -600 {
+lab=Dn}
+N 2140 -600 2160 -600 {
+lab=Dn}
+N 2200 -740 2200 -730 {
+lab=VDD}
+N 2200 -700 2230 -700 {
+lab=VDD}
+N 2230 -740 2230 -700 {
+lab=VDD}
+N 2200 -740 2230 -740 {
+lab=VDD}
+N 2200 -560 2200 -550 {
+lab=GND}
+N 2200 -600 2230 -600 {
+lab=GND}
+N 2230 -600 2230 -560 {
+lab=GND}
+N 2200 -560 2230 -560 {
+lab=GND}
+N 2200 -770 2200 -740 {
+lab=VDD}
+N 2200 -570 2200 -560 {
+lab=GND}
+N 2200 -670 2200 -650 {
+lab=Ln}
+N 2140 -700 2140 -650 {
+lab=Dn}
+C {sky130_fd_pr/nfet_01v8.sym} 1360 -640 0 0 {name=M1
+L=0.15
+W=5.3
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 1810 -630 0 1 {name=M2
+L=0.15
+W=5.3
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 1570 -520 0 0 {name=M3
+L=0.15
+W=4
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 1240 -1000 0 0 {name=M11
+L=0.15
+W=0.5
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 1340 -1100 0 0 {name=M12
+L=0.15
+W=0.5
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 1820 -1100 0 0 {name=M13
+L=0.15
+W=0.5
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 1920 -990 0 0 {name=M14
+L=0.15
+W=0.5
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {devices/lab_pin.sym} 1510 -520 0 0 {name=l5 sig_type=std_logic lab=CLK
+}
+C {sky130_fd_pr/nfet_01v8.sym} 1690 -890 0 0 {name=M15
+L=0.15
+W=0.78
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 1490 -890 0 1 {name=M16
+L=0.15
+W=0.78
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 1690 -1030 0 0 {name=M17
+L=0.15
+W=0.78
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 1490 -1030 0 1 {name=M18
+L=0.15
+W=0.78
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {devices/lab_pin.sym} 1470 -940 0 0 {name=l14 sig_type=std_logic lab=Dn}
+C {devices/lab_pin.sym} 1710 -960 2 0 {name=l15 sig_type=std_logic lab=Dp}
+C {sky130_fd_pr/nfet_01v8.sym} 2860 -970 0 1 {name=M20
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 2580 -970 0 0 {name=M21
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 2820 -1110 0 0 {name=M22
+L=0.15
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 2620 -1110 0 1 {name=M23
+L=0.15
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {devices/lab_pin.sym} 2530 -970 0 0 {name=l30 sig_type=std_logic lab=Ln}
+C {devices/lab_pin.sym} 2910 -970 2 0 {name=l31 sig_type=std_logic lab=Lp}
+C {devices/lab_pin.sym} 2840 -1060 2 0 {name=l34 sig_type=std_logic lab=outp}
+C {devices/iopin.sym} 740 -270 0 0 {name=p1 lab=VDD}
+C {devices/iopin.sym} 740 -230 0 0 {name=p2 lab=GND
+}
+C {devices/ipin.sym} 1870 -630 2 0 {name=p3 lab=Vp
+}
+C {devices/ipin.sym} 1320 -640 0 0 {name=p4 lab=Vn}
+C {devices/iopin.sym} 790 -330 2 0 {name=p5 lab=CLK}
+C {devices/lab_pin.sym} 1610 -1150 1 0 {name=l9 sig_type=std_logic lab=VDD}
+C {devices/lab_pin.sym} 2710 -1200 1 0 {name=l27 sig_type=std_logic lab=VDD}
+C {devices/lab_pin.sym} 1590 -460 3 0 {name=l10 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 2690 -920 3 0 {name=l19 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 1590 -600 0 0 {name=l1 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 2600 -1060 2 0 {name=l18 sig_type=std_logic lab=outn}
+C {sky130_fd_pr/nfet_01v8.sym} 2180 -910 0 0 {name=M4
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 2180 -1010 0 0 {name=M5
+L=0.15
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 2180 -600 0 0 {name=M6
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 2180 -700 0 0 {name=M7
+L=0.15
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {devices/lab_pin.sym} 2140 -960 2 0 {name=l4 sig_type=std_logic lab=Dp}
+C {devices/lab_pin.sym} 2140 -650 0 0 {name=l6 sig_type=std_logic lab=Dn}
+C {devices/lab_pin.sym} 2200 -650 2 0 {name=l7 sig_type=std_logic lab=Ln}
+C {devices/lab_pin.sym} 2200 -960 2 0 {name=l11 sig_type=std_logic lab=Lp}
+C {devices/lab_pin.sym} 2200 -1080 1 0 {name=l12 sig_type=std_logic lab=VDD}
+C {devices/lab_pin.sym} 2200 -770 1 0 {name=l13 sig_type=std_logic lab=VDD}
+C {devices/lab_pin.sym} 2200 -550 0 0 {name=l16 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 2200 -860 0 0 {name=l26 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 1180 -1000 0 0 {name=l2 sig_type=std_logic lab=CLK
+}
+C {devices/lab_pin.sym} 1890 -950 0 0 {name=l3 sig_type=std_logic lab=CLK
+}
+C {devices/lab_pin.sym} 1780 -1100 0 0 {name=l8 sig_type=std_logic lab=CLK
+}
+C {devices/iopin.sym} 850 -270 0 0 {name=p6 lab=outn}
+C {devices/iopin.sym} 850 -230 0 0 {name=p7 lab=outp
+}
diff --git a/xschem/comparator_lvs.spice b/xschem/comparator_lvs.spice
new file mode 100644
index 0000000..a7b7d6a
--- /dev/null
+++ b/xschem/comparator_lvs.spice
@@ -0,0 +1,68 @@
+** sch_path: /home/krishna/Strong_Arm_MPW6/xschem/comparator_lvs.sch
+.subckt comparator_lvs VDD GND Vp Vn CLK outn outp
+.iopin VDD
+.iopin GND
+.ipin Vp
+.ipin Vn
+.iopin CLK
+.iopin outn
+.iopin outp
+XM1 net2 Vn net1 GND sky130_fd_pr__nfet_01v8 L=0.15 W=5.3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 net3 Vp net1 GND sky130_fd_pr__nfet_01v8 L=0.15 W=5.3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net1 CLK GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM11 net2 CLK VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM12 Dn CLK VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM13 Dp CLK VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM14 net3 CLK VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM15 Dp Dn net3 GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.78 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM16 Dn Dp net2 GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.78 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM17 Dp Dn VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.78 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM18 Dn Dp VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.78 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM20 outp Lp GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM21 outn Ln GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM22 outp outn VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM23 outn outp VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 Lp Dp GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM5 Lp Dp VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 Ln Dn GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM7 Ln Dn VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+.end
diff --git a/xschem/comparator_tb.sch b/xschem/comparator_tb.sch
new file mode 100644
index 0000000..2ef6464
--- /dev/null
+++ b/xschem/comparator_tb.sch
@@ -0,0 +1,84 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 800 -820 800 -800 {
+lab=GND}
+N 800 -910 800 -880 {
+lab=VDD}
+N 1010 -710 1010 -690 {
+lab=Vp}
+N 1010 -790 1010 -770 {
+lab=Vn}
+N 1010 -690 1100 -690 {
+lab=Vp}
+N 1100 -690 1100 -670 {
+lab=Vp}
+N 1100 -610 1100 -590 {
+lab=GND}
+N 1100 -690 1170 -690 {
+lab=Vp}
+N 1170 -790 1170 -690 {
+lab=Vp}
+N 910 -910 910 -880 {
+lab=CLK}
+N 1340 -990 1400 -990 {
+lab=Vp}
+N 1340 -970 1400 -970 {
+lab=Vn}
+N 910 -820 910 -790 {
+lab=GND}
+N 1330 -710 1330 -670 {
+lab=GND}
+N 1330 -810 1330 -770 {
+lab=GND}
+N 1700 -990 1790 -990 {
+lab=VDD}
+N 1700 -970 1750 -970 {
+lab=GND}
+N 1700 -930 1730 -930 {
+lab=CLK}
+N 1700 -950 1740 -950 {
+lab=CLK}
+N 1700 -910 1740 -910 {
+lab=op}
+C {devices/TT_models.sym} 950 -1180 0 0 {name=TT_MODELS
+only_toplevel=true
+format="tcleval( @value )"
+value="
+** opencircuitdesign pdks install
+.lib /usr/local/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
+
+"
+spice_ignore=falsename=s1 only_toplevel=false value=blabla}
+C {devices/vsource.sym} 800 -850 0 0 {name=Vdd value=1.8}
+C {devices/vsource.sym} 1010 -740 0 0 {name=Vn value="pulse(-10m 10m 1ps 1ps 1ps 4ns 8ns)"}
+C {devices/lab_pin.sym} 1010 -790 0 0 {name=l24 sig_type=std_logic lab=Vn}
+C {devices/vsource.sym} 1100 -640 0 0 {name=Vcm value=1.2}
+C {devices/lab_pin.sym} 1170 -790 2 0 {name=l25 sig_type=std_logic lab=Vp}
+C {devices/code_shown.sym} 2030 -770 0 0 {name=SPICE only_toplevel=false value=".tran 0.01n 50n
+.save all"}
+C {devices/vsource.sym} 910 -850 0 0 {name=V1 value="pulse(1.8 0 1ps 1ps 1ps 2ns 4ns)"}
+C {devices/lab_pin.sym} 910 -910 0 0 {name=l22 sig_type=std_logic lab=CLK}
+C {comparator.sym} 1550 -950 0 0 {name=x1}
+C {devices/lab_pin.sym} 1340 -970 0 0 {name=l1 sig_type=std_logic lab=Vn}
+C {devices/lab_pin.sym} 1340 -990 0 0 {name=l2 sig_type=std_logic lab=Vp}
+C {devices/gnd.sym} 1330 -670 0 0 {name=l3 lab=GND}
+C {devices/lab_pin.sym} 1330 -810 2 0 {name=l4 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 1100 -590 2 0 {name=l5 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 800 -800 2 0 {name=l7 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 910 -790 2 0 {name=l8 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 800 -910 0 0 {name=l9 sig_type=std_logic lab=VDD}
+C {devices/lab_pin.sym} 1790 -990 2 0 {name=l10 sig_type=std_logic lab=VDD}
+C {devices/lab_pin.sym} 1750 -970 2 0 {name=l11 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 1730 -930 2 0 {name=l12 sig_type=std_logic lab=CLK}
+C {devices/res.sym} 1330 -740 0 0 {name=R1
+value=0
+footprint=1206
+device=resistor
+m=1}
+C {devices/lab_pin.sym} 1740 -950 2 0 {name=l6 sig_type=std_logic lab=on}
+C {devices/lab_pin.sym} 1740 -910 2 0 {name=l13 sig_type=std_logic lab=op
+}
diff --git a/xschem/comparator_tb.spice b/xschem/comparator_tb.spice
new file mode 100644
index 0000000..8902988
--- /dev/null
+++ b/xschem/comparator_tb.spice
@@ -0,0 +1,178 @@
+** sch_path: /home/krishna/Strong_Arm_MPW6/xschem/comparator_tb.sch
+**.subckt comparator_tb
+Vdd VDD GND 1.8
+Vn Vn Vp pulse(-10m 10m 1ps 1ps 1ps 4ns 8ns)
+Vcm Vp GND 1.2
+V1 CLK GND pulse(1.8 0 1ps 1ps 1ps 2ns 4ns)
+x1 VDD GND on CLK op Vp Vn comparator
+R1 GND GND 0 m=1
+**** begin user architecture code
+
+** opencircuitdesign pdks install
+.lib /usr/local/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
+
+.control
+save ALL @m.x1.xm3.msky130_fd_pr__nfet_01v8[id]
+tran 0.01n 10n
+write comparator_tb.raw
+set filetype=ascii
+run
+meas tran area INTEG @m.x1.xm3.msky130_fd_pr__nfet_01v8[id] from=0 to=4ns
+let ecbit = area*1.8
+let vdiff= v(op)
+meas tran delaytime WHEN vdiff = 0.9 FALL=LAST
+meas tran clk WHEN v(clk) = 0.9 RISE=2
+let clkdelay=clk-6ns
+#meas tran tdiff TRIG AT=2ns TARG vdiff VAL=0.9 CROSS=1
+let compdelay=delaytime-6ns-clkdelay-0.385ns
+let tdelay=delaytime-6ns
+write output_comptran.txt delaytime clkdelay tdelay
+print clkdelay tdelay compdelay ecbit
+.endc
+**** end user architecture code
+**.ends
+
+* expanding symbol: comparator.sym # of pins=7
+** sym_path: /home/krishna/Strong_Arm_MPW6/xschem/comparator.sym
+** sch_path: /home/krishna/Strong_Arm_MPW6/xschem/comparator.sch
+.subckt comparator VDD GND Outn CLK Outp Vp Vn
+*.iopin VDD
+*.iopin GND
+*.ipin Vn
+*.ipin Vp
+*.iopin CLK
+*.opin Outn
+*.opin Outp
+XM1 net2 Vp net1 GND sky130_fd_pr__nfet_01v8 L=0.15 W=5.3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 net3 Vn net1 GND sky130_fd_pr__nfet_01v8 L=0.15 W=5.3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net1 C GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM11 net2 C VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM12 Dn C VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM13 Dp C VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM14 net3 C VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM15 Dp Dn net3 GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.78 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM16 Dn Dp net2 GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.78 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM17 Dp Dn VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.78 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM18 Dn Dp VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.78 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM20 p Lp GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM21 n Ln GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM22 p n VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM23 n p VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM24 net4 CLK GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM25 net4 CLK VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM26 net5 net4 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM27 net5 net4 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM28 net6 net5 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=8 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM29 net6 net5 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM30 C net6 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM31 C net6 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=32 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM40 net7 n GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM41 net7 n VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM42 net8 net7 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM43 net8 net7 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM44 net9 net8 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=8 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM45 net9 net8 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM46 Outn net9 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM47 Outn net9 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=32 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM48 net10 p GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM49 net10 p VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM50 net11 net10 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM51 net11 net10 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM52 net12 net11 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=8 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM53 net12 net11 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM54 Outp net12 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM55 Outp net12 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=32 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 Lp Dp GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM5 Lp Dp VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 Ln Dn GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM7 Ln Dn VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+.GLOBAL GND
+.end
diff --git a/xschem/user_analog_project_wrapper.sch b/xschem/user_analog_project_wrapper.sch
new file mode 100644
index 0000000..e7c4b6a
--- /dev/null
+++ b/xschem/user_analog_project_wrapper.sch
@@ -0,0 +1,394 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 4030 -190 4100 -190 {
+lab=vccd1}
+N 4030 -170 4100 -170 {
+lab=vssa1}
+N 4030 -150 4100 -150 {
+lab=io_analog[3]}
+N 4030 -110 4100 -110 {
+lab=io_analog[2]}
+N 4030 -130 4100 -130 {
+lab=io_analog[8]}
+N 3530 500 3580 500 {
+lab=io_clamp_high[2:1]}
+N 3530 540 3580 540 {
+lab=io_clamp_high[2:1]}
+N 4010 -440 4010 -420 {
+lab=#net1}
+N 3950 -490 3970 -490 {
+lab=#net2}
+N 3950 -440 3950 -390 {
+lab=#net2}
+N 3950 -390 3970 -390 {
+lab=#net2}
+N 4010 -530 4010 -520 {
+lab=vccd1}
+N 4010 -490 4040 -490 {
+lab=vccd1}
+N 4040 -530 4040 -490 {
+lab=vccd1}
+N 4010 -530 4040 -530 {
+lab=vccd1}
+N 4010 -350 4010 -340 {
+lab=vssa1}
+N 4010 -390 4040 -390 {
+lab=vssa1}
+N 4040 -390 4040 -350 {
+lab=vssa1}
+N 4010 -350 4040 -350 {
+lab=vssa1}
+N 4170 -440 4170 -420 {
+lab=#net3}
+N 4110 -490 4130 -490 {
+lab=#net1}
+N 4110 -440 4110 -390 {
+lab=#net1}
+N 4110 -390 4130 -390 {
+lab=#net1}
+N 4170 -530 4170 -520 {
+lab=vccd1}
+N 4170 -490 4200 -490 {
+lab=vccd1}
+N 4200 -530 4200 -490 {
+lab=vccd1}
+N 4170 -530 4200 -530 {
+lab=vccd1}
+N 4170 -350 4170 -340 {
+lab=vssa1}
+N 4170 -390 4200 -390 {
+lab=vssa1}
+N 4200 -390 4200 -350 {
+lab=vssa1}
+N 4170 -350 4200 -350 {
+lab=vssa1}
+N 4330 -440 4330 -420 {
+lab=#net4}
+N 4270 -490 4290 -490 {
+lab=#net3}
+N 4270 -440 4270 -390 {
+lab=#net3}
+N 4270 -390 4290 -390 {
+lab=#net3}
+N 4330 -530 4330 -520 {
+lab=vccd1}
+N 4330 -490 4360 -490 {
+lab=vccd1}
+N 4360 -530 4360 -490 {
+lab=vccd1}
+N 4330 -530 4360 -530 {
+lab=vccd1}
+N 4330 -350 4330 -340 {
+lab=vssa1}
+N 4330 -390 4360 -390 {
+lab=vssa1}
+N 4360 -390 4360 -350 {
+lab=vssa1}
+N 4330 -350 4360 -350 {
+lab=vssa1}
+N 4480 -440 4480 -420 {
+lab=io_analog[0]}
+N 4420 -490 4440 -490 {
+lab=#net4}
+N 4420 -440 4420 -390 {
+lab=#net4}
+N 4420 -390 4440 -390 {
+lab=#net4}
+N 4480 -530 4480 -520 {
+lab=vccd1}
+N 4480 -490 4510 -490 {
+lab=vccd1}
+N 4510 -530 4510 -490 {
+lab=vccd1}
+N 4480 -530 4510 -530 {
+lab=vccd1}
+N 4480 -350 4480 -340 {
+lab=vssa1}
+N 4480 -390 4510 -390 {
+lab=vssa1}
+N 4510 -390 4510 -350 {
+lab=vssa1}
+N 4480 -350 4510 -350 {
+lab=vssa1}
+N 4010 -440 4110 -440 {
+lab=#net1}
+N 4170 -440 4270 -440 {
+lab=#net3}
+N 4330 -440 4420 -440 {
+lab=#net4}
+N 4480 -440 4570 -440 {
+lab=io_analog[0]}
+N 3920 -440 3950 -440 {
+lab=#net2}
+N 4010 -560 4010 -530 {
+lab=vccd1}
+N 4330 -560 4480 -560 {
+lab=vccd1}
+N 4480 -560 4480 -530 {
+lab=vccd1}
+N 4170 -560 4170 -530 {
+lab=vccd1}
+N 4330 -560 4330 -530 {
+lab=vccd1}
+N 4010 -360 4010 -350 {
+lab=vssa1}
+N 4170 -360 4170 -350 {
+lab=vssa1}
+N 4330 -360 4330 -350 {
+lab=vssa1}
+N 4480 -360 4480 -350 {
+lab=vssa1}
+N 4010 -460 4010 -440 {
+lab=#net1}
+N 4110 -490 4110 -440 {
+lab=#net1}
+N 4170 -460 4170 -440 {
+lab=#net3}
+N 4270 -490 4270 -440 {
+lab=#net3}
+N 4330 -460 4330 -440 {
+lab=#net4}
+N 4420 -490 4420 -440 {
+lab=#net4}
+N 4480 -460 4480 -440 {
+lab=io_analog[0]}
+N 3950 -490 3950 -440 {
+lab=#net2}
+N 4010 -560 4170 -560 {
+lab=vccd1}
+N 4170 -560 4330 -560 {
+lab=vccd1}
+N 4010 -340 4480 -340 {
+lab=vssa1}
+N 3760 -440 3760 -420 {
+lab=#net2}
+N 3700 -490 3720 -490 {
+lab=io_analog[8]}
+N 3700 -440 3700 -390 {
+lab=io_analog[8]}
+N 3700 -390 3720 -390 {
+lab=io_analog[8]}
+N 3760 -530 3760 -520 {
+lab=vccd1}
+N 3760 -490 3790 -490 {
+lab=vccd1}
+N 3790 -530 3790 -490 {
+lab=vccd1}
+N 3760 -530 3790 -530 {
+lab=vccd1}
+N 3760 -350 3760 -340 {
+lab=vssa1}
+N 3760 -390 3790 -390 {
+lab=vssa1}
+N 3790 -390 3790 -350 {
+lab=vssa1}
+N 3760 -350 3790 -350 {
+lab=vssa1}
+N 3670 -440 3700 -440 {
+lab=io_analog[8]}
+N 3760 -560 3760 -530 {
+lab=vccd1}
+N 3760 -360 3760 -350 {
+lab=vssa1}
+N 3760 -460 3760 -440 {
+lab=#net2}
+N 3700 -490 3700 -440 {
+lab=io_analog[8]}
+N 3760 -440 3920 -440 {
+lab=#net2}
+N 3760 -560 4010 -560 {
+lab=vccd1}
+N 3760 -340 4010 -340 {
+lab=vssa1}
+C {devices/iopin.sym} 3240 -470 0 0 {name=p1 lab=vdda1}
+C {devices/iopin.sym} 3240 -440 0 0 {name=p2 lab=vdda2}
+C {devices/iopin.sym} 3240 -410 0 0 {name=p3 lab=vssa1}
+C {devices/iopin.sym} 3240 -380 0 0 {name=p4 lab=vssa2}
+C {devices/iopin.sym} 3240 -350 0 0 {name=p5 lab=vccd1}
+C {devices/iopin.sym} 3240 -320 0 0 {name=p6 lab=vccd2}
+C {devices/iopin.sym} 3240 -290 0 0 {name=p7 lab=vssd1}
+C {devices/iopin.sym} 3240 -260 0 0 {name=p8 lab=vssd2}
+C {devices/ipin.sym} 3290 -190 0 0 {name=p9 lab=wb_clk_i}
+C {devices/ipin.sym} 3290 -160 0 0 {name=p10 lab=wb_rst_i}
+C {devices/ipin.sym} 3290 -130 0 0 {name=p11 lab=wbs_stb_i}
+C {devices/ipin.sym} 3290 -100 0 0 {name=p12 lab=wbs_cyc_i}
+C {devices/ipin.sym} 3290 -70 0 0 {name=p13 lab=wbs_we_i}
+C {devices/ipin.sym} 3290 -40 0 0 {name=p14 lab=wbs_sel_i[3:0]}
+C {devices/ipin.sym} 3290 -10 0 0 {name=p15 lab=wbs_dat_i[31:0]}
+C {devices/ipin.sym} 3290 20 0 0 {name=p16 lab=wbs_adr_i[31:0]}
+C {devices/opin.sym} 3280 80 0 0 {name=p17 lab=wbs_ack_o}
+C {devices/opin.sym} 3280 110 0 0 {name=p18 lab=wbs_dat_o[31:0]}
+C {devices/ipin.sym} 3290 150 0 0 {name=p19 lab=la_data_in[127:0]}
+C {devices/opin.sym} 3280 180 0 0 {name=p20 lab=la_data_out[127:0]}
+C {devices/ipin.sym} 3290 260 0 0 {name=p21 lab=io_in[26:0]}
+C {devices/ipin.sym} 3290 290 0 0 {name=p22 lab=io_in_3v3[26:0]}
+C {devices/ipin.sym} 3280 570 0 0 {name=p23 lab=user_clock2}
+C {devices/opin.sym} 3280 320 0 0 {name=p24 lab=io_out[26:0]}
+C {devices/opin.sym} 3280 350 0 0 {name=p25 lab=io_oeb[26:0]}
+C {devices/iopin.sym} 3250 410 0 0 {name=p26 lab=gpio_analog[17:0]}
+C {devices/iopin.sym} 3250 440 0 0 {name=p27 lab=gpio_noesd[17:0]}
+C {devices/iopin.sym} 3250 470 0 0 {name=p29 lab=io_analog[10:0]}
+C {devices/iopin.sym} 3250 500 0 0 {name=p30 lab=io_clamp_high[2:0]}
+C {devices/iopin.sym} 3250 530 0 0 {name=p31 lab=io_clamp_low[2:0]}
+C {devices/opin.sym} 3270 600 0 0 {name=p32 lab=user_irq[2:0]}
+C {devices/ipin.sym} 3290 210 0 0 {name=p28 lab=la_oenb[127:0]}
+C {comparator.sym} 3880 -150 0 0 {name=x1}
+C {devices/lab_pin.sym} 4100 -190 2 0 {name=l1 sig_type=std_logic lab=vccd1}
+C {devices/lab_pin.sym} 4100 -170 0 1 {name=l2 sig_type=std_logic lab=vssa1}
+C {devices/lab_pin.sym} 4100 -150 2 0 {name=l3 sig_type=std_logic lab=io_analog[3]}
+C {devices/lab_pin.sym} 4100 -110 2 0 {name=l4 sig_type=std_logic lab=io_analog[2]}
+C {devices/lab_pin.sym} 4100 -130 2 0 {name=l5 sig_type=std_logic lab=io_analog[8]}
+C {devices/lab_pin.sym} 3730 -190 0 0 {name=l7 sig_type=std_logic lab=io_analog[5]}
+C {devices/lab_pin.sym} 3730 -170 0 0 {name=l8 sig_type=std_logic lab=io_analog[6]}
+C {devices/lab_pin.sym} 3530 500 0 0 {name=l9 sig_type=std_logic lab=vccd1}
+C {devices/lab_pin.sym} 3530 540 2 1 {name=l10 sig_type=std_logic lab=vssa1}
+C {devices/lab_pin.sym} 3580 500 2 0 {name=l11 sig_type=std_logic lab=io_clamp_high[2:1]}
+C {devices/lab_pin.sym} 3580 540 2 0 {name=l12 sig_type=std_logic lab=io_clamp_high[2:1]}
+C {sky130_fd_pr/nfet_01v8.sym} 3990 -390 0 0 {name=M40
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 3990 -490 0 0 {name=M41
+L=0.15
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 4150 -390 0 0 {name=M42
+L=0.15
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 4150 -490 0 0 {name=M43
+L=0.15
+W=4
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 4310 -390 0 0 {name=M44
+L=0.15
+W=8
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 4310 -490 0 0 {name=M45
+L=0.15
+W=16
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 4460 -390 0 0 {name=M46
+L=0.15
+W=16
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 4460 -490 0 0 {name=M47
+L=0.15
+W=32
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 3740 -390 0 0 {name=M1
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 3740 -490 0 0 {name=M2
+L=0.15
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {devices/lab_pin.sym} 3670 -440 0 0 {name=l6 sig_type=std_logic lab=io_analog[8]}
+C {devices/lab_pin.sym} 4570 -440 2 0 {name=l13 sig_type=std_logic lab=io_analog[1]}
+C {devices/lab_pin.sym} 4200 -560 1 0 {name=l14 sig_type=std_logic lab=vccd1}
+C {devices/lab_pin.sym} 4220 -340 1 1 {name=l15 sig_type=std_logic lab=vssa1}
diff --git a/xschem/user_analog_project_wrapper.spice b/xschem/user_analog_project_wrapper.spice
new file mode 100644
index 0000000..2709117
--- /dev/null
+++ b/xschem/user_analog_project_wrapper.spice
@@ -0,0 +1,238 @@
+** sch_path: /home/krishna/Strong_Arm_MPW6/xschem/user_analog_project_wrapper.sch
+**.subckt user_analog_project_wrapper vdda1 vdda2 vssa1 vssa2 vccd1 vccd2 vssd1 vssd2 wb_clk_i
+*+ wb_rst_i wbs_stb_i wbs_cyc_i wbs_we_i wbs_sel_i[3],wbs_sel_i[2],wbs_sel_i[1],wbs_sel_i[0]
+*+ wbs_dat_i[31],wbs_dat_i[30],wbs_dat_i[29],wbs_dat_i[28],wbs_dat_i[27],wbs_dat_i[26],wbs_dat_i[25],wbs_dat_i[24],wbs_dat_i[23],wbs_dat_i[22],wbs_dat_i[21],wbs_dat_i[20],wbs_dat_i[19],wbs_dat_i[18],wbs_dat_i[17],wbs_dat_i[16],wbs_dat_i[15],wbs_dat_i[14],wbs_dat_i[13],wbs_dat_i[12],wbs_dat_i[11],wbs_dat_i[10],wbs_dat_i[9],wbs_dat_i[8],wbs_dat_i[7],wbs_dat_i[6],wbs_dat_i[5],wbs_dat_i[4],wbs_dat_i[3],wbs_dat_i[2],wbs_dat_i[1],wbs_dat_i[0]
+*+ wbs_adr_i[31],wbs_adr_i[30],wbs_adr_i[29],wbs_adr_i[28],wbs_adr_i[27],wbs_adr_i[26],wbs_adr_i[25],wbs_adr_i[24],wbs_adr_i[23],wbs_adr_i[22],wbs_adr_i[21],wbs_adr_i[20],wbs_adr_i[19],wbs_adr_i[18],wbs_adr_i[17],wbs_adr_i[16],wbs_adr_i[15],wbs_adr_i[14],wbs_adr_i[13],wbs_adr_i[12],wbs_adr_i[11],wbs_adr_i[10],wbs_adr_i[9],wbs_adr_i[8],wbs_adr_i[7],wbs_adr_i[6],wbs_adr_i[5],wbs_adr_i[4],wbs_adr_i[3],wbs_adr_i[2],wbs_adr_i[1],wbs_adr_i[0] wbs_ack_o
+*+ wbs_dat_o[31],wbs_dat_o[30],wbs_dat_o[29],wbs_dat_o[28],wbs_dat_o[27],wbs_dat_o[26],wbs_dat_o[25],wbs_dat_o[24],wbs_dat_o[23],wbs_dat_o[22],wbs_dat_o[21],wbs_dat_o[20],wbs_dat_o[19],wbs_dat_o[18],wbs_dat_o[17],wbs_dat_o[16],wbs_dat_o[15],wbs_dat_o[14],wbs_dat_o[13],wbs_dat_o[12],wbs_dat_o[11],wbs_dat_o[10],wbs_dat_o[9],wbs_dat_o[8],wbs_dat_o[7],wbs_dat_o[6],wbs_dat_o[5],wbs_dat_o[4],wbs_dat_o[3],wbs_dat_o[2],wbs_dat_o[1],wbs_dat_o[0]
+*+ la_data_in[127],la_data_in[126],la_data_in[125],la_data_in[124],la_data_in[123],la_data_in[122],la_data_in[121],la_data_in[120],la_data_in[119],la_data_in[118],la_data_in[117],la_data_in[116],la_data_in[115],la_data_in[114],la_data_in[113],la_data_in[112],la_data_in[111],la_data_in[110],la_data_in[109],la_data_in[108],la_data_in[107],la_data_in[106],la_data_in[105],la_data_in[104],la_data_in[103],la_data_in[102],la_data_in[101],la_data_in[100],la_data_in[99],la_data_in[98],la_data_in[97],la_data_in[96],la_data_in[95],la_data_in[94],la_data_in[93],la_data_in[92],la_data_in[91],la_data_in[90],la_data_in[89],la_data_in[88],la_data_in[87],la_data_in[86],la_data_in[85],la_data_in[84],la_data_in[83],la_data_in[82],la_data_in[81],la_data_in[80],la_data_in[79],la_data_in[78],la_data_in[77],la_data_in[76],la_data_in[75],la_data_in[74],la_data_in[73],la_data_in[72],la_data_in[71],la_data_in[70],la_data_in[69],la_data_in[68],la_data_in[67],la_data_in[66],la_data_in[65],la_data_in[64],la_data_in[63],la_data_in[62],la_data_in[61],la_data_in[60],la_data_in[59],la_data_in[58],la_data_in[57],la_data_in[56],la_data_in[55],la_data_in[54],la_data_in[53],la_data_in[52],la_data_in[51],la_data_in[50],la_data_in[49],la_data_in[48],la_data_in[47],la_data_in[46],la_data_in[45],la_data_in[44],la_data_in[43],la_data_in[42],la_data_in[41],la_data_in[40],la_data_in[39],la_data_in[38],la_data_in[37],la_data_in[36],la_data_in[35],la_data_in[34],la_data_in[33],la_data_in[32],la_data_in[31],la_data_in[30],la_data_in[29],la_data_in[28],la_data_in[27],la_data_in[26],la_data_in[25],la_data_in[24],la_data_in[23],la_data_in[22],la_data_in[21],la_data_in[20],la_data_in[19],la_data_in[18],la_data_in[17],la_data_in[16],la_data_in[15],la_data_in[14],la_data_in[13],la_data_in[12],la_data_in[11],la_data_in[10],la_data_in[9],la_data_in[8],la_data_in[7],la_data_in[6],la_data_in[5],la_data_in[4],la_data_in[3],la_data_in[2],la_data_in[1],la_data_in[0]
+*+ la_data_out[127],la_data_out[126],la_data_out[125],la_data_out[124],la_data_out[123],la_data_out[122],la_data_out[121],la_data_out[120],la_data_out[119],la_data_out[118],la_data_out[117],la_data_out[116],la_data_out[115],la_data_out[114],la_data_out[113],la_data_out[112],la_data_out[111],la_data_out[110],la_data_out[109],la_data_out[108],la_data_out[107],la_data_out[106],la_data_out[105],la_data_out[104],la_data_out[103],la_data_out[102],la_data_out[101],la_data_out[100],la_data_out[99],la_data_out[98],la_data_out[97],la_data_out[96],la_data_out[95],la_data_out[94],la_data_out[93],la_data_out[92],la_data_out[91],la_data_out[90],la_data_out[89],la_data_out[88],la_data_out[87],la_data_out[86],la_data_out[85],la_data_out[84],la_data_out[83],la_data_out[82],la_data_out[81],la_data_out[80],la_data_out[79],la_data_out[78],la_data_out[77],la_data_out[76],la_data_out[75],la_data_out[74],la_data_out[73],la_data_out[72],la_data_out[71],la_data_out[70],la_data_out[69],la_data_out[68],la_data_out[67],la_data_out[66],la_data_out[65],la_data_out[64],la_data_out[63],la_data_out[62],la_data_out[61],la_data_out[60],la_data_out[59],la_data_out[58],la_data_out[57],la_data_out[56],la_data_out[55],la_data_out[54],la_data_out[53],la_data_out[52],la_data_out[51],la_data_out[50],la_data_out[49],la_data_out[48],la_data_out[47],la_data_out[46],la_data_out[45],la_data_out[44],la_data_out[43],la_data_out[42],la_data_out[41],la_data_out[40],la_data_out[39],la_data_out[38],la_data_out[37],la_data_out[36],la_data_out[35],la_data_out[34],la_data_out[33],la_data_out[32],la_data_out[31],la_data_out[30],la_data_out[29],la_data_out[28],la_data_out[27],la_data_out[26],la_data_out[25],la_data_out[24],la_data_out[23],la_data_out[22],la_data_out[21],la_data_out[20],la_data_out[19],la_data_out[18],la_data_out[17],la_data_out[16],la_data_out[15],la_data_out[14],la_data_out[13],la_data_out[12],la_data_out[11],la_data_out[10],la_data_out[9],la_data_out[8],la_data_out[7],la_data_out[6],la_data_out[5],la_data_out[4],la_data_out[3],la_data_out[2],la_data_out[1],la_data_out[0]
+*+ io_in[26],io_in[25],io_in[24],io_in[23],io_in[22],io_in[21],io_in[20],io_in[19],io_in[18],io_in[17],io_in[16],io_in[15],io_in[14],io_in[13],io_in[12],io_in[11],io_in[10],io_in[9],io_in[8],io_in[7],io_in[6],io_in[5],io_in[4],io_in[3],io_in[2],io_in[1],io_in[0]
+*+ io_in_3v3[26],io_in_3v3[25],io_in_3v3[24],io_in_3v3[23],io_in_3v3[22],io_in_3v3[21],io_in_3v3[20],io_in_3v3[19],io_in_3v3[18],io_in_3v3[17],io_in_3v3[16],io_in_3v3[15],io_in_3v3[14],io_in_3v3[13],io_in_3v3[12],io_in_3v3[11],io_in_3v3[10],io_in_3v3[9],io_in_3v3[8],io_in_3v3[7],io_in_3v3[6],io_in_3v3[5],io_in_3v3[4],io_in_3v3[3],io_in_3v3[2],io_in_3v3[1],io_in_3v3[0] user_clock2
+*+ io_out[26],io_out[25],io_out[24],io_out[23],io_out[22],io_out[21],io_out[20],io_out[19],io_out[18],io_out[17],io_out[16],io_out[15],io_out[14],io_out[13],io_out[12],io_out[11],io_out[10],io_out[9],io_out[8],io_out[7],io_out[6],io_out[5],io_out[4],io_out[3],io_out[2],io_out[1],io_out[0]
+*+ io_oeb[26],io_oeb[25],io_oeb[24],io_oeb[23],io_oeb[22],io_oeb[21],io_oeb[20],io_oeb[19],io_oeb[18],io_oeb[17],io_oeb[16],io_oeb[15],io_oeb[14],io_oeb[13],io_oeb[12],io_oeb[11],io_oeb[10],io_oeb[9],io_oeb[8],io_oeb[7],io_oeb[6],io_oeb[5],io_oeb[4],io_oeb[3],io_oeb[2],io_oeb[1],io_oeb[0]
+*+ gpio_analog[17],gpio_analog[16],gpio_analog[15],gpio_analog[14],gpio_analog[13],gpio_analog[12],gpio_analog[11],gpio_analog[10],gpio_analog[9],gpio_analog[8],gpio_analog[7],gpio_analog[6],gpio_analog[5],gpio_analog[4],gpio_analog[3],gpio_analog[2],gpio_analog[1],gpio_analog[0]
+*+ gpio_noesd[17],gpio_noesd[16],gpio_noesd[15],gpio_noesd[14],gpio_noesd[13],gpio_noesd[12],gpio_noesd[11],gpio_noesd[10],gpio_noesd[9],gpio_noesd[8],gpio_noesd[7],gpio_noesd[6],gpio_noesd[5],gpio_noesd[4],gpio_noesd[3],gpio_noesd[2],gpio_noesd[1],gpio_noesd[0]
+*+ io_analog[10],io_analog[9],io_analog[8],io_analog[7],io_analog[6],io_analog[5],io_analog[4],io_analog[3],io_analog[2],io_analog[1],io_analog[0] io_clamp_high[2],io_clamp_high[1],io_clamp_high[0] io_clamp_low[2],io_clamp_low[1],io_clamp_low[0]
+*+ user_irq[2],user_irq[1],user_irq[0]
+*+ la_oenb[127],la_oenb[126],la_oenb[125],la_oenb[124],la_oenb[123],la_oenb[122],la_oenb[121],la_oenb[120],la_oenb[119],la_oenb[118],la_oenb[117],la_oenb[116],la_oenb[115],la_oenb[114],la_oenb[113],la_oenb[112],la_oenb[111],la_oenb[110],la_oenb[109],la_oenb[108],la_oenb[107],la_oenb[106],la_oenb[105],la_oenb[104],la_oenb[103],la_oenb[102],la_oenb[101],la_oenb[100],la_oenb[99],la_oenb[98],la_oenb[97],la_oenb[96],la_oenb[95],la_oenb[94],la_oenb[93],la_oenb[92],la_oenb[91],la_oenb[90],la_oenb[89],la_oenb[88],la_oenb[87],la_oenb[86],la_oenb[85],la_oenb[84],la_oenb[83],la_oenb[82],la_oenb[81],la_oenb[80],la_oenb[79],la_oenb[78],la_oenb[77],la_oenb[76],la_oenb[75],la_oenb[74],la_oenb[73],la_oenb[72],la_oenb[71],la_oenb[70],la_oenb[69],la_oenb[68],la_oenb[67],la_oenb[66],la_oenb[65],la_oenb[64],la_oenb[63],la_oenb[62],la_oenb[61],la_oenb[60],la_oenb[59],la_oenb[58],la_oenb[57],la_oenb[56],la_oenb[55],la_oenb[54],la_oenb[53],la_oenb[52],la_oenb[51],la_oenb[50],la_oenb[49],la_oenb[48],la_oenb[47],la_oenb[46],la_oenb[45],la_oenb[44],la_oenb[43],la_oenb[42],la_oenb[41],la_oenb[40],la_oenb[39],la_oenb[38],la_oenb[37],la_oenb[36],la_oenb[35],la_oenb[34],la_oenb[33],la_oenb[32],la_oenb[31],la_oenb[30],la_oenb[29],la_oenb[28],la_oenb[27],la_oenb[26],la_oenb[25],la_oenb[24],la_oenb[23],la_oenb[22],la_oenb[21],la_oenb[20],la_oenb[19],la_oenb[18],la_oenb[17],la_oenb[16],la_oenb[15],la_oenb[14],la_oenb[13],la_oenb[12],la_oenb[11],la_oenb[10],la_oenb[9],la_oenb[8],la_oenb[7],la_oenb[6],la_oenb[5],la_oenb[4],la_oenb[3],la_oenb[2],la_oenb[1],la_oenb[0]
+*.iopin vdda1
+*.iopin vdda2
+*.iopin vssa1
+*.iopin vssa2
+*.iopin vccd1
+*.iopin vccd2
+*.iopin vssd1
+*.iopin vssd2
+*.ipin wb_clk_i
+*.ipin wb_rst_i
+*.ipin wbs_stb_i
+*.ipin wbs_cyc_i
+*.ipin wbs_we_i
+*.ipin wbs_sel_i[3],wbs_sel_i[2],wbs_sel_i[1],wbs_sel_i[0]
+*.ipin
+*+ wbs_dat_i[31],wbs_dat_i[30],wbs_dat_i[29],wbs_dat_i[28],wbs_dat_i[27],wbs_dat_i[26],wbs_dat_i[25],wbs_dat_i[24],wbs_dat_i[23],wbs_dat_i[22],wbs_dat_i[21],wbs_dat_i[20],wbs_dat_i[19],wbs_dat_i[18],wbs_dat_i[17],wbs_dat_i[16],wbs_dat_i[15],wbs_dat_i[14],wbs_dat_i[13],wbs_dat_i[12],wbs_dat_i[11],wbs_dat_i[10],wbs_dat_i[9],wbs_dat_i[8],wbs_dat_i[7],wbs_dat_i[6],wbs_dat_i[5],wbs_dat_i[4],wbs_dat_i[3],wbs_dat_i[2],wbs_dat_i[1],wbs_dat_i[0]
+*.ipin
+*+ wbs_adr_i[31],wbs_adr_i[30],wbs_adr_i[29],wbs_adr_i[28],wbs_adr_i[27],wbs_adr_i[26],wbs_adr_i[25],wbs_adr_i[24],wbs_adr_i[23],wbs_adr_i[22],wbs_adr_i[21],wbs_adr_i[20],wbs_adr_i[19],wbs_adr_i[18],wbs_adr_i[17],wbs_adr_i[16],wbs_adr_i[15],wbs_adr_i[14],wbs_adr_i[13],wbs_adr_i[12],wbs_adr_i[11],wbs_adr_i[10],wbs_adr_i[9],wbs_adr_i[8],wbs_adr_i[7],wbs_adr_i[6],wbs_adr_i[5],wbs_adr_i[4],wbs_adr_i[3],wbs_adr_i[2],wbs_adr_i[1],wbs_adr_i[0]
+*.opin wbs_ack_o
+*.opin
+*+ wbs_dat_o[31],wbs_dat_o[30],wbs_dat_o[29],wbs_dat_o[28],wbs_dat_o[27],wbs_dat_o[26],wbs_dat_o[25],wbs_dat_o[24],wbs_dat_o[23],wbs_dat_o[22],wbs_dat_o[21],wbs_dat_o[20],wbs_dat_o[19],wbs_dat_o[18],wbs_dat_o[17],wbs_dat_o[16],wbs_dat_o[15],wbs_dat_o[14],wbs_dat_o[13],wbs_dat_o[12],wbs_dat_o[11],wbs_dat_o[10],wbs_dat_o[9],wbs_dat_o[8],wbs_dat_o[7],wbs_dat_o[6],wbs_dat_o[5],wbs_dat_o[4],wbs_dat_o[3],wbs_dat_o[2],wbs_dat_o[1],wbs_dat_o[0]
+*.ipin
+*+ la_data_in[127],la_data_in[126],la_data_in[125],la_data_in[124],la_data_in[123],la_data_in[122],la_data_in[121],la_data_in[120],la_data_in[119],la_data_in[118],la_data_in[117],la_data_in[116],la_data_in[115],la_data_in[114],la_data_in[113],la_data_in[112],la_data_in[111],la_data_in[110],la_data_in[109],la_data_in[108],la_data_in[107],la_data_in[106],la_data_in[105],la_data_in[104],la_data_in[103],la_data_in[102],la_data_in[101],la_data_in[100],la_data_in[99],la_data_in[98],la_data_in[97],la_data_in[96],la_data_in[95],la_data_in[94],la_data_in[93],la_data_in[92],la_data_in[91],la_data_in[90],la_data_in[89],la_data_in[88],la_data_in[87],la_data_in[86],la_data_in[85],la_data_in[84],la_data_in[83],la_data_in[82],la_data_in[81],la_data_in[80],la_data_in[79],la_data_in[78],la_data_in[77],la_data_in[76],la_data_in[75],la_data_in[74],la_data_in[73],la_data_in[72],la_data_in[71],la_data_in[70],la_data_in[69],la_data_in[68],la_data_in[67],la_data_in[66],la_data_in[65],la_data_in[64],la_data_in[63],la_data_in[62],la_data_in[61],la_data_in[60],la_data_in[59],la_data_in[58],la_data_in[57],la_data_in[56],la_data_in[55],la_data_in[54],la_data_in[53],la_data_in[52],la_data_in[51],la_data_in[50],la_data_in[49],la_data_in[48],la_data_in[47],la_data_in[46],la_data_in[45],la_data_in[44],la_data_in[43],la_data_in[42],la_data_in[41],la_data_in[40],la_data_in[39],la_data_in[38],la_data_in[37],la_data_in[36],la_data_in[35],la_data_in[34],la_data_in[33],la_data_in[32],la_data_in[31],la_data_in[30],la_data_in[29],la_data_in[28],la_data_in[27],la_data_in[26],la_data_in[25],la_data_in[24],la_data_in[23],la_data_in[22],la_data_in[21],la_data_in[20],la_data_in[19],la_data_in[18],la_data_in[17],la_data_in[16],la_data_in[15],la_data_in[14],la_data_in[13],la_data_in[12],la_data_in[11],la_data_in[10],la_data_in[9],la_data_in[8],la_data_in[7],la_data_in[6],la_data_in[5],la_data_in[4],la_data_in[3],la_data_in[2],la_data_in[1],la_data_in[0]
+*.opin
+*+ la_data_out[127],la_data_out[126],la_data_out[125],la_data_out[124],la_data_out[123],la_data_out[122],la_data_out[121],la_data_out[120],la_data_out[119],la_data_out[118],la_data_out[117],la_data_out[116],la_data_out[115],la_data_out[114],la_data_out[113],la_data_out[112],la_data_out[111],la_data_out[110],la_data_out[109],la_data_out[108],la_data_out[107],la_data_out[106],la_data_out[105],la_data_out[104],la_data_out[103],la_data_out[102],la_data_out[101],la_data_out[100],la_data_out[99],la_data_out[98],la_data_out[97],la_data_out[96],la_data_out[95],la_data_out[94],la_data_out[93],la_data_out[92],la_data_out[91],la_data_out[90],la_data_out[89],la_data_out[88],la_data_out[87],la_data_out[86],la_data_out[85],la_data_out[84],la_data_out[83],la_data_out[82],la_data_out[81],la_data_out[80],la_data_out[79],la_data_out[78],la_data_out[77],la_data_out[76],la_data_out[75],la_data_out[74],la_data_out[73],la_data_out[72],la_data_out[71],la_data_out[70],la_data_out[69],la_data_out[68],la_data_out[67],la_data_out[66],la_data_out[65],la_data_out[64],la_data_out[63],la_data_out[62],la_data_out[61],la_data_out[60],la_data_out[59],la_data_out[58],la_data_out[57],la_data_out[56],la_data_out[55],la_data_out[54],la_data_out[53],la_data_out[52],la_data_out[51],la_data_out[50],la_data_out[49],la_data_out[48],la_data_out[47],la_data_out[46],la_data_out[45],la_data_out[44],la_data_out[43],la_data_out[42],la_data_out[41],la_data_out[40],la_data_out[39],la_data_out[38],la_data_out[37],la_data_out[36],la_data_out[35],la_data_out[34],la_data_out[33],la_data_out[32],la_data_out[31],la_data_out[30],la_data_out[29],la_data_out[28],la_data_out[27],la_data_out[26],la_data_out[25],la_data_out[24],la_data_out[23],la_data_out[22],la_data_out[21],la_data_out[20],la_data_out[19],la_data_out[18],la_data_out[17],la_data_out[16],la_data_out[15],la_data_out[14],la_data_out[13],la_data_out[12],la_data_out[11],la_data_out[10],la_data_out[9],la_data_out[8],la_data_out[7],la_data_out[6],la_data_out[5],la_data_out[4],la_data_out[3],la_data_out[2],la_data_out[1],la_data_out[0]
+*.ipin
+*+ io_in[26],io_in[25],io_in[24],io_in[23],io_in[22],io_in[21],io_in[20],io_in[19],io_in[18],io_in[17],io_in[16],io_in[15],io_in[14],io_in[13],io_in[12],io_in[11],io_in[10],io_in[9],io_in[8],io_in[7],io_in[6],io_in[5],io_in[4],io_in[3],io_in[2],io_in[1],io_in[0]
+*.ipin
+*+ io_in_3v3[26],io_in_3v3[25],io_in_3v3[24],io_in_3v3[23],io_in_3v3[22],io_in_3v3[21],io_in_3v3[20],io_in_3v3[19],io_in_3v3[18],io_in_3v3[17],io_in_3v3[16],io_in_3v3[15],io_in_3v3[14],io_in_3v3[13],io_in_3v3[12],io_in_3v3[11],io_in_3v3[10],io_in_3v3[9],io_in_3v3[8],io_in_3v3[7],io_in_3v3[6],io_in_3v3[5],io_in_3v3[4],io_in_3v3[3],io_in_3v3[2],io_in_3v3[1],io_in_3v3[0]
+*.ipin user_clock2
+*.opin
+*+ io_out[26],io_out[25],io_out[24],io_out[23],io_out[22],io_out[21],io_out[20],io_out[19],io_out[18],io_out[17],io_out[16],io_out[15],io_out[14],io_out[13],io_out[12],io_out[11],io_out[10],io_out[9],io_out[8],io_out[7],io_out[6],io_out[5],io_out[4],io_out[3],io_out[2],io_out[1],io_out[0]
+*.opin
+*+ io_oeb[26],io_oeb[25],io_oeb[24],io_oeb[23],io_oeb[22],io_oeb[21],io_oeb[20],io_oeb[19],io_oeb[18],io_oeb[17],io_oeb[16],io_oeb[15],io_oeb[14],io_oeb[13],io_oeb[12],io_oeb[11],io_oeb[10],io_oeb[9],io_oeb[8],io_oeb[7],io_oeb[6],io_oeb[5],io_oeb[4],io_oeb[3],io_oeb[2],io_oeb[1],io_oeb[0]
+*.iopin
+*+ gpio_analog[17],gpio_analog[16],gpio_analog[15],gpio_analog[14],gpio_analog[13],gpio_analog[12],gpio_analog[11],gpio_analog[10],gpio_analog[9],gpio_analog[8],gpio_analog[7],gpio_analog[6],gpio_analog[5],gpio_analog[4],gpio_analog[3],gpio_analog[2],gpio_analog[1],gpio_analog[0]
+*.iopin
+*+ gpio_noesd[17],gpio_noesd[16],gpio_noesd[15],gpio_noesd[14],gpio_noesd[13],gpio_noesd[12],gpio_noesd[11],gpio_noesd[10],gpio_noesd[9],gpio_noesd[8],gpio_noesd[7],gpio_noesd[6],gpio_noesd[5],gpio_noesd[4],gpio_noesd[3],gpio_noesd[2],gpio_noesd[1],gpio_noesd[0]
+*.iopin
+*+ io_analog[10],io_analog[9],io_analog[8],io_analog[7],io_analog[6],io_analog[5],io_analog[4],io_analog[3],io_analog[2],io_analog[1],io_analog[0]
+*.iopin io_clamp_high[2],io_clamp_high[1],io_clamp_high[0]
+*.iopin io_clamp_low[2],io_clamp_low[1],io_clamp_low[0]
+*.opin user_irq[2],user_irq[1],user_irq[0]
+*.ipin
+*+ la_oenb[127],la_oenb[126],la_oenb[125],la_oenb[124],la_oenb[123],la_oenb[122],la_oenb[121],la_oenb[120],la_oenb[119],la_oenb[118],la_oenb[117],la_oenb[116],la_oenb[115],la_oenb[114],la_oenb[113],la_oenb[112],la_oenb[111],la_oenb[110],la_oenb[109],la_oenb[108],la_oenb[107],la_oenb[106],la_oenb[105],la_oenb[104],la_oenb[103],la_oenb[102],la_oenb[101],la_oenb[100],la_oenb[99],la_oenb[98],la_oenb[97],la_oenb[96],la_oenb[95],la_oenb[94],la_oenb[93],la_oenb[92],la_oenb[91],la_oenb[90],la_oenb[89],la_oenb[88],la_oenb[87],la_oenb[86],la_oenb[85],la_oenb[84],la_oenb[83],la_oenb[82],la_oenb[81],la_oenb[80],la_oenb[79],la_oenb[78],la_oenb[77],la_oenb[76],la_oenb[75],la_oenb[74],la_oenb[73],la_oenb[72],la_oenb[71],la_oenb[70],la_oenb[69],la_oenb[68],la_oenb[67],la_oenb[66],la_oenb[65],la_oenb[64],la_oenb[63],la_oenb[62],la_oenb[61],la_oenb[60],la_oenb[59],la_oenb[58],la_oenb[57],la_oenb[56],la_oenb[55],la_oenb[54],la_oenb[53],la_oenb[52],la_oenb[51],la_oenb[50],la_oenb[49],la_oenb[48],la_oenb[47],la_oenb[46],la_oenb[45],la_oenb[44],la_oenb[43],la_oenb[42],la_oenb[41],la_oenb[40],la_oenb[39],la_oenb[38],la_oenb[37],la_oenb[36],la_oenb[35],la_oenb[34],la_oenb[33],la_oenb[32],la_oenb[31],la_oenb[30],la_oenb[29],la_oenb[28],la_oenb[27],la_oenb[26],la_oenb[25],la_oenb[24],la_oenb[23],la_oenb[22],la_oenb[21],la_oenb[20],la_oenb[19],la_oenb[18],la_oenb[17],la_oenb[16],la_oenb[15],la_oenb[14],la_oenb[13],la_oenb[12],la_oenb[11],la_oenb[10],la_oenb[9],la_oenb[8],la_oenb[7],la_oenb[6],la_oenb[5],la_oenb[4],la_oenb[3],la_oenb[2],la_oenb[1],la_oenb[0]
+x1 vccd1 vssa1 io_analog[3] io_analog[8] io_analog[2] io_analog[5] io_analog[6] comparator
+XM40 net1 net2 vssa1 vssa1 sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM41 net1 net2 vccd1 vccd1 sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM42 net3 net1 vssa1 vssa1 sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM43 net3 net1 vccd1 vccd1 sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM44 net4 net3 vssa1 vssa1 sky130_fd_pr__nfet_01v8 L=0.15 W=8 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM45 net4 net3 vccd1 vccd1 sky130_fd_pr__pfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM46 io_analog[1] net4 vssa1 vssa1 sky130_fd_pr__nfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM47 io_analog[1] net4 vccd1 vccd1 sky130_fd_pr__pfet_01v8 L=0.15 W=32 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM1 net2 io_analog[8] vssa1 vssa1 sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM2 net2 io_analog[8] vccd1 vccd1 sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
++ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
++ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+**.ends
+
+* expanding symbol: comparator.sym # of pins=7
+** sym_path: /home/krishna/Strong_Arm_MPW6/xschem/comparator.sym
+** sch_path: /home/krishna/Strong_Arm_MPW6/xschem/comparator.sch
+.subckt comparator VDD GND Outn CLK Outp Vp Vn
+*.iopin VDD
+*.iopin GND
+*.ipin Vn
+*.ipin Vp
+*.iopin CLK
+*.opin Outn
+*.opin Outp
+XM1 net2 Vp net1 GND sky130_fd_pr__nfet_01v8 L=0.15 W=5.3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 net3 Vn net1 GND sky130_fd_pr__nfet_01v8 L=0.15 W=5.3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net1 C GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM11 net2 C VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM12 Dn C VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM13 Dp C VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM14 net3 C VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM15 Dp Dn net3 GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.78 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM16 Dn Dp net2 GND sky130_fd_pr__nfet_01v8 L=0.15 W=0.78 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM17 Dp Dn VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.78 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM18 Dn Dp VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.78 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM20 p Lp GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM21 n Ln GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM22 p n VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM23 n p VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM24 net4 CLK GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM25 net4 CLK VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM26 net5 net4 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM27 net5 net4 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM28 net6 net5 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=8 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM29 net6 net5 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM30 C net6 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM31 C net6 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=32 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM40 net7 n GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM41 net7 n VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM42 net8 net7 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM43 net8 net7 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM44 net9 net8 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=8 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM45 net9 net8 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM46 Outn net9 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM47 Outn net9 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=32 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM48 net10 p GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM49 net10 p VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM50 net11 net10 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM51 net11 net10 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM52 net12 net11 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=8 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM53 net12 net11 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM54 Outp net12 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM55 Outp net12 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=32 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 Lp Dp GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM5 Lp Dp VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 Ln Dn GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM7 Ln Dn VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+.end
diff --git a/xschem/user_analog_project_wrapper.sym b/xschem/user_analog_project_wrapper.sym
new file mode 100644
index 0000000..6cb4d88
--- /dev/null
+++ b/xschem/user_analog_project_wrapper.sym
@@ -0,0 +1,108 @@
+v {xschem version=3.0.0 file_version=1.2}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+
+T {@symname} -139.5 -6 0 0 0.3 0.3 {}
+T {@name} 135 -202 0 0 0.2 0.2 {}
+L 4 -130 -190 130 -190 {}
+L 4 -130 190 130 190 {}
+L 4 -130 -190 -130 190 {}
+L 4 130 -190 130 190 {}
+B 5 147.5 -182.5 152.5 -177.5 {name=vdda1 dir=inout }
+L 7 130 -180 150 -180 {}
+T {vdda1} 125 -184 0 1 0.2 0.2 {}
+B 5 147.5 -162.5 152.5 -157.5 {name=vdda2 dir=inout }
+L 7 130 -160 150 -160 {}
+T {vdda2} 125 -164 0 1 0.2 0.2 {}
+B 5 147.5 -142.5 152.5 -137.5 {name=vssa1 dir=inout }
+L 7 130 -140 150 -140 {}
+T {vssa1} 125 -144 0 1 0.2 0.2 {}
+B 5 147.5 -122.5 152.5 -117.5 {name=vssa2 dir=inout }
+L 7 130 -120 150 -120 {}
+T {vssa2} 125 -124 0 1 0.2 0.2 {}
+B 5 147.5 -102.5 152.5 -97.5 {name=vccd1 dir=inout }
+L 7 130 -100 150 -100 {}
+T {vccd1} 125 -104 0 1 0.2 0.2 {}
+B 5 147.5 -82.5 152.5 -77.5 {name=vccd2 dir=inout }
+L 7 130 -80 150 -80 {}
+T {vccd2} 125 -84 0 1 0.2 0.2 {}
+B 5 147.5 -62.5 152.5 -57.5 {name=vssd1 dir=inout }
+L 7 130 -60 150 -60 {}
+T {vssd1} 125 -64 0 1 0.2 0.2 {}
+B 5 147.5 -42.5 152.5 -37.5 {name=vssd2 dir=inout }
+L 7 130 -40 150 -40 {}
+T {vssd2} 125 -44 0 1 0.2 0.2 {}
+B 5 -152.5 -182.5 -147.5 -177.5 {name=wb_clk_i dir=in }
+L 4 -150 -180 -130 -180 {}
+T {wb_clk_i} -125 -184 0 0 0.2 0.2 {}
+B 5 -152.5 -162.5 -147.5 -157.5 {name=wb_rst_i dir=in }
+L 4 -150 -160 -130 -160 {}
+T {wb_rst_i} -125 -164 0 0 0.2 0.2 {}
+B 5 -152.5 -142.5 -147.5 -137.5 {name=wbs_stb_i dir=in }
+L 4 -150 -140 -130 -140 {}
+T {wbs_stb_i} -125 -144 0 0 0.2 0.2 {}
+B 5 -152.5 -122.5 -147.5 -117.5 {name=wbs_cyc_i dir=in }
+L 4 -150 -120 -130 -120 {}
+T {wbs_cyc_i} -125 -124 0 0 0.2 0.2 {}
+B 5 -152.5 -102.5 -147.5 -97.5 {name=wbs_we_i dir=in }
+L 4 -150 -100 -130 -100 {}
+T {wbs_we_i} -125 -104 0 0 0.2 0.2 {}
+B 5 -152.5 -82.5 -147.5 -77.5 {name=wbs_sel_i[3:0] dir=in }
+L 4 -150 -80 -130 -80 {}
+T {wbs_sel_i[3:0]} -125 -84 0 0 0.2 0.2 {}
+B 5 -152.5 -62.5 -147.5 -57.5 {name=wbs_dat_i[31:0] dir=in }
+L 4 -150 -60 -130 -60 {}
+T {wbs_dat_i[31:0]} -125 -64 0 0 0.2 0.2 {}
+B 5 -152.5 -42.5 -147.5 -37.5 {name=wbs_adr_i[31:0] dir=in }
+L 4 -150 -40 -130 -40 {}
+T {wbs_adr_i[31:0]} -125 -44 0 0 0.2 0.2 {}
+B 5 147.5 -22.5 152.5 -17.5 {name=wbs_ack_o dir=out }
+L 4 130 -20 150 -20 {}
+T {wbs_ack_o} 125 -24 0 1 0.2 0.2 {}
+B 5 147.5 -2.5 152.5 2.5 {name=wbs_dat_o[31:0] dir=out }
+L 4 130 0 150 0 {}
+T {wbs_dat_o[31:0]} 125 -4 0 1 0.2 0.2 {}
+B 5 -152.5 -22.5 -147.5 -17.5 {name=la_data_in[127:0] dir=in }
+L 4 -150 -20 -130 -20 {}
+T {la_data_in[127:0]} -125 -24 0 0 0.2 0.2 {}
+B 5 147.5 17.5 152.5 22.5 {name=la_data_out[127:0] dir=out }
+L 4 130 20 150 20 {}
+T {la_data_out[127:0]} 125 16 0 1 0.2 0.2 {}
+B 5 -152.5 -2.5 -147.5 2.5 {name=la_oenb[127:0] dir=in }
+L 4 -150 0 -130 0 {}
+T {la_oenb[127:0]} -125 -4 0 0 0.2 0.2 {}
+B 5 -152.5 17.5 -147.5 22.5 {name=io_in[26:0] dir=in }
+L 4 -150 20 -130 20 {}
+T {io_in[26:0]} -125 16 0 0 0.2 0.2 {}
+B 5 -152.5 37.5 -147.5 42.5 {name=io_in_3v3[26:0] dir=in }
+L 4 -150 40 -130 40 {}
+T {io_in_3v3[26:0]} -125 36 0 0 0.2 0.2 {}
+B 5 147.5 37.5 152.5 42.5 {name=io_out[26:0] dir=out }
+L 4 130 40 150 40 {}
+T {io_out[26:0]} 125 36 0 1 0.2 0.2 {}
+B 5 147.5 57.5 152.5 62.5 {name=io_oeb[26:0] dir=out }
+L 4 130 60 150 60 {}
+T {io_oeb[26:0]} 125 56 0 1 0.2 0.2 {}
+B 5 147.5 77.5 152.5 82.5 {name=gpio_analog[17:0] dir=inout }
+L 7 130 80 150 80 {}
+T {gpio_analog[17:0]} 125 76 0 1 0.2 0.2 {}
+B 5 147.5 97.5 152.5 102.5 {name=gpio_noesd[17:0] dir=inout }
+L 7 130 100 150 100 {}
+T {gpio_noesd[17:0]} 125 96 0 1 0.2 0.2 {}
+B 5 147.5 117.5 152.5 122.5 {name=io_analog[10:0] dir=inout }
+L 7 130 120 150 120 {}
+T {io_analog[10:0]} 125 116 0 1 0.2 0.2 {}
+B 5 147.5 137.5 152.5 142.5 {name=io_clamp_high[2:0] dir=inout }
+L 7 130 140 150 140 {}
+T {io_clamp_high[2:0]} 125 136 0 1 0.2 0.2 {}
+B 5 147.5 157.5 152.5 162.5 {name=io_clamp_low[2:0] dir=inout }
+L 7 130 160 150 160 {}
+T {io_clamp_low[2:0]} 125 156 0 1 0.2 0.2 {}
+B 5 -152.5 57.5 -147.5 62.5 {name=user_clock2 dir=in }
+L 4 -150 60 -130 60 {}
+T {user_clock2} -125 56 0 0 0.2 0.2 {}
+B 5 147.5 177.5 152.5 182.5 {name=user_irq[2:0] dir=out }
+L 4 130 180 150 180 {}
+T {user_irq[2:0]} 125 176 0 1 0.2 0.2 {}
diff --git a/xschem/xschemrc b/xschem/xschemrc
new file mode 100755
index 0000000..7e7fb8b
--- /dev/null
+++ b/xschem/xschemrc
@@ -0,0 +1,322 @@
+#### xschemrc system configuration file
+
+#### values may be overridden by user's ~/.xschem/xschemrc configuration file
+#### or by project-local ./xschemrc
+
+###########################################################################
+#### XSCHEM INSTALLATION DIRECTORY: XSCHEM_SHAREDIR
+###########################################################################
+#### Normally there is no reason to set this variable if using standard
+#### installation. Location of files is set at compile time but may be overridden
+#### with following line:
+# set XSCHEM_SHAREDIR $env(HOME)/share/xschem
+
+###########################################################################
+#### XSCHEM SYSTEM-WIDE DESIGN LIBRARY PATHS: XSCHEM_LIBRARY_PATH
+###########################################################################
+#### If unset xschem starts with XSCHEM_LIBRARY_PATH set to the default, typically:
+# /home/schippes/.xschem/xschem_library
+# /home/schippes/share/xschem/xschem_library/devices
+# /home/schippes/share/doc/xschem/examples
+# /home/schippes/share/doc/xschem/ngspice
+# /home/schippes/share/doc/xschem/logic
+# /home/schippes/share/doc/xschem/xschem_simulator
+# /home/schippes/share/doc/xschem/binto7seg
+# /home/schippes/share/doc/xschem/pcb
+# /home/schippes/share/doc/xschem/rom8k
+
+
+#### Flush any previous definition
+set XSCHEM_LIBRARY_PATH {}
+#### include devices/*.sym
+append XSCHEM_LIBRARY_PATH :${XSCHEM_SHAREDIR}/xschem_library
+#### include skywater libraries. Here i use [pwd]. This works if i start xschem from here.
+append XSCHEM_LIBRARY_PATH :$env(PWD)
+append XSCHEM_LIBRARY_PATH :/usr/local/share/pdk/sky130A/libs.tech/xschem
+# append XSCHEM_LIBRARY_PATH :/mnt/sda7/home/schippes/pdks/sky130A/libs.tech/xschem
+#### add ~/.xschem/xschem_library (USER_CONF_DIR is normally ~/.xschem)
+append XSCHEM_LIBRARY_PATH :$USER_CONF_DIR/xschem_library
+
+###########################################################################
+#### SET CUSTOM COLORS FOR XSCHEM LIBRARIES MATCHING CERTAIN PATTERNS
+###########################################################################
+#### each line contains a dircolor(pattern) followed by a color
+#### color can be an ordinary name (grey, brown, blue) or a hex code {#77aaff}
+#### hex code must be enclosed in braces
+array unset dircolor
+set dircolor(sky130_fd_pr$) blue
+set dircolor(sky130_tests$) blue
+set dircolor(xschem_sky130$) blue
+set dircolor(xschem_library$) red
+set dircolor(devices$) red
+
+###########################################################################
+#### WINDOW TO OPEN ON STARTUP: XSCHEM_START_WINDOW
+###########################################################################
+#### Start without a design if no filename given on command line:
+#### To avoid absolute paths, use a path that is relative to one of the
+#### XSCHEM_LIBRARY_PATH directories. Default: empty
+set XSCHEM_START_WINDOW {sky130_tests/top.sch}
+
+###########################################################################
+#### DIRECTORY WHERE SIMULATIONS, NETLIST AND SIMULATOR OUTPUTS ARE PLACED
+###########################################################################
+#### If unset $USER_CONF_DIR/simulations is assumed (normally ~/.xschem/simulations)
+# set netlist_dir $env(HOME)/.xschem/simulations
+set netlist_dir $env(PWD)
+
+###########################################################################
+#### NETLIST AND HIERARCHICAL PRINT EXCLUDE PATTERNS
+###########################################################################
+#### xschem_libs is a list of patterns of cells to exclude from netlisting.
+#### Matching is done as regular expression on full cell path
+#### Example:
+#### set xschem_libs { {/cmoslib/} {/analoglib/.*pass} buffer }
+#### in this case all schematic cells of directory cmoslib and cells containing
+#### /analoglib/...pass and buffer will be excluded from netlisting
+#### default value: empty
+# set xschem_libs {}
+#### noprint_libs is a list with same rules as for xschem_libs. This
+#### variable controls hierarchical print
+#### default value: empty
+# set noprint_libs {}
+
+###########################################################################
+#### CHANGE DEFAULT [] WITH SOME OTHER CHARACTERS FOR BUSSED SIGNALS
+#### IN SPICE NETLISTS (EXAMPLE: DATA[7] --> DATA<7>)
+###########################################################################
+#### default: empty (use xschem default, [ ])
+# set bus_replacement_char {<>}
+#### for XSPICE: replace square brackets as the are used for XSPICE vector nodes.
+# set bus_replacement_char {__}
+
+###########################################################################
+#### SOME DEFAULT BEHAVIOR
+###########################################################################
+#### Allowed values: spice, verilog, vhdl, tedax, default: spice
+# set netlist_type spice
+
+#### Some netlisting options (these are the defaults)
+# set hspice_netlist 1
+# set verilog_2001 1
+
+#### to use a fixed line with set change_lw to 0 and set some value to line_width
+#### these are the defaults
+# set line_width 0
+# set change_lw 1
+
+#### allow color postscript and svg exports. Default: 1, enable color
+# set color_ps 1
+
+#### initial size of xschem window you can specify also position with (wxh+x+y)
+#### this is the default:
+# set initial_geometry {900x600}
+
+#### if set to 0, when zooming out allow the viewport do drift toward the mouse position,
+#### allowing to move away by zooming / unzooming with mouse wheel
+#### default setting: 0
+# set unzoom_nodrift 0
+
+#### if set to 1 allow to place multiple components with same name.
+#### Warning: this is normally not allowed in any simulation netlist.
+#### default: 0, do not allow place multiple elements with same name (refdes)
+# set disable_unique_names 0
+
+#### if set to 1 continue drawing lines / wires after click
+#### default: 0
+# set persistent_command 1
+
+#### if set to 1 a wire is inserted when separating components that are
+#### connected by pins. Default: not enabled (0)
+# set connect_by_kissing 1
+
+#### if set to 1 automatically join/trim wires while editing
+#### this may slow down on rally big designs. Can be disabled via menu
+#### default: 0
+# set autotrim_wires 0
+
+#### set widget scaling (mainly for font display), this is useful on 4K displays
+#### default: unset (tk uses its default) > 1.0 ==> bigger
+# set tk_scaling 1.7
+
+#### disable some symbol layers. Default: none, all layers are visible.
+# set enable_layer(5) 0 ;# example to disable pin red boxes
+
+#### enable to scale grid point size as done with lines at close zoom, default: 0
+# set big_grid_points 0
+
+###########################################################################
+#### EXPORT FORMAT TRANSLATORS, PNG AND PDF
+###########################################################################
+#### command to translate xpm to png; (assumes command takes source
+#### and dest file as arguments, example: gm convert plot.xpm plot.png)
+#### default: {gm convert}
+# set to_png {gm convert}
+
+#### command to translate ps to pdf; (assumes command takes source
+#### and dest file as arguments, example: ps2pdf plot.ps plot.pdf)
+#### default: ps2pdf
+# set to_pdf ps2pdf
+set to_pdf {ps2pdf -dAutoRotatePages=/None}
+
+###########################################################################
+#### UNDO: SAVE ON DISK OR KEEP IN MEMORY
+###########################################################################
+#### Alloved: 'disk'or 'memory'.
+#### Saving undo on disk is safer but slower on extremely big schematics.
+#### In most cases you won't notice any delay. Undo on disk allows previous
+#### state recovery in case of crashes. In-memory undo is extremely fast
+#### but should a crash occur everything is lost.
+#### It is highly recommended to keep undo on disk.
+#### Default: disk
+# set undo_type disk
+
+###########################################################################
+#### CUSTOM GRID / SNAP VALUE SETTINGS
+###########################################################################
+#### Warning: changing these values will likely break compatibility
+#### with existing symbol libraries. Defaults: grid 20, snap 10.
+# set grid 20
+# set snap 10
+
+###########################################################################
+#### CUSTOM COLORS MAY BE DEFINED HERE
+###########################################################################
+# set cadlayers 22
+# set light_colors {
+# "#ffffff" "#0044ee" "#aaaaaa" "#222222" "#229900"
+# "#bb2200" "#00ccee" "#ff0000" "#888800" "#00aaaa"
+# "#880088" "#00ff00" "#0000cc" "#666600" "#557755"
+# "#aa2222" "#7ccc40" "#00ffcc" "#ce0097" "#d2d46b"
+# "#ef6158" "#fdb200" }
+
+# set dark_colors {
+# "#000000" "#00ccee" "#3f3f3f" "#cccccc" "#88dd00"
+# "#bb2200" "#00ccee" "#ff0000" "#ffff00" "#ffffff"
+# "#ff00ff" "#00ff00" "#0000cc" "#aaaa00" "#aaccaa"
+# "#ff7777" "#bfff81" "#00ffcc" "#ce0097" "#d2d46b"
+# "#ef6158" "#fdb200" }
+
+###########################################################################
+#### CAIRO STUFF
+###########################################################################
+#### Scale all fonts by this number
+# set cairo_font_scale 1.0
+
+#### default for following two is 0.85 (xscale) and 0.88 (yscale) to
+#### match cairo font spacing
+# set nocairo_font_xscale 1.0
+#### set nocairo_font_yscale 1.0
+
+#### Scale line spacing by this number
+# set cairo_font_line_spacing 1.0
+
+#### Specify a font
+# set cairo_font_name {Sans-Serif}
+# set svg_font_name {Sans-Serif}
+
+#### Lift up text by some zoom-corrected pixels for
+#### better compatibility wrt no cairo version.
+#### Useful values in the range [-1, 3]
+# set cairo_vert_correct 0
+# set nocairo_vert_correct 0
+
+###########################################################################
+#### KEYBINDINGS
+###########################################################################
+#### General format for specifying a replacement for a keybind
+#### Replace Ctrl-d with Escape (so you wont kill the program)
+# set replace_key(Control-d) Escape
+
+#### swap w and W keybinds; Always specify Shift for capital letters
+# set replace_key(Shift-W) w
+# set replace_key(w) Shift-W
+
+###########################################################################
+#### TERMINAL
+###########################################################################
+#### default for linux: xterm
+# set terminal {xterm -geometry 100x35 -fn 9x15 -bg black -fg white -cr white -ms white }
+#### lxterminal is not OK since it will not inherit env vars:
+#### In order to reduce memory usage and increase the performance, all instances
+#### of the lxterminal are sharing a single process. LXTerminal is part of LXDE
+
+###########################################################################
+#### EDITOR
+###########################################################################
+#### editor must not detach from launching shell (-f mandatory for gvim)
+#### default for linux: gvim -f
+# set editor {gvim -f -geometry 90x28}
+# set editor { xterm -geometry 100x40 -e nano }
+# set editor { xterm -geometry 100x40 -e pico }
+
+#### For Windows
+# set editor {notepad.exe}
+
+###########################################################################
+#### SHOW ERC INFO WINDOW (erc errors, warnings etc)
+###########################################################################
+#### default: 0 (can be enabled by menu)
+# set show_infowindow 0
+
+###########################################################################
+#### CONFIGURE COMPUTER FARM JOB REDIRECTORS FOR SIMULATIONS
+###########################################################################
+#### RTDA NC
+# set computerfarm {nc run -Il}
+#### LSF BSUB
+# set computerfarm {bsub -Is}
+
+###########################################################################
+#### TCP CONNECTION WITH GAW
+###########################################################################
+#### set gaw address for socket connection: {host port}
+#### default: set to localhost, port 2020
+# set gaw_tcp_address {localhost 2020}
+
+###########################################################################
+#### XSCHEM LISTEN TO TCP PORT
+###########################################################################
+#### set xschem listening port; default: not enabled
+# set xschem_listen_port 2021
+
+###########################################################################
+#### BESPICE WAVE SOCKET CONNECTION
+###########################################################################
+#### set bespice wave listening port; default: not enabled
+set bespice_listen_port 2022
+
+###########################################################################
+#### TCL FILES TO LOAD AT STARTUP
+###########################################################################
+#### list of tcl files to preload.
+# lappend tcl_files ${XSCHEM_SHAREDIR}/change_index.tcl
+lappend tcl_files ${XSCHEM_SHAREDIR}/ngspice_backannotate.tcl
+
+###########################################################################
+#### XSCHEM TOOLBAR
+###########################################################################
+#### default: not enabled.
+set toolbar_visible 1
+# set toolbar_horiz 1
+
+###########################################################################
+#### TABBED WINDOWS
+###########################################################################
+# default: not enabled. Interface can be changed runtime if only one window
+# or tab is open.
+set tabbed_interface 1
+
+###########################################################################
+#### SKYWATER PDK SPECIFIC VARIABLES
+###########################################################################
+
+## (spice patched) skywater-pdk install
+# set SKYWATER_MODELS ~/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest
+# set SKYWATER_STDCELLS ~/skywater-pdk/libraries/sky130_fd_sc_hd/latest
+
+## opencircuitdesign pdks install. You need to change these to point to your open_pdks installation
+set SKYWATER_MODELS /usr/local/share/pdk/sky130A/libs.tech/ngspice
+set SKYWATER_STDCELLS /usr/local/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice
+#set SKYWATER_MODELS $env(HOME)/share/pdk/sky130A/libs.tech/ngspice
+#set SKYWATER_STDCELLS $env(HOME)/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice
