| // SPDX-FileCopyrightText: 2020 Efabless Corporation |
| // |
| // Licensed under the Apache License, Version 2.0 (the "License"); |
| // you may not use this file except in compliance with the License. |
| // You may obtain a copy of the License at |
| // |
| // http://www.apache.org/licenses/LICENSE-2.0 |
| // |
| // Unless required by applicable law or agreed to in writing, software |
| // distributed under the License is distributed on an "AS IS" BASIS, |
| // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| // See the License for the specific language governing permissions and |
| // limitations under the License. |
| // SPDX-License-Identifier: Apache-2.0 |
| |
| `default_nettype none |
| |
| `include "comparator.v" |
| |
| |
| /* |
| * I/O mapping for analog |
| * |
| * mprj_io[37] io_in/out/oeb/in_3v3[26] --- --- |
| * mprj_io[36] io_in/out/oeb/in_3v3[25] --- --- |
| * mprj_io[35] io_in/out/oeb/in_3v3[24] gpio_analog/noesd[17] --- |
| * mprj_io[34] io_in/out/oeb/in_3v3[23] gpio_analog/noesd[16] --- |
| * mprj_io[33] io_in/out/oeb/in_3v3[22] gpio_analog/noesd[15] --- |
| * mprj_io[32] io_in/out/oeb/in_3v3[21] gpio_analog/noesd[14] --- |
| * mprj_io[31] io_in/out/oeb/in_3v3[20] gpio_analog/noesd[13] --- |
| * mprj_io[30] io_in/out/oeb/in_3v3[19] gpio_analog/noesd[12] --- |
| * mprj_io[29] io_in/out/oeb/in_3v3[18] gpio_analog/noesd[11] --- |
| * mprj_io[28] io_in/out/oeb/in_3v3[17] gpio_analog/noesd[10] --- |
| * mprj_io[27] io_in/out/oeb/in_3v3[16] gpio_analog/noesd[9] --- |
| * mprj_io[26] io_in/out/oeb/in_3v3[15] gpio_analog/noesd[8] --- |
| * mprj_io[25] io_in/out/oeb/in_3v3[14] gpio_analog/noesd[7] --- |
| * mprj_io[24] --- --- user_analog[10] |
| * mprj_io[23] --- --- user_analog[9] |
| * mprj_io[22] --- --- user_analog[8] |
| * mprj_io[21] --- --- user_analog[7] |
| * mprj_io[20] --- --- user_analog[6] clamp[2] |
| * mprj_io[19] --- --- user_analog[5] clamp[1] |
| * mprj_io[18] --- --- user_analog[4] clamp[0] |
| * mprj_io[17] --- --- user_analog[3] |
| * mprj_io[16] --- --- user_analog[2] |
| * mprj_io[15] --- --- user_analog[1] |
| * mprj_io[14] --- --- user_analog[0] |
| * mprj_io[13] io_in/out/oeb/in_3v3[13] gpio_analog/noesd[6] --- |
| * mprj_io[12] io_in/out/oeb/in_3v3[12] gpio_analog/noesd[5] --- |
| * mprj_io[11] io_in/out/oeb/in_3v3[11] gpio_analog/noesd[4] --- |
| * mprj_io[10] io_in/out/oeb/in_3v3[10] gpio_analog/noesd[3] --- |
| * mprj_io[9] io_in/out/oeb/in_3v3[9] gpio_analog/noesd[2] --- |
| * mprj_io[8] io_in/out/oeb/in_3v3[8] gpio_analog/noesd[1] --- |
| * mprj_io[7] io_in/out/oeb/in_3v3[7] gpio_analog/noesd[0] --- |
| * mprj_io[6] io_in/out/oeb/in_3v3[6] --- --- |
| * mprj_io[5] io_in/out/oeb/in_3v3[5] --- --- |
| * mprj_io[4] io_in/out/oeb/in_3v3[4] --- --- |
| * mprj_io[3] io_in/out/oeb/in_3v3[3] --- --- |
| * mprj_io[2] io_in/out/oeb/in_3v3[2] --- --- |
| * mprj_io[1] io_in/out/oeb/in_3v3[1] --- --- |
| * mprj_io[0] io_in/out/oeb/in_3v3[0] --- --- |
| * |
| */ |
| |
| /* |
| *---------------------------------------------------------------- |
| * |
| * user_analog_proj_example |
| * |
| * This is an example of a (trivially simple) analog user project, |
| * showing how the user project can connect to the I/O pads, both |
| * the digital pads, the analog connection on the digital pads, |
| * and the dedicated analog pins used as an additional power supply |
| * input, with a connected ESD clamp. |
| * |
| * See the testbench in directory "mprj_por" for the example |
| * program that drives this user project. |
| * |
| *---------------------------------------------------------------- |
| */ |
| |
| module user_analog_proj_example ( |
| `ifdef USE_POWER_PINS |
| inout vdda1, // User area 1 3.3V supply |
| inout vdda2, // User area 2 3.3V supply |
| inout vssa1, // User area 1 analog ground |
| inout vssa2, // User area 2 analog ground |
| inout vccd1, // User area 1 1.8V supply |
| inout vccd2, // User area 2 1.8v supply |
| inout vssd1, // User area 1 digital ground |
| inout vssd2, // User area 2 digital ground |
| `endif |
| |
| // Wishbone Slave ports (WB MI A) |
| input wb_clk_i, |
| input wb_rst_i, |
| input wbs_stb_i, |
| input wbs_cyc_i, |
| input wbs_we_i, |
| input [3:0] wbs_sel_i, |
| input [31:0] wbs_dat_i, |
| input [31:0] wbs_adr_i, |
| output wbs_ack_o, |
| output [31:0] wbs_dat_o, |
| |
| // Logic Analyzer Signals |
| input [127:0] la_data_in, |
| output [127:0] la_data_out, |
| input [127:0] la_oenb, |
| |
| // IOs |
| input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in, |
| input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3, |
| output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out, |
| output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb, |
| |
| // GPIO-analog |
| inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog, |
| inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd, |
| |
| // Dedicated analog |
| inout [`ANALOG_PADS-1:0] io_analog, |
| inout [2:0] io_clamp_high, |
| inout [2:0] io_clamp_low, |
| |
| // Clock |
| input user_clock2, |
| |
| // IRQ |
| output [2:0] irq |
| ); |
| wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in; |
| wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3; |
| wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out; |
| wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb; |
| wire [`ANALOG_PADS-1:0] io_analog; |
| |
| // wire [31:0] rdata; |
| // wire [31:0] wdata; |
| |
| // wire valid; |
| // wire [3:0] wstrb; |
| `ifdef USE_POWER_PINS |
| |
| assign io_clamp_high[2:1] = vccd1; |
| assign io_clamp_low[2:1] = vssa1; |
| `endif |
| wire analog0, analog2, analog3, ; |
| |
| // WB MI A |
| // assign valid = wbs_cyc_i && wbs_stb_i; |
| // assign wstrb = wbs_sel_i & {4{wbs_we_i}}; |
| // assign wbs_dat_o = rdata; |
| // assign wdata = wbs_dat_i; |
| |
| // IO --- unused (no need to connect to anything) |
| // assign io_out[`MPRJ_IO_PADS-`ANALOG_PADS-1:17] = 0; |
| // assign io_out[14:13] = 11'b0; |
| // assign io_out[10:0] = 11'b0; |
| |
| // assign io_oeb[`MPRJ_IO_PADS-`ANALOG_PADS-1:17] = -1; |
| // assign io_oeb[14:13] = 11'b1; |
| // assign io_oeb[10:0] = 11'b1; |
| |
| // IO --- enable outputs on 11, 12, 15, and 16 |
| assign io_analog[2] = analog2; |
| assign io_analog[3] = analog3; |
| assign io_analog[5] = analog5; |
| assign io_analog[6] = analog6; |
| assign io_analog[1] = analog1; |
| assign io_analog[8] = analog8; |
| |
| |
| comparator comp1 ( |
| `ifdef USE_POWER_PINS |
| .VDD(vccd1), |
| .GND(vssa1), |
| `endif |
| .Vp(analog5), // 3.3V domain output |
| .Vn(analog6), // 1.8V domain output |
| .CLK(analog8), |
| |
| .Outn(analog3), |
| .Outp(analog2) // 1.8V domain output |
| ); |
| |
| |
| endmodule |
| |
| `default_nettype wire |