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a1c31c5713bfdb6ae7a2dc242f6b68d2d739e798
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a1c31c5713bfdb6ae7a2dc242f6b68d2d739e798
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author
ranan-usp <oe23ranan@ec.usp.ac.jp>
Wed May 18 07:08:20 2022 +0900
committer
ranan-usp <oe23ranan@ec.usp.ac.jp>
Wed May 18 07:08:20 2022 +0900
tree
43f6726a5e4ee80a4c303fbb13f2bd735de6a579
parent
78fa95c940c3cee407228efc6232177b99a4bf85
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verilog/dv-test/count_monitor.v
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verilog/dv-test/dff.v
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verilog/dv-test/sample/sample.o
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verilog/dv-test/sample/sample.v
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verilog/dv-test/sample/tb_Prpg10.vcd
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verilog/dv-test/sample/tb_sample.v
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verilog/dv-test/tb_count_monitor.o
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verilog/dv-test/tb_count_monitor.vcd
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verilog/dv-test/tb_counter_monitor.v
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verilog/dv-test/tb_dff.o
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verilog/dv-test/tb_dff.v
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verilog/dv-test/tb_dff.vcd
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verilog/dv/mprj_por/mprj_por.elf
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verilog/dv/mprj_por/mprj_por.vvp
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verilog/dv/mprj_por/mprj_por_tb.v
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15 files changed
tree: 43f6726a5e4ee80a4c303fbb13f2bd735de6a579
.github/
docs/
gds/
mag/
netgen/
openlane/
verilog/
xschem/
caravel
.gitignore
LICENSE
Makefile
README.md
README.md
Caravel Analog User
:exclamation: Important Note
Please fill in your project documentation in this README.md file
:warning:
Use this sample project for analog user projects.
Refer to
README
for this sample project documentation.
