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foss-eda-tools / third_party / shuttle / sky130 / mpw-006 / slot-005 / 288d6944726a934f0181c2e1f6bc14c1afa92c7e / . / verilog / includes / includes.rtl.caravel_user_project
blob: 23923a72c32f204b02c7ec9628eb0224dfc1bf93 [file] [log] [blame]
dineshannayya11a64182022-03-19 08:29:11 +0530[diff] [blame]1# Caravel user project includes
dineshannayyad8a093b2022-03-26 08:32:19 +0530[diff] [blame]2+incdir+$(USER_PROJECT_VERILOG)/rtl/
dineshannayya11a64182022-03-19 08:29:11 +0530[diff] [blame]3+incdir+$(USER_PROJECT_VERILOG)/rtl/i2cm/src/includes
4+incdir+$(USER_PROJECT_VERILOG)/rtl/usb1_host/src/includes
dineshannayyad8a093b2022-03-26 08:32:19 +0530[diff] [blame]5+incdir+$(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/includes
6+incdir+$(USER_PROJECT_VERILOG)/dv/bfm
dineshannayya11a64182022-03-19 08:29:11 +0530[diff] [blame]7+incdir+$(USER_PROJECT_VERILOG)/dv/model
8+incdir+$(USER_PROJECT_VERILOG)/dv/agents
dineshannayyad8a093b2022-03-26 08:32:19 +0530[diff] [blame]9$(USER_PROJECT_VERILOG)/rtl/user_reg_map.v
dineshannayya11a64182022-03-19 08:29:11 +0530[diff] [blame]10-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pinmux.sv
11-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pinmux_reg.sv
12-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/gpio_intr.sv
13-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pwm.sv
14-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/timer.sv
15-v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type1.sv
16-v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type2.sv
17-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_top.sv
18-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_if.sv
19-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_fifo.sv
20-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_regs.sv
21-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_clkgen.sv
22-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_ctrl.sv
23-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_rx.sv
24-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_tx.sv
25-v $(USER_PROJECT_VERILOG)/rtl/uart/src/uart_core.sv
26-v $(USER_PROJECT_VERILOG)/rtl/uart/src/uart_cfg.sv
27-v $(USER_PROJECT_VERILOG)/rtl/uart/src/uart_rxfsm.sv
28-v $(USER_PROJECT_VERILOG)/rtl/uart/src/uart_txfsm.sv
29-v $(USER_PROJECT_VERILOG)/rtl/lib/async_fifo_th.sv
30-v $(USER_PROJECT_VERILOG)/rtl/lib/reset_sync.sv
31-v $(USER_PROJECT_VERILOG)/rtl/lib/double_sync_low.v
32-v $(USER_PROJECT_VERILOG)/rtl/lib/clk_buf.v
33-v $(USER_PROJECT_VERILOG)/rtl/i2cm/src/core/i2cm_bit_ctrl.v
34-v $(USER_PROJECT_VERILOG)/rtl/i2cm/src/core/i2cm_byte_ctrl.v
35-v $(USER_PROJECT_VERILOG)/rtl/i2cm/src/core/i2cm_top.v
36-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/core/usbh_core.sv
37-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/core/usbh_crc16.sv
38-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/core/usbh_crc5.sv
39-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/core/usbh_fifo.sv
40-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/core/usbh_sie.sv
41-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/phy/usb_fs_phy.v
42-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/phy/usb_transceiver.v
43-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/top/usb1_host.sv
44-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_top.sv
45-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_ctl.sv
46-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_if.sv
47-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_cfg.sv
48-v $(USER_PROJECT_VERILOG)/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv
49-v $(USER_PROJECT_VERILOG)/rtl/lib/async_fifo.sv
50-v $(USER_PROJECT_VERILOG)/rtl/lib/registers.v
51-v $(USER_PROJECT_VERILOG)/rtl/lib/clk_ctl.v
52-v $(USER_PROJECT_VERILOG)/rtl/lib/ser_inf_32b.sv
53-v $(USER_PROJECT_VERILOG)/rtl/lib/ser_shift.sv
54-v $(USER_PROJECT_VERILOG)/rtl/digital_core/src/glbl_cfg.sv
55-v $(USER_PROJECT_VERILOG)/rtl/wb_host/src/wb_host.sv
dineshannayya288d6942022-07-22 16:30:34 +0530[diff] [blame^]56-v $(USER_PROJECT_VERILOG)/rtl/sspis/src/sspis_top.sv
57-v $(USER_PROJECT_VERILOG)/rtl/sspis/src/sspis_if.sv
58-v $(USER_PROJECT_VERILOG)/rtl/sspis/src/spi2wb.sv
dineshannayya11a64182022-03-19 08:29:11 +0530[diff] [blame]59-v $(USER_PROJECT_VERILOG)/rtl/lib/async_wb.sv
60-v $(USER_PROJECT_VERILOG)/rtl/lib/sync_wbb.sv
61-v $(USER_PROJECT_VERILOG)/rtl/lib/sync_fifo2.sv
62-v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/src/wb_arb.sv
63-v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/src/wb_slave_port.sv
64-v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/src/wb_interconnect.sv
65
dineshannayyad8a093b2022-03-26 08:32:19 +0530[diff] [blame]66-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_hdu.sv
67-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_tdu.sv
68-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/core/pipeline/ycr_ipic.sv
69-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_csr.sv
70-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_exu.sv
71-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_ialu.sv
72-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_idu.sv
73-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_ifu.sv
74-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_lsu.sv
75-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_mprf.sv
76-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_mul.sv
77-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_div.sv
78-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_top.sv
79-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/core/primitives/ycr_reset_cells.sv
80-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/core/primitives/ycr_cg.sv
81-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/core/ycr_clk_ctrl.sv
82-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/core/ycr_tapc_shift_reg.sv
83-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/core/ycr_tapc.sv
84-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/core/ycr_tapc_synchronizer.sv
85-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/core/ycr_core_top.sv
86-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/core/ycr_dm.sv
87-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/core/ycr_dmi.sv
88-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/core/ycr_scu.sv
89-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/top/ycr_imem_router.sv
90-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/top/ycr_dmem_router.sv
91-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/top/ycr_dp_memory.sv
92-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/top/ycr_tcm.sv
93-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/top/ycr_timer.sv
94-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/top/ycr_dmem_wb.sv
95-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/top/ycr_imem_wb.sv
96-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/top/ycr_intf.sv
dineshannayya2ec4a8e2022-04-03 17:32:50 +0530[diff] [blame]97-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/top/ycr_sram_mux.sv
dineshannayyad8a093b2022-03-26 08:32:19 +0530[diff] [blame]98-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/top/ycr4_router.sv
99-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/top/ycr4_iconnect.sv
100-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/top/ycr4_cross_bar.sv
101-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/top/ycr4_top_wb.sv
102-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/top/ycr_icache_router.sv
103-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/top/ycr_dcache_router.sv
dineshannayyaa1ba62b2022-05-25 18:32:19 +0530[diff] [blame]104-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/top/ycr_req_retiming.sv
dineshannayyad8a093b2022-03-26 08:32:19 +0530[diff] [blame]105-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/cache/src/core/icache_top.sv
106-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/cache/src/core/icache_app_fsm.sv
107-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/cache/src/core/icache_tag_fifo.sv
108-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/cache/src/core/dcache_tag_fifo.sv
109-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/cache/src/core/dcache_top.sv
110-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/lib/ycr_async_wbb.sv
111-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/lib/ycr_arb.sv
dineshannayya11a64182022-03-19 08:29:11 +0530[diff] [blame]112
113-v $(USER_PROJECT_VERILOG)/rtl/lib/sync_fifo.sv
114-v $(USER_PROJECT_VERILOG)/rtl/uart2wb/src/uart2wb.sv
115-v $(USER_PROJECT_VERILOG)/rtl/uart2wb/src/uart2_core.sv
116-v $(USER_PROJECT_VERILOG)/rtl/uart2wb/src/uart_msg_handler.v
117-v $(USER_PROJECT_VERILOG)/rtl/lib/async_reg_bus.sv
118-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v
119-v $(USER_PROJECT_VERILOG)/rtl/lib/clk_skew_adjust.gv
120-v $(USER_PROJECT_VERILOG)/rtl/lib/ctech_cells.sv