ycr core timing cleanup
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
index f5f265c..14c6038 100644
--- a/verilog/includes/includes.rtl.caravel_user_project
+++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -91,6 +91,7 @@
-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/top/ycr_dmem_wb.sv
-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/top/ycr_imem_wb.sv
-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/top/ycr_intf.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/top/ycr_sram_mux.sv
-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/top/ycr4_router.sv
-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/top/ycr4_iconnect.sv
-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/top/ycr4_cross_bar.sv
