design fixed to take care of caravel wb address range reduced to 0xF_FFFF
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
new file mode 100644
index 0000000..5d917ec
--- /dev/null
+++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -0,0 +1,111 @@
+# Caravel user project includes
++incdir+$(USER_PROJECT_VERILOG)/rtl/i2cm/src/includes
++incdir+$(USER_PROJECT_VERILOG)/rtl/usb1_host/src/includes
++incdir+$(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/includes
++incdir+$(USER_PROJECT_VERILOG)/dv/model
++incdir+$(USER_PROJECT_VERILOG)/dv/agents
+-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pinmux.sv
+-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pinmux_reg.sv
+-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/gpio_intr.sv
+-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pwm.sv
+-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/timer.sv
+-v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type1.sv
+-v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type2.sv
+-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_top.sv
+-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_if.sv
+-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_fifo.sv
+-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_regs.sv
+-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_clkgen.sv
+-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_ctrl.sv
+-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_rx.sv
+-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_tx.sv
+-v $(USER_PROJECT_VERILOG)/rtl/uart/src/uart_core.sv
+-v $(USER_PROJECT_VERILOG)/rtl/uart/src/uart_cfg.sv
+-v $(USER_PROJECT_VERILOG)/rtl/uart/src/uart_rxfsm.sv
+-v $(USER_PROJECT_VERILOG)/rtl/uart/src/uart_txfsm.sv
+-v $(USER_PROJECT_VERILOG)/rtl/lib/async_fifo_th.sv
+-v $(USER_PROJECT_VERILOG)/rtl/lib/reset_sync.sv
+-v $(USER_PROJECT_VERILOG)/rtl/lib/double_sync_low.v
+-v $(USER_PROJECT_VERILOG)/rtl/lib/clk_buf.v
+-v $(USER_PROJECT_VERILOG)/rtl/i2cm/src/core/i2cm_bit_ctrl.v
+-v $(USER_PROJECT_VERILOG)/rtl/i2cm/src/core/i2cm_byte_ctrl.v
+-v $(USER_PROJECT_VERILOG)/rtl/i2cm/src/core/i2cm_top.v
+-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/core/usbh_core.sv
+-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/core/usbh_crc16.sv
+-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/core/usbh_crc5.sv
+-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/core/usbh_fifo.sv
+-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/core/usbh_sie.sv
+-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/phy/usb_fs_phy.v
+-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/phy/usb_transceiver.v
+-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/top/usb1_host.sv
+-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_top.sv
+-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_ctl.sv
+-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_if.sv
+-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_cfg.sv
+-v $(USER_PROJECT_VERILOG)/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv
+-v $(USER_PROJECT_VERILOG)/rtl/lib/async_fifo.sv
+-v $(USER_PROJECT_VERILOG)/rtl/lib/registers.v
+-v $(USER_PROJECT_VERILOG)/rtl/lib/clk_ctl.v
+-v $(USER_PROJECT_VERILOG)/rtl/lib/ser_inf_32b.sv
+-v $(USER_PROJECT_VERILOG)/rtl/lib/ser_shift.sv
+-v $(USER_PROJECT_VERILOG)/rtl/digital_core/src/glbl_cfg.sv
+-v $(USER_PROJECT_VERILOG)/rtl/wb_host/src/wb_host.sv
+-v $(USER_PROJECT_VERILOG)/rtl/lib/async_wb.sv
+-v $(USER_PROJECT_VERILOG)/rtl/lib/sync_wbb.sv
+-v $(USER_PROJECT_VERILOG)/rtl/lib/sync_fifo2.sv
+-v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/src/wb_arb.sv
+-v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/src/wb_slave_port.sv
+-v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/src/wb_interconnect.sv
+
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_hdu.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_tdu.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_ipic.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_csr.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_exu.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_ialu.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_idu.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_ifu.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_lsu.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_mprf.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_mul.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_div.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_top.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/primitives/ycr_reset_cells.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/primitives/ycr_cg.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/ycr_clk_ctrl.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/ycr_tapc_shift_reg.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/ycr_tapc.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/ycr_tapc_synchronizer.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/ycr_core_top.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/ycr_dm.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/ycr_dmi.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/ycr_scu.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_imem_router.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_dmem_router.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_dp_memory.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_tcm.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_timer.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_dmem_wb.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_imem_wb.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr2_mcore_router.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr2_intf.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr2_mintf.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr2_top_wb.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_icache_router.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_dcache_router.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/cache/src/core/icache_top.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/cache/src/core/icache_app_fsm.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/cache/src/core/icache_tag_fifo.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/cache/src/core/dcache_tag_fifo.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/cache/src/core/dcache_top.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/lib/ycr_async_wbb.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/lib/ycr_arb.sv
+
+-v $(USER_PROJECT_VERILOG)/rtl/lib/sync_fifo.sv
+-v $(USER_PROJECT_VERILOG)/rtl/uart2wb/src/uart2wb.sv
+-v $(USER_PROJECT_VERILOG)/rtl/uart2wb/src/uart2_core.sv
+-v $(USER_PROJECT_VERILOG)/rtl/uart2wb/src/uart_msg_handler.v
+-v $(USER_PROJECT_VERILOG)/rtl/lib/async_reg_bus.sv
+-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v
+-v $(USER_PROJECT_VERILOG)/rtl/lib/clk_skew_adjust.gv
+-v $(USER_PROJECT_VERILOG)/rtl/lib/ctech_cells.sv
