Google Git
Sign in
foss-eda-tools / third_party / shuttle / sky130 / mpw-006 / slot-004 / df55286595a1af1c67952a3aab10389a00832cd7 / . / verilog / dv / user_timer / Makefile
blob: 64791205c14439b047eb0f08a54b0dcccac342e8 [file] [log] [blame]
dineshannayya11a64182022-03-19 08:29:11 +0530[diff] [blame]1# SPDX-FileCopyrightText: 2020 Efabless Corporation
2#
3# Licensed under the Apache License, Version 2.0 (the "License");
4# you may not use this file except in compliance with the License.
5# You may obtain a copy of the License at
6#
7# http://www.apache.org/licenses/LICENSE-2.0
8#
9# Unless required by applicable law or agreed to in writing, software
10# distributed under the License is distributed on an "AS IS" BASIS,
11# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12# See the License for the specific language governing permissions and
13# limitations under the License.
14#
15# SPDX-License-Identifier: Apache-2.0
16
dineshannayya11a64182022-03-19 08:29:11 +0530[diff] [blame]17
dineshannayya54cd5f62022-04-02 17:08:28 +0530[diff] [blame]18# ---- Include Partitioned Makefiles ----
dineshannayya11a64182022-03-19 08:29:11 +0530[diff] [blame]19
dineshannayya54cd5f62022-04-02 17:08:28 +0530[diff] [blame]20CONFIG = caravel_user_project
21
22#######################################################################
23## Caravel Verilog for Integration Tests
24#######################################################################
dineshannayya11a64182022-03-19 08:29:11 +0530[diff] [blame]25
dineshannayya54cd5f62022-04-02 17:08:28 +0530[diff] [blame]26DESIGNS?=../../..
dineshannayyadf552862022-07-08 10:03:52 +0530[diff] [blame^]27TOOLS?=/opt/riscv32i/
dineshannayya54cd5f62022-04-02 17:08:28 +0530[diff] [blame]28
29export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
dineshannayya11a64182022-03-19 08:29:11 +0530[diff] [blame]30## YIFIVE FIRMWARE
dineshannayya54cd5f62022-04-02 17:08:28 +0530[diff] [blame]31YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
dineshannayyadf552862022-07-08 10:03:52 +0530[diff] [blame^]32GCC_PREFIX?=riscv32-unknown-elf
dineshannayya11a64182022-03-19 08:29:11 +0530[diff] [blame]33
dineshannayya11a64182022-03-19 08:29:11 +0530[diff] [blame]34
35## Simulation mode: RTL/GL
36SIM?=RTL
37DUMP?=OFF
dineshannayya54cd5f62022-04-02 17:08:28 +0530[diff] [blame]38RISC_CORE?=0
dineshannayya11a64182022-03-19 08:29:11 +0530[diff] [blame]39
dineshannayyad1cb6912022-03-20 13:46:04 +0530[diff] [blame]40### To Enable IVERILOG FST DUMP
41export IVERILOG_DUMPER = fst
42
43
dineshannayya11a64182022-03-19 08:29:11 +0530[diff] [blame]44.SUFFIXES:
45
46PATTERN = user_timer
47
48all: ${PATTERN:=.vcd}
49
50
51vvp: ${PATTERN:=.vvp}
52
53%.vvp: %_tb.v
54ifeq ($(SIM),RTL)
55 ifeq ($(DUMP),OFF)
dineshannayya54cd5f62022-04-02 17:08:28 +0530[diff] [blame]56 iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
57 -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
dineshannayya9be29722022-05-29 19:09:57 +0530[diff] [blame]58 -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
dineshannayya11a64182022-03-19 08:29:11 +0530[diff] [blame]59 $< -o $@
60 else
dineshannayya54cd5f62022-04-02 17:08:28 +0530[diff] [blame]61 iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
62 -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
dineshannayya9be29722022-05-29 19:09:57 +0530[diff] [blame]63 -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
dineshannayya11a64182022-03-19 08:29:11 +0530[diff] [blame]64 $< -o $@
65 endif
66else
dineshannayyaaa5e4bf2022-04-18 22:48:28 +0530[diff] [blame]67 ifeq ($(DUMP),OFF)
68 iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
69 -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
70 -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
dineshannayya11a64182022-03-19 08:29:11 +0530[diff] [blame]71 $< -o $@
dineshannayyaaa5e4bf2022-04-18 22:48:28 +0530[diff] [blame]72 else
73 iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
74 -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
75 -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
76 $< -o $@
77 endif
dineshannayya11a64182022-03-19 08:29:11 +0530[diff] [blame]78endif
79
80%.vcd: %.vvp
81 vvp $<
82
dineshannayya11a64182022-03-19 08:29:11 +0530[diff] [blame]83
84# ---- Clean ----
85
86clean:
87 rm -f *.vvp *.vcd *.log *.fst
88
89.PHONY: clean hex all