commit aa5e4bfdf6d8a177da79aba444803be41d40e6db
author dineshannayya <dinesh.annayya@gmail.com> Mon Apr 18 22:48:28 2022 +0530
committer dineshannayya <dinesh.annayya@gmail.com> Mon Apr 18 22:48:28 2022 +0530
tree 62956171e9bcb8a35352a585031fab9041c4ef84
parent 8154f8e1d9b96d5bb65bb59d42116da39c7150e6

gls clean up

verilog/dv/user_timer/Makefile

diff --git a/verilog/dv/user_timer/Makefile b/verilog/dv/user_timer/Makefile
index 6d04ada..0cc574f 100644
--- a/verilog/dv/user_timer/Makefile
+++ b/verilog/dv/user_timer/Makefile
@@ -62,9 +62,17 @@
 	$< -o $@ 
    endif
 else  
-	iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
-	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+   ifeq ($(DUMP),OFF)
+	iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
 	$< -o $@ 
+    else  
+	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+	$< -o $@ 
+   endif
 endif
 
 %.vcd: %.vvp