Riscduino Dual Risc Core SOC
Permission to use, copy, modify, and/or distribute this soc for any
purpose with or without fee is hereby granted, provided that the above
copyright notice and this permission notice appear in all copies.
THE SOC IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
WITH REGARD TO THIS SOC INCLUDING ALL IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOC.
Table of contents
Overview
Riscduino is a Dual 32 bit RISC V based SOC design pin compatible to arudino platform and this soc targetted for efabless Shuttle program. This project uses only open source tool set for simulation,synthesis and backend tools. The SOC flow follow the openlane methodology and SOC environment is compatible with efabless/carvel methodology.
Riscduino Block Diagram
Key features
* Open sourced under Apache-2.0 License (see LICENSE file) - unrestricted commercial use allowed.
* Dual 32 Bit RISC-V core
* 2KB SRAM for instruction cache
* 2KB SRAM for data cache
* 2KB SRAM for Tightly coupled memory - For Data Memory
* Quad SPI Master with 4 Chip select, supports both SPI flash and SRAM interface
* 2 x UART with 16Byte FIFO
* USB 1.1 Host
* I2C Master
* UART Master
* Simple SPI Master with 4 Chip select
* 6 Channel ADC (in Progress)
* 6 x PWM
* 3 x Timer (16 Bit), 1us/1ms/1second resolution
* Pin Compatbible to arudino uno
* Wishbone compatible design
* Written in System Verilog
* Open-source tool set
* simulation - iverilog
* synthesis - yosys
* backend/sta - openlane tool set
* Verification suite provided.
Riscduino derivatives
MPW Shuttle on Riscduino
SOC Pin Mapping
Carvel SOC provides 38 GPIO pins for user functionality. Riscduino SOC GPIO Pin Mapping as follows vs ATMEGA328 and Arudino
RISC V Core
Riscduino SOC Integrated Dual 32 Bits RISC V core. Initial version of Single core RISC-V core is picked from Syntacore SCR1 (https://github.com/syntacore/scr1)
RISC V core customization for Riscduino SOC
Following Design changes are done on the basic version of syntacore RISC core
* Some of the sv syntex are changed to standard verilog format to make compatibile with opensource tool iverilog & yosys
* local Instruction Memory depth increased from 4 to 8 location
* Instruction Mem Request are changed from Single word to 4 Word Burst
* Multiplication and Divsion are changed to improve timing
* Additional pipe line stages added to improve the RISC timing closure near to 50Mhz
* 2KB instruction cache
* 2KB data cache
* Additional router are added towards instruction cache
* Additional router are added towards data cache
* Dual core related changes
* Modified AXI/AHB interface to wishbone interface for instruction and data memory interface
Block Diagram
RISC V Core Key feature
* RV32I or RV32E ISA base + optional RVM and RVC standard extensions
* Machine privilege mode only
* 2 to 5 stage pipeline
* 2KB icache
* 2KB dcache
* Optional Integrated Programmable Interrupt Controller with 16 IRQ lines
* Optional RISC-V Debug subsystem with JTAG interface
* Optional on-chip Tightly-Coupled Memory
6 Channel SAR ADC
In Process - Looking for community help ...
SOC Memory Map
SOC Size
| Block | Total Cell | Seq | Combo |
|---|
| RISC | 20982 | 3164 | 17818 |
| PINMUX | 5693 | 1022 | 4671 |
| SPI | 7120 | 1281 | 5839 |
| UART_I2C_USB_SPI | 11196 | 2448 | 8748 |
| WB_HOST | 2796 | 588 | 2208 |
| WB_INTC | 1878 | 108 | 1770 |
| SAR_ADC | 118 | 18 | 100 |
| MBIST | 3125 | 543 | 2582 |
| | | |
| TOTAL | 52908 | 9172 | 43736 |
SOC Register Map
Register Map: Wishbone HOST
| Offset | Name | Description |
|---|
| 0x00 | GLBL_CTRL | [RW] Global Wishbone Access Control Register |
| 0x04 | BANK_CTRL | [RW] Bank Selection, MSB 8 bit Address |
| 0x08 | CLK_SKEW_CTRL1 | [RW] Clock Skew Control2 |
| 0x0c | CLK_SKEW_CTRL2 | [RW] Clock Skew Control2 |
Register: GLBL_CTRL
| Bits | Name | Description |
|---|
| 31:24 | Resevered | Unsused |
| 23:20 | RTC_CLK_CTRL | RTC Clock Div Selection |
| 19:16 | CPU_CLK_CTRL | CPU Clock Div Selection |
| 15:12 | SDARM_CLK_CTRL | SDRAM Clock Div Selection |
| 10:8 | WB_CLK_CTRL | Core Wishbone Clock Div Selection |
| 7 | UART_I2C_SEL | 0 - UART , 1 - I2C Master IO Selection |
| 5 | I2C_RST | I2C Reset Control |
| 4 | UART_RST | UART Reset Control |
| 3 | SDRAM_RST | SDRAM Reset Control |
| 2 | SPI_RST | SPI Reset Control |
| 1 | CPU_RST | CPU Reset Control |
| 0 | WB_RST | Wishbone Core Reset Control |
Register: BANK_CTRL
| Bits | Name | Description |
|---|
| 31:24 | Resevered | Unsused |
| 7:0 | BANK_SEL | Holds the upper 8 bit address core Wishbone Address |
Register: CLK_SKEW_CTRL1
| Bits | Name | Description |
|---|
| 31:28 | Resevered | Unsused |
| 27:24 | CLK_SKEW_WB | WishBone Core Clk Skew Control |
| 23:20 | CLK_SKEW_GLBL | Glbal Register Clk Skew Control |
| 19:16 | CLK_SKEW_SDRAM | SDRAM Clk Skew Control |
| 15:12 | CLK_SKEW_SPI | SPI Clk Skew Control |
| 11:8 | CLK_SKEW_UART | UART/I2C Clk Skew Control |
| 7:4 | CLK_SKEW_RISC | RISC Clk Skew Control |
| 3:0 | CLK_SKEW_WI | Wishbone Clk Skew Control |
Register Map: SPI MASTER
| Offset | Name | Description |
|---|
| 0x00 | GLBL_CTRL | [RW] Global SPI Access Control Register |
| 0x04 | DMEM_CTRL1 | [RW] Direct SPI Memory Access Control Register1 |
| 0x08 | DMEM_CTRL2 | [RW] Direct SPI Memory Access Control Register2 |
| 0x0c | IMEM_CTRL1 | [RW] Indirect SPI Memory Access Control Register1 |
| 0x10 | IMEM_CTRL2 | [RW] Indirect SPI Memory Access Control Register2 |
| 0x14 | IMEM_ADDR | [RW] Indirect SPI Memory Address |
| 0x18 | IMEM_WDATA | [W] Indirect SPI Memory Write Data |
| 0x1c | IMEM_RDATA | [R] Indirect SPI Memory Read Data |
| 0x20 | SPI_STATUS | [R] SPI Debug Status |
Register: GLBL_CTRL
| Bits | Name | Description |
|---|
| 31:16 | Resevered | Unsused |
| 15:8 | SPI_CLK_DIV | SPI Clock Div Rato Selection |
| 7:4 | Reserved | Unused |
| 3:2 | CS_LATE | CS DE_ASSERTION CONTROL |
| 1:0 | CS_EARLY | CS ASSERTION CONTROL |
Register: DMEM_CTRL1
| Bits | Name | Description |
|---|
| 31:9 | Resevered | Unsused |
| 8 | FSM_RST | Direct Mem State Machine Reset |
| 7:6 | SPI_SWITCH | Phase at which SPI Mode need to switch |
| 5:4 | SPI_MODE | SPI Mode, 0 - Single, 1 - Dual, 2 - Quad, 3 - QDDR |
| 3:0 | CS_SELECT | CHIP SELECT |
Register: DMEM_CTRL2
| Bits | Name | Description |
|---|
| 31:24 | DATA_CNT | Total Data Byte Count |
| 23:22 | DUMMY_CNT | Total Dummy Byte Count |
| 21:20 | ADDR_CNT | Total Address Byte Count |
| 19:16 | SPI_SEQ | SPI Access Sequence |
| 15:8 | MODE_REG | Mode Register Value |
| 7:0 | CMD_REG | Command Register Value |
Register: IMEM_CTRL1
| Bits | Name | Description |
|---|
| 31:9 | Resevered | Unsused |
| 8 | FSM_RST | InDirect Mem State Machine Reset |
| 7:6 | SPI_SWITCH | Phase at which SPI Mode need to switch |
| 5:4 | SPI_MODE | SPI Mode, 0 - Single, 1 - Dual, 2 - Quad, 3 - QDDR |
| 3:0 | CS_SELECT | CHIP SELECT |
Register: IMEM_CTRL2
| Bits | Name | Description |
|---|
| 31:24 | DATA_CNT | Total Data Byte Count |
| 23:22 | DUMMY_CNT | Total Dummy Byte Count |
| 21:20 | ADDR_CNT | Total Address Byte Count |
| 19:16 | SPI_SEQ | SPI Access Sequence |
| 15:8 | MODE_REG | Mode Register Value |
| 7:0 | CMD_REG | Command Register Value |
Register: IMEM_ADDR
| Bits | Name | Description |
|---|
| 31:0 | ADDR | Indirect Memory Address |
Register: IMEM_WDATA
| Bits | Name | Description |
|---|
| 31:0 | WDATA | Indirect Memory Write Data |
Register: IMEM_RDATA
| Bits | Name | Description |
|---|
| 31:0 | RDATA | Indirect Memory Read Data |
Register: SPI_STATUS
| Bits | Name | Description |
|---|
| 31:0 | DEBUG | SPI Debug Status |
Register Map: Global Register
| Offset | Name | Description |
|---|
| 0x00 | SOFT_REG0 | [RW] Software Register0 |
| 0x04 | RISC_FUSE | [RW] Risc Fuse Value |
| 0x08 | SOFT_REG2 | [RW] Software Register2 |
| 0x0c | INTR_CTRL | [RW] Interrupt Control |
| 0x10 | SDRAM_CTRL1 | [RW] Indirect SPI Memory Access Control Register2 |
| 0x14 | SDRAM_CTRL2 | [RW] Indirect SPI Memory Address |
| 0x18 | SOFT_REG6 | [RW] Software Register6 |
| 0x1C | SOFT_REG7 | [RW] Software Register7 |
| 0x20 | SOFT_REG8 | [RW] Software Register8 |
| 0x24 | SOFT_REG9 | [RW] Software Register9 |
| 0x28 | SOFT_REG10 | [RW] Software Register10 |
| 0x2C | SOFT_REG11 | [RW] Software Register11 |
| 0x30 | SOFT_REG12 | [RW] Software Register12 |
| 0x34 | SOFT_REG13 | [RW] Software Register13 |
| 0x38 | SOFT_REG14 | [RW] Software Register14 |
| 0x3C | SOFT_REG15 | [RW] Software Register15 |
Register: RISC_FUSE
| Bits | Name | Description |
|---|
| 31:0 | RISC_FUSE | RISC Core Fuse Value |
Register: INTR_CTRL
| Bits | Name | Description |
|---|
| 31:20 | Reserved | Unused |
| 19:17 | USER_IRQ | User Interrupt generation toward riscv |
| 16 | SOFT_IRQ | Software Interrupt generation toward riscv |
| 15:0 | EXT_IRQ | External Interrupt generation toward riscv |
Repository contents
|verilog
| ├─ rtl
| | |- syntacore
| | | |─ scr1
| | | | ├─ **docs** | **SCR1 documentation**
| | | | | ├─ scr1_eas.pdf | SCR1 External Architecture Specification
| | | | | └─ scr1_um.pdf | SCR1 User Manual
| | | | |─ **src** | **SCR1 RTL source and testbench files**
| | | | | ├─ includes | Header files
| | | | | ├─ core | Core top source files
| | | | | ├─ top | Cluster source files
| | | | |─ **synth** | **SCR1 RTL Synthesis files **
| | |- Qspi_master
| | | |- src | Qard SPI Master Source files
| | |-wb_interconnect
| | | |- src | 3x4 Wishbone Interconnect
| | |- digital_core
| | | |- src | Digital core Source files
| | |- lib | common library source files
| |- dv
| | |- la_test1 | carevel LA test
| | |- risc_boot | user core risc boot test
| | |- wb_port | user wishbone test
| | |- user_risc_boot | user standalone test without carevel soc
| |- gl | ** GLS Source files **
|
|- openlane
|- spi_master | spi_master openlane scripts
|- syntacore | Risc Core openlane scripts
|- user_project_wrapper | carvel user project wrapper
Prerequisites
- Docker (ensure docker daemon is running) -- tested with version 19.03.12, but any recent version should suffice.
Step-1: Docker in ubuntu 20.04 version
sudo apt update
sudo apt-get install apt-transport-https curl rtificates -agent software-properties-common
curl -fsSL https://download.docker.com/linux/ubuntu/gpg | sudo apt-key add -
sudo add-apt-repository "deb [arch=amd64] https://download.docker.com/linux/ubuntu focal stable"
sudo apt update
apt-cache policy docker-ce
sudo apt install docker-ce
#Add User Name to docker
sudo usermod -aG docker <your user name>
# Reboot the system to enable the docker setup
Step-2: Clone , update the Submodule, unzip the content
git clone https://github.com/dineshannayya/riscduino.git
cd riscduino
git submodule init
git submodule update
make unzip
Note-1: RTL to GDS Docker
- Required openlane and pdk are moved inside the riscduino docker to avoid the external dependency.
- flow automatically pull the required docker based on MPW version.
- RTL to gds docker is hardcoded inside File: openlane/Makefile
OPENLANE_TAG = mpw6
OPENLANE_IMAGE_NAME = riscduino/openlane:$(OPENLANE_TAG)
Note-1.1: View the RTL to GDS Docker content
- for MPW-6 caravel pdk and openlane avaible inside riscduino/openlane:mpw6 docker
- caravel, openlane and pdk envionment are automatically pointed to internal docker pointer
- To view the docker contents
docker run -ti --rm riscduino/openlane:mpw6 bash
cd /opt/pdk_mpw6 - pdk folder
cd /opt/caravel - caravel folder
cd /openlane - openlane folder
env - Show the internally defined env's
CARAVEL_ROOT=/opt/caravel
PDK_ROOT=/opt/pdk_mpw6
Note-2: RTL Simulation Docker
- Required caravel and pdk are moved inside the riscduino docker to avoid the external dependency.
- flow automatically pull the required docker based on MPW version.
- To view the docker contents
- RTL simulation docker hardcoded inside File: Makefile
simenv:
docker pull riscduino/dv_setup:mpw6
Note-2.1: View the RTL Simulation Docker content
- for MPW-6 caravel and pdk avaible inside riscduino/dv_setup:mpw6 docker this is used for RTL to gds flows
- caravel and pdk envionment are automatically pointed to internal docker pointer
- To view the docker contents
docker run -ti --rm riscduino/dv_setup:mpw6 bash
cd /opt/pdk_mpw6 - pdk folder
cd /opt/caravel - caravel folder
env - Show the internally defined env's
CARAVEL_ROOT=/opt/caravel
PDK_ROOT=/opt/pdk_mpw6
Tests preparation
The simulation package includes the following tests:
- risc_boot - Complete caravel User Risc core boot
- wb_port - Complete caravel User Wishbone validation
- uart_master - complete caravel user uart master test
- user_risc_boot - Standalone User Risc core boot
- user_sspi - Standalone SSPI test
- user_qspi - Standalone Quad SPI test
- user_spi - Standalone SPI test
- user_i2c - Standalone I2C test
- user_usb - Standalone USB Host test
- user_risc_boot - Standalone Risc Boot test
- user_uart - Standalone Risc with UART-0 Test
- user_uart1 - Standalone Risc with UART-1 Test
- user_gpio - Standalone GPIO Test
- user_pwm - Standalone pwm Test
- user_timer - Standalone timer Test
- user_uart_master - Standalone uart master test
- riscv_regress - Standalone riscv compliance and regression test suite
Running Simulation
Examples:
make verify-wb_port - User Wishbone Test from caravel
make verify-risc_boot - User Risc core test from caravel
make verify-uart_master - User uart master test from caravel
make verify-user_basic - Standalone Basic signal and clock divider test
make verify-user_uart - Standalone user uart-0 test using user risc core
make verify-user_uart1 - Standalone user uart-0 test using user risc core
make verify-user_i2cm - Standalone user i2c test
make verify-user_risc_boot - standalone user risc core-0 boot test
make verify-user_pwm - standalone user pwm test
make verify-user_timer - standalone user timer test
make verify-user_sspi - standalone user spi test
make verify-user_qspi - standalone user quad spi test
make verify-user_usb - standalone user usb host test
make verify-user_gpio - standalone user gpio test
make verify-user_aes - standalone aes test with risc core-0
make verify-user_cache_bypass - standalone icache and dcache bypass test with risc core-0
make verify-user_uart_master - standalone user uart master test
make verify-user_sram_exec - standalone riscv core-0 test with executing code from data memory
make verify-riscv_regress - standalone riscv compliance test suite
make verify-arudino_risc_boot - standalone riscv core-0 boot using arduino tool set
make verify-arudino_hello_world - standalone riscv core-0 hello world test using arduino tool set
make verify-user_mcore - standalone riscv multi-core test
make verify-user_sram_exec RISC_CORE=1 - standalone riscv core-1 test with executing code from data memory
make verify-user_risc_boot RISC_CORE=1 - standalone user risc core-1 boot test
make verify-user_uart RISC_CORE=1 - Standalone user uart test using user risc core-1
make verify-user_uart1 RISC_CORE=1 - Standalone user uart test using user risc core-1
make verify-user_aes RISC_CORE=1 - standalone aes test with risc core-1
make verify-user_cache_bypass RISC_CORE=1 - standalone icache and dcache bypass test with risc core-1
make verify-arudino_risc_boot RISC_CORE=1 - standalone riscv core-1 boot using arduino tool set
make verify-arudino_hello_world RISC_CORE=1 - standalone riscv core-1 hello world test using arduino tool set
make verify-user_uart SIM=RTL DUMP=OFF - Standalone user uart-0 test using user risc core with waveform dump off
make verify-user_uart SIM=RTL DUMP=ON - Standalone user uart-0 test using user risc core with waveform dump on
make verify-user_uart SIM=GL DUMP=OFF - Standalone user uart-0 test using user risc core with gatelevel netlist
make verify-user_uart SIM=GL DUMP=ON - Standalone user uart-0 test using user risc core with gatelevel netlist and waveform on
Running RTL to GDS flows
- First run the individual macro file
- Last run the user_project_wrapper
cd openlane
make pinmux
make qspim_top
make uart_i2cm_usb_spi_top
make wb_host
make wb_interconnect
make ycr_intf
make ycr_core_top
make ycr_iconnect
make user_project_wrapper
Tool Sets
Riscduino Soc flow uses Openlane tool sets.
- Synthesis
yosys - Performs RTL synthesisabc - Performs technology mappingOpenSTA - Pefroms static timing analysis on the resulting netlist to generate timing reports
- Floorplan and PDN
init_fp - Defines the core area for the macro as well as the rows (used for placement) and the tracks (used for routing)ioplacer - Places the macro input and output portspdn - Generates the power distribution networktapcell - Inserts welltap and decap cells in the floorplan
- Placement
RePLace - Performs global placementResizer - Performs optional optimizations on the designOpenPhySyn - Performs timing optimizations on the designOpenDP - Perfroms detailed placement to legalize the globally placed components
- CTS
TritonCTS - Synthesizes the clock distribution network (the clock tree)
- Routing
FastRoute - Performs global routing to generate a guide file for the detailed routerCU-GR - Another option for performing global routing.TritonRoute - Performs detailed routingSPEF-Extractor - Performs SPEF extraction
- GDSII Generation
Magic - Streams out the final GDSII layout file from the routed defKlayout - Streams out the final GDSII layout file from the routed def as a back-up
- Checks
Magic - Performs DRC Checks & Antenna ChecksKlayout - Performs DRC ChecksNetgen - Performs LVS ChecksCVC - Performs Circuit Validity Checks
Riscduino documentation
Riscduino documentation available at <https://riscduino.readthedocs.io/en/latest/>
Arduino ide integration
We are in initial phase of Riscduino board integration into arduino and integration details are available at <https://github.com/dineshannayya/riscduino_board/>
News
How To Contribute
We are looking for community help in following activity, interested user can ping me in efabless slack platform
- Analog Design - ADC, DAC, PLL,
- Digital Design - New IP Integration, Encription,DSP, Floating point functions
- Verification - Improving the Verification flow
- Linux Porting - Build Root integration
- Arudino Software Update - Tool Customisation for Riscduino, Adding additional plug-in and Riscv compilation support
- Riscv Simulator - integration to Riscduino
- Any other ideas
Contacts
Report an issue: https://github.com/dineshannayya/riscduino_dcore/issues
Documentation
News on Riscduino
