UPDATE: wb_port verification for wbuart32
diff --git a/Makefile b/Makefile index e787f93..9bb954a 100644 --- a/Makefile +++ b/Makefile
@@ -79,13 +79,15 @@ docker_run_verify=\ docker run -v ${TARGET_PATH}:${TARGET_PATH} -v ${PDK_ROOT}:${PDK_ROOT} \ -v ${CARAVEL_ROOT}:${CARAVEL_ROOT} \ + -v ${MCW_ROOT}:${MCW_ROOT} \ -e TARGET_PATH=${TARGET_PATH} -e PDK_ROOT=${PDK_ROOT} \ -e CARAVEL_ROOT=${CARAVEL_ROOT} \ -e TOOLS=/opt/riscv32i \ -e DESIGNS=$(TARGET_PATH) \ - -e CORE_VERILOG_PATH=$(TARGET_PATH)/mgmt_core_wrapper/verilog \ + -e CORE_VERILOG_PATH=$(MCW_ROOT)/verilog \ -e GCC_PREFIX=riscv32-unknown-elf \ -e MCW_ROOT=$(MCW_ROOT) \ + -e CARAVEL_PATH=$(CARAVEL_ROOT) \ -u $$(id -u $$USER):$$(id -g $$USER) efabless/dv_setup:latest \ sh -c $(verify_command)
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/wb_port/Makefile index 3fd0b56..b07bb75 100644 --- a/verilog/dv/wb_port/Makefile +++ b/verilog/dv/wb_port/Makefile
@@ -20,7 +20,8 @@ BLOCKS := $(shell basename $(PWDD)) # ---- Include Partitioned Makefiles ---- - +CARAVEL_PATH = $(CARAVEL_ROOT) +CARAVEL_VERILOG_PATH = $(CARAVEL_ROOT)/verilog CONFIG = caravel_user_project @@ -28,5 +29,3 @@ include $(MCW_ROOT)/verilog/dv/make/var.makefile include $(MCW_ROOT)/verilog/dv/make/cpu.makefile include $(MCW_ROOT)/verilog/dv/make/sim.makefile - -
diff --git a/verilog/dv/wb_port/wb_port.c b/verilog/dv/wb_port/wb_port.c index 4f59055..b5d1fa0 100644 --- a/verilog/dv/wb_port/wb_port.c +++ b/verilog/dv/wb_port/wb_port.c
@@ -25,6 +25,13 @@ - Checks counter value through the wishbone port */ +#define reg_UART_SETUP (*(volatile uint32_t*)0x30001000) +#define reg_UART_FIFO (*(volatile uint32_t*)0x30001004) +#define reg_UART_RX_DATA (*(volatile uint32_t*)0x30001008) +#define reg_UART_TX_DATA (*(volatile uint32_t*)0x3000100C) + + + void main() { @@ -70,6 +77,9 @@ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT; reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT; reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_15 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT; + /* Apply configuration */ reg_mprj_xfer = 1; @@ -80,8 +90,15 @@ // Flag start of the test reg_mprj_datal = 0xAB600000; - reg_mprj_slave = 0x00002710; - if (reg_mprj_slave == 0x2B3D) { + /* UART Setup: */ + /* 8-N-1 115200B for 50Mhz System Clock */ + reg_UART_SETUP = 434; + + + /* Send a data via UART */ + reg_UART_TX_DATA = 0x0000DE; + + if (reg_mprj_datal == 0xAB608000) { reg_mprj_datal = 0xAB610000; } }
diff --git a/verilog/dv/wb_port/wb_port_tb.v b/verilog/dv/wb_port/wb_port_tb.v index d5c2983..8bc519c 100644 --- a/verilog/dv/wb_port/wb_port_tb.v +++ b/verilog/dv/wb_port/wb_port_tb.v
@@ -17,6 +17,7 @@ `timescale 1 ns / 1 ps + module wb_port_tb; reg clock; reg RSTB;
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project index 31ab09b..f714ae3 100644 --- a/verilog/includes/includes.rtl.caravel_user_project +++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -1,5 +1,12 @@ -# Caravel user project includes --v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v +# Caravel user project includes +-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v -v $(USER_PROJECT_VERILOG)/rtl/user_proj_example.v - - \ No newline at end of file +-v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/wb_interconnect.sv +-v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/wb_stagging.sv +-v $(USER_PROJECT_VERILOG)/rtl/wbuart32/rxuart.v +-v $(USER_PROJECT_VERILOG)/rtl/wbuart32/txuart.v +-v $(USER_PROJECT_VERILOG)/rtl/wbuart32/rxuartlite.v +-v $(USER_PROJECT_VERILOG)/rtl/wbuart32/txuartlite.v +-v $(USER_PROJECT_VERILOG)/rtl/wbuart32/ufifo.v +-v $(USER_PROJECT_VERILOG)/rtl/wbuart32/skidbuffer.v +-v $(USER_PROJECT_VERILOG)/rtl/wbuart32/wbuart.v
diff --git a/verilog/includes/includes.rtl.secure-memory b/verilog/includes/includes.rtl.secure-memory new file mode 100644 index 0000000..278e739 --- /dev/null +++ b/verilog/includes/includes.rtl.secure-memory
@@ -0,0 +1,12 @@ +# Caravel user project includes +-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v +-v $(USER_PROJECT_VERILOG)/rtl/user_proj_example.v +-v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/wb_interconnect.sv +-v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/wb_stagging.sv +-v $(USER_PROJECT_VERILOG)/rtl/wbuart32/rxuart.v +-v $(USER_PROJECT_VERILOG)/rtl/wbuart32/txuart.v +-v $(USER_PROJECT_VERILOG)/rtl/wbuart32/rxuartlite.v +-v $(USER_PROJECT_VERILOG)/rtl/wbuart32/txuartlite.v +-v $(USER_PROJECT_VERILOG)/rtl/wbuart32/ufifo.v +-v $(USER_PROJECT_VERILOG)/rtl/wbuart32/skidbuffer.v +-v $(USER_PROJECT_VERILOG)/rtl/wbuart32/wbuart.v \ No newline at end of file
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v index 2293934..3ae9bc1 100644 --- a/verilog/rtl/user_proj_example.v +++ b/verilog/rtl/user_proj_example.v
@@ -217,8 +217,8 @@ .o_wb_stall ( ), .o_wb_ack (s1_wb_ack_o ), .o_wb_data (s1_wb_dat_o ), - .i_uart_rx (io_in[0] ), - .o_uart_tx (io_out[0] ), + .i_uart_rx (io_in[15] ), + .o_uart_tx (io_out[14] ), .i_cts_n (1'b0 ), .o_rts_n ( ), .o_uart_rx_int ( ),
diff --git a/verilog/rtl/wb_interconnect/wb_interconnect.sv b/verilog/rtl/wb_interconnect/wb_interconnect.sv index 4631887..e76b65a 100644 --- a/verilog/rtl/wb_interconnect/wb_interconnect.sv +++ b/verilog/rtl/wb_interconnect/wb_interconnect.sv
@@ -201,7 +201,7 @@ // Generate Multiplexed Slave Interface based on target Id wire [3:0] s_wb_tid = s_bus_wr.wb_tid; // to fix iverilog warning -always_comb begin +always begin case(s_wb_tid) 2'b00: s_bus_rd = s0_wb_rd; 2'b01: s_bus_rd = s1_wb_rd;