verilog/includes/includes.rtl.caravel_user_project

# Caravel user project includes	     
-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v
-v $(USER_PROJECT_VERILOG)/rtl/user_proj_example.v
-v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/wb_interconnect.sv
-v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/wb_stagging.sv
-v $(USER_PROJECT_VERILOG)/rtl/wbuart32/rxuart.v
-v $(USER_PROJECT_VERILOG)/rtl/wbuart32/txuart.v
-v $(USER_PROJECT_VERILOG)/rtl/wbuart32/rxuartlite.v
-v $(USER_PROJECT_VERILOG)/rtl/wbuart32/txuartlite.v
-v $(USER_PROJECT_VERILOG)/rtl/wbuart32/ufifo.v
-v $(USER_PROJECT_VERILOG)/rtl/wbuart32/skidbuffer.v
-v $(USER_PROJECT_VERILOG)/rtl/wbuart32/wbuart.v