MERGE: SRAM to UART
diff --git a/Makefile b/Makefile index 9bb954a..381430b 100644 --- a/Makefile +++ b/Makefile
@@ -17,7 +17,7 @@ CARAVEL_ROOT?=$(PWD)/caravel PRECHECK_ROOT?=${HOME}/mpw_precheck -MCW_ROOT?=$(PWD)/mgmt_core_wrapper +MCW_ROOT?=$(UPRJ_ROOT)/mgmt_core_wrapper SIM?=RTL export SKYWATER_COMMIT=c094b6e83a4f9298e47f696ec5a7fd53535ec5eb @@ -79,7 +79,11 @@ docker_run_verify=\ docker run -v ${TARGET_PATH}:${TARGET_PATH} -v ${PDK_ROOT}:${PDK_ROOT} \ -v ${CARAVEL_ROOT}:${CARAVEL_ROOT} \ +<<<<<<< HEAD -v ${MCW_ROOT}:${MCW_ROOT} \ +======= + -v $(MCW_ROOT):$(MCW_ROOT) \ +>>>>>>> sram -e TARGET_PATH=${TARGET_PATH} -e PDK_ROOT=${PDK_ROOT} \ -e CARAVEL_ROOT=${CARAVEL_ROOT} \ -e TOOLS=/opt/riscv32i \ @@ -176,7 +180,7 @@ .PHONY: clean clean: cd ./verilog/dv/ && \ - $(MAKE) -j$(THREADS) clean + $(MAKE) clean check-caravel: @if [ ! -d "$(CARAVEL_ROOT)" ]; then \
diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl index c9266ee..94eecca 100755 --- a/openlane/user_proj_example/config.tcl +++ b/openlane/user_proj_example/config.tcl
@@ -22,7 +22,12 @@ set ::env(VERILOG_FILES) "\ $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \ - $script_dir/../../verilog/rtl/user_proj_example.v" + $script_dir/../../verilog/rtl/user_proj_example.v \ + $script_dir/../../verilog/rtl/wb_interconnect/wb_interconnect.sv \ + $script_dir/../../verilog/rtl/wb_interconnect/wb_signal_reg.sv \ + $script_dir/../../verilog/rtl/sram/sky130_sram_2kbyte_1rw1r_32x512_8.v \ + $script_dir/../../verilog/rtl/sram/sram_wb_wrapper.sv \ + " set ::env(DESIGN_IS_CORE) 0
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project index f714ae3..acc27a6 100644 --- a/verilog/includes/includes.rtl.caravel_user_project +++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -1,8 +1,9 @@ # Caravel user project includes -v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v -v $(USER_PROJECT_VERILOG)/rtl/user_proj_example.v +-v $(USER_PROJECT_VERILOG)/rtl/sram/sram_wb_wrapper.sv -v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/wb_interconnect.sv --v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/wb_stagging.sv +-v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/wb_signal_reg.sv -v $(USER_PROJECT_VERILOG)/rtl/wbuart32/rxuart.v -v $(USER_PROJECT_VERILOG)/rtl/wbuart32/txuart.v -v $(USER_PROJECT_VERILOG)/rtl/wbuart32/rxuartlite.v
diff --git a/verilog/rtl/sram/sky130_sram_2kbyte_1rw1r_32x512_8.v b/verilog/rtl/sram/sky130_sram_2kbyte_1rw1r_32x512_8.v index 289a770..7da4327 100644 --- a/verilog/rtl/sram/sky130_sram_2kbyte_1rw1r_32x512_8.v +++ b/verilog/rtl/sram/sky130_sram_2kbyte_1rw1r_32x512_8.v
@@ -20,7 +20,7 @@ parameter RAM_DEPTH = 1 << ADDR_WIDTH; // FIXME: This delay is arbitrary. parameter DELAY = 3 ; - parameter VERBOSE = 0 ; //Set to 0 to only display warnings + parameter VERBOSE = 1 ; //Set to 0 to only display warnings parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary `ifdef USE_POWER_PINS
diff --git a/verilog/rtl/sram/sram_wb_wrapper.sv b/verilog/rtl/sram/sram_wb_wrapper.sv index 58ec2d3..e003b4a 100644 --- a/verilog/rtl/sram/sram_wb_wrapper.sv +++ b/verilog/rtl/sram/sram_wb_wrapper.sv
@@ -34,23 +34,23 @@ input logic wb_we_i, // write input logic [SRAM_DATA_WD-1:0] wb_dat_i, // data output input logic [SRAM_DATA_WD/8-1:0] wb_sel_i, // byte enable - output logic [SRAM_DATA_WD-1:0] wb_dat_o, // data input + output wire [SRAM_DATA_WD-1:0] wb_dat_o, // data input output logic wb_ack_o // acknowlegement ); // Port A -logic sram_clk_a; -logic sram_csb_a; -logic [SRAM_ADDR_WD-1:0] sram_addr_a; -logic [SRAM_DATA_WD-1:0] sram_dout_a; +wire sram_clk_a; +wire sram_csb_a; +wire [SRAM_ADDR_WD-1:0] sram_addr_a; +wire [SRAM_DATA_WD-1:0] sram_dout_a; // Port B -logic sram_clk_b; -logic sram_csb_b; -logic sram_web_b; -logic [SRAM_DATA_WD/8-1:0] sram_mask_b; -logic [SRAM_ADDR_WD-1:0] sram_addr_b; -logic [SRAM_DATA_WD-1:0] sram_din_b; +wire sram_clk_b; +wire sram_csb_b; +wire sram_web_b; +wire [SRAM_DATA_WD/8-1:0] sram_mask_b; +wire [SRAM_ADDR_WD-1:0] sram_addr_b; +wire [SRAM_DATA_WD-1:0] sram_din_b; // Memory Write Port assign sram_clk_b = wb_clk_i; @@ -62,7 +62,7 @@ // Memory Read Port assign sram_clk_a = wb_clk_i; -assign sram_csb_a = (wb_stb_i == 1'b1 && wb_we_i == 1'b0 && wb_ack_o == 0) ? 1'b0 : 1'b1; +assign sram_csb_a = (wb_stb_i == 1'b1 && wb_we_i == 1'b0 && wb_cyc_i == 1'b1) ? 1'b0 : 1'b1; assign sram_addr_a = wb_adr_i; assign wb_dat_o = sram_dout_a; @@ -88,13 +88,14 @@ ); // Generate once cycle delayed ACK to get the data from SRAM -always_ff @(posedge wb_clk_i) begin +always @(negedge rst_n or posedge wb_clk_i) +begin if ( rst_n == 1'b0 ) begin wb_ack_o <= 'h0; end else begin - wb_ack_o <= (wb_stb_i == 1'b1) & (wb_ack_o == 0); + wb_ack_o <= (wb_stb_i == 1'b1) & (wb_cyc_i == 1'b1) & (wb_ack_o == 0); end end
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v index 3ae9bc1..e9be131 100644 --- a/verilog/rtl/user_proj_example.v +++ b/verilog/rtl/user_proj_example.v
@@ -83,8 +83,7 @@ //--------------------------------------------------------------------- // WB Master Interface //--------------------------------------------------------------------- -wire clk; -wire rst; +wire rst_n = !wb_rst_i; wire [`MPRJ_IO_PADS-1:0] io_in; wire [`MPRJ_IO_PADS-1:0] io_out; wire [`MPRJ_IO_PADS-1:0] io_oeb; @@ -122,7 +121,7 @@ .vssd1(vssd1), // User area 1 digital ground `endif .clk_i(wb_clk_i), - .rst_n(wb_rst_i), + .rst_n(rst_n), // Master 0 Interface .m0_wb_dat_i(wbs_dat_i), @@ -133,47 +132,46 @@ .m0_wb_stb_i(wbs_stb_i), .m0_wb_dat_o(wbs_dat_o), .m0_wb_ack_o(wbs_ack_o), - .m0_wb_err_o(), // Slave 0 Interface - .s0_wb_dat_i(s0_wb_dat_i), + .s0_wb_dat_i(s0_wb_dat_o), .s0_wb_ack_i(s0_wb_ack_o), .s0_wb_dat_o(s0_wb_dat_i), .s0_wb_adr_o(s0_wb_adr_i), .s0_wb_sel_o(s0_wb_sel_i), .s0_wb_we_o (s0_wb_we_i), .s0_wb_cyc_o(s0_wb_cyc_i), - .s0_wb_stb_o(s0_wb_stb_i), + .s0_wb_stb_o(s0_wb_stb_i) // Slave 1 Interface - .s1_wb_dat_i(), - .s1_wb_ack_i(), - .s1_wb_dat_o(), - .s1_wb_adr_o(), - .s1_wb_sel_o(), - .s1_wb_we_o (), - .s1_wb_cyc_o(), - .s1_wb_stb_o(), + .s1_wb_dat_i(s1_wb_dat_o), + .s1_wb_ack_i(s1_wb_ack_o), + .s1_wb_dat_o(s1_wb_dat_i), + .s1_wb_adr_o(s1_wb_adr_i), + .s1_wb_sel_o(s1_wb_sel_i), + .s1_wb_we_o (s1_wb_we_i)), + .s1_wb_cyc_o(s1_wb_cyc_i), + .s1_wb_stb_o(s1_wb_stb_i), // Slave 2 Interface - .s2_wb_dat_i(), - .s2_wb_ack_i(), - .s2_wb_dat_o(), - .s2_wb_adr_o(), - .s2_wb_sel_o(), - .s2_wb_we_o (), - .s2_wb_cyc_o(), - .s2_wb_stb_o(), + // .s2_wb_dat_i(), + // .s2_wb_ack_i(), + // .s2_wb_dat_o(), + // .s2_wb_adr_o(), + // .s2_wb_sel_o(), + // .s2_wb_we_o (), + // .s2_wb_cyc_o(), + // .s2_wb_stb_o(), // Slave 3 Interface - .s3_wb_dat_i(), - .s3_wb_ack_i(), - .s3_wb_dat_o(), - .s3_wb_adr_o(), - .s3_wb_sel_o(), - .s3_wb_we_o (), - .s3_wb_cyc_o(), - .s3_wb_stb_o() + // .s3_wb_dat_i(), + // .s3_wb_ack_i(), + // .s3_wb_dat_o(), + // .s3_wb_adr_o(), + // .s3_wb_sel_o(), + // .s3_wb_we_o (), + // .s3_wb_cyc_o(), + // .s3_wb_stb_o() ); sram_wb_wrapper #( @@ -185,7 +183,7 @@ `endif ) wb_wrapper0 ( - .rst_n(wb_rst_i), + .rst_n(rst_n), // Wishbone Interface .wb_clk_i(wb_clk_i), // System clock .wb_cyc_i(s0_wb_cyc_i), // cycle enable
diff --git a/verilog/rtl/wb_interconnect/wb_interconnect.sv b/verilog/rtl/wb_interconnect/wb_interconnect.sv index e76b65a..6397bc6 100644 --- a/verilog/rtl/wb_interconnect/wb_interconnect.sv +++ b/verilog/rtl/wb_interconnect/wb_interconnect.sv
@@ -39,89 +39,74 @@ input logic m0_wb_we_i, input logic m0_wb_cyc_i, input logic m0_wb_stb_i, - output logic [31:0] m0_wb_dat_o, - output logic m0_wb_ack_o, - output logic m0_wb_err_o, + output wire [31:0] m0_wb_dat_o, + output wire m0_wb_ack_o, // Slave 0 Interface input logic [31:0] s0_wb_dat_i, input logic s0_wb_ack_i, - output logic [31:0] s0_wb_dat_o, - output logic [7:0] s0_wb_adr_o, - output logic [3:0] s0_wb_sel_o, - output logic s0_wb_we_o, - output logic s0_wb_cyc_o, - output logic s0_wb_stb_o, + output wire [31:0] s0_wb_dat_o, + output wire [8:0] s0_wb_adr_o, + output wire [3:0] s0_wb_sel_o, + output wire s0_wb_we_o, + output wire s0_wb_cyc_o, + output wire s0_wb_stb_o // Slave 1 Interface input logic [31:0] s1_wb_dat_i, input logic s1_wb_ack_i, - output logic [31:0] s1_wb_dat_o, - output logic [10:0] s1_wb_adr_o, - output logic [3:0] s1_wb_sel_o, - output logic s1_wb_we_o, - output logic s1_wb_cyc_o, - output logic s1_wb_stb_o, + output wire [31:0] s1_wb_dat_o, + output wire [8:0] s1_wb_adr_o, + output wire [3:0] s1_wb_sel_o, + output wire s1_wb_we_o, + output wire s1_wb_cyc_o, + output wire s1_wb_stb_o, // Slave 2 Interface - input logic [31:0] s2_wb_dat_i, - input logic s2_wb_ack_i, - output logic [31:0] s2_wb_dat_o, - output logic [10:0] s2_wb_adr_o, - output logic [3:0] s2_wb_sel_o, - output logic s2_wb_we_o, - output logic s2_wb_cyc_o, - output logic s2_wb_stb_o, + // input logic [31:0] s2_wb_dat_i, + // input logic s2_wb_ack_i, + // output wire [31:0] s2_wb_dat_o, + // output wire [8:0] s2_wb_adr_o, + // output wire [3:0] s2_wb_sel_o, + // output wire s2_wb_we_o, + // output wire s2_wb_cyc_o, + // output wire s2_wb_stb_o, // Slave 3 Interface - input logic [31:0] s3_wb_dat_i, - input logic s3_wb_ack_i, - output logic [31:0] s3_wb_dat_o, - output logic [10:0] s3_wb_adr_o, - output logic [3:0] s3_wb_sel_o, - output logic s3_wb_we_o, - output logic s3_wb_cyc_o, - output logic s3_wb_stb_o + // input logic [31:0] s3_wb_dat_i, + // input logic s3_wb_ack_i, + // output wire [31:0] s3_wb_dat_o, + // output wire [8:0] s3_wb_adr_o, + // output wire [3:0] s3_wb_sel_o, + // output wire s3_wb_we_o, + // output wire s3_wb_cyc_o, + // output wire s3_wb_stb_o ); -// WishBone Wr Interface -typedef struct packed { - logic [31:0] wb_dat; - logic [31:0] wb_adr; - logic [3:0] wb_sel; - logic wb_we; - logic wb_cyc; - logic wb_stb; - logic [1:0] wb_tid; // target id -} type_wb_wr_intf; +logic holding_busy; // Indicate Stagging for Free or not -// WishBone Rd Interface -typedef struct packed { - logic [31:0] wb_dat; - logic wb_ack; - logic wb_err; -} type_wb_rd_intf; +logic [31:0] m0_wb_dat_i_reg; +logic [31:0] m0_wb_adr_reg; +logic [3:0] m0_wb_sel_reg; +logic m0_wb_we_reg; +logic m0_wb_cyc_reg; +logic m0_wb_stb_reg; +logic [1:0] m0_wb_tid_reg; -// Master Write Interface -type_wb_wr_intf m0_wb_wr; +logic [31:0] m0_wb_dat_o_reg; +logic m0_wb_ack_reg; -// Master Read Interface -type_wb_rd_intf m0_wb_rd; +wire [31:0] s_bus_rd_wb_dat = (m0_wb_adr_i[13:12] == 2'b00) ? s0_wb_dat_i : + (m0_wb_adr_i[13:12] == 2'b01) ? s1_wb_dat_i : + (m0_wb_adr_i[13:12] == 2'b10) ? s2_wb_dat_i : + s3_wb_dat_i; +wire s_bus_rd_wb_ack = (m0_wb_adr_i[13:12] == 2'b00) ? s0_wb_ack_i : + (m0_wb_adr_i[13:12] == 2'b01) ? s1_wb_ack_i : + (m0_wb_adr_i[13:12] == 2'b10) ? s2_wb_ack_i : + s3_wb_ack_i; -// Slave Write Interface -type_wb_wr_intf s0_wb_wr; -type_wb_wr_intf s1_wb_wr; -type_wb_wr_intf s2_wb_wr; -type_wb_wr_intf s3_wb_wr; - -// Slave Read Interface -type_wb_rd_intf s0_wb_rd; -type_wb_rd_intf s1_wb_rd; -type_wb_rd_intf s2_wb_rd; -type_wb_rd_intf s3_wb_rd; - -type_wb_wr_intf s_bus_wr; // Multiplexed Master I/F -type_wb_rd_intf s_bus_rd; // Multiplexed Slave I/F +//wire [31:0] s_bus_rd_wb_dat = s0_wb_dat_i; +//wire s_bus_rd_wb_ack = s0_wb_ack_i; //------------------------------------------------------------------- // EXTERNAL MEMORY MAP @@ -129,121 +114,91 @@ // 0x0000_1000 to 0x0000_1FFF - UART // 0x0000_2000 to 0x0000_2FFF - TRNG // 0x0000_3000 to 0x0000_3FFF - SPI -// ------------------------------------------------------------------ +//------------------------------------------------------------------ wire [1:0] m0_wb_tid_i = m0_wb_adr_i[13:12]; //---------------------------------------- -// Master Mapping -// --------------------------------------- -assign m0_wb_wr.wb_dat = m0_wb_dat_i; -assign m0_wb_wr.wb_adr = {m0_wb_adr_i[31:2],2'b00}; -assign m0_wb_wr.wb_sel = m0_wb_sel_i; -assign m0_wb_wr.wb_we = m0_wb_we_i; -assign m0_wb_wr.wb_cyc = m0_wb_cyc_i; -assign m0_wb_wr.wb_stb = m0_wb_stb_i; -assign m0_wb_wr.wb_tid = m0_wb_tid_i; - -assign m0_wb_dat_o = m0_wb_rd.wb_dat; -assign m0_wb_ack_o = m0_wb_rd.wb_ack; -assign m0_wb_err_o = m0_wb_rd.wb_err; - -//---------------------------------------- // Slave Mapping -// ------------------------------------- -// 2KB SRAM -assign s0_wb_dat_o = s0_wb_wr.wb_dat; -assign s0_wb_adr_o = s0_wb_wr.wb_adr[8:0]; -assign s0_wb_sel_o = s0_wb_wr.wb_sel; -assign s0_wb_we_o = s0_wb_wr.wb_we; -assign s0_wb_cyc_o = s0_wb_wr.wb_cyc; -assign s0_wb_stb_o = s0_wb_wr.wb_stb; +//--------------------------------------- +//assign s0_wb_dat_o = m0_wb_dat_i_reg; +//assign s0_wb_adr_o = m0_wb_adr_reg[8:0]; +//assign s0_wb_sel_o = m0_wb_sel_reg; +//assign s0_wb_we_o = m0_wb_we_reg; +//assign s0_wb_cyc_o = m0_wb_cyc_reg; +//assign s0_wb_stb_o = m0_wb_stb_reg; -assign s0_wb_rd.wb_dat = s0_wb_dat_i; -assign s0_wb_rd.wb_ack = s0_wb_ack_i; -assign s0_wb_rd.wb_err = 1'b0; +assign s0_wb_dat_o = (m0_wb_tid_reg == 2'b00) ? m0_wb_dat_i_reg : 2'b00; +assign s0_wb_adr_o = (m0_wb_tid_reg == 2'b00) ? m0_wb_adr_reg : 2'b00; +assign s0_wb_sel_o = (m0_wb_tid_reg == 2'b00) ? m0_wb_sel_reg : 2'b00; +assign s0_wb_we_o = (m0_wb_tid_reg == 2'b00) ? m0_wb_we_reg : 2'b00; +assign s0_wb_cyc_o = (m0_wb_tid_reg == 2'b00) ? m0_wb_cyc_reg : 2'b00; +assign s0_wb_stb_o = (m0_wb_tid_reg == 2'b00) ? m0_wb_stb_reg : 2'b00; -// UART -assign s1_wb_dat_o = s1_wb_wr.wb_dat; -assign s1_wb_adr_o = s1_wb_wr.wb_adr[10:0]; -assign s1_wb_sel_o = s1_wb_wr.wb_sel; -assign s1_wb_we_o = s1_wb_wr.wb_we; -assign s1_wb_cyc_o = s1_wb_wr.wb_cyc; -assign s1_wb_stb_o = s1_wb_wr.wb_stb; +assign s1_wb_dat_o = (m0_wb_tid_reg == 2'b01) ? m0_wb_dat_i_reg : 2'b00; +assign s1_wb_adr_o = (m0_wb_tid_reg == 2'b01) ? m0_wb_adr_reg : 2'b00; +assign s1_wb_sel_o = (m0_wb_tid_reg == 2'b01) ? m0_wb_sel_reg : 2'b00; +assign s1_wb_we_o = (m0_wb_tid_reg == 2'b01) ? m0_wb_we_reg : 2'b00; +assign s1_wb_cyc_o = (m0_wb_tid_reg == 2'b01) ? m0_wb_cyc_reg : 2'b00; +assign s1_wb_stb_o = (m0_wb_tid_reg == 2'b01) ? m0_wb_stb_reg : 2'b00; -assign s1_wb_rd.wb_dat = s1_wb_dat_i; -assign s1_wb_rd.wb_ack = s1_wb_ack_i; -assign s1_wb_rd.wb_err = 1'b0; +// assign s2_wb_dat_o = (m0_wb_tid_reg == 2'b10) ? m0_wb_dat_i_reg : 2'b00; +// assign s2_wb_adr_o = (m0_wb_tid_reg == 2'b10) ? m0_wb_adr_reg : 2'b00; +// assign s2_wb_sel_o = (m0_wb_tid_reg == 2'b10) ? m0_wb_sel_reg : 2'b00; +// assign s2_wb_we_o = (m0_wb_tid_reg == 2'b10) ? m0_wb_we_reg : 2'b00; +// assign s2_wb_cyc_o = (m0_wb_tid_reg == 2'b10) ? m0_wb_cyc_reg : 2'b00; +// assign s2_wb_stb_o = (m0_wb_tid_reg == 2'b10) ? m0_wb_stb_reg : 2'b00; -// TRNG -assign s2_wb_dat_o = s2_wb_wr.wb_dat; -assign s2_wb_adr_o = s2_wb_wr.wb_adr[10:0]; -assign s2_wb_sel_o = s2_wb_wr.wb_sel; -assign s2_wb_we_o = s2_wb_wr.wb_we; -assign s2_wb_cyc_o = s2_wb_wr.wb_cyc; -assign s2_wb_stb_o = s2_wb_wr.wb_stb; +// assign s3_wb_dat_o = (m0_wb_tid_reg == 2'b11) ? m0_wb_dat_i_reg : 2'b00; +// assign s3_wb_adr_o = (m0_wb_tid_reg == 2'b11) ? m0_wb_adr_reg : 2'b00; +// assign s3_wb_sel_o = (m0_wb_tid_reg == 2'b11) ? m0_wb_sel_reg : 2'b00; +// assign s3_wb_we_o = (m0_wb_tid_reg == 2'b11) ? m0_wb_we_reg : 2'b00; +// assign s3_wb_cyc_o = (m0_wb_tid_reg == 2'b11) ? m0_wb_cyc_reg : 2'b00; +// assign s3_wb_stb_o = (m0_wb_tid_reg == 2'b11) ? m0_wb_stb_reg : 2'b00; -assign s2_wb_rd.wb_dat = s2_wb_dat_i; -assign s2_wb_rd.wb_ack = s2_wb_ack_i; -assign s2_wb_rd.wb_err = 1'b0; +assign m0_wb_dat_o = s_bus_rd_wb_dat; +assign m0_wb_ack_o = s_bus_rd_wb_ack; -// SPI -assign s3_wb_dat_o = s3_wb_wr.wb_dat; -assign s3_wb_adr_o = s3_wb_wr.wb_adr[10:0]; -assign s3_wb_sel_o = s3_wb_wr.wb_sel; -assign s3_wb_we_o = s3_wb_wr.wb_we; -assign s3_wb_cyc_o = s3_wb_wr.wb_cyc; -assign s3_wb_stb_o = s3_wb_wr.wb_stb; +always @(negedge rst_n or posedge clk_i) +begin + if(rst_n == 1'b0) begin + // holding_busy <= 1'b0; + m0_wb_dat_i_reg <= 'h0; + m0_wb_adr_reg <= 'h0; + m0_wb_sel_reg <= 'h0; + m0_wb_we_reg <= 'h0; + m0_wb_cyc_reg <= 'h0; + m0_wb_stb_reg <= 'h0; + m0_wb_tid_reg <= 'h0; -assign s3_wb_rd.wb_dat = s3_wb_dat_i; -assign s3_wb_rd.wb_ack = s3_wb_ack_i; -assign s3_wb_rd.wb_err = 1'b0; + m0_wb_dat_o_reg <= 'h0; + m0_wb_ack_reg <= 'h0; + + end else begin + m0_wb_dat_i_reg <= 'h0; + m0_wb_adr_reg <= 'h0; + m0_wb_sel_reg <= 'h0; + m0_wb_we_reg <= 'h0; + m0_wb_cyc_reg <= 'h0; + m0_wb_stb_reg <= 'h0; + m0_wb_tid_reg <= 'h0; -// Generate Multiplexed Slave Interface based on target Id -wire [3:0] s_wb_tid = s_bus_wr.wb_tid; // to fix iverilog warning + // m0_wb_dat_o_reg <= 'h0; + // m0_wb_ack_reg <= 'h0; -always begin - case(s_wb_tid) - 2'b00: s_bus_rd = s0_wb_rd; - 2'b01: s_bus_rd = s1_wb_rd; - 2'b10: s_bus_rd = s2_wb_rd; - 2'b11: s_bus_rd = s3_wb_rd; - endcase + if(m0_wb_stb_i && m0_wb_cyc_i && s_bus_rd_wb_ack == 0) begin + // holding_busy <= 1'b1; + m0_wb_dat_i_reg <= m0_wb_dat_i; + m0_wb_adr_reg <= {2'b00,m0_wb_adr_i[31:2]}; + m0_wb_sel_reg <= m0_wb_sel_i; + m0_wb_we_reg <= m0_wb_we_i; + m0_wb_cyc_reg <= m0_wb_cyc_i; + m0_wb_stb_reg <= m0_wb_stb_i; + m0_wb_tid_reg <= m0_wb_tid_i; + + // m0_wb_dat_o_reg <= s_bus_rd_wb_dat; + // m0_wb_ack_reg <= s_bus_rd_wb_ack; + end + end end -// Connect Master => Slave -assign s0_wb_wr = (s_wb_tid == 2'b00) ? s_bus_wr : 2'b00; -assign s1_wb_wr = (s_wb_tid == 2'b01) ? s_bus_wr : 2'b00; -assign s2_wb_wr = (s_wb_tid == 2'b10) ? s_bus_wr : 2'b00; -assign s3_wb_wr = (s_wb_tid == 2'b11) ? s_bus_wr : 2'b00; - -// Stagging FF to break write and read timing path -wb_stagging u_m_wb_stage( - .clk_i (clk_i), - .rst_n (rst_n), - - // WishBone Input master I/P - .m_wb_dat_i (m0_wb_wr.wb_dat), - .m_wb_adr_i (m0_wb_wr.wb_adr), - .m_wb_sel_i (m0_wb_wr.wb_sel), - .m_wb_we_i (m0_wb_wr.wb_we ), - .m_wb_cyc_i (m0_wb_wr.wb_cyc), - .m_wb_stb_i (m0_wb_wr.wb_stb), - .m_wb_tid_i (m0_wb_wr.wb_tid), - .m_wb_dat_o (m0_wb_rd.wb_dat), - .m_wb_ack_o (m0_wb_rd.wb_ack), - .m_wb_err_o (m0_wb_rd.wb_err), - - // Slave Interface - .s_wb_dat_i (s_bus_rd.wb_dat), - .s_wb_ack_i (s_bus_rd.wb_ack), - .s_wb_err_i (s_bus_rd.wb_err), - .s_wb_dat_o (s_bus_wr.wb_dat), - .s_wb_adr_o (s_bus_wr.wb_adr), - .s_wb_sel_o (s_bus_wr.wb_sel), - .s_wb_we_o (s_bus_wr.wb_we ), - .s_wb_cyc_o (s_bus_wr.wb_cyc), - .s_wb_stb_o (s_bus_wr.wb_stb), - .s_wb_tid_o (s_bus_wr.wb_tid) -); - endmodule
diff --git a/verilog/rtl/wb_interconnect/wb_signal_reg.sv b/verilog/rtl/wb_interconnect/wb_signal_reg.sv new file mode 100644 index 0000000..d68156d --- /dev/null +++ b/verilog/rtl/wb_interconnect/wb_signal_reg.sv
@@ -0,0 +1,94 @@ +//----------------------------------------------------------------------------- +// @file wb_signal_reg.vhd +// +// @brief Register wishbone signals. +// +// @details This logic create a holding FF for Wishbone interface. +// This is usefull to break timing issue at interconnect +// +// @author Sukru Uzun <sukru.uzun@procenne.com> +// @date 10.03.2022 +// +// @todo +// @warning +// +// @project https://github.com/Procenne-Digital-Design/secure-memory.git +// +// @revision : +// 0.1 - 10 March 2022, Sukru Uzun +// initial version +//----------------------------------------------------------------------------- + +module wb_signal_reg ( + input logic clk_i, + input logic rst_n, + + // WishBone Input master I/P + input logic [31:0] m_wb_dat_i, + input logic [31:0] m_wb_adr_i, + input logic [3:0] m_wb_sel_i, + input logic m_wb_we_i, + input logic m_wb_cyc_i, + input logic m_wb_stb_i, + input logic [1:0] m_wb_tid_i, + output logic [31:0] m_wb_dat_o, + output logic m_wb_ack_o, + output logic m_wb_err_o, + + // Slave Interface + input logic [31:0] s_wb_dat_i, + input logic s_wb_ack_i, + input logic s_wb_err_i, + output logic [31:0] s_wb_dat_o, + output logic [31:0] s_wb_adr_o, + output logic [3:0] s_wb_sel_o, + output logic s_wb_we_o, + output logic s_wb_cyc_o, + output logic s_wb_stb_o, + output logic [1:0] s_wb_tid_o +); + +logic holding_busy ; // Indicate Stagging for Free or not + +always @(negedge rst_n or posedge clk_i) +begin + if(rst_n == 1'b0) begin + holding_busy <= 1'b0; + s_wb_dat_o <= 'h0; + s_wb_adr_o <= 'h0; + s_wb_sel_o <= 'h0; + s_wb_we_o <= 'h0; + s_wb_cyc_o <= 'h0; + s_wb_stb_o <= 'h0; + s_wb_tid_o <= 'h0; + m_wb_dat_o <= 'h0; + m_wb_ack_o <= 'h0; + m_wb_err_o <= 'h0; + end else begin + m_wb_dat_o <= s_wb_dat_i; + m_wb_ack_o <= s_wb_ack_i; + m_wb_err_o <= s_wb_err_i; + if(m_wb_stb_i && holding_busy == 0 && m_wb_ack_o == 0) begin + holding_busy <= 1'b1; + s_wb_dat_o <= m_wb_dat_i; + s_wb_adr_o <= m_wb_adr_i; + s_wb_sel_o <= m_wb_sel_i; + s_wb_we_o <= m_wb_we_i; + s_wb_cyc_o <= m_wb_cyc_i; + s_wb_stb_o <= m_wb_stb_i; + s_wb_tid_o <= m_wb_tid_i; + end + else if (holding_busy && s_wb_ack_i) begin + holding_busy <= 1'b0; + s_wb_dat_o <= 'h0; + s_wb_adr_o <= 'h0; + s_wb_sel_o <= 'h0; + s_wb_we_o <= 'h0; + s_wb_cyc_o <= 'h0; + s_wb_stb_o <= 'h0; + s_wb_tid_o <= 'h0; + end + end +end + +endmodule
diff --git a/verilog/rtl/wb_interconnect/wb_stagging.sv b/verilog/rtl/wb_interconnect/wb_stagging.sv deleted file mode 100644 index 2d0121e..0000000 --- a/verilog/rtl/wb_interconnect/wb_stagging.sv +++ /dev/null
@@ -1,116 +0,0 @@ -//----------------------------------------------------------------------------- -// @file wb_staging.vhd -// -// @brief Register wishbone signals. -// -// @details This logic create a holding FF for Wishbone interface. -// This is usefull to break timing issue at interconnect -// -// @author Sukru Uzun <sukru.uzun@procenne.com> -// @date 10.03.2022 -// -// @todo -// @warning -// -// @project https://github.com/Procenne-Digital-Design/secure-memory.git -// -// @revision : -// 0.1 - 10 March 2022, Sukru Uzun -// initial version -//----------------------------------------------------------------------------- - -module wb_stagging ( - input logic clk_i, - input logic rst_n, - - // WishBone Input master I/P - input logic [31:0] m_wbd_dat_i, - input logic [31:0] m_wbd_adr_i, - input logic [3:0] m_wbd_sel_i, - input logic m_wbd_we_i, - input logic m_wbd_cyc_i, - input logic m_wbd_stb_i, - input logic [3:0] m_wbd_tid_i, - output logic [31:0] m_wbd_dat_o, - output logic m_wbd_ack_o, - output logic m_wbd_err_o, - - // Slave Interface - input logic [31:0] s_wbd_dat_i, - input logic s_wbd_ack_i, - input logic s_wbd_err_i, - output logic [31:0] s_wbd_dat_o, - output logic [31:0] s_wbd_adr_o, - output logic [3:0] s_wbd_sel_o, - output logic s_wbd_we_o, - output logic s_wbd_cyc_o, - output logic s_wbd_stb_o, - output logic [3:0] s_wbd_tid_o -); - -logic holding_busy ; // Indicate Stagging for Free or not -logic [31:0] m_wbd_dat_i_ff ; // Flopped vesion of m_wbd_dat_i -logic [31:0] m_wbd_adr_i_ff ; // Flopped vesion of m_wbd_adr_i -logic [3:0] m_wbd_sel_i_ff ; // Flopped vesion of m_wbd_sel_i -logic m_wbd_we_i_ff ; // Flopped vesion of m_wbd_we_i -logic m_wbd_cyc_i_ff ; // Flopped vesion of m_wbd_cyc_i -logic m_wbd_stb_i_ff ; // Flopped vesion of m_wbd_stb_i -logic [3:0] m_wbd_tid_i_ff ; // Flopped vesion of m_wbd_tid_i -logic [31:0] s_wbd_dat_i_ff ; // Flopped vesion of s_wbd_dat_i -logic s_wbd_ack_i_ff ; // Flopped vesion of s_wbd_ack_i -logic s_wbd_err_i_ff ; // Flopped vesion of s_wbd_err_i - -assign s_wbd_dat_o = m_wbd_dat_i_ff; -assign s_wbd_adr_o = m_wbd_adr_i_ff; -assign s_wbd_sel_o = m_wbd_sel_i_ff; -assign s_wbd_we_o = m_wbd_we_i_ff; -assign s_wbd_cyc_o = m_wbd_cyc_i_ff; -assign s_wbd_stb_o = m_wbd_stb_i_ff; -assign s_wbd_tid_o = m_wbd_tid_i_ff; - -assign m_wbd_dat_o = s_wbd_dat_i_ff; -assign m_wbd_ack_o = s_wbd_ack_i_ff; -assign m_wbd_err_o = s_wbd_err_i_ff; - -always @(negedge rst_n or posedge clk_i) -begin - if(rst_n == 1'b0) begin - holding_busy <= 1'b0; - m_wbd_dat_i_ff <= 'h0; - m_wbd_adr_i_ff <= 'h0; - m_wbd_sel_i_ff <= 'h0; - m_wbd_we_i_ff <= 'h0; - m_wbd_cyc_i_ff <= 'h0; - m_wbd_stb_i_ff <= 'h0; - m_wbd_tid_i_ff <= 'h0; - s_wbd_dat_i_ff <= 'h0; - s_wbd_ack_i_ff <= 'h0; - s_wbd_err_i_ff <= 'h0; - end else begin - s_wbd_dat_i_ff <= s_wbd_dat_i; - s_wbd_ack_i_ff <= s_wbd_ack_i; - s_wbd_err_i_ff <= s_wbd_err_i; - if(m_wbd_stb_i && holding_busy == 0 && m_wbd_ack_o == 0) begin - holding_busy <= 1'b1; - m_wbd_dat_i_ff <= m_wbd_dat_i; - m_wbd_adr_i_ff <= m_wbd_adr_i; - m_wbd_sel_i_ff <= m_wbd_sel_i; - m_wbd_we_i_ff <= m_wbd_we_i; - m_wbd_cyc_i_ff <= m_wbd_cyc_i; - m_wbd_stb_i_ff <= m_wbd_stb_i; - m_wbd_tid_i_ff <= m_wbd_tid_i; - end - else if (holding_busy && s_wbd_ack_i) begin - holding_busy <= 1'b0; - m_wbd_dat_i_ff <= 'h0; - m_wbd_adr_i_ff <= 'h0; - m_wbd_sel_i_ff <= 'h0; - m_wbd_we_i_ff <= 'h0; - m_wbd_cyc_i_ff <= 'h0; - m_wbd_stb_i_ff <= 'h0; - m_wbd_tid_i_ff <= 'h0; - end - end -end - -endmodule