commit ee65c2201e0ca4e18a1fcf8a1854223bc0263e87
author yct000 <yahyacantugrul@gmail.com> Fri Mar 18 15:06:50 2022 +0300
committer yct000 <yahyacantugrul@gmail.com> Fri Mar 18 15:06:50 2022 +0300
tree c9d315f3ee181c902d0310924b5b3c36cd97e14f
parent 32fc98212ea7a87506f8f56e94b394cd0a84238d
parent 6e3ad673bb44871e1c5af2a81f4087c6aa4c3c74

Merge branch 'main' of github.com:kasirgalabs/mpw-5c-C0 into main

README.md

diff --git a/README.md b/README.md
index 098848c..81e11dc 100644
--- a/README.md
+++ b/README.md
@@ -1,4 +1,4 @@
-# Kasırga K0 RISC-V SoC
+# Kasırga C0 RISC-V SoC
 
 [![License](https://img.shields.io/badge/License-Apache%202.0-blue.svg)](https://opensource.org/licenses/Apache-2.0) [![UPRJ_CI](https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml/badge.svg)](https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml) [![Caravel Build](https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml/badge.svg)](https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml)
 
@@ -18,11 +18,11 @@
 Overview
 ========
 
-This repo contains the RISC-V based K0 SoC that utilizes ``caravel`` chip user space.
-K0 is an silicon-proven SoC that has a RISC-V core (RV32-IM ISA) and AN UART module @ 115200 baudrate.
+This repo contains the RISC-V based C0 SoC that utilizes ``caravel`` chip user space.
+C0 is an silicon-proven SoC that has a RISC-V core (RV32-IM ISA) and AN UART module @ 115200 baudrate.
 The repo also contains all required files to run all RV32-IM ISA tests.
 
-# K0 Block Diagram
+# C0 Block Diagram
 
 TBA
 
@@ -40,7 +40,7 @@
 
 TBA
 
-# Hardening the Kasirga K0 using Openlane
+# Hardening the Kasirga C0 using Openlane
 
 TBA