commit 7f3c6cd78f653dab7b5123130cba1435374966ab
author yct000 <yahyacantugrul@gmail.com> Fri Mar 18 15:09:29 2022 +0300
committer yct000 <yahyacantugrul@gmail.com> Fri Mar 18 15:09:29 2022 +0300
tree 512c8668a8add8a888da753b1c41d0b682bf7da1
parent ee65c2201e0ca4e18a1fcf8a1854223bc0263e87

modify rtl files for slow uart

verilog/rtl/UART_alici.v

diff --git a/verilog/rtl/UART_alici.v b/verilog/rtl/UART_alici.v
index 98ae602..5225404 100644
--- a/verilog/rtl/UART_alici.v
+++ b/verilog/rtl/UART_alici.v
@@ -31,7 +31,7 @@
   `ifdef FAST_UART
    localparam UART_SAAT = 16;
   `else
-   localparam UART_SAAT = 2083;
+   localparam UART_SAAT = 5208;
   `endif
 
   /*

verilog/rtl/UART_verici.v

diff --git a/verilog/rtl/UART_verici.v b/verilog/rtl/UART_verici.v
index beee7d4..f8cc5b3 100644
--- a/verilog/rtl/UART_verici.v
+++ b/verilog/rtl/UART_verici.v
@@ -28,7 +28,7 @@
   `ifdef FAST_UART
    localparam UART_SAAT = 16;
   `else
-   localparam UART_SAAT = 2083;
+   localparam UART_SAAT = 5208;
   `endif
 
   /*

verilog/rtl/sabitler.vh

diff --git a/verilog/rtl/sabitler.vh b/verilog/rtl/sabitler.vh
index 3cd8027..cb7febb 100644
--- a/verilog/rtl/sabitler.vh
+++ b/verilog/rtl/sabitler.vh
@@ -13,7 +13,7 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 //-----------Sim Parametreleri----
-`define FAST_UART
+//`define FAST_UART
 //`define SIM_SRAM
 `define GL_RTL_SIM
 //------Sentez Parametreleri------