commit | ee65c2201e0ca4e18a1fcf8a1854223bc0263e87 | [log] [tgz] |
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author | yct000 <yahyacantugrul@gmail.com> | Fri Mar 18 15:06:50 2022 +0300 |
committer | yct000 <yahyacantugrul@gmail.com> | Fri Mar 18 15:06:50 2022 +0300 |
tree | c9d315f3ee181c902d0310924b5b3c36cd97e14f | |
parent | 32fc98212ea7a87506f8f56e94b394cd0a84238d [diff] | |
parent | 6e3ad673bb44871e1c5af2a81f4087c6aa4c3c74 [diff] |
Merge branch 'main' of github.com:kasirgalabs/mpw-5c-C0 into main
This repo contains the RISC-V based C0 SoC that utilizes caravel
chip user space. C0 is an silicon-proven SoC that has a RISC-V core (RV32-IM ISA) and AN UART module @ 115200 baudrate. The repo also contains all required files to run all RV32-IM ISA tests.
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user_project_wrapper
.user_project_wrapper
at verilog/gl/user_project_wrapper.vuser_project_wrapper
adheres to the same pin order specified at pin\_order
user_project_wrapper
adheres to the fixed wrapper configuration specified at fixed_wrapper_cfgs
mpw-precheck