commit	7ca70ccc15b4686d30693f84ef068555c1e76c4f	[log] [tgz]
author	roman3017 <rbacik@hotmail.com>	Sat Nov 13 00:12:35 2021 -0800
committer	roman3017 <rbacik@hotmail.com>	Sun Feb 20 00:30:16 2022 -0800
tree	64f60fced203638026540806bfbde322e62fb3d1
parent	c531197faf6d27a55e0a2658684ec9f8f14879d6 [diff]

add user_proj

.github/scripts/build/build-user.sh[Added - diff]
.github/scripts/build/build-wrapper.sh[Added - diff]
.github/scripts/build/run-install-magic.sh[Added - diff]
.github/scripts/dv/run-dv-tests.sh[Added - diff]
.github/workflows/caravel_build.yml[diff]
.github/workflows/user_project_ci.yml[diff]
README.md[diff]
def/user_proj.def[Added - diff]
def/user_proj_example.def[diff]
def/user_project_wrapper.def[diff]
gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds.gz[Added - diff]
gds/user_proj.gds.gz[Added - diff]
gds/user_proj_example.gds[Deleted - diff]
gds/user_project_wrapper.gds[Deleted - diff]
gds/user_project_wrapper.gds.gz[Added - diff]
lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef[Added - diff]
lef/user_proj.lef[Added - diff]
lef/user_proj_example.lef[diff]
lef/user_project_wrapper.lef[diff]
lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib[Added - diff]
mag/user_proj.mag[Added - diff]
mag/user_proj_example.mag[diff]
mag/user_project_wrapper.mag[diff]
maglef/user_proj.mag[Added - diff]
maglef/user_proj_example.mag[diff]
maglef/user_project_wrapper.mag[diff]
openlane/user_proj/config.tcl[Added - diff]
openlane/user_proj/pin_order.cfg[Renamed from openlane/user_proj_example/pin_order.cfg - diff]
openlane/user_proj/src/arbiter.v[Added - diff]
openlane/user_proj/src/fifo.v[Added - diff]
openlane/user_proj/src/hyper_xface.v[Added - diff]
openlane/user_proj/src/ram_1w_1rs.v[Added - diff]
openlane/user_proj/src/simpleuart.v[Added - diff]
openlane/user_proj/src/soc.v[Added - diff]
openlane/user_proj/src/timer_wb.v[Added - diff]
openlane/user_proj/src/user_proj.v[Added - diff]
openlane/user_proj/src/vexriscv.v[Added - diff]
openlane/user_proj/src/wb_arbiter.v[Added - diff]
openlane/user_proj/src/wb_hyper.v[Added - diff]
openlane/user_proj/src/wb_interconnect.v[Added - diff]
openlane/user_proj/src/wb_interconnect.vh[Added - diff]
openlane/user_proj/src/wb_led.v[Added - diff]
openlane/user_proj/src/wb_mux.v[Added - diff]
openlane/user_proj/src/wb_openram_wrapper.v[Added - diff]
openlane/user_proj_example/config.json[Deleted - diff]
openlane/user_proj_example/config.tcl[Deleted - diff]
openlane/user_project_wrapper/config.json[Deleted - diff]
openlane/user_project_wrapper/config.tcl[diff]
openlane/user_project_wrapper/macro.cfg[diff]
openlane/user_project_wrapper/pin_order.cfg[Deleted - diff]
openlane/user_project_wrapper/src/user_project_wrapper.v[Renamed from verilog/rtl/user_project_wrapper.v - diff]
signoff/user_proj/OPENLANE_VERSION[Added - diff]
signoff/user_proj/PDK_SOURCES[Added - diff]
signoff/user_proj/final_summary_report.csv[Added - diff]
signoff/user_proj_example/OPENLANE_VERSION[diff]
signoff/user_proj_example/PDK_SOURCES[diff]
signoff/user_proj_example/final_summary_report.csv[diff]
signoff/user_project_wrapper/OPENLANE_VERSION[diff]
signoff/user_project_wrapper/PDK_SOURCES[diff]
signoff/user_project_wrapper/final_summary_report.csv[diff]
spi/lvs/user_proj.spice[Added - diff]
spi/lvs/user_proj_example.spice[diff]
spi/lvs/user_project_wrapper.spice[diff]
verilog/dv/Makefile[diff]
verilog/dv/io_ports/Makefile[diff]
verilog/dv/io_ports/io_ports_tb.v[diff]
verilog/dv/la_test1/Makefile[diff]
verilog/dv/la_test1/la_test1_tb.v[diff]
verilog/dv/la_test2/Makefile[diff]
verilog/dv/la_test2/la_test2_tb.v[diff]
verilog/dv/mprj_stimulus/Makefile[diff]
verilog/dv/mprj_stimulus/mprj_stimulus.c[diff]
verilog/dv/wb_leds/Makefile[Added - diff]
verilog/dv/wb_leds/wb_leds.c[Added - diff]
verilog/dv/wb_leds/wb_leds.gtkw[Added - diff]
verilog/dv/wb_leds/wb_leds_tb.v[Added - diff]
verilog/dv/wb_port/Makefile[diff]
verilog/dv/wb_port/wb_port_tb.v[diff]
verilog/gl/user_proj.v[Added - diff]
verilog/gl/user_proj_example.v[Deleted - diff]
verilog/gl/user_project_wrapper.v[diff]
verilog/rtl/uprj_netlists.v[diff]
verilog/rtl/user_proj_example.v[Deleted - diff]

83 files changed

tree: 64f60fced203638026540806bfbde322e62fb3d1

README.md

Caravel User Project

RISC-V SoC

Vexriscv based SoC

Refer to README for a complete roundtrip of how to use caravel_user_project

Refer to README for this sample project documentation.