| // Generator : SpinalHDL v1.6.2 git head : 64a701fc0e270acfaf7ad7669046094440d20bc9 |
| // Component : VexRiscv |
| // Git hash : d8936a53c0572eb53f8dd48c8d41856b6949af34 |
| |
| `timescale 1ns/1ps |
| |
| module VexRiscv ( |
| `ifdef USE_POWER_PINS |
| inout vccd1, // User area 1 1.8V supply |
| inout vssd1, // User area 1 digital ground |
| `endif |
| output debug_resetOut, |
| input timerInterrupt, |
| input externalInterrupt, |
| input softwareInterrupt, |
| output reg iBusWishbone_CYC, |
| output reg iBusWishbone_STB, |
| input iBusWishbone_ACK, |
| output iBusWishbone_WE, |
| output [29:0] iBusWishbone_ADR, |
| input [31:0] iBusWishbone_DAT_MISO, |
| output [31:0] iBusWishbone_DAT_MOSI, |
| output [3:0] iBusWishbone_SEL, |
| input iBusWishbone_ERR, |
| output [2:0] iBusWishbone_CTI, |
| output [1:0] iBusWishbone_BTE, |
| output dBusWishbone_CYC, |
| output dBusWishbone_STB, |
| input dBusWishbone_ACK, |
| output dBusWishbone_WE, |
| output [29:0] dBusWishbone_ADR, |
| input [31:0] dBusWishbone_DAT_MISO, |
| output [31:0] dBusWishbone_DAT_MOSI, |
| output [3:0] dBusWishbone_SEL, |
| input dBusWishbone_ERR, |
| output [2:0] dBusWishbone_CTI, |
| output [1:0] dBusWishbone_BTE, |
| input jtag_tms, |
| input jtag_tdi, |
| output jtag_tdo, |
| input jtag_tck, |
| input clk, |
| input reset, |
| input jtag_rst |
| ); |
| localparam ShiftCtrlEnum_DISABLE_1 = 2'd0; |
| localparam ShiftCtrlEnum_SLL_1 = 2'd1; |
| localparam ShiftCtrlEnum_SRL_1 = 2'd2; |
| localparam ShiftCtrlEnum_SRA_1 = 2'd3; |
| localparam BranchCtrlEnum_INC = 2'd0; |
| localparam BranchCtrlEnum_B = 2'd1; |
| localparam BranchCtrlEnum_JAL = 2'd2; |
| localparam BranchCtrlEnum_JALR = 2'd3; |
| localparam EnvCtrlEnum_NONE = 1'd0; |
| localparam EnvCtrlEnum_XRET = 1'd1; |
| localparam AluBitwiseCtrlEnum_XOR_1 = 2'd0; |
| localparam AluBitwiseCtrlEnum_OR_1 = 2'd1; |
| localparam AluBitwiseCtrlEnum_AND_1 = 2'd2; |
| localparam AluCtrlEnum_ADD_SUB = 2'd0; |
| localparam AluCtrlEnum_SLT_SLTU = 2'd1; |
| localparam AluCtrlEnum_BITWISE = 2'd2; |
| localparam Src2CtrlEnum_RS = 2'd0; |
| localparam Src2CtrlEnum_IMI = 2'd1; |
| localparam Src2CtrlEnum_IMS = 2'd2; |
| localparam Src2CtrlEnum_PC = 2'd3; |
| localparam Src1CtrlEnum_RS = 2'd0; |
| localparam Src1CtrlEnum_IMU = 2'd1; |
| localparam Src1CtrlEnum_PC_INCREMENT = 2'd2; |
| localparam Src1CtrlEnum_URS1 = 2'd3; |
| localparam MmuPlugin_shared_State_IDLE = 3'd0; |
| localparam MmuPlugin_shared_State_L1_CMD = 3'd1; |
| localparam MmuPlugin_shared_State_L1_RSP = 3'd2; |
| localparam MmuPlugin_shared_State_L0_CMD = 3'd3; |
| localparam MmuPlugin_shared_State_L0_RSP = 3'd4; |
| |
| wire IBusCachedPlugin_cache_io_flush; |
| wire IBusCachedPlugin_cache_io_cpu_prefetch_isValid; |
| wire IBusCachedPlugin_cache_io_cpu_fetch_isValid; |
| wire IBusCachedPlugin_cache_io_cpu_fetch_isStuck; |
| wire IBusCachedPlugin_cache_io_cpu_fetch_isRemoved; |
| wire IBusCachedPlugin_cache_io_cpu_decode_isValid; |
| wire IBusCachedPlugin_cache_io_cpu_decode_isStuck; |
| wire IBusCachedPlugin_cache_io_cpu_decode_isUser; |
| reg IBusCachedPlugin_cache_io_cpu_fill_valid; |
| reg dataCache_1_io_cpu_execute_isValid; |
| reg [31:0] dataCache_1_io_cpu_execute_address; |
| reg dataCache_1_io_cpu_execute_args_wr; |
| reg [1:0] dataCache_1_io_cpu_execute_args_size; |
| reg dataCache_1_io_cpu_memory_isValid; |
| wire [31:0] dataCache_1_io_cpu_memory_address; |
| reg dataCache_1_io_cpu_memory_mmuRsp_isIoAccess; |
| reg dataCache_1_io_cpu_writeBack_isValid; |
| wire dataCache_1_io_cpu_writeBack_isUser; |
| wire [31:0] dataCache_1_io_cpu_writeBack_storeData; |
| wire [31:0] dataCache_1_io_cpu_writeBack_address; |
| wire dataCache_1_io_cpu_writeBack_fence_SW; |
| wire dataCache_1_io_cpu_writeBack_fence_SR; |
| wire dataCache_1_io_cpu_writeBack_fence_SO; |
| wire dataCache_1_io_cpu_writeBack_fence_SI; |
| wire dataCache_1_io_cpu_writeBack_fence_PW; |
| wire dataCache_1_io_cpu_writeBack_fence_PR; |
| wire dataCache_1_io_cpu_writeBack_fence_PO; |
| wire dataCache_1_io_cpu_writeBack_fence_PI; |
| wire [3:0] dataCache_1_io_cpu_writeBack_fence_FM; |
| wire dataCache_1_io_cpu_flush_valid; |
| reg dataCache_1_io_mem_cmd_ready; |
| reg [31:0] _zz_RegFilePlugin_regFile_port0; |
| reg [31:0] _zz_RegFilePlugin_regFile_port1; |
| wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; |
| wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; |
| wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; |
| wire IBusCachedPlugin_cache_io_cpu_decode_error; |
| wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; |
| wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; |
| wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; |
| wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; |
| wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; |
| wire IBusCachedPlugin_cache_io_mem_cmd_valid; |
| wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; |
| wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; |
| wire dataCache_1_io_cpu_execute_haltIt; |
| wire dataCache_1_io_cpu_execute_refilling; |
| wire dataCache_1_io_cpu_memory_isWrite; |
| wire dataCache_1_io_cpu_writeBack_haltIt; |
| wire [31:0] dataCache_1_io_cpu_writeBack_data; |
| wire dataCache_1_io_cpu_writeBack_mmuException; |
| wire dataCache_1_io_cpu_writeBack_unalignedAccess; |
| wire dataCache_1_io_cpu_writeBack_accessError; |
| wire dataCache_1_io_cpu_writeBack_isWrite; |
| wire dataCache_1_io_cpu_writeBack_keepMemRspData; |
| wire dataCache_1_io_cpu_writeBack_exclusiveOk; |
| wire dataCache_1_io_cpu_flush_ready; |
| wire dataCache_1_io_cpu_redo; |
| wire dataCache_1_io_mem_cmd_valid; |
| wire dataCache_1_io_mem_cmd_payload_wr; |
| wire dataCache_1_io_mem_cmd_payload_uncached; |
| wire [31:0] dataCache_1_io_mem_cmd_payload_address; |
| wire [31:0] dataCache_1_io_mem_cmd_payload_data; |
| wire [3:0] dataCache_1_io_mem_cmd_payload_mask; |
| wire [2:0] dataCache_1_io_mem_cmd_payload_size; |
| wire dataCache_1_io_mem_cmd_payload_last; |
| wire jtagBridge_1_io_jtag_tdo; |
| wire jtagBridge_1_io_remote_cmd_valid; |
| wire jtagBridge_1_io_remote_cmd_payload_last; |
| wire [0:0] jtagBridge_1_io_remote_cmd_payload_fragment; |
| wire jtagBridge_1_io_remote_rsp_ready; |
| wire systemDebugger_1_io_remote_cmd_ready; |
| wire systemDebugger_1_io_remote_rsp_valid; |
| wire systemDebugger_1_io_remote_rsp_payload_error; |
| wire [31:0] systemDebugger_1_io_remote_rsp_payload_data; |
| wire systemDebugger_1_io_mem_cmd_valid; |
| wire [31:0] systemDebugger_1_io_mem_cmd_payload_address; |
| wire [31:0] systemDebugger_1_io_mem_cmd_payload_data; |
| wire systemDebugger_1_io_mem_cmd_payload_wr; |
| wire [1:0] systemDebugger_1_io_mem_cmd_payload_size; |
| wire [51:0] _zz_memory_MUL_LOW; |
| wire [51:0] _zz_memory_MUL_LOW_1; |
| wire [51:0] _zz_memory_MUL_LOW_2; |
| wire [51:0] _zz_memory_MUL_LOW_3; |
| wire [32:0] _zz_memory_MUL_LOW_4; |
| wire [51:0] _zz_memory_MUL_LOW_5; |
| wire [49:0] _zz_memory_MUL_LOW_6; |
| wire [51:0] _zz_memory_MUL_LOW_7; |
| wire [49:0] _zz_memory_MUL_LOW_8; |
| wire [31:0] _zz_execute_SHIFT_RIGHT; |
| wire [32:0] _zz_execute_SHIFT_RIGHT_1; |
| wire [32:0] _zz_execute_SHIFT_RIGHT_2; |
| wire [31:0] _zz_decode_LEGAL_INSTRUCTION; |
| wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1; |
| wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2; |
| wire _zz_decode_LEGAL_INSTRUCTION_3; |
| wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4; |
| wire [13:0] _zz_decode_LEGAL_INSTRUCTION_5; |
| wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6; |
| wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7; |
| wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8; |
| wire _zz_decode_LEGAL_INSTRUCTION_9; |
| wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10; |
| wire [7:0] _zz_decode_LEGAL_INSTRUCTION_11; |
| wire [31:0] _zz_decode_LEGAL_INSTRUCTION_12; |
| wire [31:0] _zz_decode_LEGAL_INSTRUCTION_13; |
| wire [31:0] _zz_decode_LEGAL_INSTRUCTION_14; |
| wire _zz_decode_LEGAL_INSTRUCTION_15; |
| wire [0:0] _zz_decode_LEGAL_INSTRUCTION_16; |
| wire [1:0] _zz_decode_LEGAL_INSTRUCTION_17; |
| wire [2:0] _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1; |
| reg [31:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_4; |
| wire [1:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_5; |
| wire [31:0] _zz_IBusCachedPlugin_fetchPc_pc; |
| wire [2:0] _zz_IBusCachedPlugin_fetchPc_pc_1; |
| wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code; |
| wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code_1; |
| reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted; |
| wire [1:0] _zz_writeBack_DBusCachedPlugin_rspShifted_1; |
| reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted_2; |
| wire [0:0] _zz_writeBack_DBusCachedPlugin_rspShifted_3; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_1; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_2; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_3; |
| wire _zz__zz_decode_IS_SFENCE_VMA2_4; |
| wire [1:0] _zz__zz_decode_IS_SFENCE_VMA2_5; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_6; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_7; |
| wire _zz__zz_decode_IS_SFENCE_VMA2_8; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_9; |
| wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_10; |
| wire [25:0] _zz__zz_decode_IS_SFENCE_VMA2_11; |
| wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_12; |
| wire _zz__zz_decode_IS_SFENCE_VMA2_13; |
| wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_14; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_15; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_16; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_17; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_18; |
| wire [21:0] _zz__zz_decode_IS_SFENCE_VMA2_19; |
| wire _zz__zz_decode_IS_SFENCE_VMA2_20; |
| wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_21; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_22; |
| wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_23; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_24; |
| wire _zz__zz_decode_IS_SFENCE_VMA2_25; |
| wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_26; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_27; |
| wire _zz__zz_decode_IS_SFENCE_VMA2_28; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_29; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_30; |
| wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_31; |
| wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_32; |
| wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_33; |
| wire [16:0] _zz__zz_decode_IS_SFENCE_VMA2_34; |
| wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_35; |
| wire _zz__zz_decode_IS_SFENCE_VMA2_36; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_37; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_38; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_39; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_40; |
| wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_41; |
| wire _zz__zz_decode_IS_SFENCE_VMA2_42; |
| wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_43; |
| wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_44; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_45; |
| wire [13:0] _zz__zz_decode_IS_SFENCE_VMA2_46; |
| wire _zz__zz_decode_IS_SFENCE_VMA2_47; |
| wire [4:0] _zz__zz_decode_IS_SFENCE_VMA2_48; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_49; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_50; |
| wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_51; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_52; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_53; |
| wire [1:0] _zz__zz_decode_IS_SFENCE_VMA2_54; |
| wire _zz__zz_decode_IS_SFENCE_VMA2_55; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_56; |
| wire _zz__zz_decode_IS_SFENCE_VMA2_57; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_58; |
| wire _zz__zz_decode_IS_SFENCE_VMA2_59; |
| wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_60; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_61; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_62; |
| wire [2:0] _zz__zz_decode_IS_SFENCE_VMA2_63; |
| wire _zz__zz_decode_IS_SFENCE_VMA2_64; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_65; |
| wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_66; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_67; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_68; |
| wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_69; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_70; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_71; |
| wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_72; |
| wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_73; |
| wire [4:0] _zz__zz_decode_IS_SFENCE_VMA2_74; |
| wire _zz__zz_decode_IS_SFENCE_VMA2_75; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_76; |
| wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_77; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_78; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_79; |
| wire [2:0] _zz__zz_decode_IS_SFENCE_VMA2_80; |
| wire _zz__zz_decode_IS_SFENCE_VMA2_81; |
| wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_82; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_83; |
| wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_84; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_85; |
| wire [9:0] _zz__zz_decode_IS_SFENCE_VMA2_86; |
| wire [1:0] _zz__zz_decode_IS_SFENCE_VMA2_87; |
| wire _zz__zz_decode_IS_SFENCE_VMA2_88; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_89; |
| wire _zz__zz_decode_IS_SFENCE_VMA2_90; |
| wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_91; |
| wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_92; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_93; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_94; |
| wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_95; |
| wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_96; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_97; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_98; |
| wire [6:0] _zz__zz_decode_IS_SFENCE_VMA2_99; |
| wire _zz__zz_decode_IS_SFENCE_VMA2_100; |
| wire _zz__zz_decode_IS_SFENCE_VMA2_101; |
| wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_102; |
| wire [3:0] _zz__zz_decode_IS_SFENCE_VMA2_103; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_104; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_105; |
| wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_106; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_107; |
| wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_108; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_109; |
| wire [4:0] _zz__zz_decode_IS_SFENCE_VMA2_110; |
| wire _zz__zz_decode_IS_SFENCE_VMA2_111; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_112; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_113; |
| wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_114; |
| wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_115; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_116; |
| wire [1:0] _zz__zz_decode_IS_SFENCE_VMA2_117; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_118; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_119; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_120; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_121; |
| wire [2:0] _zz__zz_decode_IS_SFENCE_VMA2_122; |
| wire [1:0] _zz__zz_decode_IS_SFENCE_VMA2_123; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_124; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_125; |
| wire _zz__zz_decode_IS_SFENCE_VMA2_126; |
| wire _zz__zz_decode_IS_SFENCE_VMA2_127; |
| wire _zz__zz_decode_IS_SFENCE_VMA2_128; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_129; |
| wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_130; |
| wire _zz_RegFilePlugin_regFile_port; |
| wire _zz_decode_RegFilePlugin_rs1Data; |
| wire _zz_RegFilePlugin_regFile_port_1; |
| wire _zz_decode_RegFilePlugin_rs2Data; |
| wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA; |
| wire [2:0] _zz__zz_decode_SRC1_1; |
| wire [4:0] _zz__zz_decode_SRC1_1_1; |
| wire [11:0] _zz__zz_decode_SRC2_4; |
| wire [31:0] _zz_execute_SrcPlugin_addSub; |
| wire [31:0] _zz_execute_SrcPlugin_addSub_1; |
| wire [31:0] _zz_execute_SrcPlugin_addSub_2; |
| wire [31:0] _zz_execute_SrcPlugin_addSub_3; |
| wire [31:0] _zz_execute_SrcPlugin_addSub_4; |
| wire [31:0] _zz_execute_SrcPlugin_addSub_5; |
| wire [31:0] _zz_execute_SrcPlugin_addSub_6; |
| wire [65:0] _zz_writeBack_MulPlugin_result; |
| wire [65:0] _zz_writeBack_MulPlugin_result_1; |
| wire [31:0] _zz__zz_decode_RS2_2; |
| wire [31:0] _zz__zz_decode_RS2_2_1; |
| wire [5:0] _zz_memory_DivPlugin_div_counter_valueNext; |
| wire [0:0] _zz_memory_DivPlugin_div_counter_valueNext_1; |
| wire [32:0] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator; |
| wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder; |
| wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder_1; |
| wire [32:0] _zz_memory_DivPlugin_div_stage_0_outNumerator; |
| wire [32:0] _zz_memory_DivPlugin_div_result_1; |
| wire [32:0] _zz_memory_DivPlugin_div_result_2; |
| wire [32:0] _zz_memory_DivPlugin_div_result_3; |
| wire [32:0] _zz_memory_DivPlugin_div_result_4; |
| wire [0:0] _zz_memory_DivPlugin_div_result_5; |
| wire [32:0] _zz_memory_DivPlugin_rs1_2; |
| wire [0:0] _zz_memory_DivPlugin_rs1_3; |
| wire [31:0] _zz_memory_DivPlugin_rs2_1; |
| wire [0:0] _zz_memory_DivPlugin_rs2_2; |
| wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; |
| wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1; |
| wire _zz_when; |
| wire [29:0] _zz_CsrPlugin_jumpInterface_payload; |
| wire [29:0] _zz_CsrPlugin_jumpInterface_payload_1; |
| wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2; |
| wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4; |
| wire [9:0] _zz_MmuPlugin_ports_0_cacheHitsCalc; |
| wire [9:0] _zz_MmuPlugin_ports_0_cacheHitsCalc_1; |
| wire _zz_MmuPlugin_ports_0_cacheHitsCalc_2; |
| wire _zz_MmuPlugin_ports_0_cacheHitsCalc_3; |
| wire _zz_MmuPlugin_ports_0_cacheHitsCalc_4; |
| wire _zz_MmuPlugin_ports_0_cacheHitsCalc_5; |
| reg _zz_MmuPlugin_ports_0_cacheLine_valid_4; |
| reg _zz_MmuPlugin_ports_0_cacheLine_exception; |
| reg _zz_MmuPlugin_ports_0_cacheLine_superPage; |
| reg [9:0] _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_0; |
| reg [9:0] _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_1; |
| reg [9:0] _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_0; |
| reg [9:0] _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_1; |
| reg _zz_MmuPlugin_ports_0_cacheLine_allowRead; |
| reg _zz_MmuPlugin_ports_0_cacheLine_allowWrite; |
| reg _zz_MmuPlugin_ports_0_cacheLine_allowExecute; |
| reg _zz_MmuPlugin_ports_0_cacheLine_allowUser; |
| wire [1:0] _zz_MmuPlugin_ports_0_entryToReplace_valueNext; |
| wire [0:0] _zz_MmuPlugin_ports_0_entryToReplace_valueNext_1; |
| wire [9:0] _zz_MmuPlugin_ports_1_cacheHitsCalc; |
| wire [9:0] _zz_MmuPlugin_ports_1_cacheHitsCalc_1; |
| wire _zz_MmuPlugin_ports_1_cacheHitsCalc_2; |
| wire _zz_MmuPlugin_ports_1_cacheHitsCalc_3; |
| wire _zz_MmuPlugin_ports_1_cacheHitsCalc_4; |
| wire _zz_MmuPlugin_ports_1_cacheHitsCalc_5; |
| reg _zz_MmuPlugin_ports_1_cacheLine_valid_4; |
| reg _zz_MmuPlugin_ports_1_cacheLine_exception; |
| reg _zz_MmuPlugin_ports_1_cacheLine_superPage; |
| reg [9:0] _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_0; |
| reg [9:0] _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_1; |
| reg [9:0] _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_0; |
| reg [9:0] _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_1; |
| reg _zz_MmuPlugin_ports_1_cacheLine_allowRead; |
| reg _zz_MmuPlugin_ports_1_cacheLine_allowWrite; |
| reg _zz_MmuPlugin_ports_1_cacheLine_allowExecute; |
| reg _zz_MmuPlugin_ports_1_cacheLine_allowUser; |
| wire [1:0] _zz_MmuPlugin_ports_1_entryToReplace_valueNext; |
| wire [0:0] _zz_MmuPlugin_ports_1_entryToReplace_valueNext_1; |
| wire [1:0] _zz__zz_MmuPlugin_shared_refills_2; |
| wire [26:0] _zz_iBusWishbone_ADR_1; |
| wire [51:0] memory_MUL_LOW; |
| wire [33:0] memory_MUL_HH; |
| wire [33:0] execute_MUL_HH; |
| wire [33:0] execute_MUL_HL; |
| wire [33:0] execute_MUL_LH; |
| wire [31:0] execute_MUL_LL; |
| wire [31:0] execute_SHIFT_RIGHT; |
| wire [31:0] execute_REGFILE_WRITE_DATA; |
| wire execute_IS_DBUS_SHARING; |
| wire [31:0] memory_MEMORY_STORE_DATA_RF; |
| wire [31:0] execute_MEMORY_STORE_DATA_RF; |
| wire decode_CSR_READ_OPCODE; |
| wire decode_CSR_WRITE_OPCODE; |
| wire decode_DO_EBREAK; |
| wire [31:0] decode_SRC2; |
| wire [31:0] decode_SRC1; |
| wire decode_SRC2_FORCE_ZERO; |
| wire decode_IS_SFENCE_VMA2; |
| wire [1:0] decode_BRANCH_CTRL; |
| wire [1:0] _zz_decode_BRANCH_CTRL; |
| wire [1:0] _zz_decode_to_execute_BRANCH_CTRL; |
| wire [1:0] _zz_decode_to_execute_BRANCH_CTRL_1; |
| wire [0:0] _zz_memory_to_writeBack_ENV_CTRL; |
| wire [0:0] _zz_memory_to_writeBack_ENV_CTRL_1; |
| wire [0:0] _zz_execute_to_memory_ENV_CTRL; |
| wire [0:0] _zz_execute_to_memory_ENV_CTRL_1; |
| wire [0:0] decode_ENV_CTRL; |
| wire [0:0] _zz_decode_ENV_CTRL; |
| wire [0:0] _zz_decode_to_execute_ENV_CTRL; |
| wire [0:0] _zz_decode_to_execute_ENV_CTRL_1; |
| wire decode_IS_CSR; |
| wire decode_IS_RS2_SIGNED; |
| wire decode_IS_RS1_SIGNED; |
| wire decode_IS_DIV; |
| wire memory_IS_MUL; |
| wire execute_IS_MUL; |
| wire decode_IS_MUL; |
| wire [1:0] _zz_execute_to_memory_SHIFT_CTRL; |
| wire [1:0] _zz_execute_to_memory_SHIFT_CTRL_1; |
| wire [1:0] decode_SHIFT_CTRL; |
| wire [1:0] _zz_decode_SHIFT_CTRL; |
| wire [1:0] _zz_decode_to_execute_SHIFT_CTRL; |
| wire [1:0] _zz_decode_to_execute_SHIFT_CTRL_1; |
| wire [1:0] decode_ALU_BITWISE_CTRL; |
| wire [1:0] _zz_decode_ALU_BITWISE_CTRL; |
| wire [1:0] _zz_decode_to_execute_ALU_BITWISE_CTRL; |
| wire [1:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1; |
| wire decode_SRC_LESS_UNSIGNED; |
| wire decode_MEMORY_MANAGMENT; |
| wire memory_MEMORY_WR; |
| wire decode_MEMORY_WR; |
| wire execute_BYPASSABLE_MEMORY_STAGE; |
| wire decode_BYPASSABLE_MEMORY_STAGE; |
| wire decode_BYPASSABLE_EXECUTE_STAGE; |
| wire [1:0] decode_ALU_CTRL; |
| wire [1:0] _zz_decode_ALU_CTRL; |
| wire [1:0] _zz_decode_to_execute_ALU_CTRL; |
| wire [1:0] _zz_decode_to_execute_ALU_CTRL_1; |
| wire decode_MEMORY_FORCE_CONSTISTENCY; |
| wire [31:0] writeBack_FORMAL_PC_NEXT; |
| wire [31:0] memory_FORMAL_PC_NEXT; |
| wire [31:0] execute_FORMAL_PC_NEXT; |
| wire [31:0] decode_FORMAL_PC_NEXT; |
| wire [31:0] memory_PC; |
| wire execute_IS_SFENCE_VMA2; |
| wire [31:0] execute_BRANCH_CALC; |
| wire execute_BRANCH_DO; |
| wire [1:0] execute_BRANCH_CTRL; |
| wire [1:0] _zz_execute_BRANCH_CTRL; |
| wire execute_CSR_READ_OPCODE; |
| wire execute_CSR_WRITE_OPCODE; |
| wire execute_IS_CSR; |
| wire [0:0] memory_ENV_CTRL; |
| wire [0:0] _zz_memory_ENV_CTRL; |
| wire [0:0] execute_ENV_CTRL; |
| wire [0:0] _zz_execute_ENV_CTRL; |
| wire [0:0] writeBack_ENV_CTRL; |
| wire [0:0] _zz_writeBack_ENV_CTRL; |
| wire [31:0] execute_PC; |
| wire execute_DO_EBREAK; |
| wire decode_IS_EBREAK; |
| wire decode_RS2_USE; |
| wire decode_RS1_USE; |
| reg [31:0] _zz_decode_RS2; |
| wire execute_REGFILE_WRITE_VALID; |
| wire execute_BYPASSABLE_EXECUTE_STAGE; |
| wire memory_REGFILE_WRITE_VALID; |
| wire memory_BYPASSABLE_MEMORY_STAGE; |
| wire writeBack_REGFILE_WRITE_VALID; |
| reg [31:0] decode_RS2; |
| reg [31:0] decode_RS1; |
| wire execute_IS_RS1_SIGNED; |
| wire execute_IS_DIV; |
| wire execute_IS_RS2_SIGNED; |
| wire [31:0] memory_INSTRUCTION; |
| wire memory_IS_DIV; |
| wire writeBack_IS_MUL; |
| wire [33:0] writeBack_MUL_HH; |
| wire [51:0] writeBack_MUL_LOW; |
| wire [33:0] memory_MUL_HL; |
| wire [33:0] memory_MUL_LH; |
| wire [31:0] memory_MUL_LL; |
| (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; |
| wire [31:0] memory_SHIFT_RIGHT; |
| reg [31:0] _zz_decode_RS2_1; |
| wire [1:0] memory_SHIFT_CTRL; |
| wire [1:0] _zz_memory_SHIFT_CTRL; |
| wire [1:0] execute_SHIFT_CTRL; |
| wire [1:0] _zz_execute_SHIFT_CTRL; |
| wire execute_SRC_LESS_UNSIGNED; |
| wire execute_SRC2_FORCE_ZERO; |
| wire execute_SRC_USE_SUB_LESS; |
| wire [31:0] _zz_decode_SRC2; |
| wire [31:0] _zz_decode_SRC2_1; |
| wire [1:0] decode_SRC2_CTRL; |
| wire [1:0] _zz_decode_SRC2_CTRL; |
| wire [31:0] _zz_decode_SRC1; |
| wire [1:0] decode_SRC1_CTRL; |
| wire [1:0] _zz_decode_SRC1_CTRL; |
| wire decode_SRC_USE_SUB_LESS; |
| wire decode_SRC_ADD_ZERO; |
| wire [31:0] execute_SRC_ADD_SUB; |
| wire execute_SRC_LESS; |
| wire [1:0] execute_ALU_CTRL; |
| wire [1:0] _zz_execute_ALU_CTRL; |
| wire [31:0] execute_SRC2; |
| wire [31:0] execute_SRC1; |
| wire [1:0] execute_ALU_BITWISE_CTRL; |
| wire [1:0] _zz_execute_ALU_BITWISE_CTRL; |
| wire [31:0] _zz_lastStageRegFileWrite_payload_address; |
| wire _zz_lastStageRegFileWrite_valid; |
| reg _zz_1; |
| wire [31:0] decode_INSTRUCTION_ANTICIPATED; |
| reg decode_REGFILE_WRITE_VALID; |
| wire decode_LEGAL_INSTRUCTION; |
| wire [1:0] _zz_decode_BRANCH_CTRL_1; |
| wire [0:0] _zz_decode_ENV_CTRL_1; |
| wire [1:0] _zz_decode_SHIFT_CTRL_1; |
| wire [1:0] _zz_decode_ALU_BITWISE_CTRL_1; |
| wire [1:0] _zz_decode_SRC2_CTRL_1; |
| wire [1:0] _zz_decode_ALU_CTRL_1; |
| wire [1:0] _zz_decode_SRC1_CTRL_1; |
| wire writeBack_IS_DBUS_SHARING; |
| wire memory_IS_DBUS_SHARING; |
| reg [31:0] _zz_decode_RS2_2; |
| wire writeBack_MEMORY_WR; |
| wire [31:0] writeBack_MEMORY_STORE_DATA_RF; |
| wire [31:0] writeBack_REGFILE_WRITE_DATA; |
| wire writeBack_MEMORY_ENABLE; |
| wire [31:0] memory_REGFILE_WRITE_DATA; |
| wire memory_MEMORY_ENABLE; |
| wire execute_MEMORY_FORCE_CONSTISTENCY; |
| wire execute_MEMORY_MANAGMENT; |
| (* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ; |
| wire execute_MEMORY_WR; |
| wire [31:0] execute_SRC_ADD; |
| wire execute_MEMORY_ENABLE; |
| wire [31:0] execute_INSTRUCTION; |
| wire decode_MEMORY_ENABLE; |
| wire decode_FLUSH_ALL; |
| reg IBusCachedPlugin_rsp_issueDetected_4; |
| reg IBusCachedPlugin_rsp_issueDetected_3; |
| reg IBusCachedPlugin_rsp_issueDetected_2; |
| reg IBusCachedPlugin_rsp_issueDetected_1; |
| wire [31:0] decode_INSTRUCTION; |
| reg [31:0] _zz_execute_to_memory_FORMAL_PC_NEXT; |
| wire [31:0] decode_PC; |
| wire [31:0] writeBack_PC; |
| wire [31:0] writeBack_INSTRUCTION; |
| reg decode_arbitration_haltItself; |
| reg decode_arbitration_haltByOther; |
| reg decode_arbitration_removeIt; |
| wire decode_arbitration_flushIt; |
| reg decode_arbitration_flushNext; |
| reg decode_arbitration_isValid; |
| wire decode_arbitration_isStuck; |
| wire decode_arbitration_isStuckByOthers; |
| wire decode_arbitration_isFlushed; |
| wire decode_arbitration_isMoving; |
| wire decode_arbitration_isFiring; |
| reg execute_arbitration_haltItself; |
| reg execute_arbitration_haltByOther; |
| reg execute_arbitration_removeIt; |
| reg execute_arbitration_flushIt; |
| reg execute_arbitration_flushNext; |
| reg execute_arbitration_isValid; |
| wire execute_arbitration_isStuck; |
| wire execute_arbitration_isStuckByOthers; |
| wire execute_arbitration_isFlushed; |
| wire execute_arbitration_isMoving; |
| wire execute_arbitration_isFiring; |
| reg memory_arbitration_haltItself; |
| wire memory_arbitration_haltByOther; |
| reg memory_arbitration_removeIt; |
| wire memory_arbitration_flushIt; |
| wire memory_arbitration_flushNext; |
| reg memory_arbitration_isValid; |
| wire memory_arbitration_isStuck; |
| wire memory_arbitration_isStuckByOthers; |
| wire memory_arbitration_isFlushed; |
| wire memory_arbitration_isMoving; |
| wire memory_arbitration_isFiring; |
| reg writeBack_arbitration_haltItself; |
| wire writeBack_arbitration_haltByOther; |
| reg writeBack_arbitration_removeIt; |
| reg writeBack_arbitration_flushIt; |
| reg writeBack_arbitration_flushNext; |
| reg writeBack_arbitration_isValid; |
| wire writeBack_arbitration_isStuck; |
| wire writeBack_arbitration_isStuckByOthers; |
| wire writeBack_arbitration_isFlushed; |
| wire writeBack_arbitration_isMoving; |
| wire writeBack_arbitration_isFiring; |
| wire [31:0] lastStageInstruction /* verilator public */ ; |
| wire [31:0] lastStagePc /* verilator public */ ; |
| wire lastStageIsValid /* verilator public */ ; |
| wire lastStageIsFiring /* verilator public */ ; |
| reg IBusCachedPlugin_fetcherHalt; |
| reg IBusCachedPlugin_incomingInstruction; |
| wire IBusCachedPlugin_pcValids_0; |
| wire IBusCachedPlugin_pcValids_1; |
| wire IBusCachedPlugin_pcValids_2; |
| wire IBusCachedPlugin_pcValids_3; |
| reg IBusCachedPlugin_decodeExceptionPort_valid; |
| reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; |
| wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; |
| wire IBusCachedPlugin_mmuBus_cmd_0_isValid; |
| wire IBusCachedPlugin_mmuBus_cmd_0_isStuck; |
| wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; |
| wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; |
| reg [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; |
| wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; |
| reg IBusCachedPlugin_mmuBus_rsp_isPaging; |
| reg IBusCachedPlugin_mmuBus_rsp_allowRead; |
| reg IBusCachedPlugin_mmuBus_rsp_allowWrite; |
| reg IBusCachedPlugin_mmuBus_rsp_allowExecute; |
| reg IBusCachedPlugin_mmuBus_rsp_exception; |
| reg IBusCachedPlugin_mmuBus_rsp_refilling; |
| wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation; |
| wire IBusCachedPlugin_mmuBus_rsp_ways_0_sel; |
| wire [31:0] IBusCachedPlugin_mmuBus_rsp_ways_0_physical; |
| wire IBusCachedPlugin_mmuBus_rsp_ways_1_sel; |
| wire [31:0] IBusCachedPlugin_mmuBus_rsp_ways_1_physical; |
| wire IBusCachedPlugin_mmuBus_rsp_ways_2_sel; |
| wire [31:0] IBusCachedPlugin_mmuBus_rsp_ways_2_physical; |
| wire IBusCachedPlugin_mmuBus_rsp_ways_3_sel; |
| wire [31:0] IBusCachedPlugin_mmuBus_rsp_ways_3_physical; |
| wire IBusCachedPlugin_mmuBus_end; |
| wire IBusCachedPlugin_mmuBus_busy; |
| wire dBus_cmd_valid; |
| wire dBus_cmd_ready; |
| wire dBus_cmd_payload_wr; |
| wire dBus_cmd_payload_uncached; |
| wire [31:0] dBus_cmd_payload_address; |
| wire [31:0] dBus_cmd_payload_data; |
| wire [3:0] dBus_cmd_payload_mask; |
| wire [2:0] dBus_cmd_payload_size; |
| wire dBus_cmd_payload_last; |
| wire dBus_rsp_valid; |
| wire dBus_rsp_payload_last; |
| wire [31:0] dBus_rsp_payload_data; |
| wire dBus_rsp_payload_error; |
| wire DBusCachedPlugin_mmuBus_cmd_0_isValid; |
| wire DBusCachedPlugin_mmuBus_cmd_0_isStuck; |
| wire [31:0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; |
| reg DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; |
| reg [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; |
| wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; |
| reg DBusCachedPlugin_mmuBus_rsp_isPaging; |
| reg DBusCachedPlugin_mmuBus_rsp_allowRead; |
| reg DBusCachedPlugin_mmuBus_rsp_allowWrite; |
| reg DBusCachedPlugin_mmuBus_rsp_allowExecute; |
| reg DBusCachedPlugin_mmuBus_rsp_exception; |
| reg DBusCachedPlugin_mmuBus_rsp_refilling; |
| wire DBusCachedPlugin_mmuBus_rsp_bypassTranslation; |
| wire DBusCachedPlugin_mmuBus_rsp_ways_0_sel; |
| wire [31:0] DBusCachedPlugin_mmuBus_rsp_ways_0_physical; |
| wire DBusCachedPlugin_mmuBus_rsp_ways_1_sel; |
| wire [31:0] DBusCachedPlugin_mmuBus_rsp_ways_1_physical; |
| wire DBusCachedPlugin_mmuBus_rsp_ways_2_sel; |
| wire [31:0] DBusCachedPlugin_mmuBus_rsp_ways_2_physical; |
| wire DBusCachedPlugin_mmuBus_rsp_ways_3_sel; |
| wire [31:0] DBusCachedPlugin_mmuBus_rsp_ways_3_physical; |
| wire DBusCachedPlugin_mmuBus_end; |
| wire DBusCachedPlugin_mmuBus_busy; |
| reg DBusCachedPlugin_redoBranch_valid; |
| wire [31:0] DBusCachedPlugin_redoBranch_payload; |
| reg DBusCachedPlugin_exceptionBus_valid; |
| reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; |
| wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; |
| reg _zz_when_DBusCachedPlugin_l390; |
| wire decodeExceptionPort_valid; |
| wire [3:0] decodeExceptionPort_payload_code; |
| wire [31:0] decodeExceptionPort_payload_badAddr; |
| wire debug_bus_cmd_valid; |
| reg debug_bus_cmd_ready; |
| wire debug_bus_cmd_payload_wr; |
| wire [7:0] debug_bus_cmd_payload_address; |
| wire [31:0] debug_bus_cmd_payload_data; |
| reg [31:0] debug_bus_rsp_data; |
| reg IBusCachedPlugin_injectionPort_valid; |
| reg IBusCachedPlugin_injectionPort_ready; |
| wire [31:0] IBusCachedPlugin_injectionPort_payload; |
| wire [31:0] CsrPlugin_csrMapping_readDataSignal; |
| wire [31:0] CsrPlugin_csrMapping_readDataInit; |
| wire [31:0] CsrPlugin_csrMapping_writeDataSignal; |
| wire CsrPlugin_csrMapping_allowCsrSignal; |
| wire CsrPlugin_csrMapping_hazardFree; |
| wire CsrPlugin_inWfi /* verilator public */ ; |
| reg CsrPlugin_thirdPartyWake; |
| reg CsrPlugin_jumpInterface_valid; |
| reg [31:0] CsrPlugin_jumpInterface_payload; |
| wire CsrPlugin_exceptionPendings_0; |
| wire CsrPlugin_exceptionPendings_1; |
| wire CsrPlugin_exceptionPendings_2; |
| wire CsrPlugin_exceptionPendings_3; |
| wire contextSwitching; |
| reg [1:0] CsrPlugin_privilege; |
| reg CsrPlugin_forceMachineWire; |
| reg CsrPlugin_allowInterrupts; |
| reg CsrPlugin_allowException; |
| reg CsrPlugin_allowEbreakException; |
| wire BranchPlugin_jumpInterface_valid; |
| wire [31:0] BranchPlugin_jumpInterface_payload; |
| reg BranchPlugin_branchExceptionPort_valid; |
| wire [3:0] BranchPlugin_branchExceptionPort_payload_code; |
| wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; |
| reg MmuPlugin_dBusAccess_cmd_valid; |
| reg MmuPlugin_dBusAccess_cmd_ready; |
| reg [31:0] MmuPlugin_dBusAccess_cmd_payload_address; |
| wire [1:0] MmuPlugin_dBusAccess_cmd_payload_size; |
| wire MmuPlugin_dBusAccess_cmd_payload_write; |
| wire [31:0] MmuPlugin_dBusAccess_cmd_payload_data; |
| wire [3:0] MmuPlugin_dBusAccess_cmd_payload_writeMask; |
| wire MmuPlugin_dBusAccess_rsp_valid; |
| wire [31:0] MmuPlugin_dBusAccess_rsp_payload_data; |
| wire MmuPlugin_dBusAccess_rsp_payload_error; |
| wire MmuPlugin_dBusAccess_rsp_payload_redo; |
| wire IBusCachedPlugin_externalFlush; |
| wire IBusCachedPlugin_jump_pcLoad_valid; |
| wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; |
| wire [2:0] _zz_IBusCachedPlugin_jump_pcLoad_payload; |
| wire [2:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_1; |
| wire _zz_IBusCachedPlugin_jump_pcLoad_payload_2; |
| wire _zz_IBusCachedPlugin_jump_pcLoad_payload_3; |
| wire IBusCachedPlugin_fetchPc_output_valid; |
| wire IBusCachedPlugin_fetchPc_output_ready; |
| wire [31:0] IBusCachedPlugin_fetchPc_output_payload; |
| reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; |
| reg IBusCachedPlugin_fetchPc_correction; |
| reg IBusCachedPlugin_fetchPc_correctionReg; |
| wire IBusCachedPlugin_fetchPc_output_fire; |
| wire IBusCachedPlugin_fetchPc_corrected; |
| reg IBusCachedPlugin_fetchPc_pcRegPropagate; |
| reg IBusCachedPlugin_fetchPc_booted; |
| reg IBusCachedPlugin_fetchPc_inc; |
| wire when_Fetcher_l131; |
| wire IBusCachedPlugin_fetchPc_output_fire_1; |
| wire when_Fetcher_l131_1; |
| reg [31:0] IBusCachedPlugin_fetchPc_pc; |
| wire IBusCachedPlugin_fetchPc_redo_valid; |
| wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; |
| reg IBusCachedPlugin_fetchPc_flushed; |
| wire when_Fetcher_l158; |
| reg IBusCachedPlugin_iBusRsp_redoFetch; |
| wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; |
| wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; |
| wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; |
| wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; |
| wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; |
| wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; |
| reg IBusCachedPlugin_iBusRsp_stages_0_halt; |
| wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; |
| wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; |
| wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; |
| wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; |
| wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; |
| wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; |
| reg IBusCachedPlugin_iBusRsp_stages_1_halt; |
| wire IBusCachedPlugin_iBusRsp_stages_2_input_valid; |
| wire IBusCachedPlugin_iBusRsp_stages_2_input_ready; |
| wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload; |
| wire IBusCachedPlugin_iBusRsp_stages_2_output_valid; |
| wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; |
| wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; |
| reg IBusCachedPlugin_iBusRsp_stages_2_halt; |
| wire _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready; |
| wire _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready; |
| wire _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready; |
| wire IBusCachedPlugin_iBusRsp_flush; |
| wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; |
| wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; |
| reg _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; |
| wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; |
| wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready; |
| wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; |
| reg _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; |
| reg [31:0] _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; |
| reg IBusCachedPlugin_iBusRsp_readyForError; |
| wire IBusCachedPlugin_iBusRsp_output_valid; |
| wire IBusCachedPlugin_iBusRsp_output_ready; |
| wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc; |
| wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; |
| wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; |
| wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; |
| wire when_Fetcher_l240; |
| wire when_Fetcher_l320; |
| reg IBusCachedPlugin_injector_nextPcCalc_valids_0; |
| wire when_Fetcher_l329; |
| reg IBusCachedPlugin_injector_nextPcCalc_valids_1; |
| wire when_Fetcher_l329_1; |
| reg IBusCachedPlugin_injector_nextPcCalc_valids_2; |
| wire when_Fetcher_l329_2; |
| reg IBusCachedPlugin_injector_nextPcCalc_valids_3; |
| wire when_Fetcher_l329_3; |
| reg IBusCachedPlugin_injector_nextPcCalc_valids_4; |
| wire when_Fetcher_l329_4; |
| wire iBus_cmd_valid; |
| wire iBus_cmd_ready; |
| reg [31:0] iBus_cmd_payload_address; |
| wire [2:0] iBus_cmd_payload_size; |
| wire iBus_rsp_valid; |
| wire [31:0] iBus_rsp_payload_data; |
| wire iBus_rsp_payload_error; |
| wire [31:0] _zz_IBusCachedPlugin_rspCounter; |
| reg [31:0] IBusCachedPlugin_rspCounter; |
| wire IBusCachedPlugin_s0_tightlyCoupledHit; |
| reg IBusCachedPlugin_s1_tightlyCoupledHit; |
| reg IBusCachedPlugin_s2_tightlyCoupledHit; |
| wire IBusCachedPlugin_rsp_iBusRspOutputHalt; |
| wire IBusCachedPlugin_rsp_issueDetected; |
| reg IBusCachedPlugin_rsp_redoFetch; |
| wire when_IBusCachedPlugin_l239; |
| wire when_IBusCachedPlugin_l244; |
| wire when_IBusCachedPlugin_l250; |
| wire when_IBusCachedPlugin_l256; |
| wire when_IBusCachedPlugin_l267; |
| wire dataCache_1_io_mem_cmd_m2sPipe_valid; |
| wire dataCache_1_io_mem_cmd_m2sPipe_ready; |
| wire dataCache_1_io_mem_cmd_m2sPipe_payload_wr; |
| wire dataCache_1_io_mem_cmd_m2sPipe_payload_uncached; |
| wire [31:0] dataCache_1_io_mem_cmd_m2sPipe_payload_address; |
| wire [31:0] dataCache_1_io_mem_cmd_m2sPipe_payload_data; |
| wire [3:0] dataCache_1_io_mem_cmd_m2sPipe_payload_mask; |
| wire [2:0] dataCache_1_io_mem_cmd_m2sPipe_payload_size; |
| wire dataCache_1_io_mem_cmd_m2sPipe_payload_last; |
| reg dataCache_1_io_mem_cmd_rValid; |
| reg dataCache_1_io_mem_cmd_rData_wr; |
| reg dataCache_1_io_mem_cmd_rData_uncached; |
| reg [31:0] dataCache_1_io_mem_cmd_rData_address; |
| reg [31:0] dataCache_1_io_mem_cmd_rData_data; |
| reg [3:0] dataCache_1_io_mem_cmd_rData_mask; |
| reg [2:0] dataCache_1_io_mem_cmd_rData_size; |
| reg dataCache_1_io_mem_cmd_rData_last; |
| wire when_Stream_l342; |
| wire [31:0] _zz_DBusCachedPlugin_rspCounter; |
| reg [31:0] DBusCachedPlugin_rspCounter; |
| wire when_DBusCachedPlugin_l307; |
| wire [1:0] execute_DBusCachedPlugin_size; |
| reg [31:0] _zz_execute_MEMORY_STORE_DATA_RF; |
| wire dataCache_1_io_cpu_flush_isStall; |
| wire when_DBusCachedPlugin_l347; |
| wire when_DBusCachedPlugin_l363; |
| wire when_DBusCachedPlugin_l390; |
| wire when_DBusCachedPlugin_l442; |
| wire when_DBusCachedPlugin_l462; |
| wire [7:0] writeBack_DBusCachedPlugin_rspSplits_0; |
| wire [7:0] writeBack_DBusCachedPlugin_rspSplits_1; |
| wire [7:0] writeBack_DBusCachedPlugin_rspSplits_2; |
| wire [7:0] writeBack_DBusCachedPlugin_rspSplits_3; |
| reg [31:0] writeBack_DBusCachedPlugin_rspShifted; |
| wire [31:0] writeBack_DBusCachedPlugin_rspRf; |
| wire [1:0] switch_Misc_l211; |
| wire _zz_writeBack_DBusCachedPlugin_rspFormated; |
| reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_1; |
| wire _zz_writeBack_DBusCachedPlugin_rspFormated_2; |
| reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_3; |
| reg [31:0] writeBack_DBusCachedPlugin_rspFormated; |
| wire when_DBusCachedPlugin_l488; |
| reg DBusCachedPlugin_forceDatapath; |
| wire when_DBusCachedPlugin_l502; |
| wire when_DBusCachedPlugin_l503; |
| wire MmuPlugin_dBusAccess_cmd_fire; |
| wire [32:0] _zz_decode_IS_SFENCE_VMA2; |
| wire _zz_decode_IS_SFENCE_VMA2_1; |
| wire _zz_decode_IS_SFENCE_VMA2_2; |
| wire _zz_decode_IS_SFENCE_VMA2_3; |
| wire _zz_decode_IS_SFENCE_VMA2_4; |
| wire _zz_decode_IS_SFENCE_VMA2_5; |
| wire [1:0] _zz_decode_SRC1_CTRL_2; |
| wire [1:0] _zz_decode_ALU_CTRL_2; |
| wire [1:0] _zz_decode_SRC2_CTRL_2; |
| wire [1:0] _zz_decode_ALU_BITWISE_CTRL_2; |
| wire [1:0] _zz_decode_SHIFT_CTRL_2; |
| wire [0:0] _zz_decode_ENV_CTRL_2; |
| wire [1:0] _zz_decode_BRANCH_CTRL_2; |
| wire when_RegFilePlugin_l63; |
| wire [4:0] decode_RegFilePlugin_regFileReadAddress1; |
| wire [4:0] decode_RegFilePlugin_regFileReadAddress2; |
| wire [31:0] decode_RegFilePlugin_rs1Data; |
| wire [31:0] decode_RegFilePlugin_rs2Data; |
| reg lastStageRegFileWrite_valid /* verilator public */ ; |
| reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; |
| reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; |
| reg _zz_2; |
| reg [31:0] execute_IntAluPlugin_bitwise; |
| reg [31:0] _zz_execute_REGFILE_WRITE_DATA; |
| reg [31:0] _zz_decode_SRC1_1; |
| wire _zz_decode_SRC2_2; |
| reg [19:0] _zz_decode_SRC2_3; |
| wire _zz_decode_SRC2_4; |
| reg [19:0] _zz_decode_SRC2_5; |
| reg [31:0] _zz_decode_SRC2_6; |
| reg [31:0] execute_SrcPlugin_addSub; |
| wire execute_SrcPlugin_less; |
| wire [4:0] execute_FullBarrelShifterPlugin_amplitude; |
| reg [31:0] _zz_execute_FullBarrelShifterPlugin_reversed; |
| wire [31:0] execute_FullBarrelShifterPlugin_reversed; |
| reg [31:0] _zz_decode_RS2_3; |
| reg execute_MulPlugin_aSigned; |
| reg execute_MulPlugin_bSigned; |
| wire [31:0] execute_MulPlugin_a; |
| wire [31:0] execute_MulPlugin_b; |
| wire [1:0] switch_MulPlugin_l87; |
| wire [15:0] execute_MulPlugin_aULow; |
| wire [15:0] execute_MulPlugin_bULow; |
| wire [16:0] execute_MulPlugin_aSLow; |
| wire [16:0] execute_MulPlugin_bSLow; |
| wire [16:0] execute_MulPlugin_aHigh; |
| wire [16:0] execute_MulPlugin_bHigh; |
| wire [65:0] writeBack_MulPlugin_result; |
| wire when_MulPlugin_l147; |
| wire [1:0] switch_MulPlugin_l148; |
| reg [32:0] memory_DivPlugin_rs1; |
| reg [31:0] memory_DivPlugin_rs2; |
| reg [64:0] memory_DivPlugin_accumulator; |
| wire memory_DivPlugin_frontendOk; |
| reg memory_DivPlugin_div_needRevert; |
| reg memory_DivPlugin_div_counter_willIncrement; |
| reg memory_DivPlugin_div_counter_willClear; |
| reg [5:0] memory_DivPlugin_div_counter_valueNext; |
| reg [5:0] memory_DivPlugin_div_counter_value; |
| wire memory_DivPlugin_div_counter_willOverflowIfInc; |
| wire memory_DivPlugin_div_counter_willOverflow; |
| reg memory_DivPlugin_div_done; |
| wire when_MulDivIterativePlugin_l126; |
| wire when_MulDivIterativePlugin_l126_1; |
| reg [31:0] memory_DivPlugin_div_result; |
| wire when_MulDivIterativePlugin_l128; |
| wire when_MulDivIterativePlugin_l129; |
| wire when_MulDivIterativePlugin_l132; |
| wire [31:0] _zz_memory_DivPlugin_div_stage_0_remainderShifted; |
| wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; |
| wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; |
| wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; |
| wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; |
| wire when_MulDivIterativePlugin_l151; |
| wire [31:0] _zz_memory_DivPlugin_div_result; |
| wire when_MulDivIterativePlugin_l162; |
| wire _zz_memory_DivPlugin_rs2; |
| wire _zz_memory_DivPlugin_rs1; |
| reg [32:0] _zz_memory_DivPlugin_rs1_1; |
| reg HazardSimplePlugin_src0Hazard; |
| reg HazardSimplePlugin_src1Hazard; |
| wire HazardSimplePlugin_writeBackWrites_valid; |
| wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; |
| wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; |
| reg HazardSimplePlugin_writeBackBuffer_valid; |
| reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; |
| reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; |
| wire HazardSimplePlugin_addr0Match; |
| wire HazardSimplePlugin_addr1Match; |
| wire when_HazardSimplePlugin_l47; |
| wire when_HazardSimplePlugin_l48; |
| wire when_HazardSimplePlugin_l51; |
| wire when_HazardSimplePlugin_l45; |
| wire when_HazardSimplePlugin_l57; |
| wire when_HazardSimplePlugin_l58; |
| wire when_HazardSimplePlugin_l48_1; |
| wire when_HazardSimplePlugin_l51_1; |
| wire when_HazardSimplePlugin_l45_1; |
| wire when_HazardSimplePlugin_l57_1; |
| wire when_HazardSimplePlugin_l58_1; |
| wire when_HazardSimplePlugin_l48_2; |
| wire when_HazardSimplePlugin_l51_2; |
| wire when_HazardSimplePlugin_l45_2; |
| wire when_HazardSimplePlugin_l57_2; |
| wire when_HazardSimplePlugin_l58_2; |
| wire when_HazardSimplePlugin_l105; |
| wire when_HazardSimplePlugin_l108; |
| wire when_HazardSimplePlugin_l113; |
| reg DebugPlugin_firstCycle; |
| reg DebugPlugin_secondCycle; |
| reg DebugPlugin_resetIt; |
| reg DebugPlugin_haltIt; |
| reg DebugPlugin_stepIt; |
| reg DebugPlugin_isPipBusy; |
| reg DebugPlugin_godmode; |
| wire when_DebugPlugin_l225; |
| reg DebugPlugin_haltedByBreak; |
| reg DebugPlugin_debugUsed /* verilator public */ ; |
| reg DebugPlugin_disableEbreak; |
| wire DebugPlugin_allowEBreak; |
| reg [31:0] DebugPlugin_busReadDataReg; |
| reg _zz_when_DebugPlugin_l244; |
| wire when_DebugPlugin_l244; |
| wire [5:0] switch_DebugPlugin_l267; |
| wire when_DebugPlugin_l271; |
| wire when_DebugPlugin_l271_1; |
| wire when_DebugPlugin_l272; |
| wire when_DebugPlugin_l272_1; |
| wire when_DebugPlugin_l273; |
| wire when_DebugPlugin_l274; |
| wire when_DebugPlugin_l275; |
| wire when_DebugPlugin_l275_1; |
| wire when_DebugPlugin_l295; |
| wire when_DebugPlugin_l298; |
| wire when_DebugPlugin_l311; |
| reg DebugPlugin_resetIt_regNext; |
| wire when_DebugPlugin_l327; |
| wire [1:0] CsrPlugin_misa_base; |
| wire [25:0] CsrPlugin_misa_extensions; |
| reg [1:0] CsrPlugin_mtvec_mode; |
| reg [29:0] CsrPlugin_mtvec_base; |
| reg [31:0] CsrPlugin_mepc; |
| reg CsrPlugin_mstatus_MIE; |
| reg CsrPlugin_mstatus_MPIE; |
| reg [1:0] CsrPlugin_mstatus_MPP; |
| reg CsrPlugin_mip_MEIP; |
| reg CsrPlugin_mip_MTIP; |
| reg CsrPlugin_mip_MSIP; |
| reg CsrPlugin_mie_MEIE; |
| reg CsrPlugin_mie_MTIE; |
| reg CsrPlugin_mie_MSIE; |
| reg CsrPlugin_mcause_interrupt; |
| reg [3:0] CsrPlugin_mcause_exceptionCode; |
| reg [31:0] CsrPlugin_mtval; |
| reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; |
| reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; |
| wire _zz_when_CsrPlugin_l952; |
| wire _zz_when_CsrPlugin_l952_1; |
| wire _zz_when_CsrPlugin_l952_2; |
| reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; |
| reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; |
| reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; |
| reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; |
| reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; |
| reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; |
| reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; |
| reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; |
| reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; |
| reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; |
| wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; |
| wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; |
| wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code; |
| wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; |
| wire when_CsrPlugin_l909; |
| wire when_CsrPlugin_l909_1; |
| wire when_CsrPlugin_l909_2; |
| wire when_CsrPlugin_l909_3; |
| wire when_CsrPlugin_l922; |
| reg CsrPlugin_interrupt_valid; |
| reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; |
| reg [1:0] CsrPlugin_interrupt_targetPrivilege; |
| wire when_CsrPlugin_l946; |
| wire when_CsrPlugin_l952; |
| wire when_CsrPlugin_l952_1; |
| wire when_CsrPlugin_l952_2; |
| wire CsrPlugin_exception; |
| wire CsrPlugin_lastStageWasWfi; |
| reg CsrPlugin_pipelineLiberator_pcValids_0; |
| reg CsrPlugin_pipelineLiberator_pcValids_1; |
| reg CsrPlugin_pipelineLiberator_pcValids_2; |
| wire CsrPlugin_pipelineLiberator_active; |
| wire when_CsrPlugin_l980; |
| wire when_CsrPlugin_l980_1; |
| wire when_CsrPlugin_l980_2; |
| wire when_CsrPlugin_l985; |
| reg CsrPlugin_pipelineLiberator_done; |
| wire when_CsrPlugin_l991; |
| wire CsrPlugin_interruptJump /* verilator public */ ; |
| reg CsrPlugin_hadException /* verilator public */ ; |
| reg [1:0] CsrPlugin_targetPrivilege; |
| reg [3:0] CsrPlugin_trapCause; |
| reg [1:0] CsrPlugin_xtvec_mode; |
| reg [29:0] CsrPlugin_xtvec_base; |
| wire when_CsrPlugin_l1019; |
| wire when_CsrPlugin_l1064; |
| wire [1:0] switch_CsrPlugin_l1068; |
| reg execute_CsrPlugin_wfiWake; |
| wire when_CsrPlugin_l1116; |
| wire execute_CsrPlugin_blockedBySideEffects; |
| reg execute_CsrPlugin_illegalAccess; |
| reg execute_CsrPlugin_illegalInstruction; |
| wire when_CsrPlugin_l1136; |
| wire when_CsrPlugin_l1137; |
| reg execute_CsrPlugin_writeInstruction; |
| reg execute_CsrPlugin_readInstruction; |
| wire execute_CsrPlugin_writeEnable; |
| wire execute_CsrPlugin_readEnable; |
| wire [31:0] execute_CsrPlugin_readToWriteData; |
| wire switch_Misc_l211_1; |
| reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal; |
| wire when_CsrPlugin_l1176; |
| wire when_CsrPlugin_l1180; |
| wire [11:0] execute_CsrPlugin_csrAddress; |
| wire execute_BranchPlugin_eq; |
| wire [2:0] switch_Misc_l211_2; |
| reg _zz_execute_BRANCH_DO; |
| reg _zz_execute_BRANCH_DO_1; |
| wire [31:0] execute_BranchPlugin_branch_src1; |
| wire _zz_execute_BranchPlugin_branch_src2; |
| reg [10:0] _zz_execute_BranchPlugin_branch_src2_1; |
| wire _zz_execute_BranchPlugin_branch_src2_2; |
| reg [19:0] _zz_execute_BranchPlugin_branch_src2_3; |
| wire _zz_execute_BranchPlugin_branch_src2_4; |
| reg [18:0] _zz_execute_BranchPlugin_branch_src2_5; |
| reg [31:0] _zz_execute_BranchPlugin_branch_src2_6; |
| wire [31:0] execute_BranchPlugin_branch_src2; |
| wire [31:0] execute_BranchPlugin_branchAdder; |
| wire when_BranchPlugin_l216; |
| reg MmuPlugin_status_sum; |
| reg MmuPlugin_status_mxr; |
| reg MmuPlugin_status_mprv; |
| reg MmuPlugin_satp_mode; |
| reg [8:0] MmuPlugin_satp_asid; |
| reg [19:0] MmuPlugin_satp_ppn; |
| reg MmuPlugin_ports_0_cache_0_valid; |
| reg MmuPlugin_ports_0_cache_0_exception; |
| reg MmuPlugin_ports_0_cache_0_superPage; |
| reg [9:0] MmuPlugin_ports_0_cache_0_virtualAddress_0; |
| reg [9:0] MmuPlugin_ports_0_cache_0_virtualAddress_1; |
| reg [9:0] MmuPlugin_ports_0_cache_0_physicalAddress_0; |
| reg [9:0] MmuPlugin_ports_0_cache_0_physicalAddress_1; |
| reg MmuPlugin_ports_0_cache_0_allowRead; |
| reg MmuPlugin_ports_0_cache_0_allowWrite; |
| reg MmuPlugin_ports_0_cache_0_allowExecute; |
| reg MmuPlugin_ports_0_cache_0_allowUser; |
| reg MmuPlugin_ports_0_cache_1_valid; |
| reg MmuPlugin_ports_0_cache_1_exception; |
| reg MmuPlugin_ports_0_cache_1_superPage; |
| reg [9:0] MmuPlugin_ports_0_cache_1_virtualAddress_0; |
| reg [9:0] MmuPlugin_ports_0_cache_1_virtualAddress_1; |
| reg [9:0] MmuPlugin_ports_0_cache_1_physicalAddress_0; |
| reg [9:0] MmuPlugin_ports_0_cache_1_physicalAddress_1; |
| reg MmuPlugin_ports_0_cache_1_allowRead; |
| reg MmuPlugin_ports_0_cache_1_allowWrite; |
| reg MmuPlugin_ports_0_cache_1_allowExecute; |
| reg MmuPlugin_ports_0_cache_1_allowUser; |
| reg MmuPlugin_ports_0_cache_2_valid; |
| reg MmuPlugin_ports_0_cache_2_exception; |
| reg MmuPlugin_ports_0_cache_2_superPage; |
| reg [9:0] MmuPlugin_ports_0_cache_2_virtualAddress_0; |
| reg [9:0] MmuPlugin_ports_0_cache_2_virtualAddress_1; |
| reg [9:0] MmuPlugin_ports_0_cache_2_physicalAddress_0; |
| reg [9:0] MmuPlugin_ports_0_cache_2_physicalAddress_1; |
| reg MmuPlugin_ports_0_cache_2_allowRead; |
| reg MmuPlugin_ports_0_cache_2_allowWrite; |
| reg MmuPlugin_ports_0_cache_2_allowExecute; |
| reg MmuPlugin_ports_0_cache_2_allowUser; |
| reg MmuPlugin_ports_0_cache_3_valid; |
| reg MmuPlugin_ports_0_cache_3_exception; |
| reg MmuPlugin_ports_0_cache_3_superPage; |
| reg [9:0] MmuPlugin_ports_0_cache_3_virtualAddress_0; |
| reg [9:0] MmuPlugin_ports_0_cache_3_virtualAddress_1; |
| reg [9:0] MmuPlugin_ports_0_cache_3_physicalAddress_0; |
| reg [9:0] MmuPlugin_ports_0_cache_3_physicalAddress_1; |
| reg MmuPlugin_ports_0_cache_3_allowRead; |
| reg MmuPlugin_ports_0_cache_3_allowWrite; |
| reg MmuPlugin_ports_0_cache_3_allowExecute; |
| reg MmuPlugin_ports_0_cache_3_allowUser; |
| wire MmuPlugin_ports_0_dirty; |
| reg MmuPlugin_ports_0_requireMmuLockupCalc; |
| wire when_MmuPlugin_l125; |
| wire when_MmuPlugin_l126; |
| wire [3:0] MmuPlugin_ports_0_cacheHitsCalc; |
| wire MmuPlugin_ports_0_cacheHit; |
| wire _zz_MmuPlugin_ports_0_cacheLine_valid; |
| wire _zz_MmuPlugin_ports_0_cacheLine_valid_1; |
| wire _zz_MmuPlugin_ports_0_cacheLine_valid_2; |
| wire [1:0] _zz_MmuPlugin_ports_0_cacheLine_valid_3; |
| wire MmuPlugin_ports_0_cacheLine_valid; |
| wire MmuPlugin_ports_0_cacheLine_exception; |
| wire MmuPlugin_ports_0_cacheLine_superPage; |
| wire [9:0] MmuPlugin_ports_0_cacheLine_virtualAddress_0; |
| wire [9:0] MmuPlugin_ports_0_cacheLine_virtualAddress_1; |
| wire [9:0] MmuPlugin_ports_0_cacheLine_physicalAddress_0; |
| wire [9:0] MmuPlugin_ports_0_cacheLine_physicalAddress_1; |
| wire MmuPlugin_ports_0_cacheLine_allowRead; |
| wire MmuPlugin_ports_0_cacheLine_allowWrite; |
| wire MmuPlugin_ports_0_cacheLine_allowExecute; |
| wire MmuPlugin_ports_0_cacheLine_allowUser; |
| reg MmuPlugin_ports_0_entryToReplace_willIncrement; |
| wire MmuPlugin_ports_0_entryToReplace_willClear; |
| reg [1:0] MmuPlugin_ports_0_entryToReplace_valueNext; |
| reg [1:0] MmuPlugin_ports_0_entryToReplace_value; |
| wire MmuPlugin_ports_0_entryToReplace_willOverflowIfInc; |
| wire MmuPlugin_ports_0_entryToReplace_willOverflow; |
| reg MmuPlugin_ports_1_cache_0_valid; |
| reg MmuPlugin_ports_1_cache_0_exception; |
| reg MmuPlugin_ports_1_cache_0_superPage; |
| reg [9:0] MmuPlugin_ports_1_cache_0_virtualAddress_0; |
| reg [9:0] MmuPlugin_ports_1_cache_0_virtualAddress_1; |
| reg [9:0] MmuPlugin_ports_1_cache_0_physicalAddress_0; |
| reg [9:0] MmuPlugin_ports_1_cache_0_physicalAddress_1; |
| reg MmuPlugin_ports_1_cache_0_allowRead; |
| reg MmuPlugin_ports_1_cache_0_allowWrite; |
| reg MmuPlugin_ports_1_cache_0_allowExecute; |
| reg MmuPlugin_ports_1_cache_0_allowUser; |
| reg MmuPlugin_ports_1_cache_1_valid; |
| reg MmuPlugin_ports_1_cache_1_exception; |
| reg MmuPlugin_ports_1_cache_1_superPage; |
| reg [9:0] MmuPlugin_ports_1_cache_1_virtualAddress_0; |
| reg [9:0] MmuPlugin_ports_1_cache_1_virtualAddress_1; |
| reg [9:0] MmuPlugin_ports_1_cache_1_physicalAddress_0; |
| reg [9:0] MmuPlugin_ports_1_cache_1_physicalAddress_1; |
| reg MmuPlugin_ports_1_cache_1_allowRead; |
| reg MmuPlugin_ports_1_cache_1_allowWrite; |
| reg MmuPlugin_ports_1_cache_1_allowExecute; |
| reg MmuPlugin_ports_1_cache_1_allowUser; |
| reg MmuPlugin_ports_1_cache_2_valid; |
| reg MmuPlugin_ports_1_cache_2_exception; |
| reg MmuPlugin_ports_1_cache_2_superPage; |
| reg [9:0] MmuPlugin_ports_1_cache_2_virtualAddress_0; |
| reg [9:0] MmuPlugin_ports_1_cache_2_virtualAddress_1; |
| reg [9:0] MmuPlugin_ports_1_cache_2_physicalAddress_0; |
| reg [9:0] MmuPlugin_ports_1_cache_2_physicalAddress_1; |
| reg MmuPlugin_ports_1_cache_2_allowRead; |
| reg MmuPlugin_ports_1_cache_2_allowWrite; |
| reg MmuPlugin_ports_1_cache_2_allowExecute; |
| reg MmuPlugin_ports_1_cache_2_allowUser; |
| reg MmuPlugin_ports_1_cache_3_valid; |
| reg MmuPlugin_ports_1_cache_3_exception; |
| reg MmuPlugin_ports_1_cache_3_superPage; |
| reg [9:0] MmuPlugin_ports_1_cache_3_virtualAddress_0; |
| reg [9:0] MmuPlugin_ports_1_cache_3_virtualAddress_1; |
| reg [9:0] MmuPlugin_ports_1_cache_3_physicalAddress_0; |
| reg [9:0] MmuPlugin_ports_1_cache_3_physicalAddress_1; |
| reg MmuPlugin_ports_1_cache_3_allowRead; |
| reg MmuPlugin_ports_1_cache_3_allowWrite; |
| reg MmuPlugin_ports_1_cache_3_allowExecute; |
| reg MmuPlugin_ports_1_cache_3_allowUser; |
| wire MmuPlugin_ports_1_dirty; |
| reg MmuPlugin_ports_1_requireMmuLockupCalc; |
| wire when_MmuPlugin_l125_1; |
| wire when_MmuPlugin_l126_1; |
| wire when_MmuPlugin_l128; |
| wire [3:0] MmuPlugin_ports_1_cacheHitsCalc; |
| wire MmuPlugin_ports_1_cacheHit; |
| wire _zz_MmuPlugin_ports_1_cacheLine_valid; |
| wire _zz_MmuPlugin_ports_1_cacheLine_valid_1; |
| wire _zz_MmuPlugin_ports_1_cacheLine_valid_2; |
| wire [1:0] _zz_MmuPlugin_ports_1_cacheLine_valid_3; |
| wire MmuPlugin_ports_1_cacheLine_valid; |
| wire MmuPlugin_ports_1_cacheLine_exception; |
| wire MmuPlugin_ports_1_cacheLine_superPage; |
| wire [9:0] MmuPlugin_ports_1_cacheLine_virtualAddress_0; |
| wire [9:0] MmuPlugin_ports_1_cacheLine_virtualAddress_1; |
| wire [9:0] MmuPlugin_ports_1_cacheLine_physicalAddress_0; |
| wire [9:0] MmuPlugin_ports_1_cacheLine_physicalAddress_1; |
| wire MmuPlugin_ports_1_cacheLine_allowRead; |
| wire MmuPlugin_ports_1_cacheLine_allowWrite; |
| wire MmuPlugin_ports_1_cacheLine_allowExecute; |
| wire MmuPlugin_ports_1_cacheLine_allowUser; |
| reg MmuPlugin_ports_1_entryToReplace_willIncrement; |
| wire MmuPlugin_ports_1_entryToReplace_willClear; |
| reg [1:0] MmuPlugin_ports_1_entryToReplace_valueNext; |
| reg [1:0] MmuPlugin_ports_1_entryToReplace_value; |
| wire MmuPlugin_ports_1_entryToReplace_willOverflowIfInc; |
| wire MmuPlugin_ports_1_entryToReplace_willOverflow; |
| reg [2:0] MmuPlugin_shared_state_1; |
| reg [9:0] MmuPlugin_shared_vpn_0; |
| reg [9:0] MmuPlugin_shared_vpn_1; |
| reg [1:0] MmuPlugin_shared_portSortedOh; |
| reg MmuPlugin_shared_dBusRspStaged_valid; |
| reg [31:0] MmuPlugin_shared_dBusRspStaged_payload_data; |
| reg MmuPlugin_shared_dBusRspStaged_payload_error; |
| reg MmuPlugin_shared_dBusRspStaged_payload_redo; |
| wire MmuPlugin_shared_dBusRsp_pte_V; |
| wire MmuPlugin_shared_dBusRsp_pte_R; |
| wire MmuPlugin_shared_dBusRsp_pte_W; |
| wire MmuPlugin_shared_dBusRsp_pte_X; |
| wire MmuPlugin_shared_dBusRsp_pte_U; |
| wire MmuPlugin_shared_dBusRsp_pte_G; |
| wire MmuPlugin_shared_dBusRsp_pte_A; |
| wire MmuPlugin_shared_dBusRsp_pte_D; |
| wire [1:0] MmuPlugin_shared_dBusRsp_pte_RSW; |
| wire [9:0] MmuPlugin_shared_dBusRsp_pte_PPN0; |
| wire [11:0] MmuPlugin_shared_dBusRsp_pte_PPN1; |
| wire MmuPlugin_shared_dBusRsp_exception; |
| wire MmuPlugin_shared_dBusRsp_leaf; |
| wire when_MmuPlugin_l205; |
| reg MmuPlugin_shared_pteBuffer_V; |
| reg MmuPlugin_shared_pteBuffer_R; |
| reg MmuPlugin_shared_pteBuffer_W; |
| reg MmuPlugin_shared_pteBuffer_X; |
| reg MmuPlugin_shared_pteBuffer_U; |
| reg MmuPlugin_shared_pteBuffer_G; |
| reg MmuPlugin_shared_pteBuffer_A; |
| reg MmuPlugin_shared_pteBuffer_D; |
| reg [1:0] MmuPlugin_shared_pteBuffer_RSW; |
| reg [9:0] MmuPlugin_shared_pteBuffer_PPN0; |
| reg [11:0] MmuPlugin_shared_pteBuffer_PPN1; |
| wire [1:0] _zz_MmuPlugin_shared_refills; |
| reg [1:0] _zz_MmuPlugin_shared_refills_1; |
| wire [1:0] MmuPlugin_shared_refills; |
| wire [1:0] _zz_MmuPlugin_shared_refills_2; |
| reg [1:0] _zz_MmuPlugin_shared_refills_3; |
| wire when_MmuPlugin_l217; |
| wire [31:0] _zz_MmuPlugin_shared_vpn_0; |
| wire when_MmuPlugin_l243; |
| wire when_MmuPlugin_l272; |
| wire when_MmuPlugin_l274; |
| wire when_MmuPlugin_l280; |
| wire when_MmuPlugin_l280_1; |
| wire when_MmuPlugin_l280_2; |
| wire when_MmuPlugin_l280_3; |
| wire when_MmuPlugin_l274_1; |
| wire when_MmuPlugin_l280_4; |
| wire when_MmuPlugin_l280_5; |
| wire when_MmuPlugin_l280_6; |
| wire when_MmuPlugin_l280_7; |
| wire when_MmuPlugin_l304; |
| wire when_Pipeline_l124; |
| reg [31:0] decode_to_execute_PC; |
| wire when_Pipeline_l124_1; |
| reg [31:0] execute_to_memory_PC; |
| wire when_Pipeline_l124_2; |
| reg [31:0] memory_to_writeBack_PC; |
| wire when_Pipeline_l124_3; |
| reg [31:0] decode_to_execute_INSTRUCTION; |
| wire when_Pipeline_l124_4; |
| reg [31:0] execute_to_memory_INSTRUCTION; |
| wire when_Pipeline_l124_5; |
| reg [31:0] memory_to_writeBack_INSTRUCTION; |
| wire when_Pipeline_l124_6; |
| reg [31:0] decode_to_execute_FORMAL_PC_NEXT; |
| wire when_Pipeline_l124_7; |
| reg [31:0] execute_to_memory_FORMAL_PC_NEXT; |
| wire when_Pipeline_l124_8; |
| reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; |
| wire when_Pipeline_l124_9; |
| reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; |
| wire when_Pipeline_l124_10; |
| reg decode_to_execute_SRC_USE_SUB_LESS; |
| wire when_Pipeline_l124_11; |
| reg decode_to_execute_MEMORY_ENABLE; |
| wire when_Pipeline_l124_12; |
| reg execute_to_memory_MEMORY_ENABLE; |
| wire when_Pipeline_l124_13; |
| reg memory_to_writeBack_MEMORY_ENABLE; |
| wire when_Pipeline_l124_14; |
| reg [1:0] decode_to_execute_ALU_CTRL; |
| wire when_Pipeline_l124_15; |
| reg decode_to_execute_REGFILE_WRITE_VALID; |
| wire when_Pipeline_l124_16; |
| reg execute_to_memory_REGFILE_WRITE_VALID; |
| wire when_Pipeline_l124_17; |
| reg memory_to_writeBack_REGFILE_WRITE_VALID; |
| wire when_Pipeline_l124_18; |
| reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; |
| wire when_Pipeline_l124_19; |
| reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; |
| wire when_Pipeline_l124_20; |
| reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; |
| wire when_Pipeline_l124_21; |
| reg decode_to_execute_MEMORY_WR; |
| wire when_Pipeline_l124_22; |
| reg execute_to_memory_MEMORY_WR; |
| wire when_Pipeline_l124_23; |
| reg memory_to_writeBack_MEMORY_WR; |
| wire when_Pipeline_l124_24; |
| reg decode_to_execute_MEMORY_MANAGMENT; |
| wire when_Pipeline_l124_25; |
| reg decode_to_execute_SRC_LESS_UNSIGNED; |
| wire when_Pipeline_l124_26; |
| reg [1:0] decode_to_execute_ALU_BITWISE_CTRL; |
| wire when_Pipeline_l124_27; |
| reg [1:0] decode_to_execute_SHIFT_CTRL; |
| wire when_Pipeline_l124_28; |
| reg [1:0] execute_to_memory_SHIFT_CTRL; |
| wire when_Pipeline_l124_29; |
| reg decode_to_execute_IS_MUL; |
| wire when_Pipeline_l124_30; |
| reg execute_to_memory_IS_MUL; |
| wire when_Pipeline_l124_31; |
| reg memory_to_writeBack_IS_MUL; |
| wire when_Pipeline_l124_32; |
| reg decode_to_execute_IS_DIV; |
| wire when_Pipeline_l124_33; |
| reg execute_to_memory_IS_DIV; |
| wire when_Pipeline_l124_34; |
| reg decode_to_execute_IS_RS1_SIGNED; |
| wire when_Pipeline_l124_35; |
| reg decode_to_execute_IS_RS2_SIGNED; |
| wire when_Pipeline_l124_36; |
| reg decode_to_execute_IS_CSR; |
| wire when_Pipeline_l124_37; |
| reg [0:0] decode_to_execute_ENV_CTRL; |
| wire when_Pipeline_l124_38; |
| reg [0:0] execute_to_memory_ENV_CTRL; |
| wire when_Pipeline_l124_39; |
| reg [0:0] memory_to_writeBack_ENV_CTRL; |
| wire when_Pipeline_l124_40; |
| reg [1:0] decode_to_execute_BRANCH_CTRL; |
| wire when_Pipeline_l124_41; |
| reg decode_to_execute_IS_SFENCE_VMA2; |
| wire when_Pipeline_l124_42; |
| reg [31:0] decode_to_execute_RS1; |
| wire when_Pipeline_l124_43; |
| reg [31:0] decode_to_execute_RS2; |
| wire when_Pipeline_l124_44; |
| reg decode_to_execute_SRC2_FORCE_ZERO; |
| wire when_Pipeline_l124_45; |
| reg [31:0] decode_to_execute_SRC1; |
| wire when_Pipeline_l124_46; |
| reg [31:0] decode_to_execute_SRC2; |
| wire when_Pipeline_l124_47; |
| reg decode_to_execute_DO_EBREAK; |
| wire when_Pipeline_l124_48; |
| reg decode_to_execute_CSR_WRITE_OPCODE; |
| wire when_Pipeline_l124_49; |
| reg decode_to_execute_CSR_READ_OPCODE; |
| wire when_Pipeline_l124_50; |
| reg [31:0] execute_to_memory_MEMORY_STORE_DATA_RF; |
| wire when_Pipeline_l124_51; |
| reg [31:0] memory_to_writeBack_MEMORY_STORE_DATA_RF; |
| wire when_Pipeline_l124_52; |
| reg execute_to_memory_IS_DBUS_SHARING; |
| wire when_Pipeline_l124_53; |
| reg memory_to_writeBack_IS_DBUS_SHARING; |
| wire when_Pipeline_l124_54; |
| reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; |
| wire when_Pipeline_l124_55; |
| reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; |
| wire when_Pipeline_l124_56; |
| reg [31:0] execute_to_memory_SHIFT_RIGHT; |
| wire when_Pipeline_l124_57; |
| reg [31:0] execute_to_memory_MUL_LL; |
| wire when_Pipeline_l124_58; |
| reg [33:0] execute_to_memory_MUL_LH; |
| wire when_Pipeline_l124_59; |
| reg [33:0] execute_to_memory_MUL_HL; |
| wire when_Pipeline_l124_60; |
| reg [33:0] execute_to_memory_MUL_HH; |
| wire when_Pipeline_l124_61; |
| reg [33:0] memory_to_writeBack_MUL_HH; |
| wire when_Pipeline_l124_62; |
| reg [51:0] memory_to_writeBack_MUL_LOW; |
| wire when_Pipeline_l151; |
| wire when_Pipeline_l154; |
| wire when_Pipeline_l151_1; |
| wire when_Pipeline_l154_1; |
| wire when_Pipeline_l151_2; |
| wire when_Pipeline_l154_2; |
| reg [2:0] switch_Fetcher_l362; |
| wire when_Fetcher_l378; |
| wire when_CsrPlugin_l1264; |
| reg execute_CsrPlugin_csr_768; |
| wire when_CsrPlugin_l1264_1; |
| reg execute_CsrPlugin_csr_836; |
| wire when_CsrPlugin_l1264_2; |
| reg execute_CsrPlugin_csr_772; |
| wire when_CsrPlugin_l1264_3; |
| reg execute_CsrPlugin_csr_773; |
| wire when_CsrPlugin_l1264_4; |
| reg execute_CsrPlugin_csr_833; |
| wire when_CsrPlugin_l1264_5; |
| reg execute_CsrPlugin_csr_834; |
| wire when_CsrPlugin_l1264_6; |
| reg execute_CsrPlugin_csr_835; |
| wire when_CsrPlugin_l1264_7; |
| reg execute_CsrPlugin_csr_2816; |
| wire when_CsrPlugin_l1264_8; |
| reg execute_CsrPlugin_csr_2944; |
| wire when_CsrPlugin_l1264_9; |
| reg execute_CsrPlugin_csr_3072; |
| wire when_CsrPlugin_l1264_10; |
| reg execute_CsrPlugin_csr_3200; |
| wire when_CsrPlugin_l1264_11; |
| reg execute_CsrPlugin_csr_256; |
| wire when_CsrPlugin_l1264_12; |
| reg execute_CsrPlugin_csr_384; |
| reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit; |
| reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1; |
| reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2; |
| reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3; |
| reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4; |
| reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5; |
| reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6; |
| reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7; |
| reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_8; |
| reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_9; |
| reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_10; |
| reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_11; |
| reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_12; |
| wire when_CsrPlugin_l1297; |
| wire when_CsrPlugin_l1302; |
| reg [2:0] _zz_iBusWishbone_ADR; |
| wire when_InstructionCache_l239; |
| reg _zz_iBus_rsp_valid; |
| reg [31:0] iBusWishbone_DAT_MISO_regNext; |
| reg [2:0] _zz_dBus_cmd_ready; |
| wire _zz_dBus_cmd_ready_1; |
| wire _zz_dBus_cmd_ready_2; |
| wire _zz_dBus_cmd_ready_3; |
| wire _zz_dBus_cmd_ready_4; |
| wire _zz_dBus_cmd_ready_5; |
| reg _zz_dBus_rsp_valid; |
| reg [31:0] dBusWishbone_DAT_MISO_regNext; |
| wire debug_bus_cmd_fire; |
| reg debug_bus_cmd_fire_regNext; |
| `ifndef SYNTHESIS |
| reg [31:0] decode_BRANCH_CTRL_string; |
| reg [31:0] _zz_decode_BRANCH_CTRL_string; |
| reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string; |
| reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string; |
| reg [31:0] _zz_memory_to_writeBack_ENV_CTRL_string; |
| reg [31:0] _zz_memory_to_writeBack_ENV_CTRL_1_string; |
| reg [31:0] _zz_execute_to_memory_ENV_CTRL_string; |
| reg [31:0] _zz_execute_to_memory_ENV_CTRL_1_string; |
| reg [31:0] decode_ENV_CTRL_string; |
| reg [31:0] _zz_decode_ENV_CTRL_string; |
| reg [31:0] _zz_decode_to_execute_ENV_CTRL_string; |
| reg [31:0] _zz_decode_to_execute_ENV_CTRL_1_string; |
| reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_string; |
| reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_1_string; |
| reg [71:0] decode_SHIFT_CTRL_string; |
| reg [71:0] _zz_decode_SHIFT_CTRL_string; |
| reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string; |
| reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string; |
| reg [39:0] decode_ALU_BITWISE_CTRL_string; |
| reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string; |
| reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string; |
| reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string; |
| reg [63:0] decode_ALU_CTRL_string; |
| reg [63:0] _zz_decode_ALU_CTRL_string; |
| reg [63:0] _zz_decode_to_execute_ALU_CTRL_string; |
| reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string; |
| reg [31:0] execute_BRANCH_CTRL_string; |
| reg [31:0] _zz_execute_BRANCH_CTRL_string; |
| reg [31:0] memory_ENV_CTRL_string; |
| reg [31:0] _zz_memory_ENV_CTRL_string; |
| reg [31:0] execute_ENV_CTRL_string; |
| reg [31:0] _zz_execute_ENV_CTRL_string; |
| reg [31:0] writeBack_ENV_CTRL_string; |
| reg [31:0] _zz_writeBack_ENV_CTRL_string; |
| reg [71:0] memory_SHIFT_CTRL_string; |
| reg [71:0] _zz_memory_SHIFT_CTRL_string; |
| reg [71:0] execute_SHIFT_CTRL_string; |
| reg [71:0] _zz_execute_SHIFT_CTRL_string; |
| reg [23:0] decode_SRC2_CTRL_string; |
| reg [23:0] _zz_decode_SRC2_CTRL_string; |
| reg [95:0] decode_SRC1_CTRL_string; |
| reg [95:0] _zz_decode_SRC1_CTRL_string; |
| reg [63:0] execute_ALU_CTRL_string; |
| reg [63:0] _zz_execute_ALU_CTRL_string; |
| reg [39:0] execute_ALU_BITWISE_CTRL_string; |
| reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string; |
| reg [31:0] _zz_decode_BRANCH_CTRL_1_string; |
| reg [31:0] _zz_decode_ENV_CTRL_1_string; |
| reg [71:0] _zz_decode_SHIFT_CTRL_1_string; |
| reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string; |
| reg [23:0] _zz_decode_SRC2_CTRL_1_string; |
| reg [63:0] _zz_decode_ALU_CTRL_1_string; |
| reg [95:0] _zz_decode_SRC1_CTRL_1_string; |
| reg [95:0] _zz_decode_SRC1_CTRL_2_string; |
| reg [63:0] _zz_decode_ALU_CTRL_2_string; |
| reg [23:0] _zz_decode_SRC2_CTRL_2_string; |
| reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string; |
| reg [71:0] _zz_decode_SHIFT_CTRL_2_string; |
| reg [31:0] _zz_decode_ENV_CTRL_2_string; |
| reg [31:0] _zz_decode_BRANCH_CTRL_2_string; |
| reg [47:0] MmuPlugin_shared_state_1_string; |
| reg [63:0] decode_to_execute_ALU_CTRL_string; |
| reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; |
| reg [71:0] decode_to_execute_SHIFT_CTRL_string; |
| reg [71:0] execute_to_memory_SHIFT_CTRL_string; |
| reg [31:0] decode_to_execute_ENV_CTRL_string; |
| reg [31:0] execute_to_memory_ENV_CTRL_string; |
| reg [31:0] memory_to_writeBack_ENV_CTRL_string; |
| reg [31:0] decode_to_execute_BRANCH_CTRL_string; |
| `endif |
| |
| reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; |
| |
| assign _zz_when = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); |
| assign _zz_memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW_1) + $signed(_zz_memory_MUL_LOW_5)); |
| assign _zz_memory_MUL_LOW_1 = ($signed(_zz_memory_MUL_LOW_2) + $signed(_zz_memory_MUL_LOW_3)); |
| assign _zz_memory_MUL_LOW_2 = 52'h0; |
| assign _zz_memory_MUL_LOW_4 = {1'b0,memory_MUL_LL}; |
| assign _zz_memory_MUL_LOW_3 = {{19{_zz_memory_MUL_LOW_4[32]}}, _zz_memory_MUL_LOW_4}; |
| assign _zz_memory_MUL_LOW_6 = ({16'd0,memory_MUL_LH} <<< 16); |
| assign _zz_memory_MUL_LOW_5 = {{2{_zz_memory_MUL_LOW_6[49]}}, _zz_memory_MUL_LOW_6}; |
| assign _zz_memory_MUL_LOW_8 = ({16'd0,memory_MUL_HL} <<< 16); |
| assign _zz_memory_MUL_LOW_7 = {{2{_zz_memory_MUL_LOW_8[49]}}, _zz_memory_MUL_LOW_8}; |
| assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude); |
| assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0]; |
| assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == ShiftCtrlEnum_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; |
| assign _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload - 3'b001); |
| assign _zz_IBusCachedPlugin_fetchPc_pc_1 = {IBusCachedPlugin_fetchPc_inc,2'b00}; |
| assign _zz_IBusCachedPlugin_fetchPc_pc = {29'd0, _zz_IBusCachedPlugin_fetchPc_pc_1}; |
| assign _zz_DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); |
| assign _zz_DBusCachedPlugin_exceptionBus_payload_code_1 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); |
| assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS; |
| assign _zz__zz_decode_SRC1_1 = 3'b100; |
| assign _zz__zz_decode_SRC1_1_1 = decode_INSTRUCTION[19 : 15]; |
| assign _zz__zz_decode_SRC2_4 = {decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}; |
| assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4)); |
| assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3)); |
| assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1; |
| assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); |
| assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6); |
| assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001; |
| assign _zz_execute_SrcPlugin_addSub_6 = 32'h0; |
| assign _zz_writeBack_MulPlugin_result = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; |
| assign _zz_writeBack_MulPlugin_result_1 = ({32'd0,writeBack_MUL_HH} <<< 32); |
| assign _zz__zz_decode_RS2_2 = writeBack_MUL_LOW[31 : 0]; |
| assign _zz__zz_decode_RS2_2_1 = writeBack_MulPlugin_result[63 : 32]; |
| assign _zz_memory_DivPlugin_div_counter_valueNext_1 = memory_DivPlugin_div_counter_willIncrement; |
| assign _zz_memory_DivPlugin_div_counter_valueNext = {5'd0, _zz_memory_DivPlugin_div_counter_valueNext_1}; |
| assign _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator = {1'd0, memory_DivPlugin_rs2}; |
| assign _zz_memory_DivPlugin_div_stage_0_outRemainder = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; |
| assign _zz_memory_DivPlugin_div_stage_0_outRemainder_1 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; |
| assign _zz_memory_DivPlugin_div_stage_0_outNumerator = {_zz_memory_DivPlugin_div_stage_0_remainderShifted,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; |
| assign _zz_memory_DivPlugin_div_result_1 = _zz_memory_DivPlugin_div_result_2; |
| assign _zz_memory_DivPlugin_div_result_2 = _zz_memory_DivPlugin_div_result_3; |
| assign _zz_memory_DivPlugin_div_result_3 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_memory_DivPlugin_div_result) : _zz_memory_DivPlugin_div_result)} + _zz_memory_DivPlugin_div_result_4); |
| assign _zz_memory_DivPlugin_div_result_5 = memory_DivPlugin_div_needRevert; |
| assign _zz_memory_DivPlugin_div_result_4 = {32'd0, _zz_memory_DivPlugin_div_result_5}; |
| assign _zz_memory_DivPlugin_rs1_3 = _zz_memory_DivPlugin_rs1; |
| assign _zz_memory_DivPlugin_rs1_2 = {32'd0, _zz_memory_DivPlugin_rs1_3}; |
| assign _zz_memory_DivPlugin_rs2_2 = _zz_memory_DivPlugin_rs2; |
| assign _zz_memory_DivPlugin_rs2_1 = {31'd0, _zz_memory_DivPlugin_rs2_2}; |
| assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1)); |
| assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code - 2'b01); |
| assign _zz_CsrPlugin_jumpInterface_payload = (CsrPlugin_xtvec_base + _zz_CsrPlugin_jumpInterface_payload_1); |
| assign _zz_CsrPlugin_jumpInterface_payload_1 = {26'd0, CsrPlugin_trapCause}; |
| assign _zz__zz_execute_BranchPlugin_branch_src2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; |
| assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; |
| assign _zz_MmuPlugin_ports_0_entryToReplace_valueNext_1 = MmuPlugin_ports_0_entryToReplace_willIncrement; |
| assign _zz_MmuPlugin_ports_0_entryToReplace_valueNext = {1'd0, _zz_MmuPlugin_ports_0_entryToReplace_valueNext_1}; |
| assign _zz_MmuPlugin_ports_1_entryToReplace_valueNext_1 = MmuPlugin_ports_1_entryToReplace_willIncrement; |
| assign _zz_MmuPlugin_ports_1_entryToReplace_valueNext = {1'd0, _zz_MmuPlugin_ports_1_entryToReplace_valueNext_1}; |
| assign _zz__zz_MmuPlugin_shared_refills_2 = (_zz_MmuPlugin_shared_refills_1 - 2'b01); |
| assign _zz_iBusWishbone_ADR_1 = (iBus_cmd_payload_address >>> 5); |
| assign _zz_decode_RegFilePlugin_rs1Data = 1'b1; |
| assign _zz_decode_RegFilePlugin_rs2Data = 1'b1; |
| assign _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = {_zz_IBusCachedPlugin_jump_pcLoad_payload_3,_zz_IBusCachedPlugin_jump_pcLoad_payload_2}; |
| assign _zz_writeBack_DBusCachedPlugin_rspShifted_1 = dataCache_1_io_cpu_writeBack_address[1 : 0]; |
| assign _zz_writeBack_DBusCachedPlugin_rspShifted_3 = dataCache_1_io_cpu_writeBack_address[1 : 1]; |
| assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000107f; |
| assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000207f); |
| assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00002073; |
| assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); |
| assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); |
| assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}}; |
| assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000505f; |
| assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'h0000707b); |
| assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000063; |
| assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); |
| assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); |
| assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_12) == 32'h00001013),{(_zz_decode_LEGAL_INSTRUCTION_13 == _zz_decode_LEGAL_INSTRUCTION_14),{_zz_decode_LEGAL_INSTRUCTION_15,{_zz_decode_LEGAL_INSTRUCTION_16,_zz_decode_LEGAL_INSTRUCTION_17}}}}}}; |
| assign _zz_decode_LEGAL_INSTRUCTION_12 = 32'hfc00307f; |
| assign _zz_decode_LEGAL_INSTRUCTION_13 = (decode_INSTRUCTION & 32'hbe00707f); |
| assign _zz_decode_LEGAL_INSTRUCTION_14 = 32'h00005033; |
| assign _zz_decode_LEGAL_INSTRUCTION_15 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); |
| assign _zz_decode_LEGAL_INSTRUCTION_16 = ((decode_INSTRUCTION & 32'hfe007fff) == 32'h12000073); |
| assign _zz_decode_LEGAL_INSTRUCTION_17 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00100073)}; |
| assign _zz__zz_decode_IS_SFENCE_VMA2 = (decode_INSTRUCTION & 32'h0000001c); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_1 = 32'h00000004; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_2 = (decode_INSTRUCTION & 32'h00000058); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_3 = 32'h00000040; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_4 = ((decode_INSTRUCTION & 32'h02103050) == 32'h00000050); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_5 = {((decode_INSTRUCTION & _zz__zz_decode_IS_SFENCE_VMA2_6) == 32'h00001050),((decode_INSTRUCTION & _zz__zz_decode_IS_SFENCE_VMA2_7) == 32'h00002050)}; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_8 = (|((decode_INSTRUCTION & _zz__zz_decode_IS_SFENCE_VMA2_9) == 32'h00000050)); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_10 = (|_zz_decode_IS_SFENCE_VMA2_5); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_11 = {(|_zz_decode_IS_SFENCE_VMA2_5),{(|_zz__zz_decode_IS_SFENCE_VMA2_12),{_zz__zz_decode_IS_SFENCE_VMA2_13,{_zz__zz_decode_IS_SFENCE_VMA2_14,_zz__zz_decode_IS_SFENCE_VMA2_19}}}}; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_6 = 32'h00001050; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_7 = 32'h00002050; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_9 = 32'h10003050; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_12 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_13 = (|((decode_INSTRUCTION & 32'h02004074) == 32'h02000030)); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_14 = (|{(_zz__zz_decode_IS_SFENCE_VMA2_15 == _zz__zz_decode_IS_SFENCE_VMA2_16),(_zz__zz_decode_IS_SFENCE_VMA2_17 == _zz__zz_decode_IS_SFENCE_VMA2_18)}); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_19 = {(|{_zz__zz_decode_IS_SFENCE_VMA2_20,{_zz__zz_decode_IS_SFENCE_VMA2_21,_zz__zz_decode_IS_SFENCE_VMA2_23}}),{(|_zz__zz_decode_IS_SFENCE_VMA2_25),{(|_zz__zz_decode_IS_SFENCE_VMA2_26),{_zz__zz_decode_IS_SFENCE_VMA2_28,{_zz__zz_decode_IS_SFENCE_VMA2_31,_zz__zz_decode_IS_SFENCE_VMA2_34}}}}}; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_15 = (decode_INSTRUCTION & 32'h00007034); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_16 = 32'h00005010; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_17 = (decode_INSTRUCTION & 32'h02007064); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_18 = 32'h00005020; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_20 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_21 = ((decode_INSTRUCTION & _zz__zz_decode_IS_SFENCE_VMA2_22) == 32'h00001010); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_23 = ((decode_INSTRUCTION & _zz__zz_decode_IS_SFENCE_VMA2_24) == 32'h00001010); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_25 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_26 = ((decode_INSTRUCTION & _zz__zz_decode_IS_SFENCE_VMA2_27) == 32'h00001000); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_28 = (|(_zz__zz_decode_IS_SFENCE_VMA2_29 == _zz__zz_decode_IS_SFENCE_VMA2_30)); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_31 = (|{_zz__zz_decode_IS_SFENCE_VMA2_32,_zz__zz_decode_IS_SFENCE_VMA2_33}); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_34 = {(|_zz__zz_decode_IS_SFENCE_VMA2_35),{_zz__zz_decode_IS_SFENCE_VMA2_36,{_zz__zz_decode_IS_SFENCE_VMA2_41,_zz__zz_decode_IS_SFENCE_VMA2_46}}}; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_22 = 32'h00007034; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_24 = 32'h02007054; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_27 = 32'h00001000; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_29 = (decode_INSTRUCTION & 32'h00003000); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_30 = 32'h00002000; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_32 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_33 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_35 = ((decode_INSTRUCTION & 32'h00004048) == 32'h00004008); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_36 = (|{(_zz__zz_decode_IS_SFENCE_VMA2_37 == _zz__zz_decode_IS_SFENCE_VMA2_38),(_zz__zz_decode_IS_SFENCE_VMA2_39 == _zz__zz_decode_IS_SFENCE_VMA2_40)}); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_41 = (|{_zz__zz_decode_IS_SFENCE_VMA2_42,{_zz__zz_decode_IS_SFENCE_VMA2_43,_zz__zz_decode_IS_SFENCE_VMA2_44}}); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_46 = {(|_zz__zz_decode_IS_SFENCE_VMA2_47),{(|_zz__zz_decode_IS_SFENCE_VMA2_48),{_zz__zz_decode_IS_SFENCE_VMA2_59,{_zz__zz_decode_IS_SFENCE_VMA2_72,_zz__zz_decode_IS_SFENCE_VMA2_86}}}}; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_37 = (decode_INSTRUCTION & 32'h00000034); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_38 = 32'h00000020; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_39 = (decode_INSTRUCTION & 32'h00000064); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_40 = 32'h00000020; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_42 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000040); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_43 = _zz_decode_IS_SFENCE_VMA2_2; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_44 = ((decode_INSTRUCTION & _zz__zz_decode_IS_SFENCE_VMA2_45) == 32'h00000040); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_47 = ((decode_INSTRUCTION & 32'h00000020) == 32'h00000020); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_48 = {(_zz__zz_decode_IS_SFENCE_VMA2_49 == _zz__zz_decode_IS_SFENCE_VMA2_50),{_zz_decode_IS_SFENCE_VMA2_3,{_zz__zz_decode_IS_SFENCE_VMA2_51,_zz__zz_decode_IS_SFENCE_VMA2_54}}}; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_59 = (|{_zz_decode_IS_SFENCE_VMA2_3,{_zz__zz_decode_IS_SFENCE_VMA2_60,_zz__zz_decode_IS_SFENCE_VMA2_63}}); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_72 = (|{_zz__zz_decode_IS_SFENCE_VMA2_73,_zz__zz_decode_IS_SFENCE_VMA2_74}); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_86 = {(|_zz__zz_decode_IS_SFENCE_VMA2_87),{_zz__zz_decode_IS_SFENCE_VMA2_90,{_zz__zz_decode_IS_SFENCE_VMA2_95,_zz__zz_decode_IS_SFENCE_VMA2_99}}}; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_45 = 32'h02103040; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_49 = (decode_INSTRUCTION & 32'h00000040); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_50 = 32'h00000040; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_51 = (_zz__zz_decode_IS_SFENCE_VMA2_52 == _zz__zz_decode_IS_SFENCE_VMA2_53); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_54 = {_zz__zz_decode_IS_SFENCE_VMA2_55,_zz__zz_decode_IS_SFENCE_VMA2_57}; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_60 = (_zz__zz_decode_IS_SFENCE_VMA2_61 == _zz__zz_decode_IS_SFENCE_VMA2_62); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_63 = {_zz__zz_decode_IS_SFENCE_VMA2_64,{_zz__zz_decode_IS_SFENCE_VMA2_66,_zz__zz_decode_IS_SFENCE_VMA2_69}}; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_73 = _zz_decode_IS_SFENCE_VMA2_4; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_74 = {_zz__zz_decode_IS_SFENCE_VMA2_75,{_zz__zz_decode_IS_SFENCE_VMA2_77,_zz__zz_decode_IS_SFENCE_VMA2_80}}; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_87 = {_zz_decode_IS_SFENCE_VMA2_3,_zz__zz_decode_IS_SFENCE_VMA2_88}; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_90 = (|{_zz__zz_decode_IS_SFENCE_VMA2_91,_zz__zz_decode_IS_SFENCE_VMA2_92}); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_95 = (|_zz__zz_decode_IS_SFENCE_VMA2_96); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_99 = {_zz__zz_decode_IS_SFENCE_VMA2_100,{_zz__zz_decode_IS_SFENCE_VMA2_102,_zz__zz_decode_IS_SFENCE_VMA2_110}}; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_52 = (decode_INSTRUCTION & 32'h00004020); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_53 = 32'h00004020; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_55 = ((decode_INSTRUCTION & _zz__zz_decode_IS_SFENCE_VMA2_56) == 32'h00000010); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_57 = ((decode_INSTRUCTION & _zz__zz_decode_IS_SFENCE_VMA2_58) == 32'h00000020); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_61 = (decode_INSTRUCTION & 32'h00002030); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_62 = 32'h00002010; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_64 = ((decode_INSTRUCTION & _zz__zz_decode_IS_SFENCE_VMA2_65) == 32'h00000010); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_66 = (_zz__zz_decode_IS_SFENCE_VMA2_67 == _zz__zz_decode_IS_SFENCE_VMA2_68); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_69 = (_zz__zz_decode_IS_SFENCE_VMA2_70 == _zz__zz_decode_IS_SFENCE_VMA2_71); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_75 = ((decode_INSTRUCTION & _zz__zz_decode_IS_SFENCE_VMA2_76) == 32'h00001010); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_77 = (_zz__zz_decode_IS_SFENCE_VMA2_78 == _zz__zz_decode_IS_SFENCE_VMA2_79); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_80 = {_zz__zz_decode_IS_SFENCE_VMA2_81,{_zz__zz_decode_IS_SFENCE_VMA2_82,_zz__zz_decode_IS_SFENCE_VMA2_84}}; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_88 = ((decode_INSTRUCTION & _zz__zz_decode_IS_SFENCE_VMA2_89) == 32'h00000020); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_91 = _zz_decode_IS_SFENCE_VMA2_3; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_92 = (_zz__zz_decode_IS_SFENCE_VMA2_93 == _zz__zz_decode_IS_SFENCE_VMA2_94); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_96 = (_zz__zz_decode_IS_SFENCE_VMA2_97 == _zz__zz_decode_IS_SFENCE_VMA2_98); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_100 = (|_zz__zz_decode_IS_SFENCE_VMA2_101); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_102 = (|_zz__zz_decode_IS_SFENCE_VMA2_103); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_110 = {_zz__zz_decode_IS_SFENCE_VMA2_111,{_zz__zz_decode_IS_SFENCE_VMA2_114,_zz__zz_decode_IS_SFENCE_VMA2_122}}; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_56 = 32'h00000030; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_58 = 32'h02000020; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_65 = 32'h00001030; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_67 = (decode_INSTRUCTION & 32'h02002060); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_68 = 32'h00002020; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_70 = (decode_INSTRUCTION & 32'h02003020); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_71 = 32'h00000020; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_76 = 32'h00001010; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_78 = (decode_INSTRUCTION & 32'h00002010); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_79 = 32'h00002010; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_81 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000010); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_82 = ((decode_INSTRUCTION & _zz__zz_decode_IS_SFENCE_VMA2_83) == 32'h00000004); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_84 = ((decode_INSTRUCTION & _zz__zz_decode_IS_SFENCE_VMA2_85) == 32'h0); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_89 = 32'h00000070; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_93 = (decode_INSTRUCTION & 32'h00000020); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_94 = 32'h0; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_97 = (decode_INSTRUCTION & 32'h00004014); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_98 = 32'h00004010; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_101 = ((decode_INSTRUCTION & 32'h00006014) == 32'h00002010); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_103 = {(_zz__zz_decode_IS_SFENCE_VMA2_104 == _zz__zz_decode_IS_SFENCE_VMA2_105),{_zz_decode_IS_SFENCE_VMA2_2,{_zz__zz_decode_IS_SFENCE_VMA2_106,_zz__zz_decode_IS_SFENCE_VMA2_108}}}; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_111 = (|(_zz__zz_decode_IS_SFENCE_VMA2_112 == _zz__zz_decode_IS_SFENCE_VMA2_113)); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_114 = (|{_zz__zz_decode_IS_SFENCE_VMA2_115,_zz__zz_decode_IS_SFENCE_VMA2_117}); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_122 = {(|_zz__zz_decode_IS_SFENCE_VMA2_123),{_zz__zz_decode_IS_SFENCE_VMA2_126,_zz__zz_decode_IS_SFENCE_VMA2_128}}; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_83 = 32'h0000000c; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_85 = 32'h00000028; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_104 = (decode_INSTRUCTION & 32'h00000044); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_105 = 32'h0; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_106 = ((decode_INSTRUCTION & _zz__zz_decode_IS_SFENCE_VMA2_107) == 32'h00002000); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_108 = ((decode_INSTRUCTION & _zz__zz_decode_IS_SFENCE_VMA2_109) == 32'h00001000); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_112 = (decode_INSTRUCTION & 32'h00000058); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_113 = 32'h0; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_115 = ((decode_INSTRUCTION & _zz__zz_decode_IS_SFENCE_VMA2_116) == 32'h00000040); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_117 = {(_zz__zz_decode_IS_SFENCE_VMA2_118 == _zz__zz_decode_IS_SFENCE_VMA2_119),(_zz__zz_decode_IS_SFENCE_VMA2_120 == _zz__zz_decode_IS_SFENCE_VMA2_121)}; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_123 = {(_zz__zz_decode_IS_SFENCE_VMA2_124 == _zz__zz_decode_IS_SFENCE_VMA2_125),_zz_decode_IS_SFENCE_VMA2_1}; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_126 = (|{_zz__zz_decode_IS_SFENCE_VMA2_127,_zz_decode_IS_SFENCE_VMA2_1}); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_128 = (|(_zz__zz_decode_IS_SFENCE_VMA2_129 == _zz__zz_decode_IS_SFENCE_VMA2_130)); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_107 = 32'h00006004; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_109 = 32'h00005004; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_116 = 32'h00000044; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_118 = (decode_INSTRUCTION & 32'h00002014); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_119 = 32'h00002010; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_120 = (decode_INSTRUCTION & 32'h40000034); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_121 = 32'h40000030; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_124 = (decode_INSTRUCTION & 32'h00000014); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_125 = 32'h00000004; |
| assign _zz__zz_decode_IS_SFENCE_VMA2_127 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_129 = (decode_INSTRUCTION & 32'h00005048); |
| assign _zz__zz_decode_IS_SFENCE_VMA2_130 = 32'h00001008; |
| assign _zz_MmuPlugin_ports_0_cacheHitsCalc = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22]; |
| assign _zz_MmuPlugin_ports_0_cacheHitsCalc_1 = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]; |
| assign _zz_MmuPlugin_ports_0_cacheHitsCalc_2 = (MmuPlugin_ports_0_cache_1_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22]); |
| assign _zz_MmuPlugin_ports_0_cacheHitsCalc_3 = (MmuPlugin_ports_0_cache_1_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]); |
| assign _zz_MmuPlugin_ports_0_cacheHitsCalc_4 = (MmuPlugin_ports_0_cache_0_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22]); |
| assign _zz_MmuPlugin_ports_0_cacheHitsCalc_5 = (MmuPlugin_ports_0_cache_0_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]); |
| assign _zz_MmuPlugin_ports_1_cacheHitsCalc = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22]; |
| assign _zz_MmuPlugin_ports_1_cacheHitsCalc_1 = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]; |
| assign _zz_MmuPlugin_ports_1_cacheHitsCalc_2 = (MmuPlugin_ports_1_cache_1_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22]); |
| assign _zz_MmuPlugin_ports_1_cacheHitsCalc_3 = (MmuPlugin_ports_1_cache_1_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]); |
| assign _zz_MmuPlugin_ports_1_cacheHitsCalc_4 = (MmuPlugin_ports_1_cache_0_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22]); |
| assign _zz_MmuPlugin_ports_1_cacheHitsCalc_5 = (MmuPlugin_ports_1_cache_0_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]); |
| always @(posedge clk) begin |
| if(_zz_decode_RegFilePlugin_rs1Data) begin |
| _zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; |
| end |
| end |
| |
| always @(posedge clk) begin |
| if(_zz_decode_RegFilePlugin_rs2Data) begin |
| _zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; |
| end |
| end |
| |
| always @(posedge clk) begin |
| if(_zz_1) begin |
| RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; |
| end |
| end |
| |
| InstructionCache IBusCachedPlugin_cache ( |
| `ifdef USE_POWER_PINS |
| .vccd1(vccd1), // User area 1 1.8V power |
| .vssd1(vssd1), // User area 1 digital ground |
| `endif |
| .io_flush (IBusCachedPlugin_cache_io_flush ), //i |
| .io_cpu_prefetch_isValid (IBusCachedPlugin_cache_io_cpu_prefetch_isValid ), //i |
| .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o |
| .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i |
| .io_cpu_fetch_isValid (IBusCachedPlugin_cache_io_cpu_fetch_isValid ), //i |
| .io_cpu_fetch_isStuck (IBusCachedPlugin_cache_io_cpu_fetch_isStuck ), //i |
| .io_cpu_fetch_isRemoved (IBusCachedPlugin_cache_io_cpu_fetch_isRemoved ), //i |
| .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i |
| .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o |
| .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i |
| .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i |
| .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i |
| .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i |
| .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i |
| .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i |
| .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i |
| .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i |
| .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i |
| .io_cpu_fetch_mmuRsp_ways_0_sel (IBusCachedPlugin_mmuBus_rsp_ways_0_sel ), //i |
| .io_cpu_fetch_mmuRsp_ways_0_physical (IBusCachedPlugin_mmuBus_rsp_ways_0_physical[31:0] ), //i |
| .io_cpu_fetch_mmuRsp_ways_1_sel (IBusCachedPlugin_mmuBus_rsp_ways_1_sel ), //i |
| .io_cpu_fetch_mmuRsp_ways_1_physical (IBusCachedPlugin_mmuBus_rsp_ways_1_physical[31:0] ), //i |
| .io_cpu_fetch_mmuRsp_ways_2_sel (IBusCachedPlugin_mmuBus_rsp_ways_2_sel ), //i |
| .io_cpu_fetch_mmuRsp_ways_2_physical (IBusCachedPlugin_mmuBus_rsp_ways_2_physical[31:0] ), //i |
| .io_cpu_fetch_mmuRsp_ways_3_sel (IBusCachedPlugin_mmuBus_rsp_ways_3_sel ), //i |
| .io_cpu_fetch_mmuRsp_ways_3_physical (IBusCachedPlugin_mmuBus_rsp_ways_3_physical[31:0] ), //i |
| .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o |
| .io_cpu_decode_isValid (IBusCachedPlugin_cache_io_cpu_decode_isValid ), //i |
| .io_cpu_decode_isStuck (IBusCachedPlugin_cache_io_cpu_decode_isStuck ), //i |
| .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i |
| .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o |
| .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o |
| .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o |
| .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o |
| .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o |
| .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o |
| .io_cpu_decode_isUser (IBusCachedPlugin_cache_io_cpu_decode_isUser ), //i |
| .io_cpu_fill_valid (IBusCachedPlugin_cache_io_cpu_fill_valid ), //i |
| .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i |
| .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o |
| .io_mem_cmd_ready (iBus_cmd_ready ), //i |
| .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o |
| .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o |
| .io_mem_rsp_valid (iBus_rsp_valid ), //i |
| .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i |
| .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i |
| ._zz_when_Fetcher_l398 (switch_Fetcher_l362[2:0] ), //i |
| ._zz_decodeStage_hit_data_1 (IBusCachedPlugin_injectionPort_payload[31:0] ), //i |
| .clk (clk ), //i |
| .reset (reset ) //i |
| ); |
| DataCache dataCache_1 ( |
| `ifdef USE_POWER_PINS |
| .vccd1(vccd1), // User area 1 1.8V power |
| .vssd1(vssd1), // User area 1 digital ground |
| `endif |
| .io_cpu_execute_isValid (dataCache_1_io_cpu_execute_isValid ), //i |
| .io_cpu_execute_address (dataCache_1_io_cpu_execute_address[31:0] ), //i |
| .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o |
| .io_cpu_execute_args_wr (dataCache_1_io_cpu_execute_args_wr ), //i |
| .io_cpu_execute_args_size (dataCache_1_io_cpu_execute_args_size[1:0] ), //i |
| .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i |
| .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o |
| .io_cpu_memory_isValid (dataCache_1_io_cpu_memory_isValid ), //i |
| .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i |
| .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o |
| .io_cpu_memory_address (dataCache_1_io_cpu_memory_address[31:0] ), //i |
| .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i |
| .io_cpu_memory_mmuRsp_isIoAccess (dataCache_1_io_cpu_memory_mmuRsp_isIoAccess ), //i |
| .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i |
| .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i |
| .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i |
| .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i |
| .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i |
| .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i |
| .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i |
| .io_cpu_memory_mmuRsp_ways_0_sel (DBusCachedPlugin_mmuBus_rsp_ways_0_sel ), //i |
| .io_cpu_memory_mmuRsp_ways_0_physical (DBusCachedPlugin_mmuBus_rsp_ways_0_physical[31:0] ), //i |
| .io_cpu_memory_mmuRsp_ways_1_sel (DBusCachedPlugin_mmuBus_rsp_ways_1_sel ), //i |
| .io_cpu_memory_mmuRsp_ways_1_physical (DBusCachedPlugin_mmuBus_rsp_ways_1_physical[31:0] ), //i |
| .io_cpu_memory_mmuRsp_ways_2_sel (DBusCachedPlugin_mmuBus_rsp_ways_2_sel ), //i |
| .io_cpu_memory_mmuRsp_ways_2_physical (DBusCachedPlugin_mmuBus_rsp_ways_2_physical[31:0] ), //i |
| .io_cpu_memory_mmuRsp_ways_3_sel (DBusCachedPlugin_mmuBus_rsp_ways_3_sel ), //i |
| .io_cpu_memory_mmuRsp_ways_3_physical (DBusCachedPlugin_mmuBus_rsp_ways_3_physical[31:0] ), //i |
| .io_cpu_writeBack_isValid (dataCache_1_io_cpu_writeBack_isValid ), //i |
| .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i |
| .io_cpu_writeBack_isUser (dataCache_1_io_cpu_writeBack_isUser ), //i |
| .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o |
| .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o |
| .io_cpu_writeBack_storeData (dataCache_1_io_cpu_writeBack_storeData[31:0] ), //i |
| .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o |
| .io_cpu_writeBack_address (dataCache_1_io_cpu_writeBack_address[31:0] ), //i |
| .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o |
| .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o |
| .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o |
| .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o |
| .io_cpu_writeBack_fence_SW (dataCache_1_io_cpu_writeBack_fence_SW ), //i |
| .io_cpu_writeBack_fence_SR (dataCache_1_io_cpu_writeBack_fence_SR ), //i |
| .io_cpu_writeBack_fence_SO (dataCache_1_io_cpu_writeBack_fence_SO ), //i |
| .io_cpu_writeBack_fence_SI (dataCache_1_io_cpu_writeBack_fence_SI ), //i |
| .io_cpu_writeBack_fence_PW (dataCache_1_io_cpu_writeBack_fence_PW ), //i |
| .io_cpu_writeBack_fence_PR (dataCache_1_io_cpu_writeBack_fence_PR ), //i |
| .io_cpu_writeBack_fence_PO (dataCache_1_io_cpu_writeBack_fence_PO ), //i |
| .io_cpu_writeBack_fence_PI (dataCache_1_io_cpu_writeBack_fence_PI ), //i |
| .io_cpu_writeBack_fence_FM (dataCache_1_io_cpu_writeBack_fence_FM[3:0] ), //i |
| .io_cpu_writeBack_exclusiveOk (dataCache_1_io_cpu_writeBack_exclusiveOk ), //o |
| .io_cpu_redo (dataCache_1_io_cpu_redo ), //o |
| .io_cpu_flush_valid (dataCache_1_io_cpu_flush_valid ), //i |
| .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o |
| .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o |
| .io_mem_cmd_ready (dataCache_1_io_mem_cmd_ready ), //i |
| .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o |
| .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o |
| .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o |
| .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o |
| .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o |
| .io_mem_cmd_payload_size (dataCache_1_io_mem_cmd_payload_size[2:0] ), //o |
| .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o |
| .io_mem_rsp_valid (dBus_rsp_valid ), //i |
| .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i |
| .io_mem_rsp_payload_data (dBus_rsp_payload_data[31:0] ), //i |
| .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i |
| .clk (clk ), //i |
| .reset (reset ) //i |
| ); |
| JtagBridge jtagBridge_1 ( |
| `ifdef USE_POWER_PINS |
| .vccd1(vccd1), // User area 1 1.8V power |
| .vssd1(vssd1), // User area 1 digital ground |
| `endif |
| .io_jtag_tms (jtag_tms ), //i |
| .io_jtag_tdi (jtag_tdi ), //i |
| .io_jtag_tdo (jtagBridge_1_io_jtag_tdo ), //o |
| .io_jtag_tck (jtag_tck ), //i |
| .io_remote_cmd_valid (jtagBridge_1_io_remote_cmd_valid ), //o |
| .io_remote_cmd_ready (systemDebugger_1_io_remote_cmd_ready ), //i |
| .io_remote_cmd_payload_last (jtagBridge_1_io_remote_cmd_payload_last ), //o |
| .io_remote_cmd_payload_fragment (jtagBridge_1_io_remote_cmd_payload_fragment ), //o |
| .io_remote_rsp_valid (systemDebugger_1_io_remote_rsp_valid ), //i |
| .io_remote_rsp_ready (jtagBridge_1_io_remote_rsp_ready ), //o |
| .io_remote_rsp_payload_error (systemDebugger_1_io_remote_rsp_payload_error ), //i |
| .io_remote_rsp_payload_data (systemDebugger_1_io_remote_rsp_payload_data[31:0] ), //i |
| .clk (clk ), //i |
| .jtag_rst (jtag_rst ) //i |
| ); |
| SystemDebugger systemDebugger_1 ( |
| `ifdef USE_POWER_PINS |
| .vccd1(vccd1), // User area 1 1.8V power |
| .vssd1(vssd1), // User area 1 digital ground |
| `endif |
| .io_remote_cmd_valid (jtagBridge_1_io_remote_cmd_valid ), //i |
| .io_remote_cmd_ready (systemDebugger_1_io_remote_cmd_ready ), //o |
| .io_remote_cmd_payload_last (jtagBridge_1_io_remote_cmd_payload_last ), //i |
| .io_remote_cmd_payload_fragment (jtagBridge_1_io_remote_cmd_payload_fragment ), //i |
| .io_remote_rsp_valid (systemDebugger_1_io_remote_rsp_valid ), //o |
| .io_remote_rsp_ready (jtagBridge_1_io_remote_rsp_ready ), //i |
| .io_remote_rsp_payload_error (systemDebugger_1_io_remote_rsp_payload_error ), //o |
| .io_remote_rsp_payload_data (systemDebugger_1_io_remote_rsp_payload_data[31:0] ), //o |
| .io_mem_cmd_valid (systemDebugger_1_io_mem_cmd_valid ), //o |
| .io_mem_cmd_ready (debug_bus_cmd_ready ), //i |
| .io_mem_cmd_payload_address (systemDebugger_1_io_mem_cmd_payload_address[31:0] ), //o |
| .io_mem_cmd_payload_data (systemDebugger_1_io_mem_cmd_payload_data[31:0] ), //o |
| .io_mem_cmd_payload_wr (systemDebugger_1_io_mem_cmd_payload_wr ), //o |
| .io_mem_cmd_payload_size (systemDebugger_1_io_mem_cmd_payload_size[1:0] ), //o |
| .io_mem_rsp_valid (debug_bus_cmd_fire_regNext ), //i |
| .io_mem_rsp_payload (debug_bus_rsp_data[31:0] ), //i |
| .clk (clk ), //i |
| .jtag_rst (jtag_rst ) //i |
| ); |
| always @(*) begin |
| case(_zz_IBusCachedPlugin_jump_pcLoad_payload_5) |
| 2'b00 : begin |
| _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = DBusCachedPlugin_redoBranch_payload; |
| end |
| 2'b01 : begin |
| _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = CsrPlugin_jumpInterface_payload; |
| end |
| default : begin |
| _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = BranchPlugin_jumpInterface_payload; |
| end |
| endcase |
| end |
| |
| always @(*) begin |
| case(_zz_writeBack_DBusCachedPlugin_rspShifted_1) |
| 2'b00 : begin |
| _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_0; |
| end |
| 2'b01 : begin |
| _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_1; |
| end |
| 2'b10 : begin |
| _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_2; |
| end |
| default : begin |
| _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_3; |
| end |
| endcase |
| end |
| |
| always @(*) begin |
| case(_zz_writeBack_DBusCachedPlugin_rspShifted_3) |
| 1'b0 : begin |
| _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_1; |
| end |
| default : begin |
| _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_3; |
| end |
| endcase |
| end |
| |
| always @(*) begin |
| case(_zz_MmuPlugin_ports_0_cacheLine_valid_3) |
| 2'b00 : begin |
| _zz_MmuPlugin_ports_0_cacheLine_valid_4 = MmuPlugin_ports_0_cache_0_valid; |
| _zz_MmuPlugin_ports_0_cacheLine_exception = MmuPlugin_ports_0_cache_0_exception; |
| _zz_MmuPlugin_ports_0_cacheLine_superPage = MmuPlugin_ports_0_cache_0_superPage; |
| _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_0 = MmuPlugin_ports_0_cache_0_virtualAddress_0; |
| _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_1 = MmuPlugin_ports_0_cache_0_virtualAddress_1; |
| _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_0 = MmuPlugin_ports_0_cache_0_physicalAddress_0; |
| _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_1 = MmuPlugin_ports_0_cache_0_physicalAddress_1; |
| _zz_MmuPlugin_ports_0_cacheLine_allowRead = MmuPlugin_ports_0_cache_0_allowRead; |
| _zz_MmuPlugin_ports_0_cacheLine_allowWrite = MmuPlugin_ports_0_cache_0_allowWrite; |
| _zz_MmuPlugin_ports_0_cacheLine_allowExecute = MmuPlugin_ports_0_cache_0_allowExecute; |
| _zz_MmuPlugin_ports_0_cacheLine_allowUser = MmuPlugin_ports_0_cache_0_allowUser; |
| end |
| 2'b01 : begin |
| _zz_MmuPlugin_ports_0_cacheLine_valid_4 = MmuPlugin_ports_0_cache_1_valid; |
| _zz_MmuPlugin_ports_0_cacheLine_exception = MmuPlugin_ports_0_cache_1_exception; |
| _zz_MmuPlugin_ports_0_cacheLine_superPage = MmuPlugin_ports_0_cache_1_superPage; |
| _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_0 = MmuPlugin_ports_0_cache_1_virtualAddress_0; |
| _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_1 = MmuPlugin_ports_0_cache_1_virtualAddress_1; |
| _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_0 = MmuPlugin_ports_0_cache_1_physicalAddress_0; |
| _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_1 = MmuPlugin_ports_0_cache_1_physicalAddress_1; |
| _zz_MmuPlugin_ports_0_cacheLine_allowRead = MmuPlugin_ports_0_cache_1_allowRead; |
| _zz_MmuPlugin_ports_0_cacheLine_allowWrite = MmuPlugin_ports_0_cache_1_allowWrite; |
| _zz_MmuPlugin_ports_0_cacheLine_allowExecute = MmuPlugin_ports_0_cache_1_allowExecute; |
| _zz_MmuPlugin_ports_0_cacheLine_allowUser = MmuPlugin_ports_0_cache_1_allowUser; |
| end |
| 2'b10 : begin |
| _zz_MmuPlugin_ports_0_cacheLine_valid_4 = MmuPlugin_ports_0_cache_2_valid; |
| _zz_MmuPlugin_ports_0_cacheLine_exception = MmuPlugin_ports_0_cache_2_exception; |
| _zz_MmuPlugin_ports_0_cacheLine_superPage = MmuPlugin_ports_0_cache_2_superPage; |
| _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_0 = MmuPlugin_ports_0_cache_2_virtualAddress_0; |
| _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_1 = MmuPlugin_ports_0_cache_2_virtualAddress_1; |
| _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_0 = MmuPlugin_ports_0_cache_2_physicalAddress_0; |
| _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_1 = MmuPlugin_ports_0_cache_2_physicalAddress_1; |
| _zz_MmuPlugin_ports_0_cacheLine_allowRead = MmuPlugin_ports_0_cache_2_allowRead; |
| _zz_MmuPlugin_ports_0_cacheLine_allowWrite = MmuPlugin_ports_0_cache_2_allowWrite; |
| _zz_MmuPlugin_ports_0_cacheLine_allowExecute = MmuPlugin_ports_0_cache_2_allowExecute; |
| _zz_MmuPlugin_ports_0_cacheLine_allowUser = MmuPlugin_ports_0_cache_2_allowUser; |
| end |
| default : begin |
| _zz_MmuPlugin_ports_0_cacheLine_valid_4 = MmuPlugin_ports_0_cache_3_valid; |
| _zz_MmuPlugin_ports_0_cacheLine_exception = MmuPlugin_ports_0_cache_3_exception; |
| _zz_MmuPlugin_ports_0_cacheLine_superPage = MmuPlugin_ports_0_cache_3_superPage; |
| _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_0 = MmuPlugin_ports_0_cache_3_virtualAddress_0; |
| _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_1 = MmuPlugin_ports_0_cache_3_virtualAddress_1; |
| _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_0 = MmuPlugin_ports_0_cache_3_physicalAddress_0; |
| _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_1 = MmuPlugin_ports_0_cache_3_physicalAddress_1; |
| _zz_MmuPlugin_ports_0_cacheLine_allowRead = MmuPlugin_ports_0_cache_3_allowRead; |
| _zz_MmuPlugin_ports_0_cacheLine_allowWrite = MmuPlugin_ports_0_cache_3_allowWrite; |
| _zz_MmuPlugin_ports_0_cacheLine_allowExecute = MmuPlugin_ports_0_cache_3_allowExecute; |
| _zz_MmuPlugin_ports_0_cacheLine_allowUser = MmuPlugin_ports_0_cache_3_allowUser; |
| end |
| endcase |
| end |
| |
| always @(*) begin |
| case(_zz_MmuPlugin_ports_1_cacheLine_valid_3) |
| 2'b00 : begin |
| _zz_MmuPlugin_ports_1_cacheLine_valid_4 = MmuPlugin_ports_1_cache_0_valid; |
| _zz_MmuPlugin_ports_1_cacheLine_exception = MmuPlugin_ports_1_cache_0_exception; |
| _zz_MmuPlugin_ports_1_cacheLine_superPage = MmuPlugin_ports_1_cache_0_superPage; |
| _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_0 = MmuPlugin_ports_1_cache_0_virtualAddress_0; |
| _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_1 = MmuPlugin_ports_1_cache_0_virtualAddress_1; |
| _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_0 = MmuPlugin_ports_1_cache_0_physicalAddress_0; |
| _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_1 = MmuPlugin_ports_1_cache_0_physicalAddress_1; |
| _zz_MmuPlugin_ports_1_cacheLine_allowRead = MmuPlugin_ports_1_cache_0_allowRead; |
| _zz_MmuPlugin_ports_1_cacheLine_allowWrite = MmuPlugin_ports_1_cache_0_allowWrite; |
| _zz_MmuPlugin_ports_1_cacheLine_allowExecute = MmuPlugin_ports_1_cache_0_allowExecute; |
| _zz_MmuPlugin_ports_1_cacheLine_allowUser = MmuPlugin_ports_1_cache_0_allowUser; |
| end |
| 2'b01 : begin |
| _zz_MmuPlugin_ports_1_cacheLine_valid_4 = MmuPlugin_ports_1_cache_1_valid; |
| _zz_MmuPlugin_ports_1_cacheLine_exception = MmuPlugin_ports_1_cache_1_exception; |
| _zz_MmuPlugin_ports_1_cacheLine_superPage = MmuPlugin_ports_1_cache_1_superPage; |
| _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_0 = MmuPlugin_ports_1_cache_1_virtualAddress_0; |
| _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_1 = MmuPlugin_ports_1_cache_1_virtualAddress_1; |
| _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_0 = MmuPlugin_ports_1_cache_1_physicalAddress_0; |
| _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_1 = MmuPlugin_ports_1_cache_1_physicalAddress_1; |
| _zz_MmuPlugin_ports_1_cacheLine_allowRead = MmuPlugin_ports_1_cache_1_allowRead; |
| _zz_MmuPlugin_ports_1_cacheLine_allowWrite = MmuPlugin_ports_1_cache_1_allowWrite; |
| _zz_MmuPlugin_ports_1_cacheLine_allowExecute = MmuPlugin_ports_1_cache_1_allowExecute; |
| _zz_MmuPlugin_ports_1_cacheLine_allowUser = MmuPlugin_ports_1_cache_1_allowUser; |
| end |
| 2'b10 : begin |
| _zz_MmuPlugin_ports_1_cacheLine_valid_4 = MmuPlugin_ports_1_cache_2_valid; |
| _zz_MmuPlugin_ports_1_cacheLine_exception = MmuPlugin_ports_1_cache_2_exception; |
| _zz_MmuPlugin_ports_1_cacheLine_superPage = MmuPlugin_ports_1_cache_2_superPage; |
| _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_0 = MmuPlugin_ports_1_cache_2_virtualAddress_0; |
| _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_1 = MmuPlugin_ports_1_cache_2_virtualAddress_1; |
| _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_0 = MmuPlugin_ports_1_cache_2_physicalAddress_0; |
| _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_1 = MmuPlugin_ports_1_cache_2_physicalAddress_1; |
| _zz_MmuPlugin_ports_1_cacheLine_allowRead = MmuPlugin_ports_1_cache_2_allowRead; |
| _zz_MmuPlugin_ports_1_cacheLine_allowWrite = MmuPlugin_ports_1_cache_2_allowWrite; |
| _zz_MmuPlugin_ports_1_cacheLine_allowExecute = MmuPlugin_ports_1_cache_2_allowExecute; |
| _zz_MmuPlugin_ports_1_cacheLine_allowUser = MmuPlugin_ports_1_cache_2_allowUser; |
| end |
| default : begin |
| _zz_MmuPlugin_ports_1_cacheLine_valid_4 = MmuPlugin_ports_1_cache_3_valid; |
| _zz_MmuPlugin_ports_1_cacheLine_exception = MmuPlugin_ports_1_cache_3_exception; |
| _zz_MmuPlugin_ports_1_cacheLine_superPage = MmuPlugin_ports_1_cache_3_superPage; |
| _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_0 = MmuPlugin_ports_1_cache_3_virtualAddress_0; |
| _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_1 = MmuPlugin_ports_1_cache_3_virtualAddress_1; |
| _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_0 = MmuPlugin_ports_1_cache_3_physicalAddress_0; |
| _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_1 = MmuPlugin_ports_1_cache_3_physicalAddress_1; |
| _zz_MmuPlugin_ports_1_cacheLine_allowRead = MmuPlugin_ports_1_cache_3_allowRead; |
| _zz_MmuPlugin_ports_1_cacheLine_allowWrite = MmuPlugin_ports_1_cache_3_allowWrite; |
| _zz_MmuPlugin_ports_1_cacheLine_allowExecute = MmuPlugin_ports_1_cache_3_allowExecute; |
| _zz_MmuPlugin_ports_1_cacheLine_allowUser = MmuPlugin_ports_1_cache_3_allowUser; |
| end |
| endcase |
| end |
| |
| `ifndef SYNTHESIS |
| always @(*) begin |
| case(decode_BRANCH_CTRL) |
| BranchCtrlEnum_INC : decode_BRANCH_CTRL_string = "INC "; |
| BranchCtrlEnum_B : decode_BRANCH_CTRL_string = "B "; |
| BranchCtrlEnum_JAL : decode_BRANCH_CTRL_string = "JAL "; |
| BranchCtrlEnum_JALR : decode_BRANCH_CTRL_string = "JALR"; |
| default : decode_BRANCH_CTRL_string = "????"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_decode_BRANCH_CTRL) |
| BranchCtrlEnum_INC : _zz_decode_BRANCH_CTRL_string = "INC "; |
| BranchCtrlEnum_B : _zz_decode_BRANCH_CTRL_string = "B "; |
| BranchCtrlEnum_JAL : _zz_decode_BRANCH_CTRL_string = "JAL "; |
| BranchCtrlEnum_JALR : _zz_decode_BRANCH_CTRL_string = "JALR"; |
| default : _zz_decode_BRANCH_CTRL_string = "????"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_decode_to_execute_BRANCH_CTRL) |
| BranchCtrlEnum_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC "; |
| BranchCtrlEnum_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B "; |
| BranchCtrlEnum_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL "; |
| BranchCtrlEnum_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR"; |
| default : _zz_decode_to_execute_BRANCH_CTRL_string = "????"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_decode_to_execute_BRANCH_CTRL_1) |
| BranchCtrlEnum_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC "; |
| BranchCtrlEnum_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B "; |
| BranchCtrlEnum_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL "; |
| BranchCtrlEnum_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR"; |
| default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_memory_to_writeBack_ENV_CTRL) |
| EnvCtrlEnum_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE"; |
| EnvCtrlEnum_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET"; |
| default : _zz_memory_to_writeBack_ENV_CTRL_string = "????"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_memory_to_writeBack_ENV_CTRL_1) |
| EnvCtrlEnum_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE"; |
| EnvCtrlEnum_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET"; |
| default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "????"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_execute_to_memory_ENV_CTRL) |
| EnvCtrlEnum_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE"; |
| EnvCtrlEnum_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET"; |
| default : _zz_execute_to_memory_ENV_CTRL_string = "????"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_execute_to_memory_ENV_CTRL_1) |
| EnvCtrlEnum_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE"; |
| EnvCtrlEnum_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET"; |
| default : _zz_execute_to_memory_ENV_CTRL_1_string = "????"; |
| endcase |
| end |
| always @(*) begin |
| case(decode_ENV_CTRL) |
| EnvCtrlEnum_NONE : decode_ENV_CTRL_string = "NONE"; |
| EnvCtrlEnum_XRET : decode_ENV_CTRL_string = "XRET"; |
| default : decode_ENV_CTRL_string = "????"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_decode_ENV_CTRL) |
| EnvCtrlEnum_NONE : _zz_decode_ENV_CTRL_string = "NONE"; |
| EnvCtrlEnum_XRET : _zz_decode_ENV_CTRL_string = "XRET"; |
| default : _zz_decode_ENV_CTRL_string = "????"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_decode_to_execute_ENV_CTRL) |
| EnvCtrlEnum_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE"; |
| EnvCtrlEnum_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET"; |
| default : _zz_decode_to_execute_ENV_CTRL_string = "????"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_decode_to_execute_ENV_CTRL_1) |
| EnvCtrlEnum_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE"; |
| EnvCtrlEnum_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET"; |
| default : _zz_decode_to_execute_ENV_CTRL_1_string = "????"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_execute_to_memory_SHIFT_CTRL) |
| ShiftCtrlEnum_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; |
| ShiftCtrlEnum_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; |
| ShiftCtrlEnum_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; |
| ShiftCtrlEnum_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; |
| default : _zz_execute_to_memory_SHIFT_CTRL_string = "?????????"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_execute_to_memory_SHIFT_CTRL_1) |
| ShiftCtrlEnum_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "DISABLE_1"; |
| ShiftCtrlEnum_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SLL_1 "; |
| ShiftCtrlEnum_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRL_1 "; |
| ShiftCtrlEnum_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRA_1 "; |
| default : _zz_execute_to_memory_SHIFT_CTRL_1_string = "?????????"; |
| endcase |
| end |
| always @(*) begin |
| case(decode_SHIFT_CTRL) |
| ShiftCtrlEnum_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; |
| ShiftCtrlEnum_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; |
| ShiftCtrlEnum_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; |
| ShiftCtrlEnum_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; |
| default : decode_SHIFT_CTRL_string = "?????????"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_decode_SHIFT_CTRL) |
| ShiftCtrlEnum_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1"; |
| ShiftCtrlEnum_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 "; |
| ShiftCtrlEnum_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 "; |
| ShiftCtrlEnum_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 "; |
| default : _zz_decode_SHIFT_CTRL_string = "?????????"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_decode_to_execute_SHIFT_CTRL) |
| ShiftCtrlEnum_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; |
| ShiftCtrlEnum_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; |
| ShiftCtrlEnum_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; |
| ShiftCtrlEnum_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; |
| default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_decode_to_execute_SHIFT_CTRL_1) |
| ShiftCtrlEnum_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1"; |
| ShiftCtrlEnum_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 "; |
| ShiftCtrlEnum_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 "; |
| ShiftCtrlEnum_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 "; |
| default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????"; |
| endcase |
| end |
| always @(*) begin |
| case(decode_ALU_BITWISE_CTRL) |
| AluBitwiseCtrlEnum_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; |
| AluBitwiseCtrlEnum_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; |
| AluBitwiseCtrlEnum_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; |
| default : decode_ALU_BITWISE_CTRL_string = "?????"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_decode_ALU_BITWISE_CTRL) |
| AluBitwiseCtrlEnum_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1"; |
| AluBitwiseCtrlEnum_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 "; |
| AluBitwiseCtrlEnum_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1"; |
| default : _zz_decode_ALU_BITWISE_CTRL_string = "?????"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_decode_to_execute_ALU_BITWISE_CTRL) |
| AluBitwiseCtrlEnum_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; |
| AluBitwiseCtrlEnum_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; |
| AluBitwiseCtrlEnum_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; |
| default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1) |
| AluBitwiseCtrlEnum_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1"; |
| AluBitwiseCtrlEnum_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 "; |
| AluBitwiseCtrlEnum_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1"; |
| default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????"; |
| endcase |
| end |
| always @(*) begin |
| case(decode_ALU_CTRL) |
| AluCtrlEnum_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; |
| AluCtrlEnum_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; |
| AluCtrlEnum_BITWISE : decode_ALU_CTRL_string = "BITWISE "; |
| default : decode_ALU_CTRL_string = "????????"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_decode_ALU_CTRL) |
| AluCtrlEnum_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB "; |
| AluCtrlEnum_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU"; |
| AluCtrlEnum_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE "; |
| default : _zz_decode_ALU_CTRL_string = "????????"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_decode_to_execute_ALU_CTRL) |
| AluCtrlEnum_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB "; |
| AluCtrlEnum_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; |
| AluCtrlEnum_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE "; |
| default : _zz_decode_to_execute_ALU_CTRL_string = "????????"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_decode_to_execute_ALU_CTRL_1) |
| AluCtrlEnum_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB "; |
| AluCtrlEnum_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU"; |
| AluCtrlEnum_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE "; |
| default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????"; |
| endcase |
| end |
| always @(*) begin |
| case(execute_BRANCH_CTRL) |
| BranchCtrlEnum_INC : execute_BRANCH_CTRL_string = "INC "; |
| BranchCtrlEnum_B : execute_BRANCH_CTRL_string = "B "; |
| BranchCtrlEnum_JAL : execute_BRANCH_CTRL_string = "JAL "; |
| BranchCtrlEnum_JALR : execute_BRANCH_CTRL_string = "JALR"; |
| default : execute_BRANCH_CTRL_string = "????"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_execute_BRANCH_CTRL) |
| BranchCtrlEnum_INC : _zz_execute_BRANCH_CTRL_string = "INC "; |
| BranchCtrlEnum_B : _zz_execute_BRANCH_CTRL_string = "B "; |
| BranchCtrlEnum_JAL : _zz_execute_BRANCH_CTRL_string = "JAL "; |
| BranchCtrlEnum_JALR : _zz_execute_BRANCH_CTRL_string = "JALR"; |
| default : _zz_execute_BRANCH_CTRL_string = "????"; |
| endcase |
| end |
| always @(*) begin |
| case(memory_ENV_CTRL) |
| EnvCtrlEnum_NONE : memory_ENV_CTRL_string = "NONE"; |
| EnvCtrlEnum_XRET : memory_ENV_CTRL_string = "XRET"; |
| default : memory_ENV_CTRL_string = "????"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_memory_ENV_CTRL) |
| EnvCtrlEnum_NONE : _zz_memory_ENV_CTRL_string = "NONE"; |
| EnvCtrlEnum_XRET : _zz_memory_ENV_CTRL_string = "XRET"; |
| default : _zz_memory_ENV_CTRL_string = "????"; |
| endcase |
| end |
| always @(*) begin |
| case(execute_ENV_CTRL) |
| EnvCtrlEnum_NONE : execute_ENV_CTRL_string = "NONE"; |
| EnvCtrlEnum_XRET : execute_ENV_CTRL_string = "XRET"; |
| default : execute_ENV_CTRL_string = "????"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_execute_ENV_CTRL) |
| EnvCtrlEnum_NONE : _zz_execute_ENV_CTRL_string = "NONE"; |
| EnvCtrlEnum_XRET : _zz_execute_ENV_CTRL_string = "XRET"; |
| default : _zz_execute_ENV_CTRL_string = "????"; |
| endcase |
| end |
| always @(*) begin |
| case(writeBack_ENV_CTRL) |
| EnvCtrlEnum_NONE : writeBack_ENV_CTRL_string = "NONE"; |
| EnvCtrlEnum_XRET : writeBack_ENV_CTRL_string = "XRET"; |
| default : writeBack_ENV_CTRL_string = "????"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_writeBack_ENV_CTRL) |
| EnvCtrlEnum_NONE : _zz_writeBack_ENV_CTRL_string = "NONE"; |
| EnvCtrlEnum_XRET : _zz_writeBack_ENV_CTRL_string = "XRET"; |
| default : _zz_writeBack_ENV_CTRL_string = "????"; |
| endcase |
| end |
| always @(*) begin |
| case(memory_SHIFT_CTRL) |
| ShiftCtrlEnum_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; |
| ShiftCtrlEnum_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; |
| ShiftCtrlEnum_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; |
| ShiftCtrlEnum_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; |
| default : memory_SHIFT_CTRL_string = "?????????"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_memory_SHIFT_CTRL) |
| ShiftCtrlEnum_DISABLE_1 : _zz_memory_SHIFT_CTRL_string = "DISABLE_1"; |
| ShiftCtrlEnum_SLL_1 : _zz_memory_SHIFT_CTRL_string = "SLL_1 "; |
| ShiftCtrlEnum_SRL_1 : _zz_memory_SHIFT_CTRL_string = "SRL_1 "; |
| ShiftCtrlEnum_SRA_1 : _zz_memory_SHIFT_CTRL_string = "SRA_1 "; |
| default : _zz_memory_SHIFT_CTRL_string = "?????????"; |
| endcase |
| end |
| always @(*) begin |
| case(execute_SHIFT_CTRL) |
| ShiftCtrlEnum_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; |
| ShiftCtrlEnum_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; |
| ShiftCtrlEnum_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; |
| ShiftCtrlEnum_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; |
| default : execute_SHIFT_CTRL_string = "?????????"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_execute_SHIFT_CTRL) |
| ShiftCtrlEnum_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1"; |
| ShiftCtrlEnum_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 "; |
| ShiftCtrlEnum_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 "; |
| ShiftCtrlEnum_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 "; |
| default : _zz_execute_SHIFT_CTRL_string = "?????????"; |
| endcase |
| end |
| always @(*) begin |
| case(decode_SRC2_CTRL) |
| Src2CtrlEnum_RS : decode_SRC2_CTRL_string = "RS "; |
| Src2CtrlEnum_IMI : decode_SRC2_CTRL_string = "IMI"; |
| Src2CtrlEnum_IMS : decode_SRC2_CTRL_string = "IMS"; |
| Src2CtrlEnum_PC : decode_SRC2_CTRL_string = "PC "; |
| default : decode_SRC2_CTRL_string = "???"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_decode_SRC2_CTRL) |
| Src2CtrlEnum_RS : _zz_decode_SRC2_CTRL_string = "RS "; |
| Src2CtrlEnum_IMI : _zz_decode_SRC2_CTRL_string = "IMI"; |
| Src2CtrlEnum_IMS : _zz_decode_SRC2_CTRL_string = "IMS"; |
| Src2CtrlEnum_PC : _zz_decode_SRC2_CTRL_string = "PC "; |
| default : _zz_decode_SRC2_CTRL_string = "???"; |
| endcase |
| end |
| always @(*) begin |
| case(decode_SRC1_CTRL) |
| Src1CtrlEnum_RS : decode_SRC1_CTRL_string = "RS "; |
| Src1CtrlEnum_IMU : decode_SRC1_CTRL_string = "IMU "; |
| Src1CtrlEnum_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; |
| Src1CtrlEnum_URS1 : decode_SRC1_CTRL_string = "URS1 "; |
| default : decode_SRC1_CTRL_string = "????????????"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_decode_SRC1_CTRL) |
| Src1CtrlEnum_RS : _zz_decode_SRC1_CTRL_string = "RS "; |
| Src1CtrlEnum_IMU : _zz_decode_SRC1_CTRL_string = "IMU "; |
| Src1CtrlEnum_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT"; |
| Src1CtrlEnum_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 "; |
| default : _zz_decode_SRC1_CTRL_string = "????????????"; |
| endcase |
| end |
| always @(*) begin |
| case(execute_ALU_CTRL) |
| AluCtrlEnum_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; |
| AluCtrlEnum_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; |
| AluCtrlEnum_BITWISE : execute_ALU_CTRL_string = "BITWISE "; |
| default : execute_ALU_CTRL_string = "????????"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_execute_ALU_CTRL) |
| AluCtrlEnum_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB "; |
| AluCtrlEnum_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU"; |
| AluCtrlEnum_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE "; |
| default : _zz_execute_ALU_CTRL_string = "????????"; |
| endcase |
| end |
| always @(*) begin |
| case(execute_ALU_BITWISE_CTRL) |
| AluBitwiseCtrlEnum_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; |
| AluBitwiseCtrlEnum_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; |
| AluBitwiseCtrlEnum_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; |
| default : execute_ALU_BITWISE_CTRL_string = "?????"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_execute_ALU_BITWISE_CTRL) |
| AluBitwiseCtrlEnum_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1"; |
| AluBitwiseCtrlEnum_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 "; |
| AluBitwiseCtrlEnum_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1"; |
| default : _zz_execute_ALU_BITWISE_CTRL_string = "?????"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_decode_BRANCH_CTRL_1) |
| BranchCtrlEnum_INC : _zz_decode_BRANCH_CTRL_1_string = "INC "; |
| BranchCtrlEnum_B : _zz_decode_BRANCH_CTRL_1_string = "B "; |
| BranchCtrlEnum_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL "; |
| BranchCtrlEnum_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR"; |
| default : _zz_decode_BRANCH_CTRL_1_string = "????"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_decode_ENV_CTRL_1) |
| EnvCtrlEnum_NONE : _zz_decode_ENV_CTRL_1_string = "NONE"; |
| EnvCtrlEnum_XRET : _zz_decode_ENV_CTRL_1_string = "XRET"; |
| default : _zz_decode_ENV_CTRL_1_string = "????"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_decode_SHIFT_CTRL_1) |
| ShiftCtrlEnum_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1"; |
| ShiftCtrlEnum_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 "; |
| ShiftCtrlEnum_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 "; |
| ShiftCtrlEnum_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 "; |
| default : _zz_decode_SHIFT_CTRL_1_string = "?????????"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_decode_ALU_BITWISE_CTRL_1) |
| AluBitwiseCtrlEnum_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1"; |
| AluBitwiseCtrlEnum_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 "; |
| AluBitwiseCtrlEnum_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1"; |
| default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_decode_SRC2_CTRL_1) |
| Src2CtrlEnum_RS : _zz_decode_SRC2_CTRL_1_string = "RS "; |
| Src2CtrlEnum_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI"; |
| Src2CtrlEnum_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS"; |
| Src2CtrlEnum_PC : _zz_decode_SRC2_CTRL_1_string = "PC "; |
| default : _zz_decode_SRC2_CTRL_1_string = "???"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_decode_ALU_CTRL_1) |
| AluCtrlEnum_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB "; |
| AluCtrlEnum_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU"; |
| AluCtrlEnum_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE "; |
| default : _zz_decode_ALU_CTRL_1_string = "????????"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_decode_SRC1_CTRL_1) |
| Src1CtrlEnum_RS : _zz_decode_SRC1_CTRL_1_string = "RS "; |
| Src1CtrlEnum_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU "; |
| Src1CtrlEnum_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT"; |
| Src1CtrlEnum_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 "; |
| default : _zz_decode_SRC1_CTRL_1_string = "????????????"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_decode_SRC1_CTRL_2) |
| Src1CtrlEnum_RS : _zz_decode_SRC1_CTRL_2_string = "RS "; |
| Src1CtrlEnum_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU "; |
| Src1CtrlEnum_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT"; |
| Src1CtrlEnum_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 "; |
| default : _zz_decode_SRC1_CTRL_2_string = "????????????"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_decode_ALU_CTRL_2) |
| AluCtrlEnum_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB "; |
| AluCtrlEnum_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU"; |
| AluCtrlEnum_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE "; |
| default : _zz_decode_ALU_CTRL_2_string = "????????"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_decode_SRC2_CTRL_2) |
| Src2CtrlEnum_RS : _zz_decode_SRC2_CTRL_2_string = "RS "; |
| Src2CtrlEnum_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI"; |
| Src2CtrlEnum_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS"; |
| Src2CtrlEnum_PC : _zz_decode_SRC2_CTRL_2_string = "PC "; |
| default : _zz_decode_SRC2_CTRL_2_string = "???"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_decode_ALU_BITWISE_CTRL_2) |
| AluBitwiseCtrlEnum_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1"; |
| AluBitwiseCtrlEnum_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 "; |
| AluBitwiseCtrlEnum_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1"; |
| default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_decode_SHIFT_CTRL_2) |
| ShiftCtrlEnum_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1"; |
| ShiftCtrlEnum_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 "; |
| ShiftCtrlEnum_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 "; |
| ShiftCtrlEnum_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 "; |
| default : _zz_decode_SHIFT_CTRL_2_string = "?????????"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_decode_ENV_CTRL_2) |
| EnvCtrlEnum_NONE : _zz_decode_ENV_CTRL_2_string = "NONE"; |
| EnvCtrlEnum_XRET : _zz_decode_ENV_CTRL_2_string = "XRET"; |
| default : _zz_decode_ENV_CTRL_2_string = "????"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_decode_BRANCH_CTRL_2) |
| BranchCtrlEnum_INC : _zz_decode_BRANCH_CTRL_2_string = "INC "; |
| BranchCtrlEnum_B : _zz_decode_BRANCH_CTRL_2_string = "B "; |
| BranchCtrlEnum_JAL : _zz_decode_BRANCH_CTRL_2_string = "JAL "; |
| BranchCtrlEnum_JALR : _zz_decode_BRANCH_CTRL_2_string = "JALR"; |
| default : _zz_decode_BRANCH_CTRL_2_string = "????"; |
| endcase |
| end |
| always @(*) begin |
| case(MmuPlugin_shared_state_1) |
| MmuPlugin_shared_State_IDLE : MmuPlugin_shared_state_1_string = "IDLE "; |
| MmuPlugin_shared_State_L1_CMD : MmuPlugin_shared_state_1_string = "L1_CMD"; |
| MmuPlugin_shared_State_L1_RSP : MmuPlugin_shared_state_1_string = "L1_RSP"; |
| MmuPlugin_shared_State_L0_CMD : MmuPlugin_shared_state_1_string = "L0_CMD"; |
| MmuPlugin_shared_State_L0_RSP : MmuPlugin_shared_state_1_string = "L0_RSP"; |
| default : MmuPlugin_shared_state_1_string = "??????"; |
| endcase |
| end |
| always @(*) begin |
| case(decode_to_execute_ALU_CTRL) |
| AluCtrlEnum_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; |
| AluCtrlEnum_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; |
| AluCtrlEnum_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; |
| default : decode_to_execute_ALU_CTRL_string = "????????"; |
| endcase |
| end |
| always @(*) begin |
| case(decode_to_execute_ALU_BITWISE_CTRL) |
| AluBitwiseCtrlEnum_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; |
| AluBitwiseCtrlEnum_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; |
| AluBitwiseCtrlEnum_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; |
| default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; |
| endcase |
| end |
| always @(*) begin |
| case(decode_to_execute_SHIFT_CTRL) |
| ShiftCtrlEnum_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; |
| ShiftCtrlEnum_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; |
| ShiftCtrlEnum_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; |
| ShiftCtrlEnum_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; |
| default : decode_to_execute_SHIFT_CTRL_string = "?????????"; |
| endcase |
| end |
| always @(*) begin |
| case(execute_to_memory_SHIFT_CTRL) |
| ShiftCtrlEnum_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; |
| ShiftCtrlEnum_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; |
| ShiftCtrlEnum_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; |
| ShiftCtrlEnum_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; |
| default : execute_to_memory_SHIFT_CTRL_string = "?????????"; |
| endcase |
| end |
| always @(*) begin |
| case(decode_to_execute_ENV_CTRL) |
| EnvCtrlEnum_NONE : decode_to_execute_ENV_CTRL_string = "NONE"; |
| EnvCtrlEnum_XRET : decode_to_execute_ENV_CTRL_string = "XRET"; |
| default : decode_to_execute_ENV_CTRL_string = "????"; |
| endcase |
| end |
| always @(*) begin |
| case(execute_to_memory_ENV_CTRL) |
| EnvCtrlEnum_NONE : execute_to_memory_ENV_CTRL_string = "NONE"; |
| EnvCtrlEnum_XRET : execute_to_memory_ENV_CTRL_string = "XRET"; |
| default : execute_to_memory_ENV_CTRL_string = "????"; |
| endcase |
| end |
| always @(*) begin |
| case(memory_to_writeBack_ENV_CTRL) |
| EnvCtrlEnum_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE"; |
| EnvCtrlEnum_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET"; |
| default : memory_to_writeBack_ENV_CTRL_string = "????"; |
| endcase |
| end |
| always @(*) begin |
| case(decode_to_execute_BRANCH_CTRL) |
| BranchCtrlEnum_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; |
| BranchCtrlEnum_B : decode_to_execute_BRANCH_CTRL_string = "B "; |
| BranchCtrlEnum_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; |
| BranchCtrlEnum_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; |
| default : decode_to_execute_BRANCH_CTRL_string = "????"; |
| endcase |
| end |
| `endif |
| |
| assign memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW) + $signed(_zz_memory_MUL_LOW_7)); |
| assign memory_MUL_HH = execute_to_memory_MUL_HH; |
| assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); |
| assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); |
| assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); |
| assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); |
| assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT; |
| assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA; |
| assign execute_IS_DBUS_SHARING = MmuPlugin_dBusAccess_cmd_fire; |
| assign memory_MEMORY_STORE_DATA_RF = execute_to_memory_MEMORY_STORE_DATA_RF; |
| assign execute_MEMORY_STORE_DATA_RF = _zz_execute_MEMORY_STORE_DATA_RF; |
| assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); |
| assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); |
| assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); |
| assign decode_SRC2 = _zz_decode_SRC2_6; |
| assign decode_SRC1 = _zz_decode_SRC1_1; |
| assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); |
| assign decode_IS_SFENCE_VMA2 = _zz_decode_IS_SFENCE_VMA2[32]; |
| assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL; |
| assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1; |
| assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1; |
| assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1; |
| assign decode_ENV_CTRL = _zz_decode_ENV_CTRL; |
| assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1; |
| assign decode_IS_CSR = _zz_decode_IS_SFENCE_VMA2[28]; |
| assign decode_IS_RS2_SIGNED = _zz_decode_IS_SFENCE_VMA2[26]; |
| assign decode_IS_RS1_SIGNED = _zz_decode_IS_SFENCE_VMA2[25]; |
| assign decode_IS_DIV = _zz_decode_IS_SFENCE_VMA2[24]; |
| assign memory_IS_MUL = execute_to_memory_IS_MUL; |
| assign execute_IS_MUL = decode_to_execute_IS_MUL; |
| assign decode_IS_MUL = _zz_decode_IS_SFENCE_VMA2[23]; |
| assign _zz_execute_to_memory_SHIFT_CTRL = _zz_execute_to_memory_SHIFT_CTRL_1; |
| assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL; |
| assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1; |
| assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL; |
| assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1; |
| assign decode_SRC_LESS_UNSIGNED = _zz_decode_IS_SFENCE_VMA2[17]; |
| assign decode_MEMORY_MANAGMENT = _zz_decode_IS_SFENCE_VMA2[16]; |
| assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; |
| assign decode_MEMORY_WR = _zz_decode_IS_SFENCE_VMA2[13]; |
| assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; |
| assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_IS_SFENCE_VMA2[12]; |
| assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_IS_SFENCE_VMA2[11]; |
| assign decode_ALU_CTRL = _zz_decode_ALU_CTRL; |
| assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1; |
| assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; |
| assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; |
| assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; |
| assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; |
| assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); |
| assign memory_PC = execute_to_memory_PC; |
| assign execute_IS_SFENCE_VMA2 = decode_to_execute_IS_SFENCE_VMA2; |
| assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; |
| assign execute_BRANCH_DO = _zz_execute_BRANCH_DO_1; |
| assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL; |
| assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; |
| assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; |
| assign execute_IS_CSR = decode_to_execute_IS_CSR; |
| assign memory_ENV_CTRL = _zz_memory_ENV_CTRL; |
| assign execute_ENV_CTRL = _zz_execute_ENV_CTRL; |
| assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL; |
| assign execute_PC = decode_to_execute_PC; |
| assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; |
| assign decode_IS_EBREAK = _zz_decode_IS_SFENCE_VMA2[27]; |
| assign decode_RS2_USE = _zz_decode_IS_SFENCE_VMA2[15]; |
| assign decode_RS1_USE = _zz_decode_IS_SFENCE_VMA2[5]; |
| always @(*) begin |
| _zz_decode_RS2 = execute_REGFILE_WRITE_DATA; |
| if(when_CsrPlugin_l1176) begin |
| _zz_decode_RS2 = CsrPlugin_csrMapping_readDataSignal; |
| end |
| if(DBusCachedPlugin_forceDatapath) begin |
| _zz_decode_RS2 = MmuPlugin_dBusAccess_cmd_payload_address; |
| end |
| end |
| |
| assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; |
| assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; |
| assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; |
| assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; |
| assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; |
| always @(*) begin |
| decode_RS2 = decode_RegFilePlugin_rs2Data; |
| if(HazardSimplePlugin_writeBackBuffer_valid) begin |
| if(HazardSimplePlugin_addr1Match) begin |
| decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; |
| end |
| end |
| if(when_HazardSimplePlugin_l45) begin |
| if(when_HazardSimplePlugin_l47) begin |
| if(when_HazardSimplePlugin_l51) begin |
| decode_RS2 = _zz_decode_RS2_2; |
| end |
| end |
| end |
| if(when_HazardSimplePlugin_l45_1) begin |
| if(memory_BYPASSABLE_MEMORY_STAGE) begin |
| if(when_HazardSimplePlugin_l51_1) begin |
| decode_RS2 = _zz_decode_RS2_1; |
| end |
| end |
| end |
| if(when_HazardSimplePlugin_l45_2) begin |
| if(execute_BYPASSABLE_EXECUTE_STAGE) begin |
| if(when_HazardSimplePlugin_l51_2) begin |
| decode_RS2 = _zz_decode_RS2; |
| end |
| end |
| end |
| end |
| |
| always @(*) begin |
| decode_RS1 = decode_RegFilePlugin_rs1Data; |
| if(HazardSimplePlugin_writeBackBuffer_valid) begin |
| if(HazardSimplePlugin_addr0Match) begin |
| decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; |
| end |
| end |
| if(when_HazardSimplePlugin_l45) begin |
| if(when_HazardSimplePlugin_l47) begin |
| if(when_HazardSimplePlugin_l48) begin |
| decode_RS1 = _zz_decode_RS2_2; |
| end |
| end |
| end |
| if(when_HazardSimplePlugin_l45_1) begin |
| if(memory_BYPASSABLE_MEMORY_STAGE) begin |
| if(when_HazardSimplePlugin_l48_1) begin |
| decode_RS1 = _zz_decode_RS2_1; |
| end |
| end |
| end |
| if(when_HazardSimplePlugin_l45_2) begin |
| if(execute_BYPASSABLE_EXECUTE_STAGE) begin |
| if(when_HazardSimplePlugin_l48_2) begin |
| decode_RS1 = _zz_decode_RS2; |
| end |
| end |
| end |
| end |
| |
| assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; |
| assign execute_IS_DIV = decode_to_execute_IS_DIV; |
| assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; |
| assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; |
| assign memory_IS_DIV = execute_to_memory_IS_DIV; |
| assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL; |
| assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH; |
| assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW; |
| assign memory_MUL_HL = execute_to_memory_MUL_HL; |
| assign memory_MUL_LH = execute_to_memory_MUL_LH; |
| assign memory_MUL_LL = execute_to_memory_MUL_LL; |
| assign execute_RS1 = decode_to_execute_RS1; |
| assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; |
| always @(*) begin |
| _zz_decode_RS2_1 = memory_REGFILE_WRITE_DATA; |
| if(memory_arbitration_isValid) begin |
| case(memory_SHIFT_CTRL) |
| ShiftCtrlEnum_SLL_1 : begin |
| _zz_decode_RS2_1 = _zz_decode_RS2_3; |
| end |
| ShiftCtrlEnum_SRL_1, ShiftCtrlEnum_SRA_1 : begin |
| _zz_decode_RS2_1 = memory_SHIFT_RIGHT; |
| end |
| default : begin |
| end |
| endcase |
| end |
| if(when_MulDivIterativePlugin_l128) begin |
| _zz_decode_RS2_1 = memory_DivPlugin_div_result; |
| end |
| end |
| |
| assign memory_SHIFT_CTRL = _zz_memory_SHIFT_CTRL; |
| assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL; |
| assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; |
| assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; |
| assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; |
| assign _zz_decode_SRC2 = decode_PC; |
| assign _zz_decode_SRC2_1 = decode_RS2; |
| assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL; |
| assign _zz_decode_SRC1 = decode_RS1; |
| assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL; |
| assign decode_SRC_USE_SUB_LESS = _zz_decode_IS_SFENCE_VMA2[3]; |
| assign decode_SRC_ADD_ZERO = _zz_decode_IS_SFENCE_VMA2[20]; |
| assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; |
| assign execute_SRC_LESS = execute_SrcPlugin_less; |
| assign execute_ALU_CTRL = _zz_execute_ALU_CTRL; |
| assign execute_SRC2 = decode_to_execute_SRC2; |
| assign execute_SRC1 = decode_to_execute_SRC1; |
| assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL; |
| assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION; |
| assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID; |
| always @(*) begin |
| _zz_1 = 1'b0; |
| if(lastStageRegFileWrite_valid) begin |
| _zz_1 = 1'b1; |
| end |
| end |
| |
| assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); |
| always @(*) begin |
| decode_REGFILE_WRITE_VALID = _zz_decode_IS_SFENCE_VMA2[10]; |
| if(when_RegFilePlugin_l63) begin |
| decode_REGFILE_WRITE_VALID = 1'b0; |
| end |
| end |
| |
| assign decode_LEGAL_INSTRUCTION = (|{((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00001073),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}}); |
| assign writeBack_IS_DBUS_SHARING = memory_to_writeBack_IS_DBUS_SHARING; |
| assign memory_IS_DBUS_SHARING = execute_to_memory_IS_DBUS_SHARING; |
| always @(*) begin |
| _zz_decode_RS2_2 = writeBack_REGFILE_WRITE_DATA; |
| if(when_DBusCachedPlugin_l488) begin |
| _zz_decode_RS2_2 = writeBack_DBusCachedPlugin_rspFormated; |
| end |
| if(when_MulPlugin_l147) begin |
| case(switch_MulPlugin_l148) |
| 2'b00 : begin |
| _zz_decode_RS2_2 = _zz__zz_decode_RS2_2; |
| end |
| default : begin |
| _zz_decode_RS2_2 = _zz__zz_decode_RS2_2_1; |
| end |
| endcase |
| end |
| end |
| |
| assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR; |
| assign writeBack_MEMORY_STORE_DATA_RF = memory_to_writeBack_MEMORY_STORE_DATA_RF; |
| assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; |
| assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; |
| assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; |
| assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; |
| assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY; |
| assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT; |
| assign execute_RS2 = decode_to_execute_RS2; |
| assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR; |
| assign execute_SRC_ADD = execute_SrcPlugin_addSub; |
| assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; |
| assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; |
| assign decode_MEMORY_ENABLE = _zz_decode_IS_SFENCE_VMA2[4]; |
| assign decode_FLUSH_ALL = _zz_decode_IS_SFENCE_VMA2[0]; |
| always @(*) begin |
| IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; |
| if(when_IBusCachedPlugin_l256) begin |
| IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; |
| end |
| end |
| |
| always @(*) begin |
| IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; |
| if(when_IBusCachedPlugin_l250) begin |
| IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; |
| end |
| end |
| |
| always @(*) begin |
| IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; |
| if(when_IBusCachedPlugin_l244) begin |
| IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; |
| end |
| end |
| |
| always @(*) begin |
| IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; |
| if(when_IBusCachedPlugin_l239) begin |
| IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; |
| end |
| end |
| |
| assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; |
| always @(*) begin |
| _zz_execute_to_memory_FORMAL_PC_NEXT = execute_FORMAL_PC_NEXT; |
| if(BranchPlugin_jumpInterface_valid) begin |
| _zz_execute_to_memory_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload; |
| end |
| end |
| |
| assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; |
| assign writeBack_PC = memory_to_writeBack_PC; |
| assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; |
| always @(*) begin |
| decode_arbitration_haltItself = 1'b0; |
| if(when_DBusCachedPlugin_l307) begin |
| decode_arbitration_haltItself = 1'b1; |
| end |
| case(switch_Fetcher_l362) |
| 3'b010 : begin |
| decode_arbitration_haltItself = 1'b1; |
| end |
| default : begin |
| end |
| endcase |
| end |
| |
| always @(*) begin |
| decode_arbitration_haltByOther = 1'b0; |
| if(MmuPlugin_dBusAccess_cmd_valid) begin |
| decode_arbitration_haltByOther = 1'b1; |
| end |
| if(when_HazardSimplePlugin_l113) begin |
| decode_arbitration_haltByOther = 1'b1; |
| end |
| if(CsrPlugin_pipelineLiberator_active) begin |
| decode_arbitration_haltByOther = 1'b1; |
| end |
| if(when_CsrPlugin_l1116) begin |
| decode_arbitration_haltByOther = 1'b1; |
| end |
| end |
| |
| always @(*) begin |
| decode_arbitration_removeIt = 1'b0; |
| if(_zz_when) begin |
| decode_arbitration_removeIt = 1'b1; |
| end |
| if(decode_arbitration_isFlushed) begin |
| decode_arbitration_removeIt = 1'b1; |
| end |
| end |
| |
| assign decode_arbitration_flushIt = 1'b0; |
| always @(*) begin |
| decode_arbitration_flushNext = 1'b0; |
| if(_zz_when) begin |
| decode_arbitration_flushNext = 1'b1; |
| end |
| end |
| |
| always @(*) begin |
| execute_arbitration_haltItself = 1'b0; |
| if(when_DBusCachedPlugin_l347) begin |
| execute_arbitration_haltItself = 1'b1; |
| end |
| if(when_CsrPlugin_l1180) begin |
| if(execute_CsrPlugin_blockedBySideEffects) begin |
| execute_arbitration_haltItself = 1'b1; |
| end |
| end |
| end |
| |
| always @(*) begin |
| execute_arbitration_haltByOther = 1'b0; |
| if(when_DBusCachedPlugin_l363) begin |
| execute_arbitration_haltByOther = 1'b1; |
| end |
| if(when_DebugPlugin_l295) begin |
| execute_arbitration_haltByOther = 1'b1; |
| end |
| end |
| |
| always @(*) begin |
| execute_arbitration_removeIt = 1'b0; |
| if(BranchPlugin_branchExceptionPort_valid) begin |
| execute_arbitration_removeIt = 1'b1; |
| end |
| if(execute_arbitration_isFlushed) begin |
| execute_arbitration_removeIt = 1'b1; |
| end |
| end |
| |
| always @(*) begin |
| execute_arbitration_flushIt = 1'b0; |
| if(when_DebugPlugin_l295) begin |
| if(when_DebugPlugin_l298) begin |
| execute_arbitration_flushIt = 1'b1; |
| end |
| end |
| end |
| |
| always @(*) begin |
| execute_arbitration_flushNext = 1'b0; |
| if(when_DebugPlugin_l295) begin |
| if(when_DebugPlugin_l298) begin |
| execute_arbitration_flushNext = 1'b1; |
| end |
| end |
| if(BranchPlugin_branchExceptionPort_valid) begin |
| execute_arbitration_flushNext = 1'b1; |
| end |
| if(BranchPlugin_jumpInterface_valid) begin |
| execute_arbitration_flushNext = 1'b1; |
| end |
| end |
| |
| always @(*) begin |
| memory_arbitration_haltItself = 1'b0; |
| if(when_MulDivIterativePlugin_l128) begin |
| if(when_MulDivIterativePlugin_l129) begin |
| memory_arbitration_haltItself = 1'b1; |
| end |
| end |
| end |
| |
| assign memory_arbitration_haltByOther = 1'b0; |
| always @(*) begin |
| memory_arbitration_removeIt = 1'b0; |
| if(memory_arbitration_isFlushed) begin |
| memory_arbitration_removeIt = 1'b1; |
| end |
| end |
| |
| assign memory_arbitration_flushIt = 1'b0; |
| assign memory_arbitration_flushNext = 1'b0; |
| always @(*) begin |
| writeBack_arbitration_haltItself = 1'b0; |
| if(when_DBusCachedPlugin_l462) begin |
| writeBack_arbitration_haltItself = 1'b1; |
| end |
| end |
| |
| assign writeBack_arbitration_haltByOther = 1'b0; |
| always @(*) begin |
| writeBack_arbitration_removeIt = 1'b0; |
| if(DBusCachedPlugin_exceptionBus_valid) begin |
| writeBack_arbitration_removeIt = 1'b1; |
| end |
| if(writeBack_arbitration_isFlushed) begin |
| writeBack_arbitration_removeIt = 1'b1; |
| end |
| end |
| |
| always @(*) begin |
| writeBack_arbitration_flushIt = 1'b0; |
| if(DBusCachedPlugin_redoBranch_valid) begin |
| writeBack_arbitration_flushIt = 1'b1; |
| end |
| end |
| |
| always @(*) begin |
| writeBack_arbitration_flushNext = 1'b0; |
| if(DBusCachedPlugin_redoBranch_valid) begin |
| writeBack_arbitration_flushNext = 1'b1; |
| end |
| if(DBusCachedPlugin_exceptionBus_valid) begin |
| writeBack_arbitration_flushNext = 1'b1; |
| end |
| if(when_CsrPlugin_l1019) begin |
| writeBack_arbitration_flushNext = 1'b1; |
| end |
| if(when_CsrPlugin_l1064) begin |
| writeBack_arbitration_flushNext = 1'b1; |
| end |
| end |
| |
| assign lastStageInstruction = writeBack_INSTRUCTION; |
| assign lastStagePc = writeBack_PC; |
| assign lastStageIsValid = writeBack_arbitration_isValid; |
| assign lastStageIsFiring = writeBack_arbitration_isFiring; |
| always @(*) begin |
| IBusCachedPlugin_fetcherHalt = 1'b0; |
| if(when_DebugPlugin_l295) begin |
| if(when_DebugPlugin_l298) begin |
| IBusCachedPlugin_fetcherHalt = 1'b1; |
| end |
| end |
| if(DebugPlugin_haltIt) begin |
| IBusCachedPlugin_fetcherHalt = 1'b1; |
| end |
| if(when_DebugPlugin_l311) begin |
| IBusCachedPlugin_fetcherHalt = 1'b1; |
| end |
| if(when_CsrPlugin_l922) begin |
| IBusCachedPlugin_fetcherHalt = 1'b1; |
| end |
| if(when_CsrPlugin_l1019) begin |
| IBusCachedPlugin_fetcherHalt = 1'b1; |
| end |
| if(when_CsrPlugin_l1064) begin |
| IBusCachedPlugin_fetcherHalt = 1'b1; |
| end |
| end |
| |
| always @(*) begin |
| IBusCachedPlugin_incomingInstruction = 1'b0; |
| if(when_Fetcher_l240) begin |
| IBusCachedPlugin_incomingInstruction = 1'b1; |
| end |
| end |
| |
| always @(*) begin |
| _zz_when_DBusCachedPlugin_l390 = 1'b0; |
| if(DebugPlugin_godmode) begin |
| _zz_when_DBusCachedPlugin_l390 = 1'b1; |
| end |
| end |
| |
| assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0; |
| assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit; |
| assign CsrPlugin_inWfi = 1'b0; |
| always @(*) begin |
| CsrPlugin_thirdPartyWake = 1'b0; |
| if(DebugPlugin_haltIt) begin |
| CsrPlugin_thirdPartyWake = 1'b1; |
| end |
| end |
| |
| always @(*) begin |
| CsrPlugin_jumpInterface_valid = 1'b0; |
| if(when_CsrPlugin_l1019) begin |
| CsrPlugin_jumpInterface_valid = 1'b1; |
| end |
| if(when_CsrPlugin_l1064) begin |
| CsrPlugin_jumpInterface_valid = 1'b1; |
| end |
| end |
| |
| always @(*) begin |
| CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; |
| if(when_CsrPlugin_l1019) begin |
| CsrPlugin_jumpInterface_payload = (((CsrPlugin_xtvec_mode == 2'b00) || CsrPlugin_hadException) ? {CsrPlugin_xtvec_base,2'b00} : {_zz_CsrPlugin_jumpInterface_payload,2'b00}); |
| end |
| if(when_CsrPlugin_l1064) begin |
| case(switch_CsrPlugin_l1068) |
| 2'b11 : begin |
| CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; |
| end |
| default : begin |
| end |
| endcase |
| end |
| end |
| |
| always @(*) begin |
| CsrPlugin_forceMachineWire = 1'b0; |
| if(DebugPlugin_godmode) begin |
| CsrPlugin_forceMachineWire = 1'b1; |
| end |
| end |
| |
| always @(*) begin |
| CsrPlugin_allowInterrupts = 1'b1; |
| if(when_DebugPlugin_l327) begin |
| CsrPlugin_allowInterrupts = 1'b0; |
| end |
| end |
| |
| always @(*) begin |
| CsrPlugin_allowException = 1'b1; |
| if(DebugPlugin_godmode) begin |
| CsrPlugin_allowException = 1'b0; |
| end |
| end |
| |
| always @(*) begin |
| CsrPlugin_allowEbreakException = 1'b1; |
| if(DebugPlugin_allowEBreak) begin |
| CsrPlugin_allowEbreakException = 1'b0; |
| end |
| end |
| |
| assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); |
| assign IBusCachedPlugin_jump_pcLoad_valid = ({BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}} != 3'b000); |
| assign _zz_IBusCachedPlugin_jump_pcLoad_payload = {BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}; |
| assign _zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload & (~ _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1)); |
| assign _zz_IBusCachedPlugin_jump_pcLoad_payload_2 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[1]; |
| assign _zz_IBusCachedPlugin_jump_pcLoad_payload_3 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[2]; |
| assign IBusCachedPlugin_jump_pcLoad_payload = _zz_IBusCachedPlugin_jump_pcLoad_payload_4; |
| always @(*) begin |
| IBusCachedPlugin_fetchPc_correction = 1'b0; |
| if(IBusCachedPlugin_fetchPc_redo_valid) begin |
| IBusCachedPlugin_fetchPc_correction = 1'b1; |
| end |
| if(IBusCachedPlugin_jump_pcLoad_valid) begin |
| IBusCachedPlugin_fetchPc_correction = 1'b1; |
| end |
| end |
| |
| assign IBusCachedPlugin_fetchPc_output_fire = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); |
| assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); |
| always @(*) begin |
| IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; |
| if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin |
| IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; |
| end |
| end |
| |
| assign when_Fetcher_l131 = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate); |
| assign IBusCachedPlugin_fetchPc_output_fire_1 = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); |
| assign when_Fetcher_l131_1 = ((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready); |
| always @(*) begin |
| IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_IBusCachedPlugin_fetchPc_pc); |
| if(IBusCachedPlugin_fetchPc_redo_valid) begin |
| IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; |
| end |
| if(IBusCachedPlugin_jump_pcLoad_valid) begin |
| IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; |
| end |
| IBusCachedPlugin_fetchPc_pc[0] = 1'b0; |
| IBusCachedPlugin_fetchPc_pc[1] = 1'b0; |
| end |
| |
| always @(*) begin |
| IBusCachedPlugin_fetchPc_flushed = 1'b0; |
| if(IBusCachedPlugin_fetchPc_redo_valid) begin |
| IBusCachedPlugin_fetchPc_flushed = 1'b1; |
| end |
| if(IBusCachedPlugin_jump_pcLoad_valid) begin |
| IBusCachedPlugin_fetchPc_flushed = 1'b1; |
| end |
| end |
| |
| assign when_Fetcher_l158 = (IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)); |
| assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); |
| assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; |
| always @(*) begin |
| IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; |
| if(IBusCachedPlugin_rsp_redoFetch) begin |
| IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; |
| end |
| end |
| |
| assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; |
| assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; |
| assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; |
| always @(*) begin |
| IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; |
| if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt) begin |
| IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; |
| end |
| end |
| |
| assign _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready = (! IBusCachedPlugin_iBusRsp_stages_0_halt); |
| assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); |
| assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); |
| assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; |
| always @(*) begin |
| IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; |
| if(IBusCachedPlugin_mmuBus_busy) begin |
| IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; |
| end |
| end |
| |
| assign _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready = (! IBusCachedPlugin_iBusRsp_stages_1_halt); |
| assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); |
| assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); |
| assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; |
| always @(*) begin |
| IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; |
| if(when_IBusCachedPlugin_l267) begin |
| IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; |
| end |
| end |
| |
| assign _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready = (! IBusCachedPlugin_iBusRsp_stages_2_halt); |
| assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); |
| assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); |
| assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; |
| assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; |
| assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; |
| assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); |
| assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; |
| assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); |
| assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; |
| assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; |
| assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; |
| assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid)) || IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready); |
| assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; |
| assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; |
| assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; |
| assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready = IBusCachedPlugin_iBusRsp_stages_2_input_ready; |
| assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; |
| always @(*) begin |
| IBusCachedPlugin_iBusRsp_readyForError = 1'b1; |
| if(when_Fetcher_l320) begin |
| IBusCachedPlugin_iBusRsp_readyForError = 1'b0; |
| end |
| end |
| |
| assign when_Fetcher_l240 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid); |
| assign when_Fetcher_l320 = (! IBusCachedPlugin_pcValids_0); |
| assign when_Fetcher_l329 = (! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)); |
| assign when_Fetcher_l329_1 = (! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)); |
| assign when_Fetcher_l329_2 = (! execute_arbitration_isStuck); |
| assign when_Fetcher_l329_3 = (! memory_arbitration_isStuck); |
| assign when_Fetcher_l329_4 = (! writeBack_arbitration_isStuck); |
| assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1; |
| assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; |
| assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; |
| assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; |
| assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); |
| always @(*) begin |
| decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; |
| case(switch_Fetcher_l362) |
| 3'b010 : begin |
| decode_arbitration_isValid = 1'b1; |
| end |
| 3'b011 : begin |
| decode_arbitration_isValid = 1'b1; |
| end |
| default : begin |
| end |
| endcase |
| end |
| |
| assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; |
| always @(*) begin |
| iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; |
| iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; |
| end |
| |
| assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; |
| assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; |
| assign IBusCachedPlugin_cache_io_cpu_prefetch_isValid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); |
| assign IBusCachedPlugin_cache_io_cpu_fetch_isValid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); |
| assign IBusCachedPlugin_cache_io_cpu_fetch_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); |
| assign IBusCachedPlugin_mmuBus_cmd_0_isValid = IBusCachedPlugin_cache_io_cpu_fetch_isValid; |
| assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); |
| assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; |
| assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; |
| assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); |
| assign IBusCachedPlugin_cache_io_cpu_decode_isValid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); |
| assign IBusCachedPlugin_cache_io_cpu_decode_isStuck = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); |
| assign IBusCachedPlugin_cache_io_cpu_decode_isUser = (CsrPlugin_privilege == 2'b00); |
| assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; |
| assign IBusCachedPlugin_rsp_issueDetected = 1'b0; |
| always @(*) begin |
| IBusCachedPlugin_rsp_redoFetch = 1'b0; |
| if(when_IBusCachedPlugin_l239) begin |
| IBusCachedPlugin_rsp_redoFetch = 1'b1; |
| end |
| if(when_IBusCachedPlugin_l250) begin |
| IBusCachedPlugin_rsp_redoFetch = 1'b1; |
| end |
| end |
| |
| always @(*) begin |
| IBusCachedPlugin_cache_io_cpu_fill_valid = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); |
| if(when_IBusCachedPlugin_l250) begin |
| IBusCachedPlugin_cache_io_cpu_fill_valid = 1'b1; |
| end |
| end |
| |
| always @(*) begin |
| IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; |
| if(when_IBusCachedPlugin_l244) begin |
| IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; |
| end |
| if(when_IBusCachedPlugin_l256) begin |
| IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; |
| end |
| end |
| |
| always @(*) begin |
| IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; |
| if(when_IBusCachedPlugin_l244) begin |
| IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; |
| end |
| if(when_IBusCachedPlugin_l256) begin |
| IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; |
| end |
| end |
| |
| assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; |
| assign when_IBusCachedPlugin_l239 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); |
| assign when_IBusCachedPlugin_l244 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); |
| assign when_IBusCachedPlugin_l250 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); |
| assign when_IBusCachedPlugin_l256 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); |
| assign when_IBusCachedPlugin_l267 = (IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt); |
| assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; |
| assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; |
| assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; |
| assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; |
| assign IBusCachedPlugin_cache_io_flush = (decode_arbitration_isValid && decode_FLUSH_ALL); |
| always @(*) begin |
| dataCache_1_io_mem_cmd_ready = dataCache_1_io_mem_cmd_m2sPipe_ready; |
| if(when_Stream_l342) begin |
| dataCache_1_io_mem_cmd_ready = 1'b1; |
| end |
| end |
| |
| assign when_Stream_l342 = (! dataCache_1_io_mem_cmd_m2sPipe_valid); |
| assign dataCache_1_io_mem_cmd_m2sPipe_valid = dataCache_1_io_mem_cmd_rValid; |
| assign dataCache_1_io_mem_cmd_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_rData_wr; |
| assign dataCache_1_io_mem_cmd_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_rData_uncached; |
| assign dataCache_1_io_mem_cmd_m2sPipe_payload_address = dataCache_1_io_mem_cmd_rData_address; |
| assign dataCache_1_io_mem_cmd_m2sPipe_payload_data = dataCache_1_io_mem_cmd_rData_data; |
| assign dataCache_1_io_mem_cmd_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_rData_mask; |
| assign dataCache_1_io_mem_cmd_m2sPipe_payload_size = dataCache_1_io_mem_cmd_rData_size; |
| assign dataCache_1_io_mem_cmd_m2sPipe_payload_last = dataCache_1_io_mem_cmd_rData_last; |
| assign dBus_cmd_valid = dataCache_1_io_mem_cmd_m2sPipe_valid; |
| assign dataCache_1_io_mem_cmd_m2sPipe_ready = dBus_cmd_ready; |
| assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_m2sPipe_payload_wr; |
| assign dBus_cmd_payload_uncached = dataCache_1_io_mem_cmd_m2sPipe_payload_uncached; |
| assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_m2sPipe_payload_address; |
| assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_m2sPipe_payload_data; |
| assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_m2sPipe_payload_mask; |
| assign dBus_cmd_payload_size = dataCache_1_io_mem_cmd_m2sPipe_payload_size; |
| assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_m2sPipe_payload_last; |
| assign when_DBusCachedPlugin_l307 = ((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE); |
| assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; |
| always @(*) begin |
| dataCache_1_io_cpu_execute_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); |
| if(MmuPlugin_dBusAccess_cmd_valid) begin |
| if(when_DBusCachedPlugin_l502) begin |
| if(when_DBusCachedPlugin_l503) begin |
| dataCache_1_io_cpu_execute_isValid = 1'b1; |
| end |
| end |
| end |
| end |
| |
| always @(*) begin |
| dataCache_1_io_cpu_execute_address = execute_SRC_ADD; |
| if(MmuPlugin_dBusAccess_cmd_valid) begin |
| if(when_DBusCachedPlugin_l502) begin |
| dataCache_1_io_cpu_execute_address = MmuPlugin_dBusAccess_cmd_payload_address; |
| end |
| end |
| end |
| |
| always @(*) begin |
| dataCache_1_io_cpu_execute_args_wr = execute_MEMORY_WR; |
| if(MmuPlugin_dBusAccess_cmd_valid) begin |
| if(when_DBusCachedPlugin_l502) begin |
| dataCache_1_io_cpu_execute_args_wr = 1'b0; |
| end |
| end |
| end |
| |
| always @(*) begin |
| case(execute_DBusCachedPlugin_size) |
| 2'b00 : begin |
| _zz_execute_MEMORY_STORE_DATA_RF = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; |
| end |
| 2'b01 : begin |
| _zz_execute_MEMORY_STORE_DATA_RF = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; |
| end |
| default : begin |
| _zz_execute_MEMORY_STORE_DATA_RF = execute_RS2[31 : 0]; |
| end |
| endcase |
| end |
| |
| always @(*) begin |
| dataCache_1_io_cpu_execute_args_size = execute_DBusCachedPlugin_size; |
| if(MmuPlugin_dBusAccess_cmd_valid) begin |
| if(when_DBusCachedPlugin_l502) begin |
| dataCache_1_io_cpu_execute_args_size = MmuPlugin_dBusAccess_cmd_payload_size; |
| end |
| end |
| end |
| |
| assign dataCache_1_io_cpu_flush_valid = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); |
| assign dataCache_1_io_cpu_flush_isStall = (dataCache_1_io_cpu_flush_valid && (! dataCache_1_io_cpu_flush_ready)); |
| assign when_DBusCachedPlugin_l347 = (dataCache_1_io_cpu_flush_isStall || dataCache_1_io_cpu_execute_haltIt); |
| assign when_DBusCachedPlugin_l363 = (dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid); |
| always @(*) begin |
| dataCache_1_io_cpu_memory_isValid = (memory_arbitration_isValid && memory_MEMORY_ENABLE); |
| if(memory_IS_DBUS_SHARING) begin |
| dataCache_1_io_cpu_memory_isValid = 1'b1; |
| end |
| end |
| |
| assign dataCache_1_io_cpu_memory_address = memory_REGFILE_WRITE_DATA; |
| assign DBusCachedPlugin_mmuBus_cmd_0_isValid = dataCache_1_io_cpu_memory_isValid; |
| assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; |
| assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = dataCache_1_io_cpu_memory_address; |
| always @(*) begin |
| DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; |
| if(memory_IS_DBUS_SHARING) begin |
| DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b1; |
| end |
| end |
| |
| assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); |
| always @(*) begin |
| dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_isIoAccess; |
| if(when_DBusCachedPlugin_l390) begin |
| dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = 1'b1; |
| end |
| end |
| |
| assign when_DBusCachedPlugin_l390 = (_zz_when_DBusCachedPlugin_l390 && (! dataCache_1_io_cpu_memory_isWrite)); |
| always @(*) begin |
| dataCache_1_io_cpu_writeBack_isValid = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); |
| if(writeBack_IS_DBUS_SHARING) begin |
| dataCache_1_io_cpu_writeBack_isValid = 1'b1; |
| end |
| if(writeBack_arbitration_haltByOther) begin |
| dataCache_1_io_cpu_writeBack_isValid = 1'b0; |
| end |
| end |
| |
| assign dataCache_1_io_cpu_writeBack_isUser = (CsrPlugin_privilege == 2'b00); |
| assign dataCache_1_io_cpu_writeBack_address = writeBack_REGFILE_WRITE_DATA; |
| assign dataCache_1_io_cpu_writeBack_storeData[31 : 0] = writeBack_MEMORY_STORE_DATA_RF; |
| always @(*) begin |
| DBusCachedPlugin_redoBranch_valid = 1'b0; |
| if(when_DBusCachedPlugin_l442) begin |
| if(dataCache_1_io_cpu_redo) begin |
| DBusCachedPlugin_redoBranch_valid = 1'b1; |
| end |
| end |
| end |
| |
| assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; |
| always @(*) begin |
| DBusCachedPlugin_exceptionBus_valid = 1'b0; |
| if(when_DBusCachedPlugin_l442) begin |
| if(dataCache_1_io_cpu_writeBack_accessError) begin |
| DBusCachedPlugin_exceptionBus_valid = 1'b1; |
| end |
| if(dataCache_1_io_cpu_writeBack_mmuException) begin |
| DBusCachedPlugin_exceptionBus_valid = 1'b1; |
| end |
| if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin |
| DBusCachedPlugin_exceptionBus_valid = 1'b1; |
| end |
| if(dataCache_1_io_cpu_redo) begin |
| DBusCachedPlugin_exceptionBus_valid = 1'b0; |
| end |
| end |
| end |
| |
| assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; |
| always @(*) begin |
| DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; |
| if(when_DBusCachedPlugin_l442) begin |
| if(dataCache_1_io_cpu_writeBack_accessError) begin |
| DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code}; |
| end |
| if(dataCache_1_io_cpu_writeBack_mmuException) begin |
| DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); |
| end |
| if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin |
| DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code_1}; |
| end |
| end |
| end |
| |
| assign when_DBusCachedPlugin_l442 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); |
| assign when_DBusCachedPlugin_l462 = (dataCache_1_io_cpu_writeBack_isValid && dataCache_1_io_cpu_writeBack_haltIt); |
| assign writeBack_DBusCachedPlugin_rspSplits_0 = dataCache_1_io_cpu_writeBack_data[7 : 0]; |
| assign writeBack_DBusCachedPlugin_rspSplits_1 = dataCache_1_io_cpu_writeBack_data[15 : 8]; |
| assign writeBack_DBusCachedPlugin_rspSplits_2 = dataCache_1_io_cpu_writeBack_data[23 : 16]; |
| assign writeBack_DBusCachedPlugin_rspSplits_3 = dataCache_1_io_cpu_writeBack_data[31 : 24]; |
| always @(*) begin |
| writeBack_DBusCachedPlugin_rspShifted[7 : 0] = _zz_writeBack_DBusCachedPlugin_rspShifted; |
| writeBack_DBusCachedPlugin_rspShifted[15 : 8] = _zz_writeBack_DBusCachedPlugin_rspShifted_2; |
| writeBack_DBusCachedPlugin_rspShifted[23 : 16] = writeBack_DBusCachedPlugin_rspSplits_2; |
| writeBack_DBusCachedPlugin_rspShifted[31 : 24] = writeBack_DBusCachedPlugin_rspSplits_3; |
| end |
| |
| assign writeBack_DBusCachedPlugin_rspRf = writeBack_DBusCachedPlugin_rspShifted[31 : 0]; |
| assign switch_Misc_l211 = writeBack_INSTRUCTION[13 : 12]; |
| assign _zz_writeBack_DBusCachedPlugin_rspFormated = (writeBack_DBusCachedPlugin_rspRf[7] && (! writeBack_INSTRUCTION[14])); |
| always @(*) begin |
| _zz_writeBack_DBusCachedPlugin_rspFormated_1[31] = _zz_writeBack_DBusCachedPlugin_rspFormated; |
| _zz_writeBack_DBusCachedPlugin_rspFormated_1[30] = _zz_writeBack_DBusCachedPlugin_rspFormated; |
| _zz_writeBack_DBusCachedPlugin_rspFormated_1[29] = _zz_writeBack_DBusCachedPlugin_rspFormated; |
| _zz_writeBack_DBusCachedPlugin_rspFormated_1[28] = _zz_writeBack_DBusCachedPlugin_rspFormated; |
| _zz_writeBack_DBusCachedPlugin_rspFormated_1[27] = _zz_writeBack_DBusCachedPlugin_rspFormated; |
| _zz_writeBack_DBusCachedPlugin_rspFormated_1[26] = _zz_writeBack_DBusCachedPlugin_rspFormated; |
| _zz_writeBack_DBusCachedPlugin_rspFormated_1[25] = _zz_writeBack_DBusCachedPlugin_rspFormated; |
| _zz_writeBack_DBusCachedPlugin_rspFormated_1[24] = _zz_writeBack_DBusCachedPlugin_rspFormated; |
| _zz_writeBack_DBusCachedPlugin_rspFormated_1[23] = _zz_writeBack_DBusCachedPlugin_rspFormated; |
| _zz_writeBack_DBusCachedPlugin_rspFormated_1[22] = _zz_writeBack_DBusCachedPlugin_rspFormated; |
| _zz_writeBack_DBusCachedPlugin_rspFormated_1[21] = _zz_writeBack_DBusCachedPlugin_rspFormated; |
| _zz_writeBack_DBusCachedPlugin_rspFormated_1[20] = _zz_writeBack_DBusCachedPlugin_rspFormated; |
| _zz_writeBack_DBusCachedPlugin_rspFormated_1[19] = _zz_writeBack_DBusCachedPlugin_rspFormated; |
| _zz_writeBack_DBusCachedPlugin_rspFormated_1[18] = _zz_writeBack_DBusCachedPlugin_rspFormated; |
| _zz_writeBack_DBusCachedPlugin_rspFormated_1[17] = _zz_writeBack_DBusCachedPlugin_rspFormated; |
| _zz_writeBack_DBusCachedPlugin_rspFormated_1[16] = _zz_writeBack_DBusCachedPlugin_rspFormated; |
| _zz_writeBack_DBusCachedPlugin_rspFormated_1[15] = _zz_writeBack_DBusCachedPlugin_rspFormated; |
| _zz_writeBack_DBusCachedPlugin_rspFormated_1[14] = _zz_writeBack_DBusCachedPlugin_rspFormated; |
| _zz_writeBack_DBusCachedPlugin_rspFormated_1[13] = _zz_writeBack_DBusCachedPlugin_rspFormated; |
| _zz_writeBack_DBusCachedPlugin_rspFormated_1[12] = _zz_writeBack_DBusCachedPlugin_rspFormated; |
| _zz_writeBack_DBusCachedPlugin_rspFormated_1[11] = _zz_writeBack_DBusCachedPlugin_rspFormated; |
| _zz_writeBack_DBusCachedPlugin_rspFormated_1[10] = _zz_writeBack_DBusCachedPlugin_rspFormated; |
| _zz_writeBack_DBusCachedPlugin_rspFormated_1[9] = _zz_writeBack_DBusCachedPlugin_rspFormated; |
| _zz_writeBack_DBusCachedPlugin_rspFormated_1[8] = _zz_writeBack_DBusCachedPlugin_rspFormated; |
| _zz_writeBack_DBusCachedPlugin_rspFormated_1[7 : 0] = writeBack_DBusCachedPlugin_rspRf[7 : 0]; |
| end |
| |
| assign _zz_writeBack_DBusCachedPlugin_rspFormated_2 = (writeBack_DBusCachedPlugin_rspRf[15] && (! writeBack_INSTRUCTION[14])); |
| always @(*) begin |
| _zz_writeBack_DBusCachedPlugin_rspFormated_3[31] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; |
| _zz_writeBack_DBusCachedPlugin_rspFormated_3[30] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; |
| _zz_writeBack_DBusCachedPlugin_rspFormated_3[29] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; |
| _zz_writeBack_DBusCachedPlugin_rspFormated_3[28] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; |
| _zz_writeBack_DBusCachedPlugin_rspFormated_3[27] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; |
| _zz_writeBack_DBusCachedPlugin_rspFormated_3[26] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; |
| _zz_writeBack_DBusCachedPlugin_rspFormated_3[25] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; |
| _zz_writeBack_DBusCachedPlugin_rspFormated_3[24] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; |
| _zz_writeBack_DBusCachedPlugin_rspFormated_3[23] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; |
| _zz_writeBack_DBusCachedPlugin_rspFormated_3[22] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; |
| _zz_writeBack_DBusCachedPlugin_rspFormated_3[21] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; |
| _zz_writeBack_DBusCachedPlugin_rspFormated_3[20] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; |
| _zz_writeBack_DBusCachedPlugin_rspFormated_3[19] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; |
| _zz_writeBack_DBusCachedPlugin_rspFormated_3[18] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; |
| _zz_writeBack_DBusCachedPlugin_rspFormated_3[17] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; |
| _zz_writeBack_DBusCachedPlugin_rspFormated_3[16] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; |
| _zz_writeBack_DBusCachedPlugin_rspFormated_3[15 : 0] = writeBack_DBusCachedPlugin_rspRf[15 : 0]; |
| end |
| |
| always @(*) begin |
| case(switch_Misc_l211) |
| 2'b00 : begin |
| writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_1; |
| end |
| 2'b01 : begin |
| writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_3; |
| end |
| default : begin |
| writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspRf; |
| end |
| endcase |
| end |
| |
| assign when_DBusCachedPlugin_l488 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); |
| always @(*) begin |
| MmuPlugin_dBusAccess_cmd_ready = 1'b0; |
| if(MmuPlugin_dBusAccess_cmd_valid) begin |
| if(when_DBusCachedPlugin_l502) begin |
| if(when_DBusCachedPlugin_l503) begin |
| MmuPlugin_dBusAccess_cmd_ready = (! execute_arbitration_isStuck); |
| end |
| end |
| end |
| end |
| |
| always @(*) begin |
| DBusCachedPlugin_forceDatapath = 1'b0; |
| if(MmuPlugin_dBusAccess_cmd_valid) begin |
| if(when_DBusCachedPlugin_l502) begin |
| DBusCachedPlugin_forceDatapath = 1'b1; |
| end |
| end |
| end |
| |
| assign when_DBusCachedPlugin_l502 = (! ({(writeBack_arbitration_isValid || CsrPlugin_exceptionPendings_3),{(memory_arbitration_isValid || CsrPlugin_exceptionPendings_2),(execute_arbitration_isValid || CsrPlugin_exceptionPendings_1)}} != 3'b000)); |
| assign when_DBusCachedPlugin_l503 = (! dataCache_1_io_cpu_execute_refilling); |
| assign MmuPlugin_dBusAccess_cmd_fire = (MmuPlugin_dBusAccess_cmd_valid && MmuPlugin_dBusAccess_cmd_ready); |
| assign MmuPlugin_dBusAccess_rsp_valid = ((writeBack_IS_DBUS_SHARING && (! dataCache_1_io_cpu_writeBack_isWrite)) && (dataCache_1_io_cpu_redo || (! dataCache_1_io_cpu_writeBack_haltIt))); |
| assign MmuPlugin_dBusAccess_rsp_payload_data = writeBack_DBusCachedPlugin_rspRf; |
| assign MmuPlugin_dBusAccess_rsp_payload_error = (dataCache_1_io_cpu_writeBack_unalignedAccess || dataCache_1_io_cpu_writeBack_accessError); |
| assign MmuPlugin_dBusAccess_rsp_payload_redo = dataCache_1_io_cpu_redo; |
| assign _zz_decode_IS_SFENCE_VMA2_1 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); |
| assign _zz_decode_IS_SFENCE_VMA2_2 = ((decode_INSTRUCTION & 32'h00000018) == 32'h0); |
| assign _zz_decode_IS_SFENCE_VMA2_3 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); |
| assign _zz_decode_IS_SFENCE_VMA2_4 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); |
| assign _zz_decode_IS_SFENCE_VMA2_5 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); |
| assign _zz_decode_IS_SFENCE_VMA2 = {(|((decode_INSTRUCTION & 32'h02003050) == 32'h02000050)),{(|{_zz_decode_IS_SFENCE_VMA2_4,(_zz__zz_decode_IS_SFENCE_VMA2 == _zz__zz_decode_IS_SFENCE_VMA2_1)}),{(|(_zz__zz_decode_IS_SFENCE_VMA2_2 == _zz__zz_decode_IS_SFENCE_VMA2_3)),{(|_zz__zz_decode_IS_SFENCE_VMA2_4),{(|_zz__zz_decode_IS_SFENCE_VMA2_5),{_zz__zz_decode_IS_SFENCE_VMA2_8,{_zz__zz_decode_IS_SFENCE_VMA2_10,_zz__zz_decode_IS_SFENCE_VMA2_11}}}}}}}; |
| assign _zz_decode_SRC1_CTRL_2 = _zz_decode_IS_SFENCE_VMA2[2 : 1]; |
| assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2; |
| assign _zz_decode_ALU_CTRL_2 = _zz_decode_IS_SFENCE_VMA2[7 : 6]; |
| assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2; |
| assign _zz_decode_SRC2_CTRL_2 = _zz_decode_IS_SFENCE_VMA2[9 : 8]; |
| assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2; |
| assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_IS_SFENCE_VMA2[19 : 18]; |
| assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2; |
| assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_IS_SFENCE_VMA2[22 : 21]; |
| assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2; |
| assign _zz_decode_ENV_CTRL_2 = _zz_decode_IS_SFENCE_VMA2[29 : 29]; |
| assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_2; |
| assign _zz_decode_BRANCH_CTRL_2 = _zz_decode_IS_SFENCE_VMA2[31 : 30]; |
| assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL_2; |
| assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); |
| assign decodeExceptionPort_payload_code = 4'b0010; |
| assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; |
| assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0); |
| assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; |
| assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; |
| assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0; |
| assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1; |
| always @(*) begin |
| lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); |
| if(_zz_2) begin |
| lastStageRegFileWrite_valid = 1'b1; |
| end |
| end |
| |
| always @(*) begin |
| lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; |
| if(_zz_2) begin |
| lastStageRegFileWrite_payload_address = 5'h0; |
| end |
| end |
| |
| always @(*) begin |
| lastStageRegFileWrite_payload_data = _zz_decode_RS2_2; |
| if(_zz_2) begin |
| lastStageRegFileWrite_payload_data = 32'h0; |
| end |
| end |
| |
| always @(*) begin |
| case(execute_ALU_BITWISE_CTRL) |
| AluBitwiseCtrlEnum_AND_1 : begin |
| execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); |
| end |
| AluBitwiseCtrlEnum_OR_1 : begin |
| execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); |
| end |
| default : begin |
| execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); |
| end |
| endcase |
| end |
| |
| always @(*) begin |
| case(execute_ALU_CTRL) |
| AluCtrlEnum_BITWISE : begin |
| _zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise; |
| end |
| AluCtrlEnum_SLT_SLTU : begin |
| _zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA}; |
| end |
| default : begin |
| _zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB; |
| end |
| endcase |
| end |
| |
| always @(*) begin |
| case(decode_SRC1_CTRL) |
| Src1CtrlEnum_RS : begin |
| _zz_decode_SRC1_1 = _zz_decode_SRC1; |
| end |
| Src1CtrlEnum_PC_INCREMENT : begin |
| _zz_decode_SRC1_1 = {29'd0, _zz__zz_decode_SRC1_1}; |
| end |
| Src1CtrlEnum_IMU : begin |
| _zz_decode_SRC1_1 = {decode_INSTRUCTION[31 : 12],12'h0}; |
| end |
| default : begin |
| _zz_decode_SRC1_1 = {27'd0, _zz__zz_decode_SRC1_1_1}; |
| end |
| endcase |
| end |
| |
| assign _zz_decode_SRC2_2 = decode_INSTRUCTION[31]; |
| always @(*) begin |
| _zz_decode_SRC2_3[19] = _zz_decode_SRC2_2; |
| _zz_decode_SRC2_3[18] = _zz_decode_SRC2_2; |
| _zz_decode_SRC2_3[17] = _zz_decode_SRC2_2; |
| _zz_decode_SRC2_3[16] = _zz_decode_SRC2_2; |
| _zz_decode_SRC2_3[15] = _zz_decode_SRC2_2; |
| _zz_decode_SRC2_3[14] = _zz_decode_SRC2_2; |
| _zz_decode_SRC2_3[13] = _zz_decode_SRC2_2; |
| _zz_decode_SRC2_3[12] = _zz_decode_SRC2_2; |
| _zz_decode_SRC2_3[11] = _zz_decode_SRC2_2; |
| _zz_decode_SRC2_3[10] = _zz_decode_SRC2_2; |
| _zz_decode_SRC2_3[9] = _zz_decode_SRC2_2; |
| _zz_decode_SRC2_3[8] = _zz_decode_SRC2_2; |
| _zz_decode_SRC2_3[7] = _zz_decode_SRC2_2; |
| _zz_decode_SRC2_3[6] = _zz_decode_SRC2_2; |
| _zz_decode_SRC2_3[5] = _zz_decode_SRC2_2; |
| _zz_decode_SRC2_3[4] = _zz_decode_SRC2_2; |
| _zz_decode_SRC2_3[3] = _zz_decode_SRC2_2; |
| _zz_decode_SRC2_3[2] = _zz_decode_SRC2_2; |
| _zz_decode_SRC2_3[1] = _zz_decode_SRC2_2; |
| _zz_decode_SRC2_3[0] = _zz_decode_SRC2_2; |
| end |
| |
| assign _zz_decode_SRC2_4 = _zz__zz_decode_SRC2_4[11]; |
| always @(*) begin |
| _zz_decode_SRC2_5[19] = _zz_decode_SRC2_4; |
| _zz_decode_SRC2_5[18] = _zz_decode_SRC2_4; |
| _zz_decode_SRC2_5[17] = _zz_decode_SRC2_4; |
| _zz_decode_SRC2_5[16] = _zz_decode_SRC2_4; |
| _zz_decode_SRC2_5[15] = _zz_decode_SRC2_4; |
| _zz_decode_SRC2_5[14] = _zz_decode_SRC2_4; |
| _zz_decode_SRC2_5[13] = _zz_decode_SRC2_4; |
| _zz_decode_SRC2_5[12] = _zz_decode_SRC2_4; |
| _zz_decode_SRC2_5[11] = _zz_decode_SRC2_4; |
| _zz_decode_SRC2_5[10] = _zz_decode_SRC2_4; |
| _zz_decode_SRC2_5[9] = _zz_decode_SRC2_4; |
| _zz_decode_SRC2_5[8] = _zz_decode_SRC2_4; |
| _zz_decode_SRC2_5[7] = _zz_decode_SRC2_4; |
| _zz_decode_SRC2_5[6] = _zz_decode_SRC2_4; |
| _zz_decode_SRC2_5[5] = _zz_decode_SRC2_4; |
| _zz_decode_SRC2_5[4] = _zz_decode_SRC2_4; |
| _zz_decode_SRC2_5[3] = _zz_decode_SRC2_4; |
| _zz_decode_SRC2_5[2] = _zz_decode_SRC2_4; |
| _zz_decode_SRC2_5[1] = _zz_decode_SRC2_4; |
| _zz_decode_SRC2_5[0] = _zz_decode_SRC2_4; |
| end |
| |
| always @(*) begin |
| case(decode_SRC2_CTRL) |
| Src2CtrlEnum_RS : begin |
| _zz_decode_SRC2_6 = _zz_decode_SRC2_1; |
| end |
| Src2CtrlEnum_IMI : begin |
| _zz_decode_SRC2_6 = {_zz_decode_SRC2_3,decode_INSTRUCTION[31 : 20]}; |
| end |
| Src2CtrlEnum_IMS : begin |
| _zz_decode_SRC2_6 = {_zz_decode_SRC2_5,{decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}}; |
| end |
| default : begin |
| _zz_decode_SRC2_6 = _zz_decode_SRC2; |
| end |
| endcase |
| end |
| |
| always @(*) begin |
| execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub; |
| if(execute_SRC2_FORCE_ZERO) begin |
| execute_SrcPlugin_addSub = execute_SRC1; |
| end |
| end |
| |
| assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); |
| assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; |
| always @(*) begin |
| _zz_execute_FullBarrelShifterPlugin_reversed[0] = execute_SRC1[31]; |
| _zz_execute_FullBarrelShifterPlugin_reversed[1] = execute_SRC1[30]; |
| _zz_execute_FullBarrelShifterPlugin_reversed[2] = execute_SRC1[29]; |
| _zz_execute_FullBarrelShifterPlugin_reversed[3] = execute_SRC1[28]; |
| _zz_execute_FullBarrelShifterPlugin_reversed[4] = execute_SRC1[27]; |
| _zz_execute_FullBarrelShifterPlugin_reversed[5] = execute_SRC1[26]; |
| _zz_execute_FullBarrelShifterPlugin_reversed[6] = execute_SRC1[25]; |
| _zz_execute_FullBarrelShifterPlugin_reversed[7] = execute_SRC1[24]; |
| _zz_execute_FullBarrelShifterPlugin_reversed[8] = execute_SRC1[23]; |
| _zz_execute_FullBarrelShifterPlugin_reversed[9] = execute_SRC1[22]; |
| _zz_execute_FullBarrelShifterPlugin_reversed[10] = execute_SRC1[21]; |
| _zz_execute_FullBarrelShifterPlugin_reversed[11] = execute_SRC1[20]; |
| _zz_execute_FullBarrelShifterPlugin_reversed[12] = execute_SRC1[19]; |
| _zz_execute_FullBarrelShifterPlugin_reversed[13] = execute_SRC1[18]; |
| _zz_execute_FullBarrelShifterPlugin_reversed[14] = execute_SRC1[17]; |
| _zz_execute_FullBarrelShifterPlugin_reversed[15] = execute_SRC1[16]; |
| _zz_execute_FullBarrelShifterPlugin_reversed[16] = execute_SRC1[15]; |
| _zz_execute_FullBarrelShifterPlugin_reversed[17] = execute_SRC1[14]; |
| _zz_execute_FullBarrelShifterPlugin_reversed[18] = execute_SRC1[13]; |
| _zz_execute_FullBarrelShifterPlugin_reversed[19] = execute_SRC1[12]; |
| _zz_execute_FullBarrelShifterPlugin_reversed[20] = execute_SRC1[11]; |
| _zz_execute_FullBarrelShifterPlugin_reversed[21] = execute_SRC1[10]; |
| _zz_execute_FullBarrelShifterPlugin_reversed[22] = execute_SRC1[9]; |
| _zz_execute_FullBarrelShifterPlugin_reversed[23] = execute_SRC1[8]; |
| _zz_execute_FullBarrelShifterPlugin_reversed[24] = execute_SRC1[7]; |
| _zz_execute_FullBarrelShifterPlugin_reversed[25] = execute_SRC1[6]; |
| _zz_execute_FullBarrelShifterPlugin_reversed[26] = execute_SRC1[5]; |
| _zz_execute_FullBarrelShifterPlugin_reversed[27] = execute_SRC1[4]; |
| _zz_execute_FullBarrelShifterPlugin_reversed[28] = execute_SRC1[3]; |
| _zz_execute_FullBarrelShifterPlugin_reversed[29] = execute_SRC1[2]; |
| _zz_execute_FullBarrelShifterPlugin_reversed[30] = execute_SRC1[1]; |
| _zz_execute_FullBarrelShifterPlugin_reversed[31] = execute_SRC1[0]; |
| end |
| |
| assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == ShiftCtrlEnum_SLL_1) ? _zz_execute_FullBarrelShifterPlugin_reversed : execute_SRC1); |
| always @(*) begin |
| _zz_decode_RS2_3[0] = memory_SHIFT_RIGHT[31]; |
| _zz_decode_RS2_3[1] = memory_SHIFT_RIGHT[30]; |
| _zz_decode_RS2_3[2] = memory_SHIFT_RIGHT[29]; |
| _zz_decode_RS2_3[3] = memory_SHIFT_RIGHT[28]; |
| _zz_decode_RS2_3[4] = memory_SHIFT_RIGHT[27]; |
| _zz_decode_RS2_3[5] = memory_SHIFT_RIGHT[26]; |
| _zz_decode_RS2_3[6] = memory_SHIFT_RIGHT[25]; |
| _zz_decode_RS2_3[7] = memory_SHIFT_RIGHT[24]; |
| _zz_decode_RS2_3[8] = memory_SHIFT_RIGHT[23]; |
| _zz_decode_RS2_3[9] = memory_SHIFT_RIGHT[22]; |
| _zz_decode_RS2_3[10] = memory_SHIFT_RIGHT[21]; |
| _zz_decode_RS2_3[11] = memory_SHIFT_RIGHT[20]; |
| _zz_decode_RS2_3[12] = memory_SHIFT_RIGHT[19]; |
| _zz_decode_RS2_3[13] = memory_SHIFT_RIGHT[18]; |
| _zz_decode_RS2_3[14] = memory_SHIFT_RIGHT[17]; |
| _zz_decode_RS2_3[15] = memory_SHIFT_RIGHT[16]; |
| _zz_decode_RS2_3[16] = memory_SHIFT_RIGHT[15]; |
| _zz_decode_RS2_3[17] = memory_SHIFT_RIGHT[14]; |
| _zz_decode_RS2_3[18] = memory_SHIFT_RIGHT[13]; |
| _zz_decode_RS2_3[19] = memory_SHIFT_RIGHT[12]; |
| _zz_decode_RS2_3[20] = memory_SHIFT_RIGHT[11]; |
| _zz_decode_RS2_3[21] = memory_SHIFT_RIGHT[10]; |
| _zz_decode_RS2_3[22] = memory_SHIFT_RIGHT[9]; |
| _zz_decode_RS2_3[23] = memory_SHIFT_RIGHT[8]; |
| _zz_decode_RS2_3[24] = memory_SHIFT_RIGHT[7]; |
| _zz_decode_RS2_3[25] = memory_SHIFT_RIGHT[6]; |
| _zz_decode_RS2_3[26] = memory_SHIFT_RIGHT[5]; |
| _zz_decode_RS2_3[27] = memory_SHIFT_RIGHT[4]; |
| _zz_decode_RS2_3[28] = memory_SHIFT_RIGHT[3]; |
| _zz_decode_RS2_3[29] = memory_SHIFT_RIGHT[2]; |
| _zz_decode_RS2_3[30] = memory_SHIFT_RIGHT[1]; |
| _zz_decode_RS2_3[31] = memory_SHIFT_RIGHT[0]; |
| end |
| |
| assign execute_MulPlugin_a = execute_RS1; |
| assign execute_MulPlugin_b = execute_RS2; |
| assign switch_MulPlugin_l87 = execute_INSTRUCTION[13 : 12]; |
| always @(*) begin |
| case(switch_MulPlugin_l87) |
| 2'b01 : begin |
| execute_MulPlugin_aSigned = 1'b1; |
| end |
| 2'b10 : begin |
| execute_MulPlugin_aSigned = 1'b1; |
| end |
| default : begin |
| execute_MulPlugin_aSigned = 1'b0; |
| end |
| endcase |
| end |
| |
| always @(*) begin |
| case(switch_MulPlugin_l87) |
| 2'b01 : begin |
| execute_MulPlugin_bSigned = 1'b1; |
| end |
| 2'b10 : begin |
| execute_MulPlugin_bSigned = 1'b0; |
| end |
| default : begin |
| execute_MulPlugin_bSigned = 1'b0; |
| end |
| endcase |
| end |
| |
| assign execute_MulPlugin_aULow = execute_MulPlugin_a[15 : 0]; |
| assign execute_MulPlugin_bULow = execute_MulPlugin_b[15 : 0]; |
| assign execute_MulPlugin_aSLow = {1'b0,execute_MulPlugin_a[15 : 0]}; |
| assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; |
| assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; |
| assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; |
| assign writeBack_MulPlugin_result = ($signed(_zz_writeBack_MulPlugin_result) + $signed(_zz_writeBack_MulPlugin_result_1)); |
| assign when_MulPlugin_l147 = (writeBack_arbitration_isValid && writeBack_IS_MUL); |
| assign switch_MulPlugin_l148 = writeBack_INSTRUCTION[13 : 12]; |
| assign memory_DivPlugin_frontendOk = 1'b1; |
| always @(*) begin |
| memory_DivPlugin_div_counter_willIncrement = 1'b0; |
| if(when_MulDivIterativePlugin_l128) begin |
| if(when_MulDivIterativePlugin_l132) begin |
| memory_DivPlugin_div_counter_willIncrement = 1'b1; |
| end |
| end |
| end |
| |
| always @(*) begin |
| memory_DivPlugin_div_counter_willClear = 1'b0; |
| if(when_MulDivIterativePlugin_l162) begin |
| memory_DivPlugin_div_counter_willClear = 1'b1; |
| end |
| end |
| |
| assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21); |
| assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement); |
| always @(*) begin |
| if(memory_DivPlugin_div_counter_willOverflow) begin |
| memory_DivPlugin_div_counter_valueNext = 6'h0; |
| end else begin |
| memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_memory_DivPlugin_div_counter_valueNext); |
| end |
| if(memory_DivPlugin_div_counter_willClear) begin |
| memory_DivPlugin_div_counter_valueNext = 6'h0; |
| end |
| end |
| |
| assign when_MulDivIterativePlugin_l126 = (memory_DivPlugin_div_counter_value == 6'h20); |
| assign when_MulDivIterativePlugin_l126_1 = (! memory_arbitration_isStuck); |
| assign when_MulDivIterativePlugin_l128 = (memory_arbitration_isValid && memory_IS_DIV); |
| assign when_MulDivIterativePlugin_l129 = ((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)); |
| assign when_MulDivIterativePlugin_l132 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); |
| assign _zz_memory_DivPlugin_div_stage_0_remainderShifted = memory_DivPlugin_rs1[31 : 0]; |
| assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_memory_DivPlugin_div_stage_0_remainderShifted[31]}; |
| assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator); |
| assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_memory_DivPlugin_div_stage_0_outRemainder : _zz_memory_DivPlugin_div_stage_0_outRemainder_1); |
| assign memory_DivPlugin_div_stage_0_outNumerator = _zz_memory_DivPlugin_div_stage_0_outNumerator[31:0]; |
| assign when_MulDivIterativePlugin_l151 = (memory_DivPlugin_div_counter_value == 6'h20); |
| assign _zz_memory_DivPlugin_div_result = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); |
| assign when_MulDivIterativePlugin_l162 = (! memory_arbitration_isStuck); |
| assign _zz_memory_DivPlugin_rs2 = (execute_RS2[31] && execute_IS_RS2_SIGNED); |
| assign _zz_memory_DivPlugin_rs1 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); |
| always @(*) begin |
| _zz_memory_DivPlugin_rs1_1[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); |
| _zz_memory_DivPlugin_rs1_1[31 : 0] = execute_RS1; |
| end |
| |
| always @(*) begin |
| HazardSimplePlugin_src0Hazard = 1'b0; |
| if(when_HazardSimplePlugin_l57) begin |
| if(when_HazardSimplePlugin_l58) begin |
| if(when_HazardSimplePlugin_l48) begin |
| HazardSimplePlugin_src0Hazard = 1'b1; |
| end |
| end |
| end |
| if(when_HazardSimplePlugin_l57_1) begin |
| if(when_HazardSimplePlugin_l58_1) begin |
| if(when_HazardSimplePlugin_l48_1) begin |
| HazardSimplePlugin_src0Hazard = 1'b1; |
| end |
| end |
| end |
| if(when_HazardSimplePlugin_l57_2) begin |
| if(when_HazardSimplePlugin_l58_2) begin |
| if(when_HazardSimplePlugin_l48_2) begin |
| HazardSimplePlugin_src0Hazard = 1'b1; |
| end |
| end |
| end |
| if(when_HazardSimplePlugin_l105) begin |
| HazardSimplePlugin_src0Hazard = 1'b0; |
| end |
| end |
| |
| always @(*) begin |
| HazardSimplePlugin_src1Hazard = 1'b0; |
| if(when_HazardSimplePlugin_l57) begin |
| if(when_HazardSimplePlugin_l58) begin |
| if(when_HazardSimplePlugin_l51) begin |
| HazardSimplePlugin_src1Hazard = 1'b1; |
| end |
| end |
| end |
| if(when_HazardSimplePlugin_l57_1) begin |
| if(when_HazardSimplePlugin_l58_1) begin |
| if(when_HazardSimplePlugin_l51_1) begin |
| HazardSimplePlugin_src1Hazard = 1'b1; |
| end |
| end |
| end |
| if(when_HazardSimplePlugin_l57_2) begin |
| if(when_HazardSimplePlugin_l58_2) begin |
| if(when_HazardSimplePlugin_l51_2) begin |
| HazardSimplePlugin_src1Hazard = 1'b1; |
| end |
| end |
| end |
| if(when_HazardSimplePlugin_l108) begin |
| HazardSimplePlugin_src1Hazard = 1'b0; |
| end |
| end |
| |
| assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); |
| assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; |
| assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_decode_RS2_2; |
| assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); |
| assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); |
| assign when_HazardSimplePlugin_l47 = 1'b1; |
| assign when_HazardSimplePlugin_l48 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); |
| assign when_HazardSimplePlugin_l51 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); |
| assign when_HazardSimplePlugin_l45 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); |
| assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); |
| assign when_HazardSimplePlugin_l58 = (1'b0 || (! when_HazardSimplePlugin_l47)); |
| assign when_HazardSimplePlugin_l48_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); |
| assign when_HazardSimplePlugin_l51_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); |
| assign when_HazardSimplePlugin_l45_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); |
| assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); |
| assign when_HazardSimplePlugin_l58_1 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); |
| assign when_HazardSimplePlugin_l48_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); |
| assign when_HazardSimplePlugin_l51_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); |
| assign when_HazardSimplePlugin_l45_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); |
| assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); |
| assign when_HazardSimplePlugin_l58_2 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); |
| assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE); |
| assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE); |
| assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)); |
| assign when_DebugPlugin_l225 = (DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)); |
| assign DebugPlugin_allowEBreak = (DebugPlugin_debugUsed && (! DebugPlugin_disableEbreak)); |
| always @(*) begin |
| debug_bus_cmd_ready = 1'b1; |
| if(debug_bus_cmd_valid) begin |
| case(switch_DebugPlugin_l267) |
| 6'h01 : begin |
| if(debug_bus_cmd_payload_wr) begin |
| debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; |
| end |
| end |
| default : begin |
| end |
| endcase |
| end |
| end |
| |
| always @(*) begin |
| debug_bus_rsp_data = DebugPlugin_busReadDataReg; |
| if(when_DebugPlugin_l244) begin |
| debug_bus_rsp_data[0] = DebugPlugin_resetIt; |
| debug_bus_rsp_data[1] = DebugPlugin_haltIt; |
| debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; |
| debug_bus_rsp_data[3] = DebugPlugin_haltedByBreak; |
| debug_bus_rsp_data[4] = DebugPlugin_stepIt; |
| end |
| end |
| |
| assign when_DebugPlugin_l244 = (! _zz_when_DebugPlugin_l244); |
| always @(*) begin |
| IBusCachedPlugin_injectionPort_valid = 1'b0; |
| if(debug_bus_cmd_valid) begin |
| case(switch_DebugPlugin_l267) |
| 6'h01 : begin |
| if(debug_bus_cmd_payload_wr) begin |
| IBusCachedPlugin_injectionPort_valid = 1'b1; |
| end |
| end |
| default : begin |
| end |
| endcase |
| end |
| end |
| |
| assign IBusCachedPlugin_injectionPort_payload = debug_bus_cmd_payload_data; |
| assign switch_DebugPlugin_l267 = debug_bus_cmd_payload_address[7 : 2]; |
| assign when_DebugPlugin_l271 = debug_bus_cmd_payload_data[16]; |
| assign when_DebugPlugin_l271_1 = debug_bus_cmd_payload_data[24]; |
| assign when_DebugPlugin_l272 = debug_bus_cmd_payload_data[17]; |
| assign when_DebugPlugin_l272_1 = debug_bus_cmd_payload_data[25]; |
| assign when_DebugPlugin_l273 = debug_bus_cmd_payload_data[25]; |
| assign when_DebugPlugin_l274 = debug_bus_cmd_payload_data[25]; |
| assign when_DebugPlugin_l275 = debug_bus_cmd_payload_data[18]; |
| assign when_DebugPlugin_l275_1 = debug_bus_cmd_payload_data[26]; |
| assign when_DebugPlugin_l295 = (execute_arbitration_isValid && execute_DO_EBREAK); |
| assign when_DebugPlugin_l298 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); |
| assign when_DebugPlugin_l311 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); |
| assign debug_resetOut = DebugPlugin_resetIt_regNext; |
| assign when_DebugPlugin_l327 = (DebugPlugin_haltIt || DebugPlugin_stepIt); |
| always @(*) begin |
| CsrPlugin_privilege = 2'b11; |
| if(CsrPlugin_forceMachineWire) begin |
| CsrPlugin_privilege = 2'b11; |
| end |
| end |
| |
| assign CsrPlugin_misa_base = 2'b01; |
| assign CsrPlugin_misa_extensions = 26'h0000042; |
| assign _zz_when_CsrPlugin_l952 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); |
| assign _zz_when_CsrPlugin_l952_1 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); |
| assign _zz_when_CsrPlugin_l952_2 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); |
| assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; |
| assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); |
| assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; |
| assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1[0]; |
| always @(*) begin |
| CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; |
| if(_zz_when) begin |
| CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; |
| end |
| if(decode_arbitration_isFlushed) begin |
| CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; |
| end |
| end |
| |
| always @(*) begin |
| CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; |
| if(BranchPlugin_branchExceptionPort_valid) begin |
| CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; |
| end |
| if(execute_arbitration_isFlushed) begin |
| CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; |
| end |
| end |
| |
| always @(*) begin |
| CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; |
| if(memory_arbitration_isFlushed) begin |
| CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; |
| end |
| end |
| |
| always @(*) begin |
| CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; |
| if(DBusCachedPlugin_exceptionBus_valid) begin |
| CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; |
| end |
| if(writeBack_arbitration_isFlushed) begin |
| CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; |
| end |
| end |
| |
| assign when_CsrPlugin_l909 = (! decode_arbitration_isStuck); |
| assign when_CsrPlugin_l909_1 = (! execute_arbitration_isStuck); |
| assign when_CsrPlugin_l909_2 = (! memory_arbitration_isStuck); |
| assign when_CsrPlugin_l909_3 = (! writeBack_arbitration_isStuck); |
| assign when_CsrPlugin_l922 = ({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000); |
| assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; |
| assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; |
| assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; |
| assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; |
| assign when_CsrPlugin_l946 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); |
| assign when_CsrPlugin_l952 = ((_zz_when_CsrPlugin_l952 && 1'b1) && (! 1'b0)); |
| assign when_CsrPlugin_l952_1 = ((_zz_when_CsrPlugin_l952_1 && 1'b1) && (! 1'b0)); |
| assign when_CsrPlugin_l952_2 = ((_zz_when_CsrPlugin_l952_2 && 1'b1) && (! 1'b0)); |
| assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); |
| assign CsrPlugin_lastStageWasWfi = 1'b0; |
| assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); |
| assign when_CsrPlugin_l980 = (! execute_arbitration_isStuck); |
| assign when_CsrPlugin_l980_1 = (! memory_arbitration_isStuck); |
| assign when_CsrPlugin_l980_2 = (! writeBack_arbitration_isStuck); |
| assign when_CsrPlugin_l985 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt); |
| always @(*) begin |
| CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; |
| if(when_CsrPlugin_l991) begin |
| CsrPlugin_pipelineLiberator_done = 1'b0; |
| end |
| if(CsrPlugin_hadException) begin |
| CsrPlugin_pipelineLiberator_done = 1'b0; |
| end |
| end |
| |
| assign when_CsrPlugin_l991 = ({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000); |
| assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); |
| always @(*) begin |
| CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; |
| if(CsrPlugin_hadException) begin |
| CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; |
| end |
| end |
| |
| always @(*) begin |
| CsrPlugin_trapCause = CsrPlugin_interrupt_code; |
| if(CsrPlugin_hadException) begin |
| CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; |
| end |
| end |
| |
| always @(*) begin |
| CsrPlugin_xtvec_mode = 2'bxx; |
| case(CsrPlugin_targetPrivilege) |
| 2'b11 : begin |
| CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; |
| end |
| default : begin |
| end |
| endcase |
| end |
| |
| always @(*) begin |
| CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; |
| case(CsrPlugin_targetPrivilege) |
| 2'b11 : begin |
| CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; |
| end |
| default : begin |
| end |
| endcase |
| end |
| |
| assign when_CsrPlugin_l1019 = (CsrPlugin_hadException || CsrPlugin_interruptJump); |
| assign when_CsrPlugin_l1064 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == EnvCtrlEnum_XRET)); |
| assign switch_CsrPlugin_l1068 = writeBack_INSTRUCTION[29 : 28]; |
| assign contextSwitching = CsrPlugin_jumpInterface_valid; |
| assign when_CsrPlugin_l1116 = (|{(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == EnvCtrlEnum_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == EnvCtrlEnum_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == EnvCtrlEnum_XRET))}}); |
| assign execute_CsrPlugin_blockedBySideEffects = ((|{writeBack_arbitration_isValid,memory_arbitration_isValid}) || 1'b0); |
| always @(*) begin |
| execute_CsrPlugin_illegalAccess = 1'b1; |
| if(execute_CsrPlugin_csr_768) begin |
| execute_CsrPlugin_illegalAccess = 1'b0; |
| end |
| if(execute_CsrPlugin_csr_836) begin |
| execute_CsrPlugin_illegalAccess = 1'b0; |
| end |
| if(execute_CsrPlugin_csr_772) begin |
| execute_CsrPlugin_illegalAccess = 1'b0; |
| end |
| if(execute_CsrPlugin_csr_773) begin |
| execute_CsrPlugin_illegalAccess = 1'b0; |
| end |
| if(execute_CsrPlugin_csr_833) begin |
| execute_CsrPlugin_illegalAccess = 1'b0; |
| end |
| if(execute_CsrPlugin_csr_834) begin |
| if(execute_CSR_READ_OPCODE) begin |
| execute_CsrPlugin_illegalAccess = 1'b0; |
| end |
| end |
| if(execute_CsrPlugin_csr_835) begin |
| if(execute_CSR_READ_OPCODE) begin |
| execute_CsrPlugin_illegalAccess = 1'b0; |
| end |
| end |
| if(execute_CsrPlugin_csr_2816) begin |
| execute_CsrPlugin_illegalAccess = 1'b0; |
| end |
| if(execute_CsrPlugin_csr_2944) begin |
| execute_CsrPlugin_illegalAccess = 1'b0; |
| end |
| if(execute_CsrPlugin_csr_3072) begin |
| if(execute_CSR_READ_OPCODE) begin |
| execute_CsrPlugin_illegalAccess = 1'b0; |
| end |
| end |
| if(execute_CsrPlugin_csr_3200) begin |
| if(execute_CSR_READ_OPCODE) begin |
| execute_CsrPlugin_illegalAccess = 1'b0; |
| end |
| end |
| if(execute_CsrPlugin_csr_256) begin |
| execute_CsrPlugin_illegalAccess = 1'b0; |
| end |
| if(execute_CsrPlugin_csr_384) begin |
| execute_CsrPlugin_illegalAccess = 1'b0; |
| end |
| if(CsrPlugin_csrMapping_allowCsrSignal) begin |
| execute_CsrPlugin_illegalAccess = 1'b0; |
| end |
| if(when_CsrPlugin_l1297) begin |
| execute_CsrPlugin_illegalAccess = 1'b1; |
| end |
| if(when_CsrPlugin_l1302) begin |
| execute_CsrPlugin_illegalAccess = 1'b0; |
| end |
| end |
| |
| always @(*) begin |
| execute_CsrPlugin_illegalInstruction = 1'b0; |
| if(when_CsrPlugin_l1136) begin |
| if(when_CsrPlugin_l1137) begin |
| execute_CsrPlugin_illegalInstruction = 1'b1; |
| end |
| end |
| end |
| |
| assign when_CsrPlugin_l1136 = (execute_arbitration_isValid && (execute_ENV_CTRL == EnvCtrlEnum_XRET)); |
| assign when_CsrPlugin_l1137 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]); |
| always @(*) begin |
| execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); |
| if(when_CsrPlugin_l1297) begin |
| execute_CsrPlugin_writeInstruction = 1'b0; |
| end |
| end |
| |
| always @(*) begin |
| execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); |
| if(when_CsrPlugin_l1297) begin |
| execute_CsrPlugin_readInstruction = 1'b0; |
| end |
| end |
| |
| assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); |
| assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); |
| assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects); |
| assign execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal; |
| assign switch_Misc_l211_1 = execute_INSTRUCTION[13]; |
| always @(*) begin |
| case(switch_Misc_l211_1) |
| 1'b0 : begin |
| _zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1; |
| end |
| default : begin |
| _zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); |
| end |
| endcase |
| end |
| |
| assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal; |
| assign when_CsrPlugin_l1176 = (execute_arbitration_isValid && execute_IS_CSR); |
| assign when_CsrPlugin_l1180 = (execute_arbitration_isValid && (execute_IS_CSR || 1'b0)); |
| assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; |
| assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); |
| assign switch_Misc_l211_2 = execute_INSTRUCTION[14 : 12]; |
| always @(*) begin |
| casez(switch_Misc_l211_2) |
| 3'b000 : begin |
| _zz_execute_BRANCH_DO = execute_BranchPlugin_eq; |
| end |
| 3'b001 : begin |
| _zz_execute_BRANCH_DO = (! execute_BranchPlugin_eq); |
| end |
| 3'b1?1 : begin |
| _zz_execute_BRANCH_DO = (! execute_SRC_LESS); |
| end |
| default : begin |
| _zz_execute_BRANCH_DO = execute_SRC_LESS; |
| end |
| endcase |
| end |
| |
| always @(*) begin |
| case(execute_BRANCH_CTRL) |
| BranchCtrlEnum_INC : begin |
| _zz_execute_BRANCH_DO_1 = 1'b0; |
| end |
| BranchCtrlEnum_JAL : begin |
| _zz_execute_BRANCH_DO_1 = 1'b1; |
| end |
| BranchCtrlEnum_JALR : begin |
| _zz_execute_BRANCH_DO_1 = 1'b1; |
| end |
| default : begin |
| _zz_execute_BRANCH_DO_1 = _zz_execute_BRANCH_DO; |
| end |
| endcase |
| end |
| |
| assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == BranchCtrlEnum_JALR) ? execute_RS1 : execute_PC); |
| assign _zz_execute_BranchPlugin_branch_src2 = _zz__zz_execute_BranchPlugin_branch_src2[19]; |
| always @(*) begin |
| _zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2; |
| _zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2; |
| _zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2; |
| _zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2; |
| _zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2; |
| _zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2; |
| _zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2; |
| _zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2; |
| _zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2; |
| _zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2; |
| _zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2; |
| end |
| |
| assign _zz_execute_BranchPlugin_branch_src2_2 = execute_INSTRUCTION[31]; |
| always @(*) begin |
| _zz_execute_BranchPlugin_branch_src2_3[19] = _zz_execute_BranchPlugin_branch_src2_2; |
| _zz_execute_BranchPlugin_branch_src2_3[18] = _zz_execute_BranchPlugin_branch_src2_2; |
| _zz_execute_BranchPlugin_branch_src2_3[17] = _zz_execute_BranchPlugin_branch_src2_2; |
| _zz_execute_BranchPlugin_branch_src2_3[16] = _zz_execute_BranchPlugin_branch_src2_2; |
| _zz_execute_BranchPlugin_branch_src2_3[15] = _zz_execute_BranchPlugin_branch_src2_2; |
| _zz_execute_BranchPlugin_branch_src2_3[14] = _zz_execute_BranchPlugin_branch_src2_2; |
| _zz_execute_BranchPlugin_branch_src2_3[13] = _zz_execute_BranchPlugin_branch_src2_2; |
| _zz_execute_BranchPlugin_branch_src2_3[12] = _zz_execute_BranchPlugin_branch_src2_2; |
| _zz_execute_BranchPlugin_branch_src2_3[11] = _zz_execute_BranchPlugin_branch_src2_2; |
| _zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2; |
| _zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2; |
| _zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2; |
| _zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2; |
| _zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2; |
| _zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2; |
| _zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2; |
| _zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2; |
| _zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2; |
| _zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2; |
| _zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2; |
| end |
| |
| assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11]; |
| always @(*) begin |
| _zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4; |
| _zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4; |
| _zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4; |
| _zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4; |
| _zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4; |
| _zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4; |
| _zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4; |
| _zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4; |
| _zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4; |
| _zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4; |
| _zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4; |
| _zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4; |
| _zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4; |
| _zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4; |
| _zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4; |
| _zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4; |
| _zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4; |
| _zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4; |
| _zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4; |
| end |
| |
| always @(*) begin |
| case(execute_BRANCH_CTRL) |
| BranchCtrlEnum_JAL : begin |
| _zz_execute_BranchPlugin_branch_src2_6 = {{_zz_execute_BranchPlugin_branch_src2_1,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; |
| end |
| BranchCtrlEnum_JALR : begin |
| _zz_execute_BranchPlugin_branch_src2_6 = {_zz_execute_BranchPlugin_branch_src2_3,execute_INSTRUCTION[31 : 20]}; |
| end |
| default : begin |
| _zz_execute_BranchPlugin_branch_src2_6 = {{_zz_execute_BranchPlugin_branch_src2_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; |
| end |
| endcase |
| end |
| |
| assign execute_BranchPlugin_branch_src2 = _zz_execute_BranchPlugin_branch_src2_6; |
| assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); |
| assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && (! 1'b0)); |
| assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC; |
| always @(*) begin |
| BranchPlugin_branchExceptionPort_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && BranchPlugin_jumpInterface_payload[1]); |
| if(when_BranchPlugin_l216) begin |
| BranchPlugin_branchExceptionPort_valid = 1'b0; |
| end |
| end |
| |
| assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; |
| assign BranchPlugin_branchExceptionPort_payload_badAddr = BranchPlugin_jumpInterface_payload; |
| assign when_BranchPlugin_l216 = 1'b0; |
| assign MmuPlugin_ports_0_dirty = 1'b0; |
| always @(*) begin |
| MmuPlugin_ports_0_requireMmuLockupCalc = ((1'b1 && (! IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation)) && MmuPlugin_satp_mode); |
| if(when_MmuPlugin_l125) begin |
| MmuPlugin_ports_0_requireMmuLockupCalc = 1'b0; |
| end |
| if(when_MmuPlugin_l126) begin |
| MmuPlugin_ports_0_requireMmuLockupCalc = 1'b0; |
| end |
| end |
| |
| assign when_MmuPlugin_l125 = ((! MmuPlugin_status_mprv) && (CsrPlugin_privilege == 2'b11)); |
| assign when_MmuPlugin_l126 = (CsrPlugin_privilege == 2'b11); |
| assign MmuPlugin_ports_0_cacheHitsCalc = {((MmuPlugin_ports_0_cache_3_valid && (MmuPlugin_ports_0_cache_3_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_3_superPage || (MmuPlugin_ports_0_cache_3_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))),{((MmuPlugin_ports_0_cache_2_valid && (MmuPlugin_ports_0_cache_2_virtualAddress_1 == _zz_MmuPlugin_ports_0_cacheHitsCalc)) && (MmuPlugin_ports_0_cache_2_superPage || (MmuPlugin_ports_0_cache_2_virtualAddress_0 == _zz_MmuPlugin_ports_0_cacheHitsCalc_1))),{((MmuPlugin_ports_0_cache_1_valid && _zz_MmuPlugin_ports_0_cacheHitsCalc_2) && (MmuPlugin_ports_0_cache_1_superPage || _zz_MmuPlugin_ports_0_cacheHitsCalc_3)),((MmuPlugin_ports_0_cache_0_valid && _zz_MmuPlugin_ports_0_cacheHitsCalc_4) && (MmuPlugin_ports_0_cache_0_superPage || _zz_MmuPlugin_ports_0_cacheHitsCalc_5))}}}; |
| assign MmuPlugin_ports_0_cacheHit = (|MmuPlugin_ports_0_cacheHitsCalc); |
| assign _zz_MmuPlugin_ports_0_cacheLine_valid = MmuPlugin_ports_0_cacheHitsCalc[3]; |
| assign _zz_MmuPlugin_ports_0_cacheLine_valid_1 = (MmuPlugin_ports_0_cacheHitsCalc[1] || _zz_MmuPlugin_ports_0_cacheLine_valid); |
| assign _zz_MmuPlugin_ports_0_cacheLine_valid_2 = (MmuPlugin_ports_0_cacheHitsCalc[2] || _zz_MmuPlugin_ports_0_cacheLine_valid); |
| assign _zz_MmuPlugin_ports_0_cacheLine_valid_3 = {_zz_MmuPlugin_ports_0_cacheLine_valid_2,_zz_MmuPlugin_ports_0_cacheLine_valid_1}; |
| assign MmuPlugin_ports_0_cacheLine_valid = _zz_MmuPlugin_ports_0_cacheLine_valid_4; |
| assign MmuPlugin_ports_0_cacheLine_exception = _zz_MmuPlugin_ports_0_cacheLine_exception; |
| assign MmuPlugin_ports_0_cacheLine_superPage = _zz_MmuPlugin_ports_0_cacheLine_superPage; |
| assign MmuPlugin_ports_0_cacheLine_virtualAddress_0 = _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_0; |
| assign MmuPlugin_ports_0_cacheLine_virtualAddress_1 = _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_1; |
| assign MmuPlugin_ports_0_cacheLine_physicalAddress_0 = _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_0; |
| assign MmuPlugin_ports_0_cacheLine_physicalAddress_1 = _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_1; |
| assign MmuPlugin_ports_0_cacheLine_allowRead = _zz_MmuPlugin_ports_0_cacheLine_allowRead; |
| assign MmuPlugin_ports_0_cacheLine_allowWrite = _zz_MmuPlugin_ports_0_cacheLine_allowWrite; |
| assign MmuPlugin_ports_0_cacheLine_allowExecute = _zz_MmuPlugin_ports_0_cacheLine_allowExecute; |
| assign MmuPlugin_ports_0_cacheLine_allowUser = _zz_MmuPlugin_ports_0_cacheLine_allowUser; |
| always @(*) begin |
| MmuPlugin_ports_0_entryToReplace_willIncrement = 1'b0; |
| if(when_MmuPlugin_l272) begin |
| if(when_MmuPlugin_l274) begin |
| MmuPlugin_ports_0_entryToReplace_willIncrement = 1'b1; |
| end |
| end |
| end |
| |
| assign MmuPlugin_ports_0_entryToReplace_willClear = 1'b0; |
| assign MmuPlugin_ports_0_entryToReplace_willOverflowIfInc = (MmuPlugin_ports_0_entryToReplace_value == 2'b11); |
| assign MmuPlugin_ports_0_entryToReplace_willOverflow = (MmuPlugin_ports_0_entryToReplace_willOverflowIfInc && MmuPlugin_ports_0_entryToReplace_willIncrement); |
| always @(*) begin |
| MmuPlugin_ports_0_entryToReplace_valueNext = (MmuPlugin_ports_0_entryToReplace_value + _zz_MmuPlugin_ports_0_entryToReplace_valueNext); |
| if(MmuPlugin_ports_0_entryToReplace_willClear) begin |
| MmuPlugin_ports_0_entryToReplace_valueNext = 2'b00; |
| end |
| end |
| |
| always @(*) begin |
| if(MmuPlugin_ports_0_requireMmuLockupCalc) begin |
| IBusCachedPlugin_mmuBus_rsp_physicalAddress = {{MmuPlugin_ports_0_cacheLine_physicalAddress_1,(MmuPlugin_ports_0_cacheLine_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cacheLine_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; |
| end else begin |
| IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; |
| end |
| end |
| |
| always @(*) begin |
| if(MmuPlugin_ports_0_requireMmuLockupCalc) begin |
| IBusCachedPlugin_mmuBus_rsp_allowRead = (MmuPlugin_ports_0_cacheLine_allowRead || (MmuPlugin_status_mxr && MmuPlugin_ports_0_cacheLine_allowExecute)); |
| end else begin |
| IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; |
| end |
| end |
| |
| always @(*) begin |
| if(MmuPlugin_ports_0_requireMmuLockupCalc) begin |
| IBusCachedPlugin_mmuBus_rsp_allowWrite = MmuPlugin_ports_0_cacheLine_allowWrite; |
| end else begin |
| IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; |
| end |
| end |
| |
| always @(*) begin |
| if(MmuPlugin_ports_0_requireMmuLockupCalc) begin |
| IBusCachedPlugin_mmuBus_rsp_allowExecute = MmuPlugin_ports_0_cacheLine_allowExecute; |
| end else begin |
| IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; |
| end |
| end |
| |
| always @(*) begin |
| if(MmuPlugin_ports_0_requireMmuLockupCalc) begin |
| IBusCachedPlugin_mmuBus_rsp_exception = (((! MmuPlugin_ports_0_dirty) && MmuPlugin_ports_0_cacheHit) && ((MmuPlugin_ports_0_cacheLine_exception || ((MmuPlugin_ports_0_cacheLine_allowUser && (CsrPlugin_privilege == 2'b01)) && (! MmuPlugin_status_sum))) || ((! MmuPlugin_ports_0_cacheLine_allowUser) && (CsrPlugin_privilege == 2'b00)))); |
| end else begin |
| IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; |
| end |
| end |
| |
| always @(*) begin |
| if(MmuPlugin_ports_0_requireMmuLockupCalc) begin |
| IBusCachedPlugin_mmuBus_rsp_refilling = (MmuPlugin_ports_0_dirty || (! MmuPlugin_ports_0_cacheHit)); |
| end else begin |
| IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; |
| end |
| end |
| |
| always @(*) begin |
| if(MmuPlugin_ports_0_requireMmuLockupCalc) begin |
| IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b1; |
| end else begin |
| IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; |
| end |
| end |
| |
| assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = IBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; |
| assign IBusCachedPlugin_mmuBus_rsp_bypassTranslation = (! MmuPlugin_ports_0_requireMmuLockupCalc); |
| assign IBusCachedPlugin_mmuBus_rsp_ways_0_sel = MmuPlugin_ports_0_cacheHitsCalc[0]; |
| assign IBusCachedPlugin_mmuBus_rsp_ways_0_physical = {{MmuPlugin_ports_0_cache_0_physicalAddress_1,(MmuPlugin_ports_0_cache_0_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cache_0_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; |
| assign IBusCachedPlugin_mmuBus_rsp_ways_1_sel = MmuPlugin_ports_0_cacheHitsCalc[1]; |
| assign IBusCachedPlugin_mmuBus_rsp_ways_1_physical = {{MmuPlugin_ports_0_cache_1_physicalAddress_1,(MmuPlugin_ports_0_cache_1_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cache_1_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; |
| assign IBusCachedPlugin_mmuBus_rsp_ways_2_sel = MmuPlugin_ports_0_cacheHitsCalc[2]; |
| assign IBusCachedPlugin_mmuBus_rsp_ways_2_physical = {{MmuPlugin_ports_0_cache_2_physicalAddress_1,(MmuPlugin_ports_0_cache_2_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cache_2_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; |
| assign IBusCachedPlugin_mmuBus_rsp_ways_3_sel = MmuPlugin_ports_0_cacheHitsCalc[3]; |
| assign IBusCachedPlugin_mmuBus_rsp_ways_3_physical = {{MmuPlugin_ports_0_cache_3_physicalAddress_1,(MmuPlugin_ports_0_cache_3_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cache_3_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; |
| assign MmuPlugin_ports_1_dirty = 1'b0; |
| always @(*) begin |
| MmuPlugin_ports_1_requireMmuLockupCalc = ((1'b1 && (! DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation)) && MmuPlugin_satp_mode); |
| if(when_MmuPlugin_l125_1) begin |
| MmuPlugin_ports_1_requireMmuLockupCalc = 1'b0; |
| end |
| if(when_MmuPlugin_l126_1) begin |
| if(when_MmuPlugin_l128) begin |
| MmuPlugin_ports_1_requireMmuLockupCalc = 1'b0; |
| end |
| end |
| end |
| |
| assign when_MmuPlugin_l125_1 = ((! MmuPlugin_status_mprv) && (CsrPlugin_privilege == 2'b11)); |
| assign when_MmuPlugin_l126_1 = (CsrPlugin_privilege == 2'b11); |
| assign when_MmuPlugin_l128 = ((! MmuPlugin_status_mprv) || (CsrPlugin_mstatus_MPP == 2'b11)); |
| assign MmuPlugin_ports_1_cacheHitsCalc = {((MmuPlugin_ports_1_cache_3_valid && (MmuPlugin_ports_1_cache_3_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_3_superPage || (MmuPlugin_ports_1_cache_3_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))),{((MmuPlugin_ports_1_cache_2_valid && (MmuPlugin_ports_1_cache_2_virtualAddress_1 == _zz_MmuPlugin_ports_1_cacheHitsCalc)) && (MmuPlugin_ports_1_cache_2_superPage || (MmuPlugin_ports_1_cache_2_virtualAddress_0 == _zz_MmuPlugin_ports_1_cacheHitsCalc_1))),{((MmuPlugin_ports_1_cache_1_valid && _zz_MmuPlugin_ports_1_cacheHitsCalc_2) && (MmuPlugin_ports_1_cache_1_superPage || _zz_MmuPlugin_ports_1_cacheHitsCalc_3)),((MmuPlugin_ports_1_cache_0_valid && _zz_MmuPlugin_ports_1_cacheHitsCalc_4) && (MmuPlugin_ports_1_cache_0_superPage || _zz_MmuPlugin_ports_1_cacheHitsCalc_5))}}}; |
| assign MmuPlugin_ports_1_cacheHit = (|MmuPlugin_ports_1_cacheHitsCalc); |
| assign _zz_MmuPlugin_ports_1_cacheLine_valid = MmuPlugin_ports_1_cacheHitsCalc[3]; |
| assign _zz_MmuPlugin_ports_1_cacheLine_valid_1 = (MmuPlugin_ports_1_cacheHitsCalc[1] || _zz_MmuPlugin_ports_1_cacheLine_valid); |
| assign _zz_MmuPlugin_ports_1_cacheLine_valid_2 = (MmuPlugin_ports_1_cacheHitsCalc[2] || _zz_MmuPlugin_ports_1_cacheLine_valid); |
| assign _zz_MmuPlugin_ports_1_cacheLine_valid_3 = {_zz_MmuPlugin_ports_1_cacheLine_valid_2,_zz_MmuPlugin_ports_1_cacheLine_valid_1}; |
| assign MmuPlugin_ports_1_cacheLine_valid = _zz_MmuPlugin_ports_1_cacheLine_valid_4; |
| assign MmuPlugin_ports_1_cacheLine_exception = _zz_MmuPlugin_ports_1_cacheLine_exception; |
| assign MmuPlugin_ports_1_cacheLine_superPage = _zz_MmuPlugin_ports_1_cacheLine_superPage; |
| assign MmuPlugin_ports_1_cacheLine_virtualAddress_0 = _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_0; |
| assign MmuPlugin_ports_1_cacheLine_virtualAddress_1 = _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_1; |
| assign MmuPlugin_ports_1_cacheLine_physicalAddress_0 = _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_0; |
| assign MmuPlugin_ports_1_cacheLine_physicalAddress_1 = _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_1; |
| assign MmuPlugin_ports_1_cacheLine_allowRead = _zz_MmuPlugin_ports_1_cacheLine_allowRead; |
| assign MmuPlugin_ports_1_cacheLine_allowWrite = _zz_MmuPlugin_ports_1_cacheLine_allowWrite; |
| assign MmuPlugin_ports_1_cacheLine_allowExecute = _zz_MmuPlugin_ports_1_cacheLine_allowExecute; |
| assign MmuPlugin_ports_1_cacheLine_allowUser = _zz_MmuPlugin_ports_1_cacheLine_allowUser; |
| always @(*) begin |
| MmuPlugin_ports_1_entryToReplace_willIncrement = 1'b0; |
| if(when_MmuPlugin_l272) begin |
| if(when_MmuPlugin_l274_1) begin |
| MmuPlugin_ports_1_entryToReplace_willIncrement = 1'b1; |
| end |
| end |
| end |
| |
| assign MmuPlugin_ports_1_entryToReplace_willClear = 1'b0; |
| assign MmuPlugin_ports_1_entryToReplace_willOverflowIfInc = (MmuPlugin_ports_1_entryToReplace_value == 2'b11); |
| assign MmuPlugin_ports_1_entryToReplace_willOverflow = (MmuPlugin_ports_1_entryToReplace_willOverflowIfInc && MmuPlugin_ports_1_entryToReplace_willIncrement); |
| always @(*) begin |
| MmuPlugin_ports_1_entryToReplace_valueNext = (MmuPlugin_ports_1_entryToReplace_value + _zz_MmuPlugin_ports_1_entryToReplace_valueNext); |
| if(MmuPlugin_ports_1_entryToReplace_willClear) begin |
| MmuPlugin_ports_1_entryToReplace_valueNext = 2'b00; |
| end |
| end |
| |
| always @(*) begin |
| if(MmuPlugin_ports_1_requireMmuLockupCalc) begin |
| DBusCachedPlugin_mmuBus_rsp_physicalAddress = {{MmuPlugin_ports_1_cacheLine_physicalAddress_1,(MmuPlugin_ports_1_cacheLine_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cacheLine_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; |
| end else begin |
| DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; |
| end |
| end |
| |
| always @(*) begin |
| if(MmuPlugin_ports_1_requireMmuLockupCalc) begin |
| DBusCachedPlugin_mmuBus_rsp_allowRead = (MmuPlugin_ports_1_cacheLine_allowRead || (MmuPlugin_status_mxr && MmuPlugin_ports_1_cacheLine_allowExecute)); |
| end else begin |
| DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; |
| end |
| end |
| |
| always @(*) begin |
| if(MmuPlugin_ports_1_requireMmuLockupCalc) begin |
| DBusCachedPlugin_mmuBus_rsp_allowWrite = MmuPlugin_ports_1_cacheLine_allowWrite; |
| end else begin |
| DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; |
| end |
| end |
| |
| always @(*) begin |
| if(MmuPlugin_ports_1_requireMmuLockupCalc) begin |
| DBusCachedPlugin_mmuBus_rsp_allowExecute = MmuPlugin_ports_1_cacheLine_allowExecute; |
| end else begin |
| DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; |
| end |
| end |
| |
| always @(*) begin |
| if(MmuPlugin_ports_1_requireMmuLockupCalc) begin |
| DBusCachedPlugin_mmuBus_rsp_exception = (((! MmuPlugin_ports_1_dirty) && MmuPlugin_ports_1_cacheHit) && ((MmuPlugin_ports_1_cacheLine_exception || ((MmuPlugin_ports_1_cacheLine_allowUser && (CsrPlugin_privilege == 2'b01)) && (! MmuPlugin_status_sum))) || ((! MmuPlugin_ports_1_cacheLine_allowUser) && (CsrPlugin_privilege == 2'b00)))); |
| end else begin |
| DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; |
| end |
| end |
| |
| always @(*) begin |
| if(MmuPlugin_ports_1_requireMmuLockupCalc) begin |
| DBusCachedPlugin_mmuBus_rsp_refilling = (MmuPlugin_ports_1_dirty || (! MmuPlugin_ports_1_cacheHit)); |
| end else begin |
| DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; |
| end |
| end |
| |
| always @(*) begin |
| if(MmuPlugin_ports_1_requireMmuLockupCalc) begin |
| DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b1; |
| end else begin |
| DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; |
| end |
| end |
| |
| assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; |
| assign DBusCachedPlugin_mmuBus_rsp_bypassTranslation = (! MmuPlugin_ports_1_requireMmuLockupCalc); |
| assign DBusCachedPlugin_mmuBus_rsp_ways_0_sel = MmuPlugin_ports_1_cacheHitsCalc[0]; |
| assign DBusCachedPlugin_mmuBus_rsp_ways_0_physical = {{MmuPlugin_ports_1_cache_0_physicalAddress_1,(MmuPlugin_ports_1_cache_0_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_0_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; |
| assign DBusCachedPlugin_mmuBus_rsp_ways_1_sel = MmuPlugin_ports_1_cacheHitsCalc[1]; |
| assign DBusCachedPlugin_mmuBus_rsp_ways_1_physical = {{MmuPlugin_ports_1_cache_1_physicalAddress_1,(MmuPlugin_ports_1_cache_1_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_1_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; |
| assign DBusCachedPlugin_mmuBus_rsp_ways_2_sel = MmuPlugin_ports_1_cacheHitsCalc[2]; |
| assign DBusCachedPlugin_mmuBus_rsp_ways_2_physical = {{MmuPlugin_ports_1_cache_2_physicalAddress_1,(MmuPlugin_ports_1_cache_2_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_2_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; |
| assign DBusCachedPlugin_mmuBus_rsp_ways_3_sel = MmuPlugin_ports_1_cacheHitsCalc[3]; |
| assign DBusCachedPlugin_mmuBus_rsp_ways_3_physical = {{MmuPlugin_ports_1_cache_3_physicalAddress_1,(MmuPlugin_ports_1_cache_3_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_3_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; |
| assign MmuPlugin_shared_dBusRsp_pte_V = MmuPlugin_shared_dBusRspStaged_payload_data[0]; |
| assign MmuPlugin_shared_dBusRsp_pte_R = MmuPlugin_shared_dBusRspStaged_payload_data[1]; |
| assign MmuPlugin_shared_dBusRsp_pte_W = MmuPlugin_shared_dBusRspStaged_payload_data[2]; |
| assign MmuPlugin_shared_dBusRsp_pte_X = MmuPlugin_shared_dBusRspStaged_payload_data[3]; |
| assign MmuPlugin_shared_dBusRsp_pte_U = MmuPlugin_shared_dBusRspStaged_payload_data[4]; |
| assign MmuPlugin_shared_dBusRsp_pte_G = MmuPlugin_shared_dBusRspStaged_payload_data[5]; |
| assign MmuPlugin_shared_dBusRsp_pte_A = MmuPlugin_shared_dBusRspStaged_payload_data[6]; |
| assign MmuPlugin_shared_dBusRsp_pte_D = MmuPlugin_shared_dBusRspStaged_payload_data[7]; |
| assign MmuPlugin_shared_dBusRsp_pte_RSW = MmuPlugin_shared_dBusRspStaged_payload_data[9 : 8]; |
| assign MmuPlugin_shared_dBusRsp_pte_PPN0 = MmuPlugin_shared_dBusRspStaged_payload_data[19 : 10]; |
| assign MmuPlugin_shared_dBusRsp_pte_PPN1 = MmuPlugin_shared_dBusRspStaged_payload_data[31 : 20]; |
| assign MmuPlugin_shared_dBusRsp_exception = (((! MmuPlugin_shared_dBusRsp_pte_V) || ((! MmuPlugin_shared_dBusRsp_pte_R) && MmuPlugin_shared_dBusRsp_pte_W)) || MmuPlugin_shared_dBusRspStaged_payload_error); |
| assign MmuPlugin_shared_dBusRsp_leaf = (MmuPlugin_shared_dBusRsp_pte_R || MmuPlugin_shared_dBusRsp_pte_X); |
| assign when_MmuPlugin_l205 = (MmuPlugin_shared_dBusRspStaged_valid && (! MmuPlugin_shared_dBusRspStaged_payload_redo)); |
| always @(*) begin |
| MmuPlugin_dBusAccess_cmd_valid = 1'b0; |
| case(MmuPlugin_shared_state_1) |
| MmuPlugin_shared_State_IDLE : begin |
| end |
| MmuPlugin_shared_State_L1_CMD : begin |
| MmuPlugin_dBusAccess_cmd_valid = 1'b1; |
| end |
| MmuPlugin_shared_State_L1_RSP : begin |
| end |
| MmuPlugin_shared_State_L0_CMD : begin |
| MmuPlugin_dBusAccess_cmd_valid = 1'b1; |
| end |
| default : begin |
| end |
| endcase |
| end |
| |
| assign MmuPlugin_dBusAccess_cmd_payload_write = 1'b0; |
| assign MmuPlugin_dBusAccess_cmd_payload_size = 2'b10; |
| always @(*) begin |
| MmuPlugin_dBusAccess_cmd_payload_address = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; |
| case(MmuPlugin_shared_state_1) |
| MmuPlugin_shared_State_IDLE : begin |
| end |
| MmuPlugin_shared_State_L1_CMD : begin |
| MmuPlugin_dBusAccess_cmd_payload_address = {{MmuPlugin_satp_ppn,MmuPlugin_shared_vpn_1},2'b00}; |
| end |
| MmuPlugin_shared_State_L1_RSP : begin |
| end |
| MmuPlugin_shared_State_L0_CMD : begin |
| MmuPlugin_dBusAccess_cmd_payload_address = {{{MmuPlugin_shared_pteBuffer_PPN1[9 : 0],MmuPlugin_shared_pteBuffer_PPN0},MmuPlugin_shared_vpn_0},2'b00}; |
| end |
| default : begin |
| end |
| endcase |
| end |
| |
| assign MmuPlugin_dBusAccess_cmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; |
| assign MmuPlugin_dBusAccess_cmd_payload_writeMask = 4'bxxxx; |
| assign _zz_MmuPlugin_shared_refills = {(((DBusCachedPlugin_mmuBus_cmd_0_isValid && MmuPlugin_ports_1_requireMmuLockupCalc) && (! MmuPlugin_ports_1_dirty)) && (! MmuPlugin_ports_1_cacheHit)),(((IBusCachedPlugin_mmuBus_cmd_0_isValid && MmuPlugin_ports_0_requireMmuLockupCalc) && (! MmuPlugin_ports_0_dirty)) && (! MmuPlugin_ports_0_cacheHit))}; |
| always @(*) begin |
| _zz_MmuPlugin_shared_refills_1[0] = _zz_MmuPlugin_shared_refills[1]; |
| _zz_MmuPlugin_shared_refills_1[1] = _zz_MmuPlugin_shared_refills[0]; |
| end |
| |
| assign _zz_MmuPlugin_shared_refills_2 = (_zz_MmuPlugin_shared_refills_1 & (~ _zz__zz_MmuPlugin_shared_refills_2)); |
| always @(*) begin |
| _zz_MmuPlugin_shared_refills_3[0] = _zz_MmuPlugin_shared_refills_2[1]; |
| _zz_MmuPlugin_shared_refills_3[1] = _zz_MmuPlugin_shared_refills_2[0]; |
| end |
| |
| assign MmuPlugin_shared_refills = _zz_MmuPlugin_shared_refills_3; |
| assign when_MmuPlugin_l217 = (|MmuPlugin_shared_refills); |
| assign _zz_MmuPlugin_shared_vpn_0 = (MmuPlugin_shared_refills[0] ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress : DBusCachedPlugin_mmuBus_cmd_0_virtualAddress); |
| assign when_MmuPlugin_l243 = (MmuPlugin_shared_dBusRsp_leaf || MmuPlugin_shared_dBusRsp_exception); |
| assign IBusCachedPlugin_mmuBus_busy = ((MmuPlugin_shared_state_1 != MmuPlugin_shared_State_IDLE) && MmuPlugin_shared_portSortedOh[0]); |
| assign DBusCachedPlugin_mmuBus_busy = ((MmuPlugin_shared_state_1 != MmuPlugin_shared_State_IDLE) && MmuPlugin_shared_portSortedOh[1]); |
| assign when_MmuPlugin_l272 = ((MmuPlugin_shared_dBusRspStaged_valid && (! MmuPlugin_shared_dBusRspStaged_payload_redo)) && (MmuPlugin_shared_dBusRsp_leaf || MmuPlugin_shared_dBusRsp_exception)); |
| assign when_MmuPlugin_l274 = MmuPlugin_shared_portSortedOh[0]; |
| assign when_MmuPlugin_l280 = (MmuPlugin_ports_0_entryToReplace_value == 2'b00); |
| assign when_MmuPlugin_l280_1 = (MmuPlugin_ports_0_entryToReplace_value == 2'b01); |
| assign when_MmuPlugin_l280_2 = (MmuPlugin_ports_0_entryToReplace_value == 2'b10); |
| assign when_MmuPlugin_l280_3 = (MmuPlugin_ports_0_entryToReplace_value == 2'b11); |
| assign when_MmuPlugin_l274_1 = MmuPlugin_shared_portSortedOh[1]; |
| assign when_MmuPlugin_l280_4 = (MmuPlugin_ports_1_entryToReplace_value == 2'b00); |
| assign when_MmuPlugin_l280_5 = (MmuPlugin_ports_1_entryToReplace_value == 2'b01); |
| assign when_MmuPlugin_l280_6 = (MmuPlugin_ports_1_entryToReplace_value == 2'b10); |
| assign when_MmuPlugin_l280_7 = (MmuPlugin_ports_1_entryToReplace_value == 2'b11); |
| assign when_MmuPlugin_l304 = ((execute_arbitration_isValid && execute_arbitration_isFiring) && execute_IS_SFENCE_VMA2); |
| assign when_Pipeline_l124 = (! execute_arbitration_isStuck); |
| assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck); |
| assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)); |
| assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck); |
| assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck); |
| assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck); |
| assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck); |
| assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck); |
| assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck); |
| assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck); |
| assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1; |
| assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck); |
| assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck); |
| assign when_Pipeline_l124_12 = (! memory_arbitration_isStuck); |
| assign when_Pipeline_l124_13 = (! writeBack_arbitration_isStuck); |
| assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL; |
| assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1; |
| assign when_Pipeline_l124_14 = (! execute_arbitration_isStuck); |
| assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL; |
| assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1; |
| assign when_Pipeline_l124_15 = (! execute_arbitration_isStuck); |
| assign when_Pipeline_l124_16 = (! memory_arbitration_isStuck); |
| assign when_Pipeline_l124_17 = (! writeBack_arbitration_isStuck); |
| assign when_Pipeline_l124_18 = (! execute_arbitration_isStuck); |
| assign when_Pipeline_l124_19 = (! execute_arbitration_isStuck); |
| assign when_Pipeline_l124_20 = (! memory_arbitration_isStuck); |
| assign when_Pipeline_l124_21 = (! execute_arbitration_isStuck); |
| assign when_Pipeline_l124_22 = (! memory_arbitration_isStuck); |
| assign when_Pipeline_l124_23 = (! writeBack_arbitration_isStuck); |
| assign when_Pipeline_l124_24 = (! execute_arbitration_isStuck); |
| assign when_Pipeline_l124_25 = (! execute_arbitration_isStuck); |
| assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL; |
| assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1; |
| assign when_Pipeline_l124_26 = (! execute_arbitration_isStuck); |
| assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL; |
| assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL; |
| assign _zz_execute_to_memory_SHIFT_CTRL_1 = execute_SHIFT_CTRL; |
| assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1; |
| assign when_Pipeline_l124_27 = (! execute_arbitration_isStuck); |
| assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL; |
| assign when_Pipeline_l124_28 = (! memory_arbitration_isStuck); |
| assign _zz_memory_SHIFT_CTRL = execute_to_memory_SHIFT_CTRL; |
| assign when_Pipeline_l124_29 = (! execute_arbitration_isStuck); |
| assign when_Pipeline_l124_30 = (! memory_arbitration_isStuck); |
| assign when_Pipeline_l124_31 = (! writeBack_arbitration_isStuck); |
| assign when_Pipeline_l124_32 = (! execute_arbitration_isStuck); |
| assign when_Pipeline_l124_33 = (! memory_arbitration_isStuck); |
| assign when_Pipeline_l124_34 = (! execute_arbitration_isStuck); |
| assign when_Pipeline_l124_35 = (! execute_arbitration_isStuck); |
| assign when_Pipeline_l124_36 = (! execute_arbitration_isStuck); |
| assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL; |
| assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL; |
| assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL; |
| assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1; |
| assign when_Pipeline_l124_37 = (! execute_arbitration_isStuck); |
| assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL; |
| assign when_Pipeline_l124_38 = (! memory_arbitration_isStuck); |
| assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL; |
| assign when_Pipeline_l124_39 = (! writeBack_arbitration_isStuck); |
| assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL; |
| assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL; |
| assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1; |
| assign when_Pipeline_l124_40 = (! execute_arbitration_isStuck); |
| assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL; |
| assign when_Pipeline_l124_41 = (! execute_arbitration_isStuck); |
| assign when_Pipeline_l124_42 = (! execute_arbitration_isStuck); |
| assign when_Pipeline_l124_43 = (! execute_arbitration_isStuck); |
| assign when_Pipeline_l124_44 = (! execute_arbitration_isStuck); |
| assign when_Pipeline_l124_45 = (! execute_arbitration_isStuck); |
| assign when_Pipeline_l124_46 = (! execute_arbitration_isStuck); |
| assign when_Pipeline_l124_47 = (! execute_arbitration_isStuck); |
| assign when_Pipeline_l124_48 = (! execute_arbitration_isStuck); |
| assign when_Pipeline_l124_49 = (! execute_arbitration_isStuck); |
| assign when_Pipeline_l124_50 = (! memory_arbitration_isStuck); |
| assign when_Pipeline_l124_51 = (! writeBack_arbitration_isStuck); |
| assign when_Pipeline_l124_52 = (! memory_arbitration_isStuck); |
| assign when_Pipeline_l124_53 = (! writeBack_arbitration_isStuck); |
| assign when_Pipeline_l124_54 = (! memory_arbitration_isStuck); |
| assign when_Pipeline_l124_55 = (! writeBack_arbitration_isStuck); |
| assign when_Pipeline_l124_56 = (! memory_arbitration_isStuck); |
| assign when_Pipeline_l124_57 = (! memory_arbitration_isStuck); |
| assign when_Pipeline_l124_58 = (! memory_arbitration_isStuck); |
| assign when_Pipeline_l124_59 = (! memory_arbitration_isStuck); |
| assign when_Pipeline_l124_60 = (! memory_arbitration_isStuck); |
| assign when_Pipeline_l124_61 = (! writeBack_arbitration_isStuck); |
| assign when_Pipeline_l124_62 = (! writeBack_arbitration_isStuck); |
| assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); |
| assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); |
| assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); |
| assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); |
| assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); |
| assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); |
| assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); |
| assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); |
| assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); |
| assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); |
| assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); |
| assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); |
| assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); |
| assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); |
| assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); |
| assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); |
| assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); |
| assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); |
| assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); |
| assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); |
| assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); |
| assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); |
| assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); |
| assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); |
| assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt); |
| assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); |
| always @(*) begin |
| IBusCachedPlugin_injectionPort_ready = 1'b0; |
| case(switch_Fetcher_l362) |
| 3'b100 : begin |
| IBusCachedPlugin_injectionPort_ready = 1'b1; |
| end |
| default : begin |
| end |
| endcase |
| end |
| |
| assign when_Fetcher_l378 = (! decode_arbitration_isStuck); |
| assign when_CsrPlugin_l1264 = (! execute_arbitration_isStuck); |
| assign when_CsrPlugin_l1264_1 = (! execute_arbitration_isStuck); |
| assign when_CsrPlugin_l1264_2 = (! execute_arbitration_isStuck); |
| assign when_CsrPlugin_l1264_3 = (! execute_arbitration_isStuck); |
| assign when_CsrPlugin_l1264_4 = (! execute_arbitration_isStuck); |
| assign when_CsrPlugin_l1264_5 = (! execute_arbitration_isStuck); |
| assign when_CsrPlugin_l1264_6 = (! execute_arbitration_isStuck); |
| assign when_CsrPlugin_l1264_7 = (! execute_arbitration_isStuck); |
| assign when_CsrPlugin_l1264_8 = (! execute_arbitration_isStuck); |
| assign when_CsrPlugin_l1264_9 = (! execute_arbitration_isStuck); |
| assign when_CsrPlugin_l1264_10 = (! execute_arbitration_isStuck); |
| assign when_CsrPlugin_l1264_11 = (! execute_arbitration_isStuck); |
| assign when_CsrPlugin_l1264_12 = (! execute_arbitration_isStuck); |
| always @(*) begin |
| _zz_CsrPlugin_csrMapping_readDataInit = 32'h0; |
| if(execute_CsrPlugin_csr_768) begin |
| _zz_CsrPlugin_csrMapping_readDataInit[12 : 11] = CsrPlugin_mstatus_MPP; |
| _zz_CsrPlugin_csrMapping_readDataInit[7 : 7] = CsrPlugin_mstatus_MPIE; |
| _zz_CsrPlugin_csrMapping_readDataInit[3 : 3] = CsrPlugin_mstatus_MIE; |
| _zz_CsrPlugin_csrMapping_readDataInit[19 : 19] = MmuPlugin_status_mxr; |
| _zz_CsrPlugin_csrMapping_readDataInit[18 : 18] = MmuPlugin_status_sum; |
| _zz_CsrPlugin_csrMapping_readDataInit[17 : 17] = MmuPlugin_status_mprv; |
| end |
| end |
| |
| always @(*) begin |
| _zz_CsrPlugin_csrMapping_readDataInit_1 = 32'h0; |
| if(execute_CsrPlugin_csr_836) begin |
| _zz_CsrPlugin_csrMapping_readDataInit_1[11 : 11] = CsrPlugin_mip_MEIP; |
| _zz_CsrPlugin_csrMapping_readDataInit_1[7 : 7] = CsrPlugin_mip_MTIP; |
| _zz_CsrPlugin_csrMapping_readDataInit_1[3 : 3] = CsrPlugin_mip_MSIP; |
| end |
| end |
| |
| always @(*) begin |
| _zz_CsrPlugin_csrMapping_readDataInit_2 = 32'h0; |
| if(execute_CsrPlugin_csr_772) begin |
| _zz_CsrPlugin_csrMapping_readDataInit_2[11 : 11] = CsrPlugin_mie_MEIE; |
| _zz_CsrPlugin_csrMapping_readDataInit_2[7 : 7] = CsrPlugin_mie_MTIE; |
| _zz_CsrPlugin_csrMapping_readDataInit_2[3 : 3] = CsrPlugin_mie_MSIE; |
| end |
| end |
| |
| always @(*) begin |
| _zz_CsrPlugin_csrMapping_readDataInit_3 = 32'h0; |
| if(execute_CsrPlugin_csr_773) begin |
| _zz_CsrPlugin_csrMapping_readDataInit_3[31 : 2] = CsrPlugin_mtvec_base; |
| _zz_CsrPlugin_csrMapping_readDataInit_3[1 : 0] = CsrPlugin_mtvec_mode; |
| end |
| end |
| |
| always @(*) begin |
| _zz_CsrPlugin_csrMapping_readDataInit_4 = 32'h0; |
| if(execute_CsrPlugin_csr_833) begin |
| _zz_CsrPlugin_csrMapping_readDataInit_4[31 : 0] = CsrPlugin_mepc; |
| end |
| end |
| |
| always @(*) begin |
| _zz_CsrPlugin_csrMapping_readDataInit_5 = 32'h0; |
| if(execute_CsrPlugin_csr_834) begin |
| _zz_CsrPlugin_csrMapping_readDataInit_5[31 : 31] = CsrPlugin_mcause_interrupt; |
| _zz_CsrPlugin_csrMapping_readDataInit_5[3 : 0] = CsrPlugin_mcause_exceptionCode; |
| end |
| end |
| |
| always @(*) begin |
| _zz_CsrPlugin_csrMapping_readDataInit_6 = 32'h0; |
| if(execute_CsrPlugin_csr_835) begin |
| _zz_CsrPlugin_csrMapping_readDataInit_6[31 : 0] = CsrPlugin_mtval; |
| end |
| end |
| |
| always @(*) begin |
| _zz_CsrPlugin_csrMapping_readDataInit_7 = 32'h0; |
| if(execute_CsrPlugin_csr_2816) begin |
| _zz_CsrPlugin_csrMapping_readDataInit_7[31 : 0] = CsrPlugin_mcycle[31 : 0]; |
| end |
| end |
| |
| always @(*) begin |
| _zz_CsrPlugin_csrMapping_readDataInit_8 = 32'h0; |
| if(execute_CsrPlugin_csr_2944) begin |
| _zz_CsrPlugin_csrMapping_readDataInit_8[31 : 0] = CsrPlugin_mcycle[63 : 32]; |
| end |
| end |
| |
| always @(*) begin |
| _zz_CsrPlugin_csrMapping_readDataInit_9 = 32'h0; |
| if(execute_CsrPlugin_csr_3072) begin |
| _zz_CsrPlugin_csrMapping_readDataInit_9[31 : 0] = CsrPlugin_mcycle[31 : 0]; |
| end |
| end |
| |
| always @(*) begin |
| _zz_CsrPlugin_csrMapping_readDataInit_10 = 32'h0; |
| if(execute_CsrPlugin_csr_3200) begin |
| _zz_CsrPlugin_csrMapping_readDataInit_10[31 : 0] = CsrPlugin_mcycle[63 : 32]; |
| end |
| end |
| |
| always @(*) begin |
| _zz_CsrPlugin_csrMapping_readDataInit_11 = 32'h0; |
| if(execute_CsrPlugin_csr_256) begin |
| _zz_CsrPlugin_csrMapping_readDataInit_11[19 : 19] = MmuPlugin_status_mxr; |
| _zz_CsrPlugin_csrMapping_readDataInit_11[18 : 18] = MmuPlugin_status_sum; |
| _zz_CsrPlugin_csrMapping_readDataInit_11[17 : 17] = MmuPlugin_status_mprv; |
| end |
| end |
| |
| always @(*) begin |
| _zz_CsrPlugin_csrMapping_readDataInit_12 = 32'h0; |
| if(execute_CsrPlugin_csr_384) begin |
| _zz_CsrPlugin_csrMapping_readDataInit_12[31 : 31] = MmuPlugin_satp_mode; |
| _zz_CsrPlugin_csrMapping_readDataInit_12[30 : 22] = MmuPlugin_satp_asid; |
| _zz_CsrPlugin_csrMapping_readDataInit_12[19 : 0] = MmuPlugin_satp_ppn; |
| end |
| end |
| |
| assign CsrPlugin_csrMapping_readDataInit = ((((_zz_CsrPlugin_csrMapping_readDataInit | _zz_CsrPlugin_csrMapping_readDataInit_1) | (_zz_CsrPlugin_csrMapping_readDataInit_2 | _zz_CsrPlugin_csrMapping_readDataInit_3)) | ((_zz_CsrPlugin_csrMapping_readDataInit_4 | _zz_CsrPlugin_csrMapping_readDataInit_5) | (_zz_CsrPlugin_csrMapping_readDataInit_6 | _zz_CsrPlugin_csrMapping_readDataInit_7))) | (((_zz_CsrPlugin_csrMapping_readDataInit_8 | _zz_CsrPlugin_csrMapping_readDataInit_9) | (_zz_CsrPlugin_csrMapping_readDataInit_10 | _zz_CsrPlugin_csrMapping_readDataInit_11)) | _zz_CsrPlugin_csrMapping_readDataInit_12)); |
| assign when_CsrPlugin_l1297 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); |
| assign when_CsrPlugin_l1302 = ((! execute_arbitration_isValid) || (! execute_IS_CSR)); |
| assign iBusWishbone_ADR = {_zz_iBusWishbone_ADR_1,_zz_iBusWishbone_ADR}; |
| assign iBusWishbone_CTI = ((_zz_iBusWishbone_ADR == 3'b111) ? 3'b111 : 3'b010); |
| assign iBusWishbone_BTE = 2'b00; |
| assign iBusWishbone_SEL = 4'b1111; |
| assign iBusWishbone_WE = 1'b0; |
| assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; |
| always @(*) begin |
| iBusWishbone_CYC = 1'b0; |
| if(when_InstructionCache_l239) begin |
| iBusWishbone_CYC = 1'b1; |
| end |
| end |
| |
| always @(*) begin |
| iBusWishbone_STB = 1'b0; |
| if(when_InstructionCache_l239) begin |
| iBusWishbone_STB = 1'b1; |
| end |
| end |
| |
| assign when_InstructionCache_l239 = (iBus_cmd_valid || (_zz_iBusWishbone_ADR != 3'b000)); |
| assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); |
| assign iBus_rsp_valid = _zz_iBus_rsp_valid; |
| assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; |
| assign iBus_rsp_payload_error = 1'b0; |
| assign _zz_dBus_cmd_ready_5 = (dBus_cmd_payload_size == 3'b101); |
| assign _zz_dBus_cmd_ready_1 = dBus_cmd_valid; |
| assign _zz_dBus_cmd_ready_3 = dBus_cmd_payload_wr; |
| assign _zz_dBus_cmd_ready_4 = ((! _zz_dBus_cmd_ready_5) || (_zz_dBus_cmd_ready == 3'b111)); |
| assign dBus_cmd_ready = (_zz_dBus_cmd_ready_2 && (_zz_dBus_cmd_ready_3 || _zz_dBus_cmd_ready_4)); |
| assign dBusWishbone_ADR = ((_zz_dBus_cmd_ready_5 ? {{dBus_cmd_payload_address[31 : 5],_zz_dBus_cmd_ready},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); |
| assign dBusWishbone_CTI = (_zz_dBus_cmd_ready_5 ? (_zz_dBus_cmd_ready_4 ? 3'b111 : 3'b010) : 3'b000); |
| assign dBusWishbone_BTE = 2'b00; |
| assign dBusWishbone_SEL = (_zz_dBus_cmd_ready_3 ? dBus_cmd_payload_mask : 4'b1111); |
| assign dBusWishbone_WE = _zz_dBus_cmd_ready_3; |
| assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; |
| assign _zz_dBus_cmd_ready_2 = (_zz_dBus_cmd_ready_1 && dBusWishbone_ACK); |
| assign dBusWishbone_CYC = _zz_dBus_cmd_ready_1; |
| assign dBusWishbone_STB = _zz_dBus_cmd_ready_1; |
| assign dBus_rsp_valid = _zz_dBus_rsp_valid; |
| assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; |
| assign dBus_rsp_payload_error = 1'b0; |
| assign debug_bus_cmd_valid = systemDebugger_1_io_mem_cmd_valid; |
| assign debug_bus_cmd_payload_wr = systemDebugger_1_io_mem_cmd_payload_wr; |
| assign debug_bus_cmd_payload_data = systemDebugger_1_io_mem_cmd_payload_data; |
| assign debug_bus_cmd_payload_address = systemDebugger_1_io_mem_cmd_payload_address[7:0]; |
| assign debug_bus_cmd_fire = (debug_bus_cmd_valid && debug_bus_cmd_ready); |
| assign jtag_tdo = jtagBridge_1_io_jtag_tdo; |
| always @(posedge clk or posedge reset) begin |
| if(reset) begin |
| IBusCachedPlugin_fetchPc_pcReg <= 32'h30000000; |
| IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; |
| IBusCachedPlugin_fetchPc_booted <= 1'b0; |
| IBusCachedPlugin_fetchPc_inc <= 1'b0; |
| _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; |
| _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; |
| IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; |
| IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; |
| IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; |
| IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; |
| IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; |
| IBusCachedPlugin_rspCounter <= _zz_IBusCachedPlugin_rspCounter; |
| IBusCachedPlugin_rspCounter <= 32'h0; |
| dataCache_1_io_mem_cmd_rValid <= 1'b0; |
| DBusCachedPlugin_rspCounter <= _zz_DBusCachedPlugin_rspCounter; |
| DBusCachedPlugin_rspCounter <= 32'h0; |
| _zz_2 <= 1'b1; |
| memory_DivPlugin_div_counter_value <= 6'h0; |
| HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; |
| CsrPlugin_mtvec_mode <= 2'b00; |
| CsrPlugin_mtvec_base <= 30'h0c000000; |
| CsrPlugin_mstatus_MIE <= 1'b0; |
| CsrPlugin_mstatus_MPIE <= 1'b0; |
| CsrPlugin_mstatus_MPP <= 2'b11; |
| CsrPlugin_mie_MEIE <= 1'b0; |
| CsrPlugin_mie_MTIE <= 1'b0; |
| CsrPlugin_mie_MSIE <= 1'b0; |
| CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; |
| CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; |
| CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; |
| CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; |
| CsrPlugin_interrupt_valid <= 1'b0; |
| CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; |
| CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; |
| CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; |
| CsrPlugin_hadException <= 1'b0; |
| execute_CsrPlugin_wfiWake <= 1'b0; |
| MmuPlugin_status_sum <= 1'b0; |
| MmuPlugin_status_mxr <= 1'b0; |
| MmuPlugin_status_mprv <= 1'b0; |
| MmuPlugin_satp_mode <= 1'b0; |
| MmuPlugin_ports_0_cache_0_valid <= 1'b0; |
| MmuPlugin_ports_0_cache_1_valid <= 1'b0; |
| MmuPlugin_ports_0_cache_2_valid <= 1'b0; |
| MmuPlugin_ports_0_cache_3_valid <= 1'b0; |
| MmuPlugin_ports_0_entryToReplace_value <= 2'b00; |
| MmuPlugin_ports_1_cache_0_valid <= 1'b0; |
| MmuPlugin_ports_1_cache_1_valid <= 1'b0; |
| MmuPlugin_ports_1_cache_2_valid <= 1'b0; |
| MmuPlugin_ports_1_cache_3_valid <= 1'b0; |
| MmuPlugin_ports_1_entryToReplace_value <= 2'b00; |
| MmuPlugin_shared_state_1 <= MmuPlugin_shared_State_IDLE; |
| MmuPlugin_shared_dBusRspStaged_valid <= 1'b0; |
| execute_arbitration_isValid <= 1'b0; |
| memory_arbitration_isValid <= 1'b0; |
| writeBack_arbitration_isValid <= 1'b0; |
| switch_Fetcher_l362 <= 3'b000; |
| execute_to_memory_IS_DBUS_SHARING <= 1'b0; |
| memory_to_writeBack_IS_DBUS_SHARING <= 1'b0; |
| _zz_iBusWishbone_ADR <= 3'b000; |
| _zz_iBus_rsp_valid <= 1'b0; |
| _zz_dBus_cmd_ready <= 3'b000; |
| _zz_dBus_rsp_valid <= 1'b0; |
| end else begin |
| if(IBusCachedPlugin_fetchPc_correction) begin |
| IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; |
| end |
| if(IBusCachedPlugin_fetchPc_output_fire) begin |
| IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; |
| end |
| IBusCachedPlugin_fetchPc_booted <= 1'b1; |
| if(when_Fetcher_l131) begin |
| IBusCachedPlugin_fetchPc_inc <= 1'b0; |
| end |
| if(IBusCachedPlugin_fetchPc_output_fire_1) begin |
| IBusCachedPlugin_fetchPc_inc <= 1'b1; |
| end |
| if(when_Fetcher_l131_1) begin |
| IBusCachedPlugin_fetchPc_inc <= 1'b0; |
| end |
| if(when_Fetcher_l158) begin |
| IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; |
| end |
| if(IBusCachedPlugin_iBusRsp_flush) begin |
| _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; |
| end |
| if(_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready) begin |
| _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); |
| end |
| if(IBusCachedPlugin_iBusRsp_flush) begin |
| _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; |
| end |
| if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin |
| _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); |
| end |
| if(IBusCachedPlugin_fetchPc_flushed) begin |
| IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; |
| end |
| if(when_Fetcher_l329) begin |
| IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; |
| end |
| if(IBusCachedPlugin_fetchPc_flushed) begin |
| IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; |
| end |
| if(when_Fetcher_l329_1) begin |
| IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; |
| end |
| if(IBusCachedPlugin_fetchPc_flushed) begin |
| IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; |
| end |
| if(IBusCachedPlugin_fetchPc_flushed) begin |
| IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; |
| end |
| if(when_Fetcher_l329_2) begin |
| IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; |
| end |
| if(IBusCachedPlugin_fetchPc_flushed) begin |
| IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; |
| end |
| if(IBusCachedPlugin_fetchPc_flushed) begin |
| IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; |
| end |
| if(when_Fetcher_l329_3) begin |
| IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; |
| end |
| if(IBusCachedPlugin_fetchPc_flushed) begin |
| IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; |
| end |
| if(IBusCachedPlugin_fetchPc_flushed) begin |
| IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; |
| end |
| if(when_Fetcher_l329_4) begin |
| IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; |
| end |
| if(IBusCachedPlugin_fetchPc_flushed) begin |
| IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; |
| end |
| if(iBus_rsp_valid) begin |
| IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); |
| end |
| if(dataCache_1_io_mem_cmd_ready) begin |
| dataCache_1_io_mem_cmd_rValid <= dataCache_1_io_mem_cmd_valid; |
| end |
| if(dBus_rsp_valid) begin |
| DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); |
| end |
| _zz_2 <= 1'b0; |
| memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; |
| HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; |
| if(when_CsrPlugin_l909) begin |
| CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; |
| end else begin |
| CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; |
| end |
| if(when_CsrPlugin_l909_1) begin |
| CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); |
| end else begin |
| CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; |
| end |
| if(when_CsrPlugin_l909_2) begin |
| CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); |
| end else begin |
| CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; |
| end |
| if(when_CsrPlugin_l909_3) begin |
| CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); |
| end else begin |
| CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; |
| end |
| CsrPlugin_interrupt_valid <= 1'b0; |
| if(when_CsrPlugin_l946) begin |
| if(when_CsrPlugin_l952) begin |
| CsrPlugin_interrupt_valid <= 1'b1; |
| end |
| if(when_CsrPlugin_l952_1) begin |
| CsrPlugin_interrupt_valid <= 1'b1; |
| end |
| if(when_CsrPlugin_l952_2) begin |
| CsrPlugin_interrupt_valid <= 1'b1; |
| end |
| end |
| if(CsrPlugin_pipelineLiberator_active) begin |
| if(when_CsrPlugin_l980) begin |
| CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; |
| end |
| if(when_CsrPlugin_l980_1) begin |
| CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; |
| end |
| if(when_CsrPlugin_l980_2) begin |
| CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; |
| end |
| end |
| if(when_CsrPlugin_l985) begin |
| CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; |
| CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; |
| CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; |
| end |
| if(CsrPlugin_interruptJump) begin |
| CsrPlugin_interrupt_valid <= 1'b0; |
| end |
| CsrPlugin_hadException <= CsrPlugin_exception; |
| if(when_CsrPlugin_l1019) begin |
| case(CsrPlugin_targetPrivilege) |
| 2'b11 : begin |
| CsrPlugin_mstatus_MIE <= 1'b0; |
| CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; |
| CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; |
| end |
| default : begin |
| end |
| endcase |
| end |
| if(when_CsrPlugin_l1064) begin |
| case(switch_CsrPlugin_l1068) |
| 2'b11 : begin |
| CsrPlugin_mstatus_MPP <= 2'b00; |
| CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; |
| CsrPlugin_mstatus_MPIE <= 1'b1; |
| end |
| default : begin |
| end |
| endcase |
| end |
| execute_CsrPlugin_wfiWake <= (({_zz_when_CsrPlugin_l952_2,{_zz_when_CsrPlugin_l952_1,_zz_when_CsrPlugin_l952}} != 3'b000) || CsrPlugin_thirdPartyWake); |
| MmuPlugin_ports_0_entryToReplace_value <= MmuPlugin_ports_0_entryToReplace_valueNext; |
| if(contextSwitching) begin |
| if(MmuPlugin_ports_0_cache_0_exception) begin |
| MmuPlugin_ports_0_cache_0_valid <= 1'b0; |
| end |
| if(MmuPlugin_ports_0_cache_1_exception) begin |
| MmuPlugin_ports_0_cache_1_valid <= 1'b0; |
| end |
| if(MmuPlugin_ports_0_cache_2_exception) begin |
| MmuPlugin_ports_0_cache_2_valid <= 1'b0; |
| end |
| if(MmuPlugin_ports_0_cache_3_exception) begin |
| MmuPlugin_ports_0_cache_3_valid <= 1'b0; |
| end |
| end |
| MmuPlugin_ports_1_entryToReplace_value <= MmuPlugin_ports_1_entryToReplace_valueNext; |
| if(contextSwitching) begin |
| if(MmuPlugin_ports_1_cache_0_exception) begin |
| MmuPlugin_ports_1_cache_0_valid <= 1'b0; |
| end |
| if(MmuPlugin_ports_1_cache_1_exception) begin |
| MmuPlugin_ports_1_cache_1_valid <= 1'b0; |
| end |
| if(MmuPlugin_ports_1_cache_2_exception) begin |
| MmuPlugin_ports_1_cache_2_valid <= 1'b0; |
| end |
| if(MmuPlugin_ports_1_cache_3_exception) begin |
| MmuPlugin_ports_1_cache_3_valid <= 1'b0; |
| end |
| end |
| MmuPlugin_shared_dBusRspStaged_valid <= MmuPlugin_dBusAccess_rsp_valid; |
| case(MmuPlugin_shared_state_1) |
| MmuPlugin_shared_State_IDLE : begin |
| if(when_MmuPlugin_l217) begin |
| MmuPlugin_shared_state_1 <= MmuPlugin_shared_State_L1_CMD; |
| end |
| end |
| MmuPlugin_shared_State_L1_CMD : begin |
| if(MmuPlugin_dBusAccess_cmd_ready) begin |
| MmuPlugin_shared_state_1 <= MmuPlugin_shared_State_L1_RSP; |
| end |
| end |
| MmuPlugin_shared_State_L1_RSP : begin |
| if(MmuPlugin_shared_dBusRspStaged_valid) begin |
| MmuPlugin_shared_state_1 <= MmuPlugin_shared_State_L0_CMD; |
| if(when_MmuPlugin_l243) begin |
| MmuPlugin_shared_state_1 <= MmuPlugin_shared_State_IDLE; |
| end |
| if(MmuPlugin_shared_dBusRspStaged_payload_redo) begin |
| MmuPlugin_shared_state_1 <= MmuPlugin_shared_State_L1_CMD; |
| end |
| end |
| end |
| MmuPlugin_shared_State_L0_CMD : begin |
| if(MmuPlugin_dBusAccess_cmd_ready) begin |
| MmuPlugin_shared_state_1 <= MmuPlugin_shared_State_L0_RSP; |
| end |
| end |
| default : begin |
| if(MmuPlugin_shared_dBusRspStaged_valid) begin |
| MmuPlugin_shared_state_1 <= MmuPlugin_shared_State_IDLE; |
| if(MmuPlugin_shared_dBusRspStaged_payload_redo) begin |
| MmuPlugin_shared_state_1 <= MmuPlugin_shared_State_L0_CMD; |
| end |
| end |
| end |
| endcase |
| if(when_MmuPlugin_l272) begin |
| if(when_MmuPlugin_l274) begin |
| if(when_MmuPlugin_l280) begin |
| MmuPlugin_ports_0_cache_0_valid <= 1'b1; |
| end |
| if(when_MmuPlugin_l280_1) begin |
| MmuPlugin_ports_0_cache_1_valid <= 1'b1; |
| end |
| if(when_MmuPlugin_l280_2) begin |
| MmuPlugin_ports_0_cache_2_valid <= 1'b1; |
| end |
| if(when_MmuPlugin_l280_3) begin |
| MmuPlugin_ports_0_cache_3_valid <= 1'b1; |
| end |
| end |
| if(when_MmuPlugin_l274_1) begin |
| if(when_MmuPlugin_l280_4) begin |
| MmuPlugin_ports_1_cache_0_valid <= 1'b1; |
| end |
| if(when_MmuPlugin_l280_5) begin |
| MmuPlugin_ports_1_cache_1_valid <= 1'b1; |
| end |
| if(when_MmuPlugin_l280_6) begin |
| MmuPlugin_ports_1_cache_2_valid <= 1'b1; |
| end |
| if(when_MmuPlugin_l280_7) begin |
| MmuPlugin_ports_1_cache_3_valid <= 1'b1; |
| end |
| end |
| end |
| if(when_MmuPlugin_l304) begin |
| MmuPlugin_ports_0_cache_0_valid <= 1'b0; |
| MmuPlugin_ports_0_cache_1_valid <= 1'b0; |
| MmuPlugin_ports_0_cache_2_valid <= 1'b0; |
| MmuPlugin_ports_0_cache_3_valid <= 1'b0; |
| MmuPlugin_ports_1_cache_0_valid <= 1'b0; |
| MmuPlugin_ports_1_cache_1_valid <= 1'b0; |
| MmuPlugin_ports_1_cache_2_valid <= 1'b0; |
| MmuPlugin_ports_1_cache_3_valid <= 1'b0; |
| end |
| if(when_Pipeline_l124_52) begin |
| execute_to_memory_IS_DBUS_SHARING <= execute_IS_DBUS_SHARING; |
| end |
| if(when_Pipeline_l124_53) begin |
| memory_to_writeBack_IS_DBUS_SHARING <= memory_IS_DBUS_SHARING; |
| end |
| if(when_Pipeline_l151) begin |
| execute_arbitration_isValid <= 1'b0; |
| end |
| if(when_Pipeline_l154) begin |
| execute_arbitration_isValid <= decode_arbitration_isValid; |
| end |
| if(when_Pipeline_l151_1) begin |
| memory_arbitration_isValid <= 1'b0; |
| end |
| if(when_Pipeline_l154_1) begin |
| memory_arbitration_isValid <= execute_arbitration_isValid; |
| end |
| if(when_Pipeline_l151_2) begin |
| writeBack_arbitration_isValid <= 1'b0; |
| end |
| if(when_Pipeline_l154_2) begin |
| writeBack_arbitration_isValid <= memory_arbitration_isValid; |
| end |
| case(switch_Fetcher_l362) |
| 3'b000 : begin |
| if(IBusCachedPlugin_injectionPort_valid) begin |
| switch_Fetcher_l362 <= 3'b001; |
| end |
| end |
| 3'b001 : begin |
| switch_Fetcher_l362 <= 3'b010; |
| end |
| 3'b010 : begin |
| switch_Fetcher_l362 <= 3'b011; |
| end |
| 3'b011 : begin |
| if(when_Fetcher_l378) begin |
| switch_Fetcher_l362 <= 3'b100; |
| end |
| end |
| 3'b100 : begin |
| switch_Fetcher_l362 <= 3'b000; |
| end |
| default : begin |
| end |
| endcase |
| if(MmuPlugin_dBusAccess_rsp_valid) begin |
| memory_to_writeBack_IS_DBUS_SHARING <= 1'b0; |
| end |
| if(MmuPlugin_dBusAccess_rsp_valid) begin |
| memory_to_writeBack_IS_DBUS_SHARING <= 1'b0; |
| end |
| if(execute_CsrPlugin_csr_768) begin |
| if(execute_CsrPlugin_writeEnable) begin |
| CsrPlugin_mstatus_MPP <= CsrPlugin_csrMapping_writeDataSignal[12 : 11]; |
| CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7]; |
| CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3]; |
| MmuPlugin_status_mxr <= CsrPlugin_csrMapping_writeDataSignal[19]; |
| MmuPlugin_status_sum <= CsrPlugin_csrMapping_writeDataSignal[18]; |
| MmuPlugin_status_mprv <= CsrPlugin_csrMapping_writeDataSignal[17]; |
| end |
| end |
| if(execute_CsrPlugin_csr_772) begin |
| if(execute_CsrPlugin_writeEnable) begin |
| CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11]; |
| CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7]; |
| CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3]; |
| end |
| end |
| if(execute_CsrPlugin_csr_773) begin |
| if(execute_CsrPlugin_writeEnable) begin |
| CsrPlugin_mtvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2]; |
| CsrPlugin_mtvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0]; |
| end |
| end |
| if(execute_CsrPlugin_csr_256) begin |
| if(execute_CsrPlugin_writeEnable) begin |
| MmuPlugin_status_mxr <= CsrPlugin_csrMapping_writeDataSignal[19]; |
| MmuPlugin_status_sum <= CsrPlugin_csrMapping_writeDataSignal[18]; |
| MmuPlugin_status_mprv <= CsrPlugin_csrMapping_writeDataSignal[17]; |
| end |
| end |
| if(execute_CsrPlugin_csr_384) begin |
| if(execute_CsrPlugin_writeEnable) begin |
| MmuPlugin_satp_mode <= CsrPlugin_csrMapping_writeDataSignal[31]; |
| MmuPlugin_ports_0_cache_0_valid <= 1'b0; |
| MmuPlugin_ports_0_cache_1_valid <= 1'b0; |
| MmuPlugin_ports_0_cache_2_valid <= 1'b0; |
| MmuPlugin_ports_0_cache_3_valid <= 1'b0; |
| MmuPlugin_ports_1_cache_0_valid <= 1'b0; |
| MmuPlugin_ports_1_cache_1_valid <= 1'b0; |
| MmuPlugin_ports_1_cache_2_valid <= 1'b0; |
| MmuPlugin_ports_1_cache_3_valid <= 1'b0; |
| end |
| end |
| if(when_InstructionCache_l239) begin |
| if(iBusWishbone_ACK) begin |
| _zz_iBusWishbone_ADR <= (_zz_iBusWishbone_ADR + 3'b001); |
| end |
| end |
| _zz_iBus_rsp_valid <= (iBusWishbone_CYC && iBusWishbone_ACK); |
| if((_zz_dBus_cmd_ready_1 && _zz_dBus_cmd_ready_2)) begin |
| _zz_dBus_cmd_ready <= (_zz_dBus_cmd_ready + 3'b001); |
| if(_zz_dBus_cmd_ready_4) begin |
| _zz_dBus_cmd_ready <= 3'b000; |
| end |
| end |
| _zz_dBus_rsp_valid <= ((_zz_dBus_cmd_ready_1 && (! dBusWishbone_WE)) && dBusWishbone_ACK); |
| end |
| end |
| |
| always @(posedge clk) begin |
| if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin |
| _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; |
| end |
| if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin |
| IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; |
| end |
| if(IBusCachedPlugin_iBusRsp_stages_2_input_ready) begin |
| IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; |
| end |
| if(dataCache_1_io_mem_cmd_ready) begin |
| dataCache_1_io_mem_cmd_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; |
| dataCache_1_io_mem_cmd_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; |
| dataCache_1_io_mem_cmd_rData_address <= dataCache_1_io_mem_cmd_payload_address; |
| dataCache_1_io_mem_cmd_rData_data <= dataCache_1_io_mem_cmd_payload_data; |
| dataCache_1_io_mem_cmd_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; |
| dataCache_1_io_mem_cmd_rData_size <= dataCache_1_io_mem_cmd_payload_size; |
| dataCache_1_io_mem_cmd_rData_last <= dataCache_1_io_mem_cmd_payload_last; |
| end |
| if(when_MulDivIterativePlugin_l126) begin |
| memory_DivPlugin_div_done <= 1'b1; |
| end |
| if(when_MulDivIterativePlugin_l126_1) begin |
| memory_DivPlugin_div_done <= 1'b0; |
| end |
| if(when_MulDivIterativePlugin_l128) begin |
| if(when_MulDivIterativePlugin_l132) begin |
| memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; |
| memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; |
| if(when_MulDivIterativePlugin_l151) begin |
| memory_DivPlugin_div_result <= _zz_memory_DivPlugin_div_result_1[31:0]; |
| end |
| end |
| end |
| if(when_MulDivIterativePlugin_l162) begin |
| memory_DivPlugin_accumulator <= 65'h0; |
| memory_DivPlugin_rs1 <= ((_zz_memory_DivPlugin_rs1 ? (~ _zz_memory_DivPlugin_rs1_1) : _zz_memory_DivPlugin_rs1_1) + _zz_memory_DivPlugin_rs1_2); |
| memory_DivPlugin_rs2 <= ((_zz_memory_DivPlugin_rs2 ? (~ execute_RS2) : execute_RS2) + _zz_memory_DivPlugin_rs2_1); |
| memory_DivPlugin_div_needRevert <= ((_zz_memory_DivPlugin_rs1 ^ (_zz_memory_DivPlugin_rs2 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); |
| end |
| HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; |
| HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; |
| CsrPlugin_mip_MEIP <= externalInterrupt; |
| CsrPlugin_mip_MTIP <= timerInterrupt; |
| CsrPlugin_mip_MSIP <= softwareInterrupt; |
| CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); |
| if(writeBack_arbitration_isFiring) begin |
| CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); |
| end |
| if(_zz_when) begin |
| CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); |
| CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); |
| end |
| if(BranchPlugin_branchExceptionPort_valid) begin |
| CsrPlugin_exceptionPortCtrl_exceptionContext_code <= BranchPlugin_branchExceptionPort_payload_code; |
| CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= BranchPlugin_branchExceptionPort_payload_badAddr; |
| end |
| if(DBusCachedPlugin_exceptionBus_valid) begin |
| CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; |
| CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; |
| end |
| if(when_CsrPlugin_l946) begin |
| if(when_CsrPlugin_l952) begin |
| CsrPlugin_interrupt_code <= 4'b0111; |
| CsrPlugin_interrupt_targetPrivilege <= 2'b11; |
| end |
| if(when_CsrPlugin_l952_1) begin |
| CsrPlugin_interrupt_code <= 4'b0011; |
| CsrPlugin_interrupt_targetPrivilege <= 2'b11; |
| end |
| if(when_CsrPlugin_l952_2) begin |
| CsrPlugin_interrupt_code <= 4'b1011; |
| CsrPlugin_interrupt_targetPrivilege <= 2'b11; |
| end |
| end |
| if(when_CsrPlugin_l1019) begin |
| case(CsrPlugin_targetPrivilege) |
| 2'b11 : begin |
| CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); |
| CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; |
| CsrPlugin_mepc <= writeBack_PC; |
| if(CsrPlugin_hadException) begin |
| CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; |
| end |
| end |
| default : begin |
| end |
| endcase |
| end |
| MmuPlugin_shared_dBusRspStaged_payload_data <= MmuPlugin_dBusAccess_rsp_payload_data; |
| MmuPlugin_shared_dBusRspStaged_payload_error <= MmuPlugin_dBusAccess_rsp_payload_error; |
| MmuPlugin_shared_dBusRspStaged_payload_redo <= MmuPlugin_dBusAccess_rsp_payload_redo; |
| if(when_MmuPlugin_l205) begin |
| MmuPlugin_shared_pteBuffer_V <= MmuPlugin_shared_dBusRsp_pte_V; |
| MmuPlugin_shared_pteBuffer_R <= MmuPlugin_shared_dBusRsp_pte_R; |
| MmuPlugin_shared_pteBuffer_W <= MmuPlugin_shared_dBusRsp_pte_W; |
| MmuPlugin_shared_pteBuffer_X <= MmuPlugin_shared_dBusRsp_pte_X; |
| MmuPlugin_shared_pteBuffer_U <= MmuPlugin_shared_dBusRsp_pte_U; |
| MmuPlugin_shared_pteBuffer_G <= MmuPlugin_shared_dBusRsp_pte_G; |
| MmuPlugin_shared_pteBuffer_A <= MmuPlugin_shared_dBusRsp_pte_A; |
| MmuPlugin_shared_pteBuffer_D <= MmuPlugin_shared_dBusRsp_pte_D; |
| MmuPlugin_shared_pteBuffer_RSW <= MmuPlugin_shared_dBusRsp_pte_RSW; |
| MmuPlugin_shared_pteBuffer_PPN0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; |
| MmuPlugin_shared_pteBuffer_PPN1 <= MmuPlugin_shared_dBusRsp_pte_PPN1; |
| end |
| case(MmuPlugin_shared_state_1) |
| MmuPlugin_shared_State_IDLE : begin |
| if(when_MmuPlugin_l217) begin |
| MmuPlugin_shared_portSortedOh <= MmuPlugin_shared_refills; |
| MmuPlugin_shared_vpn_1 <= _zz_MmuPlugin_shared_vpn_0[31 : 22]; |
| MmuPlugin_shared_vpn_0 <= _zz_MmuPlugin_shared_vpn_0[21 : 12]; |
| end |
| end |
| MmuPlugin_shared_State_L1_CMD : begin |
| end |
| MmuPlugin_shared_State_L1_RSP : begin |
| end |
| MmuPlugin_shared_State_L0_CMD : begin |
| end |
| default : begin |
| end |
| endcase |
| if(when_MmuPlugin_l272) begin |
| if(when_MmuPlugin_l274) begin |
| if(when_MmuPlugin_l280) begin |
| MmuPlugin_ports_0_cache_0_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == MmuPlugin_shared_State_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); |
| MmuPlugin_ports_0_cache_0_virtualAddress_0 <= MmuPlugin_shared_vpn_0; |
| MmuPlugin_ports_0_cache_0_virtualAddress_1 <= MmuPlugin_shared_vpn_1; |
| MmuPlugin_ports_0_cache_0_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; |
| MmuPlugin_ports_0_cache_0_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; |
| MmuPlugin_ports_0_cache_0_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; |
| MmuPlugin_ports_0_cache_0_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; |
| MmuPlugin_ports_0_cache_0_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; |
| MmuPlugin_ports_0_cache_0_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; |
| MmuPlugin_ports_0_cache_0_superPage <= (MmuPlugin_shared_state_1 == MmuPlugin_shared_State_L1_RSP); |
| end |
| if(when_MmuPlugin_l280_1) begin |
| MmuPlugin_ports_0_cache_1_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == MmuPlugin_shared_State_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); |
| MmuPlugin_ports_0_cache_1_virtualAddress_0 <= MmuPlugin_shared_vpn_0; |
| MmuPlugin_ports_0_cache_1_virtualAddress_1 <= MmuPlugin_shared_vpn_1; |
| MmuPlugin_ports_0_cache_1_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; |
| MmuPlugin_ports_0_cache_1_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; |
| MmuPlugin_ports_0_cache_1_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; |
| MmuPlugin_ports_0_cache_1_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; |
| MmuPlugin_ports_0_cache_1_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; |
| MmuPlugin_ports_0_cache_1_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; |
| MmuPlugin_ports_0_cache_1_superPage <= (MmuPlugin_shared_state_1 == MmuPlugin_shared_State_L1_RSP); |
| end |
| if(when_MmuPlugin_l280_2) begin |
| MmuPlugin_ports_0_cache_2_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == MmuPlugin_shared_State_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); |
| MmuPlugin_ports_0_cache_2_virtualAddress_0 <= MmuPlugin_shared_vpn_0; |
| MmuPlugin_ports_0_cache_2_virtualAddress_1 <= MmuPlugin_shared_vpn_1; |
| MmuPlugin_ports_0_cache_2_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; |
| MmuPlugin_ports_0_cache_2_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; |
| MmuPlugin_ports_0_cache_2_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; |
| MmuPlugin_ports_0_cache_2_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; |
| MmuPlugin_ports_0_cache_2_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; |
| MmuPlugin_ports_0_cache_2_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; |
| MmuPlugin_ports_0_cache_2_superPage <= (MmuPlugin_shared_state_1 == MmuPlugin_shared_State_L1_RSP); |
| end |
| if(when_MmuPlugin_l280_3) begin |
| MmuPlugin_ports_0_cache_3_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == MmuPlugin_shared_State_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); |
| MmuPlugin_ports_0_cache_3_virtualAddress_0 <= MmuPlugin_shared_vpn_0; |
| MmuPlugin_ports_0_cache_3_virtualAddress_1 <= MmuPlugin_shared_vpn_1; |
| MmuPlugin_ports_0_cache_3_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; |
| MmuPlugin_ports_0_cache_3_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; |
| MmuPlugin_ports_0_cache_3_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; |
| MmuPlugin_ports_0_cache_3_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; |
| MmuPlugin_ports_0_cache_3_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; |
| MmuPlugin_ports_0_cache_3_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; |
| MmuPlugin_ports_0_cache_3_superPage <= (MmuPlugin_shared_state_1 == MmuPlugin_shared_State_L1_RSP); |
| end |
| end |
| if(when_MmuPlugin_l274_1) begin |
| if(when_MmuPlugin_l280_4) begin |
| MmuPlugin_ports_1_cache_0_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == MmuPlugin_shared_State_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); |
| MmuPlugin_ports_1_cache_0_virtualAddress_0 <= MmuPlugin_shared_vpn_0; |
| MmuPlugin_ports_1_cache_0_virtualAddress_1 <= MmuPlugin_shared_vpn_1; |
| MmuPlugin_ports_1_cache_0_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; |
| MmuPlugin_ports_1_cache_0_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; |
| MmuPlugin_ports_1_cache_0_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; |
| MmuPlugin_ports_1_cache_0_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; |
| MmuPlugin_ports_1_cache_0_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; |
| MmuPlugin_ports_1_cache_0_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; |
| MmuPlugin_ports_1_cache_0_superPage <= (MmuPlugin_shared_state_1 == MmuPlugin_shared_State_L1_RSP); |
| end |
| if(when_MmuPlugin_l280_5) begin |
| MmuPlugin_ports_1_cache_1_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == MmuPlugin_shared_State_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); |
| MmuPlugin_ports_1_cache_1_virtualAddress_0 <= MmuPlugin_shared_vpn_0; |
| MmuPlugin_ports_1_cache_1_virtualAddress_1 <= MmuPlugin_shared_vpn_1; |
| MmuPlugin_ports_1_cache_1_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; |
| MmuPlugin_ports_1_cache_1_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; |
| MmuPlugin_ports_1_cache_1_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; |
| MmuPlugin_ports_1_cache_1_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; |
| MmuPlugin_ports_1_cache_1_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; |
| MmuPlugin_ports_1_cache_1_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; |
| MmuPlugin_ports_1_cache_1_superPage <= (MmuPlugin_shared_state_1 == MmuPlugin_shared_State_L1_RSP); |
| end |
| if(when_MmuPlugin_l280_6) begin |
| MmuPlugin_ports_1_cache_2_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == MmuPlugin_shared_State_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); |
| MmuPlugin_ports_1_cache_2_virtualAddress_0 <= MmuPlugin_shared_vpn_0; |
| MmuPlugin_ports_1_cache_2_virtualAddress_1 <= MmuPlugin_shared_vpn_1; |
| MmuPlugin_ports_1_cache_2_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; |
| MmuPlugin_ports_1_cache_2_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; |
| MmuPlugin_ports_1_cache_2_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; |
| MmuPlugin_ports_1_cache_2_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; |
| MmuPlugin_ports_1_cache_2_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; |
| MmuPlugin_ports_1_cache_2_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; |
| MmuPlugin_ports_1_cache_2_superPage <= (MmuPlugin_shared_state_1 == MmuPlugin_shared_State_L1_RSP); |
| end |
| if(when_MmuPlugin_l280_7) begin |
| MmuPlugin_ports_1_cache_3_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == MmuPlugin_shared_State_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); |
| MmuPlugin_ports_1_cache_3_virtualAddress_0 <= MmuPlugin_shared_vpn_0; |
| MmuPlugin_ports_1_cache_3_virtualAddress_1 <= MmuPlugin_shared_vpn_1; |
| MmuPlugin_ports_1_cache_3_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; |
| MmuPlugin_ports_1_cache_3_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; |
| MmuPlugin_ports_1_cache_3_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; |
| MmuPlugin_ports_1_cache_3_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; |
| MmuPlugin_ports_1_cache_3_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; |
| MmuPlugin_ports_1_cache_3_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; |
| MmuPlugin_ports_1_cache_3_superPage <= (MmuPlugin_shared_state_1 == MmuPlugin_shared_State_L1_RSP); |
| end |
| end |
| end |
| if(when_Pipeline_l124) begin |
| decode_to_execute_PC <= _zz_decode_SRC2; |
| end |
| if(when_Pipeline_l124_1) begin |
| execute_to_memory_PC <= execute_PC; |
| end |
| if(when_Pipeline_l124_2) begin |
| memory_to_writeBack_PC <= memory_PC; |
| end |
| if(when_Pipeline_l124_3) begin |
| decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; |
| end |
| if(when_Pipeline_l124_4) begin |
| execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; |
| end |
| if(when_Pipeline_l124_5) begin |
| memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; |
| end |
| if(when_Pipeline_l124_6) begin |
| decode_to_execute_FORMAL_PC_NEXT <= decode_FORMAL_PC_NEXT; |
| end |
| if(when_Pipeline_l124_7) begin |
| execute_to_memory_FORMAL_PC_NEXT <= _zz_execute_to_memory_FORMAL_PC_NEXT; |
| end |
| if(when_Pipeline_l124_8) begin |
| memory_to_writeBack_FORMAL_PC_NEXT <= memory_FORMAL_PC_NEXT; |
| end |
| if(when_Pipeline_l124_9) begin |
| decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; |
| end |
| if(when_Pipeline_l124_10) begin |
| decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; |
| end |
| if(when_Pipeline_l124_11) begin |
| decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; |
| end |
| if(when_Pipeline_l124_12) begin |
| execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; |
| end |
| if(when_Pipeline_l124_13) begin |
| memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; |
| end |
| if(when_Pipeline_l124_14) begin |
| decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL; |
| end |
| if(when_Pipeline_l124_15) begin |
| decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; |
| end |
| if(when_Pipeline_l124_16) begin |
| execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; |
| end |
| if(when_Pipeline_l124_17) begin |
| memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; |
| end |
| if(when_Pipeline_l124_18) begin |
| decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; |
| end |
| if(when_Pipeline_l124_19) begin |
| decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; |
| end |
| if(when_Pipeline_l124_20) begin |
| execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; |
| end |
| if(when_Pipeline_l124_21) begin |
| decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; |
| end |
| if(when_Pipeline_l124_22) begin |
| execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; |
| end |
| if(when_Pipeline_l124_23) begin |
| memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; |
| end |
| if(when_Pipeline_l124_24) begin |
| decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; |
| end |
| if(when_Pipeline_l124_25) begin |
| decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; |
| end |
| if(when_Pipeline_l124_26) begin |
| decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL; |
| end |
| if(when_Pipeline_l124_27) begin |
| decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL; |
| end |
| if(when_Pipeline_l124_28) begin |
| execute_to_memory_SHIFT_CTRL <= _zz_execute_to_memory_SHIFT_CTRL; |
| end |
| if(when_Pipeline_l124_29) begin |
| decode_to_execute_IS_MUL <= decode_IS_MUL; |
| end |
| if(when_Pipeline_l124_30) begin |
| execute_to_memory_IS_MUL <= execute_IS_MUL; |
| end |
| if(when_Pipeline_l124_31) begin |
| memory_to_writeBack_IS_MUL <= memory_IS_MUL; |
| end |
| if(when_Pipeline_l124_32) begin |
| decode_to_execute_IS_DIV <= decode_IS_DIV; |
| end |
| if(when_Pipeline_l124_33) begin |
| execute_to_memory_IS_DIV <= execute_IS_DIV; |
| end |
| if(when_Pipeline_l124_34) begin |
| decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; |
| end |
| if(when_Pipeline_l124_35) begin |
| decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; |
| end |
| if(when_Pipeline_l124_36) begin |
| decode_to_execute_IS_CSR <= decode_IS_CSR; |
| end |
| if(when_Pipeline_l124_37) begin |
| decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL; |
| end |
| if(when_Pipeline_l124_38) begin |
| execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL; |
| end |
| if(when_Pipeline_l124_39) begin |
| memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL; |
| end |
| if(when_Pipeline_l124_40) begin |
| decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL; |
| end |
| if(when_Pipeline_l124_41) begin |
| decode_to_execute_IS_SFENCE_VMA2 <= decode_IS_SFENCE_VMA2; |
| end |
| if(when_Pipeline_l124_42) begin |
| decode_to_execute_RS1 <= _zz_decode_SRC1; |
| end |
| if(when_Pipeline_l124_43) begin |
| decode_to_execute_RS2 <= _zz_decode_SRC2_1; |
| end |
| if(when_Pipeline_l124_44) begin |
| decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; |
| end |
| if(when_Pipeline_l124_45) begin |
| decode_to_execute_SRC1 <= decode_SRC1; |
| end |
| if(when_Pipeline_l124_46) begin |
| decode_to_execute_SRC2 <= decode_SRC2; |
| end |
| if(when_Pipeline_l124_47) begin |
| decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; |
| end |
| if(when_Pipeline_l124_48) begin |
| decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; |
| end |
| if(when_Pipeline_l124_49) begin |
| decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; |
| end |
| if(when_Pipeline_l124_50) begin |
| execute_to_memory_MEMORY_STORE_DATA_RF <= execute_MEMORY_STORE_DATA_RF; |
| end |
| if(when_Pipeline_l124_51) begin |
| memory_to_writeBack_MEMORY_STORE_DATA_RF <= memory_MEMORY_STORE_DATA_RF; |
| end |
| if(when_Pipeline_l124_54) begin |
| execute_to_memory_REGFILE_WRITE_DATA <= _zz_decode_RS2; |
| end |
| if(when_Pipeline_l124_55) begin |
| memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_decode_RS2_1; |
| end |
| if(when_Pipeline_l124_56) begin |
| execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; |
| end |
| if(when_Pipeline_l124_57) begin |
| execute_to_memory_MUL_LL <= execute_MUL_LL; |
| end |
| if(when_Pipeline_l124_58) begin |
| execute_to_memory_MUL_LH <= execute_MUL_LH; |
| end |
| if(when_Pipeline_l124_59) begin |
| execute_to_memory_MUL_HL <= execute_MUL_HL; |
| end |
| if(when_Pipeline_l124_60) begin |
| execute_to_memory_MUL_HH <= execute_MUL_HH; |
| end |
| if(when_Pipeline_l124_61) begin |
| memory_to_writeBack_MUL_HH <= memory_MUL_HH; |
| end |
| if(when_Pipeline_l124_62) begin |
| memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; |
| end |
| if(when_CsrPlugin_l1264) begin |
| execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); |
| end |
| if(when_CsrPlugin_l1264_1) begin |
| execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); |
| end |
| if(when_CsrPlugin_l1264_2) begin |
| execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); |
| end |
| if(when_CsrPlugin_l1264_3) begin |
| execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); |
| end |
| if(when_CsrPlugin_l1264_4) begin |
| execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); |
| end |
| if(when_CsrPlugin_l1264_5) begin |
| execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); |
| end |
| if(when_CsrPlugin_l1264_6) begin |
| execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); |
| end |
| if(when_CsrPlugin_l1264_7) begin |
| execute_CsrPlugin_csr_2816 <= (decode_INSTRUCTION[31 : 20] == 12'hb00); |
| end |
| if(when_CsrPlugin_l1264_8) begin |
| execute_CsrPlugin_csr_2944 <= (decode_INSTRUCTION[31 : 20] == 12'hb80); |
| end |
| if(when_CsrPlugin_l1264_9) begin |
| execute_CsrPlugin_csr_3072 <= (decode_INSTRUCTION[31 : 20] == 12'hc00); |
| end |
| if(when_CsrPlugin_l1264_10) begin |
| execute_CsrPlugin_csr_3200 <= (decode_INSTRUCTION[31 : 20] == 12'hc80); |
| end |
| if(when_CsrPlugin_l1264_11) begin |
| execute_CsrPlugin_csr_256 <= (decode_INSTRUCTION[31 : 20] == 12'h100); |
| end |
| if(when_CsrPlugin_l1264_12) begin |
| execute_CsrPlugin_csr_384 <= (decode_INSTRUCTION[31 : 20] == 12'h180); |
| end |
| if(execute_CsrPlugin_csr_836) begin |
| if(execute_CsrPlugin_writeEnable) begin |
| CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3]; |
| end |
| end |
| if(execute_CsrPlugin_csr_833) begin |
| if(execute_CsrPlugin_writeEnable) begin |
| CsrPlugin_mepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; |
| end |
| end |
| if(execute_CsrPlugin_csr_2816) begin |
| if(execute_CsrPlugin_writeEnable) begin |
| CsrPlugin_mcycle[31 : 0] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; |
| end |
| end |
| if(execute_CsrPlugin_csr_2944) begin |
| if(execute_CsrPlugin_writeEnable) begin |
| CsrPlugin_mcycle[63 : 32] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; |
| end |
| end |
| if(execute_CsrPlugin_csr_384) begin |
| if(execute_CsrPlugin_writeEnable) begin |
| MmuPlugin_satp_asid <= CsrPlugin_csrMapping_writeDataSignal[30 : 22]; |
| MmuPlugin_satp_ppn <= CsrPlugin_csrMapping_writeDataSignal[19 : 0]; |
| end |
| end |
| iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; |
| dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; |
| end |
| |
| always @(posedge clk) begin |
| DebugPlugin_firstCycle <= 1'b0; |
| if(debug_bus_cmd_ready) begin |
| DebugPlugin_firstCycle <= 1'b1; |
| end |
| DebugPlugin_secondCycle <= DebugPlugin_firstCycle; |
| DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != 4'b0000) || IBusCachedPlugin_incomingInstruction); |
| if(writeBack_arbitration_isValid) begin |
| DebugPlugin_busReadDataReg <= _zz_decode_RS2_2; |
| end |
| _zz_when_DebugPlugin_l244 <= debug_bus_cmd_payload_address[2]; |
| if(when_DebugPlugin_l295) begin |
| DebugPlugin_busReadDataReg <= execute_PC; |
| end |
| DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; |
| end |
| |
| always @(posedge clk or posedge jtag_rst) begin |
| if(jtag_rst) begin |
| DebugPlugin_resetIt <= 1'b0; |
| DebugPlugin_haltIt <= 1'b0; |
| DebugPlugin_stepIt <= 1'b0; |
| DebugPlugin_godmode <= 1'b0; |
| DebugPlugin_haltedByBreak <= 1'b0; |
| DebugPlugin_debugUsed <= 1'b0; |
| DebugPlugin_disableEbreak <= 1'b0; |
| debug_bus_cmd_fire_regNext <= 1'b0; |
| end else begin |
| if(when_DebugPlugin_l225) begin |
| DebugPlugin_godmode <= 1'b1; |
| end |
| if(debug_bus_cmd_valid) begin |
| DebugPlugin_debugUsed <= 1'b1; |
| end |
| if(debug_bus_cmd_valid) begin |
| case(switch_DebugPlugin_l267) |
| 6'h0 : begin |
| if(debug_bus_cmd_payload_wr) begin |
| DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; |
| if(when_DebugPlugin_l271) begin |
| DebugPlugin_resetIt <= 1'b1; |
| end |
| if(when_DebugPlugin_l271_1) begin |
| DebugPlugin_resetIt <= 1'b0; |
| end |
| if(when_DebugPlugin_l272) begin |
| DebugPlugin_haltIt <= 1'b1; |
| end |
| if(when_DebugPlugin_l272_1) begin |
| DebugPlugin_haltIt <= 1'b0; |
| end |
| if(when_DebugPlugin_l273) begin |
| DebugPlugin_haltedByBreak <= 1'b0; |
| end |
| if(when_DebugPlugin_l274) begin |
| DebugPlugin_godmode <= 1'b0; |
| end |
| if(when_DebugPlugin_l275) begin |
| DebugPlugin_disableEbreak <= 1'b1; |
| end |
| if(when_DebugPlugin_l275_1) begin |
| DebugPlugin_disableEbreak <= 1'b0; |
| end |
| end |
| end |
| default : begin |
| end |
| endcase |
| end |
| if(when_DebugPlugin_l295) begin |
| if(when_DebugPlugin_l298) begin |
| DebugPlugin_haltIt <= 1'b1; |
| DebugPlugin_haltedByBreak <= 1'b1; |
| end |
| end |
| if(when_DebugPlugin_l311) begin |
| if(decode_arbitration_isValid) begin |
| DebugPlugin_haltIt <= 1'b1; |
| end |
| end |
| debug_bus_cmd_fire_regNext <= debug_bus_cmd_fire; |
| end |
| end |
| |
| |
| endmodule |
| |
| module SystemDebugger ( |
| `ifdef USE_POWER_PINS |
| inout vccd1, // User area 1 1.8V supply |
| inout vssd1, // User area 1 digital ground |
| `endif |
| input io_remote_cmd_valid, |
| output io_remote_cmd_ready, |
| input io_remote_cmd_payload_last, |
| input [0:0] io_remote_cmd_payload_fragment, |
| output io_remote_rsp_valid, |
| input io_remote_rsp_ready, |
| output io_remote_rsp_payload_error, |
| output [31:0] io_remote_rsp_payload_data, |
| output io_mem_cmd_valid, |
| input io_mem_cmd_ready, |
| output [31:0] io_mem_cmd_payload_address, |
| output [31:0] io_mem_cmd_payload_data, |
| output io_mem_cmd_payload_wr, |
| output [1:0] io_mem_cmd_payload_size, |
| input io_mem_rsp_valid, |
| input [31:0] io_mem_rsp_payload, |
| input clk, |
| input jtag_rst |
| ); |
| |
| reg [66:0] dispatcher_dataShifter; |
| reg dispatcher_dataLoaded; |
| reg [7:0] dispatcher_headerShifter; |
| wire [7:0] dispatcher_header; |
| reg dispatcher_headerLoaded; |
| reg [2:0] dispatcher_counter; |
| wire when_Fragment_l346; |
| wire when_Fragment_l349; |
| wire [66:0] _zz_io_mem_cmd_payload_address; |
| wire io_mem_cmd_isStall; |
| wire when_Fragment_l372; |
| |
| assign dispatcher_header = dispatcher_headerShifter[7 : 0]; |
| assign when_Fragment_l346 = (dispatcher_headerLoaded == 1'b0); |
| assign when_Fragment_l349 = (dispatcher_counter == 3'b111); |
| assign io_remote_cmd_ready = (! dispatcher_dataLoaded); |
| assign _zz_io_mem_cmd_payload_address = dispatcher_dataShifter[66 : 0]; |
| assign io_mem_cmd_payload_address = _zz_io_mem_cmd_payload_address[31 : 0]; |
| assign io_mem_cmd_payload_data = _zz_io_mem_cmd_payload_address[63 : 32]; |
| assign io_mem_cmd_payload_wr = _zz_io_mem_cmd_payload_address[64]; |
| assign io_mem_cmd_payload_size = _zz_io_mem_cmd_payload_address[66 : 65]; |
| assign io_mem_cmd_valid = (dispatcher_dataLoaded && (dispatcher_header == 8'h0)); |
| assign io_mem_cmd_isStall = (io_mem_cmd_valid && (! io_mem_cmd_ready)); |
| assign when_Fragment_l372 = ((dispatcher_headerLoaded && dispatcher_dataLoaded) && (! io_mem_cmd_isStall)); |
| assign io_remote_rsp_valid = io_mem_rsp_valid; |
| assign io_remote_rsp_payload_error = 1'b0; |
| assign io_remote_rsp_payload_data = io_mem_rsp_payload; |
| always @(posedge clk or posedge jtag_rst) begin |
| if(jtag_rst) begin |
| dispatcher_dataLoaded <= 1'b0; |
| dispatcher_headerLoaded <= 1'b0; |
| dispatcher_counter <= 3'b000; |
| end else begin |
| if(io_remote_cmd_valid) begin |
| if(when_Fragment_l346) begin |
| dispatcher_counter <= (dispatcher_counter + 3'b001); |
| if(when_Fragment_l349) begin |
| dispatcher_headerLoaded <= 1'b1; |
| end |
| end |
| if(io_remote_cmd_payload_last) begin |
| dispatcher_headerLoaded <= 1'b1; |
| dispatcher_dataLoaded <= 1'b1; |
| dispatcher_counter <= 3'b000; |
| end |
| end |
| if(when_Fragment_l372) begin |
| dispatcher_headerLoaded <= 1'b0; |
| dispatcher_dataLoaded <= 1'b0; |
| end |
| end |
| end |
| |
| always @(posedge clk) begin |
| if(io_remote_cmd_valid) begin |
| if(when_Fragment_l346) begin |
| dispatcher_headerShifter <= ({io_remote_cmd_payload_fragment,dispatcher_headerShifter} >>> 1); |
| end else begin |
| dispatcher_dataShifter <= ({io_remote_cmd_payload_fragment,dispatcher_dataShifter} >>> 1); |
| end |
| end |
| end |
| |
| |
| endmodule |
| |
| module JtagBridge ( |
| `ifdef USE_POWER_PINS |
| inout vccd1, // User area 1 1.8V supply |
| inout vssd1, // User area 1 digital ground |
| `endif |
| input io_jtag_tms, |
| input io_jtag_tdi, |
| output io_jtag_tdo, |
| input io_jtag_tck, |
| output io_remote_cmd_valid, |
| input io_remote_cmd_ready, |
| output io_remote_cmd_payload_last, |
| output [0:0] io_remote_cmd_payload_fragment, |
| input io_remote_rsp_valid, |
| output io_remote_rsp_ready, |
| input io_remote_rsp_payload_error, |
| input [31:0] io_remote_rsp_payload_data, |
| input clk, |
| input jtag_rst |
| ); |
| localparam JtagState_RESET = 4'd0; |
| localparam JtagState_IDLE = 4'd1; |
| localparam JtagState_IR_SELECT = 4'd2; |
| localparam JtagState_IR_CAPTURE = 4'd3; |
| localparam JtagState_IR_SHIFT = 4'd4; |
| localparam JtagState_IR_EXIT1 = 4'd5; |
| localparam JtagState_IR_PAUSE = 4'd6; |
| localparam JtagState_IR_EXIT2 = 4'd7; |
| localparam JtagState_IR_UPDATE = 4'd8; |
| localparam JtagState_DR_SELECT = 4'd9; |
| localparam JtagState_DR_CAPTURE = 4'd10; |
| localparam JtagState_DR_SHIFT = 4'd11; |
| localparam JtagState_DR_EXIT1 = 4'd12; |
| localparam JtagState_DR_PAUSE = 4'd13; |
| localparam JtagState_DR_EXIT2 = 4'd14; |
| localparam JtagState_DR_UPDATE = 4'd15; |
| |
| wire flowCCByToggle_1_io_output_valid; |
| wire flowCCByToggle_1_io_output_payload_last; |
| wire [0:0] flowCCByToggle_1_io_output_payload_fragment; |
| wire [3:0] _zz_jtag_tap_isBypass; |
| wire [3:0] _zz_jtag_tap_isBypass_1; |
| wire [1:0] _zz_jtag_tap_instructionShift; |
| wire system_cmd_valid; |
| wire system_cmd_payload_last; |
| wire [0:0] system_cmd_payload_fragment; |
| wire system_cmd_toStream_valid; |
| wire system_cmd_toStream_ready; |
| wire system_cmd_toStream_payload_last; |
| wire [0:0] system_cmd_toStream_payload_fragment; |
| (* async_reg = "true" *) reg system_rsp_valid; |
| (* async_reg = "true" *) reg system_rsp_payload_error; |
| (* async_reg = "true" *) reg [31:0] system_rsp_payload_data; |
| wire io_remote_rsp_fire; |
| wire [3:0] jtag_tap_fsm_stateNext; |
| reg [3:0] jtag_tap_fsm_state = JtagState_RESET; |
| reg [3:0] _zz_jtag_tap_fsm_stateNext; |
| reg [3:0] jtag_tap_instruction; |
| reg [3:0] jtag_tap_instructionShift; |
| reg jtag_tap_bypass; |
| reg jtag_tap_tdoUnbufferd; |
| reg jtag_tap_tdoDr; |
| wire jtag_tap_tdoIr; |
| wire jtag_tap_isBypass; |
| reg jtag_tap_tdoUnbufferd_regNext; |
| wire jtag_idcodeArea_ctrl_tdi; |
| wire jtag_idcodeArea_ctrl_enable; |
| wire jtag_idcodeArea_ctrl_capture; |
| wire jtag_idcodeArea_ctrl_shift; |
| wire jtag_idcodeArea_ctrl_update; |
| wire jtag_idcodeArea_ctrl_reset; |
| wire jtag_idcodeArea_ctrl_tdo; |
| reg [31:0] jtag_idcodeArea_shifter; |
| wire when_JtagTap_l120; |
| wire jtag_writeArea_ctrl_tdi; |
| wire jtag_writeArea_ctrl_enable; |
| wire jtag_writeArea_ctrl_capture; |
| wire jtag_writeArea_ctrl_shift; |
| wire jtag_writeArea_ctrl_update; |
| wire jtag_writeArea_ctrl_reset; |
| wire jtag_writeArea_ctrl_tdo; |
| wire jtag_writeArea_source_valid; |
| wire jtag_writeArea_source_payload_last; |
| wire [0:0] jtag_writeArea_source_payload_fragment; |
| reg jtag_writeArea_valid; |
| reg jtag_writeArea_data; |
| wire jtag_readArea_ctrl_tdi; |
| wire jtag_readArea_ctrl_enable; |
| wire jtag_readArea_ctrl_capture; |
| wire jtag_readArea_ctrl_shift; |
| wire jtag_readArea_ctrl_update; |
| wire jtag_readArea_ctrl_reset; |
| wire jtag_readArea_ctrl_tdo; |
| reg [33:0] jtag_readArea_full_shifter; |
| `ifndef SYNTHESIS |
| reg [79:0] jtag_tap_fsm_stateNext_string; |
| reg [79:0] jtag_tap_fsm_state_string; |
| reg [79:0] _zz_jtag_tap_fsm_stateNext_string; |
| `endif |
| |
| |
| assign _zz_jtag_tap_isBypass = jtag_tap_instruction; |
| assign _zz_jtag_tap_isBypass_1 = 4'b1111; |
| assign _zz_jtag_tap_instructionShift = 2'b01; |
| FlowCCByToggle flowCCByToggle_1 ( |
| `ifdef USE_POWER_PINS |
| .vccd1(vccd1), // User area 1 1.8V power |
| .vssd1(vssd1), // User area 1 digital ground |
| `endif |
| .io_input_valid (jtag_writeArea_source_valid ), //i |
| .io_input_payload_last (jtag_writeArea_source_payload_last ), //i |
| .io_input_payload_fragment (jtag_writeArea_source_payload_fragment ), //i |
| .io_output_valid (flowCCByToggle_1_io_output_valid ), //o |
| .io_output_payload_last (flowCCByToggle_1_io_output_payload_last ), //o |
| .io_output_payload_fragment (flowCCByToggle_1_io_output_payload_fragment ), //o |
| .io_jtag_tck (io_jtag_tck ), //i |
| .clk (clk ), //i |
| .jtag_rst (jtag_rst ) //i |
| ); |
| `ifndef SYNTHESIS |
| always @(*) begin |
| case(jtag_tap_fsm_stateNext) |
| JtagState_RESET : jtag_tap_fsm_stateNext_string = "RESET "; |
| JtagState_IDLE : jtag_tap_fsm_stateNext_string = "IDLE "; |
| JtagState_IR_SELECT : jtag_tap_fsm_stateNext_string = "IR_SELECT "; |
| JtagState_IR_CAPTURE : jtag_tap_fsm_stateNext_string = "IR_CAPTURE"; |
| JtagState_IR_SHIFT : jtag_tap_fsm_stateNext_string = "IR_SHIFT "; |
| JtagState_IR_EXIT1 : jtag_tap_fsm_stateNext_string = "IR_EXIT1 "; |
| JtagState_IR_PAUSE : jtag_tap_fsm_stateNext_string = "IR_PAUSE "; |
| JtagState_IR_EXIT2 : jtag_tap_fsm_stateNext_string = "IR_EXIT2 "; |
| JtagState_IR_UPDATE : jtag_tap_fsm_stateNext_string = "IR_UPDATE "; |
| JtagState_DR_SELECT : jtag_tap_fsm_stateNext_string = "DR_SELECT "; |
| JtagState_DR_CAPTURE : jtag_tap_fsm_stateNext_string = "DR_CAPTURE"; |
| JtagState_DR_SHIFT : jtag_tap_fsm_stateNext_string = "DR_SHIFT "; |
| JtagState_DR_EXIT1 : jtag_tap_fsm_stateNext_string = "DR_EXIT1 "; |
| JtagState_DR_PAUSE : jtag_tap_fsm_stateNext_string = "DR_PAUSE "; |
| JtagState_DR_EXIT2 : jtag_tap_fsm_stateNext_string = "DR_EXIT2 "; |
| JtagState_DR_UPDATE : jtag_tap_fsm_stateNext_string = "DR_UPDATE "; |
| default : jtag_tap_fsm_stateNext_string = "??????????"; |
| endcase |
| end |
| always @(*) begin |
| case(jtag_tap_fsm_state) |
| JtagState_RESET : jtag_tap_fsm_state_string = "RESET "; |
| JtagState_IDLE : jtag_tap_fsm_state_string = "IDLE "; |
| JtagState_IR_SELECT : jtag_tap_fsm_state_string = "IR_SELECT "; |
| JtagState_IR_CAPTURE : jtag_tap_fsm_state_string = "IR_CAPTURE"; |
| JtagState_IR_SHIFT : jtag_tap_fsm_state_string = "IR_SHIFT "; |
| JtagState_IR_EXIT1 : jtag_tap_fsm_state_string = "IR_EXIT1 "; |
| JtagState_IR_PAUSE : jtag_tap_fsm_state_string = "IR_PAUSE "; |
| JtagState_IR_EXIT2 : jtag_tap_fsm_state_string = "IR_EXIT2 "; |
| JtagState_IR_UPDATE : jtag_tap_fsm_state_string = "IR_UPDATE "; |
| JtagState_DR_SELECT : jtag_tap_fsm_state_string = "DR_SELECT "; |
| JtagState_DR_CAPTURE : jtag_tap_fsm_state_string = "DR_CAPTURE"; |
| JtagState_DR_SHIFT : jtag_tap_fsm_state_string = "DR_SHIFT "; |
| JtagState_DR_EXIT1 : jtag_tap_fsm_state_string = "DR_EXIT1 "; |
| JtagState_DR_PAUSE : jtag_tap_fsm_state_string = "DR_PAUSE "; |
| JtagState_DR_EXIT2 : jtag_tap_fsm_state_string = "DR_EXIT2 "; |
| JtagState_DR_UPDATE : jtag_tap_fsm_state_string = "DR_UPDATE "; |
| default : jtag_tap_fsm_state_string = "??????????"; |
| endcase |
| end |
| always @(*) begin |
| case(_zz_jtag_tap_fsm_stateNext) |
| JtagState_RESET : _zz_jtag_tap_fsm_stateNext_string = "RESET "; |
| JtagState_IDLE : _zz_jtag_tap_fsm_stateNext_string = "IDLE "; |
| JtagState_IR_SELECT : _zz_jtag_tap_fsm_stateNext_string = "IR_SELECT "; |
| JtagState_IR_CAPTURE : _zz_jtag_tap_fsm_stateNext_string = "IR_CAPTURE"; |
| JtagState_IR_SHIFT : _zz_jtag_tap_fsm_stateNext_string = "IR_SHIFT "; |
| JtagState_IR_EXIT1 : _zz_jtag_tap_fsm_stateNext_string = "IR_EXIT1 "; |
| JtagState_IR_PAUSE : _zz_jtag_tap_fsm_stateNext_string = "IR_PAUSE "; |
| JtagState_IR_EXIT2 : _zz_jtag_tap_fsm_stateNext_string = "IR_EXIT2 "; |
| JtagState_IR_UPDATE : _zz_jtag_tap_fsm_stateNext_string = "IR_UPDATE "; |
| JtagState_DR_SELECT : _zz_jtag_tap_fsm_stateNext_string = "DR_SELECT "; |
| JtagState_DR_CAPTURE : _zz_jtag_tap_fsm_stateNext_string = "DR_CAPTURE"; |
| JtagState_DR_SHIFT : _zz_jtag_tap_fsm_stateNext_string = "DR_SHIFT "; |
| JtagState_DR_EXIT1 : _zz_jtag_tap_fsm_stateNext_string = "DR_EXIT1 "; |
| JtagState_DR_PAUSE : _zz_jtag_tap_fsm_stateNext_string = "DR_PAUSE "; |
| JtagState_DR_EXIT2 : _zz_jtag_tap_fsm_stateNext_string = "DR_EXIT2 "; |
| JtagState_DR_UPDATE : _zz_jtag_tap_fsm_stateNext_string = "DR_UPDATE "; |
| default : _zz_jtag_tap_fsm_stateNext_string = "??????????"; |
| endcase |
| end |
| `endif |
| |
| assign system_cmd_toStream_valid = system_cmd_valid; |
| assign system_cmd_toStream_payload_last = system_cmd_payload_last; |
| assign system_cmd_toStream_payload_fragment = system_cmd_payload_fragment; |
| assign io_remote_cmd_valid = system_cmd_toStream_valid; |
| assign system_cmd_toStream_ready = io_remote_cmd_ready; |
| assign io_remote_cmd_payload_last = system_cmd_toStream_payload_last; |
| assign io_remote_cmd_payload_fragment = system_cmd_toStream_payload_fragment; |
| assign io_remote_rsp_fire = (io_remote_rsp_valid && io_remote_rsp_ready); |
| assign io_remote_rsp_ready = 1'b1; |
| always @(*) begin |
| case(jtag_tap_fsm_state) |
| JtagState_IDLE : begin |
| _zz_jtag_tap_fsm_stateNext = (io_jtag_tms ? JtagState_DR_SELECT : JtagState_IDLE); |
| end |
| JtagState_IR_SELECT : begin |
| _zz_jtag_tap_fsm_stateNext = (io_jtag_tms ? JtagState_RESET : JtagState_IR_CAPTURE); |
| end |
| JtagState_IR_CAPTURE : begin |
| _zz_jtag_tap_fsm_stateNext = (io_jtag_tms ? JtagState_IR_EXIT1 : JtagState_IR_SHIFT); |
| end |
| JtagState_IR_SHIFT : begin |
| _zz_jtag_tap_fsm_stateNext = (io_jtag_tms ? JtagState_IR_EXIT1 : JtagState_IR_SHIFT); |
| end |
| JtagState_IR_EXIT1 : begin |
| _zz_jtag_tap_fsm_stateNext = (io_jtag_tms ? JtagState_IR_UPDATE : JtagState_IR_PAUSE); |
| end |
| JtagState_IR_PAUSE : begin |
| _zz_jtag_tap_fsm_stateNext = (io_jtag_tms ? JtagState_IR_EXIT2 : JtagState_IR_PAUSE); |
| end |
| JtagState_IR_EXIT2 : begin |
| _zz_jtag_tap_fsm_stateNext = (io_jtag_tms ? JtagState_IR_UPDATE : JtagState_IR_SHIFT); |
| end |
| JtagState_IR_UPDATE : begin |
| _zz_jtag_tap_fsm_stateNext = (io_jtag_tms ? JtagState_DR_SELECT : JtagState_IDLE); |
| end |
| JtagState_DR_SELECT : begin |
| _zz_jtag_tap_fsm_stateNext = (io_jtag_tms ? JtagState_IR_SELECT : JtagState_DR_CAPTURE); |
| end |
| JtagState_DR_CAPTURE : begin |
| _zz_jtag_tap_fsm_stateNext = (io_jtag_tms ? JtagState_DR_EXIT1 : JtagState_DR_SHIFT); |
| end |
| JtagState_DR_SHIFT : begin |
| _zz_jtag_tap_fsm_stateNext = (io_jtag_tms ? JtagState_DR_EXIT1 : JtagState_DR_SHIFT); |
| end |
| JtagState_DR_EXIT1 : begin |
| _zz_jtag_tap_fsm_stateNext = (io_jtag_tms ? JtagState_DR_UPDATE : JtagState_DR_PAUSE); |
| end |
| JtagState_DR_PAUSE : begin |
| _zz_jtag_tap_fsm_stateNext = (io_jtag_tms ? JtagState_DR_EXIT2 : JtagState_DR_PAUSE); |
| end |
| JtagState_DR_EXIT2 : begin |
| _zz_jtag_tap_fsm_stateNext = (io_jtag_tms ? JtagState_DR_UPDATE : JtagState_DR_SHIFT); |
| end |
| JtagState_DR_UPDATE : begin |
| _zz_jtag_tap_fsm_stateNext = (io_jtag_tms ? JtagState_DR_SELECT : JtagState_IDLE); |
| end |
| default : begin |
| _zz_jtag_tap_fsm_stateNext = (io_jtag_tms ? JtagState_RESET : JtagState_IDLE); |
| end |
| endcase |
| end |
| |
| assign jtag_tap_fsm_stateNext = _zz_jtag_tap_fsm_stateNext; |
| always @(*) begin |
| jtag_tap_tdoUnbufferd = jtag_tap_bypass; |
| case(jtag_tap_fsm_state) |
| JtagState_IR_SHIFT : begin |
| jtag_tap_tdoUnbufferd = jtag_tap_tdoIr; |
| end |
| JtagState_DR_SHIFT : begin |
| if(jtag_tap_isBypass) begin |
| jtag_tap_tdoUnbufferd = jtag_tap_bypass; |
| end else begin |
| jtag_tap_tdoUnbufferd = jtag_tap_tdoDr; |
| end |
| end |
| default : begin |
| end |
| endcase |
| end |
| |
| always @(*) begin |
| jtag_tap_tdoDr = 1'b0; |
| if(jtag_idcodeArea_ctrl_enable) begin |
| jtag_tap_tdoDr = jtag_idcodeArea_ctrl_tdo; |
| end |
| if(jtag_writeArea_ctrl_enable) begin |
| jtag_tap_tdoDr = jtag_writeArea_ctrl_tdo; |
| end |
| if(jtag_readArea_ctrl_enable) begin |
| jtag_tap_tdoDr = jtag_readArea_ctrl_tdo; |
| end |
| end |
| |
| assign jtag_tap_tdoIr = jtag_tap_instructionShift[0]; |
| assign jtag_tap_isBypass = ($signed(_zz_jtag_tap_isBypass) == $signed(_zz_jtag_tap_isBypass_1)); |
| assign io_jtag_tdo = jtag_tap_tdoUnbufferd_regNext; |
| assign jtag_idcodeArea_ctrl_tdo = jtag_idcodeArea_shifter[0]; |
| assign jtag_idcodeArea_ctrl_tdi = io_jtag_tdi; |
| assign jtag_idcodeArea_ctrl_enable = (jtag_tap_instruction == 4'b0001); |
| assign jtag_idcodeArea_ctrl_capture = (jtag_tap_fsm_state == JtagState_DR_CAPTURE); |
| assign jtag_idcodeArea_ctrl_shift = (jtag_tap_fsm_state == JtagState_DR_SHIFT); |
| assign jtag_idcodeArea_ctrl_update = (jtag_tap_fsm_state == JtagState_DR_UPDATE); |
| assign jtag_idcodeArea_ctrl_reset = (jtag_tap_fsm_state == JtagState_RESET); |
| assign when_JtagTap_l120 = (jtag_tap_fsm_state == JtagState_RESET); |
| assign jtag_writeArea_source_valid = jtag_writeArea_valid; |
| assign jtag_writeArea_source_payload_last = (! (jtag_writeArea_ctrl_enable && jtag_writeArea_ctrl_shift)); |
| assign jtag_writeArea_source_payload_fragment[0] = jtag_writeArea_data; |
| assign system_cmd_valid = flowCCByToggle_1_io_output_valid; |
| assign system_cmd_payload_last = flowCCByToggle_1_io_output_payload_last; |
| assign system_cmd_payload_fragment = flowCCByToggle_1_io_output_payload_fragment; |
| assign jtag_writeArea_ctrl_tdo = 1'b0; |
| assign jtag_writeArea_ctrl_tdi = io_jtag_tdi; |
| assign jtag_writeArea_ctrl_enable = (jtag_tap_instruction == 4'b0010); |
| assign jtag_writeArea_ctrl_capture = (jtag_tap_fsm_state == JtagState_DR_CAPTURE); |
| assign jtag_writeArea_ctrl_shift = (jtag_tap_fsm_state == JtagState_DR_SHIFT); |
| assign jtag_writeArea_ctrl_update = (jtag_tap_fsm_state == JtagState_DR_UPDATE); |
| assign jtag_writeArea_ctrl_reset = (jtag_tap_fsm_state == JtagState_RESET); |
| assign jtag_readArea_ctrl_tdo = jtag_readArea_full_shifter[0]; |
| assign jtag_readArea_ctrl_tdi = io_jtag_tdi; |
| assign jtag_readArea_ctrl_enable = (jtag_tap_instruction == 4'b0011); |
| assign jtag_readArea_ctrl_capture = (jtag_tap_fsm_state == JtagState_DR_CAPTURE); |
| assign jtag_readArea_ctrl_shift = (jtag_tap_fsm_state == JtagState_DR_SHIFT); |
| assign jtag_readArea_ctrl_update = (jtag_tap_fsm_state == JtagState_DR_UPDATE); |
| assign jtag_readArea_ctrl_reset = (jtag_tap_fsm_state == JtagState_RESET); |
| always @(posedge clk) begin |
| if(io_remote_cmd_valid) begin |
| system_rsp_valid <= 1'b0; |
| end |
| if(io_remote_rsp_fire) begin |
| system_rsp_valid <= 1'b1; |
| system_rsp_payload_error <= io_remote_rsp_payload_error; |
| system_rsp_payload_data <= io_remote_rsp_payload_data; |
| end |
| end |
| |
| always @(posedge io_jtag_tck) begin |
| jtag_tap_fsm_state <= jtag_tap_fsm_stateNext; |
| jtag_tap_bypass <= io_jtag_tdi; |
| case(jtag_tap_fsm_state) |
| JtagState_IR_CAPTURE : begin |
| jtag_tap_instructionShift <= {2'd0, _zz_jtag_tap_instructionShift}; |
| end |
| JtagState_IR_SHIFT : begin |
| jtag_tap_instructionShift <= ({io_jtag_tdi,jtag_tap_instructionShift} >>> 1); |
| end |
| JtagState_IR_UPDATE : begin |
| jtag_tap_instruction <= jtag_tap_instructionShift; |
| end |
| JtagState_DR_SHIFT : begin |
| jtag_tap_instructionShift <= ({io_jtag_tdi,jtag_tap_instructionShift} >>> 1); |
| end |
| default : begin |
| end |
| endcase |
| if(jtag_idcodeArea_ctrl_enable) begin |
| if(jtag_idcodeArea_ctrl_shift) begin |
| jtag_idcodeArea_shifter <= ({jtag_idcodeArea_ctrl_tdi,jtag_idcodeArea_shifter} >>> 1); |
| end |
| end |
| if(jtag_idcodeArea_ctrl_capture) begin |
| jtag_idcodeArea_shifter <= 32'h10001fff; |
| end |
| if(when_JtagTap_l120) begin |
| jtag_tap_instruction <= 4'b0001; |
| end |
| jtag_writeArea_valid <= (jtag_writeArea_ctrl_enable && jtag_writeArea_ctrl_shift); |
| jtag_writeArea_data <= jtag_writeArea_ctrl_tdi; |
| if(jtag_readArea_ctrl_enable) begin |
| if(jtag_readArea_ctrl_capture) begin |
| jtag_readArea_full_shifter <= {{system_rsp_payload_data,system_rsp_payload_error},system_rsp_valid}; |
| end |
| if(jtag_readArea_ctrl_shift) begin |
| jtag_readArea_full_shifter <= ({jtag_readArea_ctrl_tdi,jtag_readArea_full_shifter} >>> 1); |
| end |
| end |
| end |
| |
| always @(negedge io_jtag_tck) begin |
| jtag_tap_tdoUnbufferd_regNext <= jtag_tap_tdoUnbufferd; |
| end |
| |
| |
| endmodule |
| |
| module DataCache ( |
| `ifdef USE_POWER_PINS |
| inout vccd1, // User area 1 1.8V supply |
| inout vssd1, // User area 1 digital ground |
| `endif |
| input io_cpu_execute_isValid, |
| input [31:0] io_cpu_execute_address, |
| output reg io_cpu_execute_haltIt, |
| input io_cpu_execute_args_wr, |
| input [1:0] io_cpu_execute_args_size, |
| input io_cpu_execute_args_totalyConsistent, |
| output io_cpu_execute_refilling, |
| input io_cpu_memory_isValid, |
| input io_cpu_memory_isStuck, |
| output io_cpu_memory_isWrite, |
| input [31:0] io_cpu_memory_address, |
| input [31:0] io_cpu_memory_mmuRsp_physicalAddress, |
| input io_cpu_memory_mmuRsp_isIoAccess, |
| input io_cpu_memory_mmuRsp_isPaging, |
| input io_cpu_memory_mmuRsp_allowRead, |
| input io_cpu_memory_mmuRsp_allowWrite, |
| input io_cpu_memory_mmuRsp_allowExecute, |
| input io_cpu_memory_mmuRsp_exception, |
| input io_cpu_memory_mmuRsp_refilling, |
| input io_cpu_memory_mmuRsp_bypassTranslation, |
| input io_cpu_memory_mmuRsp_ways_0_sel, |
| input [31:0] io_cpu_memory_mmuRsp_ways_0_physical, |
| input io_cpu_memory_mmuRsp_ways_1_sel, |
| input [31:0] io_cpu_memory_mmuRsp_ways_1_physical, |
| input io_cpu_memory_mmuRsp_ways_2_sel, |
| input [31:0] io_cpu_memory_mmuRsp_ways_2_physical, |
| input io_cpu_memory_mmuRsp_ways_3_sel, |
| input [31:0] io_cpu_memory_mmuRsp_ways_3_physical, |
| input io_cpu_writeBack_isValid, |
| input io_cpu_writeBack_isStuck, |
| input io_cpu_writeBack_isUser, |
| output reg io_cpu_writeBack_haltIt, |
| output io_cpu_writeBack_isWrite, |
| input [31:0] io_cpu_writeBack_storeData, |
| output reg [31:0] io_cpu_writeBack_data, |
| input [31:0] io_cpu_writeBack_address, |
| output io_cpu_writeBack_mmuException, |
| output io_cpu_writeBack_unalignedAccess, |
| output reg io_cpu_writeBack_accessError, |
| output io_cpu_writeBack_keepMemRspData, |
| input io_cpu_writeBack_fence_SW, |
| input io_cpu_writeBack_fence_SR, |
| input io_cpu_writeBack_fence_SO, |
| input io_cpu_writeBack_fence_SI, |
| input io_cpu_writeBack_fence_PW, |
| input io_cpu_writeBack_fence_PR, |
| input io_cpu_writeBack_fence_PO, |
| input io_cpu_writeBack_fence_PI, |
| input [3:0] io_cpu_writeBack_fence_FM, |
| output io_cpu_writeBack_exclusiveOk, |
| output reg io_cpu_redo, |
| input io_cpu_flush_valid, |
| output io_cpu_flush_ready, |
| output reg io_mem_cmd_valid, |
| input io_mem_cmd_ready, |
| output reg io_mem_cmd_payload_wr, |
| output io_mem_cmd_payload_uncached, |
| output reg [31:0] io_mem_cmd_payload_address, |
| output [31:0] io_mem_cmd_payload_data, |
| output [3:0] io_mem_cmd_payload_mask, |
| output reg [2:0] io_mem_cmd_payload_size, |
| output io_mem_cmd_payload_last, |
| input io_mem_rsp_valid, |
| input io_mem_rsp_payload_last, |
| input [31:0] io_mem_rsp_payload_data, |
| input io_mem_rsp_payload_error, |
| input clk, |
| input reset |
| ); |
| |
| reg [31:0] _zz_ways_0_data_port0; |
| wire [2:0] _zz_stage0_dataColisions; |
| wire [2:0] _zz__zz_stageA_dataColisions; |
| wire [0:0] _zz_when; |
| wire [2:0] _zz_loader_counter_valueNext; |
| wire [0:0] _zz_loader_counter_valueNext_1; |
| wire [1:0] _zz_loader_waysAllocator; |
| reg _zz_1; |
| reg when_Phase_l623; |
| wire haltCpu; |
| reg tagsReadCmd_valid; |
| reg tagsWriteCmd_valid; |
| reg [0:0] tagsWriteCmd_payload_way; |
| reg tagsWriteCmd_payload_data_valid; |
| reg tagsWriteCmd_payload_data_error; |
| reg [26:0] tagsWriteCmd_payload_data_address; |
| reg tagsWriteLastCmd_valid; |
| reg [0:0] tagsWriteLastCmd_payload_way; |
| reg tagsWriteLastCmd_payload_data_valid; |
| reg tagsWriteLastCmd_payload_data_error; |
| reg [26:0] tagsWriteLastCmd_payload_data_address; |
| reg dataReadCmd_valid; |
| reg [2:0] dataReadCmd_payload; |
| reg dataWriteCmd_valid; |
| reg [0:0] dataWriteCmd_payload_way; |
| reg [2:0] dataWriteCmd_payload_address; |
| reg [31:0] dataWriteCmd_payload_data; |
| reg [3:0] dataWriteCmd_payload_mask; |
| wire when_Phase_l650; |
| wire ways_0_tagsReadRsp_valid; |
| wire ways_0_tagsReadRsp_error; |
| wire [26:0] ways_0_tagsReadRsp_address; |
| wire [28:0] _zz_ways_0_tagsReadRsp_valid; |
| wire _zz_ways_0_dataReadRspMem; |
| wire [31:0] ways_0_dataReadRspMem; |
| wire [31:0] ways_0_dataReadRsp; |
| wire when_DataCache_l635; |
| wire when_DataCache_l638; |
| wire when_DataCache_l657; |
| wire rspSync; |
| wire rspLast; |
| reg memCmdSent; |
| wire io_mem_cmd_fire; |
| wire when_DataCache_l679; |
| reg [3:0] _zz_stage0_mask; |
| wire [3:0] stage0_mask; |
| wire [0:0] stage0_dataColisions; |
| wire [0:0] stage0_wayInvalidate; |
| wire stage0_isAmo; |
| wire when_DataCache_l764; |
| reg stageA_request_wr; |
| reg [1:0] stageA_request_size; |
| reg stageA_request_totalyConsistent; |
| wire when_DataCache_l764_1; |
| reg [3:0] stageA_mask; |
| wire stageA_isAmo; |
| wire stageA_isLrsc; |
| wire [0:0] stageA_wayHits; |
| wire when_DataCache_l764_2; |
| reg [0:0] stageA_wayInvalidate; |
| wire when_DataCache_l764_3; |
| reg [0:0] stage0_dataColisions_regNextWhen; |
| wire [0:0] _zz_stageA_dataColisions; |
| wire [0:0] stageA_dataColisions; |
| wire when_DataCache_l815; |
| reg stageB_request_wr; |
| reg [1:0] stageB_request_size; |
| reg stageB_request_totalyConsistent; |
| reg stageB_mmuRspFreeze; |
| wire when_DataCache_l817; |
| reg [31:0] stageB_mmuRsp_physicalAddress; |
| reg stageB_mmuRsp_isIoAccess; |
| reg stageB_mmuRsp_isPaging; |
| reg stageB_mmuRsp_allowRead; |
| reg stageB_mmuRsp_allowWrite; |
| reg stageB_mmuRsp_allowExecute; |
| reg stageB_mmuRsp_exception; |
| reg stageB_mmuRsp_refilling; |
| reg stageB_mmuRsp_bypassTranslation; |
| reg stageB_mmuRsp_ways_0_sel; |
| reg [31:0] stageB_mmuRsp_ways_0_physical; |
| reg stageB_mmuRsp_ways_1_sel; |
| reg [31:0] stageB_mmuRsp_ways_1_physical; |
| reg stageB_mmuRsp_ways_2_sel; |
| reg [31:0] stageB_mmuRsp_ways_2_physical; |
| reg stageB_mmuRsp_ways_3_sel; |
| reg [31:0] stageB_mmuRsp_ways_3_physical; |
| wire when_DataCache_l814; |
| reg stageB_tagsReadRsp_0_valid; |
| reg stageB_tagsReadRsp_0_error; |
| reg [26:0] stageB_tagsReadRsp_0_address; |
| wire when_DataCache_l814_1; |
| reg [31:0] stageB_dataReadRsp_0; |
| wire when_DataCache_l813; |
| reg [0:0] stageB_wayInvalidate; |
| wire stageB_consistancyHazard; |
| wire when_DataCache_l813_1; |
| reg [0:0] stageB_dataColisions; |
| wire when_DataCache_l813_2; |
| reg stageB_unaligned; |
| wire when_DataCache_l813_3; |
| reg [0:0] stageB_waysHitsBeforeInvalidate; |
| wire [0:0] stageB_waysHits; |
| wire stageB_waysHit; |
| wire [31:0] stageB_dataMux; |
| wire when_DataCache_l813_4; |
| reg [3:0] stageB_mask; |
| reg stageB_loaderValid; |
| wire [31:0] stageB_ioMemRspMuxed; |
| reg stageB_flusher_waitDone; |
| wire stageB_flusher_hold; |
| reg [0:0] stageB_flusher_counter; |
| wire when_DataCache_l843; |
| wire when_DataCache_l849; |
| reg stageB_flusher_start; |
| wire stageB_isAmo; |
| wire stageB_isAmoCached; |
| wire stageB_isExternalLsrc; |
| wire stageB_isExternalAmo; |
| wire [31:0] stageB_requestDataBypass; |
| reg stageB_cpuWriteToCache; |
| wire when_DataCache_l912; |
| wire stageB_badPermissions; |
| wire stageB_loadStoreFault; |
| wire stageB_bypassCache; |
| wire when_DataCache_l981; |
| wire when_DataCache_l990; |
| wire when_DataCache_l995; |
| wire when_DataCache_l1006; |
| wire when_DataCache_l1018; |
| wire when_DataCache_l977; |
| wire when_DataCache_l1052; |
| wire when_DataCache_l1061; |
| reg loader_valid; |
| reg loader_counter_willIncrement; |
| wire loader_counter_willClear; |
| reg [2:0] loader_counter_valueNext; |
| reg [2:0] loader_counter_value; |
| wire loader_counter_willOverflowIfInc; |
| wire loader_counter_willOverflow; |
| reg [0:0] loader_waysAllocator; |
| reg loader_error; |
| wire loader_kill; |
| reg loader_killReg; |
| wire when_DataCache_l1076; |
| wire loader_done; |
| wire when_DataCache_l1104; |
| reg loader_valid_regNext; |
| wire when_DataCache_l1108; |
| wire when_DataCache_l1111; |
| wire [28:0] _zz_ways_0_tagsReadRsp_valid_1; |
| reg [28:0] _zz_ways_0_tagsReadRsp_valid_2; |
| reg [28:0] _zz_ways_0_tagsReadRsp_valid_3; |
| reg [7:0] ways_0_data_symbol0 [0:7]; |
| reg [7:0] ways_0_data_symbol1 [0:7]; |
| reg [7:0] ways_0_data_symbol2 [0:7]; |
| reg [7:0] ways_0_data_symbol3 [0:7]; |
| reg [7:0] _zz_ways_0_datasymbol_read; |
| reg [7:0] _zz_ways_0_datasymbol_read_1; |
| reg [7:0] _zz_ways_0_datasymbol_read_2; |
| reg [7:0] _zz_ways_0_datasymbol_read_3; |
| |
| assign _zz_stage0_dataColisions = (io_cpu_execute_address[4 : 2] >>> 0); |
| assign _zz__zz_stageA_dataColisions = (io_cpu_memory_address[4 : 2] >>> 0); |
| assign _zz_when = 1'b1; |
| assign _zz_loader_counter_valueNext_1 = loader_counter_willIncrement; |
| assign _zz_loader_counter_valueNext = {2'd0, _zz_loader_counter_valueNext_1}; |
| assign _zz_loader_waysAllocator = {loader_waysAllocator,loader_waysAllocator[0]}; |
| always @(*) begin |
| _zz_ways_0_data_port0 = {_zz_ways_0_datasymbol_read_3, _zz_ways_0_datasymbol_read_2, _zz_ways_0_datasymbol_read_1, _zz_ways_0_datasymbol_read}; |
| end |
| always @(posedge clk) begin |
| if(_zz_ways_0_dataReadRspMem) begin |
| _zz_ways_0_datasymbol_read <= ways_0_data_symbol0[dataReadCmd_payload]; |
| _zz_ways_0_datasymbol_read_1 <= ways_0_data_symbol1[dataReadCmd_payload]; |
| _zz_ways_0_datasymbol_read_2 <= ways_0_data_symbol2[dataReadCmd_payload]; |
| _zz_ways_0_datasymbol_read_3 <= ways_0_data_symbol3[dataReadCmd_payload]; |
| end |
| end |
| |
| always @(posedge clk) begin |
| if(dataWriteCmd_payload_mask[0] && _zz_1) begin |
| ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; |
| end |
| if(dataWriteCmd_payload_mask[1] && _zz_1) begin |
| ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; |
| end |
| if(dataWriteCmd_payload_mask[2] && _zz_1) begin |
| ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; |
| end |
| if(dataWriteCmd_payload_mask[3] && _zz_1) begin |
| ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; |
| end |
| end |
| |
| always @(*) begin |
| _zz_1 = 1'b0; |
| if(when_DataCache_l638) begin |
| _zz_1 = 1'b1; |
| end |
| end |
| |
| always @(*) begin |
| when_Phase_l623 = 1'b0; |
| if(when_DataCache_l635) begin |
| when_Phase_l623 = 1'b1; |
| end |
| end |
| |
| assign haltCpu = 1'b0; |
| assign when_Phase_l650 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); |
| assign _zz_ways_0_tagsReadRsp_valid = _zz_ways_0_tagsReadRsp_valid_2; |
| assign ways_0_tagsReadRsp_valid = _zz_ways_0_tagsReadRsp_valid[0]; |
| assign ways_0_tagsReadRsp_error = _zz_ways_0_tagsReadRsp_valid[1]; |
| assign ways_0_tagsReadRsp_address = _zz_ways_0_tagsReadRsp_valid[28 : 2]; |
| assign _zz_ways_0_dataReadRspMem = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); |
| assign ways_0_dataReadRspMem = _zz_ways_0_data_port0; |
| assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; |
| assign when_DataCache_l635 = (tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]); |
| assign when_DataCache_l638 = (dataWriteCmd_valid && dataWriteCmd_payload_way[0]); |
| always @(*) begin |
| tagsReadCmd_valid = 1'b0; |
| if(when_DataCache_l657) begin |
| tagsReadCmd_valid = 1'b1; |
| end |
| end |
| |
| always @(*) begin |
| dataReadCmd_valid = 1'b0; |
| if(when_DataCache_l657) begin |
| dataReadCmd_valid = 1'b1; |
| end |
| end |
| |
| always @(*) begin |
| dataReadCmd_payload = 3'bxxx; |
| if(when_DataCache_l657) begin |
| dataReadCmd_payload = io_cpu_execute_address[4 : 2]; |
| end |
| end |
| |
| always @(*) begin |
| tagsWriteCmd_valid = 1'b0; |
| if(when_DataCache_l843) begin |
| tagsWriteCmd_valid = 1'b1; |
| end |
| if(when_DataCache_l1052) begin |
| tagsWriteCmd_valid = 1'b0; |
| end |
| if(loader_done) begin |
| tagsWriteCmd_valid = 1'b1; |
| end |
| end |
| |
| always @(*) begin |
| tagsWriteCmd_payload_way = 1'bx; |
| if(when_DataCache_l843) begin |
| tagsWriteCmd_payload_way = 1'b1; |
| end |
| if(loader_done) begin |
| tagsWriteCmd_payload_way = loader_waysAllocator; |
| end |
| end |
| |
| always @(*) begin |
| tagsWriteCmd_payload_data_valid = 1'bx; |
| if(when_DataCache_l843) begin |
| tagsWriteCmd_payload_data_valid = 1'b0; |
| end |
| if(loader_done) begin |
| tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); |
| end |
| end |
| |
| always @(*) begin |
| tagsWriteCmd_payload_data_error = 1'bx; |
| if(loader_done) begin |
| tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); |
| end |
| end |
| |
| always @(*) begin |
| tagsWriteCmd_payload_data_address = 27'bxxxxxxxxxxxxxxxxxxxxxxxxxxx; |
| if(loader_done) begin |
| tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 5]; |
| end |
| end |
| |
| always @(*) begin |
| dataWriteCmd_valid = 1'b0; |
| if(stageB_cpuWriteToCache) begin |
| if(when_DataCache_l912) begin |
| dataWriteCmd_valid = 1'b1; |
| end |
| end |
| if(when_DataCache_l1052) begin |
| dataWriteCmd_valid = 1'b0; |
| end |
| if(when_DataCache_l1076) begin |
| dataWriteCmd_valid = 1'b1; |
| end |
| end |
| |
| always @(*) begin |
| dataWriteCmd_payload_way = 1'bx; |
| if(stageB_cpuWriteToCache) begin |
| dataWriteCmd_payload_way = stageB_waysHits; |
| end |
| if(when_DataCache_l1076) begin |
| dataWriteCmd_payload_way = loader_waysAllocator; |
| end |
| end |
| |
| always @(*) begin |
| dataWriteCmd_payload_address = 3'bxxx; |
| if(stageB_cpuWriteToCache) begin |
| dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[4 : 2]; |
| end |
| if(when_DataCache_l1076) begin |
| dataWriteCmd_payload_address = loader_counter_value; |
| end |
| end |
| |
| always @(*) begin |
| dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; |
| if(stageB_cpuWriteToCache) begin |
| dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; |
| end |
| if(when_DataCache_l1076) begin |
| dataWriteCmd_payload_data = io_mem_rsp_payload_data; |
| end |
| end |
| |
| always @(*) begin |
| dataWriteCmd_payload_mask = 4'bxxxx; |
| if(stageB_cpuWriteToCache) begin |
| dataWriteCmd_payload_mask = 4'b0000; |
| if(_zz_when[0]) begin |
| dataWriteCmd_payload_mask[3 : 0] = stageB_mask; |
| end |
| end |
| if(when_DataCache_l1076) begin |
| dataWriteCmd_payload_mask = 4'b1111; |
| end |
| end |
| |
| assign when_DataCache_l657 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); |
| always @(*) begin |
| io_cpu_execute_haltIt = 1'b0; |
| if(when_DataCache_l843) begin |
| io_cpu_execute_haltIt = 1'b1; |
| end |
| end |
| |
| assign rspSync = 1'b1; |
| assign rspLast = 1'b1; |
| assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); |
| assign when_DataCache_l679 = (! io_cpu_writeBack_isStuck); |
| always @(*) begin |
| _zz_stage0_mask = 4'bxxxx; |
| case(io_cpu_execute_args_size) |
| 2'b00 : begin |
| _zz_stage0_mask = 4'b0001; |
| end |
| 2'b01 : begin |
| _zz_stage0_mask = 4'b0011; |
| end |
| 2'b10 : begin |
| _zz_stage0_mask = 4'b1111; |
| end |
| default : begin |
| end |
| endcase |
| end |
| |
| assign stage0_mask = (_zz_stage0_mask <<< io_cpu_execute_address[1 : 0]); |
| assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_stage0_dataColisions)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); |
| assign stage0_wayInvalidate = 1'b0; |
| assign stage0_isAmo = 1'b0; |
| assign when_DataCache_l764 = (! io_cpu_memory_isStuck); |
| assign when_DataCache_l764_1 = (! io_cpu_memory_isStuck); |
| assign io_cpu_memory_isWrite = stageA_request_wr; |
| assign stageA_isAmo = 1'b0; |
| assign stageA_isLrsc = 1'b0; |
| assign stageA_wayHits = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 5] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); |
| assign when_DataCache_l764_2 = (! io_cpu_memory_isStuck); |
| assign when_DataCache_l764_3 = (! io_cpu_memory_isStuck); |
| assign _zz_stageA_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz__zz_stageA_dataColisions)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); |
| assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_stageA_dataColisions); |
| assign when_DataCache_l815 = (! io_cpu_writeBack_isStuck); |
| always @(*) begin |
| stageB_mmuRspFreeze = 1'b0; |
| if(when_DataCache_l1111) begin |
| stageB_mmuRspFreeze = 1'b1; |
| end |
| end |
| |
| assign when_DataCache_l817 = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)); |
| assign when_DataCache_l814 = (! io_cpu_writeBack_isStuck); |
| assign when_DataCache_l814_1 = (! io_cpu_writeBack_isStuck); |
| assign when_DataCache_l813 = (! io_cpu_writeBack_isStuck); |
| assign stageB_consistancyHazard = 1'b0; |
| assign when_DataCache_l813_1 = (! io_cpu_writeBack_isStuck); |
| assign when_DataCache_l813_2 = (! io_cpu_writeBack_isStuck); |
| assign when_DataCache_l813_3 = (! io_cpu_writeBack_isStuck); |
| assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); |
| assign stageB_waysHit = (|stageB_waysHits); |
| assign stageB_dataMux = stageB_dataReadRsp_0; |
| assign when_DataCache_l813_4 = (! io_cpu_writeBack_isStuck); |
| always @(*) begin |
| stageB_loaderValid = 1'b0; |
| if(io_cpu_writeBack_isValid) begin |
| if(!stageB_isExternalAmo) begin |
| if(!when_DataCache_l977) begin |
| if(!when_DataCache_l990) begin |
| if(io_mem_cmd_ready) begin |
| stageB_loaderValid = 1'b1; |
| end |
| end |
| end |
| end |
| end |
| if(when_DataCache_l1052) begin |
| stageB_loaderValid = 1'b0; |
| end |
| end |
| |
| assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; |
| always @(*) begin |
| io_cpu_writeBack_haltIt = 1'b1; |
| if(io_cpu_writeBack_isValid) begin |
| if(!stageB_isExternalAmo) begin |
| if(when_DataCache_l977) begin |
| if(when_DataCache_l981) begin |
| io_cpu_writeBack_haltIt = 1'b0; |
| end |
| end else begin |
| if(when_DataCache_l990) begin |
| if(when_DataCache_l995) begin |
| io_cpu_writeBack_haltIt = 1'b0; |
| end |
| end |
| end |
| end |
| end |
| if(when_DataCache_l1052) begin |
| io_cpu_writeBack_haltIt = 1'b0; |
| end |
| end |
| |
| assign stageB_flusher_hold = 1'b0; |
| assign when_DataCache_l843 = (! stageB_flusher_counter[0]); |
| assign when_DataCache_l849 = (! stageB_flusher_hold); |
| assign io_cpu_flush_ready = (stageB_flusher_waitDone && stageB_flusher_counter[0]); |
| assign stageB_isAmo = 1'b0; |
| assign stageB_isAmoCached = 1'b0; |
| assign stageB_isExternalLsrc = 1'b0; |
| assign stageB_isExternalAmo = 1'b0; |
| assign stageB_requestDataBypass = io_cpu_writeBack_storeData; |
| always @(*) begin |
| stageB_cpuWriteToCache = 1'b0; |
| if(io_cpu_writeBack_isValid) begin |
| if(!stageB_isExternalAmo) begin |
| if(!when_DataCache_l977) begin |
| if(when_DataCache_l990) begin |
| stageB_cpuWriteToCache = 1'b1; |
| end |
| end |
| end |
| end |
| end |
| |
| assign when_DataCache_l912 = (stageB_request_wr && stageB_waysHit); |
| assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo))); |
| assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); |
| always @(*) begin |
| io_cpu_redo = 1'b0; |
| if(io_cpu_writeBack_isValid) begin |
| if(!stageB_isExternalAmo) begin |
| if(!when_DataCache_l977) begin |
| if(when_DataCache_l990) begin |
| if(when_DataCache_l1006) begin |
| io_cpu_redo = 1'b1; |
| end |
| end |
| end |
| end |
| end |
| if(when_DataCache_l1061) begin |
| io_cpu_redo = 1'b1; |
| end |
| if(when_DataCache_l1108) begin |
| io_cpu_redo = 1'b1; |
| end |
| end |
| |
| always @(*) begin |
| io_cpu_writeBack_accessError = 1'b0; |
| if(stageB_bypassCache) begin |
| io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); |
| end else begin |
| io_cpu_writeBack_accessError = (((stageB_waysHits & stageB_tagsReadRsp_0_error) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); |
| end |
| end |
| |
| assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); |
| assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); |
| assign io_cpu_writeBack_isWrite = stageB_request_wr; |
| always @(*) begin |
| io_mem_cmd_valid = 1'b0; |
| if(io_cpu_writeBack_isValid) begin |
| if(!stageB_isExternalAmo) begin |
| if(when_DataCache_l977) begin |
| io_mem_cmd_valid = (! memCmdSent); |
| end else begin |
| if(when_DataCache_l990) begin |
| if(stageB_request_wr) begin |
| io_mem_cmd_valid = 1'b1; |
| end |
| end else begin |
| if(when_DataCache_l1018) begin |
| io_mem_cmd_valid = 1'b1; |
| end |
| end |
| end |
| end |
| end |
| if(when_DataCache_l1052) begin |
| io_mem_cmd_valid = 1'b0; |
| end |
| end |
| |
| always @(*) begin |
| io_mem_cmd_payload_address = stageB_mmuRsp_physicalAddress; |
| if(io_cpu_writeBack_isValid) begin |
| if(!stageB_isExternalAmo) begin |
| if(!when_DataCache_l977) begin |
| if(!when_DataCache_l990) begin |
| io_mem_cmd_payload_address[4 : 0] = 5'h0; |
| end |
| end |
| end |
| end |
| end |
| |
| assign io_mem_cmd_payload_last = 1'b1; |
| always @(*) begin |
| io_mem_cmd_payload_wr = stageB_request_wr; |
| if(io_cpu_writeBack_isValid) begin |
| if(!stageB_isExternalAmo) begin |
| if(!when_DataCache_l977) begin |
| if(!when_DataCache_l990) begin |
| io_mem_cmd_payload_wr = 1'b0; |
| end |
| end |
| end |
| end |
| end |
| |
| assign io_mem_cmd_payload_mask = stageB_mask; |
| assign io_mem_cmd_payload_data = stageB_requestDataBypass; |
| assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; |
| always @(*) begin |
| io_mem_cmd_payload_size = {1'd0, stageB_request_size}; |
| if(io_cpu_writeBack_isValid) begin |
| if(!stageB_isExternalAmo) begin |
| if(!when_DataCache_l977) begin |
| if(!when_DataCache_l990) begin |
| io_mem_cmd_payload_size = 3'b101; |
| end |
| end |
| end |
| end |
| end |
| |
| assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); |
| assign io_cpu_writeBack_keepMemRspData = 1'b0; |
| assign when_DataCache_l981 = ((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready); |
| assign when_DataCache_l990 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); |
| assign when_DataCache_l995 = ((! stageB_request_wr) || io_mem_cmd_ready); |
| assign when_DataCache_l1006 = (((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)); |
| assign when_DataCache_l1018 = (! memCmdSent); |
| assign when_DataCache_l977 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); |
| always @(*) begin |
| if(stageB_bypassCache) begin |
| io_cpu_writeBack_data = stageB_ioMemRspMuxed; |
| end else begin |
| io_cpu_writeBack_data = stageB_dataMux; |
| end |
| end |
| |
| assign when_DataCache_l1052 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); |
| assign when_DataCache_l1061 = (io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)); |
| always @(*) begin |
| loader_counter_willIncrement = 1'b0; |
| if(when_DataCache_l1076) begin |
| loader_counter_willIncrement = 1'b1; |
| end |
| end |
| |
| assign loader_counter_willClear = 1'b0; |
| assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111); |
| assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); |
| always @(*) begin |
| loader_counter_valueNext = (loader_counter_value + _zz_loader_counter_valueNext); |
| if(loader_counter_willClear) begin |
| loader_counter_valueNext = 3'b000; |
| end |
| end |
| |
| assign loader_kill = 1'b0; |
| assign when_DataCache_l1076 = ((loader_valid && io_mem_rsp_valid) && rspLast); |
| assign loader_done = loader_counter_willOverflow; |
| assign when_DataCache_l1104 = (! loader_valid); |
| assign when_DataCache_l1108 = (loader_valid && (! loader_valid_regNext)); |
| assign io_cpu_execute_refilling = loader_valid; |
| assign when_DataCache_l1111 = (stageB_loaderValid || loader_valid); |
| assign _zz_ways_0_tagsReadRsp_valid_1 = _zz_ways_0_tagsReadRsp_valid_3; |
| always @(posedge clk) begin |
| tagsWriteLastCmd_valid <= tagsWriteCmd_valid; |
| tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; |
| tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; |
| tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; |
| tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; |
| if(when_DataCache_l764) begin |
| stageA_request_wr <= io_cpu_execute_args_wr; |
| stageA_request_size <= io_cpu_execute_args_size; |
| stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; |
| end |
| if(when_DataCache_l764_1) begin |
| stageA_mask <= stage0_mask; |
| end |
| if(when_DataCache_l764_2) begin |
| stageA_wayInvalidate <= stage0_wayInvalidate; |
| end |
| if(when_DataCache_l764_3) begin |
| stage0_dataColisions_regNextWhen <= stage0_dataColisions; |
| end |
| if(when_DataCache_l815) begin |
| stageB_request_wr <= stageA_request_wr; |
| stageB_request_size <= stageA_request_size; |
| stageB_request_totalyConsistent <= stageA_request_totalyConsistent; |
| end |
| if(when_DataCache_l817) begin |
| stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; |
| stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; |
| stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; |
| stageB_mmuRsp_allowRead <= io_cpu_memory_mmuRsp_allowRead; |
| stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuRsp_allowWrite; |
| stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuRsp_allowExecute; |
| stageB_mmuRsp_exception <= io_cpu_memory_mmuRsp_exception; |
| stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; |
| stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; |
| stageB_mmuRsp_ways_0_sel <= io_cpu_memory_mmuRsp_ways_0_sel; |
| stageB_mmuRsp_ways_0_physical <= io_cpu_memory_mmuRsp_ways_0_physical; |
| stageB_mmuRsp_ways_1_sel <= io_cpu_memory_mmuRsp_ways_1_sel; |
| stageB_mmuRsp_ways_1_physical <= io_cpu_memory_mmuRsp_ways_1_physical; |
| stageB_mmuRsp_ways_2_sel <= io_cpu_memory_mmuRsp_ways_2_sel; |
| stageB_mmuRsp_ways_2_physical <= io_cpu_memory_mmuRsp_ways_2_physical; |
| stageB_mmuRsp_ways_3_sel <= io_cpu_memory_mmuRsp_ways_3_sel; |
| stageB_mmuRsp_ways_3_physical <= io_cpu_memory_mmuRsp_ways_3_physical; |
| end |
| if(when_DataCache_l814) begin |
| stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; |
| stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; |
| stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; |
| end |
| if(when_DataCache_l814_1) begin |
| stageB_dataReadRsp_0 <= ways_0_dataReadRsp; |
| end |
| if(when_DataCache_l813) begin |
| stageB_wayInvalidate <= stageA_wayInvalidate; |
| end |
| if(when_DataCache_l813_1) begin |
| stageB_dataColisions <= stageA_dataColisions; |
| end |
| if(when_DataCache_l813_2) begin |
| stageB_unaligned <= ({((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)),((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))} != 2'b00); |
| end |
| if(when_DataCache_l813_3) begin |
| stageB_waysHitsBeforeInvalidate <= stageA_wayHits; |
| end |
| if(when_DataCache_l813_4) begin |
| stageB_mask <= stageA_mask; |
| end |
| loader_valid_regNext <= loader_valid; |
| if(when_Phase_l650) begin |
| _zz_ways_0_tagsReadRsp_valid_2 <= _zz_ways_0_tagsReadRsp_valid_1; |
| end |
| if(when_Phase_l623) begin |
| _zz_ways_0_tagsReadRsp_valid_3 <= {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; |
| end |
| end |
| |
| always @(posedge clk or posedge reset) begin |
| if(reset) begin |
| memCmdSent <= 1'b0; |
| stageB_flusher_waitDone <= 1'b0; |
| stageB_flusher_counter <= 1'b0; |
| stageB_flusher_start <= 1'b1; |
| loader_valid <= 1'b0; |
| loader_counter_value <= 3'b000; |
| loader_waysAllocator <= 1'b1; |
| loader_error <= 1'b0; |
| loader_killReg <= 1'b0; |
| end else begin |
| if(io_mem_cmd_fire) begin |
| memCmdSent <= 1'b1; |
| end |
| if(when_DataCache_l679) begin |
| memCmdSent <= 1'b0; |
| end |
| if(io_cpu_flush_ready) begin |
| stageB_flusher_waitDone <= 1'b0; |
| end |
| if(when_DataCache_l843) begin |
| if(when_DataCache_l849) begin |
| stageB_flusher_counter <= (stageB_flusher_counter + 1'b1); |
| end |
| end |
| stageB_flusher_start <= (((((((! stageB_flusher_waitDone) && (! stageB_flusher_start)) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); |
| if(stageB_flusher_start) begin |
| stageB_flusher_waitDone <= 1'b1; |
| stageB_flusher_counter <= 1'b0; |
| end |
| `ifndef SYNTHESIS |
| `ifdef FORMAL |
| assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); |
| `else |
| if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin |
| $display("ERROR writeBack stuck by another plugin is not allowed"); |
| end |
| `endif |
| `endif |
| if(stageB_loaderValid) begin |
| loader_valid <= 1'b1; |
| end |
| loader_counter_value <= loader_counter_valueNext; |
| if(loader_kill) begin |
| loader_killReg <= 1'b1; |
| end |
| if(when_DataCache_l1076) begin |
| loader_error <= (loader_error || io_mem_rsp_payload_error); |
| end |
| if(loader_done) begin |
| loader_valid <= 1'b0; |
| loader_error <= 1'b0; |
| loader_killReg <= 1'b0; |
| end |
| if(when_DataCache_l1104) begin |
| loader_waysAllocator <= _zz_loader_waysAllocator[0:0]; |
| end |
| end |
| end |
| |
| |
| endmodule |
| |
| module InstructionCache ( |
| `ifdef USE_POWER_PINS |
| inout vccd1, // User area 1 1.8V supply |
| inout vssd1, // User area 1 digital ground |
| `endif |
| input io_flush, |
| input io_cpu_prefetch_isValid, |
| output reg io_cpu_prefetch_haltIt, |
| input [31:0] io_cpu_prefetch_pc, |
| input io_cpu_fetch_isValid, |
| input io_cpu_fetch_isStuck, |
| input io_cpu_fetch_isRemoved, |
| input [31:0] io_cpu_fetch_pc, |
| output [31:0] io_cpu_fetch_data, |
| input [31:0] io_cpu_fetch_mmuRsp_physicalAddress, |
| input io_cpu_fetch_mmuRsp_isIoAccess, |
| input io_cpu_fetch_mmuRsp_isPaging, |
| input io_cpu_fetch_mmuRsp_allowRead, |
| input io_cpu_fetch_mmuRsp_allowWrite, |
| input io_cpu_fetch_mmuRsp_allowExecute, |
| input io_cpu_fetch_mmuRsp_exception, |
| input io_cpu_fetch_mmuRsp_refilling, |
| input io_cpu_fetch_mmuRsp_bypassTranslation, |
| input io_cpu_fetch_mmuRsp_ways_0_sel, |
| input [31:0] io_cpu_fetch_mmuRsp_ways_0_physical, |
| input io_cpu_fetch_mmuRsp_ways_1_sel, |
| input [31:0] io_cpu_fetch_mmuRsp_ways_1_physical, |
| input io_cpu_fetch_mmuRsp_ways_2_sel, |
| input [31:0] io_cpu_fetch_mmuRsp_ways_2_physical, |
| input io_cpu_fetch_mmuRsp_ways_3_sel, |
| input [31:0] io_cpu_fetch_mmuRsp_ways_3_physical, |
| output [31:0] io_cpu_fetch_physicalAddress, |
| input io_cpu_decode_isValid, |
| input io_cpu_decode_isStuck, |
| input [31:0] io_cpu_decode_pc, |
| output [31:0] io_cpu_decode_physicalAddress, |
| output [31:0] io_cpu_decode_data, |
| output io_cpu_decode_cacheMiss, |
| output io_cpu_decode_error, |
| output io_cpu_decode_mmuRefilling, |
| output io_cpu_decode_mmuException, |
| input io_cpu_decode_isUser, |
| input io_cpu_fill_valid, |
| input [31:0] io_cpu_fill_payload, |
| output io_mem_cmd_valid, |
| input io_mem_cmd_ready, |
| output [31:0] io_mem_cmd_payload_address, |
| output [2:0] io_mem_cmd_payload_size, |
| input io_mem_rsp_valid, |
| input [31:0] io_mem_rsp_payload_data, |
| input io_mem_rsp_payload_error, |
| input [2:0] _zz_when_Fetcher_l398, |
| input [31:0] _zz_decodeStage_hit_data_1, |
| input clk, |
| input reset |
| ); |
| |
| reg [31:0] _zz_banks_0_port1; |
| reg _zz_1; |
| reg when_Phase_l623; |
| reg lineLoader_fire; |
| reg lineLoader_valid; |
| (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; |
| reg lineLoader_hadError; |
| reg lineLoader_flushPending; |
| reg [0:0] lineLoader_flushCounter; |
| wire when_InstructionCache_l338; |
| reg _zz_when_InstructionCache_l342; |
| wire when_InstructionCache_l342; |
| wire when_InstructionCache_l351; |
| reg lineLoader_cmdSent; |
| wire io_mem_cmd_fire; |
| wire when_Utils_l489; |
| reg lineLoader_wayToAllocate_willIncrement; |
| wire lineLoader_wayToAllocate_willClear; |
| wire lineLoader_wayToAllocate_willOverflowIfInc; |
| wire lineLoader_wayToAllocate_willOverflow; |
| (* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; |
| wire lineLoader_write_tag_0_valid; |
| wire lineLoader_write_tag_0_payload_data_valid; |
| wire lineLoader_write_tag_0_payload_data_error; |
| wire [26:0] lineLoader_write_tag_0_payload_data_address; |
| wire lineLoader_write_data_0_valid; |
| wire [2:0] lineLoader_write_data_0_payload_address; |
| wire [31:0] lineLoader_write_data_0_payload_data; |
| wire when_InstructionCache_l401; |
| wire [2:0] _zz_fetchStage_read_banksValue_0_dataMem; |
| wire _zz_fetchStage_read_banksValue_0_dataMem_1; |
| wire [31:0] fetchStage_read_banksValue_0_dataMem; |
| wire [31:0] fetchStage_read_banksValue_0_data; |
| wire when_Phase_l650; |
| wire fetchStage_read_waysValues_0_tag_valid; |
| wire fetchStage_read_waysValues_0_tag_error; |
| wire [26:0] fetchStage_read_waysValues_0_tag_address; |
| wire [28:0] _zz_fetchStage_read_waysValues_0_tag_valid; |
| wire when_InstructionCache_l459; |
| reg [31:0] decodeStage_mmuRsp_physicalAddress; |
| reg decodeStage_mmuRsp_isIoAccess; |
| reg decodeStage_mmuRsp_isPaging; |
| reg decodeStage_mmuRsp_allowRead; |
| reg decodeStage_mmuRsp_allowWrite; |
| reg decodeStage_mmuRsp_allowExecute; |
| reg decodeStage_mmuRsp_exception; |
| reg decodeStage_mmuRsp_refilling; |
| reg decodeStage_mmuRsp_bypassTranslation; |
| reg decodeStage_mmuRsp_ways_0_sel; |
| reg [31:0] decodeStage_mmuRsp_ways_0_physical; |
| reg decodeStage_mmuRsp_ways_1_sel; |
| reg [31:0] decodeStage_mmuRsp_ways_1_physical; |
| reg decodeStage_mmuRsp_ways_2_sel; |
| reg [31:0] decodeStage_mmuRsp_ways_2_physical; |
| reg decodeStage_mmuRsp_ways_3_sel; |
| reg [31:0] decodeStage_mmuRsp_ways_3_physical; |
| wire when_InstructionCache_l459_1; |
| reg decodeStage_hit_tags_0_valid; |
| reg decodeStage_hit_tags_0_error; |
| reg [26:0] decodeStage_hit_tags_0_address; |
| wire decodeStage_hit_hits_0; |
| wire decodeStage_hit_valid; |
| wire when_InstructionCache_l459_2; |
| reg [31:0] _zz_decodeStage_hit_data; |
| wire [31:0] decodeStage_hit_data; |
| wire when_Fetcher_l398; |
| wire [28:0] _zz_fetchStage_read_waysValues_0_tag_valid_1; |
| reg [28:0] _zz_fetchStage_read_waysValues_0_tag_valid_2; |
| reg [28:0] _zz_fetchStage_read_waysValues_0_tag_valid_3; |
| reg [31:0] banks_0 [0:7]; |
| |
| always @(posedge clk) begin |
| if(_zz_1) begin |
| banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; |
| end |
| end |
| |
| always @(posedge clk) begin |
| if(_zz_fetchStage_read_banksValue_0_dataMem_1) begin |
| _zz_banks_0_port1 <= banks_0[_zz_fetchStage_read_banksValue_0_dataMem]; |
| end |
| end |
| |
| always @(*) begin |
| _zz_1 = 1'b0; |
| if(lineLoader_write_data_0_valid) begin |
| _zz_1 = 1'b1; |
| end |
| end |
| |
| always @(*) begin |
| when_Phase_l623 = 1'b0; |
| if(lineLoader_write_tag_0_valid) begin |
| when_Phase_l623 = 1'b1; |
| end |
| end |
| |
| always @(*) begin |
| lineLoader_fire = 1'b0; |
| if(io_mem_rsp_valid) begin |
| if(when_InstructionCache_l401) begin |
| lineLoader_fire = 1'b1; |
| end |
| end |
| end |
| |
| always @(*) begin |
| io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); |
| if(when_InstructionCache_l338) begin |
| io_cpu_prefetch_haltIt = 1'b1; |
| end |
| if(when_InstructionCache_l342) begin |
| io_cpu_prefetch_haltIt = 1'b1; |
| end |
| if(io_flush) begin |
| io_cpu_prefetch_haltIt = 1'b1; |
| end |
| end |
| |
| assign when_InstructionCache_l338 = (! lineLoader_flushCounter[0]); |
| assign when_InstructionCache_l342 = (! _zz_when_InstructionCache_l342); |
| assign when_InstructionCache_l351 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); |
| assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); |
| assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); |
| assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; |
| assign io_mem_cmd_payload_size = 3'b101; |
| assign when_Utils_l489 = (! lineLoader_valid); |
| always @(*) begin |
| lineLoader_wayToAllocate_willIncrement = 1'b0; |
| if(when_Utils_l489) begin |
| lineLoader_wayToAllocate_willIncrement = 1'b1; |
| end |
| end |
| |
| assign lineLoader_wayToAllocate_willClear = 1'b0; |
| assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; |
| assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); |
| assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[0])); |
| assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[0]; |
| assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); |
| assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 5]; |
| assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); |
| assign lineLoader_write_data_0_payload_address = lineLoader_wordIndex; |
| assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; |
| assign when_InstructionCache_l401 = (lineLoader_wordIndex == 3'b111); |
| assign _zz_fetchStage_read_banksValue_0_dataMem = io_cpu_prefetch_pc[4 : 2]; |
| assign _zz_fetchStage_read_banksValue_0_dataMem_1 = (! io_cpu_fetch_isStuck); |
| assign fetchStage_read_banksValue_0_dataMem = _zz_banks_0_port1; |
| assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; |
| assign when_Phase_l650 = (! io_cpu_fetch_isStuck); |
| assign _zz_fetchStage_read_waysValues_0_tag_valid = _zz_fetchStage_read_waysValues_0_tag_valid_3; |
| assign fetchStage_read_waysValues_0_tag_valid = _zz_fetchStage_read_waysValues_0_tag_valid[0]; |
| assign fetchStage_read_waysValues_0_tag_error = _zz_fetchStage_read_waysValues_0_tag_valid[1]; |
| assign fetchStage_read_waysValues_0_tag_address = _zz_fetchStage_read_waysValues_0_tag_valid[28 : 2]; |
| assign io_cpu_fetch_data = fetchStage_read_banksValue_0_data; |
| assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; |
| assign when_InstructionCache_l459 = (! io_cpu_decode_isStuck); |
| assign when_InstructionCache_l459_1 = (! io_cpu_decode_isStuck); |
| assign decodeStage_hit_hits_0 = (decodeStage_hit_tags_0_valid && (decodeStage_hit_tags_0_address == decodeStage_mmuRsp_physicalAddress[31 : 5])); |
| assign decodeStage_hit_valid = (|decodeStage_hit_hits_0); |
| assign when_InstructionCache_l459_2 = (! io_cpu_decode_isStuck); |
| assign decodeStage_hit_data = _zz_decodeStage_hit_data; |
| assign io_cpu_decode_data = decodeStage_hit_data; |
| assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); |
| assign io_cpu_decode_error = (decodeStage_hit_tags_0_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); |
| assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; |
| assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); |
| assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; |
| assign when_Fetcher_l398 = (_zz_when_Fetcher_l398 != 3'b000); |
| assign _zz_fetchStage_read_waysValues_0_tag_valid_1 = _zz_fetchStage_read_waysValues_0_tag_valid_2; |
| always @(posedge clk or posedge reset) begin |
| if(reset) begin |
| lineLoader_valid <= 1'b0; |
| lineLoader_hadError <= 1'b0; |
| lineLoader_flushPending <= 1'b1; |
| lineLoader_cmdSent <= 1'b0; |
| lineLoader_wordIndex <= 3'b000; |
| end else begin |
| if(lineLoader_fire) begin |
| lineLoader_valid <= 1'b0; |
| end |
| if(lineLoader_fire) begin |
| lineLoader_hadError <= 1'b0; |
| end |
| if(io_cpu_fill_valid) begin |
| lineLoader_valid <= 1'b1; |
| end |
| if(io_flush) begin |
| lineLoader_flushPending <= 1'b1; |
| end |
| if(when_InstructionCache_l351) begin |
| lineLoader_flushPending <= 1'b0; |
| end |
| if(io_mem_cmd_fire) begin |
| lineLoader_cmdSent <= 1'b1; |
| end |
| if(lineLoader_fire) begin |
| lineLoader_cmdSent <= 1'b0; |
| end |
| if(io_mem_rsp_valid) begin |
| lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); |
| if(io_mem_rsp_payload_error) begin |
| lineLoader_hadError <= 1'b1; |
| end |
| end |
| end |
| end |
| |
| always @(posedge clk) begin |
| if(io_cpu_fill_valid) begin |
| lineLoader_address <= io_cpu_fill_payload; |
| end |
| if(when_InstructionCache_l338) begin |
| lineLoader_flushCounter <= (lineLoader_flushCounter + 1'b1); |
| end |
| _zz_when_InstructionCache_l342 <= lineLoader_flushCounter[0]; |
| if(when_InstructionCache_l351) begin |
| lineLoader_flushCounter <= 1'b0; |
| end |
| if(when_InstructionCache_l459) begin |
| decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; |
| decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; |
| decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; |
| decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead; |
| decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite; |
| decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute; |
| decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuRsp_exception; |
| decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; |
| decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; |
| decodeStage_mmuRsp_ways_0_sel <= io_cpu_fetch_mmuRsp_ways_0_sel; |
| decodeStage_mmuRsp_ways_0_physical <= io_cpu_fetch_mmuRsp_ways_0_physical; |
| decodeStage_mmuRsp_ways_1_sel <= io_cpu_fetch_mmuRsp_ways_1_sel; |
| decodeStage_mmuRsp_ways_1_physical <= io_cpu_fetch_mmuRsp_ways_1_physical; |
| decodeStage_mmuRsp_ways_2_sel <= io_cpu_fetch_mmuRsp_ways_2_sel; |
| decodeStage_mmuRsp_ways_2_physical <= io_cpu_fetch_mmuRsp_ways_2_physical; |
| decodeStage_mmuRsp_ways_3_sel <= io_cpu_fetch_mmuRsp_ways_3_sel; |
| decodeStage_mmuRsp_ways_3_physical <= io_cpu_fetch_mmuRsp_ways_3_physical; |
| end |
| if(when_InstructionCache_l459_1) begin |
| decodeStage_hit_tags_0_valid <= fetchStage_read_waysValues_0_tag_valid; |
| decodeStage_hit_tags_0_error <= fetchStage_read_waysValues_0_tag_error; |
| decodeStage_hit_tags_0_address <= fetchStage_read_waysValues_0_tag_address; |
| end |
| if(when_InstructionCache_l459_2) begin |
| _zz_decodeStage_hit_data <= fetchStage_read_banksValue_0_data; |
| end |
| if(when_Fetcher_l398) begin |
| _zz_decodeStage_hit_data <= _zz_decodeStage_hit_data_1; |
| end |
| if(when_Phase_l623) begin |
| _zz_fetchStage_read_waysValues_0_tag_valid_2 <= {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; |
| end |
| if(when_Phase_l650) begin |
| _zz_fetchStage_read_waysValues_0_tag_valid_3 <= _zz_fetchStage_read_waysValues_0_tag_valid_1; |
| end |
| end |
| |
| |
| endmodule |
| |
| module FlowCCByToggle ( |
| `ifdef USE_POWER_PINS |
| inout vccd1, // User area 1 1.8V supply |
| inout vssd1, // User area 1 digital ground |
| `endif |
| input io_input_valid, |
| input io_input_payload_last, |
| input [0:0] io_input_payload_fragment, |
| output io_output_valid, |
| output io_output_payload_last, |
| output [0:0] io_output_payload_fragment, |
| input io_jtag_tck, |
| input clk, |
| input jtag_rst |
| ); |
| |
| wire inputArea_target_buffercc_io_dataOut; |
| wire outHitSignal; |
| reg inputArea_target = 0; |
| reg inputArea_data_last; |
| reg [0:0] inputArea_data_fragment; |
| wire outputArea_target; |
| reg outputArea_hit; |
| wire outputArea_flow_valid; |
| wire outputArea_flow_payload_last; |
| wire [0:0] outputArea_flow_payload_fragment; |
| reg outputArea_flow_m2sPipe_valid; |
| reg outputArea_flow_m2sPipe_payload_last; |
| reg [0:0] outputArea_flow_m2sPipe_payload_fragment; |
| |
| BufferCC inputArea_target_buffercc ( |
| `ifdef USE_POWER_PINS |
| .vccd1(vccd1), // User area 1 1.8V power |
| .vssd1(vssd1), // User area 1 digital ground |
| `endif |
| .io_dataIn (inputArea_target ), //i |
| .io_dataOut (inputArea_target_buffercc_io_dataOut ), //o |
| .clk (clk ), //i |
| .jtag_rst (jtag_rst ) //i |
| ); |
| assign outputArea_target = inputArea_target_buffercc_io_dataOut; |
| assign outputArea_flow_valid = (outputArea_target != outputArea_hit); |
| assign outputArea_flow_payload_last = inputArea_data_last; |
| assign outputArea_flow_payload_fragment = inputArea_data_fragment; |
| assign io_output_valid = outputArea_flow_m2sPipe_valid; |
| assign io_output_payload_last = outputArea_flow_m2sPipe_payload_last; |
| assign io_output_payload_fragment = outputArea_flow_m2sPipe_payload_fragment; |
| always @(posedge io_jtag_tck) begin |
| if(io_input_valid) begin |
| inputArea_target <= (! inputArea_target); |
| inputArea_data_last <= io_input_payload_last; |
| inputArea_data_fragment <= io_input_payload_fragment; |
| end |
| end |
| |
| always @(posedge clk) begin |
| outputArea_hit <= outputArea_target; |
| if(outputArea_flow_valid) begin |
| outputArea_flow_m2sPipe_payload_last <= outputArea_flow_payload_last; |
| outputArea_flow_m2sPipe_payload_fragment <= outputArea_flow_payload_fragment; |
| end |
| end |
| |
| always @(posedge clk or posedge jtag_rst) begin |
| if(jtag_rst) begin |
| outputArea_flow_m2sPipe_valid <= 1'b0; |
| end else begin |
| outputArea_flow_m2sPipe_valid <= outputArea_flow_valid; |
| end |
| end |
| |
| |
| endmodule |
| |
| module BufferCC ( |
| `ifdef USE_POWER_PINS |
| inout vccd1, // User area 1 1.8V supply |
| inout vssd1, // User area 1 digital ground |
| `endif |
| input io_dataIn, |
| output io_dataOut, |
| input clk, |
| input jtag_rst |
| ); |
| |
| (* async_reg = "true" *) reg buffers_0; |
| (* async_reg = "true" *) reg buffers_1; |
| |
| assign io_dataOut = buffers_1; |
| always @(posedge clk) begin |
| buffers_0 <= io_dataIn; |
| buffers_1 <= buffers_0; |
| end |
| |
| |
| endmodule |