removing old test
diff --git a/verilog/dv/mprj_stimulus/Makefile b/verilog/dv/mprj_stimulus/Makefile deleted file mode 100644 index 3fd0b56..0000000 --- a/verilog/dv/mprj_stimulus/Makefile +++ /dev/null
@@ -1,32 +0,0 @@ -# SPDX-FileCopyrightText: 2020 Efabless Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# SPDX-License-Identifier: Apache-2.0 - - - -PWDD := $(shell pwd) -BLOCKS := $(shell basename $(PWDD)) - -# ---- Include Partitioned Makefiles ---- - -CONFIG = caravel_user_project - - -include $(MCW_ROOT)/verilog/dv/make/env.makefile -include $(MCW_ROOT)/verilog/dv/make/var.makefile -include $(MCW_ROOT)/verilog/dv/make/cpu.makefile -include $(MCW_ROOT)/verilog/dv/make/sim.makefile - -
diff --git a/verilog/dv/mprj_stimulus/mprj_stimulus.c b/verilog/dv/mprj_stimulus/mprj_stimulus.c deleted file mode 100644 index d049848..0000000 --- a/verilog/dv/mprj_stimulus/mprj_stimulus.c +++ /dev/null
@@ -1,134 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020 Efabless Corporation - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * SPDX-License-Identifier: Apache-2.0 - */ - -// This include is relative to $CARAVEL_PATH (see Makefile) -#include <defs.h> - -// -------------------------------------------------------- - -void main() -{ - // The upper GPIO pins are configured to be output - // and accessble to the management SoC. - // Used to flag the start/end of a test - // The lower GPIO pins are configured to be output - // and accessible to the user project. They show - // the project count value, although this test is - // designed to read the project count through the - // logic analyzer probes. - // I/O 6 is configured for the UART Tx line - - uint32_t testval; - - reg_mprj_datal = 0x00000000; - reg_mprj_datah = 0x00000000; - - reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT; - - reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT; - - reg_mprj_io_15 = GPIO_MODE_USER_STD_OUT_MONITORED; - reg_mprj_io_14 = GPIO_MODE_USER_STD_OUT_MONITORED; - reg_mprj_io_13 = GPIO_MODE_USER_STD_OUT_MONITORED; - reg_mprj_io_12 = GPIO_MODE_USER_STD_OUT_MONITORED; - reg_mprj_io_11 = GPIO_MODE_USER_STD_OUT_MONITORED; - reg_mprj_io_10 = GPIO_MODE_USER_STD_OUT_MONITORED; - reg_mprj_io_9 = GPIO_MODE_USER_STD_OUT_MONITORED; - reg_mprj_io_8 = GPIO_MODE_USER_STD_OUT_MONITORED; - reg_mprj_io_7 = GPIO_MODE_USER_STD_OUT_MONITORED; - reg_mprj_io_6 = GPIO_MODE_USER_STD_OUT_MONITORED; - reg_mprj_io_5 = GPIO_MODE_USER_STD_OUT_MONITORED; - reg_mprj_io_4 = GPIO_MODE_USER_STD_OUT_MONITORED; - reg_mprj_io_3 = GPIO_MODE_USER_STD_OUT_MONITORED; - reg_mprj_io_2 = GPIO_MODE_USER_STD_OUT_MONITORED; - reg_mprj_io_1 = GPIO_MODE_USER_STD_OUT_MONITORED; - reg_mprj_io_0 = GPIO_MODE_USER_STD_OUT_MONITORED; - - /* Apply configuration */ - reg_mprj_xfer = 1; - while (reg_mprj_xfer == 1); - - /* TEST: Recast channels 35 to 32 to allow input to user project */ - /* This is done locally only: Do not run reg_mprj_xfer! */ - reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT; - - // Configure LA probes [31:0], [127:64] as inputs to the cpu - // Configure LA probes [63:32] as outputs from the cpu - reg_la0_oenb = reg_la0_iena = 0x00000000; // [31:0] - reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF; // [63:32] - reg_la2_oenb = reg_la2_iena = 0x00000000; // [95:64] - reg_la3_oenb = reg_la3_iena = 0x00000000; // [127:96] - - // Flag start of the test - reg_mprj_datal = 0xAB400000; - - // Set Counter value to zero through LA probes [63:32] - reg_la1_data = 0x00000000; - - // Configure LA probes from [63:32] as inputs to disable counter write - reg_la1_oenb = reg_la1_iena = 0x00000000; - - reg_mprj_datal = 0xAB410000; - reg_mprj_datah = 0x00000000; - - // Test ability to force data on channel 37 - // NOTE: Only the low 6 bits of reg_mprj_datah are meaningful - - reg_mprj_datah = 0x0f0f0fc0; - reg_mprj_datah = 0x00000000; - reg_mprj_datah = 0x0f0f0fca; - reg_mprj_datah = 0x0000000a; - reg_mprj_datah = 0x0f0f0fc0; - reg_mprj_datah = 0x00000000; - reg_mprj_datah = 0x0f0f0fc5; - reg_mprj_datah = 0x00000005; - - // Test ability to read back data generated by the user project - // on the "monitored" outputs. Read from the lower 16 bits and - // copy the value to the upper 16 bits. - - testval = reg_mprj_datal; - reg_mprj_datal = (testval << 16); - testval = reg_mprj_datal; - reg_mprj_datal = (testval << 16); - - // Flag end of the test - reg_mprj_datal = 0xAB510000; -}
diff --git a/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v b/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v deleted file mode 100644 index 68addd0..0000000 --- a/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v +++ /dev/null
@@ -1,148 +0,0 @@ -// SPDX-FileCopyrightText: 2020 Efabless Corporation -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 - -`default_nettype wire - -`timescale 1 ns / 1 ps - -module mprj_stimulus_tb; - // Signals declaration - reg clock; - reg RSTB; - reg power1, power2; - reg CSB; - wire gpio; - wire [37:0] mprj_io; - wire [15:0] checkbits; - wire [3:0] status; - - // Signals Assignment - assign checkbits = mprj_io[31:16]; - assign status = mprj_io[35:32]; - - assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz; - - always #12.5 clock <= (clock === 1'b0); - - initial begin - clock = 0; - end - - initial begin - $dumpfile("mprj_stimulus.vcd"); - $dumpvars(0, mprj_stimulus_tb); - - // Repeat cycles of 1000 clock edges as needed to complete testbench - repeat (100) begin - repeat (1000) @(posedge clock); - end - $display("%c[1;31m",27); - `ifdef GL - $display ("Monitor: Timeout, Test Project IO Stimulus (GL) Failed"); - `else - $display ("Monitor: Timeout, Test Project IO Stimulus (RTL) Failed"); - `endif - $display("%c[0m",27); - $finish; - end - - initial begin - wait(checkbits == 16'hAB40); - $display("Monitor: mprj_stimulus test started"); - wait(status == 4'ha); - wait(status == 4'h5); - - // Values reflect copying user-controlled outputs to memory and back - // to management-controlled outputs. - wait(checkbits == 16'h1968 || checkbits == 16'h1969); // They're off because the difference between GL and RTL - wait(checkbits == 16'h1DCD || checkbits == 16'h1DCE); // They're off because the difference between GL and RTL - - wait(checkbits == 16'hAB51); - $display("Monitor: mprj_stimulus test Passed"); - #10000; - $finish; - end - - // Reset Operation - initial begin - CSB <= 1'b1; - RSTB <= 1'b0; - #2000; - RSTB <= 1'b1; // Release reset - #1000000; - CSB <= 1'b0; // Stop driving CSB - end - - initial begin // Power-up sequence - power1 <= 1'b0; - power2 <= 1'b0; - #200; - power1 <= 1'b1; - #200; - power2 <= 1'b1; - end - - wire flash_csb; - wire flash_clk; - wire flash_io0; - wire flash_io1; - - wire VDD3V3 = power1; - wire VDD1V8 = power2; - wire VSS = 1'b0; - - caravel uut ( - .vddio (VDD3V3), - .vddio_2 (VDD3V3), - .vssio (VSS), - .vssio_2 (VSS), - .vdda (VDD3V3), - .vssa (VSS), - .vccd (VDD1V8), - .vssd (VSS), - .vdda1 (VDD3V3), - .vdda1_2 (VDD3V3), - .vdda2 (VDD3V3), - .vssa1 (VSS), - .vssa1_2 (VSS), - .vssa2 (VSS), - .vccd1 (VDD1V8), - .vccd2 (VDD1V8), - .vssd1 (VSS), - .vssd2 (VSS), - .clock (clock), - .gpio (gpio), - .mprj_io (mprj_io), - .flash_csb(flash_csb), - .flash_clk(flash_clk), - .flash_io0(flash_io0), - .flash_io1(flash_io1), - .resetb (RSTB) - ); - - - spiflash #( - .FILENAME("mprj_stimulus.hex") - ) spiflash ( - .csb(flash_csb), - .clk(flash_clk), - .io0(flash_io0), - .io1(flash_io1), - .io2(), // not used - .io3() // not used - ); - -endmodule -`default_nettype wire \ No newline at end of file