verilog/includes/includes.rtl.caravel_user_project

# Caravel user project includes
-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v
//  0 Function generator             : /home/matt/work/asic-workshop/shuttle5/openlane/designs/wrapped_function_generator
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_function_generator/wrapper.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_function_generator/function_generator/src/generator.v
//  1 VGA Clock                      : /home/matt/work/asic-workshop/shuttle5/openlane/designs/wrapped_vga_clock
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_vga_clock/wrapper.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_vga_clock/vga_clock/rtl/button_pulse.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_vga_clock/vga_clock/rtl/digit.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_vga_clock/vga_clock/rtl/fontROM.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_vga_clock/vga_clock/rtl/top.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_vga_clock/vga_clock/rtl/vga_clock.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_vga_clock/vga_clock/rtl/VgaSyncGen.v
//  2 Frequency counter              : /home/matt/work/asic-workshop/shuttle5/openlane/designs/wrapped_frequency_counter
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_frequency_counter/wrapper.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_frequency_counter/frequency_counter/src/edge_detect.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_frequency_counter/frequency_counter/src/frequency_counter.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_frequency_counter/frequency_counter/src/seven_segment.v
//  3 RGB Mixer                      : /home/matt/work/asic-workshop/shuttle5/openlane/designs/wrapped_rgb_mixer
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_rgb_mixer/wrapper.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_rgb_mixer/rgb_mixer/src/debounce.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_rgb_mixer/rgb_mixer/src/encoder.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_rgb_mixer/rgb_mixer/src/pwm.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_rgb_mixer/rgb_mixer/src/rgb_mixer.v
// 11 Hack soc                       : /home/matt/work/asic-workshop/shuttle5/openlane/designs/wrapped_hack_soc
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_hack_soc/wrapped_hack_soc_dffram.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_hack_soc/hack_soc/src/dmux8way.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_hack_soc/hack_soc/src/hack_alu.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_hack_soc/hack_soc/src/hack_clock.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_hack_soc/hack_soc/src/hack_cpu.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_hack_soc/hack_soc/src/hack_soc.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_hack_soc/hack_soc/src/pc.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_hack_soc/hack_soc/src/register.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_hack_soc/hack_soc/src/spi_sram_encoder.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_hack_soc/hack_soc/src/video_signal_generator_640x480.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_hack_soc/hack_soc/src/spi_video_ram_2.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_hack_soc/hack_soc/src/vram_write_fifo.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_hack_soc/hack_soc/src/rom_stream_loader.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_hack_soc/hack_soc/src/boot_logo.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_hack_soc/hack_soc/src/DFFRF_2R1W.v
// shared Bridge                     : /home/matt/work/asic-workshop/shuttle5/openlane/designs/wb_bridge
// shared Wrapper                    : /home/matt/work/asic-workshop/shuttle5/openlane/designs/wb_openram_wrapper
// shared OpenRAM 1kybte             : /home/matt/work/asic-workshop/shuttle5/openlane/designs/openram_z2a
-v $(USER_PROJECT_VERILOG)/rtl/wb_bridge/src/wb_bridge_2way.v
-v $(USER_PROJECT_VERILOG)/rtl/wb_openram_wrapper/src/register_rw.v
-v $(USER_PROJECT_VERILOG)/rtl/wb_openram_wrapper/src/wb_port_control.v
-v $(USER_PROJECT_VERILOG)/rtl/wb_openram_wrapper/src/wb_openram_wrapper.v
-v $(USER_PROJECT_VERILOG)/rtl/openram_z2a/src/sky130_sram_1kbyte_1rw1r_32x256_8.v