final gds oasis

commit: f3cc5b019c8de45c694e36e595f7c53aef13b960 [log] [tgz]
author: Jeff DiCorpo <jeffdi@efabless.com> Sun Jan 09 11:59:47 2022 -0800
committer: Jeff DiCorpo <jeffdi@efabless.com> Sun Jan 09 11:59:47 2022 -0800
tree: 73409fef5269a49c929ee322b0a83bb3ca1c48b6
parent: bc6ec67ad103fb72ee006b8d67ca22affd254b30 [diff]
diff --git a/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/gds.info b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/gds.info
new file mode 100644
index 0000000..748a0de
--- /dev/null
+++ b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/gds.info

@@ -0,0 +1 @@
+user_analog_project_wrapper.gds: 18139089c43270a702a75d1d99c7bb9478a523d6
\ No newline at end of file

diff --git a/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/git.info b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/git.info
new file mode 100644
index 0000000..5ffcd4c
--- /dev/null
+++ b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/git.info

@@ -0,0 +1,3 @@
+Repository: https://github.com/chrische-xx/mpw4.git
+Branch: main
+Commit: bc6ec67ad103fb72ee006b8d67ca22affd254b30

diff --git a/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/klayout_beol_check.log b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/klayout_beol_check.log
new file mode 100644
index 0000000..043597c
--- /dev/null
+++ b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/klayout_beol_check.log

@@ -0,0 +1,992 @@
+/opt/checks/tech-files/sky130A_mr.drc:38: warning: already initialized constant DRC::DRCEngine::FEOL
+/opt/checks/tech-files/sky130A_mr.drc:28: warning: previous definition of FEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:42: warning: already initialized constant DRC::DRCEngine::BEOL
+/opt/checks/tech-files/sky130A_mr.drc:29: warning: previous definition of BEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:50: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/opt/checks/tech-files/sky130A_mr.drc:30: warning: previous definition of OFFGRID was here
+/opt/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::SEAL
+/opt/checks/tech-files/sky130A_mr.drc:31: warning: previous definition of SEAL was here
+/opt/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/opt/checks/tech-files/sky130A_mr.drc:32: warning: previous definition of FLOATING_MET was here
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+Writing report database: /mnt/uffs/user/u6303_christo/design/sar-adc_and_analog_circuits/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/reports/klayout_beol_check.xml ..
+Total elapsed: 17.850s  Memory: 1223.00M

diff --git a/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/klayout_beol_check.total b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/klayout_beol_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/klayout_beol_check.total

@@ -0,0 +1 @@
+0
\ No newline at end of file

diff --git a/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/klayout_feol_check.log b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/klayout_feol_check.log
new file mode 100644
index 0000000..b9cfec4
--- /dev/null
+++ b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/klayout_feol_check.log

@@ -0,0 +1,728 @@
+/opt/checks/tech-files/sky130A_mr.drc:36: warning: already initialized constant DRC::DRCEngine::FEOL
+/opt/checks/tech-files/sky130A_mr.drc:28: warning: previous definition of FEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:44: warning: already initialized constant DRC::DRCEngine::BEOL
+/opt/checks/tech-files/sky130A_mr.drc:29: warning: previous definition of BEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:50: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/opt/checks/tech-files/sky130A_mr.drc:30: warning: previous definition of OFFGRID was here
+/opt/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::SEAL
+/opt/checks/tech-files/sky130A_mr.drc:31: warning: previous definition of SEAL was here
+/opt/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/opt/checks/tech-files/sky130A_mr.drc:32: warning: previous definition of FLOATING_MET was here
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diff --git a/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/klayout_feol_check.total b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/klayout_feol_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/klayout_feol_check.total

@@ -0,0 +1 @@
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diff --git a/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/klayout_met_min_ca_density_check.log b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/klayout_met_min_ca_density_check.log
new file mode 100644
index 0000000..4ea7875
--- /dev/null
+++ b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/klayout_met_min_ca_density_check.log

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new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/klayout_met_min_ca_density_check.total

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+    Elapsed: 0.010s  Memory: 567.00M
+"ongrid" in: offgrid.lydrc:189
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 567.00M
+"output" in: offgrid.lydrc:189
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 567.00M
+"with_angle" in: offgrid.lydrc:190
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 567.00M
+"output" in: offgrid.lydrc:190
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 567.00M
+"ongrid" in: offgrid.lydrc:191
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 567.00M
+"output" in: offgrid.lydrc:191
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 567.00M
+"with_angle" in: offgrid.lydrc:192
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 567.00M
+"output" in: offgrid.lydrc:192
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 567.00M
+"ongrid" in: offgrid.lydrc:193
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 567.00M
+"output" in: offgrid.lydrc:193
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 567.00M
+"with_angle" in: offgrid.lydrc:194
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 567.00M
+"output" in: offgrid.lydrc:194
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 567.00M
+"ongrid" in: offgrid.lydrc:195
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 567.00M
+"output" in: offgrid.lydrc:195
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 567.00M
+"with_angle" in: offgrid.lydrc:196
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 567.00M
+"output" in: offgrid.lydrc:196
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 567.00M
+"ongrid" in: offgrid.lydrc:197
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 567.00M
+"output" in: offgrid.lydrc:197
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 567.00M
+"with_angle" in: offgrid.lydrc:198
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 567.00M
+"output" in: offgrid.lydrc:198
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 567.00M
+"ongrid" in: offgrid.lydrc:199
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 567.00M
+"output" in: offgrid.lydrc:199
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 567.00M
+"with_angle" in: offgrid.lydrc:200
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 567.00M
+"output" in: offgrid.lydrc:200
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 567.00M
+"ongrid" in: offgrid.lydrc:201
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 567.00M
+"output" in: offgrid.lydrc:201
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 567.00M
+"with_angle" in: offgrid.lydrc:202
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 567.00M
+"output" in: offgrid.lydrc:202
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 567.00M
+"ongrid" in: offgrid.lydrc:203
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 567.00M
+"output" in: offgrid.lydrc:203
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 567.00M
+Writing report database: /mnt/uffs/user/u6303_christo/design/sar-adc_and_analog_circuits/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/reports/klayout_offgrid_check.xml ..
+Total elapsed: 3.350s  Memory: 565.00M

diff --git a/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/klayout_offgrid_check.total b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/klayout_offgrid_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/klayout_offgrid_check.total

@@ -0,0 +1 @@
+0
\ No newline at end of file

diff --git a/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/klayout_pin_label_purposes_overlapping_drawing_check.log b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
new file mode 100644
index 0000000..45dd79e
--- /dev/null
+++ b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/klayout_pin_label_purposes_overlapping_drawing_check.log

@@ -0,0 +1,29 @@
+Running pin_label_purposes_overlapping_drawing.rb.drc on file=/root/sar-adc_and_analog_circuits/gds/user_analog_project_wrapper.gds, topcell=user_analog_project_wrapper, output to /mnt/uffs/user/u6303_christo/design/sar-adc_and_analog_circuits/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
+  deep:true tiled:false threads:8
+--- #err|description, table for cell: user_analog_project_wrapper
+NO-Check ----        pwell:64/44/EMP   122/16/EMP    64/59/EMP    44/16/EMP     44/5/EMP
+         ----        nwell:64/20/dat    64/16/EMP     64/5/EMP
+         ----         diff:65/20/dat    65/16/EMP     65/6/EMP
+         ----          tap:65/44/dat    65/48/EMP     65/5/EMP
+         ----         poly:66/20/dat    66/16/EMP     66/5/EMP
+         ----       licon1:66/44/dat    66/58/EMP
+         ----          li1:67/20/dat    67/16/EMP     67/5/EMP
+         ----         mcon:67/44/dat    67/48/EMP
+         ----         met1:68/20/dat    68/16/EMP     68/5/EMP
+         ----          via:68/44/dat    68/58/EMP
+         ----         met2:69/20/dat    69/16/dat     69/5/EMP
+         ----         via2:69/44/dat    69/58/EMP
+         ----         met3:70/20/dat    70/16/dat     70/5/EMP
+         ----         via3:70/44/dat    70/48/EMP
+         ----         met4:71/20/dat    71/16/dat     71/5/EMP
+         ----         via4:71/44/dat    71/48/EMP
+         ----         met5:72/20/dat    72/16/dat     72/5/EMP
+         ----          pad:76/20/EMP     76/5/EMP    76/16/EMP
+         ----          pnp:82/44/dat    82/59/EMP
+         ----          npn:82/20/EMP     82/5/EMP
+         ----          rdl:74/20/EMP    74/16/EMP     74/5/EMP
+         ----     inductor:82/24/EMP    82/25/EMP
+       0 total error(s) among 0 error type(s), 33 checks, cell: user_analog_project_wrapper
+Writing report...
+VmPeak:	 1878856 kB
+VmHWM:	  270520 kB

diff --git a/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/klayout_pin_label_purposes_overlapping_drawing_check.total b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/klayout_pin_label_purposes_overlapping_drawing_check.total

@@ -0,0 +1 @@
+0
\ No newline at end of file

diff --git a/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/klayout_zeroarea_check.log b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/klayout_zeroarea_check.log
new file mode 100644
index 0000000..894bd41
--- /dev/null
+++ b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/klayout_zeroarea_check.log

@@ -0,0 +1,4 @@
+0 zero-area shapes
+writing to /mnt/uffs/user/u6303_christo/design/sar-adc_and_analog_circuits/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/user_analog_project_wrapper_no_zero_areas.gds
+VmPeak:	  572084 kB
+VmHWM:	  288332 kB

diff --git a/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/klayout_zeroarea_check.total b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/klayout_zeroarea_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/klayout_zeroarea_check.total

@@ -0,0 +1 @@
+0
\ No newline at end of file

diff --git a/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/magic_drc_check.log b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/magic_drc_check.log
new file mode 100644
index 0000000..e7a6c66
--- /dev/null
+++ b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/magic_drc_check.log

@@ -0,0 +1,27 @@
+
+Magic 8.3 revision 245 - Compiled on Tue Dec 28 15:10:32 UTC 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/checks/drc_checks/magic/magic_drc_check.tcl" from command line.
+Warning: Calma reading is not undoable!  I hope that's OK.
+Library written using GDS-II Release 6.0
+Library name: LIB
+Reading "user_analog_project_wrapper".
+CIF file read warning: CIF style sky130(vendor): units rescaled by factor of 5 / 1
+[INFO]: Loading user_analog_project_wrapper
+
+DRC style is now "drc(full)"
+Loading DRC CIF style.
+No errors found.
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+[INFO]: DRC Checking DONE (/mnt/uffs/user/u6303_christo/design/sar-adc_and_analog_circuits/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/reports/magic_drc_check.drc.report)
+[INFO]: Saving mag view with DRC errors(/mnt/uffs/user/u6303_christo/design/sar-adc_and_analog_circuits/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/user_analog_project_wrapper.magic.drc.mag)
+[INFO]: Saved

diff --git a/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/magic_drc_check.total b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/magic_drc_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/magic_drc_check.total

@@ -0,0 +1 @@
+0
\ No newline at end of file

diff --git a/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/pdks.info b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/pdks.info
new file mode 100644
index 0000000..e581b63
--- /dev/null
+++ b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/pdks.info

@@ -0,0 +1,2 @@
+Open PDKs 476f7428f7f686de51a5164c702629a9b9f2da46
+Skywater PDK c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
\ No newline at end of file

diff --git a/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/precheck.log b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/precheck.log
new file mode 100644
index 0000000..9b49c4b
--- /dev/null
+++ b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/precheck.log

@@ -0,0 +1,68 @@
+2021-12-31 14:17:54 - [INFO] - {{Project Git Info}} Repository: https://github.com/chrische-xx/mpw4.git | Branch: main | Commit: bc6ec67ad103fb72ee006b8d67ca22affd254b30
+2021-12-31 14:17:54 - [INFO] - {{INSTALLING CARAVEL}} Running `make install` in sar-adc_and_analog_circuits
+2021-12-31 14:18:03 - [INFO] - {{EXTRACTING GDS}} Extracting GDS files in: sar-adc_and_analog_circuits
+2021-12-31 14:18:07 - [INFO] - {{Project GDS Info}} user_analog_project_wrapper: 18139089c43270a702a75d1d99c7bb9478a523d6
+2021-12-31 14:18:07 - [INFO] - {{Tools Info}} KLayout: v0.27.5 | Magic: v8.3.245
+2021-12-31 14:18:07 - [INFO] - {{PDKs Info}} Open PDKs: 476f7428f7f686de51a5164c702629a9b9f2da46 | Skywater PDK: c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
+2021-12-31 14:18:07 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in 'sar-adc_and_analog_circuits/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/logs'
+2021-12-31 14:18:07 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: License Makefile Default Documentation Consistency XOR Magic DRC Klayout FEOL Klayout BEOL Klayout Offgrid Klayout Metal Minimum Clear Area Density Klayout Pin Label Purposes Overlapping Drawing Klayout ZeroArea
+2021-12-31 14:18:07 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 13: License
+2021-12-31 14:18:08 - [INFO] - An approved LICENSE (Apache-2.0) was found in sar-adc_and_analog_circuits.
+2021-12-31 14:18:08 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
+2021-12-31 14:18:09 - [INFO] - An approved LICENSE (Apache-2.0) was found in sar-adc_and_analog_circuits.
+2021-12-31 14:18:10 - [INFO] - An approved LICENSE (Apache-2.0) was found in sar-adc_and_analog_circuits.
+2021-12-31 14:18:10 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
+2021-12-31 14:18:10 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 21 non-compliant file(s) with the SPDX Standard.
+2021-12-31 14:18:10 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['sar-adc_and_analog_circuits/Makefile', 'sar-adc_and_analog_circuits/docs/environment.yml', 'sar-adc_and_analog_circuits/docs/Makefile', 'sar-adc_and_analog_circuits/docs/source/index.rst', 'sar-adc_and_analog_circuits/docs/source/conf.py', 'sar-adc_and_analog_circuits/verilog/dv/Makefile', 'sar-adc_and_analog_circuits/verilog/dv/mprj_por/mprj_por_tb.v', 'sar-adc_and_analog_circuits/verilog/dv/mprj_por/Makefile', 'sar-adc_and_analog_circuits/verilog/dv/mprj_por/mprj_por.c', 'sar-adc_and_analog_circuits/verilog/rtl/example_por.v', 'sar-adc_and_analog_circuits/verilog/rtl/uprj_analog_netlists.v', 'sar-adc_and_analog_circuits/verilog/rtl/user_analog_proj_example.v', 'sar-adc_and_analog_circuits/verilog/rtl/user_analog_project_wrapper.v', 'sar-adc_and_analog_circuits/xschem/xschemrc', 'sar-adc_and_analog_circuits/xschem/user_analog_project_wrapper.sym']
+2021-12-31 14:18:10 - [INFO] - For the full SPDX compliance report check: sar-adc_and_analog_circuits/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/logs/spdx_compliance_report.log
+2021-12-31 14:18:10 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 13: Makefile
+2021-12-31 14:18:10 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
+2021-12-31 14:18:10 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 13: Default
+2021-12-31 14:18:10 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
+2021-12-31 14:18:10 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
+2021-12-31 14:18:10 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 13: Documentation
+2021-12-31 14:18:10 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
+2021-12-31 14:18:10 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 13: Consistency
+2021-12-31 14:18:10 - [INFO] - Trying to get file https://raw.githubusercontent.com/efabless/caravel/e938b7dcf30360591aac7775251abd513bb8f72f/verilog/rtl/__user_analog_project_wrapper.v
+2021-12-31 14:18:10 - [INFO] - Got file https://raw.githubusercontent.com/efabless/caravel/e938b7dcf30360591aac7775251abd513bb8f72f/verilog/rtl/__user_analog_project_wrapper.v
+2021-12-31 14:18:10 - [INFO] - Trying to get file https://raw.githubusercontent.com/efabless/caravel/e938b7dcf30360591aac7775251abd513bb8f72f/verilog/rtl/defines.v
+2021-12-31 14:18:10 - [INFO] - Got file https://raw.githubusercontent.com/efabless/caravel/e938b7dcf30360591aac7775251abd513bb8f72f/verilog/rtl/defines.v
+2021-12-31 14:18:12 - [INFO] - HIERARCHY CHECK PASSED: Module user_analog_project_wrapper is instantiated in caravan. 
+2021-12-31 14:18:12 - [INFO] - COMPLEXITY CHECK PASSED: Netlist caravan contains at least 8 instances (68 instances). 
+2021-12-31 14:18:12 - [INFO] - MODELING CHECK PASSED: Netlist caravan is structural.
+2021-12-31 14:18:12 - [INFO] - SUBMODULE HOOKS CHECK PASSED: All module ports for user_analog_project_wrapper are correctly connected in the top level netlist caravan.
+2021-12-31 14:18:12 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravan netlist passed all consistency checks.
+2021-12-31 14:18:12 - [INFO] - PORTS CHECK PASSED: Netlist user_analog_project_wrapper ports match the golden wrapper ports
+2021-12-31 14:18:12 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_analog_project_wrapper contains at least 1 instances (3 instances). 
+2021-12-31 14:18:12 - [INFO] - MODELING CHECK PASSED: Netlist user_analog_project_wrapper is structural.
+2021-12-31 14:18:12 - [INFO] - LAYOUT CHECK PASSED: The GDS layout for user_analog_project_wrapper matches the provided structural netlist.
+2021-12-31 14:18:12 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} user_analog_project_wrapper netlist passed all consistency checks.
+2021-12-31 14:18:12 - [INFO] - {{CONSISTENCY CHECK PASSED}} The user netlist and the top netlist are valid.
+2021-12-31 14:18:12 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 13: XOR
+2021-12-31 14:18:12 - [INFO] - Trying to get file https://raw.githubusercontent.com/efabless/caravel/e938b7dcf30360591aac7775251abd513bb8f72f/gds/user_analog_project_wrapper_empty.gds.gz
+2021-12-31 14:18:12 - [INFO] - Got file https://raw.githubusercontent.com/efabless/caravel/e938b7dcf30360591aac7775251abd513bb8f72f/gds/user_analog_project_wrapper_empty.gds.gz
+2021-12-31 14:18:18 - [INFO] - {XOR CHECK UPDATE} Total XOR differences: 0, for more details view sar-adc_and_analog_circuits/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/user_analog_project_wrapper.xor.gds
+2021-12-31 14:18:18 - [INFO] - {{XOR CHECK PASSED}} The GDS file has no XOR violations.
+2021-12-31 14:18:18 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 13: Magic DRC
+2021-12-31 14:18:39 - [INFO] - 0 DRC violations
+2021-12-31 14:18:39 - [INFO] - {{MAGIC DRC CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2021-12-31 14:18:39 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 13: Klayout FEOL
+2021-12-31 14:18:45 - [INFO] - No DRC Violations found
+2021-12-31 14:18:45 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2021-12-31 14:18:45 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 13: Klayout BEOL
+2021-12-31 14:19:04 - [INFO] - No DRC Violations found
+2021-12-31 14:19:04 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2021-12-31 14:19:04 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 13: Klayout Offgrid
+2021-12-31 14:19:08 - [INFO] - No DRC Violations found
+2021-12-31 14:19:08 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2021-12-31 14:19:08 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 13: Klayout Metal Minimum Clear Area Density
+2021-12-31 14:19:10 - [INFO] - No DRC Violations found
+2021-12-31 14:19:10 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2021-12-31 14:19:10 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 13: Klayout Pin Label Purposes Overlapping Drawing
+2021-12-31 14:19:12 - [INFO] - No DRC Violations found
+2021-12-31 14:19:12 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2021-12-31 14:19:12 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 13: Klayout ZeroArea
+2021-12-31 14:19:14 - [INFO] - No DRC Violations found
+2021-12-31 14:19:14 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2021-12-31 14:19:14 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in 'sar-adc_and_analog_circuits/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/logs'
+2021-12-31 14:19:14 - [INFO] - {{SUCCESS}} All Checks Passed !!!

diff --git a/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/spdx_compliance_report.log b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/spdx_compliance_report.log
new file mode 100644
index 0000000..b642c52
--- /dev/null
+++ b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/spdx_compliance_report.log

@@ -0,0 +1,21 @@
+/root/sar-adc_and_analog_circuits/Makefile
+/root/sar-adc_and_analog_circuits/docs/environment.yml
+/root/sar-adc_and_analog_circuits/docs/Makefile
+/root/sar-adc_and_analog_circuits/docs/source/index.rst
+/root/sar-adc_and_analog_circuits/docs/source/conf.py
+/root/sar-adc_and_analog_circuits/verilog/dv/Makefile
+/root/sar-adc_and_analog_circuits/verilog/dv/mprj_por/mprj_por_tb.v
+/root/sar-adc_and_analog_circuits/verilog/dv/mprj_por/Makefile
+/root/sar-adc_and_analog_circuits/verilog/dv/mprj_por/mprj_por.c
+/root/sar-adc_and_analog_circuits/verilog/rtl/example_por.v
+/root/sar-adc_and_analog_circuits/verilog/rtl/uprj_analog_netlists.v
+/root/sar-adc_and_analog_circuits/verilog/rtl/user_analog_proj_example.v
+/root/sar-adc_and_analog_circuits/verilog/rtl/user_analog_project_wrapper.v
+/root/sar-adc_and_analog_circuits/xschem/xschemrc
+/root/sar-adc_and_analog_circuits/xschem/user_analog_project_wrapper.sym
+/root/sar-adc_and_analog_circuits/xschem/user_analog_project_wrapper.sch
+/root/sar-adc_and_analog_circuits/xschem/.spiceinit
+/root/sar-adc_and_analog_circuits/openlane/Makefile
+/root/sar-adc_and_analog_circuits/netgen/run_lvs_wrapper_verilog.sh
+/root/sar-adc_and_analog_circuits/netgen/run_lvs_por.sh
+/root/sar-adc_and_analog_circuits/netgen/run_lvs_wrapper_xschem.sh

diff --git a/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/tools.info b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/tools.info
new file mode 100644
index 0000000..d545f21
--- /dev/null
+++ b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/tools.info

@@ -0,0 +1,2 @@
+KLayout: 0.27.5
+Magic: 8.3.245
\ No newline at end of file

diff --git a/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/xor_check.log b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/xor_check.log
new file mode 100644
index 0000000..6bddccb
--- /dev/null
+++ b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/xor_check.log

@@ -0,0 +1,153 @@
+Reading file /root/sar-adc_and_analog_circuits/gds/user_analog_project_wrapper.gds for cell user_analog_project_wrapper
+dbu=0.001
+cell user_analog_project_wrapper dbu-bbox(ll;ur)=(-4000,-4000;2924000,3524000)
+cell user_analog_project_wrapper dbu-bbox(left,bottom,right,top)=(-4000,-4000,2924000,3524000)
+cell user_analog_project_wrapper dbu-size(width,height)=(2928000,3528000)
+cell user_analog_project_wrapper micron-bbox(left,bottom,right,top)=(-4.0,-4.0,2924.0,3524.0)
+cell user_analog_project_wrapper micron-size(width,height)=(2928.0,3528.0)
+Done.
+
+Magic 8.3 revision 245 - Compiled on Tue Dec 28 15:10:32 UTC 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/checks/xor_check/erase_box.tcl" from command line.
+CIF input style is now "sky130(vendor)"
+Warning: Calma reading is not undoable!  I hope that's OK.
+Library written using GDS-II Release 6.0
+Library name: LIB
+Reading "user_analog_project_wrapper".
+CIF file read warning: CIF style sky130(vendor): units rescaled by factor of 5 / 1
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:   42.88 x 3520.00  (-42.88,  0.00 ), (  0.00,  3520.00)  150937.59 
+lambda:   4288.00 x 352000.00  (-4288.00,  0.00 ), (  0.00,  352000.00)  1509376000.00
+internal:   8576 x 704000  ( -8576,  0    ), (     0,  704000)  6037504000
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:   42.50 x 3520.00  ( 2920.00,  0.00 ), ( 2962.50,  3520.00)  149600.00 
+lambda:   4250.00 x 352000.00  ( 292000.00,  0.00 ), ( 296250.00,  352000.00)  1496000000.00
+internal:   8500 x 704000  ( 584000,  0    ), ( 592500,  704000)  5984000000
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  3005.38 x 37.53   (-42.88, -37.53), ( 2962.50,  0.00 )  112791.91 
+lambda:   300538.00 x 3753.00  (-4288.00, -3753.00), ( 296250.00,  0.00 )  1127919104.00
+internal: 601076 x 7506    ( -8576, -7506 ), ( 592500,  0    )  4511676456
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  3005.38 x 37.21   (-42.88,  3520.00), ( 2962.50,  3557.21)  111830.19 
+lambda:   300538.00 x 3721.00  (-4288.00,  352000.00), ( 296250.00,  355721.00)  1118301952.00
+internal: 601076 x 7442    ( -8576,  704000), ( 592500,  711442)  4473207592
+   Generating output for cell xor_target
+
+Magic 8.3 revision 245 - Compiled on Tue Dec 28 15:10:32 UTC 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/checks/xor_check/erase_box.tcl" from command line.
+CIF input style is now "sky130(vendor)"
+Warning: Calma reading is not undoable!  I hope that's OK.
+Library written using GDS-II Release 6.0
+Library name: user_analog_project_wrapper_empty
+Reading "user_analog_project_wrapper".
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:   42.88 x 3520.00  (-42.88,  0.00 ), (  0.00,  3520.00)  150937.59 
+lambda:   4288.00 x 352000.00  (-4288.00,  0.00 ), (  0.00,  352000.00)  1509376000.00
+internal:   8576 x 704000  ( -8576,  0    ), (     0,  704000)  6037504000
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:   42.50 x 3520.00  ( 2920.00,  0.00 ), ( 2962.50,  3520.00)  149600.00 
+lambda:   4250.00 x 352000.00  ( 292000.00,  0.00 ), ( 296250.00,  352000.00)  1496000000.00
+internal:   8500 x 704000  ( 584000,  0    ), ( 592500,  704000)  5984000000
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  3005.38 x 37.53   (-42.88, -37.53), ( 2962.50,  0.00 )  112791.91 
+lambda:   300538.00 x 3753.00  (-4288.00, -3753.00), ( 296250.00,  0.00 )  1127919104.00
+internal: 601076 x 7506    ( -8576, -7506 ), ( 592500,  0    )  4511676456
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  3005.38 x 37.21   (-42.88,  3520.00), ( 2962.50,  3557.21)  111830.19 
+lambda:   300538.00 x 3721.00  (-4288.00,  352000.00), ( 296250.00,  355721.00)  1118301952.00
+internal: 601076 x 7442    ( -8576,  704000), ( 592500,  711442)  4473207592
+   Generating output for cell xor_target
+Reading /mnt/uffs/user/u6303_christo/design/sar-adc_and_analog_circuits/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/user_analog_project_wrapper_erased.gds ..
+Reading /mnt/uffs/user/u6303_christo/design/sar-adc_and_analog_circuits/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/user_analog_project_wrapper_empty_erased.gds ..
+--- Running XOR for 69/20 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 494 (flat)  494 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 494 (flat)  494 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+--- Running XOR for 70/20 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 184 (flat)  184 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 184 (flat)  184 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+--- Running XOR for 72/20 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 6 (flat)  6 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 6 (flat)  6 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+--- Running XOR for 81/14 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 1 (flat)  1 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 1 (flat)  1 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 523.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 523.00M
+Writing layout file: /mnt/uffs/user/u6303_christo/design/sar-adc_and_analog_circuits/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/user_analog_project_wrapper.xor.gds ..
+Total elapsed: 0.120s  Memory: 523.00M

diff --git a/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/xor_check.total b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/xor_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/logs/xor_check.total

@@ -0,0 +1 @@
+0
\ No newline at end of file

diff --git a/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/__user_analog_project_wrapper.v b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/__user_analog_project_wrapper.v
new file mode 100644
index 0000000..6360f0b
--- /dev/null
+++ b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/__user_analog_project_wrapper.v

@@ -0,0 +1,124 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ *-------------------------------------------------------------
+ *
+ * user_analog_project_wrapper
+ *
+ * This wrapper enumerates all of the pins available to the
+ * user for the user analog project.
+ *
+ *-------------------------------------------------------------
+ */
+
+module user_analog_project_wrapper (
+`ifdef USE_POWER_PINS
+    inout vdda1,	// User area 1 3.3V supply
+    inout vdda2,	// User area 2 3.3V supply
+    inout vssa1,	// User area 1 analog ground
+    inout vssa2,	// User area 2 analog ground
+    inout vccd1,	// User area 1 1.8V supply
+    inout vccd2,	// User area 2 1.8v supply
+    inout vssd1,	// User area 1 digital ground
+    inout vssd2,	// User area 2 digital ground
+`endif
+
+    // Wishbone Slave ports (WB MI A)
+    input wb_clk_i,
+    input wb_rst_i,
+    input wbs_stb_i,
+    input wbs_cyc_i,
+    input wbs_we_i,
+    input [3:0] wbs_sel_i,
+    input [31:0] wbs_dat_i,
+    input [31:0] wbs_adr_i,
+    output wbs_ack_o,
+    output [31:0] wbs_dat_o,
+
+    // Logic Analyzer Signals
+    input  [127:0] la_data_in,
+    output [127:0] la_data_out,
+    input  [127:0] la_oenb,
+
+    /* GPIOs.  There are 27 GPIOs, on either side of the analog.
+     * These have the following mapping to the GPIO padframe pins
+     * and memory-mapped registers, since the numbering remains the
+     * same as caravel but skips over the analog I/O:
+     *
+     * io_in/out/oeb/in_3v3 [26:14]  <--->  mprj_io[37:25]
+     * io_in/out/oeb/in_3v3 [13:0]   <--->  mprj_io[13:0]	
+     *
+     * When the GPIOs are configured by the Management SoC for
+     * user use, they have three basic bidirectional controls:
+     * in, out, and oeb (output enable, sense inverted).  For
+     * analog projects, a 3.3V copy of the signal input is
+     * available.  out and oeb must be 1.8V signals.
+     */
+
+    input  [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in,
+    input  [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3,
+    output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out,
+    output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb,
+
+    /* Analog (direct connection to GPIO pad---not for high voltage or
+     * high frequency use).  The management SoC must turn off both
+     * input and output buffers on these GPIOs to allow analog access.
+     * These signals may drive a voltage up to the value of VDDIO
+     * (3.3V typical, 5.5V maximum).
+     * 
+     * Note that analog I/O is not available on the 7 lowest-numbered
+     * GPIO pads, and so the analog_io indexing is offset from the
+     * GPIO indexing by 7, as follows:
+     *
+     * gpio_analog/noesd [17:7]  <--->  mprj_io[35:25]
+     * gpio_analog/noesd [6:0]   <--->  mprj_io[13:7]	
+     *
+     */
+    
+    inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog,
+    inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd,
+
+    /* Analog signals, direct through to pad.  These have no ESD at all,
+     * so ESD protection is the responsibility of the designer.
+     *
+     * user_analog[10:0]  <--->  mprj_io[24:14]
+     *
+     */
+    inout [`ANALOG_PADS-1:0] io_analog,
+
+    /* Additional power supply ESD clamps, one per analog pad.  The
+     * high side should be connected to a 3.3-5.5V power supply.
+     * The low side should be connected to ground.
+     *
+     * clamp_high[2:0]   <--->  mprj_io[20:18]
+     * clamp_low[2:0]    <--->  mprj_io[20:18]
+     *
+     */
+    inout [2:0] io_clamp_high,
+    inout [2:0] io_clamp_low,
+
+    // Independent clock (on independent integer divider)
+    input   user_clock2,
+
+    // User maskable interrupt signals
+    output [2:0] user_irq
+);
+
+// Dummy assignment so that we can take it through the openlane flow
+assign io_out = io_in;
+
+endmodule	// user_analog_project_wrapper

diff --git a/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/defines.v b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/defines.v
new file mode 100644
index 0000000..6213b6c
--- /dev/null
+++ b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/defines.v

@@ -0,0 +1,66 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`ifndef __GLOBAL_DEFINE_H
+// Global parameters
+`define __GLOBAL_DEFINE_H
+
+`define MPRJ_IO_PADS_1 19	/* number of user GPIO pads on user1 side */
+`define MPRJ_IO_PADS_2 19	/* number of user GPIO pads on user2 side */
+`define MPRJ_IO_PADS (`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2)
+
+`define MPRJ_PWR_PADS_1 2	/* vdda1, vccd1 enable/disable control */
+`define MPRJ_PWR_PADS_2 2	/* vdda2, vccd2 enable/disable control */
+`define MPRJ_PWR_PADS (`MPRJ_PWR_PADS_1 + `MPRJ_PWR_PADS_2)
+
+// Analog pads are only used by the "caravan" module and associated
+// modules such as user_analog_project_wrapper and chip_io_alt.
+
+`define ANALOG_PADS_1 5
+`define ANALOG_PADS_2 6
+
+`define ANALOG_PADS (`ANALOG_PADS_1 + `ANALOG_PADS_2)
+
+// Size of soc_mem_synth
+
+// Type and size of soc_mem
+// `define USE_OPENRAM
+`define USE_CUSTOM_DFFRAM
+// don't change the following without double checking addr widths
+`define MEM_WORDS 256
+
+// Number of columns in the custom memory; takes one of three values:
+// 1 column : 1 KB, 2 column: 2 KB, 4 column: 4KB
+`define DFFRAM_WSIZE 4
+`define DFFRAM_USE_LATCH 0
+
+// not really parameterized but just to easily keep track of the number
+// of ram_block across different modules
+`define RAM_BLOCKS 1
+
+// Clock divisor default value
+`define CLK_DIV 3'b010
+
+// GPIO control default mode and enable for most I/Os
+// Most I/Os set to be user input pins on startup.
+// NOTE:  To be modified, with GPIOs 5 to 35 being set from a build-time-
+// programmable block.
+`define MGMT_INIT 1'b0
+`define OENB_INIT 1'b0
+`define DM_INIT 3'b001
+
+`endif // __GLOBAL_DEFINE_H

diff --git a/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/reports/klayout_beol_check.xml b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/reports/klayout_beol_check.xml
new file mode 100644
index 0000000..ec9fc1d
--- /dev/null
+++ b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/reports/klayout_beol_check.xml

@@ -0,0 +1,447 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+  <category>
+   <name>li.1</name>
+   <description>li.1 : min. li width : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.3</name>
+   <description>li.3 : min. li spacing : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.5</name>
+   <description>li.5 : min. li enclosure of licon of 2 adjacent edges : 0.08um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.6</name>
+   <description>li.6 : min. li area : 0.0561um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.1</name>
+   <description>ct.1: non-ring mcon should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.1_a</name>
+   <description>ct.1_a : minimum width of mcon : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.1_b</name>
+   <description>ct.1_b : maximum length of mcon : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.2</name>
+   <description>ct.2 : min. mcon spacing : 0.19um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.4</name>
+   <description>ct.4 : mcon should covered by li</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.1</name>
+   <description>m1.1 : min. m1 width : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.2</name>
+   <description>m1.2 : min. m1 spacing : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.3ab</name>
+   <description>m1.3ab : min. 3um.m1 spacing m1 : 0.28um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>791_m1.4</name>
+   <description>791_m1.4 : min. m1 enclosure of mcon : 0.03um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.4</name>
+   <description>m1.4 : mcon periphery must be enclosed by m1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.4a</name>
+   <description>m1.4a : min. m1 enclosure of mcon for specific cells : 0.005um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.4a_a</name>
+   <description>m1.4a_a : mcon periph must be enclosed by met1 for specific cells</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.6</name>
+   <description>m1.6 : min. m1 area : 0.083um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.7</name>
+   <description>m1.7 : min. m1 with holes area : 0.14um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.5</name>
+   <description>m1.5 : min. m1 enclosure of mcon of 2 adjacent edges : 0.06um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.1a</name>
+   <description>via.1a : via outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.1a_a</name>
+   <description>via.1a_a : min. width of via outside of moduleCut : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.1a_b</name>
+   <description>via.1a_b : maximum length of via : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.2</name>
+   <description>via.2 : min. via spacing : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.4a</name>
+   <description>via.4a : min. m1 enclosure of 0.15um via : 0.055um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.4a_a</name>
+   <description>via.4a_a : 0.15um via must be enclosed by met1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.5a</name>
+   <description>via.5a : min. m1 enclosure of 0.15um via of 2 adjacent edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.1</name>
+   <description>m2.1 : min. m2 width : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.2</name>
+   <description>m2.2 : min. m2 spacing : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.3ab</name>
+   <description>m2.3ab : min. 3um.m2 spacing m2 : 0.28um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.6</name>
+   <description>m2.6 : min. m2 area : 0.0676um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.7</name>
+   <description>m2.7 : min. m2 holes area : 0.14um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.4</name>
+   <description>m2.4 : min. m2 enclosure of via : 0.055um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.4_a</name>
+   <description>m2.4_a : via in periphery must be enclosed by met2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.5</name>
+   <description>m2.5 : min. m2 enclosure of via of 2 adjacent edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.1a</name>
+   <description>via2.1a : via2 outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.1a_a</name>
+   <description>via2.1a_a : min. width of via2 outside of moduleCut : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.1a_b</name>
+   <description>via2.1a_b : maximum length of via2 : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.2</name>
+   <description>via2.2 : min. via2 spacing : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.4</name>
+   <description>via2.4 : min. m2 enclosure of via2 : 0.04um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.4_a</name>
+   <description>via2.4_a : via must be enclosed by met2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.5</name>
+   <description>via2.5 : min. m3 enclosure of via2 of 2 adjacent edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.1</name>
+   <description>m3.1 : min. m3 width : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.2</name>
+   <description>m3.2 : min. m3 spacing : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.3cd</name>
+   <description>m3.3cd : min. 3um.m3 spacing m3 : 0.4um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.4</name>
+   <description>m3.4 : min. m3 enclosure of via2 : 0.065um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.4_a</name>
+   <description>m3.4_a : via2 must be enclosed by met3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.1</name>
+   <description>via3.1 : via3 outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.1_a</name>
+   <description>via3.1_a : min. width of via3 outside of moduleCut : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.1_b</name>
+   <description>via3.1_b : maximum length of via3 : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.2</name>
+   <description>via3.2 : min. via3 spacing : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.4</name>
+   <description>via3.4 : min. m3 enclosure of via3 : 0.06um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.4_a</name>
+   <description>via3.4_a : non-ring via3 must be enclosed by met3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.5</name>
+   <description>via3.5 : min. m3 enclosure of via3 of 2 adjacent edges : 0.09um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.1</name>
+   <description>m4.1 : min. m4 width : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.2</name>
+   <description>m4.2 : min. m4 spacing : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.4a</name>
+   <description>m4.4a : min. m4 area : 0.240um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.5ab</name>
+   <description>m4.5ab : min. 3um.m4 spacing m4 : 0.4um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.3</name>
+   <description>m4.3 : min. m4 enclosure of via3 : 0.065um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.3_a</name>
+   <description>m4.3_a : via3 must be enclosed by met4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.1</name>
+   <description>via4.1 : via4 outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.1_a</name>
+   <description>via4.1_a : min. width of via4 outside of moduleCut : 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.1_b</name>
+   <description>via4.1_b : maximum length of via4 : 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.2</name>
+   <description>via4.2 : min. via4 spacing : 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.4</name>
+   <description>via4.4 : min. m4 enclosure of via4 : 0.19um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.4_a</name>
+   <description>via4.4_a : m4 must enclose all via4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.1</name>
+   <description>m5.1 : min. m5 width : 1.6um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.2</name>
+   <description>m5.2 : min. m5 spacing : 1.6um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.3</name>
+   <description>m5.3 : min. m5 enclosure of via4 : 0.31um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.3_a</name>
+   <description>m5.3_a : via must be enclosed by m5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.4</name>
+   <description>m5.4 : min. m5 area : 4.0um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pad.2</name>
+   <description>pad.2 : min. pad spacing : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_analog_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>

diff --git a/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/reports/klayout_feol_check.xml b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/reports/klayout_feol_check.xml
new file mode 100644
index 0000000..81ff212
--- /dev/null
+++ b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/reports/klayout_feol_check.xml

@@ -0,0 +1,333 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+  <category>
+   <name>dnwell.2</name>
+   <description>dnwell.2 : min. dnwell width : 3.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell.1</name>
+   <description>nwell.1 : min. nwell width : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell.2a</name>
+   <description>nwell.2a : min. nwell spacing (merged if less) : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp.1</name>
+   <description>hvtp.1 : min. hvtp width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp.2</name>
+   <description>hvtp.2 : min. hvtp spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr.1</name>
+   <description>hvtr.1 : min. hvtr width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr.2</name>
+   <description>hvtr.2 : min. hvtr spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr.2_a</name>
+   <description>hvtr.2_a : hvtr must not overlap hvtp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn.1a</name>
+   <description>lvtn.1a : min. lvtn width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn.2</name>
+   <description>lvtn.2 : min. lvtn spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm.1</name>
+   <description>ncm.1 : min. ncm width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm.2a</name>
+   <description>ncm.2a : min. ncm spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1</name>
+   <description>difftap.1 : min. diff width across areaid:ce : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1_a</name>
+   <description>difftap.1_a : min. diff width in periphery : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1_b</name>
+   <description>difftap.1_b : min. tap width across areaid:ce : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1_c</name>
+   <description>difftap.1_c : min. tap width in periphery : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.3</name>
+   <description>difftap.3 : min. difftap spacing : 0.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm.1</name>
+   <description>tunm.1 : min. tunm width : 0.41um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm.2</name>
+   <description>tunm.2 : min. tunm spacing : 0.5um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly.1a</name>
+   <description>poly.1a : min. poly width : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly.2</name>
+   <description>poly.2 : min. poly spacing : 0.21um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm.1a</name>
+   <description>rpm.1a : min. rpm width : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm.2</name>
+   <description>rpm.2 : min. rpm spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>urpm.1a</name>
+   <description>urpm.1a : min. rpm width : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>urpm.2</name>
+   <description>urpm.2 : min. rpm spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc.1</name>
+   <description>npc.1 : min. npc width : 0.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc.2</name>
+   <description>npc.2 : min. npc spacing, should be mnually merge if less : 0.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.1</name>
+   <description>licon.1 : licon should be rectangle</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.1_a/b</name>
+   <description>licon.1_a/b : minimum/maximum width of licon : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.13</name>
+   <description>licon.13 : min. difftap licon spacing to npc : 0.09um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.13_a</name>
+   <description>licon.13_a : licon of diffTap in periphery must not overlap npc</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.17</name>
+   <description>licon.17 : Licons may not overlap both poly and (diff or tap)</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.1</name>
+   <description>capm.1 : min. capm width : 1.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.2a</name>
+   <description>capm.2a : min. capm spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.2b</name>
+   <description>capm.2b : min. capm spacing : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.2b_a</name>
+   <description>capm.2b_a : min. spacing of m3_bot_plate : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.3</name>
+   <description>capm.3 : min. capm and m3 enclosure of m3 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.3_a</name>
+   <description>capm.3_a : min. m3 enclosure of capm : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.4</name>
+   <description>capm.4 : min. capm enclosure of via3 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.5</name>
+   <description>capm.5 : min. capm spacing to via3 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.1</name>
+   <description>cap2m.1 : min. cap2m width : 1.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.2a</name>
+   <description>cap2m.2a : min. cap2m spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.2b</name>
+   <description>cap2m.2b : min. cap2m spacing : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.2b_a</name>
+   <description>cap2m.2b_a : min. spacing of m4_bot_plate : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.3</name>
+   <description>cap2m.3 : min. m4 enclosure of cap2m : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.3_a</name>
+   <description>cap2m.3_a : min. m4 enclosure of cap2m : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.4</name>
+   <description>cap2m.4 : min. cap2m enclosure of via4 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.5</name>
+   <description>cap2m.5 : min. cap2m spacing to via4 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi.1</name>
+   <description>hvi.1 : min. hvi width : 0.6um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi.2a</name>
+   <description>hvi.2a : min. hvi spacing : 0.7um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm.1</name>
+   <description>hvntm.1 : min. hvntm width : 0.7um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm.2</name>
+   <description>hvntm.2 : min. hvntm spacing : 0.7um</description>
+   <categories>
+   </categories>
+  </category>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_analog_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>

diff --git a/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/reports/klayout_met_min_ca_density_check.xml b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/reports/klayout_met_min_ca_density_check.xml
new file mode 100644
index 0000000..ebb8e2a
--- /dev/null
+++ b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/reports/klayout_met_min_ca_density_check.xml

@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>Density Checks</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/drc_checks/klayout/met_min_ca_density.lydrc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_analog_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>

diff --git a/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/reports/klayout_offgrid_check.xml b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/reports/klayout_offgrid_check.xml
new file mode 100644
index 0000000..1a44560
--- /dev/null
+++ b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/reports/klayout_offgrid_check.xml

@@ -0,0 +1,483 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/drc_checks/klayout/offgrid.lydrc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+  <category>
+   <name>dnwell_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on dnwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>dnwell_angle</name>
+   <description>x.3a : non 45 degree angle dnwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on nwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell_angle</name>
+   <description>x.3a : non 45 degree angle nwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwbm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on pwbm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwbm_angle</name>
+   <description>x.3a : non 45 degree angle pwbm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwde_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on pwde</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwde_angle</name>
+   <description>x.3a : non 45 degree angle pwde</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on hvtp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp_angle</name>
+   <description>x.3a : non 45 degree angle hvtp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on hvtr</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr_angle</name>
+   <description>x.3a : non 45 degree angle hvtr</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on lvtn</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn_angle</name>
+   <description>x.3a : non 45 degree angle lvtn</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on ncm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm_angle</name>
+   <description>x.3a : non 45 degree angle ncm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>diff_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on diff</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tap_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on tap</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>diff_angle</name>
+   <description>x.2 : non 90 degree angle diff</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>diff_angle</name>
+   <description>x.2c : non 45 degree angle diff</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tap_angle</name>
+   <description>x.2 : non 90 degree angle tap</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tap_angle</name>
+   <description>x.2c : non 45 degree angle tap</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on tunm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm_angle</name>
+   <description>x.3a : non 45 degree angle tunm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on poly</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly_angle</name>
+   <description>x.2 : non 90 degree angle poly</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on rpm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm_angle</name>
+   <description>x.3a : non 45 degree angle rpm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on npc</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc_angle</name>
+   <description>x.3a : non 45 degree angle npc</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsdm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on nsdm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsdm_angle</name>
+   <description>x.3a : non 45 degree angle nsdm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>psdm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on psdm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>psdm_angle</name>
+   <description>x.3a : non 45 degree angle psdm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on licon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon_angle</name>
+   <description>x.2 : non 90 degree angle licon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on li</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li_angle</name>
+   <description>x.3a : non 45 degree angle li</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on mcon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct_angle</name>
+   <description>x.2 : non 90 degree angle mcon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vpp_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on vpp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vpp_angle</name>
+   <description>x.3a : non 45 degree angle vpp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1_angle</name>
+   <description>x.3a : non 45 degree angle m1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on via</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via_angle</name>
+   <description>x.2 : non 90 degree angle via</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2_angle</name>
+   <description>x.3a : non 45 degree angle m2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on via2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2_angle</name>
+   <description>x.2 : non 90 degree angle via2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3_angle</name>
+   <description>x.3a : non 45 degree angle m3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on via3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3_angle</name>
+   <description>x.2 : non 90 degree angle via3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on nsm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm_angle</name>
+   <description>x.3a : non 45 degree angle nsm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4_angle</name>
+   <description>x.3a : non 45 degree angle m4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on via4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4_angle</name>
+   <description>x.2 : non 90 degree angle via4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5_angle</name>
+   <description>x.3a : non 45 degree angle m5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pad_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on pad</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pad_angle</name>
+   <description>x.3a : non 45 degree angle pad</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mf_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on mf</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mf_angle</name>
+   <description>x.2 : non 90 degree angle mf</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on hvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi_angle</name>
+   <description>x.3a : non 45 degree angle hvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on hvntm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm_angle</name>
+   <description>x.3a : non 45 degree angle hvntm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vhvi_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on vhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vhvi_angle</name>
+   <description>x.3a : non 45 degree angle vhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>uhvi_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on uhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>uhvi_angle</name>
+   <description>x.3a : non 45 degree angle uhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwell_rs_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on pwell_rs</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwell_rs_angle</name>
+   <description>x.3a : non 45 degree angle pwell_rs</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>areaid_re_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on areaid.re</description>
+   <categories>
+   </categories>
+  </category>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_analog_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>

diff --git a/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
new file mode 100644
index 0000000..ee65cfc
--- /dev/null
+++ b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml

@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>pin_label_purposes_overlapping_drawing.rb.drc, input=/root/sar-adc_and_analog_circuits/gds/user_analog_project_wrapper.gds, topcell=user_analog_project_wrapper</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/drc_checks/klayout/pin_label_purposes_overlapping_drawing.rb.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_analog_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>

diff --git a/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/reports/klayout_zeroarea_check.xml b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/reports/klayout_zeroarea_check.xml
new file mode 100644
index 0000000..4c75eb5
--- /dev/null
+++ b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/reports/klayout_zeroarea_check.xml

@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>zero area check</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/drc_checks/klayout/zeroarea.rb.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_analog_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>

diff --git a/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/reports/magic_drc_check.drc.report b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/reports/magic_drc_check.drc.report
new file mode 100644
index 0000000..829b9d5
--- /dev/null
+++ b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/reports/magic_drc_check.drc.report

@@ -0,0 +1,5 @@
+user_analog_project_wrapper
+----------------------------------------
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+

diff --git a/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/reports/magic_drc_check.rdb b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/reports/magic_drc_check.rdb
new file mode 100644
index 0000000..8a882f3
--- /dev/null
+++ b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/reports/magic_drc_check.rdb

@@ -0,0 +1,2 @@
+$user_analog_project_wrapper
+ 100

diff --git a/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/reports/magic_drc_check.tcl b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/reports/magic_drc_check.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/reports/magic_drc_check.tcl


diff --git a/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/reports/magic_drc_check.tr b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/reports/magic_drc_check.tr
new file mode 100644
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--- /dev/null
+++ b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/reports/magic_drc_check.tr


diff --git a/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/reports/magic_drc_check.xml b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/reports/magic_drc_check.xml
new file mode 100644
index 0000000..7161d7c
--- /dev/null
+++ b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/reports/magic_drc_check.xml

@@ -0,0 +1,10 @@
+<?xml version="1.0" ?>
+<report-database>
+    <categories/>
+    <cells>
+        <cell>
+            <name>user_analog_project_wrapper</name>
+        </cell>
+    </cells>
+    <items/>
+</report-database>

diff --git a/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/user_analog_project_wrapper.magic.drc.mag b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/user_analog_project_wrapper.magic.drc.mag
new file mode 100644
index 0000000..93603f9
--- /dev/null
+++ b/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/user_analog_project_wrapper.magic.drc.mag

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commit	f3cc5b019c8de45c694e36e595f7c53aef13b960	[log] [tgz]
author	Jeff DiCorpo <jeffdi@efabless.com>	Sun Jan 09 11:59:47 2022 -0800
committer	Jeff DiCorpo <jeffdi@efabless.com>	Sun Jan 09 11:59:47 2022 -0800
tree	73409fef5269a49c929ee322b0a83bb3ca1c48b6
parent	bc6ec67ad103fb72ee006b8d67ca22affd254b30 [diff]