jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/logs/precheck.log

2021-12-31 14:17:54 - [INFO] - {{Project Git Info}} Repository: https://github.com/chrische-xx/mpw4.git | Branch: main | Commit: bc6ec67ad103fb72ee006b8d67ca22affd254b30
2021-12-31 14:17:54 - [INFO] - {{INSTALLING CARAVEL}} Running `make install` in sar-adc_and_analog_circuits
2021-12-31 14:18:03 - [INFO] - {{EXTRACTING GDS}} Extracting GDS files in: sar-adc_and_analog_circuits
2021-12-31 14:18:07 - [INFO] - {{Project GDS Info}} user_analog_project_wrapper: 18139089c43270a702a75d1d99c7bb9478a523d6
2021-12-31 14:18:07 - [INFO] - {{Tools Info}} KLayout: v0.27.5 | Magic: v8.3.245
2021-12-31 14:18:07 - [INFO] - {{PDKs Info}} Open PDKs: 476f7428f7f686de51a5164c702629a9b9f2da46 | Skywater PDK: c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
2021-12-31 14:18:07 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in 'sar-adc_and_analog_circuits/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/logs'
2021-12-31 14:18:07 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: License Makefile Default Documentation Consistency XOR Magic DRC Klayout FEOL Klayout BEOL Klayout Offgrid Klayout Metal Minimum Clear Area Density Klayout Pin Label Purposes Overlapping Drawing Klayout ZeroArea
2021-12-31 14:18:07 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 13: License
2021-12-31 14:18:08 - [INFO] - An approved LICENSE (Apache-2.0) was found in sar-adc_and_analog_circuits.
2021-12-31 14:18:08 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
2021-12-31 14:18:09 - [INFO] - An approved LICENSE (Apache-2.0) was found in sar-adc_and_analog_circuits.
2021-12-31 14:18:10 - [INFO] - An approved LICENSE (Apache-2.0) was found in sar-adc_and_analog_circuits.
2021-12-31 14:18:10 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
2021-12-31 14:18:10 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 21 non-compliant file(s) with the SPDX Standard.
2021-12-31 14:18:10 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['sar-adc_and_analog_circuits/Makefile', 'sar-adc_and_analog_circuits/docs/environment.yml', 'sar-adc_and_analog_circuits/docs/Makefile', 'sar-adc_and_analog_circuits/docs/source/index.rst', 'sar-adc_and_analog_circuits/docs/source/conf.py', 'sar-adc_and_analog_circuits/verilog/dv/Makefile', 'sar-adc_and_analog_circuits/verilog/dv/mprj_por/mprj_por_tb.v', 'sar-adc_and_analog_circuits/verilog/dv/mprj_por/Makefile', 'sar-adc_and_analog_circuits/verilog/dv/mprj_por/mprj_por.c', 'sar-adc_and_analog_circuits/verilog/rtl/example_por.v', 'sar-adc_and_analog_circuits/verilog/rtl/uprj_analog_netlists.v', 'sar-adc_and_analog_circuits/verilog/rtl/user_analog_proj_example.v', 'sar-adc_and_analog_circuits/verilog/rtl/user_analog_project_wrapper.v', 'sar-adc_and_analog_circuits/xschem/xschemrc', 'sar-adc_and_analog_circuits/xschem/user_analog_project_wrapper.sym']
2021-12-31 14:18:10 - [INFO] - For the full SPDX compliance report check: sar-adc_and_analog_circuits/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/logs/spdx_compliance_report.log
2021-12-31 14:18:10 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 13: Makefile
2021-12-31 14:18:10 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
2021-12-31 14:18:10 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 13: Default
2021-12-31 14:18:10 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
2021-12-31 14:18:10 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
2021-12-31 14:18:10 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 13: Documentation
2021-12-31 14:18:10 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
2021-12-31 14:18:10 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 13: Consistency
2021-12-31 14:18:10 - [INFO] - Trying to get file https://raw.githubusercontent.com/efabless/caravel/e938b7dcf30360591aac7775251abd513bb8f72f/verilog/rtl/__user_analog_project_wrapper.v
2021-12-31 14:18:10 - [INFO] - Got file https://raw.githubusercontent.com/efabless/caravel/e938b7dcf30360591aac7775251abd513bb8f72f/verilog/rtl/__user_analog_project_wrapper.v
2021-12-31 14:18:10 - [INFO] - Trying to get file https://raw.githubusercontent.com/efabless/caravel/e938b7dcf30360591aac7775251abd513bb8f72f/verilog/rtl/defines.v
2021-12-31 14:18:10 - [INFO] - Got file https://raw.githubusercontent.com/efabless/caravel/e938b7dcf30360591aac7775251abd513bb8f72f/verilog/rtl/defines.v
2021-12-31 14:18:12 - [INFO] - HIERARCHY CHECK PASSED: Module user_analog_project_wrapper is instantiated in caravan. 
2021-12-31 14:18:12 - [INFO] - COMPLEXITY CHECK PASSED: Netlist caravan contains at least 8 instances (68 instances). 
2021-12-31 14:18:12 - [INFO] - MODELING CHECK PASSED: Netlist caravan is structural.
2021-12-31 14:18:12 - [INFO] - SUBMODULE HOOKS CHECK PASSED: All module ports for user_analog_project_wrapper are correctly connected in the top level netlist caravan.
2021-12-31 14:18:12 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravan netlist passed all consistency checks.
2021-12-31 14:18:12 - [INFO] - PORTS CHECK PASSED: Netlist user_analog_project_wrapper ports match the golden wrapper ports
2021-12-31 14:18:12 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_analog_project_wrapper contains at least 1 instances (3 instances). 
2021-12-31 14:18:12 - [INFO] - MODELING CHECK PASSED: Netlist user_analog_project_wrapper is structural.
2021-12-31 14:18:12 - [INFO] - LAYOUT CHECK PASSED: The GDS layout for user_analog_project_wrapper matches the provided structural netlist.
2021-12-31 14:18:12 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} user_analog_project_wrapper netlist passed all consistency checks.
2021-12-31 14:18:12 - [INFO] - {{CONSISTENCY CHECK PASSED}} The user netlist and the top netlist are valid.
2021-12-31 14:18:12 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 13: XOR
2021-12-31 14:18:12 - [INFO] - Trying to get file https://raw.githubusercontent.com/efabless/caravel/e938b7dcf30360591aac7775251abd513bb8f72f/gds/user_analog_project_wrapper_empty.gds.gz
2021-12-31 14:18:12 - [INFO] - Got file https://raw.githubusercontent.com/efabless/caravel/e938b7dcf30360591aac7775251abd513bb8f72f/gds/user_analog_project_wrapper_empty.gds.gz
2021-12-31 14:18:18 - [INFO] - {XOR CHECK UPDATE} Total XOR differences: 0, for more details view sar-adc_and_analog_circuits/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/outputs/user_analog_project_wrapper.xor.gds
2021-12-31 14:18:18 - [INFO] - {{XOR CHECK PASSED}} The GDS file has no XOR violations.
2021-12-31 14:18:18 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 13: Magic DRC
2021-12-31 14:18:39 - [INFO] - 0 DRC violations
2021-12-31 14:18:39 - [INFO] - {{MAGIC DRC CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2021-12-31 14:18:39 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 13: Klayout FEOL
2021-12-31 14:18:45 - [INFO] - No DRC Violations found
2021-12-31 14:18:45 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2021-12-31 14:18:45 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 13: Klayout BEOL
2021-12-31 14:19:04 - [INFO] - No DRC Violations found
2021-12-31 14:19:04 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2021-12-31 14:19:04 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 13: Klayout Offgrid
2021-12-31 14:19:08 - [INFO] - No DRC Violations found
2021-12-31 14:19:08 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2021-12-31 14:19:08 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 13: Klayout Metal Minimum Clear Area Density
2021-12-31 14:19:10 - [INFO] - No DRC Violations found
2021-12-31 14:19:10 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2021-12-31 14:19:10 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 13: Klayout Pin Label Purposes Overlapping Drawing
2021-12-31 14:19:12 - [INFO] - No DRC Violations found
2021-12-31 14:19:12 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2021-12-31 14:19:12 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 13: Klayout ZeroArea
2021-12-31 14:19:14 - [INFO] - No DRC Violations found
2021-12-31 14:19:14 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2021-12-31 14:19:14 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in 'sar-adc_and_analog_circuits/jobs/mpw_precheck/6981fc23-55af-43ea-8554-fd768b2317fe/logs'
2021-12-31 14:19:14 - [INFO] - {{SUCCESS}} All Checks Passed !!!