| /root/sar-adc_and_analog_circuits/Makefile |
| /root/sar-adc_and_analog_circuits/docs/environment.yml |
| /root/sar-adc_and_analog_circuits/docs/Makefile |
| /root/sar-adc_and_analog_circuits/docs/source/index.rst |
| /root/sar-adc_and_analog_circuits/docs/source/conf.py |
| /root/sar-adc_and_analog_circuits/verilog/dv/Makefile |
| /root/sar-adc_and_analog_circuits/verilog/dv/mprj_por/mprj_por_tb.v |
| /root/sar-adc_and_analog_circuits/verilog/dv/mprj_por/Makefile |
| /root/sar-adc_and_analog_circuits/verilog/dv/mprj_por/mprj_por.c |
| /root/sar-adc_and_analog_circuits/verilog/rtl/example_por.v |
| /root/sar-adc_and_analog_circuits/verilog/rtl/uprj_analog_netlists.v |
| /root/sar-adc_and_analog_circuits/verilog/rtl/user_analog_proj_example.v |
| /root/sar-adc_and_analog_circuits/verilog/rtl/user_analog_project_wrapper.v |
| /root/sar-adc_and_analog_circuits/xschem/xschemrc |
| /root/sar-adc_and_analog_circuits/xschem/user_analog_project_wrapper.sym |
| /root/sar-adc_and_analog_circuits/xschem/user_analog_project_wrapper.sch |
| /root/sar-adc_and_analog_circuits/xschem/.spiceinit |
| /root/sar-adc_and_analog_circuits/openlane/Makefile |
| /root/sar-adc_and_analog_circuits/netgen/run_lvs_wrapper_verilog.sh |
| /root/sar-adc_and_analog_circuits/netgen/run_lvs_por.sh |
| /root/sar-adc_and_analog_circuits/netgen/run_lvs_wrapper_xschem.sh |