merged README.md image
diff --git a/xschem/analog_wrapper_tb.sch b/xschem/analog_wrapper_tb.sch
deleted file mode 100644
index ee08803..0000000
--- a/xschem/analog_wrapper_tb.sch
+++ /dev/null
@@ -1,101 +0,0 @@
-v {xschem version=2.9.9 file_version=1.2 }
-G {}
-K {}
-V {}
-S {}
-E {}
-N 300 -290 510 -290 { lab=#net1}
-N 590 -290 590 -250 { lab=#net1}
-N 300 -250 430 -250 { lab=GND}
-N 510 -250 510 -150 { lab=GND}
-N 510 -150 780 -150 { lab=GND}
-N 780 -190 780 -150 { lab=GND}
-N 690 -190 690 -150 { lab=GND}
-N 590 -190 590 -150 { lab=GND}
-N 300 -210 400 -210 { lab=#net2}
-N 480 -270 480 -210 { lab=#net2}
-N 480 -270 690 -270 { lab=#net2}
-N 690 -270 690 -250 { lab=#net2}
-N 300 10 450 10 { lab=#net3}
-N 850 -270 850 0 { lab=io_analog[4]}
-N 780 -270 850 -270 { lab=io_analog[4]}
-N 780 -270 780 -250 { lab=io_analog[4]}
-N 300 30 470 30 { lab=io_clamp_high[2:0]}
-N 300 50 410 50 { lab=GND}
-N 550 30 630 30 { lab=io_clamp_high[2:0]}
-N 630 30 630 90 { lab=io_clamp_high[2:0]}
-N 500 160 810 160 { lab=GND}
-N 810 -150 810 160 { lab=GND}
-N 780 -150 810 -150 { lab=GND}
-N 530 10 660 10 { lab=io_analog[10:0]}
-N 510 -290 590 -290 { lab=#net1}
-N 430 -250 510 -250 { lab=GND}
-N 400 -210 480 -210 { lab=#net2}
-N 470 30 550 30 { lab=io_clamp_high[2:0]}
-N 460 10 530 10 { lab=io_analog[10:0]}
-N 410 50 490 50 { lab=io_clamp_low[2:0]}
-N 490 50 490 160 { lab=GND}
-N 490 160 500 160 { lab=GND}
-N 300 -50 620 -50 { lab=io_oeb[26:0]}
-N 470 40 650 40 { lab=io_clamp_high[2:1]}
-N 520 -150 520 -60 { lab=io_oeb[16:15]}
-N 610 -150 610 -60 { lab=io_oeb[12:11]}
-N 850 -0 850 40 { lab=io_analog[4]}
-N 640 40 810 40 { lab=io_clamp_high[2:1]}
-N 670 0 850 -0 { lab=io_analog[4]}
-N 640 100 850 100 { lab=io_clamp_high[0]}
-N 850 40 850 100 { lab=io_analog[4]}
-N 300 -270 400 -270 { lab=#net4}
-N 300 -230 400 -230 { lab=#net5}
-N 300 -190 400 -190 { lab=#net6}
-N 300 -190 400 -190 { lab=#net6}
-N 300 -170 400 -170 { lab=#net7}
-N 290 -150 390 -150 { lab=#net8}
-N 290 -130 390 -130 { lab=#net9}
-N 290 -110 390 -110 { lab=#net10}
-N 300 -90 400 -90 { lab=#net11}
-N 300 -10 400 -10 { lab=#net12}
-N 300 70 400 70 { lab=#net13}
-N -60 -290 -0 -290 { lab=#net14}
-N -60 -270 0 -270 { lab=#net15}
-N -60 -250 0 -250 { lab=#net16}
-N -60 -230 0 -230 { lab=#net17}
-N -60 -210 0 -210 { lab=#net18}
-N -60 -210 0 -210 { lab=#net18}
-N -60 -190 0 -190 { lab=#net19}
-N -60 -190 0 -190 { lab=#net19}
-N -60 -170 0 -170 { lab=#net20}
-N -60 -150 0 -150 { lab=#net21}
-N -60 -130 0 -130 { lab=#net22}
-N -60 -110 0 -110 { lab=#net23}
-N -60 -90 0 -90 { lab=#net24}
-N -60 -70 0 -70 { lab=#net25}
-N -60 -50 0 -50 { lab=#net26}
-N 300 -30 550 -30 { lab=#net27}
-N 300 -70 450 -70 {}
-C {user_analog_project_wrapper.sym} 150 -110 0 0 {name=x1}
-C {devices/vsource.sym} 590 -220 0 0 {name=V1 value="PWL(0.0 0 400u 0 5.4m 3.3)"}
-C {devices/vsource.sym} 690 -220 0 0 {name=V2 value="PWL(0.0 0 300u 0 5.3 1.8)"}
-C {devices/vsource.sym} 780 -220 0 0 {name=V3 value="PWL(0.0 0 100u 0 5m 3.3)"}
-C {devices/bus_connect.sym} 660 10 1 1 {name=l1 lab=io_analog[4]}
-C {devices/gnd.sym} 730 -150 0 0 {name=l2 lab=GND}
-C {devices/bus_connect.sym} 630 30 1 0 {name=l3 lab=io_clamp_high[2:1]}
-C {devices/bus_connect.sym} 630 90 1 0 {name=l8 lab=io_clamp_high[0]}
-C {devices/lab_pin.sym} 570 30 0 0 {name=l11 sig_type=std_logic lab=io_clamp_high[2:0]}
-C {devices/lab_pin.sym} 570 10 0 0 {name=l12 sig_type=std_logic lab=io_analog[10:0]}
-C {devices/lab_pin.sym} 480 50 0 0 {name=l9 sig_type=std_logic lab=io_clamp_low[2:0]}
-C {devices/lab_pin.sym} 450 -50 0 0 {name=l4 sig_type=std_logic lab=io_oeb[26:0]}
-C {devices/lab_pin.sym} 450 -70 0 0 {name=l5 sig_type=std_logic lab=io_out[26:0]}
-C {devices/bus_connect.sym} 510 -50 0 0 {name=l6 lab=io_oeb[16:15]}
-C {devices/bus_connect.sym} 600 -50 0 0 {name=l7 lab=io_oeb[12:11]}
-C {devices/code.sym} 920 -130 0 0 {name=TT_MODELS only_toplevel=false
-format="tcleval(@value )" value=".lib \\\\$::SKYWATER_MODELS\\\\/sky130.lib.spice tt
-.include \\\\$::PDKPATH\\\\/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice"}
-C {devices/code_shown.sym} 1100 -130 0 0 {name=s1
-only_toplevel=false
-value=".control
-tran 10u 20m
-plot V(\\"io_out[11]\\") V(\\"io_out[12]\\") V(\\"io_out[15]\\") V(\\"io_out[16]\\")
-+ V(\\"gpio_analog[3]\\") V(\\"gpio_analog[7]\\")
-.endc"}
-C {devices/lab_pin.sym} 550 -30 0 0 {name=l10 sig_type=std_logic lab=gpio_analog[17:0]}
diff --git a/xschem/analog_wrapper_tb.spice b/xschem/analog_wrapper_tb.spice
deleted file mode 100644
index b32d07c..0000000
--- a/xschem/analog_wrapper_tb.spice
+++ /dev/null
@@ -1,274 +0,0 @@
-**.subckt analog_wrapper_tb
-x1 net1 net4 GND net5 net2 net6 net7 net8 net14 net15 net16 net17 net18 net19[3] net19[2] net19[1]
-+ net19[0] net20[31] net20[30] net20[29] net20[28] net20[27] net20[26] net20[25] net20[24] net20[23] net20[22]
-+ net20[21] net20[20] net20[19] net20[18] net20[17] net20[16] net20[15] net20[14] net20[13] net20[12] net20[11]
-+ net20[10] net20[9] net20[8] net20[7] net20[6] net20[5] net20[4] net20[3] net20[2] net20[1] net20[0] net21[31]
-+ net21[30] net21[29] net21[28] net21[27] net21[26] net21[25] net21[24] net21[23] net21[22] net21[21] net21[20]
-+ net21[19] net21[18] net21[17] net21[16] net21[15] net21[14] net21[13] net21[12] net21[11] net21[10] net21[9]
-+ net21[8] net21[7] net21[6] net21[5] net21[4] net21[3] net21[2] net21[1] net21[0] net9 net10[31] net10[30]
-+ net10[29] net10[28] net10[27] net10[26] net10[25] net10[24] net10[23] net10[22] net10[21] net10[20] net10[19]
-+ net10[18] net10[17] net10[16] net10[15] net10[14] net10[13] net10[12] net10[11] net10[10] net10[9] net10[8]
-+ net10[7] net10[6] net10[5] net10[4] net10[3] net10[2] net10[1] net10[0] net22[127] net22[126] net22[125]
-+ net22[124] net22[123] net22[122] net22[121] net22[120] net22[119] net22[118] net22[117] net22[116] net22[115]
-+ net22[114] net22[113] net22[112] net22[111] net22[110] net22[109] net22[108] net22[107] net22[106] net22[105]
-+ net22[104] net22[103] net22[102] net22[101] net22[100] net22[99] net22[98] net22[97] net22[96] net22[95]
-+ net22[94] net22[93] net22[92] net22[91] net22[90] net22[89] net22[88] net22[87] net22[86] net22[85] net22[84]
-+ net22[83] net22[82] net22[81] net22[80] net22[79] net22[78] net22[77] net22[76] net22[75] net22[74] net22[73]
-+ net22[72] net22[71] net22[70] net22[69] net22[68] net22[67] net22[66] net22[65] net22[64] net22[63] net22[62]
-+ net22[61] net22[60] net22[59] net22[58] net22[57] net22[56] net22[55] net22[54] net22[53] net22[52] net22[51]
-+ net22[50] net22[49] net22[48] net22[47] net22[46] net22[45] net22[44] net22[43] net22[42] net22[41] net22[40]
-+ net22[39] net22[38] net22[37] net22[36] net22[35] net22[34] net22[33] net22[32] net22[31] net22[30] net22[29]
-+ net22[28] net22[27] net22[26] net22[25] net22[24] net22[23] net22[22] net22[21] net22[20] net22[19] net22[18]
-+ net22[17] net22[16] net22[15] net22[14] net22[13] net22[12] net22[11] net22[10] net22[9] net22[8] net22[7]
-+ net22[6] net22[5] net22[4] net22[3] net22[2] net22[1] net22[0] net11[127] net11[126] net11[125] net11[124]
-+ net11[123] net11[122] net11[121] net11[120] net11[119] net11[118] net11[117] net11[116] net11[115] net11[114]
-+ net11[113] net11[112] net11[111] net11[110] net11[109] net11[108] net11[107] net11[106] net11[105] net11[104]
-+ net11[103] net11[102] net11[101] net11[100] net11[99] net11[98] net11[97] net11[96] net11[95] net11[94]
-+ net11[93] net11[92] net11[91] net11[90] net11[89] net11[88] net11[87] net11[86] net11[85] net11[84] net11[83]
-+ net11[82] net11[81] net11[80] net11[79] net11[78] net11[77] net11[76] net11[75] net11[74] net11[73] net11[72]
-+ net11[71] net11[70] net11[69] net11[68] net11[67] net11[66] net11[65] net11[64] net11[63] net11[62] net11[61]
-+ net11[60] net11[59] net11[58] net11[57] net11[56] net11[55] net11[54] net11[53] net11[52] net11[51] net11[50]
-+ net11[49] net11[48] net11[47] net11[46] net11[45] net11[44] net11[43] net11[42] net11[41] net11[40] net11[39]
-+ net11[38] net11[37] net11[36] net11[35] net11[34] net11[33] net11[32] net11[31] net11[30] net11[29] net11[28]
-+ net11[27] net11[26] net11[25] net11[24] net11[23] net11[22] net11[21] net11[20] net11[19] net11[18] net11[17]
-+ net11[16] net11[15] net11[14] net11[13] net11[12] net11[11] net11[10] net11[9] net11[8] net11[7] net11[6]
-+ net11[5] net11[4] net11[3] net11[2] net11[1] net11[0] net23[127] net23[126] net23[125] net23[124] net23[123]
-+ net23[122] net23[121] net23[120] net23[119] net23[118] net23[117] net23[116] net23[115] net23[114] net23[113]
-+ net23[112] net23[111] net23[110] net23[109] net23[108] net23[107] net23[106] net23[105] net23[104] net23[103]
-+ net23[102] net23[101] net23[100] net23[99] net23[98] net23[97] net23[96] net23[95] net23[94] net23[93]
-+ net23[92] net23[91] net23[90] net23[89] net23[88] net23[87] net23[86] net23[85] net23[84] net23[83] net23[82]
-+ net23[81] net23[80] net23[79] net23[78] net23[77] net23[76] net23[75] net23[74] net23[73] net23[72] net23[71]
-+ net23[70] net23[69] net23[68] net23[67] net23[66] net23[65] net23[64] net23[63] net23[62] net23[61] net23[60]
-+ net23[59] net23[58] net23[57] net23[56] net23[55] net23[54] net23[53] net23[52] net23[51] net23[50] net23[49]
-+ net23[48] net23[47] net23[46] net23[45] net23[44] net23[43] net23[42] net23[41] net23[40] net23[39] net23[38]
-+ net23[37] net23[36] net23[35] net23[34] net23[33] net23[32] net23[31] net23[30] net23[29] net23[28] net23[27]
-+ net23[26] net23[25] net23[24] net23[23] net23[22] net23[21] net23[20] net23[19] net23[18] net23[17] net23[16]
-+ net23[15] net23[14] net23[13] net23[12] net23[11] net23[10] net23[9] net23[8] net23[7] net23[6] net23[5]
-+ net23[4] net23[3] net23[2] net23[1] net23[0] net24[26] net24[25] net24[24] net24[23] net24[22] net24[21]
-+ net24[20] net24[19] net24[18] net24[17] net24[16] net24[15] net24[14] net24[13] net24[12] net24[11] net24[10]
-+ net24[9] net24[8] net24[7] net24[6] net24[5] net24[4] net24[3] net24[2] net24[1] net24[0] net25[26]
-+ net25[25] net25[24] net25[23] net25[22] net25[21] net25[20] net25[19] net25[18] net25[17] net25[16] net25[15]
-+ net25[14] net25[13] net25[12] net25[11] net25[10] net25[9] net25[8] net25[7] net25[6] net25[5] net25[4]
-+ net25[3] net25[2] net25[1] net25[0] io_out[26] io_out[25] io_out[24] io_out[23] io_out[22] io_out[21]
-+ io_out[20] io_out[19] io_out[18] io_out[17] io_out[16] io_out[15] io_out[14] io_out[13] io_out[12] io_out[11]
-+ io_out[10] io_out[9] io_out[8] io_out[7] io_out[6] io_out[5] io_out[4] io_out[3] io_out[2] io_out[1] io_out[0]
-+ io_oeb[26] io_oeb[25] io_oeb[24] io_oeb[23] io_oeb[22] io_oeb[21] io_oeb[20] io_oeb[19] io_oeb[18] io_oeb[17]
-+ io_oeb[16] io_oeb[15] io_oeb[14] io_oeb[13] io_oeb[12] io_oeb[11] io_oeb[10] io_oeb[9] io_oeb[8] io_oeb[7]
-+ io_oeb[6] io_oeb[5] io_oeb[4] io_oeb[3] io_oeb[2] io_oeb[1] io_oeb[0] gpio_analog[17] gpio_analog[16]
-+ gpio_analog[15] gpio_analog[14] gpio_analog[13] gpio_analog[12] gpio_analog[11] gpio_analog[10] gpio_analog[9]
-+ gpio_analog[8] gpio_analog[7] gpio_analog[6] gpio_analog[5] gpio_analog[4] gpio_analog[3] gpio_analog[2]
-+ gpio_analog[1] gpio_analog[0] net12[17] net12[16] net12[15] net12[14] net12[13] net12[12] net12[11] net12[10]
-+ net12[9] net12[8] net12[7] net12[6] net12[5] net12[4] net12[3] net12[2] net12[1] net12[0] net3[10] net3[9]
-+ net3[8] net3[7] net3[6] net3[5] net3[4] net3[3] net3[2] net3[1] net3[0] io_clamp_high[2] io_clamp_high[1]
-+ io_clamp_high[0] GND GND GND net26 net13[2] net13[1] net13[0] user_analog_project_wrapper
-V1 net1 GND PWL(0.0 0 400u 0 5.4m 3.3)
-V2 net2 GND PWL(0.0 0 300u 0 5.3 1.8)
-V3 io_analog[4] GND PWL(0.0 0 100u 0 5m 3.3)
-**** begin user architecture code
-.lib /usr/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
-.include /usr/share/pdk/sky130A/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice
-
-.control
-tran 10u 20m
-plot V("io_out[11]") V("io_out[12]") V("io_out[15]") V("io_out[16]") V("gpio_analog[3]")
-+ V("gpio_analog[7]")
-.endc
-
-**** end user architecture code
-**.ends
-
-* expanding symbol: user_analog_project_wrapper.sym # of pins=32
-* sym_path: /home/tim/gits/caravel_user_project_analog/xschem/user_analog_project_wrapper.sym
-* sch_path: /home/tim/gits/caravel_user_project_analog/xschem/user_analog_project_wrapper.sch
-.subckt user_analog_project_wrapper vdda1 vdda2 vssa1 vssa2 vccd1 vccd2 vssd1 vssd2 wb_clk_i
-+ wb_rst_i wbs_stb_i wbs_cyc_i wbs_we_i wbs_sel_i[3] wbs_sel_i[2] wbs_sel_i[1] wbs_sel_i[0] wbs_dat_i[31]
-+ wbs_dat_i[30] wbs_dat_i[29] wbs_dat_i[28] wbs_dat_i[27] wbs_dat_i[26] wbs_dat_i[25] wbs_dat_i[24] wbs_dat_i[23]
-+ wbs_dat_i[22] wbs_dat_i[21] wbs_dat_i[20] wbs_dat_i[19] wbs_dat_i[18] wbs_dat_i[17] wbs_dat_i[16] wbs_dat_i[15]
-+ wbs_dat_i[14] wbs_dat_i[13] wbs_dat_i[12] wbs_dat_i[11] wbs_dat_i[10] wbs_dat_i[9] wbs_dat_i[8] wbs_dat_i[7]
-+ wbs_dat_i[6] wbs_dat_i[5] wbs_dat_i[4] wbs_dat_i[3] wbs_dat_i[2] wbs_dat_i[1] wbs_dat_i[0] wbs_adr_i[31]
-+ wbs_adr_i[30] wbs_adr_i[29] wbs_adr_i[28] wbs_adr_i[27] wbs_adr_i[26] wbs_adr_i[25] wbs_adr_i[24] wbs_adr_i[23]
-+ wbs_adr_i[22] wbs_adr_i[21] wbs_adr_i[20] wbs_adr_i[19] wbs_adr_i[18] wbs_adr_i[17] wbs_adr_i[16] wbs_adr_i[15]
-+ wbs_adr_i[14] wbs_adr_i[13] wbs_adr_i[12] wbs_adr_i[11] wbs_adr_i[10] wbs_adr_i[9] wbs_adr_i[8] wbs_adr_i[7]
-+ wbs_adr_i[6] wbs_adr_i[5] wbs_adr_i[4] wbs_adr_i[3] wbs_adr_i[2] wbs_adr_i[1] wbs_adr_i[0] wbs_ack_o
-+ wbs_dat_o[31] wbs_dat_o[30] wbs_dat_o[29] wbs_dat_o[28] wbs_dat_o[27] wbs_dat_o[26] wbs_dat_o[25] wbs_dat_o[24]
-+ wbs_dat_o[23] wbs_dat_o[22] wbs_dat_o[21] wbs_dat_o[20] wbs_dat_o[19] wbs_dat_o[18] wbs_dat_o[17] wbs_dat_o[16]
-+ wbs_dat_o[15] wbs_dat_o[14] wbs_dat_o[13] wbs_dat_o[12] wbs_dat_o[11] wbs_dat_o[10] wbs_dat_o[9] wbs_dat_o[8]
-+ wbs_dat_o[7] wbs_dat_o[6] wbs_dat_o[5] wbs_dat_o[4] wbs_dat_o[3] wbs_dat_o[2] wbs_dat_o[1] wbs_dat_o[0]
-+ la_data_in[127] la_data_in[126] la_data_in[125] la_data_in[124] la_data_in[123] la_data_in[122] la_data_in[121]
-+ la_data_in[120] la_data_in[119] la_data_in[118] la_data_in[117] la_data_in[116] la_data_in[115] la_data_in[114]
-+ la_data_in[113] la_data_in[112] la_data_in[111] la_data_in[110] la_data_in[109] la_data_in[108] la_data_in[107]
-+ la_data_in[106] la_data_in[105] la_data_in[104] la_data_in[103] la_data_in[102] la_data_in[101] la_data_in[100]
-+ la_data_in[99] la_data_in[98] la_data_in[97] la_data_in[96] la_data_in[95] la_data_in[94] la_data_in[93]
-+ la_data_in[92] la_data_in[91] la_data_in[90] la_data_in[89] la_data_in[88] la_data_in[87] la_data_in[86]
-+ la_data_in[85] la_data_in[84] la_data_in[83] la_data_in[82] la_data_in[81] la_data_in[80] la_data_in[79]
-+ la_data_in[78] la_data_in[77] la_data_in[76] la_data_in[75] la_data_in[74] la_data_in[73] la_data_in[72]
-+ la_data_in[71] la_data_in[70] la_data_in[69] la_data_in[68] la_data_in[67] la_data_in[66] la_data_in[65]
-+ la_data_in[64] la_data_in[63] la_data_in[62] la_data_in[61] la_data_in[60] la_data_in[59] la_data_in[58]
-+ la_data_in[57] la_data_in[56] la_data_in[55] la_data_in[54] la_data_in[53] la_data_in[52] la_data_in[51]
-+ la_data_in[50] la_data_in[49] la_data_in[48] la_data_in[47] la_data_in[46] la_data_in[45] la_data_in[44]
-+ la_data_in[43] la_data_in[42] la_data_in[41] la_data_in[40] la_data_in[39] la_data_in[38] la_data_in[37]
-+ la_data_in[36] la_data_in[35] la_data_in[34] la_data_in[33] la_data_in[32] la_data_in[31] la_data_in[30]
-+ la_data_in[29] la_data_in[28] la_data_in[27] la_data_in[26] la_data_in[25] la_data_in[24] la_data_in[23]
-+ la_data_in[22] la_data_in[21] la_data_in[20] la_data_in[19] la_data_in[18] la_data_in[17] la_data_in[16]
-+ la_data_in[15] la_data_in[14] la_data_in[13] la_data_in[12] la_data_in[11] la_data_in[10] la_data_in[9]
-+ la_data_in[8] la_data_in[7] la_data_in[6] la_data_in[5] la_data_in[4] la_data_in[3] la_data_in[2] la_data_in[1]
-+ la_data_in[0] la_data_out[127] la_data_out[126] la_data_out[125] la_data_out[124] la_data_out[123]
-+ la_data_out[122] la_data_out[121] la_data_out[120] la_data_out[119] la_data_out[118] la_data_out[117]
-+ la_data_out[116] la_data_out[115] la_data_out[114] la_data_out[113] la_data_out[112] la_data_out[111]
-+ la_data_out[110] la_data_out[109] la_data_out[108] la_data_out[107] la_data_out[106] la_data_out[105]
-+ la_data_out[104] la_data_out[103] la_data_out[102] la_data_out[101] la_data_out[100] la_data_out[99] la_data_out[98]
-+ la_data_out[97] la_data_out[96] la_data_out[95] la_data_out[94] la_data_out[93] la_data_out[92] la_data_out[91]
-+ la_data_out[90] la_data_out[89] la_data_out[88] la_data_out[87] la_data_out[86] la_data_out[85] la_data_out[84]
-+ la_data_out[83] la_data_out[82] la_data_out[81] la_data_out[80] la_data_out[79] la_data_out[78] la_data_out[77]
-+ la_data_out[76] la_data_out[75] la_data_out[74] la_data_out[73] la_data_out[72] la_data_out[71] la_data_out[70]
-+ la_data_out[69] la_data_out[68] la_data_out[67] la_data_out[66] la_data_out[65] la_data_out[64] la_data_out[63]
-+ la_data_out[62] la_data_out[61] la_data_out[60] la_data_out[59] la_data_out[58] la_data_out[57] la_data_out[56]
-+ la_data_out[55] la_data_out[54] la_data_out[53] la_data_out[52] la_data_out[51] la_data_out[50] la_data_out[49]
-+ la_data_out[48] la_data_out[47] la_data_out[46] la_data_out[45] la_data_out[44] la_data_out[43] la_data_out[42]
-+ la_data_out[41] la_data_out[40] la_data_out[39] la_data_out[38] la_data_out[37] la_data_out[36] la_data_out[35]
-+ la_data_out[34] la_data_out[33] la_data_out[32] la_data_out[31] la_data_out[30] la_data_out[29] la_data_out[28]
-+ la_data_out[27] la_data_out[26] la_data_out[25] la_data_out[24] la_data_out[23] la_data_out[22] la_data_out[21]
-+ la_data_out[20] la_data_out[19] la_data_out[18] la_data_out[17] la_data_out[16] la_data_out[15] la_data_out[14]
-+ la_data_out[13] la_data_out[12] la_data_out[11] la_data_out[10] la_data_out[9] la_data_out[8] la_data_out[7]
-+ la_data_out[6] la_data_out[5] la_data_out[4] la_data_out[3] la_data_out[2] la_data_out[1] la_data_out[0]
-+ la_oenb[127] la_oenb[126] la_oenb[125] la_oenb[124] la_oenb[123] la_oenb[122] la_oenb[121] la_oenb[120]
-+ la_oenb[119] la_oenb[118] la_oenb[117] la_oenb[116] la_oenb[115] la_oenb[114] la_oenb[113] la_oenb[112]
-+ la_oenb[111] la_oenb[110] la_oenb[109] la_oenb[108] la_oenb[107] la_oenb[106] la_oenb[105] la_oenb[104]
-+ la_oenb[103] la_oenb[102] la_oenb[101] la_oenb[100] la_oenb[99] la_oenb[98] la_oenb[97] la_oenb[96] la_oenb[95]
-+ la_oenb[94] la_oenb[93] la_oenb[92] la_oenb[91] la_oenb[90] la_oenb[89] la_oenb[88] la_oenb[87] la_oenb[86]
-+ la_oenb[85] la_oenb[84] la_oenb[83] la_oenb[82] la_oenb[81] la_oenb[80] la_oenb[79] la_oenb[78] la_oenb[77]
-+ la_oenb[76] la_oenb[75] la_oenb[74] la_oenb[73] la_oenb[72] la_oenb[71] la_oenb[70] la_oenb[69] la_oenb[68]
-+ la_oenb[67] la_oenb[66] la_oenb[65] la_oenb[64] la_oenb[63] la_oenb[62] la_oenb[61] la_oenb[60] la_oenb[59]
-+ la_oenb[58] la_oenb[57] la_oenb[56] la_oenb[55] la_oenb[54] la_oenb[53] la_oenb[52] la_oenb[51] la_oenb[50]
-+ la_oenb[49] la_oenb[48] la_oenb[47] la_oenb[46] la_oenb[45] la_oenb[44] la_oenb[43] la_oenb[42] la_oenb[41]
-+ la_oenb[40] la_oenb[39] la_oenb[38] la_oenb[37] la_oenb[36] la_oenb[35] la_oenb[34] la_oenb[33] la_oenb[32]
-+ la_oenb[31] la_oenb[30] la_oenb[29] la_oenb[28] la_oenb[27] la_oenb[26] la_oenb[25] la_oenb[24] la_oenb[23]
-+ la_oenb[22] la_oenb[21] la_oenb[20] la_oenb[19] la_oenb[18] la_oenb[17] la_oenb[16] la_oenb[15] la_oenb[14]
-+ la_oenb[13] la_oenb[12] la_oenb[11] la_oenb[10] la_oenb[9] la_oenb[8] la_oenb[7] la_oenb[6] la_oenb[5]
-+ la_oenb[4] la_oenb[3] la_oenb[2] la_oenb[1] la_oenb[0] io_in[26] io_in[25] io_in[24] io_in[23] io_in[22]
-+ io_in[21] io_in[20] io_in[19] io_in[18] io_in[17] io_in[16] io_in[15] io_in[14] io_in[13] io_in[12] io_in[11]
-+ io_in[10] io_in[9] io_in[8] io_in[7] io_in[6] io_in[5] io_in[4] io_in[3] io_in[2] io_in[1] io_in[0]
-+ io_in_3v3[26] io_in_3v3[25] io_in_3v3[24] io_in_3v3[23] io_in_3v3[22] io_in_3v3[21] io_in_3v3[20] io_in_3v3[19]
-+ io_in_3v3[18] io_in_3v3[17] io_in_3v3[16] io_in_3v3[15] io_in_3v3[14] io_in_3v3[13] io_in_3v3[12] io_in_3v3[11]
-+ io_in_3v3[10] io_in_3v3[9] io_in_3v3[8] io_in_3v3[7] io_in_3v3[6] io_in_3v3[5] io_in_3v3[4] io_in_3v3[3]
-+ io_in_3v3[2] io_in_3v3[1] io_in_3v3[0] io_out[26] io_out[25] io_out[24] io_out[23] io_out[22] io_out[21]
-+ io_out[20] io_out[19] io_out[18] io_out[17] io_out[16] io_out[15] io_out[14] io_out[13] io_out[12] io_out[11]
-+ io_out[10] io_out[9] io_out[8] io_out[7] io_out[6] io_out[5] io_out[4] io_out[3] io_out[2] io_out[1] io_out[0]
-+ io_oeb[26] io_oeb[25] io_oeb[24] io_oeb[23] io_oeb[22] io_oeb[21] io_oeb[20] io_oeb[19] io_oeb[18] io_oeb[17]
-+ io_oeb[16] io_oeb[15] io_oeb[14] io_oeb[13] io_oeb[12] io_oeb[11] io_oeb[10] io_oeb[9] io_oeb[8] io_oeb[7]
-+ io_oeb[6] io_oeb[5] io_oeb[4] io_oeb[3] io_oeb[2] io_oeb[1] io_oeb[0] gpio_analog[17] gpio_analog[16]
-+ gpio_analog[15] gpio_analog[14] gpio_analog[13] gpio_analog[12] gpio_analog[11] gpio_analog[10] gpio_analog[9]
-+ gpio_analog[8] gpio_analog[7] gpio_analog[6] gpio_analog[5] gpio_analog[4] gpio_analog[3] gpio_analog[2]
-+ gpio_analog[1] gpio_analog[0] gpio_noesd[17] gpio_noesd[16] gpio_noesd[15] gpio_noesd[14] gpio_noesd[13]
-+ gpio_noesd[12] gpio_noesd[11] gpio_noesd[10] gpio_noesd[9] gpio_noesd[8] gpio_noesd[7] gpio_noesd[6] gpio_noesd[5]
-+ gpio_noesd[4] gpio_noesd[3] gpio_noesd[2] gpio_noesd[1] gpio_noesd[0] io_analog[10] io_analog[9] io_analog[8]
-+ io_analog[7] io_analog[6] io_analog[5] io_analog[4] io_analog[3] io_analog[2] io_analog[1] io_analog[0]
-+ io_clamp_high[2] io_clamp_high[1] io_clamp_high[0] io_clamp_low[2] io_clamp_low[1] io_clamp_low[0] user_clock2
-+ user_irq[2] user_irq[1] user_irq[0]
-*.iopin vdda1
-*.iopin vdda2
-*.iopin vssa1
-*.iopin vssa2
-*.iopin vccd1
-*.iopin vccd2
-*.iopin vssd1
-*.iopin vssd2
-*.ipin wb_clk_i
-*.ipin wb_rst_i
-*.ipin wbs_stb_i
-*.ipin wbs_cyc_i
-*.ipin wbs_we_i
-*.ipin wbs_sel_i[3],wbs_sel_i[2],wbs_sel_i[1],wbs_sel_i[0]
-*.ipin
-*+ wbs_dat_i[31],wbs_dat_i[30],wbs_dat_i[29],wbs_dat_i[28],wbs_dat_i[27],wbs_dat_i[26],wbs_dat_i[25],wbs_dat_i[24],wbs_dat_i[23],wbs_dat_i[22],wbs_dat_i[21],wbs_dat_i[20],wbs_dat_i[19],wbs_dat_i[18],wbs_dat_i[17],wbs_dat_i[16],wbs_dat_i[15],wbs_dat_i[14],wbs_dat_i[13],wbs_dat_i[12],wbs_dat_i[11],wbs_dat_i[10],wbs_dat_i[9],wbs_dat_i[8],wbs_dat_i[7],wbs_dat_i[6],wbs_dat_i[5],wbs_dat_i[4],wbs_dat_i[3],wbs_dat_i[2],wbs_dat_i[1],wbs_dat_i[0]
-*.ipin
-*+ wbs_adr_i[31],wbs_adr_i[30],wbs_adr_i[29],wbs_adr_i[28],wbs_adr_i[27],wbs_adr_i[26],wbs_adr_i[25],wbs_adr_i[24],wbs_adr_i[23],wbs_adr_i[22],wbs_adr_i[21],wbs_adr_i[20],wbs_adr_i[19],wbs_adr_i[18],wbs_adr_i[17],wbs_adr_i[16],wbs_adr_i[15],wbs_adr_i[14],wbs_adr_i[13],wbs_adr_i[12],wbs_adr_i[11],wbs_adr_i[10],wbs_adr_i[9],wbs_adr_i[8],wbs_adr_i[7],wbs_adr_i[6],wbs_adr_i[5],wbs_adr_i[4],wbs_adr_i[3],wbs_adr_i[2],wbs_adr_i[1],wbs_adr_i[0]
-*.opin wbs_ack_o
-*.opin
-*+ wbs_dat_o[31],wbs_dat_o[30],wbs_dat_o[29],wbs_dat_o[28],wbs_dat_o[27],wbs_dat_o[26],wbs_dat_o[25],wbs_dat_o[24],wbs_dat_o[23],wbs_dat_o[22],wbs_dat_o[21],wbs_dat_o[20],wbs_dat_o[19],wbs_dat_o[18],wbs_dat_o[17],wbs_dat_o[16],wbs_dat_o[15],wbs_dat_o[14],wbs_dat_o[13],wbs_dat_o[12],wbs_dat_o[11],wbs_dat_o[10],wbs_dat_o[9],wbs_dat_o[8],wbs_dat_o[7],wbs_dat_o[6],wbs_dat_o[5],wbs_dat_o[4],wbs_dat_o[3],wbs_dat_o[2],wbs_dat_o[1],wbs_dat_o[0]
-*.ipin
-*+ la_data_in[127],la_data_in[126],la_data_in[125],la_data_in[124],la_data_in[123],la_data_in[122],la_data_in[121],la_data_in[120],la_data_in[119],la_data_in[118],la_data_in[117],la_data_in[116],la_data_in[115],la_data_in[114],la_data_in[113],la_data_in[112],la_data_in[111],la_data_in[110],la_data_in[109],la_data_in[108],la_data_in[107],la_data_in[106],la_data_in[105],la_data_in[104],la_data_in[103],la_data_in[102],la_data_in[101],la_data_in[100],la_data_in[99],la_data_in[98],la_data_in[97],la_data_in[96],la_data_in[95],la_data_in[94],la_data_in[93],la_data_in[92],la_data_in[91],la_data_in[90],la_data_in[89],la_data_in[88],la_data_in[87],la_data_in[86],la_data_in[85],la_data_in[84],la_data_in[83],la_data_in[82],la_data_in[81],la_data_in[80],la_data_in[79],la_data_in[78],la_data_in[77],la_data_in[76],la_data_in[75],la_data_in[74],la_data_in[73],la_data_in[72],la_data_in[71],la_data_in[70],la_data_in[69],la_data_in[68],la_data_in[67],la_data_in[66],la_data_in[65],la_data_in[64],la_data_in[63],la_data_in[62],la_data_in[61],la_data_in[60],la_data_in[59],la_data_in[58],la_data_in[57],la_data_in[56],la_data_in[55],la_data_in[54],la_data_in[53],la_data_in[52],la_data_in[51],la_data_in[50],la_data_in[49],la_data_in[48],la_data_in[47],la_data_in[46],la_data_in[45],la_data_in[44],la_data_in[43],la_data_in[42],la_data_in[41],la_data_in[40],la_data_in[39],la_data_in[38],la_data_in[37],la_data_in[36],la_data_in[35],la_data_in[34],la_data_in[33],la_data_in[32],la_data_in[31],la_data_in[30],la_data_in[29],la_data_in[28],la_data_in[27],la_data_in[26],la_data_in[25],la_data_in[24],la_data_in[23],la_data_in[22],la_data_in[21],la_data_in[20],la_data_in[19],la_data_in[18],la_data_in[17],la_data_in[16],la_data_in[15],la_data_in[14],la_data_in[13],la_data_in[12],la_data_in[11],la_data_in[10],la_data_in[9],la_data_in[8],la_data_in[7],la_data_in[6],la_data_in[5],la_data_in[4],la_data_in[3],la_data_in[2],la_data_in[1],la_data_in[0]
-*.opin
-*+ la_data_out[127],la_data_out[126],la_data_out[125],la_data_out[124],la_data_out[123],la_data_out[122],la_data_out[121],la_data_out[120],la_data_out[119],la_data_out[118],la_data_out[117],la_data_out[116],la_data_out[115],la_data_out[114],la_data_out[113],la_data_out[112],la_data_out[111],la_data_out[110],la_data_out[109],la_data_out[108],la_data_out[107],la_data_out[106],la_data_out[105],la_data_out[104],la_data_out[103],la_data_out[102],la_data_out[101],la_data_out[100],la_data_out[99],la_data_out[98],la_data_out[97],la_data_out[96],la_data_out[95],la_data_out[94],la_data_out[93],la_data_out[92],la_data_out[91],la_data_out[90],la_data_out[89],la_data_out[88],la_data_out[87],la_data_out[86],la_data_out[85],la_data_out[84],la_data_out[83],la_data_out[82],la_data_out[81],la_data_out[80],la_data_out[79],la_data_out[78],la_data_out[77],la_data_out[76],la_data_out[75],la_data_out[74],la_data_out[73],la_data_out[72],la_data_out[71],la_data_out[70],la_data_out[69],la_data_out[68],la_data_out[67],la_data_out[66],la_data_out[65],la_data_out[64],la_data_out[63],la_data_out[62],la_data_out[61],la_data_out[60],la_data_out[59],la_data_out[58],la_data_out[57],la_data_out[56],la_data_out[55],la_data_out[54],la_data_out[53],la_data_out[52],la_data_out[51],la_data_out[50],la_data_out[49],la_data_out[48],la_data_out[47],la_data_out[46],la_data_out[45],la_data_out[44],la_data_out[43],la_data_out[42],la_data_out[41],la_data_out[40],la_data_out[39],la_data_out[38],la_data_out[37],la_data_out[36],la_data_out[35],la_data_out[34],la_data_out[33],la_data_out[32],la_data_out[31],la_data_out[30],la_data_out[29],la_data_out[28],la_data_out[27],la_data_out[26],la_data_out[25],la_data_out[24],la_data_out[23],la_data_out[22],la_data_out[21],la_data_out[20],la_data_out[19],la_data_out[18],la_data_out[17],la_data_out[16],la_data_out[15],la_data_out[14],la_data_out[13],la_data_out[12],la_data_out[11],la_data_out[10],la_data_out[9],la_data_out[8],la_data_out[7],la_data_out[6],la_data_out[5],la_data_out[4],la_data_out[3],la_data_out[2],la_data_out[1],la_data_out[0]
-*.ipin
-*+ io_in[26],io_in[25],io_in[24],io_in[23],io_in[22],io_in[21],io_in[20],io_in[19],io_in[18],io_in[17],io_in[16],io_in[15],io_in[14],io_in[13],io_in[12],io_in[11],io_in[10],io_in[9],io_in[8],io_in[7],io_in[6],io_in[5],io_in[4],io_in[3],io_in[2],io_in[1],io_in[0]
-*.ipin
-*+ io_in_3v3[26],io_in_3v3[25],io_in_3v3[24],io_in_3v3[23],io_in_3v3[22],io_in_3v3[21],io_in_3v3[20],io_in_3v3[19],io_in_3v3[18],io_in_3v3[17],io_in_3v3[16],io_in_3v3[15],io_in_3v3[14],io_in_3v3[13],io_in_3v3[12],io_in_3v3[11],io_in_3v3[10],io_in_3v3[9],io_in_3v3[8],io_in_3v3[7],io_in_3v3[6],io_in_3v3[5],io_in_3v3[4],io_in_3v3[3],io_in_3v3[2],io_in_3v3[1],io_in_3v3[0]
-*.ipin user_clock2
-*.opin
-*+ io_out[26],io_out[25],io_out[24],io_out[23],io_out[22],io_out[21],io_out[20],io_out[19],io_out[18],io_out[17],io_out[16],io_out[15],io_out[14],io_out[13],io_out[12],io_out[11],io_out[10],io_out[9],io_out[8],io_out[7],io_out[6],io_out[5],io_out[4],io_out[3],io_out[2],io_out[1],io_out[0]
-*.opin
-*+ io_oeb[26],io_oeb[25],io_oeb[24],io_oeb[23],io_oeb[22],io_oeb[21],io_oeb[20],io_oeb[19],io_oeb[18],io_oeb[17],io_oeb[16],io_oeb[15],io_oeb[14],io_oeb[13],io_oeb[12],io_oeb[11],io_oeb[10],io_oeb[9],io_oeb[8],io_oeb[7],io_oeb[6],io_oeb[5],io_oeb[4],io_oeb[3],io_oeb[2],io_oeb[1],io_oeb[0]
-*.iopin
-*+ gpio_analog[17],gpio_analog[16],gpio_analog[15],gpio_analog[14],gpio_analog[13],gpio_analog[12],gpio_analog[11],gpio_analog[10],gpio_analog[9],gpio_analog[8],gpio_analog[7],gpio_analog[6],gpio_analog[5],gpio_analog[4],gpio_analog[3],gpio_analog[2],gpio_analog[1],gpio_analog[0]
-*.iopin
-*+ gpio_noesd[17],gpio_noesd[16],gpio_noesd[15],gpio_noesd[14],gpio_noesd[13],gpio_noesd[12],gpio_noesd[11],gpio_noesd[10],gpio_noesd[9],gpio_noesd[8],gpio_noesd[7],gpio_noesd[6],gpio_noesd[5],gpio_noesd[4],gpio_noesd[3],gpio_noesd[2],gpio_noesd[1],gpio_noesd[0]
-*.iopin
-*+ io_analog[10],io_analog[9],io_analog[8],io_analog[7],io_analog[6],io_analog[5],io_analog[4],io_analog[3],io_analog[2],io_analog[1],io_analog[0]
-*.iopin io_clamp_high[2],io_clamp_high[1],io_clamp_high[0]
-*.iopin io_clamp_low[2],io_clamp_low[1],io_clamp_low[0]
-*.opin user_irq[2],user_irq[1],user_irq[0]
-*.ipin
-*+ la_oenb[127],la_oenb[126],la_oenb[125],la_oenb[124],la_oenb[123],la_oenb[122],la_oenb[121],la_oenb[120],la_oenb[119],la_oenb[118],la_oenb[117],la_oenb[116],la_oenb[115],la_oenb[114],la_oenb[113],la_oenb[112],la_oenb[111],la_oenb[110],la_oenb[109],la_oenb[108],la_oenb[107],la_oenb[106],la_oenb[105],la_oenb[104],la_oenb[103],la_oenb[102],la_oenb[101],la_oenb[100],la_oenb[99],la_oenb[98],la_oenb[97],la_oenb[96],la_oenb[95],la_oenb[94],la_oenb[93],la_oenb[92],la_oenb[91],la_oenb[90],la_oenb[89],la_oenb[88],la_oenb[87],la_oenb[86],la_oenb[85],la_oenb[84],la_oenb[83],la_oenb[82],la_oenb[81],la_oenb[80],la_oenb[79],la_oenb[78],la_oenb[77],la_oenb[76],la_oenb[75],la_oenb[74],la_oenb[73],la_oenb[72],la_oenb[71],la_oenb[70],la_oenb[69],la_oenb[68],la_oenb[67],la_oenb[66],la_oenb[65],la_oenb[64],la_oenb[63],la_oenb[62],la_oenb[61],la_oenb[60],la_oenb[59],la_oenb[58],la_oenb[57],la_oenb[56],la_oenb[55],la_oenb[54],la_oenb[53],la_oenb[52],la_oenb[51],la_oenb[50],la_oenb[49],la_oenb[48],la_oenb[47],la_oenb[46],la_oenb[45],la_oenb[44],la_oenb[43],la_oenb[42],la_oenb[41],la_oenb[40],la_oenb[39],la_oenb[38],la_oenb[37],la_oenb[36],la_oenb[35],la_oenb[34],la_oenb[33],la_oenb[32],la_oenb[31],la_oenb[30],la_oenb[29],la_oenb[28],la_oenb[27],la_oenb[26],la_oenb[25],la_oenb[24],la_oenb[23],la_oenb[22],la_oenb[21],la_oenb[20],la_oenb[19],la_oenb[18],la_oenb[17],la_oenb[16],la_oenb[15],la_oenb[14],la_oenb[13],la_oenb[12],la_oenb[11],la_oenb[10],la_oenb[9],la_oenb[8],la_oenb[7],la_oenb[6],la_oenb[5],la_oenb[4],la_oenb[3],la_oenb[2],la_oenb[1],la_oenb[0]
-x1 vdda1 vccd1 gpio_analog[3] io_out[11] io_out[12] vssa1 example_por
-x2 io_analog[4] vccd1 gpio_analog[7] io_out[15] io_out[16] vssa1 example_por
-.ends
-
-
-* expanding symbol: example_por.sym # of pins=6
-* sym_path: /home/tim/gits/caravel_user_project_analog/xschem/example_por.sym
-* sch_path: /home/tim/gits/caravel_user_project_analog/xschem/example_por.sch
-.subckt example_por vdd3v3 vdd1v8 porb_h porb_l por_l vss
-*.iopin vdd3v3
-*.iopin vss
-*.opin porb_h
-*.opin porb_l
-*.opin por_l
-*.iopin vdd1v8
-XC1 net9 vss sky130_fd_pr__cap_mim_m3_1 W=30 L=30 MF=1 m=1
-XC2 vss net9 sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=1 m=1
-XM1 net3 net7 net5 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
-+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
-+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
-XM2 net2 net3 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
-+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
-+ sa=0 sb=0 sd=0 mult=1 m=1
-XR1 net4 vdd3v3 vss sky130_fd_pr__res_xhigh_po_0p69 L=500 mult=1 m=1
-XM4 net5 net6 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
-+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
-+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
-XM5 net3 net3 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
-+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
-+ sa=0 sb=0 sd=0 mult=1 m=1
-XR2 vss net4 vss sky130_fd_pr__res_xhigh_po_0p69 L=150 mult=1 m=1
-XM7 net2 net2 net1 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
-+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
-+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
-XM8 net1 net1 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29'
-+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
-+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
-XM10 net7 net4 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
-+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
-+ sa=0 sb=0 sd=0 mult=1 m=1
-XM9 net7 net7 net6 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
-+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
-+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
-XM11 net6 net6 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=16 nf=8 ad='int((nf+1)/2) * W/nf * 0.29'
-+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
-+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
-XM12 net8 net1 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
-+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
-+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
-XM13 net9 net2 net8 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
-+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
-+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
-XR3 vss vss vss sky130_fd_pr__res_xhigh_po_0p69 L=25 mult=2 m=2
-x2 net10 vss vss vdd3v3 vdd3v3 porb_h sky130_fd_sc_hvl__buf_8
-x3 net10 vss vss vdd1v8 vdd1v8 porb_l sky130_fd_sc_hvl__buf_8
-x4 net10 vss vss vdd1v8 vdd1v8 por_l sky130_fd_sc_hvl__inv_8
-x5 net9 vss vss vdd3v3 vdd3v3 net10 sky130_fd_sc_hvl__schmittbuf_1
-.ends
-
-.GLOBAL GND
-** flattened .save nodes
-.end
diff --git a/xschem/current_test.spice b/xschem/current_test.spice
deleted file mode 100644
index 8e4162d..0000000
--- a/xschem/current_test.spice
+++ /dev/null
@@ -1,86 +0,0 @@
-*---------------------------------------------------------------------------
-* SPDX-FileCopyrightText: 2020 Efabless Corporation
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* https://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*
-* SPDX-License-Identifier: Apache-2.0
-*---------------------------------------------------------------------------
-* Simple POR circuit for Caravel current mirror test
-*-------------------------------------------------------------------
-
-.param mc_mm_switch=0
-.lib /usr/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
-
-* Note: 20 resistors of length 25um connected in series
-Xres1 vdda vin vss sky130_fd_pr__res_xhigh_po_0p69 l=500
-Xres2 vin vss vss sky130_fd_pr__res_xhigh_po_0p69 l=149
-
-* voltage sources at 0V for measuring current in each branch
-
-Vm1 vssm1 vss DC=0
-Vm2 vdda vddm2 DC=0
-Vm3 vdda vddm3 DC=0
-Vm4 vssm4 vss DC=0
-Vm5 vssm5 vss DC=0
-Vm6 vdda vddm6 DC=0
-Vm7 vdda vddm7 DC=0
-
-* D G S B
-Xm1 casc1 vin vssm1 vss sky130_fd_pr__nfet_g5v0d10v5 w=2 l=0.8 m=1
-Xc1 mir1 casc1 casc1 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1
-Xm2 mir1 mir1 vddm2 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=8
-Xm3 mir2 mir1 vddm3 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1
-Xc2 casc2 casc1 mir2 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1
-Xm4 casc2 casc2 vssm4 vss sky130_fd_pr__nfet_g5v0d10v5 w=2 l=0.8 m=7
-Xm5 casc3 casc2 vssm5 vss sky130_fd_pr__nfet_g5v0d10v5 w=2 l=0.8 m=1
-Xc3 mir3 casc3 casc3 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1
-Xm6 mir3 mir3 vddm6 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=7
-Xm7 mir4 mir3 vddm7 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1
-Xc4 vcap casc3 mir4 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1
-
-* Check branch currents in each mirror branch.
-* 1st branch should be 240nA
-* 2nd branch should be 30nA
-* 3rd branch should be 4.3nA
-* 4th branch should be 612pA
-*
-* Result: vin sits at 0.7590 (close to 0.7575 target)
-* I(Vm1/2) = 202.80 nA
-* I(Vm3/4) = 26.10 nA (should be /8) actually /7.77
-* I(Vm5/6) = 4.58 nA (should be /7) actually /5.70
-* I(Vm7) = 0.67 nA (should be /7) actually /6.80
-
-*----------------------------
-* Testbench circuit
-*----------------------------
-Vpwr vdda vss DC=3.3
-Rgnd vss 0 0.01
-Rload vcap vss 1MEG
-*----------------------------
-
-*----------------------------
-* Testbench control
-*----------------------------
-.control
-op
-print V(vin)
-print I(Vm1)
-print I(Vm2)
-print I(Vm3)
-print I(Vm4)
-print I(Vm5)
-print I(Vm6)
-print I(Vm7)
-.endc
-
-.end
-
diff --git a/xschem/example_por.sch b/xschem/example_por.sch
deleted file mode 100644
index cf6e0c3..0000000
--- a/xschem/example_por.sch
+++ /dev/null
@@ -1,297 +0,0 @@
-v {xschem version=2.9.9 file_version=1.2 }
-G {}
-K {}
-V {}
-S {}
-E {}
-L 4 3370 -60 3390 -60 {}
-L 4 3390 -60 3390 80 {}
-L 4 3370 80 3390 80 {}
-T {Current step-down mirror} 2270 140 0 0 0.4 0.4 {}
-T {Charge accumulator} 2650 140 0 0 0.4 0.4 {}
-T {Voltage divider} 1860 140 0 0 0.4 0.4 {}
-T {Schmitt trigger} 2930 -200 0 0 0.4 0.4 {}
-T {150 / 650 * 3.3V = 0.76V} 1860 180 0 0 0.4 0.4 {}
-T {step down 8x} 2130 -430 0 0 0.4 0.4 {}
-T {step down 7x} 2330 80 0 0 0.4 0.4 {}
-T {step down 7x} 2520 -430 0 0 0.4 0.4 {}
-T {1.8V domain outputs} 3400 0 0 0 0.4 0.4 {}
-T {3.3V domain output} 3410 -140 0 0 0.4 0.4 {}
-T {392 : 1} 2270 180 0 0 0.4 0.4 {}
-T {Simple power-on-reset circuit
-calibrated to 500us nominal delay
-no temperature compensation} 1950 -570 0 0 0.6 0.6 {}
-N 2500 -310 2500 -270 { lab=#net1}
-N 2500 -210 2500 -100 { lab=#net2}
-N 2300 -40 2300 20 { lab=#net3}
-N 2300 80 2300 110 { lab=vss}
-N 2360 110 2500 110 { lab=vss}
-N 2500 80 2500 110 { lab=vss}
-N 2400 50 2460 50 { lab=#net3}
-N 2360 -400 2500 -400 { lab=vdd3v3}
-N 2500 -400 2500 -370 { lab=vdd3v3}
-N 2500 -400 2790 -400 { lab=vdd3v3}
-N 2300 -10 2370 -10 { lab=#net3}
-N 2370 -10 2370 50 { lab=#net3}
-N 2500 -290 2570 -290 { lab=#net1}
-N 2570 -340 2570 -290 { lab=#net1}
-N 2540 -340 2570 -340 { lab=#net1}
-N 2500 -190 2570 -190 { lab=#net2}
-N 2570 -240 2570 -190 { lab=#net2}
-N 2540 -240 2570 -240 { lab=#net2}
-N 2240 110 2360 110 { lab=vss}
-N 2500 110 2630 110 { lab=vss}
-N 2500 50 2630 50 { lab=vss}
-N 2110 110 2240 110 { lab=vss}
-N 1930 60 1930 110 { lab=vss}
-N 1930 -160 1930 0 { lab=#net4}
-N 1930 -400 1930 -220 { lab=vdd3v3}
-N 2110 -400 2360 -400 { lab=vdd3v3}
-N 1880 -190 1910 -190 { lab=vss}
-N 1880 -190 1880 110 { lab=vss}
-N 1880 110 1930 110 { lab=vss}
-N 1880 30 1910 30 { lab=vss}
-N 2300 -310 2300 -270 { lab=#net5}
-N 2300 -400 2300 -370 { lab=vdd3v3}
-N 2300 -140 2300 -100 { lab=#net3}
-N 2340 50 2400 50 { lab=#net3}
-N 2300 -210 2300 -140 { lab=#net3}
-N 2100 80 2100 110 { lab=vss}
-N 2100 110 2110 110 { lab=vss}
-N 2050 50 2060 50 { lab=#net4}
-N 2050 -70 2050 50 { lab=#net4}
-N 1930 -70 2050 -70 { lab=#net4}
-N 1930 -400 2110 -400 { lab=vdd3v3}
-N 2100 -400 2100 -370 { lab=vdd3v3}
-N 2100 -310 2100 -270 { lab=#net6}
-N 2100 -210 2100 20 { lab=#net7}
-N 2100 50 2300 50 { lab=vss}
-N 2200 50 2200 110 { lab=vss}
-N 2140 -240 2260 -240 { lab=#net7}
-N 2140 -340 2260 -340 { lab=#net6}
-N 2100 -290 2180 -290 { lab=#net6}
-N 2180 -340 2180 -290 { lab=#net6}
-N 2100 -180 2180 -180 { lab=#net7}
-N 2180 -240 2180 -180 { lab=#net7}
-N 1930 -240 2100 -240 { lab=vdd3v3}
-N 1930 -340 2100 -340 { lab=vdd3v3}
-N 1930 110 2100 110 { lab=vss}
-N 2300 -240 2500 -240 { lab=vdd3v3}
-N 2300 -340 2500 -340 { lab=vdd3v3}
-N 2400 -340 2400 -240 { lab=vdd3v3}
-N 2400 -400 2400 -340 { lab=vdd3v3}
-N 2570 -240 2650 -240 { lab=#net2}
-N 2570 -340 2650 -340 { lab=#net1}
-N 2690 -400 2690 -370 { lab=vdd3v3}
-N 2790 -400 2790 -340 { lab=vdd3v3}
-N 2690 -340 2790 -340 { lab=vdd3v3}
-N 2690 -240 2790 -240 { lab=vdd3v3}
-N 2790 -340 2790 -240 { lab=vdd3v3}
-N 2690 -310 2690 -270 { lab=#net8}
-N 2690 -210 2690 -150 { lab=#net9}
-N 1830 30 1880 30 { lab=vss}
-N 1810 60 1810 110 { lab=vss}
-N 1810 110 1880 110 { lab=vss}
-N 1810 -70 1810 0 { lab=vss}
-N 1810 -70 1880 -70 { lab=vss}
-N 2690 -150 2690 -70 { lab=#net9}
-N 2820 -130 2820 -70 { lab=#net9}
-N 2690 -130 2820 -130 { lab=#net9}
-N 2630 110 2820 110 { lab=vss}
-N 2820 -10 2820 110 { lab=vss}
-N 2690 -10 2690 110 { lab=vss}
-N 2820 -130 2980 -130 { lab=#net9}
-N 3060 -130 3130 -130 { lab=#net10}
-N 3090 -130 3090 60 { lab=#net10}
-N 3090 60 3130 60 { lab=#net10}
-N 3090 -40 3130 -40 { lab=#net10}
-N 3210 -130 3300 -130 { lab=porb_h}
-N 3210 -40 3300 -40 { lab=porb_l}
-N 3210 60 3300 60 { lab=por_l}
-N 2790 -400 2840 -400 { lab=vdd3v3}
-N 2820 110 2870 110 { lab=vss}
-N 2630 50 2690 50 { lab=vss}
-N 2300 -100 2300 -40 { lab=#net3}
-N 2500 -100 2500 -30 { lab=#net2}
-N 2500 -30 2500 20 { lab=#net2}
-C {sky130_fd_pr/cap_mim_m3_1.sym} 2690 -40 0 0 {name=C1 model=cap_mim_m3_1 W=30 L=30 MF=1 spiceprefix=X}
-C {sky130_fd_pr/cap_mim_m3_2.sym} 2820 -40 2 1 {name=C2 model=cap_mim_m3_2 W=30 L=30 MF=1 spiceprefix=X}
-C {sky130_fd_pr/pfet_g5v0d10v5.sym} 2280 -240 0 0 {name=M1
-L=0.8
-W=2
-nf=1
-mult=1
-ad="'int((nf+1)/2) * W/nf * 0.29'"
-pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
-as="'int((nf+2)/2) * W/nf * 0.29'"
-ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
-nrd="'0.29 / W'" nrs="'0.29 / W'"
-sa=0 sb=0 sd=0
-model=pfet_g5v0d10v5
-spiceprefix=X
-}
-C {sky130_fd_pr/nfet_g5v0d10v5.sym} 2480 50 0 0 {name=M2
-L=0.8
-W=2
-nf=1
-mult=1
-ad="'int((nf+1)/2) * W/nf * 0.29'"
-pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
-as="'int((nf+2)/2) * W/nf * 0.29'"
-ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
-nrd="'0.29 / W'" nrs="'0.29 / W'"
-sa=0 sb=0 sd=0
-model=nfet_g5v0d10v5
-spiceprefix=X
-}
-C {sky130_fd_pr/res_xhigh_po_0p69.sym} 1930 -190 0 0 {name=R1
-L=500
-model=res_xhigh_po_0p69
-spiceprefix=X
-mult=1}
-C {sky130_fd_pr/pfet_g5v0d10v5.sym} 2280 -340 0 0 {name=M4
-L=0.8
-W=2
-nf=1
-mult=1
-ad="'int((nf+1)/2) * W/nf * 0.29'"
-pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
-as="'int((nf+2)/2) * W/nf * 0.29'"
-ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
-nrd="'0.29 / W'" nrs="'0.29 / W'"
-sa=0 sb=0 sd=0
-model=pfet_g5v0d10v5
-spiceprefix=X
-}
-C {sky130_fd_pr/nfet_g5v0d10v5.sym} 2320 50 0 1 {name=M5
-L=0.8
-W=14
-nf=7
-mult=1
-ad="'int((nf+1)/2) * W/nf * 0.29'"
-pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
-as="'int((nf+2)/2) * W/nf * 0.29'"
-ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
-nrd="'0.29 / W'" nrs="'0.29 / W'"
-sa=0 sb=0 sd=0
-model=nfet_g5v0d10v5
-spiceprefix=X
-}
-C {sky130_fd_pr/res_xhigh_po_0p69.sym} 1930 30 0 0 {name=R2
-L=150
-model=res_xhigh_po_0p69
-spiceprefix=X
-mult=1}
-C {sky130_fd_pr/pfet_g5v0d10v5.sym} 2520 -240 0 1 {name=M7
-L=0.8
-W=2
-nf=1
-mult=1
-ad="'int((nf+1)/2) * W/nf * 0.29'"
-pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
-as="'int((nf+2)/2) * W/nf * 0.29'"
-ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
-nrd="'0.29 / W'" nrs="'0.29 / W'"
-sa=0 sb=0 sd=0
-model=pfet_g5v0d10v5
-spiceprefix=X
-}
-C {sky130_fd_pr/pfet_g5v0d10v5.sym} 2520 -340 0 1 {name=M8
-L=0.8
-W=14
-nf=7
-mult=1
-ad="'int((nf+1)/2) * W/nf * 0.29'"
-pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
-as="'int((nf+2)/2) * W/nf * 0.29'"
-ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
-nrd="'0.29 / W'" nrs="'0.29 / W'"
-sa=0 sb=0 sd=0
-model=pfet_g5v0d10v5
-spiceprefix=X
-}
-C {sky130_fd_pr/nfet_g5v0d10v5.sym} 2080 50 0 0 {name=M10
-L=0.8
-W=2
-nf=1
-mult=1
-ad="'int((nf+1)/2) * W/nf * 0.29'"
-pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
-as="'int((nf+2)/2) * W/nf * 0.29'"
-ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
-nrd="'0.29 / W'" nrs="'0.29 / W'"
-sa=0 sb=0 sd=0
-model=nfet_g5v0d10v5
-spiceprefix=X
-}
-C {sky130_fd_pr/pfet_g5v0d10v5.sym} 2120 -240 0 1 {name=M9
-L=0.8
-W=2
-nf=1
-mult=1
-ad="'int((nf+1)/2) * W/nf * 0.29'"
-pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
-as="'int((nf+2)/2) * W/nf * 0.29'"
-ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
-nrd="'0.29 / W'" nrs="'0.29 / W'"
-sa=0 sb=0 sd=0
-model=pfet_g5v0d10v5
-spiceprefix=X
-}
-C {sky130_fd_pr/pfet_g5v0d10v5.sym} 2120 -340 0 1 {name=M11
-L=0.8
-W=16
-nf=8
-mult=1
-ad="'int((nf+1)/2) * W/nf * 0.29'"
-pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
-as="'int((nf+2)/2) * W/nf * 0.29'"
-ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
-nrd="'0.29 / W'" nrs="'0.29 / W'"
-sa=0 sb=0 sd=0
-model=pfet_g5v0d10v5
-spiceprefix=X
-}
-C {sky130_fd_pr/pfet_g5v0d10v5.sym} 2670 -340 0 0 {name=M12
-L=0.8
-W=2
-nf=1
-mult=1
-ad="'int((nf+1)/2) * W/nf * 0.29'"
-pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
-as="'int((nf+2)/2) * W/nf * 0.29'"
-ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
-nrd="'0.29 / W'" nrs="'0.29 / W'"
-sa=0 sb=0 sd=0
-model=pfet_g5v0d10v5
-spiceprefix=X
-}
-C {sky130_fd_pr/pfet_g5v0d10v5.sym} 2670 -240 0 0 {name=M13
-L=0.8
-W=2
-nf=1
-mult=1
-ad="'int((nf+1)/2) * W/nf * 0.29'"
-pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
-as="'int((nf+2)/2) * W/nf * 0.29'"
-ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
-nrd="'0.29 / W'" nrs="'0.29 / W'"
-sa=0 sb=0 sd=0
-model=pfet_g5v0d10v5
-spiceprefix=X
-}
-C {sky130_fd_pr/res_xhigh_po_0p69.sym} 1810 30 0 1 {name=R3
-L=25
-model=res_xhigh_po_0p69
-spiceprefix=X
-mult=2}
-C {sky130_stdcells/buf_8.sym} 3170 -130 0 0 {name=x2 VGND=vss VNB=vss VPB=vdd3v3 VPWR=vdd3v3 prefix=sky130_fd_sc_hvl__ }
-C {sky130_stdcells/buf_8.sym} 3170 -40 0 0 {name=x3 VGND=vss VNB=vss VPB=vdd1v8 VPWR=vdd1v8 prefix=sky130_fd_sc_hvl__ }
-C {sky130_stdcells/inv_8.sym} 3170 60 0 0 {name=x4 VGND=vss VNB=vss VPB=vdd1v8 VPWR=vdd1v8 prefix=sky130_fd_sc_hvl__ }
-C {sky130_stdcells/buf_1.sym} 3020 -130 0 0 {name=x5 VGND=vss VNB=vss VPB=vdd3v3 VPWR=vdd3v3 prefix=sky130_fd_sc_hvl__schmitt }
-C {devices/iopin.sym} 2840 -400 0 0 {name=p1 lab=vdd3v3}
-C {devices/iopin.sym} 2870 110 0 0 {name=p2 lab=vss}
-C {devices/opin.sym} 3300 -130 0 0 {name=p3 lab=porb_h}
-C {devices/opin.sym} 3300 -40 0 0 {name=p4 lab=porb_l}
-C {devices/opin.sym} 3300 60 0 0 {name=p5 lab=por_l}
-C {devices/iopin.sym} 2840 -330 0 0 {name=p6 lab=vdd1v8}
diff --git a/xschem/example_por.sym b/xschem/example_por.sym
deleted file mode 100644
index e3875f5..0000000
--- a/xschem/example_por.sym
+++ /dev/null
@@ -1,33 +0,0 @@
-v {xschem version=2.9.9 file_version=1.2 }
-G {}
-K {type=subcircuit
-format="@name @pinlist @symname"
-template="name=x1"
-}
-V {}
-S {}
-E {}
-L 4 -130 -60 130 -60 {}
-L 4 -130 60 130 60 {}
-L 4 -130 -60 -130 60 {}
-L 4 130 -60 130 60 {}
-L 4 130 -30 150 -30 {}
-L 4 130 0 150 0 {}
-L 4 130 30 150 30 {}
-L 7 -30 -80 -30 -60 {}
-L 7 30 -80 30 -60 {}
-L 7 0 60 0 80 {}
-B 5 -32.5 -82.5 -27.5 -77.5 {name=vdd3v3 dir=inout }
-B 5 27.5 -82.5 32.5 -77.5 {name=vdd1v8 dir=inout }
-B 5 147.5 -32.5 152.5 -27.5 {name=porb_h dir=out }
-B 5 147.5 -2.5 152.5 2.5 {name=porb_l dir=out }
-B 5 147.5 27.5 152.5 32.5 {name=por_l dir=out }
-B 5 -2.5 77.5 2.5 82.5 {name=vss dir=inout }
-T {@symname} -47.5 -6 0 0 0.3 0.3 {}
-T {@name} -25 18 0 0 0.2 0.2 {}
-T {vdd3v3} -15 -54 0 1 0.2 0.2 {}
-T {vdd1v8} 55 -54 0 1 0.2 0.2 {}
-T {porb_h} 125 -34 0 1 0.2 0.2 {}
-T {porb_l} 125 -4 0 1 0.2 0.2 {}
-T {por_l} 125 26 0 1 0.2 0.2 {}
-T {vss} 5 46 0 1 0.2 0.2 {}
diff --git a/xschem/example_por_tb.sch b/xschem/example_por_tb.sch
deleted file mode 100644
index a24d814..0000000
--- a/xschem/example_por_tb.sch
+++ /dev/null
@@ -1,45 +0,0 @@
-v {xschem version=2.9.9 file_version=1.2 }
-G {}
-K {}
-V {}
-S {}
-E {}
-T {Testbench for simple POR} -350 -240 0 0 0.6 0.6 {}
-N -280 60 -10 60 { lab=GND}
-N -540 0 -540 60 { lab=GND}
-N -330 0 -330 60 { lab=GND}
-N -330 -100 -330 -60 { lab=vdd3v3}
-N -330 -110 -330 -100 { lab=vdd3v3}
-N -210 -110 -40 -110 { lab=vdd3v3}
-N -40 -110 -40 -100 { lab=vdd3v3}
-N -540 -130 -540 -60 { lab=vdd1v8}
-N -280 -130 20 -130 { lab=vdd1v8}
-N 20 -130 20 -100 { lab=vdd1v8}
-N 140 -50 180 -50 { lab=porb_h}
-N 140 -20 180 -20 { lab=porb_l}
-N 140 10 180 10 { lab=por_l}
-N -340 -110 -330 -110 { lab=vdd3v3}
-N -500 -130 -490 -130 { lab=vdd1v8}
-N -540 -130 -500 -130 { lab=vdd1v8}
-N -560 -130 -540 -130 { lab=vdd1v8}
-N -540 60 -490 60 { lab=GND}
-N -490 -130 -280 -130 { lab=vdd1v8}
-N -490 60 -330 60 { lab=GND}
-N -330 60 -280 60 { lab=GND}
-N -330 -110 -210 -110 { lab=vdd3v3}
-C {example_por.sym} -10 -20 0 0 {name=x1}
-C {devices/gnd.sym} -100 60 0 0 {name=l1 lab=GND}
-C {devices/vsource.sym} -330 -30 0 0 {name=V1 value="PWL(0.0 0 100u 0 5m 3.3)"}
-C {devices/vsource.sym} -540 -30 0 0 {name=V2 value="PWL(0.0 0 300u 0 5.3m 1.8)"}
-C {devices/opin.sym} -340 -110 0 1 {name=p1 lab=vdd3v3}
-C {devices/opin.sym} -560 -130 0 1 {name=p2 lab=vdd1v8}
-C {devices/opin.sym} 180 -50 0 0 {name=p3 lab=porb_h}
-C {devices/opin.sym} 180 -20 0 0 {name=p4 lab=porb_l}
-C {devices/opin.sym} 180 10 0 0 {name=p5 lab=por_l}
-C {devices/code.sym} -470 140 0 0 {name=TT_MODELS only_toplevel=false
-format="tcleval(@value )" value=".lib \\\\$::SKYWATER_MODELS\\\\/sky130.lib.spice tt
-.include \\\\$::PDKPATH\\\\/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice"}
-C {devices/code_shown.sym} -320 160 0 0 {name=s2 only_toplevel=false value=".control
-tran 1u 20m
-plot V(vdd3v3) V(vdd1v8) V(porb_h) V(porb_l) V(por_l)
-.endc"}
diff --git a/xschem/example_por_tb.spice b/xschem/example_por_tb.spice
deleted file mode 100644
index fa82f74..0000000
--- a/xschem/example_por_tb.spice
+++ /dev/null
@@ -1,78 +0,0 @@
-**.subckt example_por_tb vdd3v3 vdd1v8 porb_h porb_l por_l
-*.opin vdd3v3
-*.opin vdd1v8
-*.opin porb_h
-*.opin porb_l
-*.opin por_l
-x1 vdd3v3 vdd1v8 porb_h porb_l por_l GND example_por
-V1 vdd3v3 GND PWL(0.0 0 100u 0 5m 3.3)
-V2 vdd1v8 GND PWL(0.0 0 300u 0 5.3m 1.8)
-**** begin user architecture code
-.lib /usr/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
-.include /usr/share/pdk/sky130A/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice
-
-.control
-tran 1u 20m
-plot V(vdd3v3) V(vdd1v8) V(porb_h) V(porb_l) V(por_l)
-.endc
-
-**** end user architecture code
-**.ends
-
-* expanding symbol: example_por.sym # of pins=6
-* sym_path: /home/tim/gits/caravel_user_project_analog/xschem/example_por.sym
-* sch_path: /home/tim/gits/caravel_user_project_analog/xschem/example_por.sch
-.subckt example_por vdd3v3 vdd1v8 porb_h porb_l por_l vss
-*.iopin vdd3v3
-*.iopin vss
-*.opin porb_h
-*.opin porb_l
-*.opin por_l
-*.iopin vdd1v8
-XC1 net9 vss sky130_fd_pr__cap_mim_m3_1 W=30 L=30 MF=1 m=1
-XC2 vss net9 sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=1 m=1
-XM1 net3 net7 net5 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
-+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
-+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
-XM2 net2 net3 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
-+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
-+ sa=0 sb=0 sd=0 mult=1 m=1
-XR1 net4 vdd3v3 vss sky130_fd_pr__res_xhigh_po_0p69 L=500 mult=1 m=1
-XM4 net5 net6 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
-+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
-+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
-XM5 net3 net3 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
-+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
-+ sa=0 sb=0 sd=0 mult=1 m=1
-XR2 vss net4 vss sky130_fd_pr__res_xhigh_po_0p69 L=150 mult=1 m=1
-XM7 net2 net2 net1 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
-+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
-+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
-XM8 net1 net1 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29'
-+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
-+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
-XM10 net7 net4 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
-+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
-+ sa=0 sb=0 sd=0 mult=1 m=1
-XM9 net7 net7 net6 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
-+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
-+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
-XM11 net6 net6 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=16 nf=8 ad='int((nf+1)/2) * W/nf * 0.29'
-+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
-+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
-XM12 net8 net1 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
-+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
-+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
-XM13 net9 net2 net8 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
-+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
-+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
-XR3 vss vss vss sky130_fd_pr__res_xhigh_po_0p69 L=25 mult=2 m=2
-x2 net10 vss vss vdd3v3 vdd3v3 porb_h sky130_fd_sc_hvl__buf_8
-x3 net10 vss vss vdd1v8 vdd1v8 porb_l sky130_fd_sc_hvl__buf_8
-x4 net10 vss vss vdd1v8 vdd1v8 por_l sky130_fd_sc_hvl__inv_8
-x5 net9 vss vss vdd3v3 vdd3v3 net10 sky130_fd_sc_hvl__schmittbuf_1
-.ends
-
-.GLOBAL GND
-** flattened .save nodes
-.end
diff --git a/xschem/example_por_tb.spice.orig b/xschem/example_por_tb.spice.orig
deleted file mode 100644
index 069c74d..0000000
--- a/xschem/example_por_tb.spice.orig
+++ /dev/null
@@ -1,88 +0,0 @@
-**.subckt example_por_tb vdd3v3 vdd1v8 porb_h porb_l por_l
-.param mc_switch=0
-*.opin vdd3v3
-*.opin vdd1v8
-*.opin porb_h
-*.opin porb_l
-*.opin por_l
-x1 vdd3v3 vdd1v8 porb_h porb_l por_l GND example_por
-V1 vdd3v3 GND PWL(0.0 0 100u 0 5m 3.3)
-V2 vdd1v8 GND PWL(0.0 0 300u 0 5.3m 1.8)
-**** begin user architecture code
-
-.lib /usr/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
-
-
-.include /usr/share/pdk/sky130A/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice
-
-.control
-tran 1u 20m
-plot V(vdd3v3) V(vdd1v8) V(porb_h) V(porb_l) V(por_l)
-.endc
-
-**** end user architecture code
-**.ends
-
-* expanding symbol: example_por.sym # of pins=6
-* sym_path: /home/tim/gits/caravel_user_project_analog/xschem/example_por.sym
-* sch_path: /home/tim/gits/caravel_user_project_analog/xschem/example_por.sch
-.subckt example_por vdd3v3 vdd1v8 porb_h porb_l por_l vss
-*.iopin vdd3v3
-*.iopin vss
-*.opin porb_h
-*.opin porb_l
-*.opin por_l
-*.iopin vdd1v8
-XC1 net11 vss sky130_fd_pr__cap_mim_m3_1 W=30 L=30 MF=1 m=1
-XC2 net11 vss sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=1 m=1
-XM1 net5 net9 net7 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
-+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
-+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
-XM2 net1 net4 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
-+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
-+ sa=0 sb=0 sd=0 mult=1 m=1
-XR1 net6 vdd3v3 vss sky130_fd_pr__res_xhigh_po_0p69 W=0.69 L=500 mult=1 m=1
-XM3 net3 net5 net1 vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
-+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
-+ sa=0 sb=0 sd=0 mult=1 m=1
-XM4 net7 net8 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
-+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
-+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
-XM5 net4 net4 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
-+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
-+ sa=0 sb=0 sd=0 mult=1 m=1
-XM6 net5 net5 net4 vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
-+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
-+ sa=0 sb=0 sd=0 mult=1 m=1
-XR2 vss net6 vss sky130_fd_pr__res_xhigh_po_0p69 W=0.69 L=150 mult=1 m=1
-XM7 net3 net3 net2 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
-+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
-+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
-XM8 net2 net2 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29'
-+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
-+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
-XM10 net9 net6 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
-+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
-+ sa=0 sb=0 sd=0 mult=1 m=1
-XM9 net9 net9 net8 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
-+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
-+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
-XM11 net8 net8 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=16 nf=8 ad='int((nf+1)/2) * W/nf * 0.29'
-+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
-+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
-XM12 net10 net2 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
-+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
-+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
-XM13 net11 net3 net10 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
-+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
-+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
-XR3 vss vss vss sky130_fd_pr__res_xhigh_po_0p69 W=0.69 L=25 mult=2 m=2
-x2 net12 vss vss vdd3v3 vdd3v3 porb_h sky130_fd_sc_hvl__buf_8
-x3 net12 vss vss vdd1v8 vdd1v8 porb_l sky130_fd_sc_hvl__buf_8
-x4 net12 vss vss vdd1v8 vdd1v8 por_l sky130_fd_sc_hvl__inv_8
-x5 net11 vss vss vdd3v3 vdd3v3 net12 sky130_fd_sc_hvl__schmittbuf_1
-.ends
-
-.GLOBAL GND
-** flattened .save nodes
-.end
diff --git a/xschem/sar/comparator/comparator.sch b/xschem/sar/comparator/comparator.sch
new file mode 100644
index 0000000..36e407b
--- /dev/null
+++ b/xschem/sar/comparator/comparator.sch
@@ -0,0 +1,266 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 780 -100 810 -100 { lab=vss}
+N 660 -270 690 -270 { lab=vss}
+N 870 -270 900 -270 { lab=vss}
+N 900 -240 900 -180 { lab=diff}
+N 700 -100 740 -100 { lab=clk}
+N 660 -750 660 -670 { lab=vdd}
+N 660 -750 900 -750 { lab=vdd}
+N 900 -750 900 -670 { lab=vdd}
+N 620 -750 660 -750 { lab=vdd}
+N 900 -750 940 -750 { lab=vdd}
+N 450 -750 450 -670 { lab=vdd}
+N 450 -750 620 -750 { lab=vdd}
+N 940 -750 1070 -750 { lab=vdd}
+N 1070 -750 1100 -750 { lab=vdd}
+N 1100 -750 1100 -670 { lab=vdd}
+N 370 -640 410 -640 { lab=clk}
+N 1140 -640 1180 -640 { lab=clk}
+N 660 -430 660 -300 { lab=in}
+N 900 -430 900 -300 { lab=ip}
+N 700 -640 720 -640 { lab=outp}
+N 720 -640 720 -460 { lab=outp}
+N 700 -460 720 -460 { lab=outp}
+N 840 -460 860 -460 { lab=outn}
+N 840 -640 840 -460 { lab=outn}
+N 840 -640 860 -640 { lab=outn}
+N 600 -270 620 -270 { lab=vn}
+N 940 -270 960 -270 { lab=vp}
+N 900 -460 930 -460 { lab=vss}
+N 630 -460 660 -460 { lab=vss}
+N 1400 -750 1400 -670 { lab=vdd}
+N 1440 -640 1480 -640 { lab=clk}
+N 1100 -750 1400 -750 { lab=vdd}
+N 140 -750 140 -670 { lab=vdd}
+N 60 -640 100 -640 { lab=clk}
+N 140 -750 450 -750 { lab=vdd}
+N 780 -70 780 -40 { lab=vss}
+N 660 -240 660 -180 { lab=diff}
+N 660 -180 900 -180 { lab=diff}
+N 780 -180 780 -130 { lab=diff}
+N 630 -640 660 -640 { lab=vdd}
+N 450 -640 480 -640 { lab=vdd}
+N 140 -640 170 -640 { lab=vdd}
+N 900 -640 930 -640 { lab=vdd}
+N 1070 -640 1100 -640 { lab=vdd}
+N 1370 -640 1400 -640 { lab=vdd}
+N 110 -750 140 -750 { lab=vdd}
+N 660 -610 660 -490 { lab=outn}
+N 900 -610 900 -490 { lab=outp}
+N 380 -550 660 -550 { lab=outn}
+N 450 -610 450 -550 { lab=outn}
+N 900 -550 1170 -550 { lab=outp}
+N 1100 -610 1100 -550 { lab=outp}
+N 750 -510 810 -570 { lab=outp}
+N 720 -510 750 -510 { lab=outp}
+N 810 -570 900 -570 { lab=outp}
+N 750 -570 810 -510 { lab=outn}
+N 810 -510 840 -510 { lab=outn}
+N 660 -570 750 -570 { lab=outn}
+N 650 -40 780 -40 { lab=vss}
+N 1400 -610 1400 -360 { lab=ip}
+N 140 -610 140 -360 { lab=in}
+N 140 -360 660 -360 { lab=in}
+N 140 -360 140 -330 { lab=in}
+N 140 -170 140 -140 { lab=vss}
+N 20 -250 100 -250 { lab=trim[4:0]}
+N 900 -360 1400 -360 { lab=ip}
+N 1400 -360 1400 -330 { lab=ip}
+N 1400 -170 1400 -140 { lab=vss}
+N 1440 -250 1520 -250 { lab=trimb[4:0]}
+C {sky130_primitives/nfet_01v8.sym} 760 -100 0 0 {name=Mdiff
+L=0.3
+W=1
+nf=1
+mult=2
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_primitives/nfet_01v8.sym} 640 -270 0 0 {name=Minn
+L=0.3
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {devices/lab_wire.sym} 690 -270 0 0 {name=l48 sig_type=std_logic lab=vss}
+C {sky130_primitives/nfet_01v8.sym} 920 -270 0 1 {name=Minp
+L=0.3
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {devices/lab_wire.sym} 870 -270 0 1 {name=l49 sig_type=std_logic lab=vss}
+C {devices/lab_wire.sym} 730 -100 0 0 {name=l29 sig_type=std_logic lab=clk}
+C {sky130_primitives/pfet_01v8.sym} 880 -640 0 0 {name=Ml4
+L=0.3
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_primitives/pfet_01v8.sym} 680 -640 0 1 {name=Ml3
+L=0.3
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_primitives/pfet_01v8.sym} 1120 -640 0 1 {name=M3
+L=0.3
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_primitives/pfet_01v8.sym} 430 -640 0 0 {name=M2
+L=0.3
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {devices/lab_wire.sym} 400 -640 0 0 {name=l47 sig_type=std_logic lab=clk}
+C {devices/lab_wire.sym} 1180 -640 0 0 {name=l52 sig_type=std_logic lab=clk}
+C {sky130_primitives/nfet_01v8.sym} 680 -460 0 1 {name=Ml1
+L=0.3
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_primitives/nfet_01v8.sym} 880 -460 0 0 {name=Ml2
+L=0.3
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {devices/lab_wire.sym} 900 -460 0 1 {name=l55 sig_type=std_logic lab=vss}
+C {devices/lab_wire.sym} 630 -460 0 1 {name=l56 sig_type=std_logic lab=vss}
+C {devices/ipin.sym} 600 -270 0 0 {name=p1 lab=vn}
+C {devices/ipin.sym} 960 -270 2 0 {name=p2 lab=vp}
+C {devices/ipin.sym} 700 -100 0 0 {name=p3 lab=clk}
+C {devices/iopin.sym} 110 -750 2 0 {name=p4 lab=vdd}
+C {devices/iopin.sym} 650 -40 2 0 {name=p5 lab=vss}
+C {devices/opin.sym} 1170 -550 0 0 {name=p6 lab=outp}
+C {devices/opin.sym} 380 -550 2 0 {name=p7 lab=outn}
+C {sky130_primitives/pfet_01v8.sym} 1420 -640 0 1 {name=M4
+L=0.3
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {devices/lab_wire.sym} 1480 -640 0 0 {name=l1 sig_type=std_logic lab=clk}
+C {sky130_primitives/pfet_01v8.sym} 120 -640 0 0 {name=M1
+L=0.3
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {devices/lab_wire.sym} 90 -640 0 0 {name=l2 sig_type=std_logic lab=clk}
+C {devices/lab_wire.sym} 780 -180 0 1 {name=l3 sig_type=std_logic lab=diff}
+C {devices/lab_wire.sym} 620 -360 0 1 {name=l4 sig_type=std_logic lab=in}
+C {devices/lab_wire.sym} 920 -360 0 1 {name=l5 sig_type=std_logic lab=ip}
+C {devices/lab_wire.sym} 780 -100 0 1 {name=l6 sig_type=std_logic lab=vss}
+C {devices/lab_wire.sym} 660 -640 0 0 {name=l7 sig_type=std_logic lab=vdd}
+C {devices/lab_wire.sym} 450 -640 0 1 {name=l8 sig_type=std_logic lab=vdd}
+C {devices/lab_wire.sym} 140 -640 0 1 {name=l9 sig_type=std_logic lab=vdd}
+C {devices/lab_wire.sym} 900 -640 0 1 {name=l10 sig_type=std_logic lab=vdd}
+C {devices/lab_wire.sym} 1100 -640 0 0 {name=l11 sig_type=std_logic lab=vdd}
+C {devices/lab_wire.sym} 1400 -640 0 0 {name=l12 sig_type=std_logic lab=vdd}
+C {devices/ipin.sym} 110 -50 0 0 {name=p8 lab=trim[4:0]}
+C {sar/comparator/trim.sym} 140 -240 0 0 {name=x2}
+C {devices/lab_wire.sym} 140 -140 3 1 {name=l13 sig_type=std_logic lab=vss}
+C {devices/lab_wire.sym} 20 -250 0 1 {name=l14 sig_type=std_logic lab=trim[4:0]
+}
+C {sar/comparator/trim.sym} 1400 -240 0 1 {name=x3}
+C {devices/lab_wire.sym} 1400 -140 1 0 {name=l15 sig_type=std_logic lab=vss}
+C {devices/lab_wire.sym} 1520 -250 0 0 {name=l16 sig_type=std_logic lab=trimb[4:0]
+}
+C {devices/ipin.sym} 110 -10 0 0 {name=p9 lab=trimb[4:0]
+}
diff --git a/xschem/sar/comparator/comparator.sym b/xschem/sar/comparator/comparator.sym
new file mode 100644
index 0000000..254a0fa
--- /dev/null
+++ b/xschem/sar/comparator/comparator.sym
@@ -0,0 +1,41 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -80 -130 -60 -130 {}
+L 4 -80 -190 -60 -190 {}
+L 4 -60 -210 -60 -110 {}
+B 5 -32.5 -92.5 -27.5 -87.5 {name=vss dir=inout }
+B 5 -32.5 -232.5 -27.5 -227.5 {name=vdd dir=inout }
+B 5 -2.5 -112.5 2.5 -107.5 {name=clk dir=in }
+B 5 47.5 -182.5 52.5 -177.5 {name=outp dir=out}
+B 5 -82.5 -192.5 -77.5 -187.5 {name=vp dir=in }
+B 5 47.5 -142.5 52.5 -137.5 {name=outn dir=out }
+B 5 -82.5 -132.5 -77.5 -127.5 {name=vn dir=in }
+B 5 -2.5 -212.5 2.5 -207.5 {name=trim[4:0] dir=in }
+B 5 17.5 -202.5 22.5 -197.5 {name=trimb[4:0] dir=in }
+P 4 5 -60 -210 -60 -90 60 -160 -60 -230 -60 -210 {}
+P 4 2 -30 -90 -30 -107 {}
+P 4 2 -30 -213 -30 -230 {}
+P 4 2 -0 -110 0 -125 {}
+P 4 2 -0 -209 0 -195 {}
+P 4 4 -34 -148 -17 -148 -17 -174 0 -174 {}
+P 4 2 50 -180 26 -180 {}
+P 4 2 50 -140 26 -140 {}
+P 4 2 20 -200 20 -183.5 {}
+T {@symname} 13 -126 0 0 0.2 0.2 {}
+T {@name} 13 -113 0 0 0.2 0.2 {}
+T {clk} -8 -141 0 0 0.2 0.2 {}
+T {outp} 34 -175 0 1 0.2 0.2 {}
+T {vp} -58 -196 0 0 0.2 0.2 {}
+T {outn} 34 -157 0 1 0.2 0.2 {}
+T {vn} -58 -136 0 0 0.2 0.2 {}
+T {trim} -26 -197 0 0 0.2 0.2 {}
+T {vdd} -49 -213 0 0 0.2 0.2 {}
+T {vss} -41 -121 0 0 0.2 0.2 {}
+T {trimb} -9 -186 0 0 0.2 0.2 {}
diff --git a/xschem/sar/comparator/trim.sch b/xschem/sar/comparator/trim.sch
new file mode 100644
index 0000000..e6d4baa
--- /dev/null
+++ b/xschem/sar/comparator/trim.sch
@@ -0,0 +1,148 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 440 -630 440 -590 { lab=n4}
+N 440 -560 470 -560 { lab=vss}
+N 440 -710 440 -690 { lab=drain}
+N 360 -560 400 -560 { lab=d[4]}
+N 440 -530 440 -500 { lab=vss}
+N 630 -630 630 -590 { lab=n3}
+N 630 -560 660 -560 { lab=vss}
+N 630 -710 630 -690 { lab=drain}
+N 550 -560 590 -560 { lab=d[3]}
+N 630 -530 630 -500 { lab=vss}
+N 820 -500 1010 -500 { lab=vss}
+N 820 -630 820 -590 { lab=n2}
+N 820 -560 850 -560 { lab=vss}
+N 820 -710 820 -690 { lab=drain}
+N 740 -560 780 -560 { lab=d[2]}
+N 820 -530 820 -500 { lab=vss}
+N 630 -500 820 -500 { lab=vss}
+N 440 -500 630 -500 { lab=vss}
+N 1010 -500 1200 -500 { lab=vss}
+N 1010 -630 1010 -590 { lab=n1}
+N 1010 -710 1010 -690 { lab=drain}
+N 930 -560 970 -560 { lab=d[1]}
+N 1010 -530 1010 -500 { lab=vss}
+N 1200 -630 1200 -590 { lab=n0}
+N 1200 -560 1230 -560 { lab=vss}
+N 1200 -710 1200 -690 { lab=drain}
+N 1120 -560 1160 -560 { lab=d[0]}
+N 1200 -530 1200 -500 { lab=vss}
+N 1230 -560 1230 -500 { lab=vss}
+N 1200 -500 1230 -500 { lab=vss}
+N 1040 -560 1040 -500 { lab=vss}
+N 850 -560 850 -500 { lab=vss}
+N 660 -560 660 -500 { lab=vss}
+N 470 -560 470 -500 { lab=vss}
+N 440 -710 1310 -710 { lab=drain}
+N 1010 -560 1040 -560 { lab=vss}
+N 310 -500 440 -500 { lab=vss}
+C {devices/lab_wire.sym} 400 -560 0 0 {name=l34 sig_type=std_logic lab=d[4]
+}
+C {devices/iopin.sym} 310 -500 2 0 {name=p5 lab=vss}
+C {devices/ipin.sym} 310 -560 0 0 {name=p8 lab=d[4:0]
+}
+C {xschem_library/devices/opin.sym} 1310 -710 0 0 {name=p1 lab=drain
+}
+C {sky130_primitives/nfet_01v8_lvt.sym} 420 -560 0 0 {name=M4[7:0]
+L=0.3
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8_lvt
+spiceprefix=X
+}
+C {devices/lab_wire.sym} 590 -560 0 0 {name=l1 sig_type=std_logic lab=d[3]
+}
+C {sky130_primitives/nfet_01v8_lvt.sym} 610 -560 0 0 {name=M3[3:0]
+L=0.3
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8_lvt
+spiceprefix=X
+}
+C {devices/lab_wire.sym} 780 -560 0 0 {name=l2 sig_type=std_logic lab=d[2]
+}
+C {sky130_primitives/nfet_01v8_lvt.sym} 800 -560 0 0 {name=M2[1:0]
+L=0.3
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8_lvt
+spiceprefix=X
+}
+C {devices/lab_wire.sym} 970 -560 0 0 {name=l3 sig_type=std_logic lab=d[1]
+}
+C {sky130_primitives/nfet_01v8_lvt.sym} 990 -560 0 0 {name=M1
+L=0.3
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8_lvt
+spiceprefix=X
+}
+C {devices/lab_wire.sym} 1160 -560 0 0 {name=l4 sig_type=std_logic lab=d[0]
+}
+C {sky130_primitives/nfet_01v8_lvt.sym} 1180 -560 0 0 {name=M0
+L=0.3
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8_lvt
+spiceprefix=X
+}
+C {devices/lab_wire.sym} 440 -600 0 0 {name=l5 sig_type=std_logic lab=n4
+}
+C {devices/lab_wire.sym} 630 -600 0 0 {name=l6 sig_type=std_logic lab=n3
+}
+C {devices/lab_wire.sym} 820 -600 0 0 {name=l7 sig_type=std_logic lab=n2
+}
+C {devices/lab_wire.sym} 1010 -600 0 0 {name=l8 sig_type=std_logic lab=n1
+}
+C {devices/lab_wire.sym} 1200 -600 0 0 {name=l9 sig_type=std_logic lab=n0
+}
+C {sar/comparator/trimcap.sym} 420 -620 0 0 {name=x4[7:0]
+}
+C {sar/comparator/trimcap.sym} 610 -620 0 0 {name=x3[3:0]
+}
+C {sar/comparator/trimcap.sym} 800 -620 0 0 {name=x2[1:0]
+}
+C {sar/comparator/trimcap.sym} 990 -620 0 0 {name=x1
+}
+C {sar/comparator/trimcap.sym} 1180 -620 0 0 {name=x0
+}
diff --git a/xschem/sar/comparator/trim.sym b/xschem/sar/comparator/trim.sym
new file mode 100644
index 0000000..b565c62
--- /dev/null
+++ b/xschem/sar/comparator/trim.sym
@@ -0,0 +1,23 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 0 -90 0 -70 {}
+L 4 -40 -10 -20 -10 {}
+L 4 0 50 0 70 {}
+B 5 -2.5 -92.5 2.5 -87.5 {name=drain dir=out }
+B 5 -42.5 -12.5 -37.5 -7.5 {name=d[4:0] dir=in }
+B 5 -2.5 67.5 2.5 72.5 {name=vss dir=inout }
+A 4 0 26 31.01612483854165 69.22774531795417 41.54450936409165 {}
+P 4 2 -11 -15 11 -15 {}
+P 4 2 -0 -5 -0 50 {}
+P 4 2 0 -70 0 -15 {}
+P 4 5 -12 2 13 -23 8 -23 13 -18 13 -23 {}
+T {@symname} 4 -76 0 0 0.3 0.3 {}
+T {@name} 5 -52 0 0 0.2 0.2 {}
+T {d[4:0]} -45 -34 0 0 0.2 0.2 {}
diff --git a/xschem/sar/comparator/trim_pex.sp b/xschem/sar/comparator/trim_pex.sp
new file mode 100644
index 0000000..18a7355
--- /dev/null
+++ b/xschem/sar/comparator/trim_pex.sp
@@ -0,0 +1,37 @@
+* pex extracted trim circuit
+
+.subckt trim drain d_4 d_3 d_2 d_1 d_0 vss
+X0 n4 d_4 vss vss sky130_fd_pr__nfet_01v8_lvt ad=1.16e+12p pd=1.032e+07u as=2.61e+12p ps=2.322e+07u w=1e+06u l=300000u
+X2 n4 d_4 vss vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=300000u
+X5 vss d_4 n4 vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=300000u
+X6 vss d_4 n4 vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=300000u
+X7 vss d_4 n4 vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=300000u
+X10 vss d_4 n4 vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=300000u
+X12 n4 d_4 vss vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=300000u
+X14 n4 d_4 vss vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=300000u
+
+X4 n3 d_3 vss vss sky130_fd_pr__nfet_01v8_lvt ad=8.7e+11p pd=7.74e+06u as=0p ps=0u w=1e+06u l=300000u
+X8 vss d_3 n3 vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=300000u
+X11 vss d_3 n3 vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=300000u
+X15 n3 d_3 vss vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=300000u
+
+X1 n2 d_2 vss vss sky130_fd_pr__nfet_01v8_lvt ad=5.8e+11p pd=5.16e+06u as=0p ps=0u w=1e+06u l=300000u
+X9 vss d_2 n2 vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=300000u
+
+X13 n1 d_1 vss vss sky130_fd_pr__nfet_01v8_lvt ad=2.9e+11p pd=2.58e+06u as=0p ps=0u w=1e+06u l=300000u
+
+X3 vss d_0 n0 vss sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=2.9e+11p ps=2.58e+06u w=1e+06u l=300000u
+
+C6 drain n4 29.02fF
+C3 drain n3 14.55fF
+C2 drain n2 7.38fF
+C4 drain n1 3.69fF
+C5 drain n0 3.69fF
+
+C1 n4 n3 6.78fF
+C0 n4 n2 3.57fF
+C7 n3 n2 2.16fF
+
+C8 drain vss 13.51fF
+.ends
+
diff --git a/xschem/sar/comparator/trimcap.sch b/xschem/sar/comparator/trimcap.sch
new file mode 100644
index 0000000..1cc0ff3
--- /dev/null
+++ b/xschem/sar/comparator/trimcap.sch
@@ -0,0 +1,15 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+T {Custom made MOM cap} 160 -120 0 0 0.4 0.4 {}
+N 70 -170 70 -140 { lab=cp}
+N 70 -170 80 -170 { lab=cp}
+N 70 -80 70 -50 { lab=cn}
+N 70 -50 80 -50 { lab=cn}
+C {devices/iopin.sym} 80 -170 0 0 {name=p1 lab=cp}
+C {devices/iopin.sym} 80 -50 0 0 {name=p2 lab=cn}
+C {xschem_library/devices/capa.sym} 70 -110 0 0 {name=c0 m=1 value=2f
+}
diff --git a/xschem/sar/comparator/trimcap.sym b/xschem/sar/comparator/trimcap.sym
new file mode 100644
index 0000000..3a8163e
--- /dev/null
+++ b/xschem/sar/comparator/trimcap.sym
@@ -0,0 +1,17 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 20 -35 20 -10 {}
+L 4 20 -70 20 -45 {}
+L 4 10 -45 30 -45 {}
+B 5 17.5 -72.5 22.5 -67.5 {name=cp dir=inout }
+B 5 17.5 -12.5 22.5 -7.5 {name=cn dir=inout }
+A 4 20 -13.75 21.25 61.92751306414704 56.14497387170592 {}
+T {@symname} 30.5 -66 0 0 0.2 0.2 {}
+T {@name} 35 -22 0 0 0.2 0.2 {}
diff --git a/xschem/sar/control/cmos_cells_digital.sp b/xschem/sar/control/cmos_cells_digital.sp
new file mode 100644
index 0000000..2353e4c
--- /dev/null
+++ b/xschem/sar/control/cmos_cells_digital.sp
@@ -0,0 +1,34 @@
+.SUBCKT BUF A Y
+.model buffer d_buffer
+Abuf A Y buffer
+.ENDS NOT
+
+.SUBCKT NOT A Y
+.model not d_inverter
+Anot A Y not
+.ENDS NOT
+
+.SUBCKT NAND A B Y
+.model nand d_nand
+Anand [A B] Y nand
+.ENDS NAND
+
+.SUBCKT NOR A B Y
+.model nor d_nor
+Anor [A B] Y nor
+.ENDS NOR
+
+.SUBCKT DLATCH E D Q
+.model latch d_latch
+Alatch D E null null Q nQ latch
+.ENDS DLATCH
+
+.SUBCKT DFF C D Q
+.model dff d_dff
+Adff D C null null Q null dff
+.ENDS DFF
+
+.SUBCKT DFFSR C D Q S R
+.model dff d_dff
+Adsrff D C S R Q null dff
+.ENDS DFF
diff --git a/xschem/sar/control/sar_logic.sp b/xschem/sar/control/sar_logic.sp
new file mode 100644
index 0000000..64c03ed
--- /dev/null
+++ b/xschem/sar/control/sar_logic.sp
@@ -0,0 +1,343 @@
+* SPICE netlist generated by Yosys 0.8 (git sha1 5706e90)
+
+.SUBCKT sar_logic clk rstn en comp cal valid result.0 result.1 result.2 result.3 result.4 result.5 result.6 result.7 sample ctlp.0 ctlp.1 ctlp.2 ctlp.3 ctlp.4 ctlp.5 ctlp.6 ctlp.7 ctln.0 ctln.1 ctln.2 ctln.3 ctln.4 ctln.5 ctln.6 ctln.7 trim.0 trim.1 trim.2 trim.3 trim.4 trimb.0 trimb.1 trimb.2 trimb.3 trimb.4 clkc
+X0 rstn 1 NOT
+X1 en 2 NOT
+X2 cal_count.2 3 NOT
+X3 cal_count.3 4 NOT
+X4 en_co_clk 5 NOT
+X5 trim_mask.0 6 NOT
+X6 trim_val.4 7 NOT
+X7 state.0 8 NOT
+X8 state.1 9 NOT
+X9 state.2 10 NOT
+X10 result.0 11 NOT
+X11 result.1 12 NOT
+X12 result.2 13 NOT
+X13 result.3 14 NOT
+X14 result.4 15 NOT
+X15 result.5 16 NOT
+X16 result.6 17 NOT
+X17 result.7 18 NOT
+X18 cal_itt.1 19 NOT
+X19 cal_itt.2 20 NOT
+X20 cal_itt.3 21 NOT
+X21 state.0 state.1 22 NOR
+X22 8 9 23 NAND
+X23 state.2 22 24 NAND
+X24 24 valid NOT
+X25 state.0 state.2 25 NOR
+X26 25 26 NOT
+X27 state.1 25 27 NAND
+X28 27 28 NOT
+X29 8 state.1 29 NOR
+X30 state.0 9 30 NAND
+X31 10 30 31 NOR
+X32 state.2 29 32 NAND
+X33 27 32 sample NAND
+X34 cal_itt.0 cal_itt.1 33 NAND
+X35 33 34 NOT
+X36 20 33 35 NOR
+X37 cal_itt.2 34 36 NAND
+X38 cal_itt.3 36 37 NOR
+X39 21 35 38 NAND
+X40 6 38 39 NOR
+X41 trim_mask.0 37 40 NAND
+X42 cal_itt.0 40 41 NAND
+X43 31 41 42 NAND
+X44 en state.2 43 NOR
+X45 43 44 NOT
+X46 30 43 45 NOR
+X47 29 44 46 NAND
+X48 cal_itt.0 46 47 NAND
+X49 42 47 48.0 NAND
+X50 cal_itt.0 cal_itt.1 49 NOR
+X51 19 45 50 NOR
+X52 33 39 51 NOR
+X53 32 51 52 NOR
+X54 50 52 53 NOR
+X55 49 53 48.1 NOR
+X56 20 33 54 NAND
+X57 36 54 55 NAND
+X58 40 55 56 NAND
+X59 31 56 57 NAND
+X60 cal_itt.2 46 58 NAND
+X61 57 58 48.2 NAND
+X62 8 state.2 59 NOR
+X63 59 60 NOT
+X64 state.2 30 61 NOR
+X65 61 62 NOT
+X66 2 62 63 NOR
+X67 en 61 64 NAND
+X68 31 35 65 NAND
+X69 cal_itt.3 65 66 NAND
+X70 63 66 48.3 NOR
+X71 32 37 67 NOR
+X72 31 38 68 NAND
+X73 cal_count.0 68 69 NAND
+X74 cal_count.0 state.2 70 NAND
+X75 45 70 71 NAND
+X76 69 71 72.0 NAND
+X77 cal_count.1 45 73 NOR
+X78 cal_count.0 cal_count.1 74 NAND
+X79 comp 74 75 NAND
+X80 cal_count.0 cal_count.1 76 NOR
+X81 76 77 NOT
+X82 comp 74 78 NOR
+X83 78 79 NOT
+X84 75 77 80 NAND
+X85 78 80 81 NOR
+X86 comp 76 82 NAND
+X87 67 82 83 NAND
+X88 81 83 84 NOR
+X89 73 84 72.1 NOR
+X90 cal_count.2 45 85 NOR
+X91 79 82 86 NAND
+X92 3 86 87 NAND
+X93 67 87 88 NAND
+X94 3 86 89 NOR
+X95 88 89 90 NOR
+X96 85 90 72.2 NOR
+X97 cal_count.3 46 91 NAND
+X98 cal_count.2 78 92 NAND
+X99 92 93 NOT
+X100 cal_count.2 82 94 NOR
+X101 94 95 NOT
+X102 93 94 96 NOR
+X103 92 95 97 NAND
+X104 4 97 98 NAND
+X105 cal_count.3 96 99 NAND
+X106 98 99 100 NAND
+X107 67 100 101 NAND
+X108 91 101 72.3 NAND
+X109 5 64 102 NAND
+X110 31 40 103 NAND
+X111 9 60 104 NOR
+X112 state.1 59 105 NAND
+X113 mask.0 105 106 NOR
+X114 61 106 107 NOR
+X115 103 107 108 NAND
+X116 102 108 109 NAND
+X117 5 29 110 NOR
+X118 60 110 111 NAND
+X119 109 111 112 NAND
+X120 calibrate 27 113 NOR
+X121 26 113 114 NOR
+X122 32 38 115 NOR
+X123 31 37 116 NAND
+X124 trim_mask.0 115 117 NAND
+X125 4 117 118 NOR
+X126 trim_val.0 118 119 NOR
+X127 114 119 120.0 NOR
+X128 trim_mask.1 115 121 NAND
+X129 4 121 122 NOR
+X130 trim_val.1 122 123 NOR
+X131 114 123 120.1 NOR
+X132 trim_mask.2 115 124 NAND
+X133 4 124 125 NOR
+X134 trim_val.2 125 126 NOR
+X135 114 126 120.2 NOR
+X136 trim_mask.3 115 127 NAND
+X137 4 127 128 NOR
+X138 trim_val.3 128 129 NOR
+X139 114 129 120.3 NOR
+X140 state.2 23 130 NOR
+X141 7 114 131 NOR
+X142 130 131 132 NOR
+X143 trim_mask.4 115 133 NAND
+X144 133 134 NOT
+X145 cal_count.3 134 135 NAND
+X146 132 135 120.4 NAND
+X147 calibrate 28 136 NAND
+X148 32 136 137 NAND
+X149 68 137 138 NAND
+X150 trim_mask.0 138 139 NAND
+X151 121 139 140.0 NAND
+X152 trim_mask.1 138 141 NAND
+X153 124 141 140.1 NAND
+X154 trim_mask.2 138 142 NAND
+X155 127 142 140.2 NAND
+X156 trim_mask.3 138 143 NAND
+X157 133 143 140.3 NAND
+X158 trim_mask.4 116 144 NAND
+X159 136 144 140.4 NAND
+X160 mask.1 104 145 NAND
+X161 29 43 146 NAND
+X162 59 146 147 NAND
+X163 mask.0 147 148 NAND
+X164 145 148 149.0 NAND
+X165 mask.2 104 150 NAND
+X166 mask.1 147 151 NAND
+X167 150 151 149.1 NAND
+X168 mask.3 104 152 NAND
+X169 mask.2 147 153 NAND
+X170 152 153 149.2 NAND
+X171 mask.4 104 154 NAND
+X172 mask.3 147 155 NAND
+X173 154 155 149.3 NAND
+X174 mask.5 104 156 NAND
+X175 mask.4 147 157 NAND
+X176 156 157 149.4 NAND
+X177 mask.6 104 158 NAND
+X178 mask.5 147 159 NAND
+X179 158 159 149.5 NAND
+X180 mask.7 104 160 NAND
+X181 mask.6 147 161 NAND
+X182 160 161 149.6 NAND
+X183 mask.7 63 162 NOR
+X184 104 162 149.7 NOR
+X185 23 27 163 NAND
+X186 state.1 state.2 164 NAND
+X187 164 165 NOT
+X188 103 164 166 NAND
+X189 state.0 166 167 NAND
+X190 trim_mask.0 116 168 NOR
+X191 106 163 169 NOR
+X192 146 169 170 NAND
+X193 168 170 171 NOR
+X194 167 171 172.0 NAND
+X195 63 106 173 NOR
+X196 113 165 174 NOR
+X197 173 174 172.1 NAND
+X198 mask.0 104 175 NAND
+X199 137 165 176 NOR
+X200 175 176 172.2 NAND
+X201 cal 63 177 NAND
+X202 45 103 178 NAND
+X203 calibrate 178 179 NAND
+X204 177 179 180 NAND
+X205 comp 104 181 NAND
+X206 11 181 182 NAND
+X207 mask.0 result.0 ctln.0 NOR
+X208 ctln.0 ctlp.0 NOT
+X209 182 ctlp.0 183 NAND
+X210 63 183 184.0 NOR
+X211 12 181 185 NAND
+X212 mask.1 result.1 ctln.1 NOR
+X213 ctln.1 ctlp.1 NOT
+X214 185 ctlp.1 186 NAND
+X215 63 186 184.1 NOR
+X216 13 181 187 NAND
+X217 mask.2 result.2 ctln.2 NOR
+X218 ctln.2 ctlp.2 NOT
+X219 187 ctlp.2 188 NAND
+X220 63 188 184.2 NOR
+X221 14 181 189 NAND
+X222 mask.3 result.3 ctln.3 NOR
+X223 ctln.3 ctlp.3 NOT
+X224 189 ctlp.3 190 NAND
+X225 63 190 184.3 NOR
+X226 15 181 191 NAND
+X227 mask.4 result.4 ctln.4 NOR
+X228 ctln.4 ctlp.4 NOT
+X229 191 ctlp.4 192 NAND
+X230 63 192 184.4 NOR
+X231 16 181 193 NAND
+X232 mask.5 result.5 ctln.5 NOR
+X233 ctln.5 ctlp.5 NOT
+X234 193 ctlp.5 194 NAND
+X235 63 194 184.5 NOR
+X236 17 181 195 NAND
+X237 mask.6 result.6 ctln.6 NOR
+X238 ctln.6 ctlp.6 NOT
+X239 195 ctlp.6 196 NAND
+X240 63 196 184.6 NOR
+X241 18 181 197 NAND
+X242 mask.7 result.7 ctln.7 NOR
+X243 ctln.7 ctlp.7 NOT
+X244 197 ctlp.7 198 NAND
+X245 63 198 184.7 NOR
+X246 trim_mask.0 trim_val.0 trimb.0 NOR
+X247 trimb.0 trim.0 NOT
+X248 trim_val.1 trim_mask.1 trimb.1 NOR
+X249 trimb.1 trim.1 NOT
+X250 trim_val.2 trim_mask.2 trimb.2 NOR
+X251 trimb.2 trim.2 NOT
+X252 trim_val.3 trim_mask.3 trimb.3 NOR
+X253 trimb.3 trim.3 NOT
+X254 trim_val.4 trim_mask.4 trimb.4 NOR
+X255 trimb.4 trim.4 NOT
+X256 5 clk clkc NOR
+X257 rstn 199 NOT
+X258 rstn 200 NOT
+X259 rstn 201 NOT
+X260 rstn 202 NOT
+X261 rstn 203 NOT
+X262 rstn 204 NOT
+X263 rstn 205 NOT
+X264 rstn 206 NOT
+X265 rstn 207 NOT
+X266 rstn 208 NOT
+X267 rstn 209 NOT
+X268 rstn 210 NOT
+X269 rstn 211 NOT
+X270 rstn 212 NOT
+X271 rstn 213 NOT
+X272 rstn 214 NOT
+X273 rstn 215 NOT
+X274 rstn 216 NOT
+X275 rstn 217 NOT
+X276 rstn 218 NOT
+X277 rstn 219 NOT
+X278 rstn 220 NOT
+X279 rstn 221 NOT
+X280 rstn 222 NOT
+X281 rstn 223 NOT
+X282 rstn 224 NOT
+X283 rstn 225 NOT
+X284 rstn 226 NOT
+X285 rstn 227 NOT
+X286 rstn 228 NOT
+X287 rstn 229 NOT
+X288 rstn 230 NOT
+X289 rstn 231 NOT
+X290 rstn 232 NOT
+X291 rstn 233 NOT
+X292 rstn 234 NOT
+X293 rstn 235 NOT
+X294 rstn 236 NOT
+X295 clk 184.0 result.0 0s 199 DFFSR
+X296 clk 184.1 result.1 0s 200 DFFSR
+X297 clk 184.2 result.2 0s 201 DFFSR
+X298 clk 184.3 result.3 0s 202 DFFSR
+X299 clk 184.4 result.4 0s 203 DFFSR
+X300 clk 184.5 result.5 0s 204 DFFSR
+X301 clk 184.6 result.6 0s 205 DFFSR
+X302 clk 184.7 result.7 0s 206 DFFSR
+X303 clk 180 calibrate 0s 207 DFFSR
+X304 clk 172.0 state.0 0s 208 DFFSR
+X305 clk 172.1 state.1 0s 209 DFFSR
+X306 clk 172.2 state.2 0s 210 DFFSR
+X307 clk 149.0 mask.0 0s 211 DFFSR
+X308 clk 149.1 mask.1 0s 212 DFFSR
+X309 clk 149.2 mask.2 0s 213 DFFSR
+X310 clk 149.3 mask.3 0s 214 DFFSR
+X311 clk 149.4 mask.4 0s 215 DFFSR
+X312 clk 149.5 mask.5 0s 216 DFFSR
+X313 clk 149.6 mask.6 0s 217 DFFSR
+X314 clk 149.7 mask.7 0s 218 DFFSR
+X315 clk 140.0 trim_mask.0 0s 219 DFFSR
+X316 clk 140.1 trim_mask.1 0s 220 DFFSR
+X317 clk 140.2 trim_mask.2 0s 221 DFFSR
+X318 clk 140.3 trim_mask.3 0s 222 DFFSR
+X319 clk 140.4 trim_mask.4 0s 223 DFFSR
+X320 clk 120.0 trim_val.0 0s 224 DFFSR
+X321 clk 120.1 trim_val.1 0s 225 DFFSR
+X322 clk 120.2 trim_val.2 0s 226 DFFSR
+X323 clk 120.3 trim_val.3 0s 227 DFFSR
+X324 clk 120.4 trim_val.4 0s 228 DFFSR
+X325 clk 112 en_co_clk 0s 229 DFFSR
+X326 clk 72.0 cal_count.0 230 0s DFFSR
+X327 clk 72.1 cal_count.1 231 0s DFFSR
+X328 clk 72.2 cal_count.2 232 0s DFFSR
+X329 clk 72.3 cal_count.3 0s 233 DFFSR
+X330 clk 48.0 cal_itt.0 0s 234 DFFSR
+X331 clk 48.1 cal_itt.1 0s 235 DFFSR
+X332 clk 48.2 cal_itt.2 0s 236 DFFSR
+X333 clk 48.3 cal_itt.3 0s 1 DFFSR
+.ENDS sar_logic
+
+************************
+* end of SPICE netlist *
+************************
+
diff --git a/xschem/sar/dac/carray.sch b/xschem/sar/dac/carray.sch
new file mode 100644
index 0000000..f344216
--- /dev/null
+++ b/xschem/sar/dac/carray.sch
@@ -0,0 +1,70 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 1400 -240 1400 -190 { lab=n3}
+N 1620 -240 1620 -190 { lab=n2}
+N 1870 -240 1870 -190 { lab=n1}
+N 2110 -240 2110 -190 { lab=n0}
+N 1400 -340 1400 -300 { lab=top}
+N 1620 -340 1620 -300 { lab=top}
+N 1870 -340 1870 -300 { lab=top}
+N 2110 -340 2110 -300 { lab=top}
+N 2360 -240 2360 -190 { lab=ndum}
+N 2360 -340 2360 -300 { lab=top}
+N 1180 -240 1180 -190 { lab=n4}
+N 1180 -340 1180 -300 { lab=top}
+N 960 -240 960 -190 { lab=n5}
+N 960 -340 960 -300 { lab=top}
+N 740 -240 740 -190 { lab=n6}
+N 740 -340 740 -300 { lab=top}
+N 520 -240 520 -190 { lab=n7}
+N 520 -340 520 -300 { lab=top}
+N 520 -340 2360 -340 { lab=top}
+N 2360 -340 2420 -340 { lab=top}
+N 2620 -320 2620 -290 { lab=top}
+N 2580 -320 2620 -320 { lab=top}
+N 2620 -230 2620 -180 { lab=dum_bot[83:0]}
+N 2620 -180 2620 -150 { lab=dum_bot[83:0]}
+N 2600 -150 2620 -150 { lab=dum_bot[83:0]}
+C {sar/unitcap/unitcap.sym} 2340 -230 0 0 {name=xcdum}
+C {sar/unitcap/unitcap.sym} 2090 -230 0 0 {name=xc0}
+C {sar/unitcap/unitcap.sym} 1850 -230 0 0 {name=xc1[1:0]}
+C {sar/unitcap/unitcap.sym} 1600 -230 0 0 {name=xc2[3:0]}
+C {sar/unitcap/unitcap.sym} 1380 -230 0 0 {name=xc3[7:0]
+}
+C {sar/unitcap/unitcap.sym} 1160 -230 0 0 {name=xc4[15:0]}
+C {sar/unitcap/unitcap.sym} 940 -230 0 0 {name=xc5[31:0]}
+C {sar/unitcap/unitcap.sym} 720 -230 0 0 {name=xc6[63:0]}
+C {sar/unitcap/unitcap.sym} 500 -230 0 0 {name=xc7[127:0]}
+C {xschem_library/devices/iopin.sym} 2420 -340 0 0 {name=p1 lab=top
+}
+C {xschem_library/devices/iopin.sym} 520 -190 1 0 {name=p2 lab=n7
+}
+C {xschem_library/devices/iopin.sym} 740 -190 1 0 {name=p4 lab=n6
+}
+C {xschem_library/devices/iopin.sym} 960 -190 1 0 {name=p5 lab=n5
+}
+C {xschem_library/devices/iopin.sym} 1180 -190 1 0 {name=p6 lab=n4
+}
+C {xschem_library/devices/iopin.sym} 1620 -190 1 0 {name=p9 lab=n2
+}
+C {xschem_library/devices/iopin.sym} 2110 -190 1 0 {name=p11 lab=n0
+}
+C {xschem_library/devices/iopin.sym} 2360 -190 1 0 {name=p12 lab=ndum
+}
+C {xschem_library/devices/iopin.sym} 1400 -190 1 0 {name=p7 lab=n3
+}
+C {xschem_library/devices/iopin.sym} 1870 -190 1 0 {name=p8 lab=n1
+}
+C {adc/unitcap/unitcap.sym} 2600 -220 0 0 {name=xdummy[83:0]
+spice_ignore="tcleval($dummy_ignore)"
+}
+C {lab_wire.sym} 2610 -320 0 0 {name=l1 sig_type=std_logic lab=top
+}
+C {lab_wire.sym} 2620 -190 0 0 {name=l2 sig_type=std_logic lab=dum_bot[83:0]
+}
+C {xschem_library/devices/noconn.sym} 2600 -150 0 0 {name=l3[83:0]
+}
diff --git a/xschem/sar/dac/carray.sym b/xschem/sar/dac/carray.sym
new file mode 100644
index 0000000..543e5da
--- /dev/null
+++ b/xschem/sar/dac/carray.sym
@@ -0,0 +1,73 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+B 5 -2.5 -112.5 2.5 -107.5 {name=top dir=inout }
+B 5 307.5 -2.5 312.5 2.5 {name=n6 dir=inout }
+B 5 1627.5 -2.5 1632.5 2.5 {name=n0 dir=inout }
+B 5 527.5 -2.5 532.5 2.5 {name=n5 dir=inout }
+B 5 747.5 -2.5 752.5 2.5 {name=n4 dir=inout }
+B 5 1187.5 -2.5 1192.5 2.5 {name=n2 dir=inout }
+B 5 1847.5 -2.5 1852.5 2.5 {name=ndum dir=inout }
+B 5 967.5 -2.5 972.5 2.5 {name=n3 dir=inout }
+B 5 1407.5 -2.5 1412.5 2.5 {name=n1 dir=inout }
+B 5 87.5 -2.5 92.5 2.5 {name=n7 dir=inout }
+A 4 90 -7.5 42.5 61.92751306414704 56.14497387170592 {}
+A 4 310 -7.5 42.5 61.92751306414704 56.14497387170592 {}
+A 4 530 -7.5 42.5 61.92751306414704 56.14497387170592 {}
+A 4 750 -7.5 42.5 61.92751306414704 56.14497387170592 {}
+A 4 970 -7.5 42.5 61.92751306414704 56.14497387170592 {}
+A 4 1190 -7.5 42.5 61.92751306414704 56.14497387170592 {}
+A 4 1410 -7.5 42.5 61.92751306414704 56.14497387170592 {}
+A 4 1630 -7.5 42.5 61.92751306414704 56.14497387170592 {}
+A 4 1850 -7.5 42.5 61.92751306414704 56.14497387170592 {}
+P 4 1 99 -39 {}
+P 4 1 319 -39 {}
+P 4 1 759 -39 {}
+P 4 1 1639 -39 {}
+P 4 2 90 0 90 -50 {}
+P 4 2 70 -60 110 -60 {}
+P 4 2 310 0 310 -50 {}
+P 4 2 290 -60 330 -60 {}
+P 4 2 90 -60 90 -110 {}
+P 4 2 310 -60 310 -110 {}
+P 4 2 530 0 530 -50 {}
+P 4 2 510 -60 550 -60 {}
+P 4 2 530 -60 530 -110 {}
+P 4 2 750 0 750 -50 {}
+P 4 2 730 -60 770 -60 {}
+P 4 2 750 -60 750 -110 {}
+P 4 2 970 0 970 -50 {}
+P 4 2 950 -60 990 -60 {}
+P 4 2 970 -60 970 -110 {}
+P 4 2 1190 0 1190 -50 {}
+P 4 2 1170 -60 1210 -60 {}
+P 4 2 1190 -60 1190 -110 {}
+P 4 2 1410 0 1410 -50 {}
+P 4 2 1390 -60 1430 -60 {}
+P 4 2 1410 -60 1410 -110 {}
+P 4 2 1630 0 1630 -50 {}
+P 4 2 1610 -60 1650 -60 {}
+P 4 2 1630 -60 1630 -110 {}
+P 4 2 1850 0 1850 -50 {}
+P 4 2 1830 -60 1870 -60 {}
+P 4 2 1850 -60 1850 -110 {}
+P 4 2 0 -110 1850 -110 {}
+P 4 5 0 0 1920 0 1920 -190 0 -190 0 0 {}
+T {@symname} 15 -176 0 0 0.3 0.3 {}
+T {@name} 15 -152 0 0 0.2 0.2 {}
+T {top} 25 -124 0 1 0.2 0.2 {}
+T {n6} 309 -10 1 1 0.2 0.2 {}
+T {n0} 1629 -10 1 1 0.2 0.2 {}
+T {n5} 529 -10 1 1 0.2 0.2 {}
+T {n4} 749 -10 1 1 0.2 0.2 {}
+T {n2} 1189 -10 1 1 0.2 0.2 {}
+T {ndum} 1839 -10 1 1 0.2 0.2 {}
+T {n3} 969 -10 1 1 0.2 0.2 {}
+T {n1} 1399 -10 1 1 0.2 0.2 {}
+T {n7} 89 -10 1 1 0.2 0.2 {}
diff --git a/xschem/sar/dac/dac.sch b/xschem/sar/dac/dac.sch
new file mode 100644
index 0000000..da65176
--- /dev/null
+++ b/xschem/sar/dac/dac.sch
@@ -0,0 +1,95 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 1470 -540 1470 -490 { lab=n3}
+N 1690 -540 1690 -490 { lab=n2}
+N 1910 -540 1910 -490 { lab=n1}
+N 2130 -540 2130 -490 { lab=n0}
+N 110 -650 170 -650 { lab=vin}
+N 2350 -540 2350 -490 { lab=ndum}
+N 1250 -540 1250 -490 { lab=n4}
+N 1030 -540 1030 -490 { lab=n5}
+N 810 -540 810 -490 { lab=n6}
+N 590 -540 590 -490 { lab=n7}
+N 270 -650 500 -650 { lab=out}
+N 350 -720 370 -720 { lab=out}
+N 350 -720 350 -650 { lab=out}
+N 160 -710 220 -710 { lab=sample}
+N 220 -710 220 -680 { lab=sample}
+N 590 -410 590 -380 { lab=ctl[7]}
+N 810 -410 810 -380 { lab=ctl[6]}
+N 1030 -410 1030 -380 { lab=ctl[5]}
+N 1250 -410 1250 -380 { lab=ctl[4]}
+N 1470 -410 1470 -380 { lab=ctl[3]}
+N 1690 -410 1690 -380 { lab=ctl[2]}
+N 1910 -410 1910 -380 { lab=ctl[1]}
+N 2130 -410 2130 -380 { lab=ctl[0]}
+N 2350 -410 2350 -380 { lab=dum}
+C {devices/ipin.sym} 110 -650 0 0 {name=p2 lab=vin}
+C {devices/ipin.sym} 260 -505 0 0 {name=p5 lab=sample}
+C {devices/lab_wire.sym} 210 -710 0 0 {name=l24 sig_type=std_logic lab=sample}
+C {devices/opin.sym} 370 -720 0 0 {name=p18 lab=out}
+C {devices/ipin.sym} 260 -470 0 0 {name=p10 lab=ctl[7:0]
+}
+C {devices/lab_wire.sym} 2350 -540 3 0 {name=l60 sig_type=std_logic lab=ndum}
+C {devices/lab_wire.sym} 2130 -540 3 0 {name=l61 sig_type=std_logic lab=n0}
+C {devices/lab_wire.sym} 1910 -540 3 0 {name=l62 sig_type=std_logic lab=n1}
+C {devices/lab_wire.sym} 1690 -540 3 0 {name=l63 sig_type=std_logic lab=n2}
+C {devices/lab_wire.sym} 1470 -540 3 0 {name=l64 sig_type=std_logic lab=n3}
+C {devices/lab_wire.sym} 1250 -540 3 0 {name=l65 sig_type=std_logic lab=n4}
+C {devices/lab_wire.sym} 1030 -540 3 0 {name=l66 sig_type=std_logic lab=n5}
+C {devices/lab_wire.sym} 810 -540 3 0 {name=l67 sig_type=std_logic lab=n6}
+C {devices/lab_wire.sym} 590 -540 3 0 {name=l68 sig_type=std_logic lab=n7}
+C {sar/dac/carray.sym} 500 -540 0 0 {name=xca
+}
+C {sar/sw/sw_top.sym} 160 -620 0 0 {name=xswt[3:0]
+}
+C {devices/lab_wire.sym} 200 -670 2 1 {name=l50 sig_type=std_logic lab=vdd}
+C {devices/lab_wire.sym} 200 -630 0 0 {name=l51 sig_type=std_logic lab=vss}
+C {devices/ipin.sym} 260 -440 0 0 {name=p1 lab=dum
+}
+C {xschem_library/devices/iopin.sym} 260 -240 2 0 {name=p6 lab=vdd
+}
+C {xschem_library/devices/iopin.sym} 260 -210 2 0 {name=p8 lab=vss
+}
+C {devices/lab_wire.sym} 590 -410 3 0 {name=l1 sig_type=std_logic lab=ctl[7]
+}
+C {xschem_sky130/sky130_stdcells/inv_2.sym} 810 -450 3 0 {name=xi6 VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__
+}
+C {devices/lab_wire.sym} 810 -410 3 0 {name=l2 sig_type=std_logic lab=ctl[6]
+}
+C {xschem_sky130/sky130_stdcells/inv_2.sym} 1030 -450 3 0 {name=xi5 VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__
+}
+C {devices/lab_wire.sym} 1030 -410 3 0 {name=l3 sig_type=std_logic lab=ctl[5]
+}
+C {xschem_sky130/sky130_stdcells/inv_2.sym} 1250 -450 3 0 {name=xi4 VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__
+}
+C {devices/lab_wire.sym} 1250 -410 3 0 {name=l4 sig_type=std_logic lab=ctl[4]
+}
+C {xschem_sky130/sky130_stdcells/inv_2.sym} 1470 -450 3 0 {name=xi3 VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__
+}
+C {devices/lab_wire.sym} 1470 -410 3 0 {name=l5 sig_type=std_logic lab=ctl[3]
+}
+C {xschem_sky130/sky130_stdcells/inv_2.sym} 1690 -450 3 0 {name=xi2 VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__
+}
+C {devices/lab_wire.sym} 1690 -410 3 0 {name=l6 sig_type=std_logic lab=ctl[2]
+}
+C {xschem_sky130/sky130_stdcells/inv_2.sym} 1910 -450 3 0 {name=xi1 VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__
+}
+C {devices/lab_wire.sym} 1910 -410 3 0 {name=l7 sig_type=std_logic lab=ctl[1]
+}
+C {xschem_sky130/sky130_stdcells/inv_2.sym} 2130 -450 3 0 {name=xi0 VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__
+}
+C {devices/lab_wire.sym} 2130 -410 3 0 {name=l8 sig_type=std_logic lab=ctl[0]
+}
+C {xschem_sky130/sky130_stdcells/inv_2.sym} 2350 -450 3 0 {name=xidum VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__
+}
+C {devices/lab_wire.sym} 2350 -410 3 0 {name=l9 sig_type=std_logic lab=dum
+}
+C {xschem_sky130/sky130_stdcells/inv_2.sym} 590 -450 3 0 {name=xi7 VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__
+}
+C {xschem_sky130/sky130_stdcells/tap_2.sym} 370 -250 0 0 {name=x2[2:0] VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__
+}
diff --git a/xschem/sar/dac/dac.sym b/xschem/sar/dac/dac.sym
new file mode 100644
index 0000000..b4f30dc
--- /dev/null
+++ b/xschem/sar/dac/dac.sym
@@ -0,0 +1,96 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -130 -70 130 -70 {}
+L 4 -130 90 130 90 {}
+L 4 130 -10 150 -10 {}
+L 4 -150 -40 -130 -40 {}
+L 4 -150 40 -130 40 {}
+L 4 0 -90 0 -70 {}
+L 4 0 90 0 110 {}
+L 4 -150 -10 -130 -10 {}
+L 4 -150 60 -130 60 {}
+L 4 -130 -70 -130 90 {}
+L 4 130 -70 130 90 {}
+L 4 -130 -40 -40 -40 {dash=4}
+L 4 -40 -40 -40 -20 {dash=4}
+L 4 -130 40 50 40 {dash=4}
+L 4 -130 60 50 60 {dash=4}
+L 4 31 36 31 40 {dash=4}
+L 4 11 36 11 40 {dash=4}
+L 4 -27 36 -27 40 {dash=4}
+B 5 147.5 -12.5 152.5 -7.5 {name=out dir=out }
+B 5 -152.5 -42.5 -147.5 -37.5 {name=sample dir=in }
+B 5 -2.5 -92.5 2.5 -87.5 {name=vdd dir=inout}
+B 5 -2.5 107.5 2.5 112.5 {name=vss dir=inout}
+B 5 -152.5 -12.5 -147.5 -7.5 {name=vin dir=in }
+B 5 -152.5 37.5 -147.5 42.5 {name=ctl[7:0] dir=in }
+B 5 -152.5 57.5 -147.5 62.5 {name=dum dir=in }
+A 4 -2.64285714285711 -4.78571428571431 1.821078397711702 138.1798301198641 360 {}
+A 4 -7.64285714285711 -4.78571428571431 1.821078397711702 138.1798301198641 360 {}
+A 4 -12.64285714285711 -4.78571428571431 1.821078397711702 138.1798301198641 360 {}
+A 4 -27.04285714285711 16.1142857142857 1.821078397711702 138.1798301198641 360 {}
+A 4 10.95714285714289 16.1142857142857 1.821078397711702 138.1798301198641 360 {}
+A 4 30.95714285714289 16.1142857142857 1.821078397711702 138.1798301198641 360 {}
+A 4 50.95714285714288 16.1142857142857 1.821078397711702 138.1798301198641 360 {}
+A 4 70.95714285714288 16.1142857142857 1.821078397711702 138.1798301198641 360 {}
+P 4 2 6 10 16 10 {}
+P 4 2 6 5 16 5 {}
+P 4 2 26 10 36 10 {}
+P 4 2 26 5 36 5 {}
+P 4 2 46 10 56 10 {}
+P 4 2 46 5 56 5 {}
+P 4 2 66 10 76 10 {}
+P 4 2 66 5 76 5 {}
+P 4 2 31 5 31 -5 {}
+P 4 2 51 5 51 -5 {}
+P 4 2 71 5 71 -5 {}
+P 4 2 91 -10 130 -10 {}
+P 4 2 -32 10 -22 10 {}
+P 4 2 -32 5 -22 5 {}
+P 4 2 -27 5 -27 -5 {}
+P 4 2 11 5 11 -5 {}
+P 4 3 91 -10 -27 -10 -27 -5 {}
+P 4 2 11 -5 11 -10 {}
+P 4 2 31 -5 31 -10 {}
+P 4 2 51 -5 51 -10 {}
+P 4 2 71 -5 71 -10 {}
+P 4 2 -32 -10 -43 -17 {}
+P 4 2 -27 -10 -32 -10 {}
+P 4 2 -130 -10 -70 -10 {}
+P 4 2 -27 28 -27 36 {}
+P 4 4 -27 18 -33 28 -21 28 -27 18 {}
+P 4 2 -27 10 -27 14 {}
+P 4 2 11 28 11 36 {}
+P 4 4 11 18 5 28 17 28 11 18 {}
+P 4 2 11 10 11 14 {}
+P 4 2 31 28 31 36 {}
+P 4 4 31 18 25 28 37 28 31 18 {}
+P 4 2 31 10 31 14 {}
+P 4 2 51 28 51 36 {}
+P 4 4 51 18 45 28 57 28 51 18 {}
+P 4 2 51 10 51 14 {}
+P 4 2 71 28 71 36 {}
+P 4 4 71 18 65 28 77 28 71 18 {}
+P 4 2 71 10 71 14 {}
+P 4 2 -70 -10 -50 -10 {}
+P 4 3 71 36 71 60 50 60 {dash=4
+}
+P 4 3 51 36 51 40 50 40 {dash=4}
+T {@symname} -129.5 -83 0 0 0.2 0.2 {}
+T {@name} 90 -83 0 0 0.2 0.2 {}
+T {out} 126 -25 0 1 0.2 0.2 {}
+T {sample} -125 -54 0 0 0.2 0.2 {}
+T {ctl[7:0]
+} -125 26 0 0 0.2 0.2 {}
+T {vdd} 4 -55 2 0 0.2 0.2 {}
+T {vss} -4 75 0 0 0.2 0.2 {}
+T {vin} -125 -24 0 0 0.2 0.2 {}
+T {dum
+} -125 46 0 0 0.2 0.2 {}
diff --git a/xschem/sar/latch/latch.sch b/xschem/sar/latch/latch.sch
new file mode 100644
index 0000000..1d5c182
--- /dev/null
+++ b/xschem/sar/latch/latch.sch
@@ -0,0 +1,94 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 120 -760 150 -760 { lab=S}
+N 230 -760 270 -760 { lab=#net1}
+N 310 -730 310 -700 { lab=vss}
+N 280 -700 310 -700 { lab=vss}
+N 310 -760 330 -760 { lab=vss}
+N 330 -760 330 -700 { lab=vss}
+N 310 -700 330 -700 { lab=vss}
+N 470 -730 470 -700 { lab=vss}
+N 470 -700 500 -700 { lab=vss}
+N 450 -760 470 -760 { lab=vss}
+N 450 -760 450 -700 { lab=vss}
+N 450 -700 470 -700 { lab=vss}
+N 510 -760 550 -760 { lab=#net2}
+N 310 -930 350 -930 { lab=Qn}
+N 310 -830 350 -830 { lab=Qn}
+N 430 -930 470 -930 { lab=Q}
+N 430 -830 470 -830 { lab=Q}
+N 630 -760 670 -760 { lab=R}
+N 470 -930 485 -930 { lab=Q}
+N 285 -930 310 -930 { lab=Qn}
+N 310 -930 310 -790 { lab=Qn}
+N 470 -930 470 -790 { lab=Q}
+N 390 -910 390 -890 { lab=vss}
+N 390 -970 390 -950 { lab=vdd}
+N 390 -810 390 -790 { lab=vss}
+N 390 -870 390 -850 { lab=vdd}
+N 590 -740 590 -720 { lab=vss}
+N 590 -800 590 -780 { lab=vdd}
+N 190 -740 190 -720 { lab=vss}
+N 190 -800 190 -780 { lab=vdd}
+C {devices/lab_wire.sym} 150 -760 0 0 {name=l39 sig_type=std_logic lab=S}
+C {devices/lab_wire.sym} 670 -760 0 0 {name=l41 sig_type=std_logic lab=R}
+C {devices/lab_wire.sym} 310 -700 0 0 {name=l45 sig_type=std_logic lab=vss}
+C {devices/lab_wire.sym} 470 -700 0 1 {name=l46 sig_type=std_logic lab=vss}
+C {devices/ipin.sym} 120 -760 0 0 {name=p1 lab=S}
+C {devices/ipin.sym} 670 -760 2 0 {name=p6 lab=R}
+C {devices/iopin.sym} 95 -870 0 0 {name=p7 lab=vss}
+C {devices/iopin.sym} 95 -900 0 0 {name=p2 lab=vdd}
+C {devices/opin.sym} 485 -930 0 0 {name=p5 lab=Q}
+C {devices/opin.sym} 285 -930 2 0 {name=p8 lab=Qn}
+C {logic/inv_lvt.sym} 500 -910 0 0 {name=x1}
+C {lab_wire.sym} 390 -910 3 0 {name=l2 sig_type=std_logic lab=vss
+}
+C {lab_wire.sym} 390 -950 3 1 {name=l1 sig_type=std_logic lab=vdd
+}
+C {logic/inv_lvt.sym} 280 -810 0 1 {name=x2}
+C {lab_wire.sym} 390 -810 1 1 {name=l3 sig_type=std_logic lab=vss
+}
+C {lab_wire.sym} 390 -850 1 0 {name=l4 sig_type=std_logic lab=vdd
+}
+C {logic/inv_lvt.sym} 480 -740 0 1 {name=x3}
+C {lab_wire.sym} 590 -740 1 1 {name=l5 sig_type=std_logic lab=vss
+}
+C {lab_wire.sym} 590 -780 1 0 {name=l6 sig_type=std_logic lab=vdd
+}
+C {logic/inv_lvt.sym} 300 -740 0 0 {name=x4}
+C {lab_wire.sym} 190 -740 3 0 {name=l7 sig_type=std_logic lab=vss
+}
+C {lab_wire.sym} 190 -780 3 1 {name=l8 sig_type=std_logic lab=vdd
+}
+C {xschem_sky130/sky130_fd_pr/nfet_01v8_lvt.sym} 290 -760 0 0 {name=M3
+L=0.4
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8_lvt
+spiceprefix=X
+}
+C {xschem_sky130/sky130_fd_pr/nfet_01v8_lvt.sym} 490 -760 0 1 {name=M1
+L=0.4
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8_lvt
+spiceprefix=X
+}
diff --git a/xschem/sar/latch/latch.sym b/xschem/sar/latch/latch.sym
new file mode 100644
index 0000000..fa818e2
--- /dev/null
+++ b/xschem/sar/latch/latch.sym
@@ -0,0 +1,33 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 80 -20 100 -20 {}
+L 4 80 20 100 20 {}
+L 4 -90 20 -70 20 {}
+L 4 -90 -20 -70 -20 {}
+L 4 -70 35 80 35 {}
+L 4 -70 -35 -70 35 {}
+L 4 80 -35 80 35 {}
+L 4 -70 -35 80 -35 {}
+B 5 -2.5 -52.5 2.5 -47.5 {name=vdd dir=inout }
+B 5 97.5 -22.5 102.5 -17.5 {name=Q dir=out }
+B 5 97.5 17.5 102.5 22.5 {name=Qn dir=out }
+B 5 -2.5 47.5 2.5 52.5 {name=vss dir=inout }
+B 5 -92.5 17.5 -87.5 22.5 {name=R dir=in }
+B 5 -92.5 -22.5 -87.5 -17.5 {name=S dir=in }
+P 4 2 0 35 -0 50 {}
+P 4 2 0 -50 -0 -35 {}
+T {@symname} -15.5 -6 0 0 0.3 0.3 {}
+T {@name} -10 -17 0 0 0.2 0.2 {}
+T {vdd} 10 -34 0 1 0.2 0.2 {}
+T {Q} 75 -24 0 1 0.2 0.2 {}
+T {Qn} 75 16 0 1 0.2 0.2 {}
+T {vss} 10 21 0 1 0.2 0.2 {}
+T {R} -65 16 0 0 0.2 0.2 {}
+T {S} -65 -24 0 0 0.2 0.2 {}
diff --git a/xschem/sar/sar/sar.sch b/xschem/sar/sar/sar.sch
new file mode 100644
index 0000000..1dfb8bc
--- /dev/null
+++ b/xschem/sar/sar/sar.sch
@@ -0,0 +1,168 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {Xuut dclk drstn den dcomp dcal dvalid dres0 dres1 dres2 dres3 dres4 dres5 dres6 dres7 dsamp dctlp0 dctlp1 dctlp2 dctlp3 dctlp4 dctlp5 dctlp6 dctlp7 dctln0 dctln1 dctln2 dctln3 dctln4 dctln5 dctln6 dctln7 dtrim0 dtrim1 dtrim2 dtrim3 dtrim4 dtrimb0 dtrimb1 dtrimb2 dtrimb3 dtrimb4 dclkc sar_logic
+
+.model adc_buff adc_bridge(in_low = 0.2 in_high=0.8)
+.model dac_buff dac_bridge(out_high = 1.2)
+
+Aad [clk rstn en comp cal] [dclk drstn den dcomp dcal] adc_buff
+Ada [dctlp0 dctlp1 dctlp2 dctlp3 dctlp4 dctlp5 dctlp6 dctlp7 dctln0 dctln1 dctln2 dctln3 dctln4 dctln5 dctln6 dctln7 dres0 dres1 dres2 dres3 dres4 dres5 dres6 dres7 dsamp dclkc] [ctlp_0_ ctlp_1_ ctlp_2_ ctlp_3_ ctlp_4_ ctlp_5_ ctlp_6_ ctlp_7_ ctln_0_ ctln_1_ ctln_2_ ctln_3_ ctln_4_ ctln_5_ ctln_6_ ctln_7_ res0 res1 res2 res3 res4 res5 res6 res7 sample clkc] dac_buff
+Ada2 [dtrim4 dtrim3 dtrim2 dtrim1 dtrim0 dtrimb4 dtrimb3 dtrimb2 dtrimb1 dtrimb0] [trim_4_ trim_3_ trim_2_ trim_1_ trim_0_ trimb_4_ trimb_3_ trimb_2_ trimb_1_ trimb_0_ ] dac_buff
+}
+E {}
+B 6 1200 -210 1220 -70 {}
+B 6 940 -210 960 -70 {}
+P 4 5 1220 -230 1220 -50 940 -50 940 -230 1220 -230 {dash=4 fill=True}
+P 4 5 961 -209 961 -71 1199 -71 1199 -209 961 -209 {}
+P 6 5 1220 -210 940 -210 940 -230 1220 -230 1220 -210 {fill=true}
+P 6 5 1220 -50 940 -50 940 -70 1220 -70 1220 -50 {fill=true}
+T {sar_logic.sp} 1110 -140 0 1 0.2 0.2 {}
+T {SAR-CTL} 1120 -170 0 1 0.4 0.4 {}
+N 620 -410 730 -410 { lab=vn}
+N 780 -540 780 -510 { lab=avdd}
+N 1110 -420 1125 -420 { lab=#net1}
+N 980 -370 1010 -370 { lab=avss}
+N 1010 -390 1010 -370 { lab=avss}
+N 980 -510 1010 -510 { lab=avdd}
+N 1010 -510 1010 -490 { lab=avdd}
+N 150 -600 180 -600 { lab=vinp}
+N 120 -550 180 -550 { lab=ctlp[7:0]}
+N 150 -280 180 -280 { lab=vinn}
+N 120 -230 180 -230 { lab=ctln[7:0]}
+N 610 -410 620 -410 { lab=vn}
+N 330 -480 330 -450 { lab=avss}
+N 330 -160 330 -130 { lab=avss}
+N 330 -710 330 -680 { lab=avdd}
+N 1110 -460 1160 -460 { lab=comp}
+N 780 -370 780 -340 { lab=avss}
+N 860 -420 920 -420 { lab=outn}
+N 860 -460 920 -460 { lab=outp}
+N 150 -210 180 -210 { lab=avss}
+N 150 -530 180 -530 { lab=avdd}
+N 810 -550 810 -490 { lab=trim[4:0]}
+N 810 -550 870 -550 { lab=trim[4:0]}
+N 830 -520 830 -480 { lab=trimb[4:0]}
+N 900 -210 940 -210 { lab=clkc}
+N 830 -520 900 -520 { lab=trimb[4:0]}
+N 1160 -460 1270 -460 { lab=comp}
+N 810 -390 810 -210 { lab=clkc}
+N 810 -210 820 -210 { lab=clkc}
+N 810 -70 940 -70 { lab=sample}
+N 810 -110 940 -110 { lab=ctln[7:0]}
+N 810 -150 940 -150 { lab=ctlp[7:0]}
+N 1070 -290 1070 -230 { lab=trim[4:0]}
+N 1110 -300 1110 -230 { lab=trimb[4:0]}
+N 1220 -120 1340 -120 { lab=result[7:0]}
+N 1220 -90 1340 -90 { lab=valid}
+N 1270 -460 1270 -210 { lab=comp}
+N 1220 -150 1340 -150 { lab=clk}
+N 1220 -170 1340 -170 { lab=en}
+N 1220 -210 1270 -210 { lab=comp}
+N 1220 -190 1340 -190 { lab=cal}
+N 130 -310 180 -310 { lab=sample}
+N 120 -630 180 -630 { lab=sample}
+N 480 -280 610 -280 { lab=vn}
+N 610 -410 610 -280 { lab=vn}
+N 480 -600 610 -600 { lab=vp}
+N 610 -470 730 -470 { lab=vp}
+N 610 -600 610 -470 { lab=vp}
+N 330 -400 330 -360 { lab=avdd}
+N 820 -210 900 -210 { lab=clkc}
+N 1220 -70 1340 -70 { lab=rstn}
+C {devices/lab_wire.sym} 730 -410 0 0 {name=l58 sig_type=std_logic lab=vn}
+C {devices/lab_wire.sym} 180 -310 0 0 {name=l80 sig_type=std_logic lab=sample}
+C {devices/lab_wire.sym} 180 -230 0 0 {name=l44 sig_type=std_logic lab=ctln[7:0]}
+C {devices/lab_wire.sym} 900 -210 0 1 {name=l1 sig_type=std_logic lab=clkc}
+C {devices/lab_wire.sym} 920 -460 0 0 {name=l39 sig_type=std_logic lab=outp}
+C {devices/lab_wire.sym} 920 -420 0 0 {name=l41 sig_type=std_logic lab=outn}
+C {devices/lab_wire.sym} 730 -470 0 0 {name=l62 sig_type=std_logic lab=vp}
+C {devices/lab_wire.sym} 780 -510 3 1 {name=l66 sig_type=std_logic lab=avdd}
+C {sar/latch/latch.sym} 1010 -440 0 0 {name=xlat}
+C {devices/noconn.sym} 1125 -420 2 0 {name=l87}
+C {devices/lab_wire.sym} 1010 -370 0 0 {name=l5 sig_type=std_logic lab=avss
+}
+C {devices/lab_wire.sym} 1010 -510 0 0 {name=l6 sig_type=std_logic lab=avdd
+}
+C {devices/iopin.sym} -100 -490 0 0 {name=p6 lab=avss}
+C {devices/iopin.sym} -100 -520 0 0 {name=p8 lab=avdd}
+C {devices/iopin.sym} -210 -490 0 0 {name=p7 lab=dvss}
+C {devices/iopin.sym} -210 -520 0 0 {name=p9 lab=dvdd}
+C {devices/ipin.sym} -100 -450 0 1 {name=p5 lab=vinp}
+C {devices/ipin.sym} -100 -420 0 1 {name=p13 lab=vinn}
+C {devices/opin.sym} -210 -260 2 1 {name=p1 lab=result[7:0]}
+C {devices/ipin.sym} -210 -350 0 1 {name=p3 lab=clk}
+C {devices/ipin.sym} -100 -350 0 1 {name=p11 lab=en}
+C {devices/lab_wire.sym} 1110 -460 0 1 {name=l9 sig_type=std_logic lab=comp}
+C {devices/noconn.sym} 1220 -210 0 0 {name=l12}
+C {devices/lab_wire.sym} 180 -550 0 0 {name=l11 sig_type=std_logic lab=ctlp[7:0]}
+C {devices/lab_wire.sym} 180 -600 0 0 {name=l19 sig_type=std_logic lab=vinp}
+C {devices/lab_wire.sym} 180 -280 0 0 {name=l29 sig_type=std_logic lab=vinn}
+C {devices/lab_wire.sym} 330 -360 1 0 {name=l24 sig_type=std_logic lab=avdd}
+C {devices/lab_wire.sym} 330 -480 3 0 {name=l15 sig_type=std_logic lab=avss}
+C {devices/lab_wire.sym} 330 -160 3 0 {name=l25 sig_type=std_logic lab=avss}
+C {devices/lab_wire.sym} 330 -680 1 0 {name=l14 sig_type=std_logic lab=avdd}
+C {devices/opin.sym} -210 -230 2 1 {name=p14 lab=valid}
+C {devices/ipin.sym} -210 -310 0 1 {name=p15 lab=cal}
+C {devices/lab_wire.sym} 780 -370 3 0 {name=l2 sig_type=std_logic lab=avss}
+C {code.sym} -220 -160 0 0 {name=INCLUDES only_toplevel=false
+format="tcleval(@value )"
+value=".include \\\\$::DESIGN_PATH\\\\/sar/control/cmos_cells_digital.sp
+.include \\\\$::DESIGN_PATH\\\\/sar/control/sar_logic.sp
+"}
+C {devices/lab_wire.sym} 180 -210 0 0 {name=l23 sig_type=std_logic lab=avss
+}
+C {devices/lab_wire.sym} 180 -530 0 0 {name=l31 sig_type=std_logic lab=avdd
+}
+C {devices/lab_wire.sym} 830 -520 0 1 {name=l3 sig_type=std_logic lab=trimb[4:0]
+}
+C {devices/lab_wire.sym} 810 -550 0 1 {name=l13 sig_type=std_logic lab=trim[4:0]}
+C {devices/lab_wire.sym} 180 -630 0 0 {name=l4 sig_type=std_logic lab=sample}
+C {devices/lab_wire.sym} 900 -70 0 0 {name=l7 sig_type=std_logic lab=sample}
+C {devices/noconn.sym} 810 -70 0 0 {name=l8}
+C {devices/lab_wire.sym} 900 -110 0 0 {name=l10 sig_type=std_logic lab=ctln[7:0]}
+C {devices/noconn.sym} 810 -110 0 0 {name=l20[7:0]
+}
+C {devices/lab_wire.sym} 900 -150 0 0 {name=l21 sig_type=std_logic lab=ctlp[7:0]
+}
+C {devices/noconn.sym} 810 -150 0 0 {name=l22[7:0]
+}
+C {devices/lab_wire.sym} 1110 -230 3 1 {name=l30 sig_type=std_logic lab=trimb[4:0]
+}
+C {devices/lab_wire.sym} 1070 -230 3 1 {name=l32 sig_type=std_logic lab=trim[4:0]}
+C {devices/noconn.sym} 1070 -290 1 0 {name=l33}
+C {devices/noconn.sym} 1110 -300 1 0 {name=l34}
+C {devices/lab_wire.sym} 1320 -120 0 0 {name=l35 sig_type=std_logic lab=result[7:0]
+}
+C {devices/noconn.sym} 1220 -120 0 0 {name=l36[7:0]
+}
+C {devices/lab_wire.sym} 1300 -90 0 0 {name=l36 sig_type=std_logic lab=valid
+}
+C {devices/noconn.sym} 1220 -90 0 0 {name=l37
+}
+C {devices/noconn.sym} 940 -210 2 0 {name=l38}
+C {devices/lab_wire.sym} 1300 -150 0 0 {name=l20 sig_type=std_logic lab=clk
+}
+C {devices/noconn.sym} 1220 -150 0 0 {name=l22
+}
+C {devices/lab_wire.sym} 1300 -170 0 0 {name=l40 sig_type=std_logic lab=en
+}
+C {devices/noconn.sym} 1220 -170 0 0 {name=l42
+}
+C {devices/lab_wire.sym} 1300 -190 0 0 {name=l43 sig_type=std_logic lab=cal
+}
+C {devices/noconn.sym} 1220 -190 0 0 {name=l45
+}
+C {sar/dac/dac.sym} 330 -270 0 0 {name=xdn
+}
+C {sar/dac/dac.sym} 330 -590 0 0 {name=xdp
+}
+C {sar/comparator/comparator.sym} 810 -280 0 0 {name=xcom
+}
+C {devices/lab_wire.sym} 1300 -70 0 0 {name=l27 sig_type=std_logic lab=rstn
+}
+C {devices/noconn.sym} 1220 -70 0 0 {name=l28
+}
+C {devices/ipin.sym} -100 -320 0 1 {name=p2 lab=rstn
+}
diff --git a/xschem/sar/sar/sar.sym b/xschem/sar/sar/sar.sym
new file mode 100644
index 0000000..55fec95
--- /dev/null
+++ b/xschem/sar/sar/sar.sym
@@ -0,0 +1,130 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 30 -180 50 -180 {}
+L 4 -280 -130 -260 -130 {}
+L 4 -140 -110 -140 -90 {}
+L 4 -140 -270 -140 -250 {}
+L 4 -180 -270 -180 -250 {}
+L 4 -50 -110 -50 -90 {}
+L 4 -280 -230 -260 -230 {}
+L 4 -180 -110 -180 -90 {}
+L 4 -260 -250 30 -250 {}
+L 4 -260 -110 30 -110 {}
+L 4 -260 -250 -260 -110 {}
+L 4 30 -250 30 -110 {}
+L 4 -20 -110 -20 -90 {}
+L 4 30 -150 50 -150 {}
+L 4 -50 -270 -50 -250 {}
+L 4 -195 -155 -195 -152.6 {}
+L 4 -175 -155 -175 -152.6 {}
+L 4 -155 -155 -155 -152.6 {}
+L 4 -135 -155 -135 -152.6 {}
+L 4 -135 -207.4 -135 -205 {}
+L 4 -155 -207.4 -155 -205 {}
+L 4 -175 -207.4 -175 -205 {}
+L 4 -195 -207.4 -195 -205 {}
+L 4 0 -110 0 -90 {}
+B 5 -182.5 -272.5 -177.5 -267.5 {name=avdd dir=inout }
+B 5 -142.5 -272.5 -137.5 -267.5 {name=dvdd dir=inout }
+B 5 -142.5 -92.5 -137.5 -87.5 {name=dvss dir=inout }
+B 5 47.5 -182.5 52.5 -177.5 {name=result[7:0] dir=out }
+B 5 -282.5 -132.5 -277.5 -127.5 {name=vinn dir=in }
+B 5 -182.5 -92.5 -177.5 -87.5 {name=avss dir=inout }
+B 5 -52.5 -92.5 -47.5 -87.5 {name=clk dir=in }
+B 5 -282.5 -232.5 -277.5 -227.5 {name=vinp dir=in }
+B 5 -22.5 -92.5 -17.5 -87.5 {name=en dir=in }
+B 5 47.5 -152.5 52.5 -147.5 {name=valid dir=out }
+B 5 -52.5 -272.5 -47.5 -267.5 {name=cal dir=in }
+B 5 -2.5 -92.5 2.5 -87.5 {name=rstn
+ dir=in }
+A 4 -200.6428571428571 -169.7857142857143 1.821078397711702 138.1798301198641 360 {}
+A 4 -205.6428571428571 -169.7857142857143 1.821078397711702 138.1798301198641 360 {}
+A 4 -210.6428571428571 -169.7857142857143 1.821078397711702 138.1798301198641 360 {}
+A 4 -200.6428571428571 -190.7857142857143 1.821078397711702 138.1798301198641 360 {}
+A 4 -205.6428571428571 -190.7857142857143 1.821078397711702 138.1798301198641 360 {}
+A 4 -210.6428571428571 -190.7857142857143 1.821078397711702 138.1798301198641 360 {}
+A 4 -195.0428571428571 -150.7857142857143 1.821078397711702 138.1798301198641 360 {}
+A 4 -175.0428571428571 -150.7857142857143 1.821078397711702 138.1798301198641 360 {}
+A 4 -155.0428571428571 -150.7857142857143 1.821078397711702 138.1798301198641 360 {}
+A 4 -135.0428571428571 -150.7857142857143 1.821078397711702 138.1798301198641 360 {}
+A 4 -134.9571428571429 -209.2142857142857 1.821078397711702 318.1798301198641 360 {}
+A 4 -154.9571428571429 -209.2142857142857 1.821078397711702 318.1798301198641 360 {}
+A 4 -174.9571428571429 -209.2142857142857 1.821078397711702 318.1798301198641 360 {}
+A 4 -194.9571428571429 -209.2142857142857 1.821078397711702 318.1798301198641 360 {}
+P 4 4 -120 -200 -120 -160 -85 -180 -120 -200 {}
+P 4 2 -200 -155 -190 -155 {}
+P 4 2 -200 -160 -190 -160 {}
+P 4 2 -180 -155 -170 -155 {}
+P 4 2 -180 -160 -170 -160 {}
+P 4 2 -160 -155 -150 -155 {}
+P 4 2 -160 -160 -150 -160 {}
+P 4 2 -140 -155 -130 -155 {}
+P 4 2 -140 -160 -130 -160 {}
+P 4 3 -195 -160 -195 -170 -120 -170 {}
+P 4 2 -175 -160 -175 -170 {}
+P 4 2 -155 -160 -155 -170 {}
+P 4 2 -135 -160 -135 -170 {}
+P 4 2 -200 -205 -190 -205 {}
+P 4 2 -200 -200 -190 -200 {}
+P 4 2 -180 -205 -170 -205 {}
+P 4 2 -180 -200 -170 -200 {}
+P 4 2 -160 -205 -150 -205 {}
+P 4 2 -160 -200 -150 -200 {}
+P 4 2 -140 -205 -130 -205 {}
+P 4 2 -140 -200 -130 -200 {}
+P 4 3 -195 -200 -195 -190 -120 -190 {}
+P 4 2 -175 -200 -175 -190 {}
+P 4 2 -155 -200 -155 -190 {}
+P 4 2 -135 -200 -135 -190 {}
+P 4 2 -115 -193 -115 -187 {}
+P 4 2 -118 -190 -112 -190 {}
+P 4 2 -118 -170 -112 -170 {}
+P 4 2 -85 -180 -68 -180 {}
+P 4 5 -68 -199 -68 -161 -34 -161 -34 -199 -68 -199 {}
+P 4 6 -61 -199 -61 -216 -126 -216 -124 -217 -124 -215 -126 -216 {}
+P 4 6 -61 -161 -61 -144 -126 -144 -124 -143 -124 -145 -126 -144 {}
+P 4 2 30 -180 10 -180 {}
+P 4 2 10 -180 -34 -180 {}
+P 4 2 -50 -161 -50 -110 {}
+P 4 4 30 -150 -0 -150 -0 -170 -30 -170 {}
+P 4 2 -30 -170 -34 -170 {}
+P 4 2 -50 -250 -50 -200 {}
+P 4 2 -195 -141 -195 -135 {}
+P 4 4 -195 -149 -200 -141 -190 -141 -195 -149 {}
+P 4 2 -175 -141 -175 -135 {}
+P 4 4 -175 -149 -180 -141 -170 -141 -175 -149 {}
+P 4 2 -155 -141 -155 -135 {}
+P 4 4 -155 -149 -160 -141 -150 -141 -155 -149 {}
+P 4 2 -135 -141 -135 -135 {}
+P 4 4 -135 -149 -140 -141 -130 -141 -135 -149 {}
+P 4 2 -135 -219 -135 -225 {}
+P 4 4 -135 -211 -130 -219 -140 -219 -135 -211 {}
+P 4 2 -155 -219 -155 -225 {}
+P 4 4 -155 -211 -150 -219 -160 -219 -155 -211 {}
+P 4 2 -175 -219 -175 -225 {}
+P 4 4 -175 -211 -170 -219 -180 -219 -175 -211 {}
+P 4 2 -195 -219 -195 -225 {}
+P 4 4 -195 -211 -190 -219 -200 -219 -195 -211 {}
+P 4 4 -20 -110 -20 -144 -39 -144 -39 -161 {}
+P 6 5 -69 -200 -33 -200 -33 -160 -69 -160 -69 -200 {}
+T {@symname} -260.5 -263 0 0 0.2 0.2 {}
+T {@name} 9 -263 0 0 0.2 0.2 {}
+T {avdd} -164 -250 0 1 0.2 0.2 {}
+T {dvdd} -124 -250 0 1 0.2 0.2 {}
+T {dvss} -151 -110 2 1 0.2 0.2 {}
+T {result[7:0]} 25 -194 0 1 0.2 0.2 {}
+T {vinn} -255 -144 0 0 0.2 0.2 {}
+T {avss} -191 -110 2 1 0.2 0.2 {}
+T {clk} -68 -122 0 0 0.2 0.2 {}
+T {vinp} -255 -228 0 0 0.2 0.2 {}
+T {en} -38 -122 0 0 0.2 0.2 {}
+T {valid} 2 -162 0 0 0.2 0.2 {}
+T {cal} -67 -250 0 0 0.2 0.2 {}
+T {rstn} 2 -122 0 0 0.2 0.2 {}
diff --git a/xschem/sar/sw/sw_top.sch b/xschem/sar/sw/sw_top.sch
new file mode 100644
index 0000000..d2358e1
--- /dev/null
+++ b/xschem/sar/sw/sw_top.sch
@@ -0,0 +1,76 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 230 -360 260 -360 { lab=out}
+N 260 -360 260 -280 { lab=out}
+N 230 -210 260 -210 { lab=out}
+N 260 -280 260 -210 { lab=out}
+N 140 -210 170 -210 { lab=in}
+N 140 -360 140 -210 { lab=in}
+N 140 -360 170 -360 { lab=in}
+N 200 -360 200 -330 { lab=vdd}
+N 200 -330 200 -320 { lab=vdd}
+N 200 -240 200 -210 { lab=vss}
+N 80 -290 140 -290 { lab=in}
+N 350 -40 400 -40 { lab=en}
+N 260 -290 320 -290 { lab=out}
+N 480 -40 510 -40 { lab=enb}
+N 590 -40 640 -40 { lab=en_buf}
+N 200 -440 200 -400 { lab=enb}
+N 200 -170 200 -120 { lab=en_buf}
+C {devices/iopin.sym} 320 -290 0 0 {name=p1 lab=out}
+C {devices/ipin.sym} 350 -40 0 0 {name=p2 lab=en}
+C {devices/iopin.sym} 20 -20 0 0 {name=p3 lab=vss}
+C {devices/iopin.sym} 20 -50 0 0 {name=p4 lab=vdd}
+C {devices/iopin.sym} 80 -290 2 0 {name=p5 lab=in}
+C {devices/lab_wire.sym} 200 -350 3 0 {name=l21 sig_type=std_logic lab=vdd}
+C {devices/lab_wire.sym} 200 -240 3 0 {name=l22 sig_type=std_logic lab=vss}
+C {devices/lab_wire.sym} 200 -170 3 0 {name=l23 sig_type=std_logic lab=en_buf
+}
+C {devices/lab_wire.sym} 380 -40 0 0 {name=l24 sig_type=std_logic lab=en
+}
+C {sky130_primitives/pfet_01v8.sym} 200 -380 1 0 {name=M3
+L=0.3
+W=1
+nf=1
+mult=10
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_primitives/nfet_01v8.sym} 200 -190 3 0 {name=M4
+L=0.3
+W=1
+nf=1
+mult=10
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {xschem_sky130/sky130_stdcells/decap_8.sym} 160 -20 0 0 {name=x2 VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__
+}
+C {xschem_sky130/sky130_stdcells/inv_4.sym} 440 -40 0 0 {name=x3 VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__
+}
+C {devices/lab_wire.sym} 510 -40 0 0 {name=l1 sig_type=std_logic lab=enb
+}
+C {xschem_sky130/sky130_stdcells/inv_4.sym} 550 -40 0 0 {name=x4 VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__
+}
+C {devices/lab_wire.sym} 640 -40 0 0 {name=l2 sig_type=std_logic lab=en_buf
+}
+C {devices/lab_wire.sym} 200 -410 1 0 {name=l3 sig_type=std_logic lab=enb
+}
+C {xschem_sky130/sky130_stdcells/decap_3.sym} 160 -50 0 0 {name=x5 VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__
+}
diff --git a/xschem/sar/sw/sw_top.sym b/xschem/sar/sw/sw_top.sym
new file mode 100644
index 0000000..5d1801e
--- /dev/null
+++ b/xschem/sar/sw/sw_top.sym
@@ -0,0 +1,25 @@
+v {xschem version=2.9.9 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+B 5 107.5 -32.5 112.5 -27.5 {name=out dir=inout }
+B 5 57.5 -62.5 62.5 -57.5 {name=en dir=in }
+B 5 37.5 -52.5 42.5 -47.5 {name=vdd dir=inout }
+B 5 7.5 -32.5 12.5 -27.5 {name=in dir=inout }
+B 5 37.5 -12.5 42.5 -7.5 {name=vss dir=inout }
+A 4 60 -22 2.23606797749979 206.565051177078 360 {}
+P 4 2 10 -30 40 -30 {}
+P 4 8 40 -30 40 -20 50 -20 50 -10 70 -10 70 -20 80 -20 80 -30 {}
+P 4 8 80 -30 80 -40 70 -40 70 -50 50 -50 50 -40 40 -40 40 -30 {}
+P 4 2 80 -30 110 -30 {}
+P 4 2 52 -52 68 -52 {}
+P 4 2 52 -8 68 -8 {}
+P 4 2 60 -60 60 -52 {}
+P 4 6 60 -52 60 -33 55 -33 60 -25 65 -33 60 -33 {}
+P 4 2 60 -20 60 -8 {}
+T {@name} 73 -54 0 0 0.2 0.2 {}
diff --git a/xschem/sar/unitcap/unitcap.sch b/xschem/sar/unitcap/unitcap.sch
new file mode 100644
index 0000000..56ad359
--- /dev/null
+++ b/xschem/sar/unitcap/unitcap.sch
@@ -0,0 +1,14 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 70 -170 70 -140 { lab=cp}
+N 70 -170 80 -170 { lab=cp}
+N 70 -80 70 -50 { lab=cn}
+N 70 -50 80 -50 { lab=cn}
+C {devices/iopin.sym} 80 -170 0 0 {name=p1 lab=cp}
+C {devices/iopin.sym} 80 -50 0 0 {name=p2 lab=cn}
+C {xschem_sky130/sky130_fd_pr/cap_mim_m3_1.sym} 70 -110 0 0 {name=C1 model=cap_mim_m3_1 W=2 L=2 MF=1 spiceprefix=X
+}
diff --git a/xschem/sar/unitcap/unitcap.sym b/xschem/sar/unitcap/unitcap.sym
new file mode 100644
index 0000000..89c8d7e
--- /dev/null
+++ b/xschem/sar/unitcap/unitcap.sym
@@ -0,0 +1,17 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 20 -35 20 -10 {}
+L 4 20 -70 20 -45 {}
+L 4 10 -45 30 -45 {}
+B 5 17.5 -72.5 22.5 -67.5 {name=cp dir=inout }
+B 5 17.5 -12.5 22.5 -7.5 {name=cn dir=inout }
+A 4 20 -13.75 21.25 61.92751306414704 56.14497387170592 {}
+T {@symname} 30.5 -66 0 0 0.2 0.2 {}
+T {@name} 35 -22 0 0 0.2 0.2 {}
diff --git a/xschem/tb/comparator/tran_comparator_trim.sch b/xschem/tb/comparator/tran_comparator_trim.sch
new file mode 100644
index 0000000..d9ec238
--- /dev/null
+++ b/xschem/tb/comparator/tran_comparator_trim.sch
@@ -0,0 +1,241 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+B 6 1040 -190 1060 -50 {}
+B 6 780 -190 800 -50 {}
+P 4 5 1060 -210 1060 -30 780 -30 780 -210 1060 -210 {dash=4 fill=True}
+P 4 5 -0 -0 1240 0 1240 -650 0 -650 -0 -0 {}
+P 6 5 1060 -190 780 -190 780 -210 1060 -210 1060 -190 {fill=true}
+P 6 5 1060 -30 780 -30 780 -50 1060 -50 1060 -30 {fill=true}
+T {sar_logic.sp} 950 -120 0 1 0.2 0.2 {}
+T {TRIM-LOGIC
+} 990 -150 0 1 0.4 0.4 {}
+N 180 -590 180 -560 { lab=vss}
+N 80 -590 80 -560 { lab=vdd}
+N 580 -590 580 -560 { lab=vdd}
+N 580 -420 580 -390 { lab=vss}
+N 500 -460 530 -460 { lab=vn}
+N 500 -520 530 -520 { lab=vp}
+N 660 -470 710 -470 { lab=outn}
+N 610 -440 610 -340 { lab=clkcc}
+N 360 -460 500 -460 { lab=vn}
+N 610 -590 610 -540 { lab=trim[4:0]}
+N 610 -590 680 -590 { lab=trim[4:0]}
+N 630 -550 700 -550 { lab=trimb[4:0]}
+N 630 -550 630 -530 { lab=trimb[4:0]}
+N 360 -520 390 -520 { lab=#net1}
+N 450 -520 500 -520 { lab=vp}
+N 740 -180 780 -180 { lab=clkc}
+N 650 -180 660 -180 { lab=clkcc}
+N 650 -60 780 -60 { lab=sample}
+N 650 -100 780 -100 { lab=ctln[7:0]}
+N 650 -130 780 -130 { lab=ctlp[7:0]}
+N 910 -270 910 -210 { lab=trim[4:0]}
+N 950 -280 950 -210 { lab=trimb[4:0]}
+N 1060 -90 1180 -90 { lab=result[7:0]}
+N 1060 -70 1180 -70 { lab=valid}
+N 1060 -110 1180 -110 { lab=clk}
+N 1060 -130 1180 -130 { lab=en}
+N 1060 -180 1110 -180 { lab=comp}
+N 1060 -150 1180 -150 { lab=cal}
+N 980 -470 995 -470 { lab=#net2}
+N 850 -420 880 -420 { lab=vss}
+N 880 -440 880 -420 { lab=vss}
+N 850 -560 880 -560 { lab=vdd}
+N 880 -560 880 -540 { lab=vdd}
+N 980 -510 1030 -510 { lab=comp}
+N 660 -510 710 -510 { lab=outp}
+N 710 -510 790 -510 { lab=outp}
+N 710 -470 790 -470 { lab=outn}
+N 1180 -510 1180 -190 { lab=comp}
+N 1030 -510 1180 -510 { lab=comp}
+N 1110 -180 1180 -180 { lab=comp}
+N 1180 -190 1180 -180 { lab=comp}
+N 190 -320 190 -290 { lab=clk}
+N 610 -340 610 -180 { lab=clkcc}
+N 610 -180 650 -180 { lab=clkcc}
+N 80 -320 80 -290 { lab=cal}
+N 80 -440 80 -410 { lab=en}
+N 1060 -50 1180 -50 { lab=rstn}
+N 450 -320 450 -290 { lab=rstn}
+C {adc/comparator/comparator.sym} 610 -330 0 0 {name=xcom}
+C {devices/vsource.sym} 180 -530 0 0 {name=V1 value=0}
+C {devices/vsource.sym} 80 -530 0 0 {name=V2 value=1.4
+}
+C {devices/lab_wire.sym} 180 -560 3 1 {name=l7 sig_type=std_logic lab=vss}
+C {devices/lab_wire.sym} 80 -560 3 1 {name=l8 sig_type=std_logic lab=vdd}
+C {devices/gnd.sym} 80 -500 0 0 {name=l11 lab=GND}
+C {devices/gnd.sym} 180 -500 0 0 {name=l12 lab=GND}
+C {devices/lab_wire.sym} 580 -560 3 1 {name=l3 sig_type=std_logic lab=vdd}
+C {devices/lab_wire.sym} 580 -420 3 0 {name=l4 sig_type=std_logic lab=vss}
+C {devices/lab_wire.sym} 520 -460 0 0 {name=l13 sig_type=std_logic lab=vn}
+C {devices/lab_wire.sym} 520 -520 0 0 {name=l14 sig_type=std_logic lab=vp}
+C {devices/lab_wire.sym} 710 -510 0 0 {name=l17 sig_type=std_logic lab=outp}
+C {devices/lab_wire.sym} 710 -470 0 0 {name=l18 sig_type=std_logic lab=outn}
+C {devices/vsource.sym} 330 -520 1 0 {name=V3 value=vin
+}
+C {devices/gnd.sym} 300 -520 1 0 {name=l9 lab=GND}
+C {devices/vsource.sym} 330 -460 1 0 {name=V4 value=vin
+}
+C {devices/gnd.sym} 300 -460 1 0 {name=l5 lab=GND}
+C {devices/lab_wire.sym} 610 -590 0 1 {name=l6 sig_type=std_logic lab=trim[4:0]}
+C {devices/lab_wire.sym} 630 -550 0 1 {name=l35 sig_type=std_logic lab=trimb[4:0]
+}
+C {devices/vsource.sym} 420 -520 1 0 {name=V10 value=voff
+}
+C {devices/lab_wire.sym} 740 -180 0 1 {name=l20 sig_type=std_logic lab=clkc}
+C {devices/noconn.sym} 1060 -180 0 0 {name=l21}
+C {sky130_stdcells/buf_1.sym} 700 -180 0 1 {name=x4 VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__
+}
+C {devices/lab_wire.sym} 740 -60 0 0 {name=l22 sig_type=std_logic lab=sample}
+C {devices/noconn.sym} 780 -60 2 0 {name=l23}
+C {devices/lab_wire.sym} 740 -100 0 0 {name=l24 sig_type=std_logic lab=ctln[7:0]}
+C {devices/noconn.sym} 780 -100 2 0 {name=l20[7:0]
+}
+C {devices/lab_wire.sym} 740 -130 0 0 {name=l25 sig_type=std_logic lab=ctlp[7:0]
+}
+C {devices/noconn.sym} 780 -130 2 0 {name=l22[7:0]
+}
+C {devices/lab_wire.sym} 950 -210 3 1 {name=l26 sig_type=std_logic lab=trimb[4:0]
+}
+C {devices/lab_wire.sym} 910 -210 3 1 {name=l27 sig_type=std_logic lab=trim[4:0]}
+C {devices/noconn.sym} 910 -210 3 0 {name=l33[4:0]
+}
+C {devices/noconn.sym} 950 -210 3 0 {name=l34[4:0]
+}
+C {devices/lab_wire.sym} 1160 -90 0 0 {name=l28 sig_type=std_logic lab=result[7:0]
+}
+C {devices/noconn.sym} 1060 -90 0 0 {name=l36[7:0]
+}
+C {devices/lab_wire.sym} 1140 -70 0 0 {name=l36 sig_type=std_logic lab=valid
+}
+C {devices/noconn.sym} 1060 -70 0 0 {name=l37
+}
+C {devices/noconn.sym} 780 -180 2 0 {name=l29}
+C {devices/lab_wire.sym} 1140 -110 0 0 {name=l31 sig_type=std_logic lab=clk
+}
+C {devices/noconn.sym} 1060 -110 0 0 {name=l39
+}
+C {devices/lab_wire.sym} 1140 -130 0 0 {name=l40 sig_type=std_logic lab=en
+}
+C {devices/noconn.sym} 1060 -130 0 0 {name=l42
+}
+C {devices/lab_wire.sym} 1140 -150 0 0 {name=l43 sig_type=std_logic lab=cal
+}
+C {devices/noconn.sym} 1060 -150 0 0 {name=l45
+}
+C {devices/lab_wire.sym} 1070 -180 0 1 {name=l10 sig_type=std_logic lab=comp}
+C {sar/latch/latch.sym} 880 -490 0 0 {name=xlat}
+C {devices/noconn.sym} 995 -470 2 0 {name=l87}
+C {devices/lab_wire.sym} 880 -420 0 0 {name=l30 sig_type=std_logic lab=vss
+}
+C {devices/lab_wire.sym} 880 -560 0 0 {name=l38 sig_type=std_logic lab=vdd
+}
+C {vsource.sym} 190 -260 0 0 {name=Vclk1 value="PULSE(0 1 1e-9 1e-9 1e-9 2e-6 4e-6)"
+}
+C {lab_wire.sym} 190 -320 3 0 {name=l2 sig_type=std_logic lab=clk
+}
+C {gnd.sym} 190 -230 0 0 {name=l15 lab=GND}
+C {devices/vsource.sym} 80 -260 0 0 {name=V5 value=1.4}
+C {devices/lab_wire.sym} 80 -290 3 1 {name=l1 sig_type=std_logic lab=cal
+}
+C {devices/gnd.sym} 80 -230 0 0 {name=l16 lab=GND}
+C {devices/code.sym} 30 -150 0 0 {name=NGSPICE
+only_toplevel=true
+value=".include \\\\$::DESIGN_PATH\\\\/sar/control/cmos_cells_digital.sp
+.include \\\\$::DESIGN_PATH\\\\/sar/control/sar_logic.sp
+
+.param MC_SWITCH=0
+.param vin=0.6
+.param voff=-0.03
+
+.options method trap
+
+.control
+tran 100e-9 200e-6
+meas tran tdiff_a TRIG v(xcom.ip) val=1 fall=2 targ v(xcom.in) val=1 fall=2
+meas tran tdiff_b TRIG v(xcom.ip) val=1 fall=-2 targ v(xcom.in) val=1 fall=-2
+
+let tuntr=abs(tdiff_a)
+let tres=abs(tdiff_b)
+print tuntr
+print tres
+
+.endc
+" }
+C {devices/code.sym} 290 -150 0 0 {name=MIXEDMODE
+only_toplevel=true
+value="Xuut dclk drstn den dcomp dcal dvalid dres0 dres1 dres2 dres3 dres4 dres5 dres6 dres7 dsamp dctlp0 dctlp1 dctlp2 dctlp3 dctlp4 dctlp5 dctlp6 dctlp7 dctln0 dctln1 dctln2 dctln3 dctln4 dctln5 dctln6 dctln7 dtrim0 dtrim1 dtrim2 dtrim3 dtrim4 dtrimb0 dtrimb1 dtrimb2 dtrimb3 dtrimb4 dclkc sar_logic
+
+.model adc_buff adc_bridge(in_low = 0.2 in_high=0.8)
+.model dac_buff dac_bridge(out_high = 1.2)
+
+Aad [clk rstn en comp cal] [dclk drstn den dcomp dcal] adc_buff
+Ada [dctlp0 dctlp1 dctlp2 dctlp3 dctlp4 dctlp5 dctlp6 dctlp7 dctln0 dctln1 dctln2 dctln3 dctln4 dctln5 dctln6 dctln7 dres0 dres1 dres2 dres3 dres4 dres5 dres6 dres7 dsamp dclkc] [ctlp_0_ ctlp_1_ ctlp_2_ ctlp_3_ ctlp_4_ ctlp_5_ ctlp_6_ ctlp_7_ ctln_0_ ctln_1_ ctln_2_ ctln_3_ ctln_4_ ctln_5_ ctln_6_ ctln_7_ res0 res1 res2 res3 res4 res5 res6 res7 sample clkc] dac_buff
+Ada2 [dtrim4 dtrim3 dtrim2 dtrim1 dtrim0 dtrimb4 dtrimb3 dtrimb2 dtrimb1 dtrimb0] [trim_4_ trim_3_ trim_2_ trim_1_ trim_0_ trimb_4_ trimb_3_ trimb_2_ trimb_1_ trimb_0_ ] dac_buff
+" }
+C {devices/code.sym} 160 -150 0 0 {name=CORNERS
+only_toplevel=true
+format="tcleval( @value )"
+spice_ignore="tcleval($cmdline_ignore)"
+value="
+* FET CORNERS
+.include \\\\$::SKYWATER_MODELS\\\\/corners/tt.spice
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/ff.spice
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/ss.spice
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/sf.spice
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/fs.spice
+
+* TT + R + C
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/tt_rmax_cmax.spice
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/tt_rmin_cmin.spice
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/tt_rmax_cmin.spice
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/tt_rmin_cmax.spice
+
+* FF + R + C
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/ff_rmax_cmax.spice
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/ff_rmin_cmin.spice
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/ff_rmax_cmin.spice
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/ff_rmin_cmax.spice
+
+
+* SS + R + C
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/ss_rmax_cmax.spice
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/ss_rmin_cmin.spice
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/ss_rmax_cmin.spice
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/ss_rmin_cmax.spice
+
+* SF + R + C
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/sf_rmax_cmax.spice
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/sf_rmin_cmin.spice
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/sf_rmax_cmin.spice
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/sf_rmin_cmax.spice
+
+* FS + R + C
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/fs_rmax_cmax.spice
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/fs_rmin_cmin.spice
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/fs_rmax_cmin.spice
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/fs_rmin_cmax.spice
+"}
+C {code.sym} 420 -150 0 0 {name=STDCELLS only_toplevel=false
+format="tcleval(@value )"
+value="[sky130_models]"}
+C {vsource.sym} 80 -380 0 0 {name=Ven value="PULSE(0 1 0.5e-6 0.1e-6 0.1e-6 10e-6 10e-3)"
+}
+C {lab_wire.sym} 80 -410 1 0 {name=l33 sig_type=std_logic lab=en
+}
+C {gnd.sym} 80 -350 0 0 {name=l34 lab=GND}
+C {devices/lab_wire.sym} 620 -180 0 1 {name=l19 sig_type=std_logic lab=clkcc
+}
+C {devices/lab_wire.sym} 1140 -50 0 0 {name=l32 sig_type=std_logic lab=rstn
+}
+C {devices/noconn.sym} 1060 -50 0 0 {name=l41
+}
+C {devices/vsource.sym} 450 -260 0 0 {name=V6 value=1.4
+}
+C {devices/lab_wire.sym} 450 -290 3 1 {name=l44 sig_type=std_logic lab=rstn
+}
+C {devices/gnd.sym} 450 -230 0 0 {name=l46 lab=GND}
diff --git a/xschem/tb/sar/tr_sar.sch b/xschem/tb/sar/tr_sar.sch
new file mode 100644
index 0000000..f40305a
--- /dev/null
+++ b/xschem/tb/sar/tr_sar.sch
@@ -0,0 +1,230 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+P 4 5 0 -660 1370 -660 1370 0 0 0 0 -660 {}
+P 4 2 500 -660 500 0 {}
+P 4 2 500 -310 0 -310 {}
+N 900 -220 930 -220 { lab=vss}
+N 900 -220 900 -190 { lab=vss}
+N 820 -220 820 -190 { lab=vdd}
+N 820 -130 820 -90 { lab=GND}
+N 900 -130 900 -90 { lab=GND}
+N 740 -220 770 -220 { lab=vinn}
+N 740 -220 740 -190 { lab=vinn}
+N 740 -130 740 -90 { lab=GND}
+N 640 -220 670 -220 { lab=vinp}
+N 640 -220 640 -190 { lab=vinp}
+N 640 -130 640 -90 { lab=GND}
+N 820 -220 850 -220 { lab=vdd}
+N 940 -450 1020 -450 { lab=result[7:0]}
+N 710 -360 710 -330 { lab=vss}
+N 750 -360 750 -330 { lab=vss}
+N 710 -570 710 -540 { lab=vdd}
+N 750 -570 750 -540 { lab=vdd}
+N 580 -400 610 -400 { lab=vinn}
+N 580 -500 610 -500 { lab=vinp}
+N 1090 -220 1120 -220 { lab=clk}
+N 1090 -220 1090 -190 { lab=clk}
+N 1090 -130 1090 -90 { lab=GND}
+N 840 -360 840 -330 { lab=clk}
+N 1090 -500 1120 -500 { lab=en}
+N 1090 -500 1090 -470 { lab=en}
+N 1090 -410 1090 -370 { lab=GND}
+N 870 -360 870 -330 { lab=en}
+N 940 -420 990 -420 { lab=valid}
+N 970 -220 1000 -220 { lab=cal}
+N 970 -220 970 -190 { lab=cal}
+N 970 -130 970 -90 { lab=GND}
+N 840 -570 840 -540 { lab=cal}
+N 50 -460 70 -460 { lab=GND}
+N 50 -600 70 -600 { lab=GND}
+N 50 -530 70 -530 { lab=GND}
+N 50 -390 70 -390 { lab=GND}
+N 540 -220 540 -190 { lab=rstn}
+N 540 -130 540 -90 { lab=GND}
+N 540 -220 570 -220 { lab=rstn}
+N 890 -360 890 -330 { lab=rstn}
+C {vsource.sym} 900 -160 0 0 {name=V1 value=0}
+C {vsource.sym} 820 -160 0 0 {name=V2 value=1.4
+}
+C {lab_wire.sym} 930 -220 0 0 {name=l7 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 850 -220 0 0 {name=l8 sig_type=std_logic lab=vdd}
+C {gnd.sym} 820 -90 0 0 {name=l11 lab=GND}
+C {gnd.sym} 900 -90 0 0 {name=l12 lab=GND}
+C {vsource.sym} 740 -160 0 0 {name=V4 value=vsign
+}
+C {lab_wire.sym} 770 -220 0 0 {name=l17 sig_type=std_logic lab=vinn}
+C {gnd.sym} 740 -90 0 0 {name=l18 lab=GND}
+C {vsource.sym} 640 -160 0 0 {name=V5 value=vsigp
+}
+C {lab_wire.sym} 670 -220 0 0 {name=l19 sig_type=std_logic lab=vinp}
+C {gnd.sym} 640 -90 0 0 {name=l20 lab=GND}
+C {code.sym} 270 -450 0 0 {name=STDCELLS only_toplevel=false
+format="tcleval(@value )"
+value="[sky130_models]"}
+C {code.sym} 80 -140 0 0 {name=CTL
+only_toplevel=false
+format="tcleval(@value )"
+value="*sar control
+
+*.options method trap
+*.options method gear
+
+.param MC_SWITCH=0
+.param vin=0.05
+.param vcm=0.7
+.param vsigp=\\"\{vcm + vin/2\}\\"
+.param vsign=\\"\{vcm - vin/2\}\\"
+
+.tran 100e-9 48e-6
+
+.control
+
+run
+
+meas tran d0 find v(xsar.res0) at=47e-6
+meas tran d1 find v(xsar.res1) at=47e-6
+meas tran d2 find v(xsar.res2) at=47e-6
+meas tran d3 find v(xsar.res3) at=47e-6
+meas tran d4 find v(xsar.res4) at=47e-6
+meas tran d5 find v(xsar.res5) at=47e-6
+meas tran d6 find v(xsar.res6) at=47e-6
+meas tran d7 find v(xsar.res7) at=47e-6
+
+print d0
+print d1
+print d2
+print d3
+print d4
+print d5
+print d6
+print d7
+
+eprvcd xsar.dclk xsar.den xsar.dsamp xsar.dctlp0 xsar.dctlp1 xsar.dctlp2 xsar.dctlp3 xsar.dctlp4 xsar.dctlp5 xsar.dctlp6 xsar.dctlp7 xsar.dctln0 xsar.dctln1 xsar.dctln2 xsar.dctln3 xsar.dctln4 xsar.dctln5 xsar.dctln6 xsar.dctln7 xsar.dcomp xsar.dsamp xsar.dvalid xsar.dtrim4 xsar.dtrim3 xsar.dtrim2 xsar.dtrim1 xsar.dtrim0 xsar.dtrimb4 xsar.dtrimb3 xsar.dtrimb2 xsar.dtrimb1 xsar.dtrimb0 xsar.dres0 xsar.dres1 xsar.dres2 xsar.dres3 xsar.dres4 xsar.dres5 xsar.dres6 xsar.dres7 > sarlogic.vcd
+display > \\"$design_path/sim/sar_nets.txt\\"
+edisplay > \\"$design_path/sim/sar_enets.txt\\"
+write sar_tb.raw
+*shell gtkwave \\"$design_path/sim/sarlogic.vcd\\" --script \\"$design_path/tools/scripts/gtkwave/nggtk.tcl\\" &
+
+.endc
+.end
+"
+tclcommand="exec xterm -geometry 100x40 -e nvim \\$::DESIGN_PATH\\/tb/sar/ctl.sp"}
+C {lab_wire.sym} 940 -450 0 1 {name=l15 sig_type=std_logic lab=result[7:0]
+}
+C {lab_wire.sym} 710 -360 3 0 {name=l16 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 750 -360 3 0 {name=l23 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 710 -540 3 1 {name=l24 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 750 -540 3 1 {name=l25 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 610 -400 0 0 {name=l27 sig_type=std_logic lab=vinn}
+C {lab_wire.sym} 610 -500 0 0 {name=l28 sig_type=std_logic lab=vinp}
+C {vsource.sym} 1090 -160 0 0 {name=Vclk value="PULSE(0 1 1e-9 1e-9 1e-9 2e-6 4e-6)"
+}
+C {lab_wire.sym} 1120 -220 0 0 {name=l31 sig_type=std_logic lab=clk
+}
+C {gnd.sym} 1090 -90 0 0 {name=l32 lab=GND}
+C {lab_wire.sym} 840 -360 3 0 {name=l33 sig_type=std_logic lab=clk
+}
+C {vsource.sym} 1090 -440 0 0 {name=Ven value="PULSE(0 1 0.5e-6 0.1e-6 0.1e-6 10e-6 10e-3)"
+}
+C {lab_wire.sym} 1120 -500 0 0 {name=l35 sig_type=std_logic lab=en
+}
+C {gnd.sym} 1090 -370 0 0 {name=l36 lab=GND}
+C {lab_wire.sym} 870 -360 3 0 {name=l37 sig_type=std_logic lab=en
+}
+C {code.sym} 240 -140 0 0 {name=CORNERS
+only_toplevel=true
+format="tcleval( @value )"
+spice_ignore="tcleval($cmdline_ignore)"
+value="
+* FET CORNERS
+.include \\\\$::SKYWATER_MODELS\\\\/corners/tt.spice
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/ff.spice
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/ss.spice
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/sf.spice
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/fs.spice
+
+* TT + R + C
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/tt_rmax_cmax.spice
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/tt_rmin_cmin.spice
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/tt_rmax_cmin.spice
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/tt_rmin_cmax.spice
+
+* FF + R + C
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/ff_rmax_cmax.spice
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/ff_rmin_cmin.spice
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/ff_rmax_cmin.spice
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/ff_rmin_cmax.spice
+
+
+* SS + R + C
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/ss_rmax_cmax.spice
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/ss_rmin_cmin.spice
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/ss_rmax_cmin.spice
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/ss_rmin_cmax.spice
+
+* SF + R + C
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/sf_rmax_cmax.spice
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/sf_rmin_cmin.spice
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/sf_rmax_cmin.spice
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/sf_rmin_cmax.spice
+
+* FS + R + C
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/fs_rmax_cmax.spice
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/fs_rmin_cmin.spice
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/fs_rmax_cmin.spice
+*.include \\\\$::SKYWATER_MODELS\\\\/corners/fs_rmin_cmax.spice
+"}
+C {lab_wire.sym} 940 -420 0 1 {name=l38 sig_type=std_logic lab=valid
+}
+C {noconn.sym} 990 -420 2 0 {name=l39}
+C {vsource.sym} 970 -160 0 0 {name=V3 value=0
+}
+C {lab_wire.sym} 1000 -220 0 0 {name=l40 sig_type=std_logic lab=cal
+}
+C {gnd.sym} 970 -90 0 0 {name=l43 lab=GND}
+C {lab_wire.sym} 840 -540 3 1 {name=l44 sig_type=std_logic lab=cal
+}
+C {xschem_sky130/sky130_stdcells/inv_4.sym} 110 -460 0 0 {name=x2 VGND=VGND VNB=VNB VPB=VPB VPWR=VPWR prefix=sky130_fd_sc_hd__ }
+C {noconn.sym} 150 -460 2 0 {name=l41}
+C {gnd.sym} 50 -460 0 0 {name=l42 lab=GND}
+C {xschem_sky130/sky130_stdcells/decap_8.sym} 330 -620 0 0 {name=x6 VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__
+}
+C {xschem_library/devices/launcher.sym} 150 -260 0 0 {name=h1
+descr="simulation netlist"
+tclcommand="set dummy_ignore true"
+}
+C {xschem_sky130/sky130_stdcells/decap_3.sym} 330 -580 0 0 {name=x8 VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__
+}
+C {noconn.sym} 1020 -450 2 0 {name=l49[7:0]
+}
+C {gnd.sym} 50 -600 0 0 {name=l2 lab=GND}
+C {noconn.sym} 150 -600 2 0 {name=l3}
+C {xschem_sky130/sky130_stdcells/buf_1.sym} 110 -600 0 0 {name=x3 VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__
+}
+C {sar/sar/sar.sym} 890 -270 0 0 {name=xsar
+}
+C {gnd.sym} 50 -530 0 0 {name=l10 lab=GND}
+C {noconn.sym} 150 -530 2 0 {name=l13}
+C {xschem_sky130/sky130_stdcells/inv_1.sym} 110 -530 0 0 {name=x4 VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__
+}
+C {xschem_sky130/sky130_stdcells/inv_2.sym} 110 -390 0 0 {name=x1 VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__
+}
+C {gnd.sym} 50 -390 0 0 {name=l1 lab=GND}
+C {noconn.sym} 150 -390 2 0 {name=l4}
+C {vsource.sym} 540 -160 0 0 {name=V7 value=1.4
+}
+C {lab_wire.sym} 570 -220 0 0 {name=l5 sig_type=std_logic lab=rstn
+}
+C {gnd.sym} 540 -90 0 0 {name=l6 lab=GND}
+C {lab_wire.sym} 890 -360 3 0 {name=l9 sig_type=std_logic lab=rstn
+}
+C {xschem_sky130/sky130_stdcells/tap_2.sym} 330 -540 0 0 {name=x5 VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__
+}
+C {xschem_library/devices/launcher.sym} 150 -210 0 0 {name=h2
+descr="lvs netlist"
+tclcommand="set dummy_ignore false"
+}
diff --git a/xschem/test.data b/xschem/test.data
deleted file mode 100644
index c9cde37..0000000
--- a/xschem/test.data
+++ /dev/null
@@ -1,101 +0,0 @@
- 7.00000000e-01 -8.93059159e-08 7.00000000e-01 7.00000000e-01
- 7.01000000e-01 -9.08452852e-08 7.01000000e-01 7.01000000e-01
- 7.02000000e-01 -9.24385447e-08 7.02000000e-01 7.02000000e-01
- 7.03000000e-01 -9.40459956e-08 7.03000000e-01 7.03000000e-01
- 7.04000000e-01 -9.56814959e-08 7.04000000e-01 7.04000000e-01
- 7.05000000e-01 -9.73455368e-08 7.05000000e-01 7.05000000e-01
- 7.06000000e-01 -9.90386085e-08 7.06000000e-01 7.06000000e-01
- 7.07000000e-01 -1.00761227e-07 7.07000000e-01 7.07000000e-01
- 7.08000000e-01 -1.02513882e-07 7.08000000e-01 7.08000000e-01
- 7.09000000e-01 -1.04297110e-07 7.09000000e-01 7.09000000e-01
- 7.10000000e-01 -1.06111443e-07 7.10000000e-01 7.10000000e-01
- 7.11000000e-01 -1.07957415e-07 7.11000000e-01 7.11000000e-01
- 7.12000000e-01 -1.09835552e-07 7.12000000e-01 7.12000000e-01
- 7.13000000e-01 -1.11746436e-07 7.13000000e-01 7.13000000e-01
- 7.14000000e-01 -1.13690603e-07 7.14000000e-01 7.14000000e-01
- 7.15000000e-01 -1.15668634e-07 7.15000000e-01 7.15000000e-01
- 7.16000000e-01 -1.17681129e-07 7.16000000e-01 7.16000000e-01
- 7.17000000e-01 -1.19728657e-07 7.17000000e-01 7.17000000e-01
- 7.18000000e-01 -1.21811839e-07 7.18000000e-01 7.18000000e-01
- 7.19000000e-01 -1.23931259e-07 7.19000000e-01 7.19000000e-01
- 7.20000000e-01 -1.26087554e-07 7.20000000e-01 7.20000000e-01
- 7.21000000e-01 -1.28281358e-07 7.21000000e-01 7.21000000e-01
- 7.22000000e-01 -1.30513286e-07 7.22000000e-01 7.22000000e-01
- 7.23000000e-01 -1.32784003e-07 7.23000000e-01 7.23000000e-01
- 7.24000000e-01 -1.35094165e-07 7.24000000e-01 7.24000000e-01
- 7.25000000e-01 -1.37444453e-07 7.25000000e-01 7.25000000e-01
- 7.26000000e-01 -1.39835535e-07 7.26000000e-01 7.26000000e-01
- 7.27000000e-01 -1.42268085e-07 7.27000000e-01 7.27000000e-01
- 7.28000000e-01 -1.44742842e-07 7.28000000e-01 7.28000000e-01
- 7.29000000e-01 -1.47260486e-07 7.29000000e-01 7.29000000e-01
- 7.30000000e-01 -1.49821761e-07 7.30000000e-01 7.30000000e-01
- 7.31000000e-01 -1.52427364e-07 7.31000000e-01 7.31000000e-01
- 7.32000000e-01 -1.55078077e-07 7.32000000e-01 7.32000000e-01
- 7.33000000e-01 -1.57774611e-07 7.33000000e-01 7.33000000e-01
- 7.34000000e-01 -1.60517775e-07 7.34000000e-01 7.34000000e-01
- 7.35000000e-01 -1.63308337e-07 7.35000000e-01 7.35000000e-01
- 7.36000000e-01 -1.66147061e-07 7.36000000e-01 7.36000000e-01
- 7.37000000e-01 -1.69034765e-07 7.37000000e-01 7.37000000e-01
- 7.38000000e-01 -1.71972266e-07 7.38000000e-01 7.38000000e-01
- 7.39000000e-01 -1.74960357e-07 7.39000000e-01 7.39000000e-01
- 7.40000000e-01 -1.77999888e-07 7.40000000e-01 7.40000000e-01
- 7.41000000e-01 -1.81091703e-07 7.41000000e-01 7.41000000e-01
- 7.42000000e-01 -1.84236664e-07 7.42000000e-01 7.42000000e-01
- 7.43000000e-01 -1.87435634e-07 7.43000000e-01 7.43000000e-01
- 7.44000000e-01 -1.90689493e-07 7.44000000e-01 7.44000000e-01
- 7.45000000e-01 -1.93999127e-07 7.45000000e-01 7.45000000e-01
- 7.46000000e-01 -1.97365464e-07 7.46000000e-01 7.46000000e-01
- 7.47000000e-01 -2.00789378e-07 7.47000000e-01 7.47000000e-01
- 7.48000000e-01 -2.04271837e-07 7.48000000e-01 7.48000000e-01
- 7.49000000e-01 -2.07813739e-07 7.49000000e-01 7.49000000e-01
- 7.50000000e-01 -2.11416073e-07 7.50000000e-01 7.50000000e-01
- 7.51000000e-01 -2.15079797e-07 7.51000000e-01 7.51000000e-01
- 7.52000000e-01 -2.18805863e-07 7.52000000e-01 7.52000000e-01
- 7.53000000e-01 -2.22595278e-07 7.53000000e-01 7.53000000e-01
- 7.54000000e-01 -2.26449036e-07 7.54000000e-01 7.54000000e-01
- 7.55000000e-01 -2.30368144e-07 7.55000000e-01 7.55000000e-01
- 7.56000000e-01 -2.34353630e-07 7.56000000e-01 7.56000000e-01
- 7.57000000e-01 -2.38406548e-07 7.57000000e-01 7.57000000e-01
- 7.58000000e-01 -2.42527913e-07 7.58000000e-01 7.58000000e-01
- 7.59000000e-01 -2.46718795e-07 7.59000000e-01 7.59000000e-01
- 7.60000000e-01 -2.50980278e-07 7.60000000e-01 7.60000000e-01
- 7.61000000e-01 -2.55313430e-07 7.61000000e-01 7.61000000e-01
- 7.62000000e-01 -2.59719344e-07 7.62000000e-01 7.62000000e-01
- 7.63000000e-01 -2.64199148e-07 7.63000000e-01 7.63000000e-01
- 7.64000000e-01 -2.68753946e-07 7.64000000e-01 7.64000000e-01
- 7.65000000e-01 -2.73384860e-07 7.65000000e-01 7.65000000e-01
- 7.66000000e-01 -2.78093044e-07 7.66000000e-01 7.66000000e-01
- 7.67000000e-01 -2.82879650e-07 7.67000000e-01 7.67000000e-01
- 7.68000000e-01 -2.87745826e-07 7.68000000e-01 7.68000000e-01
- 7.69000000e-01 -2.92692776e-07 7.69000000e-01 7.69000000e-01
- 7.70000000e-01 -2.97721660e-07 7.70000000e-01 7.70000000e-01
- 7.71000000e-01 -3.02833688e-07 7.71000000e-01 7.71000000e-01
- 7.72000000e-01 -3.08030053e-07 7.72000000e-01 7.72000000e-01
- 7.73000000e-01 -3.13311974e-07 7.73000000e-01 7.73000000e-01
- 7.74000000e-01 -3.18680710e-07 7.74000000e-01 7.74000000e-01
- 7.75000000e-01 -3.24137468e-07 7.75000000e-01 7.75000000e-01
- 7.76000000e-01 -3.29683509e-07 7.76000000e-01 7.76000000e-01
- 7.77000000e-01 -3.35320078e-07 7.77000000e-01 7.77000000e-01
- 7.78000000e-01 -3.41048451e-07 7.78000000e-01 7.78000000e-01
- 7.79000000e-01 -3.46869908e-07 7.79000000e-01 7.79000000e-01
- 7.80000000e-01 -3.52785731e-07 7.80000000e-01 7.80000000e-01
- 7.81000000e-01 -3.58797218e-07 7.81000000e-01 7.81000000e-01
- 7.82000000e-01 -3.64905663e-07 7.82000000e-01 7.82000000e-01
- 7.83000000e-01 -3.71112381e-07 7.83000000e-01 7.83000000e-01
- 7.84000000e-01 -3.77418703e-07 7.84000000e-01 7.84000000e-01
- 7.85000000e-01 -3.83825919e-07 7.85000000e-01 7.85000000e-01
- 7.86000000e-01 -3.90335390e-07 7.86000000e-01 7.86000000e-01
- 7.87000000e-01 -3.96948455e-07 7.87000000e-01 7.87000000e-01
- 7.88000000e-01 -4.03666461e-07 7.88000000e-01 7.88000000e-01
- 7.89000000e-01 -4.10490750e-07 7.89000000e-01 7.89000000e-01
- 7.90000000e-01 -4.17422681e-07 7.90000000e-01 7.90000000e-01
- 7.91000000e-01 -4.24463629e-07 7.91000000e-01 7.91000000e-01
- 7.92000000e-01 -4.31614946e-07 7.92000000e-01 7.92000000e-01
- 7.93000000e-01 -4.38878017e-07 7.93000000e-01 7.93000000e-01
- 7.94000000e-01 -4.46254218e-07 7.94000000e-01 7.94000000e-01
- 7.95000000e-01 -4.53744916e-07 7.95000000e-01 7.95000000e-01
- 7.96000000e-01 -4.61351506e-07 7.96000000e-01 7.96000000e-01
- 7.97000000e-01 -4.69075369e-07 7.97000000e-01 7.97000000e-01
- 7.98000000e-01 -4.76917893e-07 7.98000000e-01 7.98000000e-01
- 7.99000000e-01 -4.84880471e-07 7.99000000e-01 7.99000000e-01
- 8.00000000e-01 -4.92964482e-07 8.00000000e-01 8.00000000e-01
diff --git a/xschem/threshold_test_tb.spice b/xschem/threshold_test_tb.spice
deleted file mode 100644
index 3e9804c..0000000
--- a/xschem/threshold_test_tb.spice
+++ /dev/null
@@ -1,46 +0,0 @@
-*---------------------------------------------------------------------------
-* SPDX-FileCopyrightText: 2020 Efabless Corporation
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* https://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*
-* SPDX-License-Identifier: Apache-2.0
-*---------------------------------------------------------------------------
-* Threshold test for POR circuit
-* Determine gate voltage at which the HV NFET draws 240nA nominal
-*
-* Result: 0.7575V
-*-------------------------------------------------------------------
-
-.lib /usr/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
-
-*----------------------------
-* Testbench circuit
-*----------------------------
-Rtest vdda mir1 1MEG
-Xm1 mir1 vin vss vss sky130_fd_pr__nfet_g5v0d10v5 w=2 l=0.8
-
-Vgate vin vss DC=0
-Vpwr vdda vss DC=3.3
-Rgnd vss 0 0.1
-
-*----------------------------
-* Testbench control
-*----------------------------
-.control
-* DC sweep from 0.7 to 0.8V
-dc Vgate 0.7 0.8 0.001
-wrdata test.data Vpwr#branch vin
-
-.endc
-
-.end
-
diff --git a/xschem/xschem/corners/ff.spice b/xschem/xschem/corners/ff.spice
new file mode 100644
index 0000000..2d5e0e1
--- /dev/null
+++ b/xschem/xschem/corners/ff.spice
@@ -0,0 +1,17 @@
+* FET FF
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__ff.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__ff.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__ff.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__ff.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__ff.corner.spice
+.include sky130_fd_pr_ngspice/latest/models/all.spice
+.include sky130_fd_pr_ngspice/latest/models/corners/ff/nonfet.spice
+
+* R+C typical
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_typical__cap_typical.spice
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_typical__cap_typical__lin.spice
diff --git a/xschem/xschem/corners/ff_rmax_cmax.spice b/xschem/xschem/corners/ff_rmax_cmax.spice
new file mode 100644
index 0000000..dadff19
--- /dev/null
+++ b/xschem/xschem/corners/ff_rmax_cmax.spice
@@ -0,0 +1,17 @@
+* FET FF
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__ff.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__ff.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__ff.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__ff.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__ff.corner.spice
+.include sky130_fd_pr_ngspice/latest/models/all.spice
+.include sky130_fd_pr_ngspice/latest/models/corners/ff/nonfet.spice
+
+* R max C max
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_high__cap_high.spice
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_high__cap_high__lin.spice
diff --git a/xschem/xschem/corners/ff_rmax_cmin.spice b/xschem/xschem/corners/ff_rmax_cmin.spice
new file mode 100644
index 0000000..135e7b8
--- /dev/null
+++ b/xschem/xschem/corners/ff_rmax_cmin.spice
@@ -0,0 +1,17 @@
+* FET FF
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__ff.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__ff.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__ff.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__ff.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__ff.corner.spice
+.include sky130_fd_pr_ngspice/latest/models/all.spice
+.include sky130_fd_pr_ngspice/latest/models/corners/ff/nonfet.spice
+
+* R max C min
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_high__cap_low.spice
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_high__cap_low__lin.spice
diff --git a/xschem/xschem/corners/ff_rmin_cmax.spice b/xschem/xschem/corners/ff_rmin_cmax.spice
new file mode 100644
index 0000000..a3f0d73
--- /dev/null
+++ b/xschem/xschem/corners/ff_rmin_cmax.spice
@@ -0,0 +1,17 @@
+* FET FF
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__ff.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__ff.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__ff.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__ff.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__ff.corner.spice
+.include sky130_fd_pr_ngspice/latest/models/all.spice
+.include sky130_fd_pr_ngspice/latest/models/corners/ff/nonfet.spice
+
+* R min C max
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_low__cap_high.spice
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_low__cap_high__lin.spice
diff --git a/xschem/xschem/corners/ff_rmin_cmin.spice b/xschem/xschem/corners/ff_rmin_cmin.spice
new file mode 100644
index 0000000..33e3b3d
--- /dev/null
+++ b/xschem/xschem/corners/ff_rmin_cmin.spice
@@ -0,0 +1,17 @@
+* FET FF
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__ff.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__ff.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__ff.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__ff.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__ff.corner.spice
+.include sky130_fd_pr_ngspice/latest/models/all.spice
+.include sky130_fd_pr_ngspice/latest/models/corners/ff/nonfet.spice
+
+* R min C min
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_low__cap_low.spice
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_low__cap_low__lin.spice
diff --git a/xschem/xschem/corners/fs.spice b/xschem/xschem/corners/fs.spice
new file mode 100644
index 0000000..8237588
--- /dev/null
+++ b/xschem/xschem/corners/fs.spice
@@ -0,0 +1,17 @@
+* FET FS
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__fs.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__fs.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__fs.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__fs.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__fs.corner.spice
+.include sky130_fd_pr_ngspice/latest/models/all.spice
+.include sky130_fd_pr_ngspice/latest/models/corners/fs/nonfet.spice
+
+* R+C typical
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_typical__cap_typical.spice
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_typical__cap_typical__lin.spice
diff --git a/xschem/xschem/corners/fs_rmax_cmax.spice b/xschem/xschem/corners/fs_rmax_cmax.spice
new file mode 100644
index 0000000..071ce4d
--- /dev/null
+++ b/xschem/xschem/corners/fs_rmax_cmax.spice
@@ -0,0 +1,17 @@
+* FET FS
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__fs.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__fs.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__fs.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__fs.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__fs.corner.spice
+.include sky130_fd_pr_ngspice/latest/models/all.spice
+.include sky130_fd_pr_ngspice/latest/models/corners/fs/nonfet.spice
+
+* R max C max
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_high__cap_high.spice
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_high__cap_high__lin.spice
diff --git a/xschem/xschem/corners/fs_rmax_cmin.spice b/xschem/xschem/corners/fs_rmax_cmin.spice
new file mode 100644
index 0000000..b5b6102
--- /dev/null
+++ b/xschem/xschem/corners/fs_rmax_cmin.spice
@@ -0,0 +1,17 @@
+* FET FS
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__fs.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__fs.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__fs.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__fs.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__fs.corner.spice
+.include sky130_fd_pr_ngspice/latest/models/all.spice
+.include sky130_fd_pr_ngspice/latest/models/corners/fs/nonfet.spice
+
+* R max C min
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_high__cap_low.spice
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_high__cap_low__lin.spice
diff --git a/xschem/xschem/corners/fs_rmin_cmax.spice b/xschem/xschem/corners/fs_rmin_cmax.spice
new file mode 100644
index 0000000..5d76806
--- /dev/null
+++ b/xschem/xschem/corners/fs_rmin_cmax.spice
@@ -0,0 +1,17 @@
+* FET FS
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__fs.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__fs.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__fs.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__fs.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__fs.corner.spice
+.include sky130_fd_pr_ngspice/latest/models/all.spice
+.include sky130_fd_pr_ngspice/latest/models/corners/fs/nonfet.spice
+
+* R min C max
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_low__cap_high.spice
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_low__cap_high__lin.spice
diff --git a/xschem/xschem/corners/fs_rmin_cmin.spice b/xschem/xschem/corners/fs_rmin_cmin.spice
new file mode 100644
index 0000000..d5a434b
--- /dev/null
+++ b/xschem/xschem/corners/fs_rmin_cmin.spice
@@ -0,0 +1,17 @@
+* FET FS
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__fs.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__fs.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__fs.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__fs.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__fs.corner.spice
+.include sky130_fd_pr_ngspice/latest/models/all.spice
+.include sky130_fd_pr_ngspice/latest/models/corners/fs/nonfet.spice
+
+* R min C min
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_low__cap_low.spice
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_low__cap_low__lin.spice
diff --git a/xschem/xschem/corners/sf.spice b/xschem/xschem/corners/sf.spice
new file mode 100644
index 0000000..92850e4
--- /dev/null
+++ b/xschem/xschem/corners/sf.spice
@@ -0,0 +1,17 @@
+* FET SF
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__sf.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__sf.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__sf.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__sf.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__sf.corner.spice
+.include sky130_fd_pr_ngspice/latest/models/all.spice
+.include sky130_fd_pr_ngspice/latest/models/corners/sf/nonfet.spice
+
+* R+C typical
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_typical__cap_typical.spice
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_typical__cap_typical__lin.spice
diff --git a/xschem/xschem/corners/sf_rmax_cmax.spice b/xschem/xschem/corners/sf_rmax_cmax.spice
new file mode 100644
index 0000000..ee092f6
--- /dev/null
+++ b/xschem/xschem/corners/sf_rmax_cmax.spice
@@ -0,0 +1,17 @@
+* FET SF
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__sf.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__sf.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__sf.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__sf.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__sf.corner.spice
+.include sky130_fd_pr_ngspice/latest/models/all.spice
+.include sky130_fd_pr_ngspice/latest/models/corners/sf/nonfet.spice
+
+* R max C max
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_high__cap_high.spice
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_high__cap_high__lin.spice
diff --git a/xschem/xschem/corners/sf_rmax_cmin.spice b/xschem/xschem/corners/sf_rmax_cmin.spice
new file mode 100644
index 0000000..c60e75d
--- /dev/null
+++ b/xschem/xschem/corners/sf_rmax_cmin.spice
@@ -0,0 +1,17 @@
+* FET SF
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__sf.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__sf.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__sf.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__sf.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__sf.corner.spice
+.include sky130_fd_pr_ngspice/latest/models/all.spice
+.include sky130_fd_pr_ngspice/latest/models/corners/sf/nonfet.spice
+
+* R max C min
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_high__cap_low.spice
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_high__cap_low__lin.spice
diff --git a/xschem/xschem/corners/sf_rmin_cmax.spice b/xschem/xschem/corners/sf_rmin_cmax.spice
new file mode 100644
index 0000000..26032cd
--- /dev/null
+++ b/xschem/xschem/corners/sf_rmin_cmax.spice
@@ -0,0 +1,17 @@
+* FET SF
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__sf.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__sf.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__sf.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__sf.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__sf.corner.spice
+.include sky130_fd_pr_ngspice/latest/models/all.spice
+.include sky130_fd_pr_ngspice/latest/models/corners/sf/nonfet.spice
+
+* R min C max
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_low__cap_high.spice
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_low__cap_high__lin.spice
diff --git a/xschem/xschem/corners/sf_rmin_cmin.spice b/xschem/xschem/corners/sf_rmin_cmin.spice
new file mode 100644
index 0000000..01afea4
--- /dev/null
+++ b/xschem/xschem/corners/sf_rmin_cmin.spice
@@ -0,0 +1,17 @@
+* FET SF
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__sf.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__sf.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__sf.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__sf.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__sf.corner.spice
+.include sky130_fd_pr_ngspice/latest/models/all.spice
+.include sky130_fd_pr_ngspice/latest/models/corners/sf/nonfet.spice
+
+* R min C min
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_low__cap_low.spice
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_low__cap_low__lin.spice
diff --git a/xschem/xschem/corners/ss.spice b/xschem/xschem/corners/ss.spice
new file mode 100644
index 0000000..b668155
--- /dev/null
+++ b/xschem/xschem/corners/ss.spice
@@ -0,0 +1,17 @@
+* FET SS
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__ss.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__ss.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__ss.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__ss.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__ss.corner.spice
+.include sky130_fd_pr_ngspice/latest/models/all.spice
+.include sky130_fd_pr_ngspice/latest/models/corners/ss/nonfet.spice
+
+* R+C typical
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_typical__cap_typical.spice
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_typical__cap_typical__lin.spice
diff --git a/xschem/xschem/corners/ss_rmax_cmax.spice b/xschem/xschem/corners/ss_rmax_cmax.spice
new file mode 100644
index 0000000..8568259
--- /dev/null
+++ b/xschem/xschem/corners/ss_rmax_cmax.spice
@@ -0,0 +1,17 @@
+* FET SS
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__ss.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__ss.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__ss.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__ss.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__ss.corner.spice
+.include sky130_fd_pr_ngspice/latest/models/all.spice
+.include sky130_fd_pr_ngspice/latest/models/corners/ss/nonfet.spice
+
+* R max C max
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_high__cap_high.spice
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_high__cap_high__lin.spice
diff --git a/xschem/xschem/corners/ss_rmax_cmin.spice b/xschem/xschem/corners/ss_rmax_cmin.spice
new file mode 100644
index 0000000..6b51441
--- /dev/null
+++ b/xschem/xschem/corners/ss_rmax_cmin.spice
@@ -0,0 +1,17 @@
+* FET SS
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__ss.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__ss.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__ss.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__ss.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__ss.corner.spice
+.include sky130_fd_pr_ngspice/latest/models/all.spice
+.include sky130_fd_pr_ngspice/latest/models/corners/ss/nonfet.spice
+
+* R max C min
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_high__cap_low.spice
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_high__cap_low__lin.spice
diff --git a/xschem/xschem/corners/ss_rmin_cmax.spice b/xschem/xschem/corners/ss_rmin_cmax.spice
new file mode 100644
index 0000000..cead652
--- /dev/null
+++ b/xschem/xschem/corners/ss_rmin_cmax.spice
@@ -0,0 +1,17 @@
+* FET SS
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__ss.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__ss.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__ss.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__ss.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__ss.corner.spice
+.include sky130_fd_pr_ngspice/latest/models/all.spice
+.include sky130_fd_pr_ngspice/latest/models/corners/ss/nonfet.spice
+
+* R min C
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_low__cap_high.spice
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_low__cap_high__lin.spice
diff --git a/xschem/xschem/corners/ss_rmin_cmin.spice b/xschem/xschem/corners/ss_rmin_cmin.spice
new file mode 100644
index 0000000..af25386
--- /dev/null
+++ b/xschem/xschem/corners/ss_rmin_cmin.spice
@@ -0,0 +1,17 @@
+* FET SS
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__ss.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__ss.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__ss.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__ss.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__ss.corner.spice
+.include sky130_fd_pr_ngspice/latest/models/all.spice
+.include sky130_fd_pr_ngspice/latest/models/corners/ss/nonfet.spice
+
+* R min C min
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_low__cap_low.spice
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_low__cap_low__lin.spice
diff --git a/xschem/xschem/corners/tt.spice b/xschem/xschem/corners/tt.spice
new file mode 100644
index 0000000..f6595e3
--- /dev/null
+++ b/xschem/xschem/corners/tt.spice
@@ -0,0 +1,17 @@
+* FET typical
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__tt.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__tt.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__tt.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__tt.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__tt.corner.spice
+.include sky130_fd_pr_ngspice/latest/models/all.spice
+.include sky130_fd_pr_ngspice/latest/models/corners/tt/nonfet.spice
+
+* R+C typical
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_typical__cap_typical.spice
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_typical__cap_typical__lin.spice
diff --git a/xschem/xschem/corners/tt_rmax_cmax.spice b/xschem/xschem/corners/tt_rmax_cmax.spice
new file mode 100644
index 0000000..f7fc6a0
--- /dev/null
+++ b/xschem/xschem/corners/tt_rmax_cmax.spice
@@ -0,0 +1,17 @@
+* FET typical
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__tt.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__tt.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__tt.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__tt.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__tt.corner.spice
+.include sky130_fd_pr_ngspice/latest/models/all.spice
+.include sky130_fd_pr_ngspice/latest/models/corners/tt/nonfet.spice
+
+* R max C max
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_high__cap_high.spice
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_high__cap_high__lin.spice
diff --git a/xschem/xschem/corners/tt_rmax_cmin.spice b/xschem/xschem/corners/tt_rmax_cmin.spice
new file mode 100644
index 0000000..2f04ee2
--- /dev/null
+++ b/xschem/xschem/corners/tt_rmax_cmin.spice
@@ -0,0 +1,17 @@
+* FET typical
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__tt.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__tt.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__tt.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__tt.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__tt.corner.spice
+.include sky130_fd_pr_ngspice/latest/models/all.spice
+.include sky130_fd_pr_ngspice/latest/models/corners/tt/nonfet.spice
+
+* R max C min
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_high__cap_low.spice
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_high__cap_low__lin.spice
diff --git a/xschem/xschem/corners/tt_rmin_cmax.spice b/xschem/xschem/corners/tt_rmin_cmax.spice
new file mode 100644
index 0000000..09dd6a6
--- /dev/null
+++ b/xschem/xschem/corners/tt_rmin_cmax.spice
@@ -0,0 +1,17 @@
+* FET typical
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__tt.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__tt.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__tt.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__tt.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__tt.corner.spice
+.include sky130_fd_pr_ngspice/latest/models/all.spice
+.include sky130_fd_pr_ngspice/latest/models/corners/tt/nonfet.spice
+
+* R min C max
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_low__cap_high.spice
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_low__cap_high__lin.spice
diff --git a/xschem/xschem/corners/tt_rmin_cmin.spice b/xschem/xschem/corners/tt_rmin_cmin.spice
new file mode 100644
index 0000000..cafd977
--- /dev/null
+++ b/xschem/xschem/corners/tt_rmin_cmin.spice
@@ -0,0 +1,17 @@
+* FET typical
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__tt.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__tt.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8__tt.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__tt.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__mismatch.corner.spice
+.include sky130_fd_pr_ngspice/latest/cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__tt.corner.spice
+.include sky130_fd_pr_ngspice/latest/models/all.spice
+.include sky130_fd_pr_ngspice/latest/models/corners/tt/nonfet.spice
+
+* R min C min
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_low__cap_low.spice
+.include sky130_fd_pr_ngspice/latest/models/r+c/res_low__cap_low__lin.spice
diff --git a/xschem/xschem/scripts/corner_preproc.sh b/xschem/xschem/scripts/corner_preproc.sh
new file mode 100755
index 0000000..c4374cc
--- /dev/null
+++ b/xschem/xschem/scripts/corner_preproc.sh
@@ -0,0 +1,24 @@
+#!/bin/bash
+#-----------------------------------------------------------
+#
+# SYNOPSIS:
+# corner_preproces.sh
+#
+#
+# DESCRIPTION
+# Simple preprocessor script to update the
+# corners to point to the path of the PDK.
+#
+#
+#-----------------------------------------------------------
+
+PDKPATH=${SKY130_PDK_PATH}
+CORNERPATH="$PDKPATH/sky130_fd_pr_ngspice/latest/corners/"
+TEMPLATE_CORNER_PATH="../corners"
+
+if [ ! -d "$CORNERPATH" ]; then
+ mkdir -p $CORNERPATH
+fi
+for file in $(ls $TEMPLATE_CORNER_PATH); do
+ sed "s|^\.include |\.include $PDKPATH/|" ../corners/$file > "$PDKPATH/sky130_fd_pr_ngspice/latest/corners/$file"
+done
diff --git a/xschem/xschem/scripts/get_pdk.sh b/xschem/xschem/scripts/get_pdk.sh
new file mode 100755
index 0000000..1ca22b3
--- /dev/null
+++ b/xschem/xschem/scripts/get_pdk.sh
@@ -0,0 +1,15 @@
+#!/bin/bash
+
+git clone https://github.com/google/skywater-pdk
+cd skywater-pdk
+# git submodule init libraries/sky130_fd_io/latest
+git submodule init libraries/sky130_fd_pr/latest
+git submodule init libraries/sky130_fd_sc_hd/latest
+# git submodule init libraries/sky130_fd_sc_hvl/latest
+# git submodule init libraries/sky130_fd_sc_hdll/latest
+# git submodule init libraries/sky130_fd_sc_hs/latest
+# git submodule init libraries/sky130_fd_sc_ms/latest
+# git submodule init libraries/sky130_fd_sc_ls/latest
+# git submodule init libraries/sky130_fd_sc_lp/latest
+git submodule update
+cp -r libraries/sky130_fd_pr libraries/sky130_fd_pr_ngspice
diff --git a/xschem/xschem/scripts/sky130_models.tcl b/xschem/xschem/scripts/sky130_models.tcl
new file mode 100644
index 0000000..f5e4770
--- /dev/null
+++ b/xschem/xschem/scripts/sky130_models.tcl
@@ -0,0 +1,21 @@
+proc sky130_models {} {
+ global SKYWATER_STDCELLS
+ set l {}
+ if {![info exists SKYWATER_STDCELLS]} {
+ puts "ERROR: SKYWATER_STDCELLS TCL variable undefined, please set in xschemrc and restart xschem"
+ return {***** ERROR: missing TCL var SKYWATER_STDCELLS}
+ }
+ foreach i [xschem symbols] {
+ if { [regexp {stdcells} $i] } {
+ set cell [lindex ${i} 1]
+ regsub {/latest *$} $SKYWATER_STDCELLS {} prefix
+ regsub {.*/} $prefix {} prefix
+ append prefix __
+ regsub {.*/} $cell {} cell
+ regsub {\.sym} $cell {.spice} spice
+ regsub {_[^_]+\.sym} $cell {} dir
+ append l .include\ $SKYWATER_STDCELLS/cells/$dir/$prefix$spice\n
+ }
+ }
+ return $l
+}
diff --git a/xschem/xschemrc b/xschem/xschemrc
index ca6e33e..f899691 100644
--- a/xschem/xschemrc
+++ b/xschem/xschemrc
@@ -1,51 +1,80 @@
-#### xschemrc system configuration file
+#----------------------------------------------------------------------
+# PATH DEFINITIONS
+#----------------------------------------------------------------------
+set DESIGN_PATH [exec pwd]
+set PDK_PATH $env(SKY130_PDK_PATH)
-#### values may be overridden by user's ~/.xschem/xschemrc configuration file
-#### or by project-local ./xschemrc
+#----------------------------------------------------------------------
+# xschem system-wide design library paths: xschem_library_path
+#----------------------------------------------------------------------
+append XSCHEM_LIBRARY_PATH :${DESIGN_PATH}
+append XSCHEM_LIBRARY_PATH :${DESIGN_PATH}/xschem/symbols
+set XSCHEM_SKY130_SCRIPTS_PATH ${DESIGN_PATH}/xschem/scripts
-###########################################################################
-#### XSCHEM INSTALLATION DIRECTORY: XSCHEM_SHAREDIR
-###########################################################################
-#### Normally there is no reason to set this variable if using standard
-#### installation. Location of files is set at compile time but may be overridden
-#### with following line:
-# set XSCHEM_SHAREDIR $env(HOME)/share/xschem
+#----------------------------------------------------------------------
+# window to open on startup: xschem_start_window
+#----------------------------------------------------------------------
+set XSCHEM_START_WINDOW ${DESIGN_PATH}/top/top.sch
-###########################################################################
-#### XSCHEM SYSTEM-WIDE DESIGN LIBRARY PATHS: XSCHEM_LIBRARY_PATH
-###########################################################################
-#### If unset xschem starts with XSCHEM_LIBRARY_PATH set to the default, typically:
-# /home/schippes/.xschem/xschem_library
-# /home/schippes/share/xschem/xschem_library/devices
-# /home/schippes/share/doc/xschem/examples
-# /home/schippes/share/doc/xschem/ngspice
-# /home/schippes/share/doc/xschem/logic
-# /home/schippes/share/doc/xschem/xschem_simulator
-# /home/schippes/share/doc/xschem/binto7seg
-# /home/schippes/share/doc/xschem/pcb
-# /home/schippes/share/doc/xschem/rom8k
+#----------------------------------------------------------------------
+# DIRECTORY WHERE SIMULATIONS, NETLIST AND SIMULATOR OUTPUTS ARE PLACED
+#----------------------------------------------------------------------
+set netlist_dir ${DESIGN_PATH}/../sim
-#### Allow user environment to override the path to the PDK
-if {[catch {set PDKPATH $env(PDKPATH)}]} {
- set PDKPATH "/usr/share/pdk/sky130A"
-}
-#### Flush any previous definition
-set XSCHEM_LIBRARY_PATH {}
-#### include devices/*.sym
-append XSCHEM_LIBRARY_PATH ${XSCHEM_SHAREDIR}/xschem_library
-#### include skywater libraries. Here i use [pwd]. This works if i start xschem from here.
-append XSCHEM_LIBRARY_PATH :$env(PWD)
-append XSCHEM_LIBRARY_PATH :$PDKPATH/libs.tech/xschem
-# append XSCHEM_LIBRARY_PATH :/mnt/sda7/home/schippes/pdks/sky130A/libs.tech/xschem
-#### add ~/.xschem/xschem_library (USER_CONF_DIR is normally ~/.xschem)
-append XSCHEM_LIBRARY_PATH :$USER_CONF_DIR/xschem_library
+#----------------------------------------------------------------------
+# change default [] with some other characters for bussed signals
+# in spice netlists (example: data[7] --> data<7>)
+# set bus_replacement_char {<>}
+#----------------------------------------------------------------------
+set bus_replacement_char {__}
-###########################################################################
-#### SET CUSTOM COLORS FOR XSCHEM LIBRARIES MATCHING CERTAIN PATTERNS
-###########################################################################
-#### each line contains a dircolor(pattern) followed by a color
-#### color can be an ordinary name (grey, brown, blue) or a hex code {#77aaff}
-#### hex code must be enclosed in braces
+#----------------------------------------------------------------------
+# some default behavior
+#----------------------------------------------------------------------
+set netlist_type spice
+set hspice_netlist 1
+set initial_geometry {1920x1080}
+set persistent_command 1
+
+#----------------------------------------------------------------------
+# custom grid / snap value settings
+#----------------------------------------------------------------------
+set grid 20
+set snap 10
+
+#----------------------------------------------------------------------
+# custom colors may be defined here
+#----------------------------------------------------------------------
+
+set light_colors {
+"#eee4c2" "#268BD2"
+"#aaaaaa" "#222222"
+"#229900" "#bb2200"
+"#00ccee" "#ff0000"
+"#888800" "#00aaaa"
+"#880088" "#00ff00"
+"#0000cc" "#666600"
+"#557755" "#aa2222"
+"#7ccc40" "#00ffcc"
+"#ce0097" "#d2d46b"
+"#ef6158" "#fdb200" }
+
+set dark_colors {
+"#222222" "#00ccee"
+"#3f3f3f" "#cccccc"
+"#88dd00" "#bb2200"
+"#00ccee" "#ff0000"
+"#ffff00" "#ffffff"
+"#ff00ff" "#00ff00"
+"#0000cc" "#aaaa00"
+"#aaccaa" "#ff7777"
+"#bfff81" "#00ffcc"
+"#ce0097" "#d2d46b"
+"#ef6158" "#fdb200" }
+
+#----------------------------------------------------------------------
+# set custom colors for xschem libraries matching certain patterns
+#----------------------------------------------------------------------
array unset dircolor
set dircolor(sky130_fd_pr$) blue
set dircolor(sky130_tests$) blue
@@ -53,244 +82,40 @@
set dircolor(xschem_library$) red
set dircolor(devices$) red
-###########################################################################
-#### WINDOW TO OPEN ON STARTUP: XSCHEM_START_WINDOW
-###########################################################################
-#### Start without a design if no filename given on command line:
-#### To avoid absolute paths, use a path that is relative to one of the
-#### XSCHEM_LIBRARY_PATH directories. Default: empty
-set XSCHEM_START_WINDOW {sky130_tests/top.sch}
+#----------------------------------------------------------------------
+# keybindings
+#----------------------------------------------------------------------
-###########################################################################
-#### DIRECTORY WHERE SIMULATIONS, NETLIST AND SIMULATOR OUTPUTS ARE PLACED
-###########################################################################
-#### If unset $USER_CONF_DIR/simulations is assumed (normally ~/.xschem/simulations)
-# set netlist_dir $env(HOME)/.xschem/simulations
-set netlist_dir .
+set replace_key(Key-a) m
+set replace_key(Key-d) Delete
+set replace_key(Key-i) Insert
+set replace_key(Key-r) Control-e
+set replace_key(Key-y) Control-c
+set replace_key(Key-q) Shift-Q
+set replace_key(Shift-Q) q
+set replace_key(Key-l) Alt-Shift-L
+set replace_key(Shift-L) Alt-l
+set replace_key(Shift-L) Alt-l
+set replace_key(Key-p) Control-w
-###########################################################################
-#### CHANGE DEFAULT [] WITH SOME OTHER CHARACTERS FOR BUSSED SIGNALS
-#### IN SPICE NETLISTS (EXAMPLE: DATA[7] --> DATA<7>)
-###########################################################################
-#### default: empty (use xschem default, [ ])
-# set bus_replacement_char {<>}
-#### for XSPICE: replace square brackets as the are used for XSPICE vector nodes.
-# set bus_replacement_char {__}
+#----------------------------------------------------------------------
+# terminal
+#----------------------------------------------------------------------
+set terminal {gnome-terminal}
-###########################################################################
-#### SOME DEFAULT BEHAVIOR
-###########################################################################
-#### Allowed values: spice, verilog, vhdl, tedax, default: spice
-# set netlist_type spice
+#----------------------------------------------------------------------
+# editor
+#----------------------------------------------------------------------
+set editor { xterm -geometry 70x25 -e nvim }
-#### Some netlisting options (these are the defaults)
-# set hspice_netlist 1
-# set verilog_2001 1
-
-#### to use a fixed line with set change_lw to 0 and set some value to line_width
-#### these are the defaults
-# set line_width 0
-# set change_lw 1
-
-#### allow color postscript and svg exports. Default: 1, enable color
-# set color_ps 1
-
-#### initial size of xschem window you can specify also position with (wxh+x+y)
-#### this is the default:
-# set initial_geometry {900x600}
-
-#### if set to 0, when zooming out allow the viewport do drift toward the mouse position,
-#### allowing to move away by zooming / unzooming with mouse wheel
-#### default setting: 0
-# set unzoom_nodrift 0
-
-#### if set to 1 allow to place multiple components with same name.
-#### Warning: this is normally not allowed in any simulation netlist.
-#### default: 0, do not allow place multiple elements with same name (refdes)
-# set disable_unique_names 0
-
-#### if set to 1 continue drawing lines / wires after click
-#### default: 0
-# set persistent_command 1
-
-#### if set to 1 automatically join/trim wires while editing
-#### this may slow down on rally big designs. Can be disabled via menu
-#### default: 0
-# set autotrim_wires 0
-
-#### set widget scaling (mainly for font display), this is useful on 4K displays
-#### default: unset (tk uses its default) > 1.0 ==> bigger
-# set tk_scaling 1.7
-
-#### disable some symbol layers. Default: none, all layers are visible.
-# set enable_layer(5) 0 ;# example to disable pin red boxes
-
-#### enable to scale grid point size as done with lines at close zoom, default: 0
-# set big_grid_points 0
-
-###########################################################################
-#### EXPORT FORMAT TRANSLATORS, PNG AND PDF
-###########################################################################
-#### command to translate xpm to png; (assumes command takes source
-#### and dest file as arguments, example: gm convert plot.xpm plot.png)
-#### default: {gm convert}
-# set to_png {gm convert}
-
-#### command to translate ps to pdf; (assumes command takes source
-#### and dest file as arguments, example: ps2pdf plot.ps plot.pdf)
-#### default: ps2pdf
-# set to_pdf ps2pdf
-set to_pdf {ps2pdf -dAutoRotatePages=/None}
-
-
-###########################################################################
-#### CUSTOM GRID / SNAP VALUE SETTINGS
-###########################################################################
-#### Warning: changing these values will likely break compatibility
-#### with existing symbol libraries. Defaults: grid 20, snap 10.
-# set grid 20
-# set snap 10
-
-###########################################################################
-#### CUSTOM COLORS MAY BE DEFINED HERE
-###########################################################################
-# set cadlayers 22
-# set light_colors {
-# "#ffffff" "#0044ee" "#aaaaaa" "#222222" "#229900"
-# "#bb2200" "#00ccee" "#ff0000" "#888800" "#00aaaa"
-# "#880088" "#00ff00" "#0000cc" "#666600" "#557755"
-# "#aa2222" "#7ccc40" "#00ffcc" "#ce0097" "#d2d46b"
-# "#ef6158" "#fdb200" }
-
-# set dark_colors {
-# "#000000" "#00ccee" "#3f3f3f" "#cccccc" "#88dd00"
-# "#bb2200" "#00ccee" "#ff0000" "#ffff00" "#ffffff"
-# "#ff00ff" "#00ff00" "#0000cc" "#aaaa00" "#aaccaa"
-# "#ff7777" "#bfff81" "#00ffcc" "#ce0097" "#d2d46b"
-# "#ef6158" "#fdb200" }
-
-###########################################################################
-#### CAIRO STUFF
-###########################################################################
-#### Scale all fonts by this number
-# set cairo_font_scale 1.0
-
-#### default for following two is 0.85 (xscale) and 0.88 (yscale) to
-#### match cairo font spacing
-# set nocairo_font_xscale 1.0
-#### set nocairo_font_yscale 1.0
-
-#### Scale line spacing by this number
-# set cairo_font_line_spacing 1.0
-
-#### Specify a font
-# set cairo_font_name {Sans-Serif}
-# set svg_font_name {Sans-Serif}
-
-#### Lift up text by some zoom-corrected pixels for
-#### better compatibility wrt no cairo version.
-#### Useful values in the range [-1, 3]
-# set cairo_vert_correct 0
-# set nocairo_vert_correct 0
-
-###########################################################################
-#### KEYBINDINGS
-###########################################################################
-#### General format for specifying a replacement for a keybind
-#### Replace Ctrl-d with Escape (so you wont kill the program)
-# set replace_key(Control-d) Escape
-
-#### swap w and W keybinds; Always specify Shift for capital letters
-# set replace_key(Shift-W) w
-# set replace_key(w) Shift-W
-
-###########################################################################
-#### TERMINAL
-###########################################################################
-#### default for linux: xterm
-# set terminal {xterm -geometry 100x35 -fn 9x15 -bg black -fg white -cr white -ms white }
-#### lxterminal is not OK since it will not inherit env vars:
-#### In order to reduce memory usage and increase the performance, all instances
-#### of the lxterminal are sharing a single process. LXTerminal is part of LXDE
-
-###########################################################################
-#### EDITOR
-###########################################################################
-#### editor must not detach from launching shell (-f mandatory for gvim)
-#### default for linux: gvim -f
-# set editor {gvim -f -geometry 90x28}
-# set editor { xterm -geometry 100x40 -e nano }
-# set editor { xterm -geometry 100x40 -e pico }
-
-#### For Windows
-# set editor {notepad.exe}
-
-###########################################################################
-#### SHOW ERC INFO WINDOW (erc errors, warnings etc)
-###########################################################################
-#### default: 0 (can be enabled by menu)
-# set show_infowindow 0
-
-###########################################################################
-#### CONFIGURE COMPUTER FARM JOB REDIRECTORS FOR SIMULATIONS
-###########################################################################
-#### RTDA NC
-# set computerfarm {nc run -Il}
-#### LSF BSUB
-# set computerfarm {bsub -Is}
-
-###########################################################################
-#### TCP CONNECTION WITH GAW
-###########################################################################
-#### set gaw address for socket connection: {host port}
-#### default: set to localhost, port 2020
-# set gaw_tcp_address {localhost 2020}
-
-###########################################################################
-#### XSCHEM LISTEN TO TCP PORT
-###########################################################################
-#### set xschem listening port; default: not enabled
-# set xschem_listen_port 2021
-
-###########################################################################
-#### BESPICE WAVE SOCKET CONNECTION
-###########################################################################
-#### set bespice wave listening port; default: not enabled
-set bespice_listen_port 2022
-
-
-
-###########################################################################
-#### UTILE SPICE STIMULI DESCRIPTION LANGUAGE AND TRANSLATOR
-###########################################################################
-#### default paths are set as shown here:
-# set utile_gui_path ${XSCHEM_SHAREDIR}/utile/utile3
-# set utile_cmd_path ${XSCHEM_SHAREDIR}/utile/utile
-
-###########################################################################
-#### TCL FILES TO LOAD AT STARTUP
-###########################################################################
-#### list of tcl files to preload.
-# lappend tcl_files ${XSCHEM_SHAREDIR}/change_index.tcl
+#----------------------------------------------------------------------
+# tcl files to load at startup
+#----------------------------------------------------------------------
lappend tcl_files ${XSCHEM_SHAREDIR}/ngspice_backannotate.tcl
-lappend tcl_files $PDKPATH/libs.tech/xschem/scripts/sky130_models.tcl
-###########################################################################
-#### XSCHEM TOOLBAR
-###########################################################################
-#### default: not enabled.
-# set toolbar_visible 1
-# set toolbar_horiz 1
+lappend tcl_files ${XSCHEM_SKY130_SCRIPTS_PATH}/sky130_models.tcl
-###########################################################################
-#### SKYWATER PDK SPECIFIC VARIABLES
-###########################################################################
-
-## (spice patched) skywater-pdk install
-# set SKYWATER_MODELS ~/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest
-# set SKYWATER_STDCELLS ~/skywater-pdk/libraries/sky130_fd_sc_hd/latest
-
-## opencircuitdesign pdks install. You need to change these to point to your open_pdks installation
-# set SKYWATER_MODELS /usr/local/share/pdk/sky130A/libs.tech/ngspice
-# set SKYWATER_STDCELLS /usr/local/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice
-set SKYWATER_MODELS $PDKPATH/libs.tech/ngspice
-set SKYWATER_STDCELLS $PDKPATH/libs.ref/sky130_fd_sc_hd/spice
+#----------------------------------------------------------------------
+# skywater pdk specific variables
+#----------------------------------------------------------------------
+set SKYWATER_MODELS ${PDK_PATH}/sky130_fd_pr_ngspice/latest
+set SKYWATER_STDCELLS ${PDK_PATH}/sky130_fd_sc_hd/latest
