| commit | 02de3137b96a07aa782cf1f0ef60afcc593a8984 | [log] [tgz] |
|---|---|---|
| author | chrische-xx <christoph-weiser@gmx.de> | Fri Nov 12 21:24:06 2021 +0100 |
| committer | GitHub <noreply@github.com> | Fri Nov 12 21:24:06 2021 +0100 |
| tree | 83228ae2b324134683b11e2f1e6c5cf19ece0b13 | |
| parent | 411d725836adf3cf856d9241b91871d32d08d3c0 [diff] |
Update README.md
This is a mixed-mode project featuring a 8-bit SAR-ADC, with offset calibration. The logic section is synthesized using the openlane digital flow.
The adc is composed of a top-plate sampled CDAC, with a capacitor array of mimimum sized MIM caps.
The comparator is a single-stage regenerative comparator, with a MOM array for trimming ADC offset.
The simulation is carried out using ngspice using the mixed-mode xspice capabilities. The digital section is synthesized using yosys that can then be bridged to/from the analog section.
The layout is created using magic as a pcell generator and drc checker, while the connection of the design is done using klayout.
