| commit | 3e86a67d8011a2d409ed5b69047864983b092ce4 | [log] [tgz] |
|---|---|---|
| author | chrische <christoph-weiser@gmx.de> | Fri Nov 12 22:48:42 2021 +0100 |
| committer | chrische <christoph-weiser@gmx.de> | Fri Nov 12 22:48:42 2021 +0100 |
| tree | 432f47f70bdc9af9b5eeb16923e2ba912ccd7083 | |
| parent | 9084336764e29b7236e6f8b43610a68d24fc24d6 [diff] | |
| parent | 02de3137b96a07aa782cf1f0ef60afcc593a8984 [diff] |
merged README.md image
This is a mixed-mode project featuring a 8-bit SAR-ADC, with offset calibration. The logic section is synthesized using the openlane digital flow.
The adc is composed of a top-plate sampled CDAC, with a capacitor array of mimimum sized MIM caps.
The comparator is a single-stage regenerative comparator, with a MOM array for trimming ADC offset.
The simulation is carried out using ngspice using the mixed-mode xspice capabilities. The digital section is synthesized using yosys that can then be bridged to/from the analog section.
The layout is created using magic as a pcell generator and drc checker, while the connection of the design is done using klayout.
