commit	954416c5a8d50065a7e8b5dd5827124ccd532479	[log] [tgz]
author	ssprasad <ssprasad12a@gmail.com>	Fri Oct 29 00:08:28 2021 +0530
committer	ssprasad <ssprasad12a@gmail.com>	Fri Oct 29 00:08:28 2021 +0530
tree	df207801963b4684f04d525cff09acb0b6a9e31b

First commit

.github/scripts/build/run-set-id.sh[Added - diff]
.github/scripts/build/run-ship.sh[Added - diff]
.github/scripts/build/run-xor.sh[Added - diff]
.github/scripts/dv/pdkBuild.sh[Added - diff]
.github/scripts/dv/run-dv-wrapper.sh[Added - diff]
.github/scripts/dv/run-dv.sh[Added - diff]
.github/scripts/precheck/precheckBuild.sh[Added - diff]
.github/scripts/precheck/run-precheck-drc.sh[Added - diff]
.github/scripts/precheck/run-precheck.sh[Added - diff]
.github/workflows/auto_update_submodule.yml[Added - diff]
.github/workflows/caravel_build.yml[Added - diff]
.github/workflows/user_project_ci.yml[Added - diff]
.gitignore[Added - diff]
.gitmodules[Added - diff]
LICENSE[Added - diff]
Makefile[Added - diff]
README.md[Added - diff]
caravel/LICENSE[Added - diff]
caravel/Makefile[Added - diff]
caravel/gds/antenna_on_gds.tcl[Added - diff]
caravel/gds/drc_on_gds.tcl[Added - diff]
caravel/gds/gds2mag-all.sh[Added - diff]
caravel/gds/user_analog_project_wrapper_empty.gds[Added - diff]
caravel/gds/user_project_wrapper_empty.gds[Added - diff]
caravel/lef/user_analog_project_wrapper_empty.lef[Added - diff]
caravel/lef/user_project_wrapper_empty.lef[Added - diff]
caravel/mag/user_analog_project_wrapper_empty.mag[Added - diff]
caravel/manifest[Added - diff]
caravel/openlane/Makefile[Added - diff]
caravel/openlane/user_analog_project_wrapper_empty/config.tcl[Added - diff]
caravel/openlane/user_analog_project_wrapper_empty/fixed_wrapper_cfgs.tcl[Added - diff]
caravel/openlane/user_analog_project_wrapper_empty/interactive.tcl[Added - diff]
caravel/openlane/user_analog_project_wrapper_empty/or_ioplace.tcl[Added - diff]
caravel/openlane/user_analog_project_wrapper_empty/pin_order.cfg[Added - diff]
caravel/openlane/user_project_wrapper_empty/config.tcl[Added - diff]
caravel/openlane/user_project_wrapper_empty/default_wrapper_cfgs.tcl[Added - diff]
caravel/openlane/user_project_wrapper_empty/fixed_wrapper_cfgs.tcl[Added - diff]
caravel/openlane/user_project_wrapper_empty/interactive.tcl[Added - diff]
caravel/openlane/user_project_wrapper_empty/pin_order.cfg[Added - diff]
caravel/scripts/check_density.py[Added - diff]
caravel/scripts/compositor.py[Added - diff]
caravel/scripts/count_lvs.py[Added - diff]
caravel/scripts/create-caravel-diagram.py[Added - diff]
caravel/scripts/generate_fill.py[Added - diff]
caravel/scripts/generate_fill_orig.py[Added - diff]
caravel/scripts/make_bump_bonds.tcl[Added - diff]
caravel/scripts/set_user_id.py[Added - diff]
caravel/spi/lvs/caravan.spice[Added - diff]
caravel/spi/lvs/caravel.spice[Added - diff]
caravel/spi/lvs/run_lvs.sh[Added - diff]
caravel/utils/MAGIC.txt[Added - diff]
caravel/utils/README.txt[Added - diff]
caravel/utils/addmpwseal.tcl[Added - diff]
caravel/utils/apply_caravel.sh[Added - diff]
caravel/utils/core_scripts/README.md[Added - diff]
caravel/utils/core_scripts/magic-drc.sh[Added - diff]
caravel/utils/core_scripts/magic-drc.tcl[Added - diff]
caravel/utils/core_scripts/magic-ext.sh[Added - diff]
caravel/utils/core_scripts/magic-ext.tcl[Added - diff]
caravel/utils/draw_boundary.sh[Added - diff]
caravel/utils/drc-def-sky130A.sh[Added - diff]
caravel/utils/drc-gds-sky130A.sh[Added - diff]
caravel/utils/drc-mag-sky130A.sh[Added - diff]
caravel/utils/erase_box.sh[Added - diff]
caravel/utils/examples/README.md[Added - diff]
caravel/utils/examples/addmpwseal.tcl[Added - diff]
caravel/utils/examples/create-project.sh[Added - diff]
caravel/utils/examples/dot.magicrc[Added - diff]
caravel/utils/examples/drc-mag.sh[Added - diff]
caravel/utils/examples/drc-maglef.sh[Added - diff]
caravel/utils/examples/drc.sh[Added - diff]
caravel/utils/examples/edit.tcl[Added - diff]
caravel/utils/examples/ext-gds.sh[Added - diff]
caravel/utils/examples/ext-mag.sh[Added - diff]
caravel/utils/examples/ext.sh[Added - diff]
caravel/utils/examples/extract.tcl[Added - diff]
caravel/utils/examples/lvs.sh[Added - diff]
caravel/utils/examples/mag2gds.tcl[Added - diff]
caravel/utils/examples/magic_drc.tcl[Added - diff]
caravel/utils/examples/pfg.sh[Added - diff]
caravel/utils/examples/run_openram_tc_1kb.sh[Added - diff]
caravel/utils/examples/setup.tcl[Added - diff]
caravel/utils/examples/wrap.tcl[Added - diff]
caravel/utils/examples/wrap2.tcl[Added - diff]
caravel/utils/examples/xor.drc[Added - diff]
caravel/utils/examples/xor.sh[Added - diff]
caravel/utils/export_pin_labels.sh[Added - diff]
caravel/utils/ext-def-sky130A.sh[Added - diff]
caravel/utils/ext-gds-sky130A.sh[Added - diff]
caravel/utils/ext-mag-sky130A.sh[Added - diff]
caravel/utils/gds2mag-mag.local.sh[Added - diff]
caravel/utils/gds2mag-mag.sh[Added - diff]
caravel/utils/lef2maglef.sh[Added - diff]
caravel/utils/mag2maglef-mag.sh[Added - diff]
caravel/utils/mag2maglef-maglef.localrc.sh[Added - diff]
caravel/utils/mag2maglef-maglef.sh[Added - diff]
caravel/utils/magicDrc[Added - diff]
caravel/utils/magicGdrc[Added - diff]
caravel/utils/parse_klayout_xor_log.py[Added - diff]
caravel/utils/rcx.sh[Added - diff]
caravel/utils/rename_pins.sh[Added - diff]
caravel/utils/scrotLayout.py[Added - diff]
caravel/utils/scrotLayout.sh[Added - diff]
caravel/utils/xor.drc[Added - diff]
caravel/utils/xor.sh[Added - diff]
caravel/verilog/dv/README.md[Added - diff]
caravel/verilog/dv/caravel/defs.h[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/Makefile[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/caravan/Makefile[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/caravan/README[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/caravan/caravan.c[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/caravan/caravan_tb.v[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/gpio/Makefile[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/gpio/README[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/gpio/gpio.c[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/gpio_mgmt/Makefile[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/gpio_mgmt/README[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/gpio_mgmt/gpio_mgmt.c[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/gpio_mgmt/gpio_mgmt_tb.v[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/hkspi/Makefile[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/hkspi/hkspi.c[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/irq/Makefile[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/irq/README[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/irq/custom_ops.S[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/irq/irq.c[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/irq/irq_tb.v[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/irq/sections.lds[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/irq/start.S[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/mem/Makefile[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/mem/mem.c[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl.c[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/pass_thru/Makefile[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru.c[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/perf/Makefile[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/perf/perf.c[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/pll/Makefile[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/pll/pll.c[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/qspi/Makefile[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/qspi/README[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/qspi/qspi.c[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/qspi/qspi_tb.v[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/storage/Makefile[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/storage/storage.c[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/sysctrl/Makefile[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl.c[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/timer/Makefile[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/timer/timer.c[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/timer2/Makefile[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/timer2/timer2.c[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/uart/Makefile[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/uart/uart.c[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/user_pass_thru/Makefile[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/user_pass_thru/README[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/user_pass_thru/user_pass_thru.c[Added - diff]
caravel/verilog/dv/caravel/mgmt_soc/user_pass_thru/user_pass_thru_tb.v[Added - diff]
caravel/verilog/dv/caravel/sections.lds[Added - diff]
caravel/verilog/dv/caravel/spiflash.v[Added - diff]
caravel/verilog/dv/caravel/start.s[Added - diff]
caravel/verilog/dv/caravel/stub.c[Added - diff]
caravel/verilog/dv/caravel/tbuart.v[Added - diff]
caravel/verilog/dv/dummy_slave.v[Added - diff]
caravel/verilog/dv/wb_utests/Makefile[Added - diff]
caravel/verilog/dv/wb_utests/chip_io/Makefile[Added - diff]
caravel/verilog/dv/wb_utests/chip_io/chip_io_split.v[Added - diff]
caravel/verilog/dv/wb_utests/chip_io/chip_io_tb.v[Added - diff]
caravel/verilog/dv/wb_utests/chip_io/ports.v[Added - diff]
caravel/verilog/dv/wb_utests/gpio_wb/Makefile[Added - diff]
caravel/verilog/dv/wb_utests/gpio_wb/gpio_wb_tb.v[Added - diff]
caravel/verilog/dv/wb_utests/intercon_wb/Makefile[Added - diff]
caravel/verilog/dv/wb_utests/intercon_wb/intercon_wb_tb.v[Added - diff]
caravel/verilog/dv/wb_utests/la_wb/Makefile[Added - diff]
caravel/verilog/dv/wb_utests/la_wb/la_wb_tb.v[Added - diff]
caravel/verilog/dv/wb_utests/mem_wb/Makefile[Added - diff]
caravel/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v[Added - diff]
caravel/verilog/dv/wb_utests/mgmt_protect/Makefile[Added - diff]
caravel/verilog/dv/wb_utests/mgmt_protect/mgmt_protect_tb.v[Added - diff]
caravel/verilog/dv/wb_utests/mprj_ctrl/Makefile[Added - diff]
caravel/verilog/dv/wb_utests/mprj_ctrl/mprj_ctrl_tb.v[Added - diff]
caravel/verilog/dv/wb_utests/spi_sysctrl_wb/Makefile[Added - diff]
caravel/verilog/dv/wb_utests/spi_sysctrl_wb/spi_sysctrl_wb_tb.v[Added - diff]
caravel/verilog/dv/wb_utests/spimemio_wb/Makefile[Added - diff]
caravel/verilog/dv/wb_utests/spimemio_wb/flash.hex[Added - diff]
caravel/verilog/dv/wb_utests/spimemio_wb/spimemio_wb_tb.v[Added - diff]
caravel/verilog/dv/wb_utests/storage_wb/Makefile[Added - diff]
caravel/verilog/dv/wb_utests/storage_wb/storage_wb_tb.v[Added - diff]
caravel/verilog/dv/wb_utests/sysctrl_wb/Makefile[Added - diff]
caravel/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v[Added - diff]
caravel/verilog/dv/wb_utests/uart_wb/Makefile[Added - diff]
caravel/verilog/dv/wb_utests/uart_wb/uart_wb_tb.v[Added - diff]
caravel/verilog/gl/DFFRAM.v[Added - diff]
caravel/verilog/gl/__user_analog_project_wrapper.v[Added - diff]
caravel/verilog/gl/__user_project_wrapper.v[Added - diff]
caravel/verilog/gl/caravan.v[Added - diff]
caravel/verilog/gl/caravel.v[Added - diff]
caravel/verilog/gl/chip_io.v[Added - diff]
caravel/verilog/gl/chip_io_alt.v[Added - diff]
caravel/verilog/gl/digital_pll.v[Added - diff]
caravel/verilog/gl/gpio_control_block.v[Added - diff]
caravel/verilog/gl/gpio_logic_high.v[Added - diff]
caravel/verilog/gl/mgmt_core.v[Added - diff]
caravel/verilog/gl/mgmt_protect.v[Added - diff]
caravel/verilog/gl/mgmt_protect_hv.v[Added - diff]
caravel/verilog/gl/mprj2_logic_high.v[Added - diff]
caravel/verilog/gl/mprj_logic_high.v[Added - diff]
caravel/verilog/gl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v[Added - diff]
caravel/verilog/gl/storage.v[Added - diff]
caravel/verilog/gl/user_id_programming.v[Added - diff]
caravel/verilog/rtl/DFFRAM.v[Added - diff]
caravel/verilog/rtl/DFFRAMBB.v[Added - diff]
caravel/verilog/rtl/README[Added - diff]
caravel/verilog/rtl/__uprj_analog_netlists.v[Added - diff]
caravel/verilog/rtl/__uprj_netlists.v[Added - diff]
caravel/verilog/rtl/__user_analog_project_wrapper.v[Added - diff]
caravel/verilog/rtl/__user_project_wrapper.v[Added - diff]
caravel/verilog/rtl/caravan.v[Added - diff]
caravel/verilog/rtl/caravan_netlists.v[Added - diff]
caravel/verilog/rtl/caravel.v[Added - diff]
caravel/verilog/rtl/caravel_clocking.v[Added - diff]
caravel/verilog/rtl/caravel_netlists.v[Added - diff]
caravel/verilog/rtl/chip_io.v[Added - diff]
caravel/verilog/rtl/chip_io_alt.v[Added - diff]
caravel/verilog/rtl/clock_div.v[Added - diff]
caravel/verilog/rtl/convert_gpio_sigs.v[Added - diff]
caravel/verilog/rtl/counter_timer_high.v[Added - diff]
caravel/verilog/rtl/counter_timer_low.v[Added - diff]
caravel/verilog/rtl/defines.v[Added - diff]
caravel/verilog/rtl/digital_pll.v[Added - diff]
caravel/verilog/rtl/digital_pll_controller.v[Added - diff]
caravel/verilog/rtl/gpio_control_block.v[Added - diff]
caravel/verilog/rtl/gpio_logic_high.v[Added - diff]
caravel/verilog/rtl/gpio_wb.v[Added - diff]
caravel/verilog/rtl/housekeeping_spi.v[Added - diff]
caravel/verilog/rtl/la_wb.v[Added - diff]
caravel/verilog/rtl/mem_wb.v[Added - diff]
caravel/verilog/rtl/mgmt_core.v[Added - diff]
caravel/verilog/rtl/mgmt_protect.v[Added - diff]
caravel/verilog/rtl/mgmt_protect_hv.v[Added - diff]
caravel/verilog/rtl/mgmt_soc.v[Added - diff]
caravel/verilog/rtl/mprj2_logic_high.v[Added - diff]
caravel/verilog/rtl/mprj_ctrl.v[Added - diff]
caravel/verilog/rtl/mprj_io.v[Added - diff]
caravel/verilog/rtl/mprj_logic_high.v[Added - diff]
caravel/verilog/rtl/pads.v[Added - diff]
caravel/verilog/rtl/picorv32.v[Added - diff]
caravel/verilog/rtl/ring_osc2x13.v[Added - diff]
caravel/verilog/rtl/simple_por.v[Added - diff]
caravel/verilog/rtl/simple_spi_master.v[Added - diff]
caravel/verilog/rtl/simpleuart.v[Added - diff]
caravel/verilog/rtl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v[Added - diff]
caravel/verilog/rtl/spimemio.v[Added - diff]
caravel/verilog/rtl/sram_1rw1r_32_256_8_sky130.v[Added - diff]
caravel/verilog/rtl/storage.v[Added - diff]
caravel/verilog/rtl/storage_bridge_wb.v[Added - diff]
caravel/verilog/rtl/sysctrl.v[Added - diff]
caravel/verilog/rtl/user_id_programming.v[Added - diff]
caravel/verilog/rtl/wb_intercon.v[Added - diff]
caravel/verilog/stubs/sky130_fd_io__top_xres4v2.v[Added - diff]
def/user_proj_example.def[Added - diff]
def/user_project_wrapper.def[Added - diff]
docs/Makefile[Added - diff]
docs/environment.yml[Added - diff]
docs/requirements.txt[Added - diff]
docs/source/_static/counter_32.png[Added - diff]
docs/source/_static/empty.png[Added - diff]
docs/source/_static/layout.png[Added - diff]
docs/source/_static/option1.png[Added - diff]
docs/source/_static/option2.png[Added - diff]
docs/source/_static/option3.png[Added - diff]
docs/source/_static/pitch.png[Added - diff]
docs/source/_static/wrapper.png[Added - diff]
docs/source/conf.py[Added - diff]
docs/source/index.rst[Added - diff]
gds/user_proj_example.gds[Added - diff]
gds/user_project_wrapper.gds[Added - diff]
lef/user_proj_example.lef[Added - diff]
lef/user_project_wrapper.lef[Added - diff]
mag/user_proj_example.mag[Added - diff]
mag/user_project_wrapper.mag[Added - diff]
maglef/user_proj_example.mag[Added - diff]
maglef/user_project_wrapper.mag[Added - diff]
openlane/.gitignore[Added - diff]
openlane/Makefile[Added - diff]
openlane/user_proj_example/config.tcl[Added - diff]
openlane/user_proj_example/pin_order.cfg[Added - diff]
openlane/user_proj_example/user_proj_example.sdc[Added - diff]
openlane/user_project_wrapper/config.json[Added - diff]
openlane/user_project_wrapper/config.tcl[Added - diff]
openlane/user_project_wrapper/macro.cfg[Added - diff]
openlane/user_project_wrapper/pin_order.cfg[Added - diff]
signoff/user_proj_example/OPENLANE_VERSION[Added - diff]
signoff/user_proj_example/PDK_SOURCES[Added - diff]
signoff/user_proj_example/final_summary_report.csv[Added - diff]
signoff/user_project_wrapper/OPENLANE_VERSION[Added - diff]
signoff/user_project_wrapper/PDK_SOURCES[Added - diff]
signoff/user_project_wrapper/final_summary_report.csv[Added - diff]
spi/lvs/user_proj_example.spice[Added - diff]
spi/lvs/user_project_wrapper.spice[Added - diff]
verilog/dv/Makefile[Added - diff]
verilog/dv/README.md[Added - diff]
verilog/dv/gpio_test_0/Makefile[Added - diff]
verilog/dv/gpio_test_0/expected_result.rpt[Added - diff]
verilog/dv/gpio_test_0/gpio_test.c[Added - diff]
verilog/dv/gpio_test_0/gpio_test.hex[Added - diff]
verilog/dv/gpio_test_0/gpio_test_tb.v[Added - diff]
verilog/dv/i2c_test/Makefile[Added - diff]
verilog/dv/i2c_test/expected_result.rpt[Added - diff]
verilog/dv/i2c_test/i2c_test.c[Added - diff]
verilog/dv/i2c_test/i2c_test.hex[Added - diff]
verilog/dv/i2c_test/i2c_test_tb.v[Added - diff]
verilog/dv/output_test/Makefile[Added - diff]
verilog/dv/output_test/expected_result.rpt[Added - diff]
verilog/dv/output_test/io_ports.c[Added - diff]
verilog/dv/output_test/io_ports.hex[Added - diff]
verilog/dv/output_test/io_ports_tb.v[Added - diff]
verilog/dv/spi_test/Makefile[Added - diff]
verilog/dv/spi_test/expected_result.rpt[Added - diff]
verilog/dv/spi_test/spi_test.c[Added - diff]
verilog/dv/spi_test/spi_test.hex[Added - diff]
verilog/dv/spi_test/spi_test_tb.v[Added - diff]
verilog/dv/uart_test/Makefile[Added - diff]
verilog/dv/uart_test/expected_result.rpt[Added - diff]
verilog/dv/uart_test/uart_test.c[Added - diff]
verilog/dv/uart_test/uart_test.hex[Added - diff]
verilog/dv/uart_test/uart_test_tb.v[Added - diff]
verilog/gl/user_proj_example.v[Added - diff]
verilog/gl/user_project_wrapper.v[Added - diff]
verilog/rtl/SyncFIFO.v[Added - diff]
verilog/rtl/apb_crossbar_ssp.v[Added - diff]
verilog/rtl/apbled.v[Added - diff]
verilog/rtl/apbqspi_ssp.v[Added - diff]
verilog/rtl/apbspi_ssp.v[Added - diff]
verilog/rtl/apbuart_ssp.v[Added - diff]
verilog/rtl/dirctrl_ssp.v[Added - diff]
verilog/rtl/gpio_ssp.v[Added - diff]
verilog/rtl/i2c_ssp.v[Added - diff]
verilog/rtl/i2s_transmitter.v[Added - diff]
verilog/rtl/jtag_ssp.v[Added - diff]
verilog/rtl/mkAudiofifo.v[Added - diff]
verilog/rtl/peripheral_top.v[Added - diff]
verilog/rtl/pwm_ssp.v[Added - diff]
verilog/rtl/timer_ssp.v[Added - diff]
verilog/rtl/uprj_netlists.v[Added - diff]
verilog/rtl/user_proj_example.v[Added - diff]
verilog/rtl/user_project_wrapper.v[Added - diff]
verilog/rtl/wishbone2apb.v[Added - diff]
verilog/user_behav_models/24AA64.v[Added - diff]
verilog/user_behav_models/MEM.txt[Added - diff]
verilog/user_behav_models/W25Q32JVxxIM.v[Added - diff]

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tree: df207801963b4684f04d525cff09acb0b6a9e31b

README.md

Caravel_peripheral_extender

:exclamation: Important Note

Refer to README for this sample project documentation. This Project integrates various IP‘s like I2C, I2S, SPI ,QSPI, PWM, GPIO, UART, JTAG to the caravel SoC. The IP’s connect to the Caravel Wishbone Bus and use the User Adddessable space from address 0x3000_0000.