| ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY |
| 0,/project/openlane/user_proj_example,user_proj_example,user_proj_example,flow_completed,0h35m36s,-1,31555.55555555555,1.35,15777.777777777776,18.82,1295.51,21300,0,-1,-1,-1,-1,0,0,-1,0,0,-1,1080114,205343,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,706071341.0,0.0,29.75,21.44,12.13,0.34,-1,16624,35077,2639,20753,0,0,0,19327,0,0,0,0,0,0,0,4,5443,5919,48,644,18630,0,19274,24.390243902439025,41,40,AREA 0,5,50,1,153.6,153.18,0.4,0.3,sky130_fd_sc_hd,4,4 |
