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@@ -32,39 +32,50 @@
 ## Supply variation
 We made dc sweep on the supply and plotted voltage of the output node and vdd node overlaid on the same plot
+@Load current = 0.1mA
+![Image of LDO_Vout_vs_Vin](https://github.com/mabrains/Analog_blocks/blob/main/Analog_Blocks/LDO/Images/LDO_v2/vddsweep100u.png)
-![Image of LDO_Vout_vs_Vin](https://github.com/mabrains/Analog_blocks/blob/main/Analog_Blocks/LDO/Images/LDO_v2/dcsweep.png)
+@Load current = 10mA
+![Image of LDO_Vout_vs_Vin](https://github.com/mabrains/Analog_blocks/blob/main/Analog_Blocks/LDO/Images/LDO_v2/vddsweep10m.png)
+@Load current = 100mA
+![Image of LDO_Vout_vs_Vin](https://github.com/mabrains/Analog_blocks/blob/main/Analog_Blocks/LDO/Images/LDO_v2/vddsweep100m.png)
 ## Temperature variation
 We made dc sweep on temperature from 0 to 85°C and plotted the output voltage vs temperature from which we found temperature coeffiecient in ppm/°C.
+@Load current = 100uA
+![Image of LDO_Vout_vs_Vin](https://github.com/mabrains/Analog_blocks/blob/main/Analog_Blocks/LDO/Images/LDO_v2/tempvar100u.png)
-![Image of LDO_Vout_vs_Vin](https://github.com/mabrains/Analog_blocks/blob/main/Analog_Blocks/LDO/Images/LDO_v2/tempsweep.png)
+@Load current = 10mA
+![Image of LDO_Vout_vs_Vin](https://github.com/mabrains/Analog_blocks/blob/main/Analog_Blocks/LDO/Images/LDO_v2/tempvar100u.png)
 ## c. AC analysis
 ## PSRR
 We used AC analysis by injecting small ac signal over the supply and plotted the output voltage in dB which refers to the PSRR vs Frequency.
-![Image of LDO_PSRR](https://github.com/mabrains/Analog_blocks/blob/main/Analog_Blocks/LDO/Images/LDO_v2/psrr.png)
+![Image of LDO_PSRR](https://github.com/mabrains/Analog_blocks/blob/main/Analog_Blocks/LDO/Images/LDO_v2/psrr50u.png)
 ## Stability analysis
 We made the above testbench to cut the feedback loop of the ldo and inject ac signal and then measure the loop gain and phase to find phase margin.
 ## d. Transient analysis
 ## Line Transient 
-We used transient analysis to show the line transient by varying the supply from 0 to vdd at different supply levels corners such that the nominal supply is 2.3v.
+We used transient analysis to show the line transient by varying the supply from 0 to vdd where the nominal supply voltage is 2.3v.
 When VDD varies from 0 to 2.3v
-![Image of LDO_Transient](https://github.com/mabrains/Analog_blocks/blob/main/Analog_Blocks/LDO/Images/LDO_v2/tran2.3v.png)
-When VDD varies from 0 to 2.07v
-![Image of LDO_Transient](https://github.com/mabrains/Analog_blocks/blob/main/Analog_Blocks/LDO/Images/LDO_v2/tran2.1v.png)
-When VDD varies from 0 to 2.53v
-![Image of LDO_Transient](https://github.com/mabrains/Analog_blocks/blob/main/Analog_Blocks/LDO/Images/LDO_v2/tran2.5v.png)
-## Load Transient 
-The load is varied from 0.1mA to 10mA where the load is modeled as current source varied as PWL source.
-![Image of LDO_netlist](https://github.com/mabrains/Analog_blocks/blob/main/Analog_Blocks/LDO/Images/LDO_v2/load_transient.png)
+![Image of LDO_Transient](https://github.com/mabrains/Analog_blocks/blob/main/Analog_Blocks/LDO/Images/LDO_v2/tran02.3v.png)
+When VDD varies from 2 to 3v
+![Image of LDO_Transient](https://github.com/mabrains/Analog_blocks/blob/main/Analog_Blocks/LDO/Images/LDO_v2/tran2v3v.png)
+The load is varied from 0.1mA to 10mA where the load is modeled as current source varied as PWL source where the output voltage suffers from under shoot of 40mV due to change of load current from 0.1mA to 10mA in 10uS then it settles back to its original value so we used this analysis to measure the load regulation. 
+The plot includes load current variation and ac-coupled ldo_output overlaid on the same plot.
+![Image of LDO_netlist](https://github.com/mabrains/Analog_blocks/blob/main/Analog_Blocks/LDO/Images/LDO_v2/load_transient_ac_coupled.png)
+## Turn-on Characteristic
+We have an enable signal so we varied it from 0 to Vin in 0.1uS and plotted the ldo_out. The start up time is less than 10uS.
+![Image of LDO_netlist](https://github.com/mabrains/Analog_blocks/blob/main/Analog_Blocks/LDO/Images/LDO_v2/stup_50m.png)
 ## e. Testbench netlist
-The netlist of all previous analyses is below or you can simply run it using script "LDO_script.bash" existed in scripts folder.
-![Image of LDO_netlist](https://github.com/mabrains/Analog_blocks/blob/main/Analog_Blocks/LDO/Images/LDO_v2/Testbench.png)
+![Image of LDO_netlist](https://github.com/mabrains/Analog_blocks/blob/main/Analog_Blocks/LDO/Images/LDO_v2/TB.png)
 ## Simulation results
 The typical conditions are tt corner ,load of 50uA, T=27°C , VDD=2.3V , We have a script to automate running process corners then getting their statistical distribution where the variation of the load from 50uA till 100mA is included in the corners  
@@ -72,7 +83,9 @@
   Specification  |      TT                  
 -----------------| ---------------
 Temperature Coeffiecient   | 49.4 ppm/°C
-Dropout Voltage            | 0.124mV
+Dropout Voltage            | 0.211mV @IL=0.1mA
+                           |  85.6mV @IL=10mA
+                           |  168.45mV @IL=100mA
 Line Regulation            | 0.0325 mv/v
 Load Regulation            | 0.06mV    IL=0.1mA till IL=10mA
 PSRR @ 100Hz               | 88.1dB
@@ -80,7 +93,7 @@
 Load range                 | 50uA -> 100mA
 Phase Margin               | 50.1°
 Quiescent Current          | 130uA
+Startup time               | 7uS
 ### Circuit Design
 The implementation of the LDO is as follows.