Skywaters 130nm LDO Design Integrated in Caravel

LDO Design

This is a caravel that has an LDO Design implemented on Skywaters 130nm technology.

LDO Simulation

We have an enable switch so all the following analysis when the enable signal is high.

Schematic

Error Amplifier

Bandgap

a. DC analysis

We used dc analysis for displaying the operating point for proper biasing of transistors and also dc sweep of output voltage against variations in supply and temprature to calculate dropout voltage,line regulation,temperature coefficient.

Supply variation

We made dc sweep on the supply and plotted voltage of the output node and vdd node overlaid on the same plot

Temperature variation

We made dc sweep on temperature from 0 to 85°C and plotted the output voltage vs temperature from which we found temperature coeffiecient in ppm/°C.

c. AC analysis

PSRR

We used AC analysis by injecting small ac signal over the supply and plotted the output voltage in dB which refers to the PSRR vs Frequency.

Stability analysis

We made the above testbench to cut the feedback loop of the ldo and inject ac signal and then measure the loop gain and phase to find phase margin.

d. Transient analysis

Line Transient

We used transient analysis to show the line transient by varying the supply from 0 to vdd at different supply levels corners such that the nominal supply is 2.3v. When VDD varies from 0 to 2.3v When VDD varies from 0 to 2.07v When VDD varies from 0 to 2.53v

Load Transient

The load is varied from 0.1mA to 10mA where the load is modeled as current source varied as PWL source.

e. Testbench netlist

The netlist of all previous analyses is below or you can simply run it using script “LDO_script.bash” existed in scripts folder.

Simulation results

The typical conditions are tt corner ,load of 50uA, T=27°C , VDD=2.3V , We have a script to automate running process corners then getting their statistical distribution where the variation of the load from 50uA till 100mA is included in the corners

Specification	TT
Temperature Coeffiecient	49.4 ppm/°C
Dropout Voltage	0.124mV
Line Regulation	0.0325 mv/v
Load Regulation	0.06mV IL=0.1mA till IL=10mA
PSRR @ 100Hz	88.1dB
PSRR @ 100kHz	44.7dB
Load range	50uA -> 100mA
Phase Margin	50.1°
Quiescent Current	130uA

Circuit Design

The implementation of the LDO is as follows.

Layout Design

Analog User Project Documentation

Refer to README for this sample project documentation.