commit: dcd1995c36f6589f6abe5945a75e3b653c3e396d
[log] [tgz]
author: zeeshanrafique23 <zeeshanrafique23@gmail.com>
Tue Jun 01 16:45:51 2021 +0500
committer: zeeshanrafique23 <zeeshanrafique23@gmail.com>
Tue Jun 01 16:45:51 2021 +0500
tree: 825f2e235ef00f820f637becd59a0a8884e9380f
parent: d3e050539b229d532a45c37a645482e081e344cc [diff]

added azadi_soc design files

verilog/rtl/.azadi_soc_top.sv.swp[Added - diff]
verilog/rtl/.user_project_wrapper.v.swp[Added - diff]
verilog/rtl/PWM.v[Added - diff]
verilog/rtl/azadi_soc_top.sv[Added - diff]
verilog/rtl/brq_core.sv[Added - diff]
verilog/rtl/brq_core_top.sv[Added - diff]
verilog/rtl/brq_counter.sv[Added - diff]
verilog/rtl/brq_cs_registers.sv[Added - diff]
verilog/rtl/brq_csr.sv[Added - diff]
verilog/rtl/brq_exu.sv[Added - diff]
verilog/rtl/brq_exu_alu.sv[Added - diff]
verilog/rtl/brq_exu_multdiv_fast.sv[Added - diff]
verilog/rtl/brq_exu_multdiv_slow.sv[Added - diff]
verilog/rtl/brq_fp_register_file_ff.sv[Added - diff]
verilog/rtl/brq_idu.sv[Added - diff]
verilog/rtl/brq_idu_controller.sv[Added - diff]
verilog/rtl/brq_idu_decoder.sv[Added - diff]
verilog/rtl/brq_ifu.sv[Added - diff]
verilog/rtl/brq_ifu_compressed_decoder.sv[Added - diff]
verilog/rtl/brq_ifu_dummy_instr.sv[Added - diff]
verilog/rtl/brq_ifu_fifo.sv[Added - diff]
verilog/rtl/brq_ifu_icache.sv[Added - diff]
verilog/rtl/brq_ifu_prefetch_buffer.sv[Added - diff]
verilog/rtl/brq_lsu.sv[Added - diff]
verilog/rtl/brq_pkg.sv[Added - diff]
verilog/rtl/brq_pmp.sv[Added - diff]
verilog/rtl/brq_register_file_ff.sv[Added - diff]
verilog/rtl/brq_wbu.sv[Added - diff]
verilog/rtl/cf_math_pkg.sv[Added - diff]
verilog/rtl/control_mvp.sv[Added - diff]
verilog/rtl/data_mem_top.sv[Added - diff]
verilog/rtl/debug_rom.sv[Added - diff]
verilog/rtl/debug_rom_one_scratch.sv[Added - diff]
verilog/rtl/defs_div_sqrt_mvp.sv[Added - diff]
verilog/rtl/div_sqrt_top_mvp.sv[Added - diff]
verilog/rtl/dm_csrs.sv[Added - diff]
verilog/rtl/dm_mem.sv[Added - diff]
verilog/rtl/dm_pkg.sv[Added - diff]
verilog/rtl/dm_sba.sv[Added - diff]
verilog/rtl/dmi_cdc.sv[Added - diff]
verilog/rtl/dmi_jtag.sv[Added - diff]
verilog/rtl/dmi_jtag_tap.sv[Added - diff]
verilog/rtl/down_clocking_even.v[Added - diff]
verilog/rtl/down_clocking_odd.v[Added - diff]
verilog/rtl/fifo_async.sv[Added - diff]
verilog/rtl/fifo_sync.sv[Added - diff]
verilog/rtl/fpnew_cast_multi.sv[Added - diff]
verilog/rtl/fpnew_classifier.sv[Added - diff]
verilog/rtl/fpnew_divsqrt_multi.sv[Added - diff]
verilog/rtl/fpnew_fma.sv[Added - diff]
verilog/rtl/fpnew_fma_multi.sv[Added - diff]
verilog/rtl/fpnew_noncomp.sv[Added - diff]
verilog/rtl/fpnew_opgroup_block.sv[Added - diff]
verilog/rtl/fpnew_opgroup_fmt_slice.sv[Added - diff]
verilog/rtl/fpnew_opgroup_multifmt_slice.sv[Added - diff]
verilog/rtl/fpnew_pkg.sv[Added - diff]
verilog/rtl/fpnew_rounding.sv[Added - diff]
verilog/rtl/fpnew_top.sv[Added - diff]
verilog/rtl/gpio.sv[Added - diff]
verilog/rtl/gpio_reg_pkg.sv[Added - diff]
verilog/rtl/gpio_reg_top.sv[Added - diff]
verilog/rtl/iccm_controller.v[Added - diff]
verilog/rtl/instr_mem_top.sv[Added - diff]
verilog/rtl/iteration_div_sqrt_mvp.sv[Added - diff]
verilog/rtl/jtag_pkg.sv[Added - diff]
verilog/rtl/lzc.sv[Added - diff]
verilog/rtl/minus_one.v[Added - diff]
verilog/rtl/norm_div_sqrt_mvp.sv[Added - diff]
verilog/rtl/nrbd_nrsc_mvp.sv[Added - diff]
verilog/rtl/preprocess_mvp.sv[Added - diff]
verilog/rtl/prim_arbiter_ppc.sv[Added - diff]
verilog/rtl/prim_clock_gating.sv[Added - diff]
verilog/rtl/prim_filter_ctr.sv[Added - diff]
verilog/rtl/prim_generic_clock_inv.sv[Added - diff]
verilog/rtl/prim_generic_clock_mux2.sv[Added - diff]
verilog/rtl/prim_generic_flop.sv[Added - diff]
verilog/rtl/prim_generic_flop_2sync.sv[Added - diff]
verilog/rtl/prim_intr_hw.sv[Added - diff]
verilog/rtl/prim_pkg.sv[Added - diff]
verilog/rtl/prim_subreg.sv[Added - diff]
verilog/rtl/prim_subreg_arb.sv[Added - diff]
verilog/rtl/prim_subreg_ext.sv[Added - diff]
verilog/rtl/prim_util_pkg.sv[Added - diff]
verilog/rtl/pwm_top.sv[Added - diff]
verilog/rtl/rr_arb_tree.sv[Added - diff]
verilog/rtl/rstmgr.sv[Added - diff]
verilog/rtl/rv_dm.sv[Added - diff]
verilog/rtl/rv_plic.sv[Added - diff]
verilog/rtl/rv_plic_gateway.sv[Added - diff]
verilog/rtl/rv_plic_reg_pkg.sv[Added - diff]
verilog/rtl/rv_plic_reg_top.sv[Added - diff]
verilog/rtl/rv_plic_target.sv[Added - diff]
verilog/rtl/rv_timer.sv[Added - diff]
verilog/rtl/rv_timer_reg_pkg.sv[Added - diff]
verilog/rtl/rv_timer_reg_top.sv[Added - diff]
verilog/rtl/spi_clgen.v[Added - diff]
verilog/rtl/spi_core.sv[Added - diff]
verilog/rtl/spi_defines.v[Added - diff]
verilog/rtl/spi_shift.v[Added - diff]
verilog/rtl/spi_top.sv[Added - diff]
verilog/rtl/sram.v[Added - diff]
verilog/rtl/timer_core.sv[Added - diff]
verilog/rtl/tl_main_pkg.sv[Added - diff]
verilog/rtl/tl_xbar_main.sv[Added - diff]
verilog/rtl/tlul_adapter_reg.sv[Added - diff]
verilog/rtl/tlul_err.sv[Added - diff]
verilog/rtl/tlul_err_resp.sv[Added - diff]
verilog/rtl/tlul_fifo_sync.sv[Added - diff]
verilog/rtl/tlul_host_adapter.sv[Added - diff]
verilog/rtl/tlul_pkg.sv[Added - diff]
verilog/rtl/tlul_socket_1n.sv[Added - diff]
verilog/rtl/tlul_socket_m1.sv[Added - diff]
verilog/rtl/tlul_sram_adapter.sv[Added - diff]
verilog/rtl/uart.sv[Added - diff]
verilog/rtl/uart_core.sv[Added - diff]
verilog/rtl/uart_reg_pkg.sv[Added - diff]
verilog/rtl/uart_reg_top.sv[Added - diff]
verilog/rtl/uart_rx.sv[Added - diff]
verilog/rtl/uart_rx_prog.v[Added - diff]
verilog/rtl/uart_tx.sv[Added - diff]

120 files changed

tree: 825f2e235ef00f820f637becd59a0a8884e9380f

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.