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foss-eda-tools
/
third_party
/
shuttle
/
sky130
/
mpw-002
/
slot-018
/
dcd1995c36f6589f6abe5945a75e3b653c3e396d
/
.
/
verilog
/
rtl
/
prim_clock_gating.sv
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module
prim_clock_gating
(
input clk_i
,
input en_i
,
input test_en_i
,
output logic clk_o
);
sky130_fd_sc_hd__dlclkp_1 CG
(
.
CLK
(
clk_i
),
.
GCLK
(
clk_o
),
.
GATE
(
en_i
|
test_en_i
));
endmodule