| // Copyright lowRISC contributors. |
| // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| // SPDX-License-Identifier: Apache-2.0 |
| // |
| // Register Package auto-generated by `reggen` containing data structure |
| |
| package rv_plic_reg_pkg; |
| |
| // Param list |
| parameter int NumSrc = 44; |
| parameter int NumTarget = 1; |
| parameter int PrioWidth = 2; |
| |
| // Address width within the block |
| parameter int BlockAw = 10; |
| |
| //////////////////////////// |
| // Typedefs for registers // |
| //////////////////////////// |
| typedef struct packed { |
| logic q; |
| } rv_plic_reg2hw_le_mreg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_prio0_reg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_prio1_reg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_prio2_reg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_prio3_reg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_prio4_reg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_prio5_reg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_prio6_reg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_prio7_reg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_prio8_reg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_prio9_reg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_prio10_reg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_prio11_reg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_prio12_reg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_prio13_reg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_prio14_reg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_prio15_reg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_prio16_reg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_prio17_reg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_prio18_reg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_prio19_reg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_prio20_reg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_prio21_reg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_prio22_reg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_prio23_reg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_prio24_reg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_prio25_reg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_prio26_reg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_prio27_reg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_prio28_reg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_prio29_reg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_prio30_reg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_prio31_reg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_prio32_reg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_prio33_reg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_prio34_reg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_prio35_reg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_prio36_reg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_prio37_reg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_prio38_reg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_prio39_reg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_prio40_reg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_prio41_reg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_prio42_reg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_prio43_reg_t; |
| |
| typedef struct packed { |
| logic q; |
| } rv_plic_reg2hw_ie0_mreg_t; |
| |
| typedef struct packed { |
| logic [1:0] q; |
| } rv_plic_reg2hw_threshold0_reg_t; |
| |
| typedef struct packed { |
| logic [7:0] q; |
| logic qe; |
| logic re; |
| } rv_plic_reg2hw_cc0_reg_t; |
| |
| typedef struct packed { |
| logic q; |
| } rv_plic_reg2hw_msip0_reg_t; |
| |
| |
| typedef struct packed { |
| logic d; |
| logic de; |
| } rv_plic_hw2reg_ip_mreg_t; |
| |
| typedef struct packed { |
| logic [7:0] d; |
| } rv_plic_hw2reg_cc0_reg_t; |
| |
| |
| /////////////////////////////////////// |
| // Register to internal design logic // |
| /////////////////////////////////////// |
| typedef struct packed { |
| rv_plic_reg2hw_le_mreg_t [43:0] le; // [700:529] |
| rv_plic_reg2hw_prio0_reg_t prio0; // [528:527] |
| rv_plic_reg2hw_prio1_reg_t prio1; // [526:525] |
| rv_plic_reg2hw_prio2_reg_t prio2; // [524:523] |
| rv_plic_reg2hw_prio3_reg_t prio3; // [522:521] |
| rv_plic_reg2hw_prio4_reg_t prio4; // [520:519] |
| rv_plic_reg2hw_prio5_reg_t prio5; // [518:517] |
| rv_plic_reg2hw_prio6_reg_t prio6; // [516:515] |
| rv_plic_reg2hw_prio7_reg_t prio7; // [514:513] |
| rv_plic_reg2hw_prio8_reg_t prio8; // [512:511] |
| rv_plic_reg2hw_prio9_reg_t prio9; // [510:509] |
| rv_plic_reg2hw_prio10_reg_t prio10; // [508:507] |
| rv_plic_reg2hw_prio11_reg_t prio11; // [506:505] |
| rv_plic_reg2hw_prio12_reg_t prio12; // [504:503] |
| rv_plic_reg2hw_prio13_reg_t prio13; // [502:501] |
| rv_plic_reg2hw_prio14_reg_t prio14; // [500:499] |
| rv_plic_reg2hw_prio15_reg_t prio15; // [498:497] |
| rv_plic_reg2hw_prio16_reg_t prio16; // [496:495] |
| rv_plic_reg2hw_prio17_reg_t prio17; // [494:493] |
| rv_plic_reg2hw_prio18_reg_t prio18; // [492:491] |
| rv_plic_reg2hw_prio19_reg_t prio19; // [490:489] |
| rv_plic_reg2hw_prio20_reg_t prio20; // [488:487] |
| rv_plic_reg2hw_prio21_reg_t prio21; // [486:485] |
| rv_plic_reg2hw_prio22_reg_t prio22; // [484:483] |
| rv_plic_reg2hw_prio23_reg_t prio23; // [482:481] |
| rv_plic_reg2hw_prio24_reg_t prio24; // [480:479] |
| rv_plic_reg2hw_prio25_reg_t prio25; // [478:477] |
| rv_plic_reg2hw_prio26_reg_t prio26; // [476:475] |
| rv_plic_reg2hw_prio27_reg_t prio27; // [474:473] |
| rv_plic_reg2hw_prio28_reg_t prio28; // [472:471] |
| rv_plic_reg2hw_prio29_reg_t prio29; // [470:469] |
| rv_plic_reg2hw_prio30_reg_t prio30; // [468:467] |
| rv_plic_reg2hw_prio31_reg_t prio31; // [466:465] |
| rv_plic_reg2hw_prio32_reg_t prio32; // [464:463] |
| rv_plic_reg2hw_prio33_reg_t prio33; // [462:461] |
| rv_plic_reg2hw_prio34_reg_t prio34; // [460:459] |
| rv_plic_reg2hw_prio35_reg_t prio35; // [458:457] |
| rv_plic_reg2hw_prio36_reg_t prio36; // [456:455] |
| rv_plic_reg2hw_prio37_reg_t prio37; // [454:453] |
| rv_plic_reg2hw_prio38_reg_t prio38; // [452:451] |
| rv_plic_reg2hw_prio39_reg_t prio39; // [450:449] |
| rv_plic_reg2hw_prio40_reg_t prio40; // [448:447] |
| rv_plic_reg2hw_prio41_reg_t prio41; // [446:445] |
| rv_plic_reg2hw_prio42_reg_t prio42; // [444:443] |
| rv_plic_reg2hw_prio43_reg_t prio43; // [442:441] |
| rv_plic_reg2hw_ie0_mreg_t [43:0] ie0; // [184:13] |
| rv_plic_reg2hw_threshold0_reg_t threshold0; // [12:11] |
| rv_plic_reg2hw_cc0_reg_t cc0; // [10:1] |
| rv_plic_reg2hw_msip0_reg_t msip0; // [0:0] |
| } rv_plic_reg2hw_t; |
| |
| /////////////////////////////////////// |
| // Internal design logic to register // |
| /////////////////////////////////////// |
| typedef struct packed { |
| rv_plic_hw2reg_ip_mreg_t [43:0] ip; // [351:8] |
| rv_plic_hw2reg_cc0_reg_t cc0; // [7:0] |
| } rv_plic_hw2reg_t; |
| |
| // Register Address |
| parameter logic [BlockAw-1:0] RV_PLIC_IP_0_OFFSET = 10'h 0; |
| parameter logic [BlockAw-1:0] RV_PLIC_IP_1_OFFSET = 10'h 4; |
| parameter logic [BlockAw-1:0] RV_PLIC_LE_0_OFFSET = 10'h 8; |
| parameter logic [BlockAw-1:0] RV_PLIC_LE_1_OFFSET = 10'h c; |
| parameter logic [BlockAw-1:0] RV_PLIC_PRIO0_OFFSET = 10'h 10; |
| parameter logic [BlockAw-1:0] RV_PLIC_PRIO1_OFFSET = 10'h 14; |
| parameter logic [BlockAw-1:0] RV_PLIC_PRIO2_OFFSET = 10'h 18; |
| parameter logic [BlockAw-1:0] RV_PLIC_PRIO3_OFFSET = 10'h 1c; |
| parameter logic [BlockAw-1:0] RV_PLIC_PRIO4_OFFSET = 10'h 20; |
| parameter logic [BlockAw-1:0] RV_PLIC_PRIO5_OFFSET = 10'h 24; |
| parameter logic [BlockAw-1:0] RV_PLIC_PRIO6_OFFSET = 10'h 28; |
| parameter logic [BlockAw-1:0] RV_PLIC_PRIO7_OFFSET = 10'h 2c; |
| parameter logic [BlockAw-1:0] RV_PLIC_PRIO8_OFFSET = 10'h 30; |
| parameter logic [BlockAw-1:0] RV_PLIC_PRIO9_OFFSET = 10'h 34; |
| parameter logic [BlockAw-1:0] RV_PLIC_PRIO10_OFFSET = 10'h 38; |
| parameter logic [BlockAw-1:0] RV_PLIC_PRIO11_OFFSET = 10'h 3c; |
| parameter logic [BlockAw-1:0] RV_PLIC_PRIO12_OFFSET = 10'h 40; |
| parameter logic [BlockAw-1:0] RV_PLIC_PRIO13_OFFSET = 10'h 44; |
| parameter logic [BlockAw-1:0] RV_PLIC_PRIO14_OFFSET = 10'h 48; |
| parameter logic [BlockAw-1:0] RV_PLIC_PRIO15_OFFSET = 10'h 4c; |
| parameter logic [BlockAw-1:0] RV_PLIC_PRIO16_OFFSET = 10'h 50; |
| parameter logic [BlockAw-1:0] RV_PLIC_PRIO17_OFFSET = 10'h 54; |
| parameter logic [BlockAw-1:0] RV_PLIC_PRIO18_OFFSET = 10'h 58; |
| parameter logic [BlockAw-1:0] RV_PLIC_PRIO19_OFFSET = 10'h 5c; |
| parameter logic [BlockAw-1:0] RV_PLIC_PRIO20_OFFSET = 10'h 60; |
| parameter logic [BlockAw-1:0] RV_PLIC_PRIO21_OFFSET = 10'h 64; |
| parameter logic [BlockAw-1:0] RV_PLIC_PRIO22_OFFSET = 10'h 68; |
| parameter logic [BlockAw-1:0] RV_PLIC_PRIO23_OFFSET = 10'h 6c; |
| parameter logic [BlockAw-1:0] RV_PLIC_PRIO24_OFFSET = 10'h 70; |
| parameter logic [BlockAw-1:0] RV_PLIC_PRIO25_OFFSET = 10'h 74; |
| parameter logic [BlockAw-1:0] RV_PLIC_PRIO26_OFFSET = 10'h 78; |
| parameter logic [BlockAw-1:0] RV_PLIC_PRIO27_OFFSET = 10'h 7c; |
| parameter logic [BlockAw-1:0] RV_PLIC_PRIO28_OFFSET = 10'h 80; |
| parameter logic [BlockAw-1:0] RV_PLIC_PRIO29_OFFSET = 10'h 84; |
| parameter logic [BlockAw-1:0] RV_PLIC_PRIO30_OFFSET = 10'h 88; |
| parameter logic [BlockAw-1:0] RV_PLIC_PRIO31_OFFSET = 10'h 8c; |
| parameter logic [BlockAw-1:0] RV_PLIC_PRIO32_OFFSET = 10'h 90; |
| parameter logic [BlockAw-1:0] RV_PLIC_PRIO33_OFFSET = 10'h 94; |
| parameter logic [BlockAw-1:0] RV_PLIC_PRIO34_OFFSET = 10'h 98; |
| parameter logic [BlockAw-1:0] RV_PLIC_PRIO35_OFFSET = 10'h 9c; |
| parameter logic [BlockAw-1:0] RV_PLIC_PRIO36_OFFSET = 10'h a0; |
| parameter logic [BlockAw-1:0] RV_PLIC_PRIO37_OFFSET = 10'h a4; |
| parameter logic [BlockAw-1:0] RV_PLIC_PRIO38_OFFSET = 10'h a8; |
| parameter logic [BlockAw-1:0] RV_PLIC_PRIO39_OFFSET = 10'h ac; |
| parameter logic [BlockAw-1:0] RV_PLIC_PRIO40_OFFSET = 10'h b0; |
| parameter logic [BlockAw-1:0] RV_PLIC_PRIO41_OFFSET = 10'h b4; |
| parameter logic [BlockAw-1:0] RV_PLIC_PRIO42_OFFSET = 10'h b8; |
| parameter logic [BlockAw-1:0] RV_PLIC_PRIO43_OFFSET = 10'h bc; |
| parameter logic [BlockAw-1:0] RV_PLIC_IE0_0_OFFSET = 10'h c0; |
| parameter logic [BlockAw-1:0] RV_PLIC_IE0_1_OFFSET = 10'h c4; |
| parameter logic [BlockAw-1:0] RV_PLIC_THRESHOLD0_OFFSET = 10'h c8; |
| parameter logic [BlockAw-1:0] RV_PLIC_CC0_OFFSET = 10'h cc; |
| parameter logic [BlockAw-1:0] RV_PLIC_MSIP0_OFFSET = 10'h d0; |
| |
| |
| // Register Index |
| typedef enum int { |
| RV_PLIC_IP_0, |
| RV_PLIC_IP_1, |
| RV_PLIC_LE_0, |
| RV_PLIC_LE_1, |
| RV_PLIC_PRIO0, |
| RV_PLIC_PRIO1, |
| RV_PLIC_PRIO2, |
| RV_PLIC_PRIO3, |
| RV_PLIC_PRIO4, |
| RV_PLIC_PRIO5, |
| RV_PLIC_PRIO6, |
| RV_PLIC_PRIO7, |
| RV_PLIC_PRIO8, |
| RV_PLIC_PRIO9, |
| RV_PLIC_PRIO10, |
| RV_PLIC_PRIO11, |
| RV_PLIC_PRIO12, |
| RV_PLIC_PRIO13, |
| RV_PLIC_PRIO14, |
| RV_PLIC_PRIO15, |
| RV_PLIC_PRIO16, |
| RV_PLIC_PRIO17, |
| RV_PLIC_PRIO18, |
| RV_PLIC_PRIO19, |
| RV_PLIC_PRIO20, |
| RV_PLIC_PRIO21, |
| RV_PLIC_PRIO22, |
| RV_PLIC_PRIO23, |
| RV_PLIC_PRIO24, |
| RV_PLIC_PRIO25, |
| RV_PLIC_PRIO26, |
| RV_PLIC_PRIO27, |
| RV_PLIC_PRIO28, |
| RV_PLIC_PRIO29, |
| RV_PLIC_PRIO30, |
| RV_PLIC_PRIO31, |
| RV_PLIC_PRIO32, |
| RV_PLIC_PRIO33, |
| RV_PLIC_PRIO34, |
| RV_PLIC_PRIO35, |
| RV_PLIC_PRIO36, |
| RV_PLIC_PRIO37, |
| RV_PLIC_PRIO38, |
| RV_PLIC_PRIO39, |
| RV_PLIC_PRIO40, |
| RV_PLIC_PRIO41, |
| RV_PLIC_PRIO42, |
| RV_PLIC_PRIO43, |
| RV_PLIC_IE0_0, |
| RV_PLIC_IE0_1, |
| RV_PLIC_THRESHOLD0, |
| RV_PLIC_CC0, |
| RV_PLIC_MSIP0 |
| } rv_plic_id_e; |
| |
| // Register width information to check illegal writes |
| parameter logic [3:0] RV_PLIC_PERMIT [53] = '{ |
| 4'b 1111, // index[ 0] RV_PLIC_IP_0 |
| 4'b 1111, // index[ 1] RV_PLIC_IP_1 |
| 4'b 1111, // index[ 6] RV_PLIC_LE_0 |
| 4'b 1111, // index[ 7] RV_PLIC_LE_1 |
| 4'b 0001, // index[ 12] RV_PLIC_PRIO0 |
| 4'b 0001, // index[ 13] RV_PLIC_PRIO1 |
| 4'b 0001, // index[ 14] RV_PLIC_PRIO2 |
| 4'b 0001, // index[ 15] RV_PLIC_PRIO3 |
| 4'b 0001, // index[ 16] RV_PLIC_PRIO4 |
| 4'b 0001, // index[ 17] RV_PLIC_PRIO5 |
| 4'b 0001, // index[ 18] RV_PLIC_PRIO6 |
| 4'b 0001, // index[ 19] RV_PLIC_PRIO7 |
| 4'b 0001, // index[ 20] RV_PLIC_PRIO8 |
| 4'b 0001, // index[ 21] RV_PLIC_PRIO9 |
| 4'b 0001, // index[ 22] RV_PLIC_PRIO10 |
| 4'b 0001, // index[ 23] RV_PLIC_PRIO11 |
| 4'b 0001, // index[ 24] RV_PLIC_PRIO12 |
| 4'b 0001, // index[ 25] RV_PLIC_PRIO13 |
| 4'b 0001, // index[ 26] RV_PLIC_PRIO14 |
| 4'b 0001, // index[ 27] RV_PLIC_PRIO15 |
| 4'b 0001, // index[ 28] RV_PLIC_PRIO16 |
| 4'b 0001, // index[ 29] RV_PLIC_PRIO17 |
| 4'b 0001, // index[ 30] RV_PLIC_PRIO18 |
| 4'b 0001, // index[ 31] RV_PLIC_PRIO19 |
| 4'b 0001, // index[ 32] RV_PLIC_PRIO20 |
| 4'b 0001, // index[ 33] RV_PLIC_PRIO21 |
| 4'b 0001, // index[ 34] RV_PLIC_PRIO22 |
| 4'b 0001, // index[ 35] RV_PLIC_PRIO23 |
| 4'b 0001, // index[ 36] RV_PLIC_PRIO24 |
| 4'b 0001, // index[ 37] RV_PLIC_PRIO25 |
| 4'b 0001, // index[ 38] RV_PLIC_PRIO26 |
| 4'b 0001, // index[ 39] RV_PLIC_PRIO27 |
| 4'b 0001, // index[ 40] RV_PLIC_PRIO28 |
| 4'b 0001, // index[ 41] RV_PLIC_PRIO29 |
| 4'b 0001, // index[ 42] RV_PLIC_PRIO30 |
| 4'b 0001, // index[ 43] RV_PLIC_PRIO31 |
| 4'b 0001, // index[ 44] RV_PLIC_PRIO32 |
| 4'b 0001, // index[ 45] RV_PLIC_PRIO33 |
| 4'b 0001, // index[ 46] RV_PLIC_PRIO34 |
| 4'b 0001, // index[ 47] RV_PLIC_PRIO35 |
| 4'b 0001, // index[ 48] RV_PLIC_PRIO36 |
| 4'b 0001, // index[ 49] RV_PLIC_PRIO37 |
| 4'b 0001, // index[ 50] RV_PLIC_PRIO38 |
| 4'b 0001, // index[ 51] RV_PLIC_PRIO39 |
| 4'b 0001, // index[ 52] RV_PLIC_PRIO40 |
| 4'b 0001, // index[ 53] RV_PLIC_PRIO41 |
| 4'b 0001, // index[ 54] RV_PLIC_PRIO42 |
| 4'b 0001, // index[ 55] RV_PLIC_PRIO43 |
| 4'b 1111, // index[184] RV_PLIC_IE0_0 |
| 4'b 1111, // index[185] RV_PLIC_IE0_1 |
| 4'b 0001, // index[190] RV_PLIC_THRESHOLD0 |
| 4'b 0001, // index[191] RV_PLIC_CC0 |
| 4'b 0001 // index[192] RV_PLIC_MSIP0 |
| }; |
| endpackage |
| |