commit: ede0f7e2f5c3b61f49e534762a5ef41d414c7e6d
[log] [tgz]
author: nguyendao-uom <nguyen.dao@manchester.ac.uk>
Wed Nov 17 17:41:57 2021 +0000
committer: nguyendao-uom <nguyen.dao@manchester.ac.uk>
Wed Nov 17 17:41:57 2021 +0000
tree: 387763699d4e4c5e814f63cf3273771c6d2f88ae
parent: c5da9e9885e361d05dee2aa6303a69fc26423c8e [diff]

eFPGA ver3

gds/eFPGA_top.gds[Added - diff]
lef/eFPGA_top.lef[Added - diff]
openlane/user_project_wrapper/config.tcl[diff]
openlane/user_project_wrapper/macro.cfg[diff]
openlane/user_project_wrapper/pin_order.cfg[diff]
verilog/rtl/eFPGA_top.v[Added - diff]
verilog/rtl/user_project_wrapper.v[diff]

7 files changed

tree: 387763699d4e4c5e814f63cf3273771c6d2f88ae

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.