| commit | 7cacabbebff0acaf7504995dcf1fd7a0fb090e9d | [log] [tgz] |
|---|---|---|
| author | nguyendao-uom <nguyen.dao@manchester.ac.uk> | Thu Dec 02 14:06:53 2021 +0000 |
| committer | nguyendao-uom <nguyen.dao@manchester.ac.uk> | Thu Dec 02 14:06:53 2021 +0000 |
| tree | ea6a3e55ca8066cde7e33fbf5af5a3bb2758cd54 | |
| parent | ede0f7e2f5c3b61f49e534762a5ef41d414c7e6d [diff] |
add gds pic
Demonstration of the Fabulous FPGA design flow using the Skywater 130 process.
This repo experiments an implementation of an FPGA from RTL to GDS with open Skywater-130 PDK. The design RTL was generated by FABulous framework. The fabric consists of 896 LUT4s (16x7 CLBs), 64 LUT5s (16x1 RegFiles), 8 DSPs and 8 BRAMs (8x1KB) with dual-ported memory blocks for register files and FIFOs. An embedded UART for configurations and CPU_IO interface (e.g. to RISC-V core) were also implemented in this version.
Refer to README for this sample project documentation.
