add gds pic
diff --git a/README.md b/README.md index 3706438..7aee96d 100644 --- a/README.md +++ b/README.md
@@ -2,10 +2,14 @@ [](https://opensource.org/licenses/Apache-2.0) [](https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml) [](https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml) -| :exclamation: Important Note | -|-----------------------------------------| +Demonstration of the Fabulous FPGA design flow using the Skywater 130 process. -## Please fill in your project documentation in this README.md file +This repo experiments an implementation of an FPGA from RTL to GDS with open Skywater-130 PDK. The design RTL was generated by FABulous framework. The fabric consists of 896 LUT4s (16x7 CLBs), 64 LUT5s (16x1 RegFiles), 8 DSPs and 8 BRAMs (8x1KB) with dual-ported memory blocks for register files and FIFOs. An embedded UART for configurations and CPU_IO interface (e.g. to RISC-V core) were also implemented in this version. + + <p align="center"> + <img src="./docs/source/eFPGA_ver3.png" width="50%" height="50%"> + </p> + Refer to [README](docs/source/index.rst) for this sample project documentation.
diff --git a/docs/source/eFPGA_ver3.png b/docs/source/eFPGA_ver3.png new file mode 100644 index 0000000..0889c1b --- /dev/null +++ b/docs/source/eFPGA_ver3.png Binary files differ
